Merge branch 'master' of git://git.denx.de/u-boot-mmc
authorTom Rini <trini@ti.com>
Mon, 17 Feb 2014 19:16:08 +0000 (14:16 -0500)
committerTom Rini <trini@ti.com>
Mon, 17 Feb 2014 19:16:08 +0000 (14:16 -0500)
76 files changed:
MAKEALL
arch/arc/config.mk [new file with mode: 0644]
arch/arc/cpu/arc700/Makefile [new file with mode: 0644]
arch/arc/cpu/arc700/cache.c [new file with mode: 0644]
arch/arc/cpu/arc700/config.mk [new file with mode: 0644]
arch/arc/cpu/arc700/cpu.c [new file with mode: 0644]
arch/arc/cpu/arc700/interrupts.c [new file with mode: 0644]
arch/arc/cpu/arc700/reset.c [new file with mode: 0644]
arch/arc/cpu/arc700/start.S [new file with mode: 0644]
arch/arc/cpu/arc700/timer.c [new file with mode: 0644]
arch/arc/cpu/arc700/u-boot.lds [new file with mode: 0644]
arch/arc/include/asm/arch-arc700/hardware.h [new file with mode: 0644]
arch/arc/include/asm/arcregs.h [new file with mode: 0644]
arch/arc/include/asm/bitops.h [new file with mode: 0644]
arch/arc/include/asm/byteorder.h [new file with mode: 0644]
arch/arc/include/asm/cache.h [new file with mode: 0644]
arch/arc/include/asm/config.h [new file with mode: 0644]
arch/arc/include/asm/errno.h [new file with mode: 0644]
arch/arc/include/asm/global_data.h [new file with mode: 0644]
arch/arc/include/asm/io.h [new file with mode: 0644]
arch/arc/include/asm/posix_types.h [new file with mode: 0644]
arch/arc/include/asm/ptrace.h [new file with mode: 0644]
arch/arc/include/asm/sections.h [new file with mode: 0644]
arch/arc/include/asm/string.h [new file with mode: 0644]
arch/arc/include/asm/types.h [new file with mode: 0644]
arch/arc/include/asm/u-boot-arc.h [new file with mode: 0644]
arch/arc/include/asm/u-boot.h [new file with mode: 0644]
arch/arc/include/asm/unaligned.h [new file with mode: 0644]
arch/arc/lib/Makefile [new file with mode: 0644]
arch/arc/lib/bootm.c [new file with mode: 0644]
arch/arc/lib/memcmp.S [new file with mode: 0644]
arch/arc/lib/memcpy-700.S [new file with mode: 0644]
arch/arc/lib/memset.S [new file with mode: 0644]
arch/arc/lib/relocate.c [new file with mode: 0644]
arch/arc/lib/sections.c [new file with mode: 0644]
arch/arc/lib/strchr-700.S [new file with mode: 0644]
arch/arc/lib/strcmp.S [new file with mode: 0644]
arch/arc/lib/strcpy-700.S [new file with mode: 0644]
arch/arc/lib/strlen.S [new file with mode: 0644]
arch/blackfin/cpu/initcode.h
arch/blackfin/cpu/start.S
arch/blackfin/include/asm/mach-common/bits/emac.h
arch/blackfin/lib/board.c
board/bf609-ezkit/bf609-ezkit.c
board/spear/spear300/spear300.c
board/spear/spear310/spear310.c
board/spear/spear320/spear320.c
board/spear/spear600/spear600.c
board/spear/x600/x600.c
board/synopsys/arcangel4/Makefile [new file with mode: 0644]
board/synopsys/axs101/Makefile [new file with mode: 0644]
board/synopsys/axs101/axs101.c [new file with mode: 0644]
board/synopsys/axs101/nand.c [new file with mode: 0644]
boards.cfg
common/cmd_bdinfo.c
common/image.c
doc/README.ARC [new file with mode: 0644]
doc/README.designware_eth [deleted file]
drivers/net/bfin_mac.c
drivers/net/designware.c
drivers/net/designware.h
drivers/serial/Makefile
drivers/serial/serial.c
drivers/serial/serial_arc.c [new file with mode: 0644]
examples/standalone/stubs.c
include/common.h
include/configs/arcangel4-be.h [new file with mode: 0644]
include/configs/arcangel4.h [new file with mode: 0644]
include/configs/axs101.h [new file with mode: 0644]
include/configs/bf609-ezkit.h
include/configs/spear-common.h
include/configs/spear6xx_evb.h
include/configs/x600.h
include/image.h
include/netdev.h
net/eth.c

diff --git a/MAKEALL b/MAKEALL
index 562071a..54b0d89 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -529,6 +529,12 @@ LIST_sparc="$(targets_by_arch sparc)"
 
 LIST_nds32="$(targets_by_arch nds32)"
 
+#########################################################################
+## ARC Systems
+#########################################################################
+
+LIST_arc="$(targets_by_arch arc)"
+
 #-----------------------------------------------------------------------
 
 get_target_location() {
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
new file mode 100644 (file)
index 0000000..76f4f7c
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifndef CONFIG_SYS_BIG_ENDIAN
+CONFIG_SYS_LITTLE_ENDIAN = 1
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+CROSS_COMPILE ?= arc-buildroot-linux-uclibc-
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+CROSS_COMPILE ?= arceb-buildroot-linux-uclibc-
+PLATFORM_LDFLAGS += -EB
+endif
+
+PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+# Needed for relocation
+LDFLAGS_FINAL += -pie
+
+# Load address for standalone apps
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
+
+# Support generic board on ARC
+__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile
new file mode 100644 (file)
index 0000000..cdc5002
--- /dev/null
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+extra-y        += start.o
+
+obj-y  += cache.o
+obj-y  += cpu.o
+obj-y  += interrupts.o
+obj-y  += reset.o
+obj-y  += timer.o
diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c
new file mode 100644 (file)
index 0000000..39d522d
--- /dev/null
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arcregs.h>
+
+/* Bit values in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE  (1 << 0)
+
+/* Bit values in DC_CTRL */
+#define DC_CTRL_CACHE_DISABLE  (1 << 0)
+#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
+#define DC_CTRL_FLUSH_STATUS   (1 << 8)
+
+int icache_status(void)
+{
+       return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
+              IC_CTRL_CACHE_DISABLE;
+}
+
+void icache_enable(void)
+{
+       write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+                     ~IC_CTRL_CACHE_DISABLE);
+}
+
+void icache_disable(void)
+{
+       write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+                     IC_CTRL_CACHE_DISABLE);
+}
+
+void invalidate_icache_all(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       /* Any write to IC_IVIC register triggers invalidation of entire I$ */
+       write_aux_reg(ARC_AUX_IC_IVIC, 1);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+
+int dcache_status(void)
+{
+       return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
+               DC_CTRL_CACHE_DISABLE;
+}
+
+void dcache_enable(void)
+{
+       write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
+                     ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
+}
+
+void dcache_disable(void)
+{
+       write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
+                     DC_CTRL_CACHE_DISABLE);
+}
+
+void flush_dcache_all(void)
+{
+       /* Do flush of entire cache */
+       write_aux_reg(ARC_AUX_DC_FLSH, 1);
+
+       /* Wait flush end */
+       while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+               ;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+static void dcache_flush_line(unsigned addr)
+{
+#if (CONFIG_ARC_MMU_VER > 2)
+       write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+       write_aux_reg(ARC_AUX_DC_FLDL, addr);
+
+       /* Wait flush end */
+       while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+               ;
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+       /*
+        * Invalidate I$ for addresses range just flushed from D$.
+        * If we try to execute data flushed above it will be valid/correct
+        */
+#if (CONFIG_ARC_MMU_VER > 2)
+       write_aux_reg(ARC_AUX_IC_PTAG, addr);
+#endif
+       write_aux_reg(ARC_AUX_IC_IVIL, addr);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+       unsigned int addr;
+
+       start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+       end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+       for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
+               dcache_flush_line(addr);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+       unsigned int addr;
+
+       start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+       end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+       for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+#if (CONFIG_ARC_MMU_VER > 2)
+               write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+               write_aux_reg(ARC_AUX_DC_IVDL, addr);
+       }
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_all(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+       /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
+       write_aux_reg(ARC_AUX_DC_IVDC, 1);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+       flush_dcache_range(start, start + size);
+}
diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arc700/config.mk
new file mode 100644 (file)
index 0000000..3206ff4
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mA7
diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/cpu/arc700/cpu.c
new file mode 100644 (file)
index 0000000..50634b8
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SYS_ICACHE_OFF
+       icache_disable();
+#else
+       icache_enable();
+       invalidate_icache_all();
+#endif
+
+       flush_dcache_all();
+#ifdef CONFIG_SYS_DCACHE_OFF
+       dcache_disable();
+#else
+       dcache_enable();
+#endif
+       timer_init();
+
+/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
+       if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
+               gd->arch.running_on_hw = 0;
+       else
+               gd->arch.running_on_hw = 1;
+
+       gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+int arch_early_init_r(void)
+{
+       gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+       return 0;
+}
diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c
new file mode 100644 (file)
index 0000000..d93a6eb
--- /dev/null
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/ptrace.h>
+
+/* Bit values in STATUS32 */
+#define E1_MASK                (1 << 1)        /* Level 1 interrupts enable */
+#define E2_MASK                (1 << 2)        /* Level 2 interrupts enable */
+
+int interrupt_init(void)
+{
+       return 0;
+}
+
+/*
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+       int status = read_aux_reg(ARC_AUX_STATUS32);
+       int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
+
+       status &= ~(E1_MASK | E2_MASK);
+       /* STATUS32 register is updated indirectly with "FLAG" instruction */
+       __asm__("flag %0" : : "r" (status));
+       return state;
+}
+
+void enable_interrupts(void)
+{
+       unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
+
+       status |= E1_MASK | E2_MASK;
+       /* STATUS32 register is updated indirectly with "FLAG" instruction */
+       __asm__("flag %0" : : "r" (status));
+}
+
+static void print_reg_file(long *reg_rev, int start_num)
+{
+       unsigned int i;
+
+       /* Print 3 registers per line */
+       for (i = start_num; i < start_num + 25; i++) {
+               printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
+               if (((i + 1) % 3) == 0)
+                       printf("\n");
+
+               /* Because pt_regs has registers reversed */
+               reg_rev--;
+       }
+
+       /* Add new-line if none was inserted in the end of loop above */
+       if (((i + 1) % 3) != 0)
+               printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+       printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
+              regs->ret, regs->blink, regs->status32);
+       printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
+       printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
+              regs->sp, regs->fp);
+       printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
+              regs->lp_end, regs->lp_count);
+
+       print_reg_file(&(regs->r0), 0);
+}
+
+void bad_mode(struct pt_regs *regs)
+{
+       if (regs)
+               show_regs(regs);
+
+       panic("Resetting CPU ...\n");
+}
+
+void do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+       printf("Memory error exception @ 0x%lx\n", address);
+       bad_mode(regs);
+}
+
+void do_instruction_error(unsigned long address, struct pt_regs *regs)
+{
+       printf("Instruction error exception @ 0x%lx\n", address);
+       bad_mode(regs);
+}
+
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
+{
+       printf("Machine check exception @ 0x%lx\n", address);
+       bad_mode(regs);
+}
+
+void do_interrupt_handler(void)
+{
+       printf("Interrupt fired\n");
+       bad_mode(0);
+}
+
+void do_itlb_miss(struct pt_regs *regs)
+{
+       printf("I TLB miss exception\n");
+       bad_mode(regs);
+}
+
+void do_dtlb_miss(struct pt_regs *regs)
+{
+       printf("D TLB miss exception\n");
+       bad_mode(regs);
+}
+
+void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
+{
+       printf("TLB protection violation or misaligned access @ 0x%lx\n",
+              address);
+       bad_mode(regs);
+}
+
+void do_privilege_violation(struct pt_regs *regs)
+{
+       printf("Privilege violation exception\n");
+       bad_mode(regs);
+}
+
+void do_trap(struct pt_regs *regs)
+{
+       printf("Trap exception\n");
+       bad_mode(regs);
+}
+
+void do_extension(struct pt_regs *regs)
+{
+       printf("Extension instruction exception\n");
+       bad_mode(regs);
+}
diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/cpu/arc700/reset.c
new file mode 100644 (file)
index 0000000..98ebf1d
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <command.h>
+#include <common.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       printf("Put your restart handler here\n");
+
+#ifdef DEBUG
+       /* Stop debug session here */
+       __asm__("brk");
+#endif
+       return 0;
+}
diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S
new file mode 100644 (file)
index 0000000..563513b
--- /dev/null
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+       st.a    \reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+       lr      %r9, [\aux]
+       PUSH    %r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+       PUSH    %r1
+       PUSH    %r2
+       PUSH    %r3
+       PUSH    %r4
+       PUSH    %r5
+       PUSH    %r6
+       PUSH    %r7
+       PUSH    %r8
+       PUSH    %r9
+       PUSH    %r10
+       PUSH    %r11
+       PUSH    %r12
+       PUSH    %r13
+       PUSH    %r14
+       PUSH    %r15
+       PUSH    %r16
+       PUSH    %r17
+       PUSH    %r18
+       PUSH    %r19
+       PUSH    %r20
+       PUSH    %r21
+       PUSH    %r22
+       PUSH    %r23
+       PUSH    %r24
+.endm
+
+.macro SAVE_ALL_SYS
+
+       st      %r0, [%sp]
+       lr      %r0, [%ecr]
+       st      %r0, [%sp, 8]   /* ECR */
+       st      %sp, [%sp, 4]
+
+       SAVE_R1_TO_R24
+       PUSH    %r25
+       PUSH    %gp
+       PUSH    %fp
+       PUSH    %blink
+       PUSHAX  %eret
+       PUSHAX  %erstatus
+       PUSH    %lp_count
+       PUSHAX  %lp_end
+       PUSHAX  %lp_start
+       PUSHAX  %erbta
+.endm
+
+.align 4
+.globl _start
+_start:
+       /* Critical system events */
+       j       reset                   /* 0 - 0x000 */
+       j       memory_error            /* 1 - 0x008 */
+       j       instruction_error       /* 2 - 0x010 */
+
+       /* Device interrupts */
+.rept  29
+       j       interrupt_handler       /* 3:31 - 0x018:0xF8 */
+.endr
+       /* Exceptions */
+       j       EV_MachineCheck         /* 0x100, Fatal Machine check  (0x20) */
+       j       EV_TLBMissI             /* 0x108, Intruction TLB miss  (0x21) */
+       j       EV_TLBMissD             /* 0x110, Data TLB miss        (0x22) */
+       j       EV_TLBProtV             /* 0x118, Protection Violation (0x23)
+                                                       or Misaligned Access  */
+       j       EV_PrivilegeV           /* 0x120, Privilege Violation  (0x24) */
+       j       EV_Trap                 /* 0x128, Trap exception       (0x25) */
+       j       EV_Extension            /* 0x130, Extn Intruction Excp (0x26) */
+
+memory_error:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_memory_error
+
+instruction_error:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_instruction_error
+
+interrupt_handler:
+       /* Todo - save and restore CPU context when interrupts will be in use */
+       bl      do_interrupt_handler
+       rtie
+
+EV_MachineCheck:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_machine_check_fault
+
+EV_TLBMissI:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_itlb_miss
+
+EV_TLBMissD:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_dtlb_miss
+
+EV_TLBProtV:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_tlb_prot_violation
+
+EV_PrivilegeV:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_privilege_violation
+
+EV_Trap:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_trap
+
+EV_Extension:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_extension
+
+
+reset:
+       /* Setup interrupt vector base that matches "__text_start" */
+       sr      __text_start, [ARC_AUX_INTR_VEC_BASE]
+
+       /* Setup stack pointer */
+       mov     %sp, CONFIG_SYS_INIT_SP_ADDR
+       mov     %fp, %sp
+
+       /* Clear bss */
+       mov     %r0, __bss_start
+       mov     %r1, __bss_end
+
+clear_bss:
+       st.ab   0, [%r0, 4]
+       brlt    %r0, %r1, clear_bss
+
+       /* Zero the one and only argument of "board_init_f" */
+       mov_s   %r0, 0
+       j       board_init_f
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl relocate_code
+relocate_code:
+       /*
+        * r0-r12 might be clobbered by C functions
+        * so we use r13-r16 for storage here
+        */
+       mov     %r13, %r0               /* save addr_sp */
+       mov     %r14, %r1               /* save addr of gd */
+       mov     %r15, %r2               /* save addr of destination */
+
+       mov     %r16, %r2               /* %r9 - relocation offset */
+       sub     %r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+       mov     %sp, %r13
+       mov     %fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+       mov     %r0, __image_copy_start
+       cmp     %r0, %r15               /* skip relocation if code loaded */
+       bz      do_board_init_r         /* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+       mov     %r1, %r15
+       mov     %r2, __image_copy_end
+       sub     %r2, %r2, %r0           /* r3 <- amount of bytes to copy */
+       asr     %r2, %r2, 2             /* r3 <- amount of words to copy */
+       mov     %lp_count, %r2
+       lp      copy_end
+       ld.ab   %r2,[%r0,4]
+       st.ab   %r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+       bl      do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+       bl      invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       bl      flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+       lr      %r0, [ARC_AUX_INTR_VEC_BASE]    /* Read current position */
+       add     %r0, %r0, %r16                  /* Update address */
+       sr      %r0, [ARC_AUX_INTR_VEC_BASE]    /* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+       mov     %r2, board_init_r       /* old address of "board_init_r()" */
+       add     %r2, %r2, %r16          /* new address of "board_init_r()" */
+       mov     %r0, %r14               /* 1-st parameter: gd_t */
+       mov     %r1, %r15               /* 2-nd parameter: dest_addr */
+       j       [%r2]
diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/cpu/arc700/timer.c
new file mode 100644 (file)
index 0000000..a0acbbc
--- /dev/null
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arcregs.h>
+
+#define NH_MODE        (1 << 1)        /* Disable timer if CPU is halted */
+
+int timer_init(void)
+{
+       write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+       /* Set max value for counter/timer */
+       write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+       /* Set initial count value and restart counter/timer */
+       write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+       return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+       return read_aux_reg(ARC_AUX_TIMER0_CNT);
+}
diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds
new file mode 100644 (file)
index 0000000..2d01b21
--- /dev/null
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+       . = ALIGN(4);
+       .text : {
+               *(.__text_start)
+               *(.__image_copy_start)
+               CPUDIR/start.o (.text*)
+               *(.text*)
+       }
+
+       . = ALIGN(4);
+       .text_end :
+       {
+               *(.__text_end)
+       }
+
+       . = ALIGN(4);
+       .rodata : {
+               *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+       }
+
+       . = ALIGN(4);
+       .data : {
+               *(.data*)
+       }
+
+       . = ALIGN(4);
+       .u_boot_list : {
+               KEEP(*(SORT(.u_boot_list*)));
+       }
+
+       . = ALIGN(4);
+       .rel_dyn_start : {
+               *(.__rel_dyn_start)
+       }
+
+       .rela.dyn : {
+               *(.rela.dyn)
+       }
+
+       .rel_dyn_end : {
+               *(.__rel_dyn_end)
+       }
+
+       . = ALIGN(4);
+       .bss_start : {
+               *(.__bss_start);
+       }
+
+       .bss : {
+               *(.bss*)
+       }
+
+       .bss_end : {
+               *(.__bss_end);
+       }
+
+       . = ALIGN(4);
+       .image_copy_end : {
+               *(.__image_copy_end)
+               *(.__init_end)
+       }
+}
diff --git a/arch/arc/include/asm/arch-arc700/hardware.h b/arch/arc/include/asm/arch-arc700/hardware.h
new file mode 100644 (file)
index 0000000..8ec13a8
--- /dev/null
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * This file is only required to allow compilation of "designware_i2c" driver.
+ * Which explicitly includes <asm/arch/hardware.h>.
+ */
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
new file mode 100644 (file)
index 0000000..5d48d11
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_ARCREGS_H
+#define _ASM_ARC_ARCREGS_H
+
+/*
+ * ARC architecture has additional address space - auxiliary registers.
+ * These registers are mostly used for configuration purposes.
+ * These registers are not memory mapped and special commands are used for
+ * access: "lr"/"sr".
+ */
+
+#define ARC_AUX_IDENTITY       0x04
+#define ARC_AUX_STATUS32       0x0a
+
+/* Instruction cache related auxiliary registers */
+#define ARC_AUX_IC_IVIC                0x10
+#define ARC_AUX_IC_CTRL                0x11
+#define ARC_AUX_IC_IVIL                0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_IC_PTAG                0x1E
+#endif
+
+/* Timer related auxiliary registers */
+#define ARC_AUX_TIMER0_CNT     0x21    /* Timer 0 count */
+#define ARC_AUX_TIMER0_CTRL    0x22    /* Timer 0 control */
+#define ARC_AUX_TIMER0_LIMIT   0x23    /* Timer 0 limit */
+
+#define ARC_AUX_INTR_VEC_BASE  0x25
+
+/* Data cache related auxiliary registers */
+#define ARC_AUX_DC_IVDC                0x47
+#define ARC_AUX_DC_CTRL                0x48
+
+#define ARC_AUX_DC_IVDL                0x4A
+#define ARC_AUX_DC_FLSH                0x4B
+#define ARC_AUX_DC_FLDL                0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_DC_PTAG                0x5C
+#endif
+
+#ifndef __ASSEMBLY__
+/* Accessors for auxiliary registers */
+#define read_aux_reg(reg)      __builtin_arc_lr(reg)
+
+/* gcc builtin sr needs reg param to be long immediate */
+#define write_aux_reg(reg_immed, val)          \
+               __builtin_arc_sr((unsigned int)val, reg_immed)
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARC_ARCREGS_H */
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
new file mode 100644 (file)
index 0000000..85721aa
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BITOPS_H
+#define __ASM_ARC_BITOPS_H
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __ASM_ARC_BITOPS_H */
diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h
new file mode 100644 (file)
index 0000000..2fa9776
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BYTEORDER_H
+#define __ASM_ARC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+       #define __BYTEORDER_HAS_U64__
+       #define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+       #include <linux/byteorder/little_endian.h>
+#else
+       #include <linux/byteorder/big_endian.h>
+#endif /* CONFIG_SYS_BIG_ENDIAN */
+
+#endif /* ASM_ARC_BYTEORDER_H */
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
new file mode 100644 (file)
index 0000000..16e7568
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CACHE_H
+#define __ASM_ARC_CACHE_H
+
+#include <config.h>
+
+/*
+ * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN      128
+#endif
+
+#endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h
new file mode 100644 (file)
index 0000000..5761def
--- /dev/null
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CONFIG_H_
+#define __ASM_ARC_CONFIG_H_
+
+#define CONFIG_LMB
+
+#endif /*__ASM_ARC_CONFIG_H_ */
diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h
new file mode 100644 (file)
index 0000000..4c82b50
--- /dev/null
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
new file mode 100644 (file)
index 0000000..d644e80
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef        __ASM_ARC_GLOBAL_DATA_H
+#define __ASM_ARC_GLOBAL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+       int running_on_hw;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR                register volatile gd_t *gd asm ("r25")
+
+#endif /* __ASM_ARC_GLOBAL_DATA_H */
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
new file mode 100644 (file)
index 0000000..24b7337
--- /dev/null
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_IO_H
+#define __ASM_ARC_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+       /* Not yet implemented */
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+       u8 b;
+
+       __asm__ __volatile__("ldb%U1    %0, %1\n"
+                            : "=r" (b)
+                            : "m" (*(volatile u8 __force *)addr)
+                            : "memory");
+       return b;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+       u16 s;
+
+       __asm__ __volatile__("ldw%U1    %0, %1\n"
+                            : "=r" (s)
+                            : "m" (*(volatile u16 __force *)addr)
+                            : "memory");
+       return s;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+       u32 w;
+
+       __asm__ __volatile__("ld%U1     %0, %1\n"
+                            : "=r" (w)
+                            : "m" (*(volatile u32 __force *)addr)
+                            : "memory");
+       return w;
+}
+
+#define readb __raw_readb
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+       return __le16_to_cpu(__raw_readw(addr));
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+       return __le32_to_cpu(__raw_readl(addr));
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+       __asm__ __volatile__("stb%U1    %0, %1\n"
+                            :
+                            : "r" (b), "m" (*(volatile u8 __force *)addr)
+                            : "memory");
+}
+
+static inline void __raw_writew(u16 s, volatile void __iomem *addr)
+{
+       __asm__ __volatile__("stw%U1    %0, %1\n"
+                            :
+                            : "r" (s), "m" (*(volatile u16 __force *)addr)
+                            : "memory");
+}
+
+static inline void __raw_writel(u32 w, volatile void __iomem *addr)
+{
+       __asm__ __volatile__("st%U1     %0, %1\n"
+                            :
+                            : "r" (w), "m" (*(volatile u32 __force *)addr)
+                            : "memory");
+}
+
+#define writeb __raw_writeb
+#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
+#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
+
+static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+       __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "stb.ab   r8, [r1, 1]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (bytelen)
+                             : "r8");
+       return bytelen;
+}
+
+static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+       __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "stw.ab   r8, [r1, 2]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (wordlen)
+                             : "r8");
+       return wordlen;
+}
+
+static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+       __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.ab    r8, [r1, 4]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (longlen)
+                             : "r8");
+       return longlen;
+}
+
+static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
+{
+       __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.di    r8, [r0, 0]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (bytelen)
+                             : "r8");
+       return bytelen;
+}
+
+static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
+{
+       __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.ab.di r8, [r0, 0]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (wordlen)
+                             : "r8");
+       return wordlen;
+}
+
+static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
+{
+       __asm__ __volatile__ ("1:ld.ab  r8, [r1, 4]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.ab.di r8, [r0, 0]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (longlen)
+                             : "r8");
+       return longlen;
+}
+
+#define out_arch(type, endian, a, v)   __raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)       endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v) out_arch(l, le32, a, v)
+#define out_le16(a, v) out_arch(w, le16, a, v)
+
+#define in_le32(a)     in_arch(l, le32, a)
+#define in_le16(a)     in_arch(w, le16, a)
+
+#define out_be32(a, v) out_arch(l, be32, a, v)
+#define out_be16(a, v) out_arch(w, be16, a, v)
+
+#define in_be32(a)     in_arch(l, be32, a)
+#define in_be16(a)     in_arch(w, be16, a)
+
+#define out_8(a, v)    __raw_writeb(v, a)
+#define in_8(a)                __raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+       out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+       out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+       out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#endif /* __ASM_ARC_IO_H */
diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h
new file mode 100644 (file)
index 0000000..20415f0
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_POSIX_TYPES_H
+#define __ASM_ARC_POSIX_TYPES_H
+
+typedef unsigned short         __kernel_dev_t;
+typedef unsigned long          __kernel_ino_t;
+typedef unsigned short         __kernel_mode_t;
+typedef unsigned short         __kernel_nlink_t;
+typedef long                   __kernel_off_t;
+typedef int                    __kernel_pid_t;
+typedef unsigned short         __kernel_ipc_pid_t;
+typedef unsigned short         __kernel_uid_t;
+typedef unsigned short         __kernel_gid_t;
+typedef unsigned int           __kernel_size_t;
+typedef int                    __kernel_ssize_t;
+typedef int                    __kernel_ptrdiff_t;
+typedef long                   __kernel_time_t;
+typedef long                   __kernel_suseconds_t;
+typedef long                   __kernel_clock_t;
+typedef int                    __kernel_daddr_t;
+typedef char                   *__kernel_caddr_t;
+typedef unsigned short         __kernel_uid16_t;
+typedef unsigned short         __kernel_gid16_t;
+typedef unsigned int           __kernel_uid32_t;
+typedef unsigned int           __kernel_gid32_t;
+
+typedef unsigned short         __kernel_old_uid_t;
+typedef unsigned short         __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long              __kernel_loff_t;
+#endif
+
+#endif /* __ASM_ARC_POSIX_TYPES_H */
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
new file mode 100644 (file)
index 0000000..8f73b31
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_PTRACE_H
+#define __ASM_ARC_PTRACE_H
+
+struct pt_regs {
+       long bta;
+       long lp_start;
+       long lp_end;
+       long lp_count;
+       long status32;
+       long ret;
+       long blink;
+       long fp;
+       long r26;       /* gp */
+       long r25;
+       long r24;
+       long r23;
+       long r22;
+       long r21;
+       long r20;
+       long r19;
+       long r18;
+       long r17;
+       long r16;
+       long r15;
+       long r14;
+       long r13;
+       long r12;
+       long r11;
+       long r10;
+       long r9;
+       long r8;
+       long r7;
+       long r6;
+       long r5;
+       long r4;
+       long r3;
+       long r2;
+       long r1;
+       long r0;
+       long sp;
+       long ecr;
+};
+
+#endif /* __ASM_ARC_PTRACE_H */
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
new file mode 100644 (file)
index 0000000..18484a1
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_SECTIONS_H
+#define __ASM_ARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern ulong __text_end;
+
+#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
new file mode 100644 (file)
index 0000000..909129c
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_STRING_H
+#define __ASM_ARC_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_STRCHR
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRLEN
+
+extern void *memset(void *ptr, int, __kernel_size_t);
+extern void *memcpy(void *, const void *, __kernel_size_t);
+extern void memzero(void *ptr, __kernel_size_t n);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+extern char *strchr(const char *s, int c);
+extern char *strcpy(char *dest, const char *src);
+extern int strcmp(const char *cs, const char *ct);
+extern __kernel_size_t strlen(const char *);
+
+#endif /* __ASM_ARC_STRING_H */
diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h
new file mode 100644 (file)
index 0000000..24eeb76
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_TYPES_H
+#define __ASM_ARC_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __ASM_ARC_TYPES_H */
diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h
new file mode 100644 (file)
index 0000000..0c0e8e6
--- /dev/null
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_ARC_H__
+#define __ASM_ARC_U_BOOT_ARC_H__
+
+int arch_early_init_r(void);
+
+#endif /* __ASM_ARC_U_BOOT_ARC_H__ */
diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h
new file mode 100644 (file)
index 0000000..e354edf
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_H__
+#define __ASM_ARC_U_BOOT_H__
+
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_ARC
+
+#endif /* __ASM_ARC_U_BOOT_H__ */
diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h
new file mode 100644 (file)
index 0000000..6cecbbb
--- /dev/null
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
new file mode 100644 (file)
index 0000000..7675f85
--- /dev/null
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += sections.o
+obj-y += relocate.o
+obj-y += strchr-700.o
+obj-y += strcmp.o
+obj-y += strcpy-700.o
+obj-y += strlen.o
+obj-y += memcmp.o
+obj-y += memcpy-700.o
+obj-y += memset.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
new file mode 100644 (file)
index 0000000..d185a50
--- /dev/null
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
+{
+       ulong ret;
+
+       asm("mov %0, sp" : "=r"(ret) : );
+       return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+       ulong sp;
+
+       /*
+        * Booting a (Linux) kernel image
+        *
+        * Allocate space for command line and board info - the
+        * address should be as high as possible within the reach of
+        * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+        * memory, which means far enough below the current stack
+        * pointer.
+        */
+       sp = get_sp();
+       debug("## Current stack ends at 0x%08lx ", sp);
+
+       /* adjust sp by 4K to be safe */
+       sp -= 4096;
+       lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+}
+
+static int cleanup_before_linux(void)
+{
+       disable_interrupts();
+       flush_dcache_all();
+       invalidate_icache_all();
+
+       return 0;
+}
+
+/* Subcommand: PREP */
+static void boot_prep_linux(bootm_headers_t *images)
+{
+       if (image_setup_linux(images))
+               hang();
+}
+
+/* Subcommand: GO */
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+       void (*kernel_entry)(int zero, int arch, uint params);
+       unsigned int r0, r2;
+       int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+       kernel_entry = (void (*)(int, int, uint))images->ep;
+
+       debug("## Transferring control to Linux (at address %08lx)...\n",
+             (ulong) kernel_entry);
+       bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+       printf("\nStarting kernel ...%s\n\n", fake ?
+              "(fake run for tracing)" : "");
+       bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+
+       cleanup_before_linux();
+
+       if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+               r0 = 2;
+               r2 = (unsigned int)images->ft_addr;
+       } else {
+               r0 = 1;
+               r2 = (unsigned int)getenv("bootargs");
+       }
+
+       if (!fake)
+               kernel_entry(r0, 0, r2);
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+       /* No need for those on ARC */
+       if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
+               return -1;
+
+       if (flag & BOOTM_STATE_OS_PREP) {
+               boot_prep_linux(images);
+               return 0;
+       }
+
+       if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+               boot_jump_linux(images, flag);
+               return 0;
+       }
+
+       boot_prep_linux(images);
+       boot_jump_linux(images, flag);
+       return 0;
+}
diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
new file mode 100644 (file)
index 0000000..fa5aac5
--- /dev/null
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifdef __LITTLE_ENDIAN__
+#define WORD2 r2
+#define SHIFT r3
+#else /* __BIG_ENDIAN__ */
+#define WORD2 r3
+#define SHIFT r2
+#endif /* _ENDIAN__ */
+
+.global memcmp
+.align 4
+memcmp:
+       or      %r12, %r0, %r1
+       asl_s   %r12, %r12, 30
+       sub     %r3, %r2, 1
+       brls    %r2, %r12, .Lbytewise
+       ld      %r4, [%r0, 0]
+       ld      %r5, [%r1, 0]
+       lsr.f   %lp_count, %r3, 3
+       lpne    .Loop_end
+       ld_s    WORD2, [%r0, 4]
+       ld_s    %r12, [%r1, 4]
+       brne    %r4, %r5, .Leven
+       ld.a    %r4, [%r0, 8]
+       ld.a    %r5, [%r1, 8]
+       brne    WORD2, %r12, .Lodd
+.Loop_end:
+       asl_s   SHIFT, SHIFT, 3
+       bhs_s   .Last_cmp
+       brne    %r4, %r5, .Leven
+       ld      %r4, [%r0, 4]
+       ld      %r5, [%r1, 4]
+#ifdef __LITTLE_ENDIAN__
+       nop_s
+       /* one more load latency cycle */
+.Last_cmp:
+       xor     %r0, %r4, %r5
+       bset    %r0, %r0, SHIFT
+       sub_s   %r1, %r0, 1
+       bic_s   %r1, %r1, %r0
+       norm    %r1, %r1
+       b.d     .Leven_cmp
+       and     %r1, %r1, 24
+.Leven:
+       xor     %r0, %r4, %r5
+       sub_s   %r1, %r0, 1
+       bic_s   %r1, %r1, %r0
+       norm    %r1, %r1
+       /* slow track insn */
+       and     %r1, %r1, 24
+.Leven_cmp:
+       asl     %r2, %r4, %r1
+       asl     %r12, %r5, %r1
+       lsr_s   %r2, %r2, 1
+       lsr_s   %r12, %r12, 1
+       j_s.d   [%blink]
+       sub     %r0, %r2, %r12
+       .balign 4
+.Lodd:
+       xor     %r0, WORD2, %r12
+       sub_s   %r1, %r0, 1
+       bic_s   %r1, %r1, %r0
+       norm    %r1, %r1
+       /* slow track insn */
+       and     %r1, %r1, 24
+       asl_s   %r2, %r2, %r1
+       asl_s   %r12, %r12, %r1
+       lsr_s   %r2, %r2, 1
+       lsr_s   %r12, %r12, 1
+       j_s.d   [%blink]
+       sub     %r0, %r2, %r12
+#else /* __BIG_ENDIAN__ */
+.Last_cmp:
+       neg_s   SHIFT, SHIFT
+       lsr     %r4, %r4, SHIFT
+       lsr     %r5, %r5, SHIFT
+       /* slow track insn */
+.Leven:
+       sub.f   %r0, %r4, %r5
+       mov.ne  %r0, 1
+       j_s.d   [%blink]
+       bset.cs %r0, %r0, 31
+.Lodd:
+       cmp_s   WORD2, %r12
+
+       mov_s   %r0, 1
+       j_s.d   [%blink]
+       bset.cs %r0, %r0, 31
+#endif /* _ENDIAN__ */
+       .balign 4
+.Lbytewise:
+       breq    %r2, 0, .Lnil
+       ldb     %r4, [%r0, 0]
+       ldb     %r5, [%r1, 0]
+       lsr.f   %lp_count, %r3
+       lpne    .Lbyte_end
+       ldb_s   %r3, [%r0, 1]
+       ldb     %r12, [%r1, 1]
+       brne    %r4, %r5, .Lbyte_even
+       ldb.a   %r4, [%r0, 2]
+       ldb.a   %r5, [%r1, 2]
+       brne    %r3, %r12, .Lbyte_odd
+.Lbyte_end:
+       bcc     .Lbyte_even
+       brne    %r4, %r5, .Lbyte_even
+       ldb_s   %r3, [%r0, 1]
+       ldb_s   %r12, [%r1, 1]
+.Lbyte_odd:
+       j_s.d   [%blink]
+       sub     %r0, %r3, %r12
+.Lbyte_even:
+       j_s.d   [%blink]
+       sub     %r0, %r4, %r5
+.Lnil:
+       j_s.d   [%blink]
+       mov     %r0, 0
diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S
new file mode 100644 (file)
index 0000000..51dd73a
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+.global memcpy
+.align 4
+memcpy:
+       or      %r3, %r0, %r1
+       asl_s   %r3, %r3, 30
+       mov_s   %r5, %r0
+       brls.d  %r2, %r3, .Lcopy_bytewise
+       sub.f   %r3, %r2, 1
+       ld_s    %r12, [%r1, 0]
+       asr.f   %lp_count, %r3, 3
+       bbit0.d %r3, 2, .Lnox4
+       bmsk_s  %r2, %r2, 1
+       st.ab   %r12, [%r5, 4]
+       ld.a    %r12, [%r1, 4]
+.Lnox4:
+       lppnz   .Lendloop
+       ld_s    %r3, [%r1, 4]
+       st.ab   %r12, [%r5, 4]
+       ld.a    %r12, [%r1, 8]
+       st.ab   %r3, [%r5, 4]
+.Lendloop:
+       breq    %r2, 0, .Last_store
+       ld      %r3, [%r5, 0]
+#ifdef __LITTLE_ENDIAN__
+       add3    %r2, -1, %r2
+       /* uses long immediate */
+       xor_s   %r12, %r12, %r3
+       bmsk    %r12, %r12, %r2
+       xor_s   %r12, %r12, %r3
+#else /* __BIG_ENDIAN__ */
+       sub3    %r2, 31, %r2
+       /* uses long immediate */
+       xor_s   %r3, %r3, %r12
+       bmsk    %r3, %r3, %r2
+       xor_s   %r12, %r12, %r3
+#endif /* _ENDIAN__ */
+.Last_store:
+       j_s.d   [%blink]
+       st      %r12, [%r5, 0]
+
+       .balign 4
+.Lcopy_bytewise:
+       jcs     [%blink]
+       ldb_s   %r12, [%r1, 0]
+       lsr.f   %lp_count, %r3
+       bhs_s   .Lnox1
+       stb.ab  %r12, [%r5, 1]
+       ldb.a   %r12, [%r1, 1]
+.Lnox1:
+       lppnz   .Lendbloop
+       ldb_s   %r3, [%r1, 1]
+       stb.ab  %r12, [%r5, 1]
+       ldb.a   %r12, [%r1, 2]
+       stb.ab  %r3, [%r5, 1]
+.Lendbloop:
+       j_s.d   [%blink]
+       stb     %r12, [%r5, 0]
diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S
new file mode 100644 (file)
index 0000000..017e8af
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#define SMALL  7 /* Must be at least 6 to deal with alignment/loop issues.  */
+
+.global memset
+.align 4
+memset:
+       mov_s   %r4, %r0
+       or      %r12, %r0, %r2
+       bmsk.f  %r12, %r12, 1
+       extb_s  %r1, %r1
+       asl     %r3, %r1, 8
+       beq.d   .Laligned
+       or_s    %r1, %r1, %r3
+       brls    %r2, SMALL, .Ltiny
+       add     %r3, %r2, %r0
+       stb     %r1, [%r3, -1]
+       bclr_s  %r3, %r3, 0
+       stw     %r1, [%r3, -2]
+       bmsk.f  %r12, %r0, 1
+       add_s   %r2, %r2, %r12
+       sub.ne  %r2, %r2, 4
+       stb.ab  %r1, [%r4, 1]
+       and     %r4, %r4, -2
+       stw.ab  %r1, [%r4, 2]
+       and     %r4, %r4, -4
+
+       .balign 4
+.Laligned:
+       asl     %r3, %r1, 16
+       lsr.f   %lp_count, %r2, 2
+       or_s    %r1, %r1, %r3
+       lpne    .Loop_end
+       st.ab   %r1, [%r4, 4]
+.Loop_end:
+       j_s     [%blink]
+
+       .balign 4
+.Ltiny:
+       mov.f   %lp_count, %r2
+       lpne    .Ltiny_end
+       stb.ab  %r1, [%r4, 1]
+.Ltiny_end:
+       j_s     [%blink]
+
+/*
+ * memzero: @r0 = mem, @r1 = size_t
+ * memset:  @r0 = mem, @r1 = char, @r2 = size_t
+ */
+
+.global memzero
+.align 4
+memzero:
+       /* adjust bzero args to memset args */
+       mov     %r2, %r1
+       mov     %r1, 0
+       /* tail call so need to tinker with blink */
+       b       memset
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
new file mode 100644 (file)
index 0000000..956aa14
--- /dev/null
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <elf.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Base functionality is taken from x86 version with added ARC-specifics
+ */
+int do_elf_reloc_fixups(void)
+{
+       Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
+       Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+
+       Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+       Elf32_Addr *offset_ptr_ram;
+
+       do {
+               /* Get the location from the relocation entry */
+               offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+
+               /* Check that the location of the relocation is in .text */
+               if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+                   offset_ptr_rom > last_offset) {
+                       unsigned int val;
+                       /* Switch to the in-RAM version */
+                       offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
+                                                       gd->reloc_off);
+
+                       /*
+                        * Use "memcpy" because target location might be
+                        * 16-bit aligned on ARC so we may need to read
+                        * byte-by-byte. On attempt to read entire word by
+                        * CPU throws an exception
+                        */
+                       memcpy(&val, offset_ptr_ram, sizeof(int));
+
+                       /* If location in ".text" section swap value */
+                       if ((unsigned int)offset_ptr_rom <
+                           (unsigned int)&__text_end)
+                               val = (val << 16) | (val >> 16);
+
+                       /* Check that the target points into .text */
+                       if (val >= CONFIG_SYS_TEXT_BASE && val <=
+                           (unsigned int)&__bss_end) {
+                               val += gd->reloc_off;
+                               /* If location in ".text" section swap value */
+                               if ((unsigned int)offset_ptr_rom <
+                                   (unsigned int)&__text_end)
+                                       val = (val << 16) | (val >> 16);
+                               memcpy(offset_ptr_ram, &val, sizeof(int));
+                       } else {
+                               debug("   %p: rom reloc %x, ram %p, value %x, limit %x\n",
+                                     re_src, re_src->r_offset, offset_ptr_ram,
+                                     val, (unsigned int)&__bss_end);
+                       }
+               } else {
+                       debug("   %p: rom reloc %x, last %p\n", re_src,
+                             re_src->r_offset, last_offset);
+               }
+               last_offset = offset_ptr_rom;
+
+       } while (++re_src < re_end);
+
+       return 0;
+}
diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c
new file mode 100644 (file)
index 0000000..b0b46a4
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * For some reason linker sets linker-generated symbols to zero in PIE mode.
+ * A work-around is substitution of linker-generated symbols with
+ * compiler-generated symbols which are properly handled by linker in PAE mode.
+ */
+
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char __text_start[0] __attribute__((section(".__text_start")));
+char __text_end[0] __attribute__((section(".__text_end")));
+char __init_end[0] __attribute__((section(".__init_end")));
diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S
new file mode 100644 (file)
index 0000000..55fcc9f
--- /dev/null
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * ARC700 has a relatively long pipeline and branch prediction, so we want
+ * to avoid branches that are hard to predict.  On the other hand, the
+ * presence of the norm instruction makes it easier to operate on whole
+ * words branch-free.
+ */
+
+.global strchr
+.align 4
+strchr:
+       extb_s  %r1, %r1
+       asl     %r5, %r1, 8
+       bmsk    %r2, %r0, 1
+       or      %r5, %r5, %r1
+       mov_s   %r3, 0x01010101
+       breq.d  %r2, %r0, .Laligned
+       asl     %r4, %r5, 16
+       sub_s   %r0, %r0, %r2
+       asl     %r7, %r2, 3
+       ld_s    %r2, [%r0]
+#ifdef __LITTLE_ENDIAN__
+       asl     %r7, %r3, %r7
+#else /* __BIG_ENDIAN__ */
+       lsr     %r7, %r3, %r7
+#endif /* _ENDIAN__ */
+       or      %r5, %r5, %r4
+       ror     %r4, %r3
+       sub     %r12, %r2, %r7
+       bic_s   %r12, %r12, %r2
+       and     %r12, %r12, %r4
+       brne.d  %r12, 0, .Lfound0_ua
+       xor     %r6, %r2, %r5
+       ld.a    %r2, [%r0, 4]
+       sub     %r12, %r6, %r7
+       bic     %r12, %r12, %r6
+#ifdef __LITTLE_ENDIAN__
+       and     %r7, %r12, %r4
+       /* For speed, we want this branch to be unaligned. */
+       breq    %r7, 0, .Loop
+       /* Likewise this one */
+       b       .Lfound_char
+#else /* __BIG_ENDIAN__ */
+       and     %r12, %r12, %r4
+       /* For speed, we want this branch to be unaligned. */
+       breq    %r12, 0, .Loop
+       lsr_s   %r12, %r12, 7
+       bic     %r2, %r7, %r6
+       b.d     .Lfound_char_b
+       and_s   %r2, %r2, %r12
+#endif /* _ENDIAN__ */
+       /* We require this code address to be unaligned for speed...  */
+.Laligned:
+       ld_s    %r2, [%r0]
+       or      %r5, %r5, %r4
+       ror     %r4, %r3
+       /* ... so that this code address is aligned, for itself and ...  */
+.Loop:
+       sub     %r12, %r2, %r3
+       bic_s   %r12, %r12, %r2
+       and     %r12, %r12, %r4
+       brne.d  %r12, 0, .Lfound0
+       xor     %r6, %r2, %r5
+       ld.a    %r2, [%r0, 4]
+       sub     %r12, %r6, %r3
+       bic     %r12, %r12, %r6
+       and     %r7, %r12, %r4
+       breq    %r7, 0, .Loop
+       /*
+        *... so that this branch is unaligned.
+        * Found searched-for character.
+        * r0 has already advanced to next word.
+        */
+#ifdef __LITTLE_ENDIAN__
+       /*
+        * We only need the information about the first matching byte
+        * (i.e. the least significant matching byte) to be exact,
+        * hence there is no problem with carry effects.
+        */
+.Lfound_char:
+       sub     %r3, %r7, 1
+       bic     %r3, %r3, %r7
+       norm    %r2, %r3
+       sub_s   %r0, %r0, 1
+       asr_s   %r2, %r2, 3
+       j.d     [%blink]
+       sub_s   %r0, %r0, %r2
+
+       .balign 4
+.Lfound0_ua:
+       mov     %r3, %r7
+.Lfound0:
+       sub     %r3, %r6, %r3
+       bic     %r3, %r3, %r6
+       and     %r2, %r3, %r4
+       or_s    %r12, %r12, %r2
+       sub_s   %r3, %r12, 1
+       bic_s   %r3, %r3, %r12
+       norm    %r3, %r3
+       add_s   %r0, %r0, 3
+       asr_s   %r12, %r3, 3
+       asl.f   0, %r2, %r3
+       sub_s   %r0, %r0, %r12
+       j_s.d   [%blink]
+       mov.pl  %r0, 0
+#else /* __BIG_ENDIAN__ */
+.Lfound_char:
+       lsr     %r7, %r7, 7
+
+       bic     %r2, %r7, %r6
+.Lfound_char_b:
+       norm    %r2, %r2
+       sub_s   %r0, %r0, 4
+       asr_s   %r2, %r2, 3
+       j.d     [%blink]
+       add_s   %r0, %r0, %r2
+
+.Lfound0_ua:
+       mov_s   %r3, %r7
+.Lfound0:
+       asl_s   %r2, %r2, 7
+       or      %r7, %r6, %r4
+       bic_s   %r12, %r12, %r2
+       sub     %r2, %r7, %r3
+       or      %r2, %r2, %r6
+       bic     %r12, %r2, %r12
+       bic.f   %r3, %r4, %r12
+       norm    %r3, %r3
+
+       add.pl  %r3, %r3, 1
+       asr_s   %r12, %r3, 3
+       asl.f   0, %r2, %r3
+       add_s   %r0, %r0, %r12
+       j_s.d   [%blink]
+       mov.mi  %r0, 0
+#endif /* _ENDIAN__ */
diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S
new file mode 100644 (file)
index 0000000..8cb7d2f
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * This is optimized primarily for the ARC700.
+ * It would be possible to speed up the loops by one cycle / word
+ * respective one cycle / byte by forcing double source 1 alignment, unrolling
+ * by a factor of two, and speculatively loading the second word / byte of
+ * source 1; however, that would increase the overhead for loop setup / finish,
+ * and strcmp might often terminate early.
+ */
+
+.global strcmp
+.align 4
+strcmp:
+       or      %r2, %r0, %r1
+       bmsk_s  %r2, %r2, 1
+       brne    %r2, 0, .Lcharloop
+       mov_s   %r12, 0x01010101
+       ror     %r5, %r12
+.Lwordloop:
+       ld.ab   %r2, [%r0, 4]
+       ld.ab   %r3, [%r1, 4]
+       nop_s
+       sub     %r4, %r2, %r12
+       bic     %r4, %r4, %r2
+       and     %r4, %r4, %r5
+       brne    %r4, 0, .Lfound0
+       breq    %r2 ,%r3, .Lwordloop
+#ifdef __LITTLE_ENDIAN__
+       xor     %r0, %r2, %r3   /* mask for difference */
+       sub_s   %r1, %r0, 1
+       bic_s   %r0, %r0, %r1   /* mask for least significant difference bit */
+       sub     %r1, %r5, %r0
+       xor     %r0, %r5, %r1   /* mask for least significant difference byte */
+       and_s   %r2, %r2, %r0
+       and_s   %r3, %r3, %r0
+#endif /* _ENDIAN__ */
+       cmp_s   %r2, %r3
+       mov_s   %r0, 1
+       j_s.d   [%blink]
+       bset.lo %r0, %r0, 31
+
+       .balign 4
+#ifdef __LITTLE_ENDIAN__
+.Lfound0:
+       xor     %r0, %r2, %r3   /* mask for difference */
+       or      %r0, %r0, %r4   /* or in zero indicator */
+       sub_s   %r1, %r0, 1
+       bic_s   %r0, %r0, %r1   /* mask for least significant difference bit */
+       sub     %r1, %r5, %r0
+       xor     %r0, %r5, %r1   /* mask for least significant difference byte */
+       and_s   %r2, %r2, %r0
+       and_s   %r3, %r3, %r0
+       sub.f   %r0, %r2, %r3
+       mov.hi  %r0, 1
+       j_s.d   [%blink]
+       bset.lo %r0, %r0, 31
+#else /* __BIG_ENDIAN__ */
+       /*
+        * The zero-detection above can mis-detect 0x01 bytes as zeroes
+        * because of carry-propagateion from a lower significant zero byte.
+        * We can compensate for this by checking that bit0 is zero.
+        * This compensation is not necessary in the step where we
+        * get a low estimate for r2, because in any affected bytes
+        * we already have 0x00 or 0x01, which will remain unchanged
+        * when bit 7 is cleared.
+        */
+       .balign 4
+.Lfound0:
+       lsr     %r0, %r4, 8
+       lsr_s   %r1, %r2
+       bic_s   %r2, %r2, %r0   /* get low estimate for r2 and get ... */
+       bic_s   %r0, %r0, %r1   /* <this is the adjusted mask for zeros> */
+       or_s    %r3, %r3, %r0   /* ... high estimate r3 so that r2 > r3 will */
+       cmp_s   %r3, %r2        /* ... be independent of trailing garbage */
+       or_s    %r2, %r2, %r0   /* likewise for r3 > r2 */
+       bic_s   %r3, %r3, %r0
+       rlc     %r0, 0          /* r0 := r2 > r3 ? 1 : 0 */
+       cmp_s   %r2, %r3
+       j_s.d   [%blink]
+       bset.lo %r0, %r0, 31
+#endif /* _ENDIAN__ */
+
+       .balign 4
+.Lcharloop:
+       ldb.ab  %r2,[%r0,1]
+       ldb.ab  %r3,[%r1,1]
+       nop_s
+       breq    %r2, 0, .Lcmpend
+       breq    %r2, %r3, .Lcharloop
+.Lcmpend:
+       j_s.d   [%blink]
+       sub     %r0, %r2, %r3
diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S
new file mode 100644 (file)
index 0000000..41bb53e
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * If dst and src are 4 byte aligned, copy 8 bytes at a time.
+ * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
+ * it 8 byte aligned.  Thus, we can do a little read-ahead, without
+ * dereferencing a cache line that we should not touch.
+ * Note that short and long instructions have been scheduled to avoid
+ * branch stalls.
+ * The beq_s to r3z could be made unaligned & long to avoid a stall
+ * there, but it is not likely to be taken often, and it would also be likely
+ * to cost an unaligned mispredict at the next call.
+ */
+
+.global strcpy
+.align 4
+strcpy:
+       or      %r2, %r0, %r1
+       bmsk_s  %r2, %r2, 1
+       brne.d  %r2, 0, charloop
+       mov_s   %r10, %r0
+       ld_s    %r3, [%r1, 0]
+       mov     %r8, 0x01010101
+       bbit0.d %r1, 2, loop_start
+       ror     %r12, %r8
+       sub     %r2, %r3, %r8
+       bic_s   %r2, %r2, %r3
+       tst_s   %r2,%r12
+       bne     r3z
+       mov_s   %r4,%r3
+       .balign 4
+loop:
+       ld.a    %r3, [%r1, 4]
+       st.ab   %r4, [%r10, 4]
+loop_start:
+       ld.a    %r4, [%r1, 4]
+       sub     %r2, %r3, %r8
+       bic_s   %r2, %r2, %r3
+       tst_s   %r2, %r12
+       bne_s   r3z
+       st.ab   %r3, [%r10, 4]
+       sub     %r2, %r4, %r8
+       bic     %r2, %r2, %r4
+       tst     %r2, %r12
+       beq     loop
+       mov_s   %r3, %r4
+#ifdef __LITTLE_ENDIAN__
+r3z:   bmsk.f  %r1, %r3, 7
+       lsr_s   %r3, %r3, 8
+#else /* __BIG_ENDIAN__ */
+r3z:   lsr.f   %r1, %r3, 24
+       asl_s   %r3, %r3, 8
+#endif /* _ENDIAN__ */
+       bne.d   r3z
+       stb.ab  %r1, [%r10, 1]
+       j_s     [%blink]
+
+       .balign 4
+charloop:
+       ldb.ab  %r3, [%r1, 1]
+       brne.d  %r3, 0, charloop
+       stb.ab  %r3, [%r10, 1]
+       j       [%blink]
diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S
new file mode 100644 (file)
index 0000000..666e22c
--- /dev/null
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+.global strlen
+.align 4
+strlen:
+       or      %r3, %r0, 7
+       ld      %r2, [%r3, -7]
+       ld.a    %r6, [%r3, -3]
+       mov     %r4, 0x01010101
+       /* uses long immediate */
+#ifdef __LITTLE_ENDIAN__
+       asl_s   %r1, %r0, 3
+       btst_s  %r0, 2
+       asl     %r7, %r4, %r1
+       ror     %r5, %r4
+       sub     %r1, %r2, %r7
+       bic_s   %r1, %r1, %r2
+       mov.eq  %r7, %r4
+       sub     %r12, %r6, %r7
+       bic     %r12, %r12, %r6
+       or.eq   %r12, %r12, %r1
+       and     %r12, %r12, %r5
+       brne    %r12, 0, .Learly_end
+#else /* __BIG_ENDIAN__ */
+       ror     %r5, %r4
+       btst_s  %r0, 2
+       mov_s   %r1, 31
+       sub3    %r7, %r1, %r0
+       sub     %r1, %r2, %r4
+       bic_s   %r1, %r1, %r2
+       bmsk    %r1, %r1, %r7
+       sub     %r12, %r6, %r4
+       bic     %r12, %r12, %r6
+       bmsk.ne %r12, %r12, %r7
+       or.eq   %r12, %r12, %r1
+       and     %r12, %r12, %r5
+       brne    %r12, 0, .Learly_end
+#endif /* _ENDIAN__ */
+
+.Loop:
+       ld_s    %r2, [%r3, 4]
+       ld.a    %r6, [%r3, 8]
+       /* stall for load result */
+       sub     %r1, %r2, %r4
+       bic_s   %r1, %r1, %r2
+       sub     %r12, %r6, %r4
+       bic     %r12, %r12, %r6
+       or      %r12, %r12, %r1
+       and     %r12, %r12, %r5
+       breq    %r12, 0, .Loop
+.Lend:
+       and.f   %r1, %r1, %r5
+       sub.ne  %r3, %r3, 4
+       mov.eq  %r1, %r12
+#ifdef __LITTLE_ENDIAN__
+       sub_s   %r2, %r1, 1
+       bic_s   %r2, %r2, %r1
+       norm    %r1, %r2
+       sub_s   %r0, %r0, 3
+       lsr_s   %r1, %r1, 3
+       sub     %r0, %r3, %r0
+       j_s.d   [%blink]
+       sub     %r0, %r0, %r1
+#else /* __BIG_ENDIAN__ */
+       lsr_s   %r1, %r1, 7
+       mov.eq  %r2, %r6
+       bic_s   %r1, %r1, %r2
+       norm    %r1, %r1
+       sub     %r0, %r3, %r0
+       lsr_s   %r1, %r1, 3
+       j_s.d   [%blink]
+       add     %r0, %r0, %r1
+#endif /* _ENDIAN */
+.Learly_end:
+       b.d     .Lend
+       sub_s.ne %r1, %r1, %r1
index 1fec7f3..ab7fa45 100644 (file)
@@ -49,7 +49,7 @@ program_async_controller(ADI_BOOT_DATA *bs)
 
        serial_putc('a');
 
-#ifdef __ADSPBF60x__
+#ifndef __ADSPBF60x__
        /* Program the async banks controller. */
 #ifdef EBIU_AMGCTL
        bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
@@ -74,7 +74,7 @@ program_async_controller(ADI_BOOT_DATA *bs)
 
        serial_putc('c');
 
-#else   /* __ADSPBF60x__ */
+#else  /* __ADSPBF60x__ */
        /* Program the static memory controller. */
 # ifdef CONFIG_SMC_GCTL_VAL
        bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
@@ -116,7 +116,7 @@ program_async_controller(ADI_BOOT_DATA *bs)
        bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
 # endif
 
-#endif
+#endif /* __ADSPBF60x__ */
        serial_putc('d');
 }
 
index c99cf49..29a7c23 100644 (file)
@@ -190,6 +190,7 @@ ENTRY(_start)
        call _memcpy_ASM;
 #endif
 
+.Lnorelocate:
        /* Initialize BSS section ... we know that memset() does not
         * use the BSS, so it is safe to call here.  The bootrom LDR
         * takes care of clearing things for us.
@@ -202,7 +203,6 @@ ENTRY(_start)
        r2.h = __bss_len;
        call _memset;
 
-.Lnorelocate:
 
        /* Setup the actual stack in external memory */
        sp.h = HI(CONFIG_STACKBASE);
index 7a43bbb..4c9bc9d 100644 (file)
 #define        TX_GE1024_CNT   0x00200000      /* 1024-Max-Byte TX Frames Sent */
 #define        TX_ABORT_CNT    0x00400000      /* TX Frames Aborted */
 
+/*default value for EMAC_VLANx reg*/
+#define EMAC_VLANX_DEF_VAL 0xFFFF
+
 #endif
index 392d72d..facbc7a 100644 (file)
@@ -142,7 +142,8 @@ void init_cplbtables(void)
        ++i;
 #if defined(__ADSPBF60x__)
        icplb_add(0x0, 0x0);
-       dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU);
+       dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
+               CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
        ++i;
 #endif
 
index cfc64fe..43a4330 100644 (file)
@@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis)
        if (CONFIG_DW_PORTS & 1) {
                static const unsigned short pins[] = P_RMII0;
                if (!peripheral_request_list(pins, "emac0"))
-                       ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
+                       ret += designware_initialize(EMAC0_MACCFG, 0);
        }
        if (CONFIG_DW_PORTS & 2) {
                static const unsigned short pins[] = P_RMII1;
                if (!peripheral_request_list(pins, "emac1"))
-                       ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
+                       ret += designware_initialize(EMAC1_MACCFG, 0);
        }
 
        return ret;
index e25aba2..6b6bd9f 100644 (file)
@@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
        u32 interface = PHY_INTERFACE_MODE_MII;
-       if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-                               interface) >= 0)
+       if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
                ret++;
 #endif
        return ret;
index 70f9aa1..a4c6a8e 100644 (file)
@@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
        u32 interface = PHY_INTERFACE_MODE_MII;
-       if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-                               interface) >= 0)
+       if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
                ret++;
 #endif
 #if defined(CONFIG_MACB)
index f6b1fdd..ab732a7 100644 (file)
@@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis)
 
 #if defined(CONFIG_DESIGNWARE_ETH)
        u32 interface = PHY_INTERFACE_MODE_MII;
-       if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-                               interface) >= 0)
+       if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
                ret++;
 #endif
 #if defined(CONFIG_MACB)
index e996a0e..8472002 100644 (file)
@@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_DW_AUTONEG)
        interface = PHY_INTERFACE_MODE_GMII;
 #endif
-       if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
-                               interface) >= 0)
+       if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
                ret++;
 #endif
        return ret;
index 044d204..b8edfcd 100644 (file)
@@ -67,31 +67,32 @@ void board_nand_init(void)
                fsmc_nand_init(nand);
 }
 
-int designware_board_phy_init(struct eth_device *dev, int phy_addr,
-       int (*mii_write)(struct eth_device *, u8, u8, u16),
-       int dw_reset_phy(struct eth_device *))
+int board_phy_config(struct phy_device *phydev)
 {
        /* Extended PHY control 1, select GMII */
-       mii_write(dev, phy_addr, 23, 0x0020);
+       phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
 
        /* Software reset necessary after GMII mode selction */
-       dw_reset_phy(dev);
+       phy_reset(phydev);
 
        /* Enable extended page register access */
-       mii_write(dev, phy_addr, 31, 0x0001);
+       phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
 
        /* 17e: Enhanced LED behavior, needs to be written twice */
-       mii_write(dev, phy_addr, 17, 0x09ff);
-       mii_write(dev, phy_addr, 17, 0x09ff);
+       phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+       phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
 
        /* 16e: Enhanced LED method select */
-       mii_write(dev, phy_addr, 16, 0xe0ea);
+       phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
 
        /* Disable extended page register access */
-       mii_write(dev, phy_addr, 31, 0x0000);
+       phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
 
        /* Enable clock output pin */
-       mii_write(dev, phy_addr, 18, 0x0049);
+       phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+
+       if (phydev->drv->config)
+               phydev->drv->config(phydev);
 
        return 0;
 }
@@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis)
 {
        int ret = 0;
 
-       if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
+       if (designware_initialize(CONFIG_SPEAR_ETHBASE,
                                  PHY_INTERFACE_MODE_GMII) >= 0)
                ret++;
 
diff --git a/board/synopsys/arcangel4/Makefile b/board/synopsys/arcangel4/Makefile
new file mode 100644 (file)
index 0000000..575e58f
--- /dev/null
@@ -0,0 +1,11 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+# This board is mostly used for debugging U-Boot in simulation (ISS).
+# The only peripheral which is used on this board is a serial port which
+# requires no initialization except those in "include/configs/arcangel4.h".
+# And now there's no specific initializations for this board.
+# So this Makefile is only required for satisfaction of U-Boot build system.
diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile
new file mode 100644 (file)
index 0000000..f0965f7
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += axs101.o
+obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
new file mode 100644 (file)
index 0000000..4dbeaea
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dwmmc.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_mmc_init(bd_t *bis)
+{
+       struct dwmci_host *host = NULL;
+
+       host = malloc(sizeof(struct dwmci_host));
+       if (!host) {
+               printf("dwmci_host malloc fail!\n");
+               return 1;
+       }
+
+       memset(host, 0, sizeof(struct dwmci_host));
+       host->name = "Synopsys Mobile storage";
+       host->ioaddr = (void *)ARC_DWMMC_BASE;
+       host->buswidth = 4;
+       host->dev_index = 0;
+       host->bus_hz = 25000000;
+
+       add_dwmci(host, 52000000, 400000);
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       if (designware_initialize(0, ARC_DWGMAC_BASE, 0,
+                                 PHY_INTERFACE_MODE_RGMII) >= 0)
+               return 1;
+
+       return 0;
+}
diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs101/nand.c
new file mode 100644 (file)
index 0000000..8672803
--- /dev/null
@@ -0,0 +1,226 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <bouncebuf.h>
+#include <common.h>
+#include <malloc.h>
+#include <nand.h>
+#include <asm/io.h>
+
+#define BUS_WIDTH      8               /* AXI data bus width in bytes  */
+
+/* DMA buffer descriptor bits & masks */
+#define BD_STAT_OWN                    (1 << 31)
+#define BD_STAT_BD_FIRST               (1 << 3)
+#define BD_STAT_BD_LAST                        (1 << 2)
+#define BD_SIZES_BUFFER1_MASK          0xfff
+
+#define BD_STAT_BD_COMPLETE    (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
+
+/* Controller command flags */
+#define B_WFR          (1 << 19)       /* 1b - Wait for ready          */
+#define B_LC           (1 << 18)       /* 1b - Last cycle              */
+#define B_IWC          (1 << 13)       /* 1b - Interrupt when complete */
+
+/* NAND cycle types */
+#define B_CT_ADDRESS   (0x0 << 16)     /* Address operation            */
+#define B_CT_COMMAND   (0x1 << 16)     /* Command operation            */
+#define B_CT_WRITE     (0x2 << 16)     /* Write operation              */
+#define B_CT_READ      (0x3 << 16)     /* Write operation              */
+
+enum nand_isr_t {
+       NAND_ISR_DATAREQUIRED = 0,
+       NAND_ISR_TXUNDERFLOW,
+       NAND_ISR_TXOVERFLOW,
+       NAND_ISR_DATAAVAILABLE,
+       NAND_ISR_RXUNDERFLOW,
+       NAND_ISR_RXOVERFLOW,
+       NAND_ISR_TXDMACOMPLETE,
+       NAND_ISR_RXDMACOMPLETE,
+       NAND_ISR_DESCRIPTORUNAVAILABLE,
+       NAND_ISR_CMDDONE,
+       NAND_ISR_CMDAVAILABLE,
+       NAND_ISR_CMDERROR,
+       NAND_ISR_DATATRANSFEROVER,
+       NAND_ISR_NONE
+};
+
+enum nand_regs_t {
+       AC_FIFO = 0,            /* address and command fifo */
+       IDMAC_BDADDR = 0x18,    /* idmac descriptor list base address */
+       INT_STATUS = 0x118,     /* interrupt status register */
+       INT_CLR_STATUS = 0x120, /* interrupt clear status register */
+};
+
+struct nand_bd {
+       uint32_t status;        /* DES0 */
+       uint32_t sizes;         /* DES1 */
+       uint32_t buffer_ptr0;   /* DES2 */
+       uint32_t buffer_ptr1;   /* DES3 */
+};
+
+#define NAND_REG_WRITE(r, v)   writel(v, CONFIG_SYS_NAND_BASE + r)
+#define NAND_REG_READ(r)       readl(CONFIG_SYS_NAND_BASE + r)
+
+static struct nand_bd *bd;     /* DMA buffer descriptors       */
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:       MTD device structure
+ * @buf:       data buffer
+ * @len:       number of bytes to write
+ */
+static uint32_t nand_flag_is_set(uint32_t flag)
+{
+       uint32_t reg = NAND_REG_READ(INT_STATUS);
+
+       if (reg & (1 << NAND_ISR_CMDERROR))
+               return 0;
+
+       if (reg & (1 << flag)) {
+               NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
+               return 1;
+       }
+
+       return 0;
+}
+
+/**
+ * axs101_nand_write_buf -  write buffer to chip
+ * @mtd:       MTD device structure
+ * @buf:       data buffer
+ * @len:       number of bytes to write
+ */
+static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
+                                  int len)
+{
+       struct bounce_buffer bbstate;
+
+       bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
+
+       /* Setup buffer descriptor */
+       writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+       writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+       writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+       writel(0, &bd->buffer_ptr1);
+
+       /* Issue "write" command */
+       NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
+
+       /* Wait for NAND command and DMA to complete */
+       while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+               ;
+       while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
+               ;
+
+       bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_buf -  read chip data into buffer
+ * @mtd:       MTD device structure
+ * @buf:       buffer to store data
+ * @len:       number of bytes to read
+ */
+static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+       struct bounce_buffer bbstate;
+
+       bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
+
+       /* Setup buffer descriptor */
+       writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
+       writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
+       writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
+       writel(0, &bd->buffer_ptr1);
+
+       /* Issue "read" command */
+       NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
+
+       /* Wait for NAND command and DMA to complete */
+       while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+               ;
+       while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
+               ;
+
+       bounce_buffer_stop(&bbstate);
+}
+
+/**
+ * axs101_nand_read_byte -  read one byte from the chip
+ * @mtd:       MTD device structure
+ */
+static u_char axs101_nand_read_byte(struct mtd_info *mtd)
+{
+       u8 byte;
+
+       axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
+       return byte;
+}
+
+/**
+ * axs101_nand_read_word -  read one word from the chip
+ * @mtd:       MTD device structure
+ */
+static u16 axs101_nand_read_word(struct mtd_info *mtd)
+{
+       u16 word;
+
+       axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
+       return word;
+}
+
+/**
+ * axs101_nand_hwcontrol - NAND control functions wrapper.
+ * @mtd:       MTD device structure
+ * @cmd:       Command
+ */
+static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
+                                  unsigned int ctrl)
+{
+       if (cmd == NAND_CMD_NONE)
+               return;
+
+       cmd = cmd & 0xff;
+
+       switch (ctrl & (NAND_ALE | NAND_CLE)) {
+       /* Address */
+       case NAND_ALE:
+               cmd |= B_CT_ADDRESS;
+               break;
+
+       /* Command */
+       case NAND_CLE:
+               cmd |= B_CT_COMMAND | B_WFR;
+
+               break;
+
+       default:
+               debug("%s: unknown ctrl %#x\n", __func__, ctrl);
+       }
+
+       NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
+       while (!nand_flag_is_set(NAND_ISR_CMDDONE))
+               ;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+       bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
+                                       sizeof(struct nand_bd));
+
+       /* Set buffer descriptor address in IDMAC */
+       NAND_REG_WRITE(IDMAC_BDADDR, bd);
+
+       nand->ecc.mode = NAND_ECC_SOFT;
+       nand->cmd_ctrl = axs101_nand_hwcontrol;
+       nand->read_byte = axs101_nand_read_byte;
+       nand->read_word = axs101_nand_read_word;
+       nand->write_buf = axs101_nand_write_buf;
+       nand->read_buf = axs101_nand_read_buf;
+
+       return 0;
+}
index 706ec96..c97c4bd 100644 (file)
@@ -1230,6 +1230,9 @@ Active  sparc       leon3          -           gaisler         -
 Active  sparc       leon3          -           gaisler         -                   gr_xc3s_1500                         -                                                                                                                                 -
 Active  sparc       leon3          -           gaisler         -                   grsim                                -                                                                                                                                 -
 Active  x86         x86            coreboot    chromebook-x86  coreboot            coreboot-x86                         coreboot:SYS_TEXT_BASE=0x01110000                                                                                                 -
+Active  arc         arc700         -           synopsys        -                   axs101                               -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
+Active  arc         arc700         -           synopsys        -                   arcangel4                            -                                                                                                                                 Alexey Brodkin <abrodkin@synopsys.com>
+Active  arc         arc700         -           synopsys        arcangel4           arcangel4-be                            -                                                                                                                              Alexey Brodkin <abrodkin@synopsys.com>
 Orphan  arm         arm1136        mx31        -               imx31_phycore       imx31_phycore_eet                    imx31_phycore:IMX31_PHYCORE_EET                                                                                                   (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 Orphan  arm         arm1136        mx31        freescale       -                   mx31ads                              -                                                                                                                                 (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 Orphan  arm         pxa            -           -               -                   lubbock                              -                                                                                                                                 (dead address) Kyle Harris <kharris@nexus-tech.net>
index 713de14..15119a7 100644 (file)
@@ -517,6 +517,24 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        return 0;
 }
 
+#elif defined(CONFIG_ARC700)
+
+int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+       bd_t *bd = gd->bd;
+
+       print_num("mem start",          bd->bi_memstart);
+       print_lnum("mem size",          bd->bi_memsize);
+
+#if defined(CONFIG_CMD_NET)
+       print_eth(0);
+       printf("ip_addr     = %s\n", getenv("ipaddr"));
+#endif
+       printf("baudrate    = %d bps\n", bd->bi_baudrate);
+
+       return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif
index ae95c3f..9c6bec5 100644 (file)
@@ -82,6 +82,7 @@ static const table_entry_t uimage_arch[] = {
        {       IH_ARCH_OPENRISC,       "or1k",         "OpenRISC 1000",},
        {       IH_ARCH_SANDBOX,        "sandbox",      "Sandbox",      },
        {       IH_ARCH_ARM64,          "arm64",        "AArch64",      },
+       {       IH_ARCH_ARC,            "arc",          "ARC",          },
        {       -1,                     "",             "",             },
 };
 
diff --git a/doc/README.ARC b/doc/README.ARC
new file mode 100644 (file)
index 0000000..5f414fb
--- /dev/null
@@ -0,0 +1,27 @@
+Synopsys' DesignWare(r) ARC(r) Processors are a family of 32-bit CPUs
+that SoC designers can optimize for a wide range of uses, from deeply embedded
+to high-performance host applications.
+
+More information on ARC cores avaialble here:
+http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
+
+Designers can differentiate their products by using patented configuration
+technology to tailor each ARC processor instance to meet specific performance,
+power and area requirements.
+
+The DesignWare ARC processors are also extendable, allowing designers to add
+their own custom instructions that dramatically increase performance.
+
+Synopsys' ARC processors have been used by over 170 customers worldwide who
+collectively ship more than 1 billion ARC-based chips annually.
+
+All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
+performance and code density for embedded and host SoC applications.
+
+The RISC microprocessors are synthesizable and can be implemented in any foundry
+or process, and are supported by a complete suite of development tools.
+
+The ARC GNU toolchain with support for all ARC Processors can be downloaded
+from here (available pre-built toolchains as well):
+
+https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
diff --git a/doc/README.designware_eth b/doc/README.designware_eth
deleted file mode 100644 (file)
index 25ec6bd..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-This driver supports Designware Ethernet Controller provided by Synopsis.
-
-The driver is enabled by CONFIG_DESIGNWARE_ETH.
-
-The driver has been developed and tested on SPEAr platforms. By default, the
-MDIO interface works at 100/Full. #defining the below options in board
-configuration file changes this behavior.
-
-Call an subroutine from respective board/.../board.c
-designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
-
-The various options suported by the driver are
-1. CONFIG_DW_ALTDESCRIPTOR
-       Define this to use the Alternate/Enhanced Descriptor configurations.
-1. CONFIG_DW_AUTONEG
-       Define this to autonegotiate with the host before proceeding with mac
-       level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
-       and CONFIG_DW_DUPLEXHALF.
-2. CONFIG_DW_SPEED10M
-       Define this to change the default behavior from 100Mbps to 10Mbps.
-3. CONFIG_DW_DUPLEXHALF
-       Define this to change the default behavior from Full Duplex to Half.
-4. CONFIG_DW_SEARCH_PHY
-       Define this to search the phy address. This would overwrite the value
-       passed as 3rd arg from designware_initialize routine.
index 0ffd59d..42e208c 100644 (file)
@@ -259,6 +259,8 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
                *opmode = 0;
 
        bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
+       bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
+       bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
 
        /* Initialize the TX DMA channel registers */
        bfin_write_DMA2_X_COUNT(0);
index 22155b4..c45593b 100644 (file)
 #include <asm/io.h>
 #include "designware.h"
 
-static int configure_phy(struct eth_device *dev);
+#if !defined(CONFIG_PHYLIB)
+# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
+#endif
+
+static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+       struct eth_mac_regs *mac_p = bus->priv;
+       ulong start;
+       u16 miiaddr;
+       int timeout = CONFIG_MDIO_TIMEOUT;
+
+       miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+                 ((reg << MIIREGSHIFT) & MII_REGMSK);
+
+       writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+       start = get_timer(0);
+       while (get_timer(start) < timeout) {
+               if (!(readl(&mac_p->miiaddr) & MII_BUSY))
+                       return readl(&mac_p->miidata);
+               udelay(10);
+       };
+
+       return -1;
+}
+
+static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+                       u16 val)
+{
+       struct eth_mac_regs *mac_p = bus->priv;
+       ulong start;
+       u16 miiaddr;
+       int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+
+       writel(val, &mac_p->miidata);
+       miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
+                 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
+
+       writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+       start = get_timer(0);
+       while (get_timer(start) < timeout) {
+               if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
+                       ret = 0;
+                       break;
+               }
+               udelay(10);
+       };
+
+       return ret;
+}
+
+static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
+{
+       struct mii_dev *bus = mdio_alloc();
+
+       if (!bus) {
+               printf("Failed to allocate MDIO bus\n");
+               return -1;
+       }
+
+       bus->read = dw_mdio_read;
+       bus->write = dw_mdio_write;
+       sprintf(bus->name, name);
+
+       bus->priv = (void *)mac_regs_p;
+
+       return mdio_register(bus);
+}
 
 static void tx_descs_init(struct eth_device *dev)
 {
@@ -51,7 +119,13 @@ static void tx_descs_init(struct eth_device *dev)
        /* Correcting the last pointer of the chain */
        desc_p->dmamac_next = &desc_table_p[0];
 
+       /* Flush all Tx buffer descriptors at once */
+       flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
+                          (unsigned int)priv->tx_mac_descrtable +
+                          sizeof(priv->tx_mac_descrtable));
+
        writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+       priv->tx_currdescnum = 0;
 }
 
 static void rx_descs_init(struct eth_device *dev)
@@ -63,6 +137,15 @@ static void rx_descs_init(struct eth_device *dev)
        struct dmamacdescr *desc_p;
        u32 idx;
 
+       /* Before passing buffers to GMAC we need to make sure zeros
+        * written there right after "priv" structure allocation were
+        * flushed into RAM.
+        * Otherwise there's a chance to get some of them flushed in RAM when
+        * GMAC is already pushing data to RAM via DMA. This way incoming from
+        * GMAC data will be corrupted. */
+       flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
+                          RX_TOTAL_BUFSIZE);
+
        for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
                desc_p = &desc_table_p[idx];
                desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
@@ -78,56 +161,68 @@ static void rx_descs_init(struct eth_device *dev)
        /* Correcting the last pointer of the chain */
        desc_p->dmamac_next = &desc_table_p[0];
 
+       /* Flush all Rx buffer descriptors at once */
+       flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
+                          (unsigned int)priv->rx_mac_descrtable +
+                          sizeof(priv->rx_mac_descrtable));
+
        writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+       priv->rx_currdescnum = 0;
 }
 
-static void descs_init(struct eth_device *dev)
+static int dw_write_hwaddr(struct eth_device *dev)
 {
-       tx_descs_init(dev);
-       rx_descs_init(dev);
+       struct dw_eth_dev *priv = dev->priv;
+       struct eth_mac_regs *mac_p = priv->mac_regs_p;
+       u32 macid_lo, macid_hi;
+       u8 *mac_id = &dev->enetaddr[0];
+
+       macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
+                  (mac_id[3] << 24);
+       macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+       writel(macid_hi, &mac_p->macaddr0hi);
+       writel(macid_lo, &mac_p->macaddr0lo);
+
+       return 0;
 }
 
-static int mac_reset(struct eth_device *dev)
+static void dw_adjust_link(struct eth_mac_regs *mac_p,
+                          struct phy_device *phydev)
 {
-       struct dw_eth_dev *priv = dev->priv;
-       struct eth_mac_regs *mac_p = priv->mac_regs_p;
-       struct eth_dma_regs *dma_p = priv->dma_regs_p;
+       u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
 
-       ulong start;
-       int timeout = CONFIG_MACRESET_TIMEOUT;
+       if (!phydev->link) {
+               printf("%s: No link.\n", phydev->dev->name);
+               return;
+       }
 
-       writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
+       if (phydev->speed != 1000)
+               conf |= MII_PORTSELECT;
 
-       if (priv->interface != PHY_INTERFACE_MODE_RGMII)
-               writel(MII_PORTSELECT, &mac_p->conf);
+       if (phydev->speed == 100)
+               conf |= FES_100;
 
-       start = get_timer(0);
-       while (get_timer(start) < timeout) {
-               if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
-                       return 0;
+       if (phydev->duplex)
+               conf |= FULLDPLXMODE;
 
-               /* Try again after 10usec */
-               udelay(10);
-       };
+       writel(conf, &mac_p->conf);
 
-       return -1;
+       printf("Speed: %d, %s duplex%s\n", phydev->speed,
+              (phydev->duplex) ? "full" : "half",
+              (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
 }
 
-static int dw_write_hwaddr(struct eth_device *dev)
+static void dw_eth_halt(struct eth_device *dev)
 {
        struct dw_eth_dev *priv = dev->priv;
        struct eth_mac_regs *mac_p = priv->mac_regs_p;
-       u32 macid_lo, macid_hi;
-       u8 *mac_id = &dev->enetaddr[0];
-
-       macid_lo = mac_id[0] + (mac_id[1] << 8) + \
-                  (mac_id[2] << 16) + (mac_id[3] << 24);
-       macid_hi = mac_id[4] + (mac_id[5] << 8);
+       struct eth_dma_regs *dma_p = priv->dma_regs_p;
 
-       writel(macid_hi, &mac_p->macaddr0hi);
-       writel(macid_lo, &mac_p->macaddr0lo);
+       writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
+       writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
 
-       return 0;
+       phy_shutdown(priv->phydev);
 }
 
 static int dw_eth_init(struct eth_device *dev, bd_t *bis)
@@ -135,55 +230,43 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
        struct dw_eth_dev *priv = dev->priv;
        struct eth_mac_regs *mac_p = priv->mac_regs_p;
        struct eth_dma_regs *dma_p = priv->dma_regs_p;
-       u32 conf;
+       unsigned int start;
 
-       if (priv->phy_configured != 1)
-               configure_phy(dev);
+       writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
 
-       /* Print link status only once */
-       if (!priv->link_printed) {
-               printf("ENET Speed is %d Mbps - %s duplex connection\n",
-                      priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
-               priv->link_printed = 1;
-       }
+       start = get_timer(0);
+       while (readl(&dma_p->busmode) & DMAMAC_SRST) {
+               if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
+                       return -1;
 
-       /* Reset ethernet hardware */
-       if (mac_reset(dev) < 0)
-               return -1;
+               mdelay(100);
+       };
 
-       /* Resore the HW MAC address as it has been lost during MAC reset */
+       /* Soft reset above clears HW address registers.
+        * So we have to set it here once again */
        dw_write_hwaddr(dev);
 
-       writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
-                       &dma_p->busmode);
-
-       writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
-               TXSECONDFRAME, &dma_p->opmode);
+       rx_descs_init(dev);
+       tx_descs_init(dev);
 
-       conf = FRAMEBURSTENABLE | DISABLERXOWN;
+       writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
 
-       if (priv->speed != 1000)
-               conf |= MII_PORTSELECT;
+       writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
+              &dma_p->opmode);
 
-       if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
-               (priv->interface != PHY_INTERFACE_MODE_GMII)) {
+       writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
 
-               if (priv->speed == 100)
-                       conf |= FES_100;
+       /* Start up the PHY */
+       if (phy_startup(priv->phydev)) {
+               printf("Could not initialize PHY %s\n",
+                      priv->phydev->dev->name);
+               return -1;
        }
 
-       if (priv->duplex == FULL)
-               conf |= FULLDPLXMODE;
-
-       writel(conf, &mac_p->conf);
-
-       descs_init(dev);
+       dw_adjust_link(mac_p, priv->phydev);
 
-       /*
-        * Start/Enable xfer at dma as well as mac level
-        */
-       writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
-       writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
+       if (!priv->phydev->link)
+               return -1;
 
        writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
 
@@ -197,6 +280,11 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
        u32 desc_num = priv->tx_currdescnum;
        struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
 
+       /* Invalidate only "status" field for the following check */
+       invalidate_dcache_range((unsigned long)&desc_p->txrx_status,
+                               (unsigned long)&desc_p->txrx_status +
+                               sizeof(desc_p->txrx_status));
+
        /* Check if the descriptor is owned by CPU */
        if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
                printf("CPU not owner of tx frame\n");
@@ -205,6 +293,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 
        memcpy((void *)desc_p->dmamac_addr, packet, length);
 
+       /* Flush data to be sent */
+       flush_dcache_range((unsigned long)desc_p->dmamac_addr,
+                          (unsigned long)desc_p->dmamac_addr + length);
+
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
        desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
        desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
@@ -220,6 +312,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
        desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
 #endif
 
+       /* Flush modified buffer descriptor */
+       flush_dcache_range((unsigned long)desc_p,
+                          (unsigned long)desc_p + sizeof(struct dmamacdescr));
+
        /* Test the wrap-around condition. */
        if (++desc_num >= CONFIG_TX_DESCR_NUM)
                desc_num = 0;
@@ -235,18 +331,28 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length)
 static int dw_eth_recv(struct eth_device *dev)
 {
        struct dw_eth_dev *priv = dev->priv;
-       u32 desc_num = priv->rx_currdescnum;
+       u32 status, desc_num = priv->rx_currdescnum;
        struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
-
-       u32 status = desc_p->txrx_status;
        int length = 0;
 
+       /* Invalidate entire buffer descriptor */
+       invalidate_dcache_range((unsigned long)desc_p,
+                               (unsigned long)desc_p +
+                               sizeof(struct dmamacdescr));
+
+       status = desc_p->txrx_status;
+
        /* Check  if the owner is the CPU */
        if (!(status & DESC_RXSTS_OWNBYDMA)) {
 
                length = (status & DESC_RXSTS_FRMLENMSK) >> \
                         DESC_RXSTS_FRMLENSHFT;
 
+               /* Invalidate received data */
+               invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
+                                       (unsigned long)desc_p->dmamac_addr +
+                                       length);
+
                NetReceive(desc_p->dmamac_addr, length);
 
                /*
@@ -255,6 +361,11 @@ static int dw_eth_recv(struct eth_device *dev)
                 */
                desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
 
+               /* Flush only status field - others weren't changed */
+               flush_dcache_range((unsigned long)&desc_p->txrx_status,
+                                  (unsigned long)&desc_p->txrx_status +
+                                  sizeof(desc_p->txrx_status));
+
                /* Test the wrap-around condition. */
                if (++desc_num >= CONFIG_RX_DESCR_NUM)
                        desc_num = 0;
@@ -265,251 +376,30 @@ static int dw_eth_recv(struct eth_device *dev)
        return length;
 }
 
-static void dw_eth_halt(struct eth_device *dev)
-{
-       struct dw_eth_dev *priv = dev->priv;
-
-       mac_reset(dev);
-       priv->tx_currdescnum = priv->rx_currdescnum = 0;
-}
-
-static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
-{
-       struct dw_eth_dev *priv = dev->priv;
-       struct eth_mac_regs *mac_p = priv->mac_regs_p;
-       ulong start;
-       u32 miiaddr;
-       int timeout = CONFIG_MDIO_TIMEOUT;
-
-       miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
-                 ((reg << MIIREGSHIFT) & MII_REGMSK);
-
-       writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
-
-       start = get_timer(0);
-       while (get_timer(start) < timeout) {
-               if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
-                       *val = readl(&mac_p->miidata);
-                       return 0;
-               }
-
-               /* Try again after 10usec */
-               udelay(10);
-       };
-
-       return -1;
-}
-
-static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
+static int dw_phy_init(struct eth_device *dev)
 {
        struct dw_eth_dev *priv = dev->priv;
-       struct eth_mac_regs *mac_p = priv->mac_regs_p;
-       ulong start;
-       u32 miiaddr;
-       int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
-       u16 value;
-
-       writel(val, &mac_p->miidata);
-       miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
-                 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
-
-       writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
-
-       start = get_timer(0);
-       while (get_timer(start) < timeout) {
-               if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
-                       ret = 0;
-                       break;
-               }
+       struct phy_device *phydev;
+       int mask = 0xffffffff;
 
-               /* Try again after 10usec */
-               udelay(10);
-       };
-
-       /* Needed as a fix for ST-Phy */
-       eth_mdio_read(dev, addr, reg, &value);
-
-       return ret;
-}
-
-#if defined(CONFIG_DW_SEARCH_PHY)
-static int find_phy(struct eth_device *dev)
-{
-       int phy_addr = 0;
-       u16 ctrl, oldctrl;
-
-       do {
-               eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
-               oldctrl = ctrl & BMCR_ANENABLE;
-
-               ctrl ^= BMCR_ANENABLE;
-               eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
-               eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
-               ctrl &= BMCR_ANENABLE;
-
-               if (ctrl == oldctrl) {
-                       phy_addr++;
-               } else {
-                       ctrl ^= BMCR_ANENABLE;
-                       eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
-
-                       return phy_addr;
-               }
-       } while (phy_addr < 32);
-
-       return -1;
-}
+#ifdef CONFIG_PHY_ADDR
+       mask = 1 << CONFIG_PHY_ADDR;
 #endif
 
-static int dw_reset_phy(struct eth_device *dev)
-{
-       struct dw_eth_dev *priv = dev->priv;
-       u16 ctrl;
-       ulong start;
-       int timeout = CONFIG_PHYRESET_TIMEOUT;
-       u32 phy_addr = priv->address;
-
-       eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
-
-       start = get_timer(0);
-       while (get_timer(start) < timeout) {
-               eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
-               if (!(ctrl & BMCR_RESET))
-                       break;
-
-               /* Try again after 10usec */
-               udelay(10);
-       };
-
-       if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
+       phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
+       if (!phydev)
                return -1;
 
-#ifdef CONFIG_PHY_RESET_DELAY
-       udelay(CONFIG_PHY_RESET_DELAY);
-#endif
-       return 0;
-}
+       phydev->supported &= PHY_GBIT_FEATURES;
+       phydev->advertising = phydev->supported;
 
-/*
- * Add weak default function for board specific PHY configuration
- */
-int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
-               int (*mii_write)(struct eth_device *, u8, u8, u16),
-               int dw_reset_phy(struct eth_device *))
-{
-       return 0;
-}
-
-static int configure_phy(struct eth_device *dev)
-{
-       struct dw_eth_dev *priv = dev->priv;
-       int phy_addr;
-       u16 bmcr;
-#if defined(CONFIG_DW_AUTONEG)
-       u16 bmsr;
-       u32 timeout;
-       ulong start;
-#endif
-
-#if defined(CONFIG_DW_SEARCH_PHY)
-       phy_addr = find_phy(dev);
-       if (phy_addr >= 0)
-               priv->address = phy_addr;
-       else
-               return -1;
-#else
-       phy_addr = priv->address;
-#endif
-
-       /*
-        * Some boards need board specific PHY initialization. This is
-        * after the main driver init code but before the auto negotiation
-        * is run.
-        */
-       if (designware_board_phy_init(dev, phy_addr,
-                                     eth_mdio_write, dw_reset_phy) < 0)
-               return -1;
-
-       if (dw_reset_phy(dev) < 0)
-               return -1;
-
-#if defined(CONFIG_DW_AUTONEG)
-       /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
-       eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
-
-       bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
-#else
-       bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
-
-#if defined(CONFIG_DW_SPEED10M)
-       bmcr &= ~BMCR_SPEED100;
-#endif
-#if defined(CONFIG_DW_DUPLEXHALF)
-       bmcr &= ~BMCR_FULLDPLX;
-#endif
-#endif
-       if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
-               return -1;
-
-       /* Read the phy status register and populate priv structure */
-#if defined(CONFIG_DW_AUTONEG)
-       timeout = CONFIG_AUTONEG_TIMEOUT;
-       start = get_timer(0);
-       puts("Waiting for PHY auto negotiation to complete");
-       while (get_timer(start) < timeout) {
-               eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
-               if (bmsr & BMSR_ANEGCOMPLETE) {
-                       priv->phy_configured = 1;
-                       break;
-               }
+       priv->phydev = phydev;
+       phy_config(phydev);
 
-               /* Print dot all 1s to show progress */
-               if ((get_timer(start) % 1000) == 0)
-                       putc('.');
-
-               /* Try again after 1msec */
-               udelay(1000);
-       };
-
-       if (!(bmsr & BMSR_ANEGCOMPLETE))
-               puts(" TIMEOUT!\n");
-       else
-               puts(" done\n");
-#else
-       priv->phy_configured = 1;
-#endif
-
-       priv->speed = miiphy_speed(dev->name, phy_addr);
-       priv->duplex = miiphy_duplex(dev->name, phy_addr);
-
-       return 0;
-}
-
-#if defined(CONFIG_MII)
-static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
-{
-       struct eth_device *dev;
-
-       dev = eth_get_dev_by_name(devname);
-       if (dev)
-               eth_mdio_read(dev, addr, reg, val);
-
-       return 0;
-}
-
-static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
-{
-       struct eth_device *dev;
-
-       dev = eth_get_dev_by_name(devname);
-       if (dev)
-               eth_mdio_write(dev, addr, reg, val);
-
-       return 0;
+       return 1;
 }
-#endif
 
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
+int designware_initialize(ulong base_addr, u32 interface)
 {
        struct eth_device *dev;
        struct dw_eth_dev *priv;
@@ -531,19 +421,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
        memset(dev, 0, sizeof(struct eth_device));
        memset(priv, 0, sizeof(struct dw_eth_dev));
 
-       sprintf(dev->name, "mii%d", id);
+       sprintf(dev->name, "dwmac.%lx", base_addr);
        dev->iobase = (int)base_addr;
        dev->priv = priv;
 
-       eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
-
        priv->dev = dev;
        priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
        priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
                        DW_DMA_BASE_OFFSET);
-       priv->address = phy_addr;
-       priv->phy_configured = 0;
-       priv->interface = interface;
 
        dev->init = dw_eth_init;
        dev->send = dw_eth_send;
@@ -553,8 +438,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
 
        eth_register(dev);
 
-#if defined(CONFIG_MII)
-       miiphy_register(dev->name, dw_mii_read, dw_mii_write);
-#endif
-       return 1;
+       priv->interface = interface;
+
+       dw_mdio_init(dev->name, priv->mac_regs_p);
+       priv->bus = miiphy_get_dev_by_name(dev->name);
+
+       return dw_phy_init(dev);
 }
index 5440c92..afeacce 100644 (file)
@@ -16,8 +16,6 @@
 
 #define CONFIG_MACRESET_TIMEOUT        (3 * CONFIG_SYS_HZ)
 #define CONFIG_MDIO_TIMEOUT    (3 * CONFIG_SYS_HZ)
-#define CONFIG_PHYRESET_TIMEOUT        (3 * CONFIG_SYS_HZ)
-#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
 
 struct eth_mac_regs {
        u32 conf;               /* 0x00 */
@@ -217,14 +215,9 @@ struct dmamacdescr {
 #endif
 
 struct dw_eth_dev {
-       u32 address;
        u32 interface;
-       u32 speed;
-       u32 duplex;
        u32 tx_currdescnum;
        u32 rx_currdescnum;
-       u32 phy_configured;
-       u32 link_printed;
 
        struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
        struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
@@ -236,15 +229,8 @@ struct dw_eth_dev {
        struct eth_dma_regs *dma_regs_p;
 
        struct eth_device *dev;
+       struct phy_device *phydev;
+       struct mii_dev *bus;
 };
 
-/* Speed specific definitions */
-#define SPEED_10M              1
-#define SPEED_100M             2
-#define SPEED_1000M            3
-
-/* Duplex mode specific definitions */
-#define HALF_DUPLEX            1
-#define FULL_DUPLEX            2
-
 #endif
index 6b4cade..5eb4601 100644 (file)
@@ -34,6 +34,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
 obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
+obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
index df2b84a..05cb369 100644 (file)
@@ -160,6 +160,7 @@ serial_initfunc(sa1100_serial_initialize);
 serial_initfunc(sh_serial_initialize);
 serial_initfunc(arm_dcc_initialize);
 serial_initfunc(mxs_auart_initialize);
+serial_initfunc(arc_serial_initialize);
 
 /**
  * serial_register() - Register serial driver with serial driver core
@@ -253,6 +254,7 @@ void serial_initialize(void)
        sh_serial_initialize();
        arm_dcc_initialize();
        mxs_auart_initialize();
+       arc_serial_initialize();
 
        serial_assign(default_serial_console()->name);
 }
diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c
new file mode 100644 (file)
index 0000000..e63d25d
--- /dev/null
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arc_serial_regs {
+       unsigned int id0;
+       unsigned int id1;
+       unsigned int id2;
+       unsigned int id3;
+       unsigned int data;
+       unsigned int status;
+       unsigned int baudl;
+       unsigned int baudh;
+};
+
+/* Bit definitions of STATUS register */
+#define UART_RXEMPTY           (1 << 5)
+#define UART_OVERFLOW_ERR      (1 << 1)
+#define UART_TXEMPTY           (1 << 7)
+
+struct arc_serial_regs *regs;
+
+static void arc_serial_setbrg(void)
+{
+       int arc_console_baud;
+
+       if (!gd->baudrate)
+               gd->baudrate = CONFIG_BAUDRATE;
+
+       arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1;
+       writel(arc_console_baud & 0xff, &regs->baudl);
+       writel((arc_console_baud & 0xff00) >> 8, &regs->baudh);
+}
+
+static int arc_serial_init(void)
+{
+       regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE;
+       serial_setbrg();
+       return 0;
+}
+
+static void arc_serial_putc(const char c)
+{
+       if (c == '\n')
+               arc_serial_putc('\r');
+
+       while (!(readl(&regs->status) & UART_TXEMPTY))
+               ;
+
+       writel(c, &regs->data);
+}
+
+static int arc_serial_tstc(void)
+{
+       return !(readl(&regs->status) & UART_RXEMPTY);
+}
+
+static int arc_serial_getc(void)
+{
+       while (!arc_serial_tstc())
+               ;
+
+       /* Check for overflow errors */
+       if (readl(&regs->status) & UART_OVERFLOW_ERR)
+               return 0;
+
+       return readl(&regs->data) & 0xFF;
+}
+
+static void arc_serial_puts(const char *s)
+{
+       while (*s)
+               arc_serial_putc(*s++);
+}
+
+static struct serial_device arc_serial_drv = {
+       .name   = "arc_serial",
+       .start  = arc_serial_init,
+       .stop   = NULL,
+       .setbrg = arc_serial_setbrg,
+       .putc   = arc_serial_putc,
+       .puts   = arc_serial_puts,
+       .getc   = arc_serial_getc,
+       .tstc   = arc_serial_tstc,
+};
+
+void arc_serial_initialize(void)
+{
+       serial_register(&arc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+       return &arc_serial_drv;
+}
index 32a19ce..c5c025d 100644 (file)
@@ -210,6 +210,19 @@ gd_t *global_data;
 "      l.jr    r13\n"          \
 "      l.nop\n"                                \
        : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r13");
+#elif defined(CONFIG_ARC)
+/*
+ * r25 holds the pointer to the global_data. r10 is call clobbered.
+  */
+#define EXPORT_FUNC(x) \
+       asm volatile( \
+"      .align 4\n" \
+"      .globl " #x "\n" \
+#x ":\n" \
+"      ld      r10, [r25, %0]\n" \
+"      ld      r10, [r10, %1]\n" \
+"      j       [r10]\n" \
+       : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r10");
 #else
 /*"    addi    $sp, $sp, -24\n"        \
 "      br      $r16\n"                 \*/
index d5ebb25..221b776 100644 (file)
@@ -408,6 +408,9 @@ static inline int setenv_addr(const char *varname, const void *addr)
 #ifdef CONFIG_MIPS
 # include <asm/u-boot-mips.h>
 #endif /* CONFIG_MIPS */
+#ifdef CONFIG_ARC
+# include <asm/u-boot-arc.h>
+#endif /* CONFIG_ARC */
 
 #ifdef CONFIG_AUTO_COMPLETE
 int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
diff --git a/include/configs/arcangel4-be.h b/include/configs/arcangel4-be.h
new file mode 100644 (file)
index 0000000..88d27db
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_SYS_BIG_ENDIAN
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER             3
+#define CONFIG_SYS_CACHELINE_SIZE      64
+#define CONFIG_SYS_CLK_FREQ            70000000
+#define CONFIG_SYS_TIMER_RATE          CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT      /* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE           0x81000000
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE          0x10000000      /* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR                \
+       (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN          0x200000        /* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN           0x2000000       /* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR           0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE           0xC0FC1000
+#define CONFIG_BAUDRATE                        115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS             16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE                        0x00200         /* 512 bytes */
+#define CONFIG_ENV_OFFSET              0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTFILE                        "uImage"
+#define CONFIG_BOOTARGS                        "console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT              "arcangel4# "
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                               sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
new file mode 100644 (file)
index 0000000..4579eb9
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CONFIG_ARCANGEL4_H_
+#define _CONFIG_ARCANGEL4_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER             3
+#define CONFIG_SYS_CACHELINE_SIZE      64
+#define CONFIG_SYS_CLK_FREQ            70000000
+#define CONFIG_SYS_TIMER_RATE          CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT      /* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE           0x81000000
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE          0x10000000      /* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR                \
+       (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN          0x200000        /* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN           0x2000000       /* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR           0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ *
+ */
+#define CONFIG_ARC_SERIAL
+#define CONFIG_ARC_UART_BASE           0xC0FC1000
+#define CONFIG_BAUDRATE                        115200
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS             16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE                        0x00200         /* 512 bytes */
+#define CONFIG_ENV_OFFSET              0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTFILE                        "uImage"
+#define CONFIG_BOOTARGS                        "console=ttyARC0,115200n8"
+#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT              "arcangel4# "
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                               sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_ARCANGEL4_H_ */
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
new file mode 100644 (file)
index 0000000..af2e63b
--- /dev/null
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _CONFIG_AXS101_H_
+#define _CONFIG_AXS101_H_
+
+/*
+ *  CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER             3
+#define CONFIG_SYS_CACHELINE_SIZE      32
+#define CONFIG_SYS_CLK_FREQ            750000000
+#define CONFIG_SYS_TIMER_RATE          CONFIG_SYS_CLK_FREQ
+
+/* dwgmac doesn't work with D$ enabled now */
+#define CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SKIP_LOWLEVEL_INIT      /* U-Boot is in RAM already */
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define ARC_FPGA_PERIPHERAL_BASE       0xE0000000
+#define ARC_APB_PERIPHERAL_BASE                0xF0000000
+#define ARC_DWMMC_BASE                 (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
+#define ARC_DWGMAC_BASE                        (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE           0x81000000
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE          0x10000000      /* 256 Mb */
+
+#define CONFIG_SYS_INIT_SP_ADDR                \
+       (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN          0x200000        /* 2 MB */
+#define CONFIG_SYS_BOOTM_LEN           0x2000000       /* 32 MB */
+#define CONFIG_SYS_LOAD_ADDR           0x82000000
+
+/*
+ * NAND Flash configuration
+ */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_NAND_BASE           (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+
+/*
+ * UART configuration
+ *
+ * CONFIG_CONS_INDEX = 1 - Debug UART
+ * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
+ */
+#define CONFIG_CONS_INDEX              4
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    -4
+#if (CONFIG_CONS_INDEX == 1)
+       /* Debug UART */
+#      define CONFIG_SYS_NS16550_CLK           33333000
+#else
+       /* FPGA UARTs use different clock */
+#      define CONFIG_SYS_NS16550_CLK           33333333
+#endif
+#define CONFIG_SYS_NS16550_COM1                (ARC_APB_PERIPHERAL_BASE + 0x5000)
+#define CONFIG_SYS_NS16550_COM2                (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
+#define CONFIG_SYS_NS16550_COM3                (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
+#define CONFIG_SYS_NS16550_COM4                (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_BAUDRATE                        115200
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_DW_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_ENV_EEPROM_BUS      2
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_SYS_I2C_SLAVE           0
+#define CONFIG_SYS_I2C_BASE            0xE001D000
+#define CONFIG_SYS_I2C_BASE1           0xE001E000
+#define CONFIG_SYS_I2C_BASE2           0xE001F000
+#define CONFIG_SYS_I2C_BUS_MAX         3
+#define IC_CLK                         50
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_MULTI_EEPROMS
+#define CONFIG_SYS_I2C_EEPROM_ADDR             (0xA8 >> 1)
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
+#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW    1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  32
+
+/*
+ * SD/MMC configuration
+ */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Ethernet PHY configuration
+ */
+#define CONFIG_PHYLIB
+#define CONFIG_MII
+#define CONFIG_PHY_GIGE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_AUTONEG
+#define CONFIG_DW_SEARCH_PHY
+#define CONFIG_NET_MULTI
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RARP
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS             16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_EEPROM
+#define CONFIG_ENV_SIZE                        0x00200         /* 512 bytes */
+#define CONFIG_ENV_OFFSET              0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTFILE                        "uImage"
+#define CONFIG_BOOTARGS                        "console=ttyS3,115200n8"
+#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT              "axs# "
+#define CONFIG_SYS_CBSIZE              256
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                               sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Misc utility configuration
+ */
+#define CONFIG_BOUNCE_BUFFER
+
+#endif /* _CONFIG_AXS101_H_ */
index 1a43e1b..12192ff 100644 (file)
 #define CONFIG_NET_MULTI
 #define CONFIG_HOSTNAME                "bf609-ezkit"
 #define CONFIG_DESIGNWARE_ETH
+#define CONFIG_PHY_ADDR                1
 #define CONFIG_DW_PORTS                1
-#define CONFIG_DW_AUTONEG
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
 #define CONFIG_MII
+#define CONFIG_PHYLIB
 
 /* i2c Settings */
 #define CONFIG_BFIN_TWI_I2C
index 23f7ad7..e090a37 100644 (file)
 /* Ethernet driver configuration */
 #define CONFIG_MII
 #define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_SEARCH_PHY
-#define CONFIG_DW0_PHY                         1
 #define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY                 10000           /* in usec */
-#define CONFIG_DW_AUTONEG
 #define CONFIG_PHY_GIGE                        /* Include GbE speed/duplex detection */
 
 /* USBD driver configuration */
index 7f4dc58..28dddcc 100644 (file)
@@ -37,6 +37,9 @@
 #define CONFIG_SYS_FSMC_NAND_8BIT
 #define CONFIG_SYS_NAND_BASE                   0xD2000000
 
+/* Ethernet PHY configuration */
+#define CONFIG_PHY_NATSEMI
+
 /* Environment Settings */
 #define CONFIG_EXTRA_ENV_SETTINGS              CONFIG_EXTRA_ENV_USBTTY
 
index 39540e3..00b938a 100644 (file)
 /* Ethernet config options */
 #define CONFIG_MII
 #define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_SEARCH_PHY
 #define CONFIG_NET_MULTI
+#define CONFIG_PHYLIB
 #define CONFIG_PHY_RESET_DELAY                 10000           /* in usec */
-#define CONFIG_DW_AUTONEG
 #define CONFIG_PHY_ADDR                0       /* PHY address */
 #define CONFIG_PHY_GIGE                        /* Include GbE speed/duplex detection */
 
index 7de2bb2..3ba8c2e 100644 (file)
@@ -157,6 +157,7 @@ struct lmb;
 #define IH_ARCH_NDS32          20      /* ANDES Technology - NDS32  */
 #define IH_ARCH_OPENRISC        21     /* OpenRISC 1000  */
 #define IH_ARCH_ARM64          22      /* ARM64        */
+#define IH_ARCH_ARC            23      /* Synopsys DesignWare ARC */
 
 /*
  * Image Types
index 47fa80d..3705629 100644 (file)
@@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr);
 int cs8900_initialize(u8 dev_num, int base_addr);
 int davinci_emac_initialize(void);
 int dc21x4x_initialize(bd_t *bis);
-int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface);
+int designware_initialize(ulong base_addr, u32 interface);
 int dm9000_initialize(bd_t *bis);
 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int e1000_initialize(bd_t *bis);
index c96e767..32bd10c 100644 (file)
--- a/net/eth.c
+++ b/net/eth.c
@@ -279,7 +279,7 @@ int eth_initialize(bd_t *bis)
        eth_current = NULL;
 
        bootstage_mark(BOOTSTAGE_ID_NET_ETH_START);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
        miiphy_init();
 #endif