Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 21 Sep 2014 14:56:44 +0000 (16:56 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 21 Sep 2014 14:56:44 +0000 (16:56 +0200)
840 files changed:
Licenses/README
Licenses/isc.txt [new file with mode: 0644]
Makefile
arch/Kconfig
arch/arc/Kconfig
arch/arm/Kconfig
arch/arm/cpu/arm926ejs/davinci/Kconfig
arch/arm/cpu/arm926ejs/kirkwood/Kconfig
arch/arm/cpu/arm926ejs/nomadik/Kconfig
arch/arm/cpu/arm926ejs/orion5x/Kconfig
arch/arm/cpu/arm926ejs/versatile/Kconfig
arch/arm/cpu/armv7/at91/clock.c
arch/arm/cpu/armv7/exynos/Kconfig
arch/arm/cpu/armv7/highbank/Kconfig
arch/arm/cpu/armv7/keystone/Kconfig
arch/arm/cpu/armv7/ls102xa/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/clock.c [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/cpu.c [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/fdt.c [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c [new file with mode: 0644]
arch/arm/cpu/armv7/ls102xa/timer.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap3/Kconfig
arch/arm/cpu/armv7/omap4/Kconfig
arch/arm/cpu/armv7/omap5/Kconfig
arch/arm/cpu/armv7/rmobile/Kconfig
arch/arm/cpu/armv7/tegra-common/Kconfig
arch/arm/cpu/armv7/tegra114/Kconfig
arch/arm/cpu/armv7/tegra124/Kconfig
arch/arm/cpu/armv7/tegra20/Kconfig
arch/arm/cpu/armv7/tegra30/Kconfig
arch/arm/cpu/armv7/zynq/Kconfig
arch/arm/cpu/armv8/Kconfig [new file with mode: 0644]
arch/arm/dts/tegra114-dalmore.dts
arch/arm/dts/tegra114.dtsi
arch/arm/dts/tegra124-jetson-tk1.dts
arch/arm/dts/tegra124-venice2.dts
arch/arm/dts/tegra124.dtsi
arch/arm/dts/tegra20-colibri_t20_iris.dts
arch/arm/dts/tegra20-harmony.dts
arch/arm/dts/tegra20-medcom-wide.dts
arch/arm/dts/tegra20-paz00.dts
arch/arm/dts/tegra20-plutux.dts
arch/arm/dts/tegra20-seaboard.dts
arch/arm/dts/tegra20-tec.dts
arch/arm/dts/tegra20-trimslice.dts
arch/arm/dts/tegra20-ventana.dts
arch/arm/dts/tegra20-whistler.dts
arch/arm/dts/tegra20.dtsi
arch/arm/dts/tegra30-beaver.dts
arch/arm/dts/tegra30-cardhu.dts
arch/arm/dts/tegra30-tamonten.dtsi
arch/arm/dts/tegra30.dtsi
arch/arm/include/asm/arch-at91/at91_pmc.h
arch/arm/include/asm/arch-at91/clk.h
arch/arm/include/asm/arch-at91/sama5d3.h
arch/arm/include/asm/arch-at91/sama5d3_smc.h
arch/arm/include/asm/arch-ls102xa/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-ls102xa/config.h [new file with mode: 0644]
arch/arm/include/asm/arch-ls102xa/fsl_serdes.h [new file with mode: 0644]
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h [new file with mode: 0644]
arch/arm/include/asm/arch-ls102xa/imx-regs.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra/gpio.h
arch/arm/include/asm/config.h
arch/arm/include/asm/io.h
arch/arm/lib/spl.c
arch/avr32/Kconfig
arch/blackfin/Kconfig
arch/m68k/Kconfig
arch/microblaze/Kconfig
arch/microblaze/include/asm/posix_types.h
arch/mips/Kconfig
arch/nds32/Kconfig
arch/nios2/Kconfig
arch/openrisc/Kconfig
arch/powerpc/Kconfig
arch/powerpc/cpu/74xx_7xx/Kconfig
arch/powerpc/cpu/mpc512x/Kconfig
arch/powerpc/cpu/mpc5xx/Kconfig
arch/powerpc/cpu/mpc5xxx/Kconfig
arch/powerpc/cpu/mpc824x/Kconfig
arch/powerpc/cpu/mpc8260/Kconfig
arch/powerpc/cpu/mpc83xx/Kconfig
arch/powerpc/cpu/mpc85xx/Kconfig
arch/powerpc/cpu/mpc86xx/Kconfig
arch/powerpc/cpu/mpc8xx/Kconfig
arch/powerpc/cpu/ppc4xx/Kconfig
arch/powerpc/include/asm/fsl_enet.h [deleted file]
arch/sandbox/Kconfig
arch/sandbox/dts/sandbox.dts
arch/sh/Kconfig
arch/sparc/Kconfig
arch/x86/Kconfig
board/8dtech/eco5pk/Kconfig
board/AndesTech/adp-ag101/Kconfig
board/AndesTech/adp-ag101p/Kconfig
board/AndesTech/adp-ag102/Kconfig
board/Barix/ipam390/Kconfig
board/BuR/kwb/Kconfig
board/BuR/tseries/Kconfig
board/BuS/eb_cpu5282/Kconfig
board/BuS/eb_cpux9k2/Kconfig
board/BuS/vl_ma2sc/Kconfig
board/CarMediaLab/flea3/Kconfig
board/LEOX/elpt860/Kconfig
board/LaCie/edminiv2/Kconfig
board/LaCie/net2big_v2/Kconfig
board/LaCie/netspace_v2/Kconfig
board/LaCie/wireless_space/Kconfig
board/Marvell/aspenite/Kconfig
board/Marvell/db64360/Kconfig
board/Marvell/db64460/Kconfig
board/Marvell/dkb/Kconfig
board/Marvell/dreamplug/Kconfig
board/Marvell/gplugd/Kconfig
board/Marvell/guruplug/Kconfig
board/Marvell/mv88f6281gtw_ge/Kconfig
board/Marvell/openrd/Kconfig
board/Marvell/rd6281a/Kconfig
board/Marvell/sheevaplug/Kconfig
board/RRvision/Kconfig
board/Seagate/dockstar/Kconfig
board/Seagate/goflexhome/Kconfig
board/a3000/Kconfig
board/a3m071/Kconfig
board/a4m072/Kconfig
board/abilis/tb100/Kconfig
board/afeb9260/Kconfig
board/ait/cam_enc_4xx/Kconfig
board/alphaproject/ap_sh4a_4a/Kconfig
board/altera/nios2-generic/Kconfig
board/altera/socfpga/Kconfig
board/amcc/acadia/Kconfig
board/amcc/bamboo/Kconfig
board/amcc/bluestone/Kconfig
board/amcc/bubinga/Kconfig
board/amcc/canyonlands/Kconfig
board/amcc/ebony/Kconfig
board/amcc/katmai/Kconfig
board/amcc/kilauea/Kconfig
board/amcc/luan/Kconfig
board/amcc/makalu/Kconfig
board/amcc/ocotea/Kconfig
board/amcc/redwood/Kconfig
board/amcc/sequoia/Kconfig
board/amcc/taihu/Kconfig
board/amcc/taishan/Kconfig
board/amcc/walnut/Kconfig
board/amcc/yosemite/Kconfig
board/amcc/yucca/Kconfig
board/aristainetos/Kconfig
board/armadeus/apf27/Kconfig
board/armltd/integrator/Kconfig
board/armltd/vexpress/Kconfig
board/armltd/vexpress64/Kconfig
board/astro/mcf5373l/Kconfig
board/atc/Kconfig
board/atmark-techno/armadillo-800eva/Kconfig
board/atmel/at91rm9200ek/Kconfig
board/atmel/at91sam9260ek/Kconfig
board/atmel/at91sam9261ek/Kconfig
board/atmel/at91sam9263ek/Kconfig
board/atmel/at91sam9m10g45ek/Kconfig
board/atmel/at91sam9n12ek/Kconfig
board/atmel/at91sam9rlek/Kconfig
board/atmel/at91sam9x5ek/Kconfig
board/atmel/atngw100/Kconfig
board/atmel/atngw100mkii/Kconfig
board/atmel/atstk1000/Kconfig
board/atmel/sama5d3_xplained/Kconfig
board/atmel/sama5d3xek/Kconfig
board/atmel/sama5d3xek/sama5d3xek.c
board/avionic-design/medcom-wide/Kconfig
board/avionic-design/plutux/Kconfig
board/avionic-design/tec-ng/Kconfig
board/avionic-design/tec/Kconfig
board/avnet/fx12mm/Kconfig
board/avnet/v5fx30teval/Kconfig
board/balloon3/Kconfig
board/barco/titanium/Kconfig
board/bc3450/Kconfig
board/bct-brettl2/Kconfig
board/bf506f-ezkit/Kconfig
board/bf518f-ezbrd/Kconfig
board/bf525-ucr2/Kconfig
board/bf526-ezbrd/Kconfig
board/bf527-ad7160-eval/Kconfig
board/bf527-ezkit/Kconfig
board/bf527-sdp/Kconfig
board/bf533-ezkit/Kconfig
board/bf533-stamp/Kconfig
board/bf537-minotaur/Kconfig
board/bf537-pnav/Kconfig
board/bf537-srv1/Kconfig
board/bf537-stamp/Kconfig
board/bf538f-ezkit/Kconfig
board/bf548-ezkit/Kconfig
board/bf561-acvilon/Kconfig
board/bf561-ezkit/Kconfig
board/bf609-ezkit/Kconfig
board/blackstamp/Kconfig
board/blackvme/Kconfig
board/bluegiga/apx4devkit/Kconfig
board/bluewater/snapper9260/Kconfig
board/boundary/nitrogen6x/Kconfig
board/br4/Kconfig
board/broadcom/bcm28155_ap/Kconfig
board/broadcom/bcm958300k/Kconfig
board/broadcom/bcm958622hr/Kconfig
board/buffalo/lsxl/Kconfig
board/calao/sbc35_a9g20/Kconfig
board/calao/tny_a9260/Kconfig
board/calao/usb_a9263/Kconfig
board/canmb/Kconfig
board/chromebook-x86/coreboot/Kconfig
board/cirrus/edb93xx/Kconfig
board/cloudengines/pogo_e02/Kconfig
board/cm-bf527/Kconfig
board/cm-bf533/Kconfig
board/cm-bf537e/Kconfig
board/cm-bf537u/Kconfig
board/cm-bf548/Kconfig
board/cm-bf561/Kconfig
board/cm4008/Kconfig
board/cm41xx/Kconfig
board/cm5200/Kconfig
board/cmi/Kconfig
board/cobra5272/Kconfig
board/cogent/Kconfig
board/comelit/dig297/Kconfig
board/compal/paz00/Kconfig
board/compulab/cm_t335/Kconfig
board/compulab/cm_t35/Kconfig
board/compulab/cm_t54/Kconfig
board/compulab/trimslice/Kconfig
board/congatec/cgtqmx6eval/Kconfig
board/corscience/tricorder/Kconfig
board/cpc45/Kconfig
board/cpu86/Kconfig
board/cpu87/Kconfig
board/cray/L1/Kconfig
board/creative/xfi3/Kconfig
board/csb272/Kconfig
board/csb472/Kconfig
board/cu824/Kconfig
board/d-link/dns325/Kconfig
board/dave/PPChameleonEVB/Kconfig
board/davedenx/aria/Kconfig
board/davedenx/qong/Kconfig
board/davinci/da8xxevm/Kconfig
board/davinci/dm355evm/Kconfig
board/davinci/dm355leopard/Kconfig
board/davinci/dm365evm/Kconfig
board/davinci/dm6467evm/Kconfig
board/davinci/dvevm/Kconfig
board/davinci/ea20/Kconfig
board/davinci/schmoogie/Kconfig
board/davinci/sffsdr/Kconfig
board/davinci/sonata/Kconfig
board/dbau1x00/Kconfig
board/denx/m28evk/Kconfig
board/denx/m53evk/Kconfig
board/dnp5370/Kconfig
board/eXalion/Kconfig
board/earthlcd/favr-32-ezkit/Kconfig
board/egnite/ethernut5/Kconfig
board/eltec/elppc/Kconfig
board/eltec/mhpc/Kconfig
board/embest/mx6boards/Kconfig
board/emk/top5200/Kconfig
board/emk/top860/Kconfig
board/emk/top9000/Kconfig
board/enbw/enbw_cmc/Kconfig
board/ep8260/Kconfig
board/ep82xxm/Kconfig
board/esd/apc405/Kconfig
board/esd/ar405/Kconfig
board/esd/ash405/Kconfig
board/esd/cms700/Kconfig
board/esd/cpci2dp/Kconfig
board/esd/cpci405/Kconfig
board/esd/cpci5200/Kconfig
board/esd/cpci750/Kconfig
board/esd/cpciiser4/Kconfig
board/esd/dp405/Kconfig
board/esd/du405/Kconfig
board/esd/du440/Kconfig
board/esd/hh405/Kconfig
board/esd/hub405/Kconfig
board/esd/mecp5123/Kconfig
board/esd/mecp5200/Kconfig
board/esd/meesc/Kconfig
board/esd/ocrtc/Kconfig
board/esd/otc570/Kconfig
board/esd/pci405/Kconfig
board/esd/pf5200/Kconfig
board/esd/plu405/Kconfig
board/esd/pmc405/Kconfig
board/esd/pmc405de/Kconfig
board/esd/pmc440/Kconfig
board/esd/tasreg/Kconfig
board/esd/vme8349/Kconfig
board/esd/voh405/Kconfig
board/esd/vom405/Kconfig
board/esd/wuh405/Kconfig
board/esg/ima3-mx53/Kconfig
board/espt/Kconfig
board/esteem192e/Kconfig
board/eukrea/cpu9260/Kconfig
board/eukrea/cpuat91/Kconfig
board/evb64260/Kconfig
board/exmeritus/hww1u1a/Kconfig
board/faraday/a320evb/Kconfig
board/freescale/b4860qds/Kconfig
board/freescale/bsc9131rdb/Kconfig
board/freescale/bsc9132qds/Kconfig
board/freescale/c29xpcie/Kconfig
board/freescale/common/Makefile
board/freescale/common/dcu_sii9022a.c [new file with mode: 0644]
board/freescale/common/dcu_sii9022a.h [new file with mode: 0644]
board/freescale/corenet_ds/Kconfig
board/freescale/ls1021aqds/Kconfig [new file with mode: 0644]
board/freescale/ls1021aqds/MAINTAINERS [new file with mode: 0644]
board/freescale/ls1021aqds/Makefile [new file with mode: 0644]
board/freescale/ls1021aqds/README [new file with mode: 0644]
board/freescale/ls1021aqds/ddr.c [new file with mode: 0644]
board/freescale/ls1021aqds/ddr.h [new file with mode: 0644]
board/freescale/ls1021aqds/eth.c [new file with mode: 0644]
board/freescale/ls1021aqds/ls1021aqds.c [new file with mode: 0644]
board/freescale/ls1021aqds/ls1021aqds_qixis.h [new file with mode: 0644]
board/freescale/ls1021atwr/Kconfig [new file with mode: 0644]
board/freescale/ls1021atwr/MAINTAINERS [new file with mode: 0644]
board/freescale/ls1021atwr/Makefile [new file with mode: 0644]
board/freescale/ls1021atwr/README [new file with mode: 0644]
board/freescale/ls1021atwr/dcu.c [new file with mode: 0644]
board/freescale/ls1021atwr/ls1021atwr.c [new file with mode: 0644]
board/freescale/ls2085a/Kconfig
board/freescale/m5208evbe/Kconfig
board/freescale/m52277evb/Kconfig
board/freescale/m5235evb/Kconfig
board/freescale/m5249evb/Kconfig
board/freescale/m5253demo/Kconfig
board/freescale/m5253evbe/Kconfig
board/freescale/m5272c3/Kconfig
board/freescale/m5275evb/Kconfig
board/freescale/m5282evb/Kconfig
board/freescale/m53017evb/Kconfig
board/freescale/m5329evb/Kconfig
board/freescale/m5373evb/Kconfig
board/freescale/m54418twr/Kconfig
board/freescale/m54451evb/Kconfig
board/freescale/m54455evb/Kconfig
board/freescale/m547xevb/Kconfig
board/freescale/m548xevb/Kconfig
board/freescale/mpc5121ads/Kconfig
board/freescale/mpc7448hpc2/Kconfig
board/freescale/mpc8266ads/Kconfig
board/freescale/mpc8308rdb/Kconfig
board/freescale/mpc8313erdb/Kconfig
board/freescale/mpc8315erdb/Kconfig
board/freescale/mpc8323erdb/Kconfig
board/freescale/mpc832xemds/Kconfig
board/freescale/mpc8349emds/Kconfig
board/freescale/mpc8349itx/Kconfig
board/freescale/mpc8360emds/Kconfig
board/freescale/mpc8360emds/mpc8360emds.c
board/freescale/mpc8360erdk/Kconfig
board/freescale/mpc837xemds/Kconfig
board/freescale/mpc837xemds/mpc837xemds.c
board/freescale/mpc837xerdb/Kconfig
board/freescale/mpc8536ds/Kconfig
board/freescale/mpc8540ads/Kconfig
board/freescale/mpc8541cds/Kconfig
board/freescale/mpc8544ds/Kconfig
board/freescale/mpc8548cds/Kconfig
board/freescale/mpc8555cds/Kconfig
board/freescale/mpc8560ads/Kconfig
board/freescale/mpc8568mds/Kconfig
board/freescale/mpc8569mds/Kconfig
board/freescale/mpc8572ds/Kconfig
board/freescale/mpc8610hpcd/Kconfig
board/freescale/mpc8641hpcn/Kconfig
board/freescale/mx23evk/Kconfig
board/freescale/mx25pdk/Kconfig
board/freescale/mx28evk/Kconfig
board/freescale/mx31ads/Kconfig
board/freescale/mx31pdk/Kconfig
board/freescale/mx35pdk/Kconfig
board/freescale/mx51evk/Kconfig
board/freescale/mx53ard/Kconfig
board/freescale/mx53evk/Kconfig
board/freescale/mx53loco/Kconfig
board/freescale/mx53smd/Kconfig
board/freescale/mx6qarm2/Kconfig
board/freescale/mx6qsabreauto/Kconfig
board/freescale/mx6sabresd/Kconfig
board/freescale/mx6slevk/Kconfig
board/freescale/mx6sxsabresd/Kconfig
board/freescale/p1010rdb/Kconfig
board/freescale/p1022ds/Kconfig
board/freescale/p1023rdb/Kconfig
board/freescale/p1_p2_rdb/Kconfig
board/freescale/p1_p2_rdb_pc/Kconfig
board/freescale/p1_twr/Kconfig
board/freescale/p2020come/Kconfig
board/freescale/p2020ds/Kconfig
board/freescale/p2041rdb/Kconfig
board/freescale/qemu-ppce500/Kconfig
board/freescale/t1040qds/Kconfig
board/freescale/t104xrdb/Kconfig
board/freescale/t208xqds/Kconfig
board/freescale/t208xrdb/Kconfig
board/freescale/t4qds/Kconfig
board/freescale/t4rdb/Kconfig
board/freescale/vf610twr/Kconfig
board/funkwerk/vovpn-gw/Kconfig
board/g2000/Kconfig
board/gaisler/gr_cpci_ax2000/Kconfig
board/gaisler/gr_ep2s60/Kconfig
board/gaisler/gr_xc3s_1500/Kconfig
board/gaisler/grsim/Kconfig
board/gaisler/grsim_leon2/Kconfig
board/galaxy5200/Kconfig
board/gateworks/gw_ventana/Kconfig
board/gdsys/405ep/Kconfig
board/gdsys/405ex/Kconfig
board/gdsys/dlvision/Kconfig
board/gdsys/gdppc440etx/Kconfig
board/gdsys/intip/Kconfig
board/gdsys/p1022/Kconfig
board/genesi/mx51_efikamx/Kconfig
board/gumstix/duovero/Kconfig
board/gumstix/pepper/Kconfig
board/gw8260/Kconfig
board/h2200/Kconfig
board/hale/tt01/Kconfig
board/hermes/Kconfig
board/htkw/mcx/Kconfig
board/hymod/Kconfig
board/ibf-dsp561/Kconfig
board/icecube/Kconfig
board/icpdas/lp8x4x/Kconfig
board/icu862/Kconfig
board/ids/ids8247/Kconfig
board/ids/ids8313/Kconfig
board/ifm/ac14xx/Kconfig
board/ifm/o2dnt2/Kconfig
board/imgtec/malta/Kconfig
board/imx31_phycore/Kconfig
board/in-circuit/grasshopper/Kconfig
board/inka4x0/Kconfig
board/intercontrol/digsy_mtc/Kconfig
board/iomega/iconnect/Kconfig
board/ip04/Kconfig
board/ip860/Kconfig
board/ipek01/Kconfig
board/iphase4539/Kconfig
board/isee/igep0033/Kconfig
board/isee/igep00x0/Kconfig
board/ivm/Kconfig
board/jornada/Kconfig
board/jse/Kconfig
board/jupiter/Kconfig
board/karo/tk71/Kconfig
board/karo/tx25/Kconfig
board/keymile/km82xx/Kconfig
board/keymile/km83xx/Kconfig
board/keymile/km_arm/Kconfig
board/keymile/kmp204x/Kconfig
board/kmc/kzm9g/Kconfig
board/korat/Kconfig
board/kup/kup4k/Kconfig
board/kup/kup4x/Kconfig
board/logicpd/am3517evm/Kconfig
board/logicpd/imx27lite/Kconfig
board/logicpd/imx31_litekit/Kconfig
board/logicpd/omap3som/Kconfig
board/logicpd/zoom1/Kconfig
board/lwmon/Kconfig
board/lwmon5/Kconfig
board/manroland/hmi1001/Kconfig
board/manroland/mucmc52/Kconfig
board/manroland/uc100/Kconfig
board/manroland/uc101/Kconfig
board/matrix_vision/mergerbox/Kconfig
board/matrix_vision/mvbc_p/Kconfig
board/matrix_vision/mvblm7/Kconfig
board/matrix_vision/mvblx/Kconfig
board/matrix_vision/mvsmr/Kconfig
board/mcc200/Kconfig
board/micronas/vct/Kconfig
board/mimc/mimc200/Kconfig
board/miromico/hammerhead/Kconfig
board/mosaixtech/icon/Kconfig
board/motionpro/Kconfig
board/mpc8308_p1m/Kconfig
board/mpl/mip405/Kconfig
board/mpl/pati/Kconfig
board/mpl/pip405/Kconfig
board/mpl/vcma9/Kconfig
board/mpr2/Kconfig
board/ms7720se/Kconfig
board/ms7722se/Kconfig
board/ms7750se/Kconfig
board/muas3001/Kconfig
board/munices/Kconfig
board/musenki/Kconfig
board/mvblue/Kconfig
board/netvia/Kconfig
board/nokia/rx51/Kconfig
board/nvidia/beaver/Kconfig
board/nvidia/cardhu/Kconfig
board/nvidia/dalmore/Kconfig
board/nvidia/harmony/Kconfig
board/nvidia/jetson-tk1/Kconfig
board/nvidia/seaboard/Kconfig
board/nvidia/seaboard/seaboard.c
board/nvidia/venice2/Kconfig
board/nvidia/ventana/Kconfig
board/nvidia/whistler/Kconfig
board/olimex/mx23_olinuxino/Kconfig
board/omicron/calimain/Kconfig
board/openrisc/openrisc-generic/Kconfig
board/overo/Kconfig
board/palmld/Kconfig
board/palmtc/Kconfig
board/palmtreo680/Kconfig
board/pandora/Kconfig
board/pb1x00/Kconfig
board/pcs440ep/Kconfig
board/pdm360ng/Kconfig
board/phytec/pcm030/Kconfig
board/phytec/pcm051/Kconfig
board/pm520/Kconfig
board/pm826/Kconfig
board/pm828/Kconfig
board/ppcag/bg0900/Kconfig
board/ppmc7xx/Kconfig
board/ppmc8260/Kconfig
board/pr1/Kconfig
board/prodrive/alpr/Kconfig
board/prodrive/p3mx/Kconfig
board/prodrive/p3p440/Kconfig
board/pxa255_idp/Kconfig
board/qemu-mips/Kconfig
board/r360mpi/Kconfig
board/raidsonic/ib62x0/Kconfig
board/raspberrypi/rpi_b/Kconfig
board/renesas/MigoR/Kconfig
board/renesas/alt/Kconfig
board/renesas/ap325rxa/Kconfig
board/renesas/ecovec/Kconfig
board/renesas/koelsch/Kconfig
board/renesas/lager/Kconfig
board/renesas/r0p7734/Kconfig
board/renesas/r2dplus/Kconfig
board/renesas/r7780mp/Kconfig
board/renesas/rsk7203/Kconfig
board/renesas/rsk7264/Kconfig
board/renesas/rsk7269/Kconfig
board/renesas/sh7752evb/Kconfig
board/renesas/sh7753evb/Kconfig
board/renesas/sh7757lcr/Kconfig
board/renesas/sh7763rdp/Kconfig
board/renesas/sh7785lcr/Kconfig
board/ronetix/pm9261/Kconfig
board/ronetix/pm9263/Kconfig
board/ronetix/pm9g45/Kconfig
board/sacsng/Kconfig
board/samsung/arndale/Kconfig
board/samsung/goni/Kconfig
board/samsung/odroid/Kconfig
board/samsung/origen/Kconfig
board/samsung/smdk2410/Kconfig
board/samsung/smdk5250/Kconfig
board/samsung/smdk5420/Kconfig
board/samsung/smdkc100/Kconfig
board/samsung/smdkv310/Kconfig
board/samsung/trats/Kconfig
board/samsung/trats2/Kconfig
board/samsung/universal_c210/Kconfig
board/sandburst/karef/Kconfig
board/sandburst/metrobox/Kconfig
board/sandisk/sansa_fuze_plus/Kconfig
board/sandpoint/Kconfig
board/sbc405/Kconfig
board/sbc8349/Kconfig
board/sbc8548/Kconfig
board/sbc8641d/Kconfig
board/sc3/Kconfig
board/scb9328/Kconfig
board/schulercontrol/sc_sps_1/Kconfig
board/shmin/Kconfig
board/siemens/corvus/Kconfig
board/siemens/draco/Kconfig
board/siemens/pxm2/Kconfig
board/siemens/rut/Kconfig
board/siemens/taurus/Kconfig
board/silica/pengwyn/Kconfig
board/socrates/Kconfig
board/solidrun/hummingboard/Kconfig
board/spd8xx/Kconfig
board/spear/spear300/Kconfig
board/spear/spear310/Kconfig
board/spear/spear320/Kconfig
board/spear/spear600/Kconfig
board/spear/x600/Kconfig
board/st-ericsson/snowball/Kconfig
board/st-ericsson/u8500/Kconfig
board/st/nhk8815/Kconfig
board/stx/stxgp3/Kconfig
board/stx/stxssa/Kconfig
board/sunxi/Kconfig
board/synopsys/Kconfig
board/synopsys/axs101/Kconfig
board/syteco/jadecpu/Kconfig
board/syteco/zmx25/Kconfig
board/t3corp/Kconfig
board/taskit/stamp9g20/Kconfig
board/tcm-bf518/Kconfig
board/tcm-bf537/Kconfig
board/technexion/tao3530/Kconfig
board/technexion/twister/Kconfig
board/teejet/mt_ventoux/Kconfig
board/ti/am335x/Kconfig
board/ti/am3517crane/Kconfig
board/ti/am43xx/Kconfig
board/ti/beagle/Kconfig
board/ti/dra7xx/Kconfig
board/ti/evm/Kconfig
board/ti/ks2_evm/Kconfig
board/ti/omap5_uevm/Kconfig
board/ti/panda/Kconfig
board/ti/sdp3430/Kconfig
board/ti/sdp4430/Kconfig
board/ti/ti814x/Kconfig
board/ti/ti816x/Kconfig
board/ti/tnetv107xevm/Kconfig
board/timll/devkit3250/Kconfig
board/timll/devkit8000/Kconfig
board/toradex/colibri_pxa270/Kconfig
board/toradex/colibri_t20_iris/Kconfig
board/toradex/colibri_t30/Kconfig
board/total5200/Kconfig
board/tqc/tqm5200/Kconfig
board/tqc/tqm8260/Kconfig
board/tqc/tqm8272/Kconfig
board/tqc/tqm834x/Kconfig
board/tqc/tqm8xx/Kconfig
board/tqc/tqma6/Kconfig
board/trizepsiv/Kconfig
board/ttcontrol/vision2/Kconfig
board/udoo/Kconfig
board/utx8245/Kconfig
board/v38b/Kconfig
board/ve8313/Kconfig
board/vpac270/Kconfig
board/w7o/Kconfig
board/wandboard/Kconfig
board/woodburn/Kconfig
board/xaeniax/Kconfig
board/xes/xpedite1000/Kconfig
board/xes/xpedite517x/Kconfig
board/xes/xpedite520x/Kconfig
board/xes/xpedite537x/Kconfig
board/xes/xpedite550x/Kconfig
board/xilinx/microblaze-generic/Kconfig
board/xilinx/ml507/Kconfig
board/xilinx/ppc405-generic/Kconfig
board/xilinx/ppc440-generic/Kconfig
board/zeus/Kconfig
board/zipitz2/Kconfig
common/aboot.c [new file with mode: 0644]
common/board_f.c
common/board_r.c
common/bouncebuf.c
common/cmd_mem.c
common/cmd_mtdparts.c
common/kgdb.c
common/spl/spl.c
common/stdio.c
configs/ls1021aqds_nor_defconfig [new file with mode: 0644]
configs/ls1021atwr_nor_defconfig [new file with mode: 0644]
configs/ls2085a_emu_D4_defconfig
configs/ls2085a_emu_defconfig
configs/ls2085a_simu_defconfig
configs/vexpress_aemv8a_defconfig
configs/vexpress_aemv8a_semi_defconfig
doc/README.fsl-esdhc [new file with mode: 0644]
doc/README.scrapyard
doc/device-tree-bindings/serial/ns16550.txt [new file with mode: 0644]
doc/device-tree-bindings/serial/sandbox-serial.txt [new file with mode: 0644]
drivers/core/lists.c
drivers/core/root.c
drivers/ddr/fsl/arm_ddr_gen3.c
drivers/ddr/fsl/ctrl_regs.c
drivers/ddr/fsl/interactive.c
drivers/gpio/tegra_gpio.c
drivers/i2c/mxc_i2c.c
drivers/mmc/fsl_esdhc.c
drivers/mtd/mtdconcat.c
drivers/mtd/mtdcore.c
drivers/mtd/mtdpart.c
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/atmel_nand_ecc.h
drivers/mtd/nand/davinci_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_bbt.c
drivers/mtd/nand/nand_ids.c
drivers/mtd/ubi/attach.c
drivers/mtd/ubi/build.c
drivers/mtd/ubi/crc32.c
drivers/mtd/ubi/debug.c
drivers/mtd/ubi/debug.h
drivers/mtd/ubi/eba.c
drivers/mtd/ubi/fastmap.c
drivers/mtd/ubi/io.c
drivers/mtd/ubi/kapi.c
drivers/mtd/ubi/ubi.h
drivers/mtd/ubi/upd.c
drivers/mtd/ubi/vmt.c
drivers/mtd/ubi/vtbl.c
drivers/mtd/ubi/wl.c
drivers/net/ethoc.c
drivers/net/fm/dtsec.c
drivers/net/fm/fm.h
drivers/net/fm/init.c
drivers/net/fm/memac.c
drivers/net/fm/tgec.c
drivers/net/fsl_mdio.c
drivers/net/rtl8169.c
drivers/net/tsec.c
drivers/qe/uec.h
drivers/serial/Makefile
drivers/serial/ns16550.c
drivers/serial/sandbox.c
drivers/serial/serial-uclass.c [new file with mode: 0644]
drivers/serial/serial.c
drivers/serial/serial_lpuart.c
drivers/serial/serial_ns16550.c
drivers/serial/serial_tegra.c [new file with mode: 0644]
drivers/usb/eth/smsc95xx.c
drivers/usb/host/ehci-atmel.c
drivers/usb/host/ohci-at91.c
drivers/usb/musb-new/am35x.c
drivers/usb/musb-new/musb_core.c
drivers/usb/musb-new/musb_dsps.c
drivers/usb/musb-new/musb_gadget.c
drivers/usb/musb-new/musb_gadget_ep0.c
drivers/usb/musb-new/musb_host.c
drivers/usb/musb-new/musb_uboot.c
drivers/usb/musb-new/omap2430.c
drivers/video/Makefile
drivers/video/fsl_dcu_fb.c [new file with mode: 0644]
drivers/watchdog/Makefile
examples/standalone/Makefile
examples/standalone/stubs.c
fs/ubifs/budget.c
fs/ubifs/debug.c
fs/ubifs/debug.h
fs/ubifs/io.c
fs/ubifs/log.c
fs/ubifs/lprops.c
fs/ubifs/lpt.c
fs/ubifs/lpt_commit.c
fs/ubifs/master.c
fs/ubifs/misc.h
fs/ubifs/recovery.c
fs/ubifs/replay.c
fs/ubifs/sb.c
fs/ubifs/scan.c
fs/ubifs/super.c
fs/ubifs/tnc.c
fs/ubifs/tnc_misc.c
fs/ubifs/ubifs.c
fs/ubifs/ubifs.h
include/aboot.h [new file with mode: 0644]
include/configs/at91sam9n12ek.h
include/configs/at91sam9rlek.h
include/configs/ls1021aqds.h [new file with mode: 0644]
include/configs/ls1021atwr.h [new file with mode: 0644]
include/configs/sama5d3xek.h
include/configs/sandbox.h
include/configs/tegra-common.h
include/dm/lists.h
include/dm/uclass-id.h
include/dt-bindings/clock/tegra114-car.h [new file with mode: 0644]
include/dt-bindings/clock/tegra124-car.h [new file with mode: 0644]
include/dt-bindings/clock/tegra20-car.h [new file with mode: 0644]
include/dt-bindings/clock/tegra30-car.h [new file with mode: 0644]
include/fdtdec.h
include/fm_eth.h
include/fsl_dcu_fb.h [new file with mode: 0644]
include/fsl_ddr_sdram.h
include/fsl_esdhc.h
include/fsl_mdio.h
include/linux/compiler-clang.h [new file with mode: 0644]
include/linux/compiler-gcc.h
include/linux/compiler-gcc3.h
include/linux/compiler-gcc4.h
include/linux/compiler-intel.h [new file with mode: 0644]
include/linux/compiler.h
include/linux/mtd/flashchip.h
include/linux/mtd/mtd.h
include/linux/mtd/nand.h
include/linux/mtd/ubi.h
include/linux/rbtree.h
include/mtd/mtd-abi.h
include/ns16550.h
include/serial.h
include/sparse_defs.h [new file with mode: 0644]
include/stdio_dev.h
include/systemace.h
include/tsec.h
lib/fdtdec.c
lib/list_sort.c
lib/rbtree.c
net/dns.c
scripts/Makefile.clean
scripts/multiconfig.sh
tools/buildman/README
tools/buildman/board.py
tools/buildman/bsettings.py
tools/buildman/builder.py
tools/buildman/builderthread.py
tools/buildman/buildman.py
tools/buildman/cmdline.py [new file with mode: 0644]
tools/buildman/control.py
tools/buildman/func_test.py [new file with mode: 0644]
tools/buildman/kconfiglib.py [new file with mode: 0644]
tools/buildman/test.py
tools/buildman/toolchain.py
tools/genboardscfg.py
tools/patman/command.py
tools/patman/gitutil.py
tools/patman/patchstream.py
tools/patman/patman.py
tools/patman/terminal.py
tools/patman/test.py

index c6ff277..fe6dadc 100644 (file)
@@ -66,3 +66,4 @@ BSD 2-Clause License                          BSD-2-Clause    Y               bsd-2-clause.txt        http://spdx.org/license
 BSD 3-clause "New" or "Revised" License                BSD-3-Clause    Y               bsd-3-clause.txt        http://spdx.org/licenses/BSD-3-Clause#licenseText
 IBM PIBS (PowerPC Initialization and           IBM-pibs                        ibm-pibs.txt
        Boot Software) license
+ISC License                                    ISC             Y               isc.txt                 https://spdx.org/licenses/ISC
diff --git a/Licenses/isc.txt b/Licenses/isc.txt
new file mode 100644 (file)
index 0000000..4b7c2ba
--- /dev/null
@@ -0,0 +1,17 @@
+ISC License:
+Copyright (c) 2004-2010 by Internet Systems Consortium, Inc. ("ISC")
+Copyright (c) 1995-2003 by Internet Software Consortium
+
+Permission to use, copy, modify, and/or distribute this software
+for any purpose with or without fee is hereby granted,
+provided that the above copyright notice and this permission notice
+appear in all copies.
+
+THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES
+WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL ISC BE LIABLE
+FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR
+ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
+WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
+ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
+THIS SOFTWARE.
index 42263e4..1fccd0b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -341,7 +341,7 @@ CHECK               = sparse
 CHECKFLAGS     := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
                  -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
 
-KBUILD_CPPFLAGS := -D__KERNEL__
+KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
 
 KBUILD_CFLAGS   := -Wall -Wstrict-prototypes \
                   -Wno-format-security \
@@ -458,7 +458,7 @@ KBUILD_DEFCONFIG := sandbox_defconfig
 export KBUILD_DEFCONFIG KBUILD_KCONFIG
 
 config: scripts_basic outputmakefile FORCE
-       (Q)$(MAKE) $(build)=scripts/kconfig $@
+       +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
 
 %config: scripts_basic outputmakefile FORCE
        +$(Q)$(CONFIG_SHELL) $(srctree)/scripts/multiconfig.sh $@
index 8620a4f..c9ccb7d 100644 (file)
@@ -49,6 +49,62 @@ config X86
 
 endchoice
 
+config SYS_ARCH
+       string
+       help
+         This option should contain the architecture name to build the
+         appropriate arch/<CONFIG_SYS_ARCH> directory.
+         All the architectures should specify this option correctly.
+
+config SYS_CPU
+       string
+       help
+         This option should contain the CPU name to build the correct
+         arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
+
+         This is optional.  For those targets without the CPU directory,
+         leave this option empty.
+
+config SYS_SOC
+       string
+       help
+         This option should contain the SoC name to build the directory
+         arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
+
+         This is optional.  For those targets without the SoC directory,
+         leave this option empty.
+
+config SYS_VENDOR
+       string
+       help
+         This option should contain the vendor name of the target board.
+         If it is set and
+         board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
+         directory is compiled.
+         If CONFIG_SYS_BOARD is also set, the sources under
+         board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
+
+         This is optional.  For those targets without the vendor directory,
+         leave this option empty.
+
+config SYS_BOARD
+       string
+       help
+         This option should contain the name of the target board.
+         If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
+         or board/<CONFIG_SYS_BOARD> directory is compiled depending on
+         whether CONFIG_SYS_VENDOR is set or not.
+
+         This is optional.  For those targets without the board directory,
+         leave this option empty.
+
+config SYS_CONFIG_NAME
+       string
+       help
+         This option should contain the base name of board header file.
+         The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
+         should be included from include/config.h.
+
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/avr32/Kconfig"
index 51d5aff..d3ef58b 100644 (file)
@@ -2,7 +2,6 @@ menu "ARC architecture"
        depends on ARC
 
 config SYS_ARCH
-       string
        default "arc"
 
 choice
index f933123..106aed9 100644 (file)
@@ -2,9 +2,11 @@ menu "ARM architecture"
        depends on ARM
 
 config SYS_ARCH
-       string
        default "arm"
 
+config ARM64
+       bool
+
 choice
        prompt "Target select"
 
@@ -463,15 +465,21 @@ config TEGRA
 
 config TARGET_VEXPRESS_AEMV8A
        bool "Support vexpress_aemv8a"
-
-config TARGET_VEXPRESS_AEMV8A_SEMI
-       bool "Support vexpress_aemv8a_semi"
+       select ARM64
 
 config TARGET_LS2085A_EMU
        bool "Support ls2085a_emu"
+       select ARM64
 
 config TARGET_LS2085A_SIMU
        bool "Support ls2085a_simu"
+       select ARM64
+
+config TARGET_LS1021AQDS
+       bool "Support ls1021aqds_nor"
+
+config TARGET_LS1021ATWR
+       bool "Support ls1021atwr_nor"
 
 config TARGET_BALLOON3
        bool "Support balloon3"
@@ -514,6 +522,8 @@ config TARGET_JORNADA
 
 endchoice
 
+source "arch/arm/cpu/armv8/Kconfig"
+
 source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
 
 source "arch/arm/cpu/armv7/exynos/Kconfig"
@@ -598,6 +608,8 @@ source "board/eukrea/cpu9260/Kconfig"
 source "board/eukrea/cpuat91/Kconfig"
 source "board/faraday/a320evb/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
+source "board/freescale/ls1021aqds/Kconfig"
+source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
index be1b0f9..4c18ab6 100644 (file)
@@ -54,11 +54,9 @@ config TARGET_CALIMAIN
 endchoice
 
 config SYS_CPU
-       string
        default "arm926ejs"
 
 config SYS_SOC
-       string
        default "davinci"
 
 source "board/enbw/enbw_cmc/Kconfig"
index 58867f3..91ffedf 100644 (file)
@@ -60,11 +60,9 @@ config TARGET_GOFLEXHOME
 endchoice
 
 config SYS_CPU
-       string
        default "arm926ejs"
 
 config SYS_SOC
-       string
        default "kirkwood"
 
 source "board/Marvell/openrd/Kconfig"
index 7177800..eda51fd 100644 (file)
@@ -9,11 +9,9 @@ config NOMADIK_NHK8815
 endchoice
 
 config SYS_CPU
-       string
        default "arm926ejs"
 
 config SYS_SOC
-       string
        default "nomadik"
 
 source "board/st/nhk8815/Kconfig"
index aa40099..2d0ab2b 100644 (file)
@@ -9,11 +9,9 @@ config TARGET_EDMINIV2
 endchoice
 
 config SYS_CPU
-       string
        default "arm926ejs"
 
 config SYS_SOC
-       string
        default "orion5x"
 
 source "board/LaCie/edminiv2/Kconfig"
index fc29c98..35c16d8 100644 (file)
@@ -1,23 +1,18 @@
 if ARCH_VERSATILE
 
 config SYS_CPU
-       string
        default "arm926ejs"
 
 config SYS_BOARD
-       string
        default "versatile"
 
 config SYS_VENDOR
-       string
        default "armltd"
 
 config SYS_SOC
-       string
        default "versatile"
 
 config SYS_CONFIG_NAME
-       string
        default "versatile"
 
 endif
index 1588e0c..36ed4a6 100644 (file)
@@ -114,9 +114,25 @@ int at91_clock_init(unsigned long main_clock)
 void at91_periph_clk_enable(int id)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       u32 regval;
 
-       if (id > 31)
-               writel(1 << (id - 32), &pmc->pcer1);
-       else
-               writel(1 << id, &pmc->pcer);
+       if (id > AT91_PMC_PCR_PID_MASK)
+               return;
+
+       regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
+
+       writel(regval, &pmc->pcr);
+}
+
+void at91_periph_clk_disable(int id)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       u32 regval;
+
+       if (id > AT91_PMC_PCR_PID_MASK)
+               return;
+
+       regval = AT91_PMC_PCR_CMD_WRITE | id;
+
+       writel(regval, &pmc->pcr);
 }
index b6a558b..d132f03 100644 (file)
@@ -39,11 +39,9 @@ config TARGET_PEACH_PIT
 endchoice
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_SOC
-       string
        default "exynos"
 
 source "board/samsung/smdkv310/Kconfig"
index 9527928..29ff995 100644 (file)
@@ -1,19 +1,15 @@
 if ARCH_HIGHBANK
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_BOARD
-       string
        default "highbank"
 
 config SYS_SOC
-       string
        default "highbank"
 
 config SYS_CONFIG_NAME
-       string
        default "highbank"
 
 endif
index 24d0cbe..8249b5e 100644 (file)
@@ -12,11 +12,9 @@ config TARGET_K2E_EVM
 endchoice
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_SOC
-       string
        default "keystone"
 
 source "board/ti/ks2_evm/Kconfig"
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
new file mode 100644 (file)
index 0000000..d82ce8d
--- /dev/null
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y  += cpu.o
+obj-y  += clock.o
+obj-y  += timer.o
+
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
new file mode 100644 (file)
index 0000000..8f80c61
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+#include <fsl_ifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS      2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+       struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+       u32 ccr;
+#endif
+       struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+       unsigned int cpu;
+       const u8 core_cplx_pll[6] = {
+               [0] = 0,        /* CC1 PPL / 1 */
+               [1] = 0,        /* CC1 PPL / 2 */
+               [4] = 1,        /* CC2 PPL / 1 */
+               [5] = 1,        /* CC2 PPL / 2 */
+       };
+
+       const u8 core_cplx_pll_div[6] = {
+               [0] = 1,        /* CC1 PPL / 1 */
+               [1] = 2,        /* CC1 PPL / 2 */
+               [4] = 1,        /* CC2 PPL / 1 */
+               [5] = 2,        /* CC2 PPL / 2 */
+       };
+
+       uint i;
+       uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+       uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+       unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+       sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+       sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+       sys_info->freq_ddrbus = sysclk;
+#endif
+
+       sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >>
+               RCWSR0_SYS_PLL_RAT_SHIFT) & RCWSR0_SYS_PLL_RAT_MASK;
+       sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >>
+               RCWSR0_MEM_PLL_RAT_SHIFT) & RCWSR0_MEM_PLL_RAT_MASK;
+
+       for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+               ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
+               if (ratio[i] > 4)
+                       freq_c_pll[i] = sysclk * ratio[i];
+               else
+                       freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+       }
+
+       for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
+               u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+                               & 0xf;
+               u32 cplx_pll = core_cplx_pll[c_pll_sel];
+
+               sys_info->freq_processor[cpu] =
+                       freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+       }
+
+#if defined(CONFIG_FSL_IFC)
+       ccr = in_be32(&ifc_regs->ifc_ccr);
+       ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+       sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#endif
+}
+
+int get_clocks(void)
+{
+       struct sys_info sys_info;
+
+       get_sys_info(&sys_info);
+       gd->cpu_clk = sys_info.freq_processor[0];
+       gd->bus_clk = sys_info.freq_systembus;
+       gd->mem_clk = sys_info.freq_ddrbus * 2;
+
+#if defined(CONFIG_FSL_ESDHC)
+       gd->arch.sdhc_clk = gd->bus_clk;
+#endif
+
+       return 0;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+       return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+       return gd->mem_clk;
+}
+
+int get_serial_clock(void)
+{
+       return gd->bus_clk / 2;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+       switch (clk) {
+       case MXC_I2C_CLK:
+               return get_bus_freq(0) / 2;
+       case MXC_ESDHC_CLK:
+               return get_bus_freq(0);
+       case MXC_DSPI_CLK:
+               return get_bus_freq(0) / 2;
+       case MXC_UART_CLK:
+               return get_bus_freq(0) / 2;
+       default:
+               printf("Unsupported clock\n");
+       }
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
new file mode 100644 (file)
index 0000000..b7dde45
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <tsec.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+       char buf1[32], buf2[32];
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       unsigned int svr, major, minor, ver, i;
+
+       svr = in_be32(&gur->svr);
+       major = SVR_MAJ(svr);
+       minor = SVR_MIN(svr);
+
+       puts("CPU:   Freescale LayerScape ");
+
+       ver = SVR_SOC_VER(svr);
+       switch (ver) {
+       case SOC_VER_SLS1020:
+               puts("SLS1020");
+               break;
+       case SOC_VER_LS1020:
+               puts("LS1020");
+               break;
+       case SOC_VER_LS1021:
+               puts("LS1021");
+               break;
+       case SOC_VER_LS1022:
+               puts("LS1022");
+               break;
+       default:
+               puts("Unknown");
+               break;
+       }
+
+       if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
+               puts("E");
+
+       printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
+
+       puts("Clock Configuration:");
+
+       printf("\n       CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
+       printf("\n       Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
+       printf("DDR:%-4s MHz (%s MT/s data rate), ",
+              strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
+       puts("\n");
+
+       /* Display the RCW, so that no one gets confused as to what RCW
+        * we're actually using for this boot.
+        */
+       puts("Reset Configuration Word (RCW):");
+       for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+               u32 rcw = in_be32(&gur->rcwsr[i]);
+
+               if ((i % 4) == 0)
+                       printf("\n       %08x:", i * 4);
+               printf(" %08x", rcw);
+       }
+       puts("\n");
+
+       return 0;
+}
+#endif
+
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       dcache_enable();
+#endif
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+       return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_TSEC_ENET
+       tsec_standard_init(bis);
+#endif
+
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
new file mode 100644 (file)
index 0000000..4ce3808
--- /dev/null
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+#include <linux/ctype.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
+#include <tsec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void ft_fixup_enet_phy_connect_type(void *fdt)
+{
+       struct eth_device *dev;
+       struct tsec_private *priv;
+       const char *enet_path, *phy_path;
+       char enet[16];
+       char phy[16];
+       int phy_node;
+       int i = 0;
+       int enet_id = 0;
+       uint32_t ph;
+
+       while ((dev = eth_get_dev_by_index(i++)) != NULL) {
+               if (strstr(dev->name, "eTSEC1"))
+                       enet_id = 0;
+               else if (strstr(dev->name, "eTSEC2"))
+                       enet_id = 1;
+               else if (strstr(dev->name, "eTSEC3"))
+                       enet_id = 2;
+               else
+                       continue;
+
+               priv = dev->priv;
+               if (priv->flags & TSEC_SGMII)
+                       continue;
+
+               sprintf(enet, "ethernet%d", enet_id);
+               enet_path = fdt_get_alias(fdt, enet);
+               if (!enet_path)
+                       continue;
+
+               sprintf(phy, "enet%d_rgmii_phy", enet_id);
+               phy_path = fdt_get_alias(fdt, phy);
+               if (!phy_path)
+                       continue;
+
+               phy_node = fdt_path_offset(fdt, phy_path);
+               if (phy_node < 0)
+                       continue;
+
+               ph = fdt_create_phandle(fdt, phy_node);
+               if (ph)
+                       do_fixup_by_path_u32(fdt, enet_path,
+                                            "phy-handle", ph, 1);
+
+               do_fixup_by_path(fdt, enet_path, "phy-connection-type",
+                                phy_string_for_interface(
+                                PHY_INTERFACE_MODE_RGMII_ID),
+                                sizeof(phy_string_for_interface(
+                                PHY_INTERFACE_MODE_RGMII_ID)),
+                                1);
+       }
+}
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+       int off;
+       int val;
+       const char *sysclk_path;
+
+       unsigned long busclk = get_bus_freq(0);
+
+       fdt_fixup_ethernet(blob);
+
+       off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+       while (off != -FDT_ERR_NOTFOUND) {
+               val = gd->cpu_clk;
+               fdt_setprop(blob, off, "clock-frequency", &val, 4);
+               off = fdt_node_offset_by_prop_value(blob, off,
+                                                   "device_type", "cpu", 4);
+       }
+
+       do_fixup_by_prop_u32(blob, "device_type", "soc",
+                            4, "bus-frequency", busclk / 2, 1);
+
+       ft_fixup_enet_phy_connect_type(blob);
+
+#ifdef CONFIG_SYS_NS16550
+       do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
+                              "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+#endif
+
+       sysclk_path = fdt_get_alias(blob, "sysclk");
+       if (sysclk_path)
+               do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
+                                    CONFIG_SYS_CLK_FREQ, 1);
+       do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
+                              "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+
+#if defined(CONFIG_FSL_ESDHC)
+       fdt_fixup_esdhc(blob, bd);
+#endif
+
+       /*
+        * platform bus clock = system bus clock/2
+        * Here busclk = system bus clock
+        * We are using the platform bus clock as 1588 Timer reference
+        * clock source select
+        */
+       do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
+                              "timer-frequency", busclk / 2, 1);
+
+       /*
+        * clock-freq should change to clock-frequency and
+        * flexcan-v1.0 should change to p1010-flexcan respectively
+        * in the future.
+        */
+       do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
+                              "clock_freq", busclk / 2, 1);
+
+       do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
+                              "clock-frequency", busclk / 2, 1);
+
+       do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
+                              "clock-frequency", busclk / 2, 1);
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
new file mode 100644 (file)
index 0000000..9b78acb
--- /dev/null
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include "fsl_ls1_serdes.h"
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u64 serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u64 serdes2_prtcl_map;
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+       u64 ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       ret |= (1ULL << device) & serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       ret |= (1ULL << device) & serdes2_prtcl_map;
+#endif
+
+       return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u32 cfg = in_be32(&gur->rcwsr[4]);
+       int i;
+
+       switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       case FSL_SRDS_1:
+               cfg &= RCWSR4_SRDS1_PRTCL_MASK;
+               cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
+               break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       case FSL_SRDS_2:
+               cfg &= RCWSR4_SRDS2_PRTCL_MASK;
+               cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
+               break;
+#endif
+       default:
+               printf("invalid SerDes%d\n", sd);
+               break;
+       }
+       /* Is serdes enabled at all? */
+       if (unlikely(cfg == 0))
+               return -ENODEV;
+
+       for (i = 0; i < SRDS_MAX_LANES; i++) {
+               if (serdes_get_prtcl(sd, cfg, i) == device)
+                       return i;
+       }
+
+       return -ENODEV;
+}
+
+u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       u64 serdes_prtcl_map = 0;
+       u32 cfg;
+       int lane;
+
+       cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
+       cfg >>= sd_prctl_shift;
+       printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+       if (!is_serdes_prtcl_valid(sd, cfg))
+               printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+       for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+
+               serdes_prtcl_map |= (1ULL << lane_prtcl);
+       }
+
+       return serdes_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+                                       CONFIG_SYS_FSL_SERDES_ADDR,
+                                       RCWSR4_SRDS1_PRTCL_MASK,
+                                       RCWSR4_SRDS1_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+                                       CONFIG_SYS_FSL_SERDES_ADDR +
+                                       FSL_SRDS_2 * 0x1000,
+                                       RCWSR4_SRDS2_PRTCL_MASK,
+                                       RCWSR4_SRDS2_PRTCL_SHIFT);
+#endif
+}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+       switch (clock) {
+       case SRDS_PLLCR0_RFCK_SEL_100:
+               return "100";
+       case SRDS_PLLCR0_RFCK_SEL_125:
+               return "125";
+       default:
+               return "100";
+       }
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
new file mode 100644 (file)
index 0000000..834aa53
--- /dev/null
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_LS1_SERDES_H
+#define __FSL_LS1_SERDES_H
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+#endif /* __FSL_LS1_SERDES_H */
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
new file mode 100644 (file)
index 0000000..cc53910
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_ls102xa.h>
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+       [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1},
+       [0x10] = {PCIE1, SATA1, PCIE2, PCIE2},
+       [0x20] = {PCIE1, SGMII_TSEC1, PCIE2, SGMII_TSEC2},
+       [0x30] = {PCIE1, SATA1, SGMII_TSEC1, SGMII_TSEC2},
+       [0x40] = {PCIE1, PCIE1, SATA1, SGMII_TSEC2},
+       [0x50] = {PCIE1, PCIE1, PCIE2, SGMII_TSEC2},
+       [0x60] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
+       [0x70] = {PCIE1, SATA1, PCIE2, SGMII_TSEC2},
+       [0x80] = {PCIE2, PCIE2, PCIE2, PCIE2},
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+       return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+       int i;
+
+       if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
+               return 0;
+
+       for (i = 0; i < SRDS_MAX_LANES; i++) {
+               if (serdes_cfg_tbl[prtcl][i] != NONE)
+                       return 1;
+       }
+
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/timer.c b/arch/arm/cpu/armv7/ls102xa/timer.c
new file mode 100644 (file)
index 0000000..11b17b2
--- /dev/null
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+       ulong ticks;
+
+       if (usec < 1000)
+               ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+       else
+               ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+       return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+       unsigned long freq;
+
+       asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+       tick *= CONFIG_SYS_HZ;
+       do_div(tick, freq);
+
+       return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+       unsigned long freq;
+
+       asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+       usec = usec * freq  + 999999;
+       do_div(usec, 1000000);
+
+       return usec;
+}
+
+int timer_init(void)
+{
+       struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+       unsigned long ctrl, val, freq;
+
+       /* Enable System Counter */
+       writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
+
+       freq = GENERIC_TIMER_CLK;
+       asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+       /* Set PL1 Physical Timer Ctrl */
+       ctrl = ARCH_TIMER_CTRL_ENABLE;
+       asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+
+       /* Set PL1 Physical Comp Value */
+       val = TIMER_COMP_VAL;
+       asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
+
+       gd->arch.tbl = 0;
+       gd->arch.tbu = 0;
+
+       return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+       unsigned long long now;
+
+       asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+       gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+       gd->arch.tbu = (unsigned long)(now >> 32);
+
+       return now;
+}
+
+unsigned long get_timer_masked(void)
+{
+       return tick_to_time(get_ticks());
+}
+
+unsigned long get_timer(ulong base)
+{
+       return get_timer_masked() - base;
+}
+
+/* delay x useconds and preserve advance timstamp value */
+void __udelay(unsigned long usec)
+{
+       unsigned long long start;
+       unsigned long tmo;
+
+       start = get_ticks();                    /* get current timestamp */
+       tmo = us_to_tick(usec);                 /* convert usecs to ticks */
+
+       while ((get_ticks() - start) < tmo)
+               ;                               /* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+       unsigned long freq;
+
+       asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+       return freq;
+}
index 6578f0c..6fae1e5 100644 (file)
@@ -75,11 +75,9 @@ config TARGET_TWISTER
 endchoice
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_SOC
-       string
        default "omap3"
 
 source "board/logicpd/am3517evm/Kconfig"
index 20d2c11..e270895 100644 (file)
@@ -15,11 +15,9 @@ config TARGET_OMAP4_SDP4430
 endchoice
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_SOC
-       string
        default "omap4"
 
 source "board/gumstix/duovero/Kconfig"
index be80393..2ccf5b9 100644 (file)
@@ -15,11 +15,9 @@ config TARGET_DRA7XX_EVM
 endchoice
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_SOC
-       string
        default "omap5"
 
 source "board/compulab/cm_t54/Kconfig"
index 55c620a..6c2bb22 100644 (file)
@@ -21,11 +21,9 @@ config TARGET_ALT
 endchoice
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_SOC
-       string
        default "rmobile"
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
index 8e2153b..bcae2d6 100644 (file)
@@ -18,7 +18,6 @@ config TEGRA124
 endchoice
 
 config SYS_CPU
-       string
        default "arm720t" if SPL_BUILD
        default "armv7" if !SPL_BUILD
 
index 33a22da..31012bc 100644 (file)
@@ -9,7 +9,6 @@ config TARGET_DALMORE
 endchoice
 
 config SYS_SOC
-       string
        default "tegra114"
 
 source "board/nvidia/dalmore/Kconfig"
index 753f511..6a1c83a 100644 (file)
@@ -12,7 +12,6 @@ config TARGET_VENICE2
 endchoice
 
 config SYS_SOC
-       string
        default "tegra124"
 
 source "board/nvidia/jetson-tk1/Kconfig"
index e2e0890..a354e2a 100644 (file)
@@ -36,7 +36,6 @@ config TARGET_COLIBRI_T20_IRIS
 endchoice
 
 config SYS_SOC
-       string
        default "tegra20"
 
 source "board/nvidia/harmony/Kconfig"
index 694e1cd..54aec4e 100644 (file)
@@ -18,7 +18,6 @@ config TARGET_TEC_NG
 endchoice
 
 config SYS_SOC
-       string
        default "tegra30"
 
 source "board/nvidia/beaver/Kconfig"
index 6b88f18..d6655a9 100644 (file)
@@ -18,23 +18,18 @@ config TARGET_ZYNQ_ZC770
 endchoice
 
 config SYS_CPU
-       string
        default "armv7"
 
 config SYS_BOARD
-       string
        default "zynq"
 
 config SYS_VENDOR
-       string
        default "xilinx"
 
 config SYS_SOC
-       string
        default "zynq"
 
 config SYS_CONFIG_NAME
-       string
        default "zynq_zed" if TARGET_ZYNQ_ZED
        default "zynq_microzed" if TARGET_ZYNQ_MICROZED
        default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
new file mode 100644 (file)
index 0000000..3d1655b
--- /dev/null
@@ -0,0 +1,6 @@
+if ARM64
+
+config SYS_CPU
+       default "armv8"
+
+endif
index 435c01e..81ad212 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Dalmore";
        compatible = "nvidia,dalmore", "nvidia,tegra114";
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                i2c0 = "/i2c@7000d000";
                i2c1 = "/i2c@7000c000";
index 59434e0..88bdc49 100644 (file)
@@ -1,3 +1,4 @@
+#include <dt-bindings/clock/tegra114-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
                status = "disabled";
        };
 
+       uarta: serial@70006000 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006000 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA114_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
+               dmas = <&apbdma 8>, <&apbdma 8>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartb: serial@70006040 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006040 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA114_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
+               dmas = <&apbdma 9>, <&apbdma 9>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartc: serial@70006200 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006200 0x100>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA114_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
+               dmas = <&apbdma 10>, <&apbdma 10>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartd: serial@70006300 {
+               compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+               reg = <0x70006300 0x100>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA114_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
+               dmas = <&apbdma 19>, <&apbdma 19>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
        spi@7000d400 {
                compatible = "nvidia,tegra114-spi";
                reg = <0x7000d400 0x200>;
index 464287e..ffad116 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Jetson TK1";
        compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                i2c0 = "/i2c@7000d000";
                i2c1 = "/i2c@7000c000";
index f003413..f7ccfc5 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Venice2";
        compatible = "nvidia,venice2", "nvidia,tegra124";
 
+       chosen {
+               stdout-path = &uarta;
+       };
+
        aliases {
                i2c0 = "/i2c@7000d000";
                i2c1 = "/i2c@7000c000";
index 4561c5f..3288f28 100644 (file)
@@ -1,3 +1,4 @@
+#include <dt-bindings/clock/tegra124-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
                status = "disabled";
        };
 
+       uarta: serial@70006000 {
+               compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
+               reg = <0x70006000 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA124_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
+               dmas = <&apbdma 8>, <&apbdma 8>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartb: serial@70006040 {
+               compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
+               reg = <0x70006040 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA124_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
+               dmas = <&apbdma 9>, <&apbdma 9>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartc: serial@70006200 {
+               compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
+               reg = <0x70006200 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA124_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
+               dmas = <&apbdma 10>, <&apbdma 10>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartd: serial@70006300 {
+               compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
+               reg = <0x70006300 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA124_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
+               dmas = <&apbdma 19>, <&apbdma 19>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uarte: serial@70006400 {
+               compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
+               reg = <0x70006400 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA124_CLK_UARTE>;
+               resets = <&tegra_car 66>;
+               reset-names = "serial";
+               dmas = <&apbdma 20>, <&apbdma 20>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
        spi@7000d400 {
                compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
                reg = <0x7000d400 0x200>;
index c0e54af..7cf08f4 100644 (file)
@@ -6,6 +6,10 @@
        model = "Toradex Colibri T20";
        compatible = "toradex,t20", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uarta;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                usb1 = "/usb@c5000000";
index b115f87..982a14c 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Tegra20 Harmony evaluation board";
        compatible = "nvidia,harmony", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                usb1 = "/usb@c5004000";
index a9a07f9..be2ed42 100644 (file)
@@ -6,6 +6,10 @@
        model = "Avionic Design Medcom-Wide";
        compatible = "ad,medcom-wide", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                sdhci0 = "/sdhci@c8000600";
index 780203c..9d735b5 100644 (file)
@@ -6,6 +6,10 @@
        model = "Toshiba AC100 / Dynabook AZ";
        compatible = "compal,paz00", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uarta;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                sdhci0 = "/sdhci@c8000600";
index 20016f2..e5562a9 100644 (file)
@@ -6,6 +6,10 @@
        model = "Avionic Design Plutux";
        compatible = "ad,plutux", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                sdhci0 = "/sdhci@c8000600";
index c0e2e1e..43b9911 100644 (file)
                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
        };
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                /* This defines the order of our ports */
                usb0 = "/usb@c5008000";
index 4c1b08d..e99bd44 100644 (file)
@@ -6,6 +6,10 @@
        model = "Avionic Design Tamonten Evaluation Carrier";
        compatible = "ad,tec", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                sdhci0 = "/sdhci@c8000600";
index ee31476..cee5cfe 100644 (file)
@@ -6,6 +6,10 @@
        model = "Compulab TrimSlice board";
        compatible = "compulab,trimslice", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uarta;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                usb1 = "/usb@c5000000";
index 1a526ba..6812203 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Tegra20 Ventana evaluation board";
        compatible = "nvidia,ventana", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                usb0 = "/usb@c5008000";
                sdhci0 = "/sdhci@c8000600";
index eb92264..4fd2496 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Tegra20 Whistler evaluation board";
        compatible = "nvidia,whistler", "nvidia,tegra20";
 
+       chosen {
+               stdout-path = &uarta;
+       };
+
        aliases {
                i2c0 = "/i2c@7000d000";
                usb0 = "/usb@c5008000";
index a524f6e..5f927f7 100644 (file)
@@ -1,3 +1,4 @@
+#include <dt-bindings/clock/tegra20-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
                dma-channel = < 1 >;
        };
 
-       serial@70006000 {
+       uarta: serial@70006000 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
-               interrupts = < 68 >;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
+               dmas = <&apbdma 8>, <&apbdma 8>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006040 {
+       uartb: serial@70006040 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
-               interrupts = < 69 >;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
+               dmas = <&apbdma 9>, <&apbdma 9>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006200 {
+       uartc: serial@70006200 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
-               interrupts = < 78 >;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
+               dmas = <&apbdma 10>, <&apbdma 10>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006300 {
+       uartd: serial@70006300 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
-               interrupts = < 122 >;
+               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
+               dmas = <&apbdma 19>, <&apbdma 19>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       serial@70006400 {
+       uarte: serial@70006400 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
-               interrupts = < 123 >;
+               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+               resets = <&tegra_car 66>;
+               reset-names = "serial";
+               dmas = <&apbdma 20>, <&apbdma 20>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
        nand: nand-controller@70008000 {
index 85e62e9..ad140de 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Beaver";
        compatible = "nvidia,beaver", "nvidia,tegra30";
 
+       chosen {
+               stdout-path = &uarta;
+       };
+
        aliases {
                i2c0 = "/i2c@7000d000";
                i2c1 = "/i2c@7000c000";
index ea2cf76..b4fbe71 100644 (file)
@@ -6,6 +6,10 @@
        model = "NVIDIA Cardhu";
        compatible = "nvidia,cardhu", "nvidia,tegra30";
 
+       chosen {
+               stdout-path = &uarta;
+       };
+
        aliases {
                i2c0 = "/i2c@7000d000";
                i2c1 = "/i2c@7000c000";
index 50d5762..c73afef 100644 (file)
@@ -8,6 +8,10 @@
                reg = <0x80000000 0x40000000>;
        };
 
+       chosen {
+               stdout-path = &uartd;
+       };
+
        aliases {
                i2c0 = "/i2c@7000c000";
                i2c1 = "/i2c@7000c700";
index 7be3791..fb92a0f 100644 (file)
@@ -1,3 +1,4 @@
+#include <dt-bindings/clock/tegra30-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
                status = "disabled";
        };
 
+       uarta: serial@70006000 {
+               compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+               reg = <0x70006000 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA30_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
+               dmas = <&apbdma 8>, <&apbdma 8>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartb: serial@70006040 {
+               compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+               reg = <0x70006040 0x40>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA30_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
+               dmas = <&apbdma 9>, <&apbdma 9>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartc: serial@70006200 {
+               compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+               reg = <0x70006200 0x100>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA30_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
+               dmas = <&apbdma 10>, <&apbdma 10>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uartd: serial@70006300 {
+               compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+               reg = <0x70006300 0x100>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA30_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
+               dmas = <&apbdma 19>, <&apbdma 19>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       uarte: serial@70006400 {
+               compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+               reg = <0x70006400 0x100>;
+               reg-shift = <2>;
+               interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA30_CLK_UARTE>;
+               resets = <&tegra_car 66>;
+               reset-names = "serial";
+               dmas = <&apbdma 20>, <&apbdma 20>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
        spi@7000d400 {
                compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                reg = <0x7000d400 0x200>;
index 04f6239..27331ff 100644 (file)
@@ -54,7 +54,7 @@ typedef struct at91_pmc {
        u32     reserved5[21];
        u32     wpmr;           /* 0xE4 Write Protect Mode Register (CAP0) */
        u32     wpsr;           /* 0xE8 Write Protect Status Register (CAP0) */
-#ifdef CONFIG_SAMA5D3
+#ifdef CPU_HAS_PCR
        u32     reserved6[8];
        u32     pcer1;          /* 0x100 Periperial Clock Enable Register 1 */
        u32     pcdr1;          /* 0x104 Periperial Clock Disable Register 1 */
@@ -147,6 +147,10 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_PCKRDY3           0x00000800
 #define AT91_PMC_IXR_MOSCSELS          0x00010000
 
+#define AT91_PMC_PCR_PID_MASK          (0x3f)
+#define AT91_PMC_PCR_CMD_WRITE         (0x1 << 12)
+#define AT91_PMC_PCR_EN                        (0x1 << 28)
+
 #define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define                AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
 #define                AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
index ce9e28f..4076a78 100644 (file)
@@ -80,4 +80,5 @@ static inline unsigned long get_mci_clk_rate(void)
 
 int at91_clock_init(unsigned long main_clock);
 void at91_periph_clk_enable(int id);
+void at91_periph_clk_disable(int id);
 #endif /* __ASM_ARM_ARCH_CLK_H__ */
index 6d936f4..f7bc4ad 100644 (file)
 #define ATMEL_PIO_PORTS                5
 #define CPU_HAS_PIO3
 #define PIO_SCDR_DIV           0x3fff
+#define CPU_HAS_PCR
 
 /*
  * PMECC table in ROM
index 6caa9b6..a859b6d 100644 (file)
@@ -14,7 +14,8 @@
 #define AT91_ASM_SMC_SETUP0    (ATMEL_BASE_SMC + 0x600)
 #define AT91_ASM_SMC_PULSE0    (ATMEL_BASE_SMC + 0x604)
 #define AT91_ASM_SMC_CYCLE0    (ATMEL_BASE_SMC + 0x608)
-#define AT91_ASM_SMC_MODE0     (ATMEL_BASE_SMC + 0x60C)
+#define AT91_ASM_SMC_TIMINGS0  (ATMEL_BASE_SMC + 0x60c)
+#define AT91_ASM_SMC_MODE0     (ATMEL_BASE_SMC + 0x610)
 #else
 struct at91_cs {
        u32     setup;          /* 0x600 SMC Setup Register */
diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h
new file mode 100644 (file)
index 0000000..fd36bb0
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
+#define __ASM_ARCH_LS102XA_CLOCK_H_
+
+#include <common.h>
+
+enum mxc_clock {
+       MXC_ARM_CLK = 0,
+       MXC_UART_CLK,
+       MXC_ESDHC_CLK,
+       MXC_I2C_CLK,
+       MXC_DSPI_CLK,
+};
+
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
new file mode 100644 (file)
index 0000000..ed78c33
--- /dev/null
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2014, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV7_LS102XA_CONFIG_
+#define _ASM_ARMV7_LS102XA_CONFIG_
+
+#define CONFIG_SYS_CACHELINE_SIZE              64
+
+#define OCRAM_BASE_ADDR                                0x10000000
+#define OCRAM_SIZE                             0x00020000
+
+#define CONFIG_SYS_IMMR                                0x01000000
+
+#define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
+#define CONFIG_SYS_FSL_SCFG_ADDR               (CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_SERDES_ADDR             (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_LS1_CLK_ADDR            (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011c0500)
+#define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_DCU_ADDR                    (CONFIG_SYS_IMMR + 0x01ce0000)
+
+#define CONFIG_SYS_TSEC1_OFFSET                        0x01d10000
+#define CONFIG_SYS_TSEC2_OFFSET                        0x01d50000
+#define CONFIG_SYS_TSEC3_OFFSET                        0x01d90000
+#define CONFIG_SYS_MDIO1_OFFSET                        0x01d24000
+
+#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
+#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+
+#define SCTR_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01b00000)
+
+#define I2C1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01180000)
+#define I2C2_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01190000)
+#define I2C3_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x011a0000)
+
+#define WDOG1_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x01ad0000)
+
+#define QSPI0_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x00550000)
+#define DSPI1_BASE_ADDR                                (CONFIG_SYS_IMMR + 0x01100000)
+
+#define LPUART_BASE                            (CONFIG_SYS_IMMR + 0x01950000)
+
+#ifdef CONFIG_DDR_SPD
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
+#define CONFIG_SYS_FSL_DDR
+#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE         ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+#endif
+
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_DCU_BE
+
+#define DCU_LAYER_MAX_NUM                      16
+
+#define CONFIG_SYS_FSL_SRDS_1
+
+#ifdef CONFIG_LS102XA
+#define CONFIG_MAX_CPUS                                2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
+#define CONFIG_NUM_DDR_CONTROLLERS             1
+#else
+#error SoC not defined
+#endif
+
+#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
new file mode 100644 (file)
index 0000000..3a92f5a
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+enum srds_prtcl {
+       NONE = 0,
+       PCIE1,
+       PCIE2,
+       SATA1,
+       SGMII_TSEC1,
+       SGMII_TSEC2,
+};
+
+enum srds {
+       FSL_SRDS_1  = 0,
+       FSL_SRDS_2  = 1,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+const char *serdes_clock_to_string(u32 clock);
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+
+#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
new file mode 100644 (file)
index 0000000..7995fe2
--- /dev/null
@@ -0,0 +1,493 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
+#define __ASM_ARCH_LS102XA_IMMAP_H_
+
+#define SVR_MAJ(svr)           (((svr) >>  4) & 0xf)
+#define SVR_MIN(svr)           (((svr) >>  0) & 0xf)
+#define SVR_SOC_VER(svr)       (((svr) >> 8) & 0x7ff)
+#define IS_E_PROCESSOR(svr)    (svr & 0x80000)
+
+#define SOC_VER_SLS1020                0x00
+#define SOC_VER_LS1020         0x10
+#define SOC_VER_LS1021         0x11
+#define SOC_VER_LS1022         0x12
+
+#define RCWSR0_SYS_PLL_RAT_SHIFT       25
+#define RCWSR0_SYS_PLL_RAT_MASK                0x1f
+#define RCWSR0_MEM_PLL_RAT_SHIFT       16
+#define RCWSR0_MEM_PLL_RAT_MASK                0x3f
+
+#define RCWSR4_SRDS1_PRTCL_SHIFT       24
+#define RCWSR4_SRDS1_PRTCL_MASK                0xff000000
+
+#define TIMER_COMP_VAL                 0xffffffff
+#define ARCH_TIMER_CTRL_ENABLE         (1 << 0)
+#define SYS_COUNTER_CTRL_ENABLE                (1 << 24)
+
+struct sys_info {
+       unsigned long freq_processor[CONFIG_MAX_CPUS];
+       unsigned long freq_systembus;
+       unsigned long freq_ddrbus;
+       unsigned long freq_localbus;
+};
+
+/* Device Configuration and Pin Control */
+struct ccsr_gur {
+       u32     porsr1;         /* POR status 1 */
+       u32     porsr2;         /* POR status 2 */
+       u8      res_008[0x20-0x8];
+       u32     gpporcr1;       /* General-purpose POR configuration */
+       u32     gpporcr2;
+       u32     dcfg_fusesr;    /* Fuse status register */
+       u8      res_02c[0x70-0x2c];
+       u32     devdisr;        /* Device disable control */
+       u32     devdisr2;       /* Device disable control 2 */
+       u32     devdisr3;       /* Device disable control 3 */
+       u32     devdisr4;       /* Device disable control 4 */
+       u32     devdisr5;       /* Device disable control 5 */
+       u8      res_084[0x94-0x84];
+       u32     coredisru;      /* uppper portion for support of 64 cores */
+       u32     coredisrl;      /* lower portion for support of 64 cores */
+       u8      res_09c[0xa4-0x9c];
+       u32     svr;            /* System version */
+       u8      res_0a8[0xb0-0xa8];
+       u32     rstcr;          /* Reset control */
+       u32     rstrqpblsr;     /* Reset request preboot loader status */
+       u8      res_0b8[0xc0-0xb8];
+       u32     rstrqmr1;       /* Reset request mask */
+       u8      res_0c4[0xc8-0xc4];
+       u32     rstrqsr1;       /* Reset request status */
+       u8      res_0cc[0xd4-0xcc];
+       u32     rstrqwdtmrl;    /* Reset request WDT mask */
+       u8      res_0d8[0xdc-0xd8];
+       u32     rstrqwdtsrl;    /* Reset request WDT status */
+       u8      res_0e0[0xe4-0xe0];
+       u32     brrl;           /* Boot release */
+       u8      res_0e8[0x100-0xe8];
+       u32     rcwsr[16];      /* Reset control word status */
+       u8      res_140[0x200-0x140];
+       u32     scratchrw[4];  /* Scratch Read/Write */
+       u8      res_210[0x300-0x210];
+       u32     scratchw1r[4];  /* Scratch Read (Write once) */
+       u8      res_310[0x400-0x310];
+       u32     crstsr;
+       u8      res_404[0x550-0x404];
+       u32     sataliodnr;
+       u8      res_554[0x604-0x554];
+       u32     pamubypenr;
+       u32     dmacr1;
+       u8      res_60c[0x740-0x60c];   /* add more registers when needed */
+       u32     tp_ityp[64];    /* Topology Initiator Type Register */
+       struct {
+               u32     upper;
+               u32     lower;
+       } tp_cluster[1];        /* Core Cluster n Topology Register */
+       u8      res_848[0xe60-0x848];
+       u32     ddrclkdr;
+       u8      res_e60[0xe68-0xe64];
+       u32     ifcclkdr;
+       u8      res_e68[0xe80-0xe6c];
+       u32     sdhcpcr;
+};
+
+#define SCFG_SCFGREVCR_REV             0xffffffff
+#define SCFG_SCFGREVCR_NOREV           0
+#define SCFG_ETSECDMAMCR_LE_BD_FR      0xf8001a0f
+#define SCFG_ETSECCMCR_GE2_CLK125      0x04000000
+#define SCFG_PIXCLKCR_PXCKEN           0x80000000
+
+/* Supplemental Configuration Unit */
+struct ccsr_scfg {
+       u32 dpslpcr;
+       u32 resv0[2];
+       u32 etsecclkdpslpcr;
+       u32 resv1[5];
+       u32 fuseovrdcr;
+       u32 pixclkcr;
+       u32 resv2[5];
+       u32 spimsicr;
+       u32 resv3[6];
+       u32 pex1pmwrcr;
+       u32 pex1pmrdsr;
+       u32 resv4[3];
+       u32 usb3prm1cr;
+       u32 usb4prm2cr;
+       u32 pex1rdmsgpldlsbsr;
+       u32 pex1rdmsgpldmsbsr;
+       u32 pex2rdmsgpldlsbsr;
+       u32 pex2rdmsgpldmsbsr;
+       u32 pex1rdmmsgrqsr;
+       u32 pex2rdmmsgrqsr;
+       u32 spimsiclrcr;
+       u32 pex1mscportsr;
+       u32 pex2mscportsr;
+       u32 pex2pmwrcr;
+       u32 resv5[24];
+       u32 mac1_streamid;
+       u32 mac2_streamid;
+       u32 mac3_streamid;
+       u32 pex1_streamid;
+       u32 pex2_streamid;
+       u32 dma_streamid;
+       u32 sata_streamid;
+       u32 usb3_streamid;
+       u32 qe_streamid;
+       u32 sdhc_streamid;
+       u32 adma_streamid;
+       u32 letechsftrstcr;
+       u32 core0_sft_rst;
+       u32 core1_sft_rst;
+       u32 resv6[1];
+       u32 usb_hi_addr;
+       u32 etsecclkadjcr;
+       u32 sai_clk;
+       u32 resv7[1];
+       u32 dcu_streamid;
+       u32 usb2_streamid;
+       u32 ftm_reset;
+       u32 altcbar;
+       u32 qspi_cfg;
+       u32 pmcintecr;
+       u32 pmcintlecr;
+       u32 pmcintsr;
+       u32 qos1;
+       u32 qos2;
+       u32 qos3;
+       u32 cci_cfg;
+       u32 resv8[1];
+       u32 etsecdmamcr;
+       u32 usb3prm3cr;
+       u32 resv9[1];
+       u32 debug_streamid;
+       u32 resv10[5];
+       u32 snpcnfgcr;
+       u32 resv11[1];
+       u32 intpcr;
+       u32 resv12[20];
+       u32 scfgrevcr;
+       u32 coresrencr;
+       u32 pex2pmrdsr;
+       u32 ddrc1cr;
+       u32 ddrc2cr;
+       u32 ddrc3cr;
+       u32 ddrc4cr;
+       u32 ddrgcr;
+       u32 resv13[120];
+       u32 qeioclkcr;
+       u32 etsecmcr;
+       u32 sdhciovserlcr;
+       u32 resv14[61];
+       u32 sparecr;
+};
+
+/* Clocking */
+struct ccsr_clk {
+       struct {
+               u32 clkcncsr;   /* core cluster n clock control status */
+               u8  res_004[0x1c];
+       } clkcsr[2];
+       u8      res_040[0x7c0]; /* 0x100 */
+       struct {
+               u32 pllcngsr;
+               u8 res_804[0x1c];
+       } pllcgsr[2];
+       u8      res_840[0x1c0];
+       u32     clkpcsr;        /* 0xa00 Platform clock domain control/status */
+       u8      res_a04[0x1fc];
+       u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
+       u8      res_c04[0x1c];
+       u32     plldgsr;        /* 0xc20 DDR PLL General Status */
+       u8      res_c24[0x3dc];
+};
+
+/* System Counter */
+struct sctr_regs {
+       u32 cntcr;
+       u32 cntsr;
+       u32 cntcv1;
+       u32 cntcv2;
+       u32 resv1[4];
+       u32 cntfid0;
+       u32 cntfid1;
+       u32 resv2[1002];
+       u32 counterid[12];
+};
+
+#define MAX_SERDES                     1
+#define SRDS_MAX_LANES                 4
+#define SRDS_MAX_BANK                  2
+
+#define SRDS_RSTCTL_RST                        0x80000000
+#define SRDS_RSTCTL_RSTDONE            0x40000000
+#define SRDS_RSTCTL_RSTERR             0x20000000
+#define SRDS_RSTCTL_SWRST              0x10000000
+#define SRDS_RSTCTL_SDEN               0x00000020
+#define SRDS_RSTCTL_SDRST_B            0x00000040
+#define SRDS_RSTCTL_PLLRST_B           0x00000080
+#define SRDS_PLLCR0_POFF               0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK      0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100       0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125       0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25    0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150       0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13    0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88    0x50000000
+#define SRDS_PLLCR0_PLL_LCK            0x00800000
+#define SRDS_PLLCR0_FRATE_SEL_MASK     0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5                0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75     0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15     0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4                0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12     0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3                0x000a0000
+#define SRDS_PLLCR1_PLL_BWSEL          0x08000000
+
+struct ccsr_serdes {
+       struct {
+               u32     rstctl; /* Reset Control Register */
+
+               u32     pllcr0; /* PLL Control Register 0 */
+
+               u32     pllcr1; /* PLL Control Register 1 */
+               u32     res_0c; /* 0x00c */
+               u32     pllcr3;
+               u32     pllcr4;
+               u8      res_18[0x20-0x18];
+       } bank[2];
+       u8      res_40[0x90-0x40];
+       u32     srdstcalcr;     /* 0x90 TX Calibration Control */
+       u8      res_94[0xa0-0x94];
+       u32     srdsrcalcr;     /* 0xa0 RX Calibration Control */
+       u8      res_a4[0xb0-0xa4];
+       u32     srdsgr0;        /* 0xb0 General Register 0 */
+       u8      res_b4[0xe0-0xb4];
+       u32     srdspccr0;      /* 0xe0 Protocol Converter Config 0 */
+       u32     srdspccr1;      /* 0xe4 Protocol Converter Config 1 */
+       u32     srdspccr2;      /* 0xe8 Protocol Converter Config 2 */
+       u32     srdspccr3;      /* 0xec Protocol Converter Config 3 */
+       u32     srdspccr4;      /* 0xf0 Protocol Converter Config 4 */
+       u8      res_f4[0x100-0xf4];
+       struct {
+               u32     lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+               u8      res_104[0x120-0x104];
+       } srdslnpssr[4];
+       u8      res_180[0x300-0x180];
+       u32     srdspexeqcr;
+       u32     srdspexeqpcr[11];
+       u8      res_330[0x400-0x330];
+       u32     srdspexapcr;
+       u8      res_404[0x440-0x404];
+       u32     srdspexbpcr;
+       u8      res_444[0x800-0x444];
+       struct {
+               u32     gcr0;   /* 0x800 General Control Register 0 */
+               u32     gcr1;   /* 0x804 General Control Register 1 */
+               u32     gcr2;   /* 0x808 General Control Register 2 */
+               u32     sscr0;
+               u32     recr0;  /* 0x810 Receive Equalization Control */
+               u32     recr1;
+               u32     tecr0;  /* 0x818 Transmit Equalization Control */
+               u32     sscr1;
+               u32     ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
+               u8      res_824[0x83c-0x824];
+               u32     tcsr3;
+       } lane[4];      /* Lane A, B, C, D, E, F, G, H */
+       u8      res_a00[0x1000-0xa00];  /* from 0xa00 to 0xfff */
+};
+
+#define DDR_SDRAM_CFG                  0x470c0008
+#define DDR_CS0_BNDS                   0x008000bf
+#define DDR_CS0_CONFIG                 0x80014302
+#define DDR_TIMING_CFG_0               0x50550004
+#define DDR_TIMING_CFG_1               0xbcb38c56
+#define DDR_TIMING_CFG_2               0x0040d120
+#define DDR_TIMING_CFG_3               0x010e1000
+#define DDR_TIMING_CFG_4               0x00000001
+#define DDR_TIMING_CFG_5               0x03401400
+#define DDR_SDRAM_CFG_2                        0x00401010
+#define DDR_SDRAM_MODE                 0x00061c60
+#define DDR_SDRAM_MODE_2               0x00180000
+#define DDR_SDRAM_INTERVAL             0x18600618
+#define DDR_DDR_WRLVL_CNTL             0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2           0x05060607
+#define DDR_DDR_WRLVL_CNTL_3           0x05050505
+#define DDR_DDR_CDR1                   0x80040000
+#define DDR_DDR_CDR2                   0x00000001
+#define DDR_SDRAM_CLK_CNTL             0x02000000
+#define DDR_DDR_ZQ_CNTL                        0x89080600
+#define DDR_CS0_CONFIG_2               0
+#define DDR_SDRAM_CFG_MEM_EN           0x80000000
+
+/* DDR memory controller registers */
+struct ccsr_ddr {
+       u32 cs0_bnds;                   /* Chip Select 0 Memory Bounds */
+       u32 resv1[1];
+       u32 cs1_bnds;                   /* Chip Select 1 Memory Bounds */
+       u32 resv2[1];
+       u32 cs2_bnds;                   /* Chip Select 2 Memory Bounds */
+       u32 resv3[1];
+       u32 cs3_bnds;                   /* Chip Select 3 Memory Bounds */
+       u32 resv4[25];
+       u32 cs0_config;                 /* Chip Select Configuration */
+       u32 cs1_config;                 /* Chip Select Configuration */
+       u32 cs2_config;                 /* Chip Select Configuration */
+       u32 cs3_config;                 /* Chip Select Configuration */
+       u32 resv5[12];
+       u32 cs0_config_2;               /* Chip Select Configuration 2 */
+       u32 cs1_config_2;               /* Chip Select Configuration 2 */
+       u32 cs2_config_2;               /* Chip Select Configuration 2 */
+       u32 cs3_config_2;               /* Chip Select Configuration 2 */
+       u32 resv6[12];
+       u32 timing_cfg_3;               /* SDRAM Timing Configuration 3 */
+       u32 timing_cfg_0;               /* SDRAM Timing Configuration 0 */
+       u32 timing_cfg_1;               /* SDRAM Timing Configuration 1 */
+       u32 timing_cfg_2;               /* SDRAM Timing Configuration 2 */
+       u32 sdram_cfg;                  /* SDRAM Control Configuration */
+       u32 sdram_cfg_2;                /* SDRAM Control Configuration 2 */
+       u32 sdram_mode;                 /* SDRAM Mode Configuration */
+       u32 sdram_mode_2;               /* SDRAM Mode Configuration 2 */
+       u32 sdram_md_cntl;              /* SDRAM Mode Control */
+       u32 sdram_interval;             /* SDRAM Interval Configuration */
+       u32 sdram_data_init;            /* SDRAM Data initialization */
+       u32 resv7[1];
+       u32 sdram_clk_cntl;             /* SDRAM Clock Control */
+       u32 resv8[5];
+       u32 init_addr;                  /* training init addr */
+       u32 init_ext_addr;              /* training init extended addr */
+       u32 resv9[4];
+       u32 timing_cfg_4;               /* SDRAM Timing Configuration 4 */
+       u32 timing_cfg_5;               /* SDRAM Timing Configuration 5 */
+       u32 timing_cfg_6;               /* SDRAM Timing Configuration 6 */
+       u32 timing_cfg_7;               /* SDRAM Timing Configuration 7 */
+       u32 ddr_zq_cntl;                /* ZQ calibration control*/
+       u32 ddr_wrlvl_cntl;             /* write leveling control*/
+       u32 resv10[1];
+       u32 ddr_sr_cntr;                /* self refresvh counter */
+       u32 ddr_sdram_rcw_1;            /* Control Words 1 */
+       u32 ddr_sdram_rcw_2;            /* Control Words 2 */
+       u32 resv11[2];
+       u32 ddr_wrlvl_cntl_2;           /* write leveling control 2 */
+       u32 ddr_wrlvl_cntl_3;           /* write leveling control 3 */
+       u32 resv12[2];
+       u32 ddr_sdram_rcw_3;            /* Control Words 3 */
+       u32 ddr_sdram_rcw_4;            /* Control Words 4 */
+       u32 ddr_sdram_rcw_5;            /* Control Words 5 */
+       u32 ddr_sdram_rcw_6;            /* Control Words 6 */
+       u32 resv13[20];
+       u32 sdram_mode_3;               /* SDRAM Mode Configuration 3 */
+       u32 sdram_mode_4;               /* SDRAM Mode Configuration 4 */
+       u32 sdram_mode_5;               /* SDRAM Mode Configuration 5 */
+       u32 sdram_mode_6;               /* SDRAM Mode Configuration 6 */
+       u32 sdram_mode_7;               /* SDRAM Mode Configuration 7 */
+       u32 sdram_mode_8;               /* SDRAM Mode Configuration 8 */
+       u32 sdram_mode_9;               /* SDRAM Mode Configuration 9 */
+       u32 sdram_mode_10;              /* SDRAM Mode Configuration 10 */
+       u32 sdram_mode_11;              /* SDRAM Mode Configuration 11 */
+       u32 sdram_mode_12;              /* SDRAM Mode Configuration 12 */
+       u32 sdram_mode_13;              /* SDRAM Mode Configuration 13 */
+       u32 sdram_mode_14;              /* SDRAM Mode Configuration 14 */
+       u32 sdram_mode_15;              /* SDRAM Mode Configuration 15 */
+       u32 sdram_mode_16;              /* SDRAM Mode Configuration 16 */
+       u32 resv14[4];
+       u32 timing_cfg_8;               /* SDRAM Timing Configuration 8 */
+       u32 timing_cfg_9;               /* SDRAM Timing Configuration 9 */
+       u32 resv15[2];
+       u32 sdram_cfg_3;                /* SDRAM Control Configuration 3 */
+       u32 resv16[15];
+       u32 deskew_cntl;                /* SDRAM Deskew Control */
+       u32 resv17[545];
+       u32 ddr_dsr1;                   /* Debug Status 1 */
+       u32 ddr_dsr2;                   /* Debug Status 2 */
+       u32 ddr_cdr1;                   /* Control Driver 1 */
+       u32 ddr_cdr2;                   /* Control Driver 2 */
+       u32 resv18[50];
+       u32 ip_rev1;                    /* IP Block Revision 1 */
+       u32 ip_rev2;                    /* IP Block Revision 2 */
+       u32 eor;                        /* Enhanced Optimization Register */
+       u32 resv19[63];
+       u32 mtcr;                       /* Memory Test Control Register */
+       u32 resv20[7];
+       u32 mtp1;                       /* Memory Test Pattern 1 */
+       u32 mtp2;                       /* Memory Test Pattern 2 */
+       u32 mtp3;                       /* Memory Test Pattern 3 */
+       u32 mtp4;                       /* Memory Test Pattern 4 */
+       u32 mtp5;                       /* Memory Test Pattern 5 */
+       u32 mtp6;                       /* Memory Test Pattern 6 */
+       u32 mtp7;                       /* Memory Test Pattern 7 */
+       u32 mtp8;                       /* Memory Test Pattern 8 */
+       u32 mtp9;                       /* Memory Test Pattern 9 */
+       u32 mtp10;                      /* Memory Test Pattern 10 */
+       u32 resv21[6];
+       u32 ddr_mt_st_ext_addr;         /* Memory Test Start Extended Address */
+       u32 ddr_mt_st_addr;             /* Memory Test Start Address */
+       u32 ddr_mt_end_ext_addr;        /* Memory Test End Extended Address */
+       u32 ddr_mt_end_addr;            /* Memory Test End Address */
+       u32 resv22[36];
+       u32 data_err_inject_hi;         /* Data Path Err Injection Mask High */
+       u32 data_err_inject_lo;         /* Data Path Err Injection Mask Low */
+       u32 ecc_err_inject;             /* Data Path Err Injection Mask ECC */
+       u32 resv23[5];
+       u32 capture_data_hi;            /* Data Path Read Capture High */
+       u32 capture_data_lo;            /* Data Path Read Capture Low */
+       u32 capture_ecc;                /* Data Path Read Capture ECC */
+       u32 resv24[5];
+       u32 err_detect;                 /* Error Detect */
+       u32 err_disable;                /* Error Disable */
+       u32 err_int_en;
+       u32 capture_attributes;         /* Error Attrs Capture */
+       u32 capture_address;            /* Error Addr Capture */
+       u32 capture_ext_address;        /* Error Extended Addr Capture */
+       u32 err_sbe;                    /* Single-Bit ECC Error Management */
+       u32 resv25[105];
+};
+
+#define CCI400_CTRLORD_TERM_BARRIER    0x00000008
+#define CCI400_CTRLORD_EN_BARRIER      0
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+       u32 ctrl_ord;                   /* Control Override */
+       u32 spec_ctrl;                  /* Speculation Control */
+       u32 secure_access;              /* Secure Access */
+       u32 status;                     /* Status */
+       u32 impr_err;                   /* Imprecise Error */
+       u8 res_14[0x100 - 0x14];
+       u32 pmcr;                       /* Performance Monitor Control */
+       u8 res_104[0xfd0 - 0x104];
+       u32 pid[8];                     /* Peripheral ID */
+       u32 cid[4];                     /* Component ID */
+       struct {
+               u32 snoop_ctrl;         /* Snoop Control */
+               u32 sha_ord;            /* Shareable Override */
+               u8 res_1008[0x1100 - 0x1008];
+               u32 rc_qos_ord;         /* read channel QoS Value Override */
+               u32 wc_qos_ord;         /* read channel QoS Value Override */
+               u8 res_1108[0x110c - 0x1108];
+               u32 qos_ctrl;           /* QoS Control */
+               u32 max_ot;             /* Max OT */
+               u8 res_1114[0x1130 - 0x1114];
+               u32 target_lat;         /* Target Latency */
+               u32 latency_regu;       /* Latency Regulation */
+               u32 qos_range;          /* QoS Range */
+               u8 res_113c[0x2000 - 0x113c];
+       } slave[5];                     /* Slave Interface */
+       u8 res_6000[0x9004 - 0x6000];
+       u32 cycle_counter;              /* Cycle counter */
+       u32 count_ctrl;                 /* Count Control */
+       u32 overflow_status;            /* Overflow Flag Status */
+       u8 res_9010[0xa000 - 0x9010];
+       struct {
+               u32 event_select;       /* Event Select */
+               u32 event_count;        /* Event Count */
+               u32 counter_ctrl;       /* Counter Control */
+               u32 overflow_status;    /* Overflow Flag Status */
+               u8 res_a010[0xb000 - 0xa010];
+       } pcounter[4];                  /* Performance Counter */
+       u8 res_e004[0x10000 - 0xe004];
+};
+#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/imx-regs.h b/arch/arm/include/asm/arch-ls102xa/imx-regs.h
new file mode 100644 (file)
index 0000000..f9cd75b
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define I2C_QUIRK_REG  /* enable 8-bit driver */
+
+#ifdef CONFIG_LPUART_32B_REG
+struct lpuart_fsl {
+       u32 baud;
+       u32 stat;
+       u32 ctrl;
+       u32 data;
+       u32 match;
+       u32 modir;
+       u32 fifo;
+       u32 water;
+};
+#else
+struct lpuart_fsl {
+       u8 ubdh;
+       u8 ubdl;
+       u8 uc1;
+       u8 uc2;
+       u8 us1;
+       u8 us2;
+       u8 uc3;
+       u8 ud;
+       u8 uma1;
+       u8 uma2;
+       u8 uc4;
+       u8 uc5;
+       u8 ued;
+       u8 umodem;
+       u8 uir;
+       u8 reserved;
+       u8 upfifo;
+       u8 ucfifo;
+       u8 usfifo;
+       u8 utwfifo;
+       u8 utcfifo;
+       u8 urwfifo;
+       u8 urcfifo;
+       u8 rsvd[28];
+};
+#endif
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
index 44cd455..7334e0c 100644 (file)
@@ -6,6 +6,8 @@
 #ifndef _TEGRA_GPIO_H_
 #define _TEGRA_GPIO_H_
 
+#define TEGRA_GPIOS_PER_PORT   8
+#define TEGRA_PORTS_PER_BANK   4
 #define MAX_NUM_GPIOS           (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
 #define GPIO_NAME_SIZE         20      /* gpio_request max label len */
 
@@ -25,9 +27,14 @@ struct tegra_gpio_config {
        u32 init:2;
 };
 
-/*
- * Tegra-specific GPIO API
+/**
+ * tegra_spl_gpio_direction_output() - set the output value of a GPIO
+ *
+ * This function is only used from SPL on seaboard, which needs to enable a
+ * GPIO to get the UART running. It could be done in U-Boot rather than SPL,
+ * but for now, this gets it working
  */
+int tegra_spl_gpio_direction_output(int gpio, int value);
 
 /**
  * Configure a list of GPIOs
@@ -37,8 +44,4 @@ struct tegra_gpio_config {
  */
 void gpio_config_table(const struct tegra_gpio_config *config, int len);
 
-void gpio_info(void);
-
-#define gpio_status()  gpio_info()
-
 #endif /* TEGRA_GPIO_H_ */
index 5f2a5f4..be80434 100644 (file)
@@ -23,4 +23,8 @@
 #include <asm/arch-fsl-lsch3/config.h>
 #endif
 
+#ifdef CONFIG_LS102XA
+#include <asm/arch/config.h>
+#endif
+
 #endif
index 88ecddb..bfbe0a0 100644 (file)
@@ -376,7 +376,12 @@ out:
        return retval;
 }
 
-#elif !defined(readb)
+#else
+#define memset_io(a, b, c)             memset((void *)(a), (b), (c))
+#define memcpy_fromio(a, b, c)         memcpy((a), (void *)(b), (c))
+#define memcpy_toio(a, b, c)           memcpy((void *)(a), (b), (c))
+
+#if !defined(readb)
 
 #define readb(addr)                    (__readwrite_bug("readb"),0)
 #define readw(addr)                    (__readwrite_bug("readw"),0)
@@ -389,6 +394,7 @@ out:
 
 #define check_signature(io,sig,len)    (0)
 
+#endif
 #endif /* __mem_pci */
 
 /*
index 75ab546..dfcc596 100644 (file)
@@ -28,6 +28,9 @@ void __weak board_init_f(ulong dummy)
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
 
+       /* Set global data pointer. */
+       gd = &gdata;
+
        board_init_r(NULL, 0);
 }
 
index 46337ae..66de2ad 100644 (file)
@@ -2,7 +2,6 @@ menu "AVR32 architecture"
        depends on AVR32
 
 config SYS_ARCH
-       string
        default "avr32"
 
 choice
index bb8a133..31913fe 100644 (file)
@@ -2,7 +2,6 @@ menu "Blackfin architecture"
        depends on BLACKFIN
 
 config SYS_ARCH
-       string
        default "blackfin"
 
 choice
index 6cda7db..5374b4d 100644 (file)
@@ -2,7 +2,6 @@ menu "M68000 architecture"
        depends on M68K
 
 config SYS_ARCH
-       string
        default "m68k"
 
 choice
index ddaa45f..33bfd9f 100644 (file)
@@ -2,7 +2,6 @@ menu "MicroBlaze architecture"
        depends on MICROBLAZE
 
 config SYS_ARCH
-       string
        default "microblaze"
 
 choice
index 38dc5aa..ccc6235 100644 (file)
@@ -27,7 +27,11 @@ typedef int          __kernel_pid_t;
 typedef unsigned short __kernel_ipc_pid_t;
 typedef unsigned int   __kernel_uid_t;
 typedef unsigned int   __kernel_gid_t;
+#ifdef __GNUC__
+typedef __SIZE_TYPE__  __kernel_size_t;
+#else
 typedef unsigned int   __kernel_size_t;
+#endif
 typedef int            __kernel_ssize_t;
 typedef int            __kernel_ptrdiff_t;
 typedef long           __kernel_time_t;
index 5bf0df4..7686b77 100644 (file)
@@ -2,7 +2,6 @@ menu "MIPS architecture"
        depends on MIPS
 
 config SYS_ARCH
-       string
        default "mips"
 
 choice
index 743a8fe..81b0a01 100644 (file)
@@ -2,7 +2,6 @@ menu "NDS32 architecture"
        depends on NDS32
 
 config SYS_ARCH
-       string
        default "nds32"
 
 choice
index 0cba45b..b3be7b5 100644 (file)
@@ -2,7 +2,6 @@ menu "Nios II architecture"
        depends on NIOS2
 
 config SYS_ARCH
-       string
        default "nios2"
 
 choice
index cc54a2e..4d62b4c 100644 (file)
@@ -2,7 +2,6 @@ menu "OpenRISC architecture"
        depends on OPENRISC
 
 config SYS_ARCH
-       string
        default "openrisc"
 
 choice
index 3325af3..6f96c7c 100644 (file)
@@ -2,7 +2,6 @@ menu "PowerPC architecture"
        depends on PPC
 
 config SYS_ARCH
-       string
        default "powerpc"
 
 choice
index 6ce464d..3378c91 100644 (file)
@@ -2,7 +2,6 @@ menu "74xx_7xx CPU"
        depends on 74xx_7xx
 
 config SYS_CPU
-       string
        default "74xx_7xx"
 
 choice
index bfc4eae..a0f0ede 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc512x CPU"
        depends on MPC512X
 
 config SYS_CPU
-       string
        default "mpc512x"
 
 choice
index 79579d7..aad4a7c 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc5xx CPU"
        depends on 5xx
 
 config SYS_CPU
-       string
        default "mpc5xx"
 
 choice
index b2f0bad..cca58e5 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc5xxx CPU"
        depends on MPC5xxx
 
 config SYS_CPU
-       string
        default "mpc5xxx"
 
 choice
index 309833f..4f98423 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc824x CPU"
        depends on MPC824X
 
 config SYS_CPU
-       string
        default "mpc824x"
 
 choice
index 1a8707d..41e4e5f 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc8260 CPU"
        depends on MPC8260
 
 config SYS_CPU
-       string
        default "mpc8260"
 
 choice
index 5fd3393..6de9265 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc83xx CPU"
        depends on MPC83xx
 
 config SYS_CPU
-       string
        default "mpc83xx"
 
 choice
index 0f70380..8c1c01c 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc85xx CPU"
        depends on MPC85xx
 
 config SYS_CPU
-       string
        default "mpc85xx"
 
 choice
index f0ff441..14e8b1a 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc86xx CPU"
        depends on MPC86xx
 
 config SYS_CPU
-       string
        default "mpc86xx"
 
 choice
index 2c39244..f1dca90 100644 (file)
@@ -2,7 +2,6 @@ menu "mpc8xx CPU"
        depends on 8xx
 
 config SYS_CPU
-       string
        default "mpc8xx"
 
 choice
index 2d15dd1..41b525c 100644 (file)
@@ -2,7 +2,6 @@ menu "ppc4xx CPU"
        depends on 4xx
 
 config SYS_CPU
-       string
        default "ppc4xx"
 
 choice
diff --git a/arch/powerpc/include/asm/fsl_enet.h b/arch/powerpc/include/asm/fsl_enet.h
deleted file mode 100644 (file)
index 96146b6..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include <phy.h>
-
-struct tsec_mii_mng {
-       u32 miimcfg;            /* MII management configuration reg */
-       u32 miimcom;            /* MII management command reg */
-       u32 miimadd;            /* MII management address reg */
-       u32 miimcon;            /* MII management control reg */
-       u32 miimstat;           /* MII management status reg  */
-       u32 miimind;            /* MII management indication reg */
-       u32 ifstat;             /* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
index c393550..3057325 100644 (file)
@@ -2,15 +2,12 @@ menu "Sandbox architecture"
        depends on SANDBOX
 
 config SYS_ARCH
-       string
        default "sandbox"
 
 config SYS_BOARD
-       string
        default "sandbox"
 
 config SYS_CONFIG_NAME
-       string
        default "sandbox"
 
 endmenu