]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
karo: tx51: reduce DDR clock to 166 MHz for TX51-8xx1
authorLothar Waßmann <LW@KARO-electronics.de>
Fri, 6 Dec 2013 08:50:19 +0000 (09:50 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 6 Dec 2013 08:50:19 +0000 (09:50 +0100)
board/karo/tx51/tx51.c
boards.cfg
doc/README.KARO-TX51
include/configs/tx51.h

index 11ec4f6291ebf0e4be0bcbc31789f89514d7c453..30296710fb3fbc1fc29370f43fc3e75c48c0f178 100644 (file)
@@ -1054,10 +1054,11 @@ exit:
 int checkboard(void)
 {
        tx51_print_cpuinfo();
-
-       printf("Board: Ka-Ro TX51-%sxx%s\n",
-               TX51_MOD_PREFIX, TX51_MOD_SUFFIX);
-
+#if CONFIG_NR_DRAM_BANKS > 1
+       printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
+#else
+       printf("Board: Ka-Ro TX51-8xx0\n");
+#endif
        return 0;
 }
 
index 5a5c0e1eb89052d60da3a3400b574eb49ffa9677..8a1a7fc8d0e2911a1953e0f2778a637fc25fe2bb 100644 (file)
@@ -270,9 +270,8 @@ mx53smd                      arm         armv7       mx53smd             freesca
 ima3-mx53                    arm         armv7       ima3-mx53           esg            mx5            ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
 vision2                      arm         armv7       vision2             ttcontrol      mx5            vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 cgtqmx6qeval                 arm         armv7       cgtqmx6eval         congatec      mx6             cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
-tx51-8xx0                    arm         armv7       tx51                karo          mx5             tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166
-tx51-8xx1                    arm         armv7       tx51                karo          mx5             tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200
-tx51-8xx2                    arm         armv7       tx51                karo          mx5             tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166
+tx51-8xx0                    arm         armv7       tx51                karo          mx5             tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1
+tx51-8xx1_2                  arm         armv7       tx51                karo          mx5             tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2
 tx53-xx30                    arm         armv7       tx53                karo          mx5             tx53:NR_DRAM_BANKS=1
 tx53-xx31                    arm         armv7       tx53                karo          mx5             tx53:NR_DRAM_BANKS=2
 tx6u-8x10                    arm         armv7       tx6                 karo          mx6             tx6:MX6DL
index efb2236ae7b3d7f03694e4ee058052126e217d97..078e8362ef7047eb4ac32aae0d6a9b38bde2dedb 100644 (file)
@@ -4,12 +4,17 @@
 Building U-Boot
 ---------------
 
-Note: There are currently six variants of the TX51 module, that
+Note: There are currently three variants of the TX51 module, that
       require slightly different U-Boot configurations. They are
-      distinguished through the first and last digit of the module
-      name suffix. Replace the '?' in the following description with
-      the corresponding numbers from your TX51 module.
-      E.g. TX51-8021 => 'make tx51-8xx1_config'
+      distinguished through the last digit of the module name
+      suffix. The following table lists the module names and the
+      corresponding U-Boot configuration name:
+
+      Module Name              U-Boot config
+      ---------------------------------------
+      TX51-8xx0                        tx51-8xx0_config
+      TX51-8xx1                        tx51-8xx1_2_config
+      TX51-8xx2                        tx51-8xx1_2_config
 
 Unpacking the source
 --------------------
@@ -25,7 +30,7 @@ Compiling U-Boot
 ----------------
 export ARCH=arm
 export CROSS_COMPILE=arm-cortexa8-linux-gnueabi-
-make tx51-?xx?_config            (see above Note!)
+make tx51-8xx?_config            (see above Note!)
 make
 
 
index 2aabb1426fdcba828b95810b23eeff199a4b3207..6506f142aa5f770825316c524f5dc959aa2eef54 100644 (file)
@@ -51,6 +51,9 @@
 /*
  * Memory configurations
  */
+#ifndef CONFIG_SYS_SDRAM_CLK
+#define CONFIG_SYS_SDRAM_CLK           166
+#endif
 #define PHYS_SDRAM_1                   0x90000000      /* Base address of bank 1 */
 #define PHYS_SDRAM_1_SIZE              SZ_128M
 #if CONFIG_NR_DRAM_BANKS > 1