arm: mx28: fix invalid definition and use of SET/CLR/TOG registers

diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 8b5ad018ea7d3000c093f14c2090ccc810ceb650..4d0cc04583324eab342cf6373a76bbc57ef6bd4f 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -406,11 +406,18 @@ void mxs_set_lcdclk(uint32_t freq)
        writeb(CLKCTRL_FRAC_CLKGATE,
                &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]);
 
-       writel(CLKCTRL_DIS_LCDIF_CLKGATE,
-               &clkctrl_regs->hw_clkctrl_lcdif_set);
-       clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif,
-                       CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE,
-                       k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET);
+       /* The i.MX28 Ref. Manual states:
+        * CLK_DIS_LCDIF Gate. If set to 1, CLK_DIS_LCDIF is gated off.
+        * 0: CLK_DIS_LCDIF is not gated.
+        * When this bit is modified, or when it is high,
+        * the DIV field should not change its value.
+        * The DIV field can change ONLY when this clock gate bit field is low.
+        * Note: This register does not have set/clear/toggle functionality!
+        */
+       /* clear CLKCTRL_DIS_LCDIF_CLKGATE */
+       writel(0, &clkctrl_regs->hw_clkctrl_lcdif);
+       writel(k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET,
+               &clkctrl_regs->hw_clkctrl_lcdif);
 
        while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY)
                ;

diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index c7664900e269aa8154ed74b0d10f41892843d483..10dbf4e5fa49d43c70d70960c89f5269990b8ac0 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -24,31 +24,31 @@ struct mxs_clkctrl_regs {
        mxs_reg_32(hw_clkctrl_pll2ctrl0);       /* 0x40 */
        mxs_reg_32(hw_clkctrl_cpu);             /* 0x50 */
        mxs_reg_32(hw_clkctrl_hbus);            /* 0x60 */
-       mxs_reg_32(hw_clkctrl_xbus);            /* 0x70 */
+       reg_32(hw_clkctrl_xbus);                /* 0x70 */
        mxs_reg_32(hw_clkctrl_xtal);            /* 0x80 */
-       mxs_reg_32(hw_clkctrl_ssp0);            /* 0x90 */
-       mxs_reg_32(hw_clkctrl_ssp1);            /* 0xa0 */
-       mxs_reg_32(hw_clkctrl_ssp2);            /* 0xb0 */
-       mxs_reg_32(hw_clkctrl_ssp3);            /* 0xc0 */
-       mxs_reg_32(hw_clkctrl_gpmi);            /* 0xd0 */
-       mxs_reg_32(hw_clkctrl_spdif);           /* 0xe0 */
-       mxs_reg_32(hw_clkctrl_emi);             /* 0xf0 */
-       mxs_reg_32(hw_clkctrl_saif0);           /* 0x100 */
-       mxs_reg_32(hw_clkctrl_saif1);           /* 0x110 */
-       mxs_reg_32(hw_clkctrl_lcdif);           /* 0x120 */
-       mxs_reg_32(hw_clkctrl_etm);             /* 0x130 */
-       mxs_reg_32(hw_clkctrl_enet);            /* 0x140 */
-       mxs_reg_32(hw_clkctrl_hsadc);           /* 0x150 */
-       mxs_reg_32(hw_clkctrl_flexcan);         /* 0x160 */
+       reg_32(hw_clkctrl_ssp0);                /* 0x90 */
+       reg_32(hw_clkctrl_ssp1);                /* 0xa0 */
+       reg_32(hw_clkctrl_ssp2);                /* 0xb0 */
+       reg_32(hw_clkctrl_ssp3);                /* 0xc0 */
+       reg_32(hw_clkctrl_gpmi);                /* 0xd0 */
+       reg_32(hw_clkctrl_spdif);               /* 0xe0 */
+       reg_32(hw_clkctrl_emi);                 /* 0xf0 */
+       reg_32(hw_clkctrl_saif0);               /* 0x100 */
+       reg_32(hw_clkctrl_saif1);               /* 0x110 */
+       reg_32(hw_clkctrl_lcdif);               /* 0x120 */
+       reg_32(hw_clkctrl_etm);                 /* 0x130 */
+       reg_32(hw_clkctrl_enet);                /* 0x140 */
+       reg_32(hw_clkctrl_hsadc);               /* 0x150 */
+       reg_32(hw_clkctrl_flexcan);             /* 0x160 */
 
        reg_32(reserved[4]);                    /* 0x170-0x1a0 */
 
        mxs_reg_8(hw_clkctrl_frac0);            /* 0x1b0 */
        mxs_reg_8(hw_clkctrl_frac1);            /* 0x1c0 */
        mxs_reg_32(hw_clkctrl_clkseq);          /* 0x1d0 */
-       mxs_reg_32(hw_clkctrl_reset);           /* 0x1e0 */
-       mxs_reg_32(hw_clkctrl_status);          /* 0x1f0 */
-       mxs_reg_32(hw_clkctrl_version);         /* 0x200 */
+       reg_32(hw_clkctrl_reset);               /* 0x1e0 */
+       reg_32(hw_clkctrl_status);              /* 0x1f0 */
+       reg_32(hw_clkctrl_version);             /* 0x200 */
 };
 #endif