avr32: rename mmu.h definitions
authorAndreas Bießmann <andreas.devel@googlemail.com>
Fri, 6 Feb 2015 22:06:42 +0000 (23:06 +0100)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 1 Sep 2015 11:53:51 +0000 (13:53 +0200)
Prefix mmu.h PAGE_xxx definitions with MMU_ in order to prevent a naming
conflict with other definitions.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
arch/avr32/cpu/at32ap700x/mmu.c
arch/avr32/include/asm/arch-at32ap700x/mmu.h
board/atmel/atngw100/atngw100.c
board/atmel/atngw100mkii/atngw100mkii.c
board/atmel/atstk1000/atstk1000.c
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
board/in-circuit/grasshopper/grasshopper.c
board/mimc/mimc200/mimc200.c
board/miromico/hammerhead/hammerhead.c

index 0e28b21..f5e62f2 100644 (file)
@@ -7,7 +7,7 @@ void mmu_init_r(unsigned long dest_addr)
        uintptr_t       vmr_table_addr;
 
        /* Round monitor address down to the nearest page boundary */
-       dest_addr &= PAGE_ADDR_MASK;
+       dest_addr &= MMU_PAGE_ADDR_MASK;
 
        /* Initialize TLB entry 0 to cover the monitor, and lock it */
        sysreg_write(TLBEHI, dest_addr | SYSREG_BIT(TLBEHI_V));
@@ -36,7 +36,7 @@ int mmu_handle_tlb_miss(void)
        unsigned int fault_pgno;
        int first, last;
 
-       fault_pgno = sysreg_read(TLBEAR) >> PAGE_SHIFT;
+       fault_pgno = sysreg_read(TLBEAR) >> MMU_PAGE_SHIFT;
        vmr_table = (const struct mmu_vm_range *)sysreg_read(PTBR);
 
        /* Do a binary search through the VM ranges */
@@ -60,8 +60,8 @@ int mmu_handle_tlb_miss(void)
                        /* Got it; let's slam it into the TLB */
                        uint32_t tlbelo;
 
-                       tlbelo = vmr->phys & ~PAGE_ADDR_MASK;
-                       tlbelo |= fault_pgno << PAGE_SHIFT;
+                       tlbelo = vmr->phys & ~MMU_PAGE_ADDR_MASK;
+                       tlbelo |= fault_pgno << MMU_PAGE_SHIFT;
                        sysreg_write(TLBELO, tlbelo);
                        __builtin_tlbw();
 
index fcd9a05..4736312 100644 (file)
@@ -13,9 +13,9 @@
 
 #include <asm/sysreg.h>
 
-#define PAGE_SHIFT     20
-#define PAGE_SIZE      (1UL << PAGE_SHIFT)
-#define PAGE_ADDR_MASK (~(PAGE_SIZE - 1))
+#define MMU_PAGE_SHIFT 20
+#define MMU_PAGE_SIZE  (1UL << MMU_PAGE_SHIFT)
+#define MMU_PAGE_ADDR_MASK     (~(MMU_PAGE_SIZE - 1))
 
 #define MMU_VMR_CACHE_NONE                                             \
        (SYSREG_BF(AP, 3) | SYSREG_BF(SZ, 3) | SYSREG_BIT(TLBELO_D))
index 03d767a..ed09c8c 100644 (file)
@@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
index 72d19e4..912ea10 100644 (file)
@@ -23,21 +23,21 @@ DECLARE_GLOBAL_DATA_PTR;
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
                /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
                /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
-               .virt_pgno      = EBI_SRAM_CS3_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT,
-               .phys           = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT)
+               .virt_pgno      = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
                /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
index 4b6b90f..f354694 100644 (file)
@@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
index a74547b..f9fde79 100644 (file)
@@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
index 340b713..2ac54db 100644 (file)
@@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                | MMU_VMR_CACHE_WRBACK,
        },
 };
index 2ad53ec..186ac7d 100644 (file)
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
-               .phys           = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
+               .virt_pgno      = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };
index d82fee7..e9a9e4b 100644 (file)
@@ -21,14 +21,14 @@ DECLARE_GLOBAL_DATA_PTR;
 
 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
        {
-               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
-               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_NONE,
        }, {
-               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
-               .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
-               .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+               .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
+               .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
+               .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
                                        | MMU_VMR_CACHE_WRBACK,
        },
 };