u32 mfd;
};
-const struct fixed_pll_mfd fixed_mfd[] = {
+static const struct fixed_pll_mfd fixed_mfd[] = {
{MXC_HCLK, 24 * 16},
};
#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX)
#define PLL_FREQ_MIN(ref_clk) \
- ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+ ((4 * (ref_clk) * PLL_MFI_MIN) / PLL_PD_MAX)
#define MAX_DDR_CLK 420000000
#define NFC_CLK_MAX 34000000
*/
static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
{
- uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
+ uint32_t ctrl, op;
+ int mfd, mfn, mfi, pdf, ret;
uint64_t refclk, temp;
- int32_t mfn_abs;
+ uint32_t mfn_abs;
ctrl = readl(&pll->ctrl);
if (mfn >= 0x04000000) {
mfn |= 0xfc000000;
mfn_abs = -mfn;
- } else
+ } else {
mfn_abs = mfn;
-
+ }
refclk = infreq * 2;
if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
refclk *= 2;
- do_div(refclk, pdf + 1);
temp = refclk * mfn_abs;
do_div(temp, mfd + 1);
ret = refclk * mfi;
- if ((int)mfn < 0)
+ if (mfn < 0)
ret -= temp;
else
ret += temp;
+ ret /= pdf + 1;
return ret;
}
*/
static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
{
- u64 pd, mfi = 1, mfn, mfd, t1;
- u32 n_target = target;
- u32 n_ref = ref, i;
+ int pd, mfi = 1, mfn, mfd;
+ u64 t1;
+ size_t i;
/*
* Make sure targeted freq is in the valid range.
* Otherwise the following calculation might be wrong!!!
*/
- if (n_target < PLL_FREQ_MIN(ref) ||
- n_target > PLL_FREQ_MAX(ref)) {
- printf("Targeted peripheral clock should be within [%d - %d]\n",
+ if (target < PLL_FREQ_MIN(ref) ||
+ target > PLL_FREQ_MAX(ref)) {
+ printf("Targeted pll clock should be within [%d - %d]\n",
PLL_FREQ_MIN(ref) / SZ_DEC_1M,
PLL_FREQ_MAX(ref) / SZ_DEC_1M);
return -EINVAL;
if (i == ARRAY_SIZE(fixed_mfd))
return -EINVAL;
- /* Use n_target and n_ref to avoid overflow */
for (pd = 1; pd <= PLL_PD_MAX; pd++) {
- t1 = n_target * pd;
- do_div(t1, (4 * n_ref));
+ t1 = (u64)target * pd;
+ do_div(t1, (4 * ref));
mfi = t1;
if (mfi > PLL_MFI_MAX)
return -EINVAL;
/*
* Now got pd and mfi already
*
- * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
+ * mfn = (((target * pd) / 4 - ref * mfi) * mfd) / ref;
*/
- t1 = n_target * pd;
+ t1 = (u64)target * pd;
do_div(t1, 4);
- t1 -= n_ref * mfi;
- t1 *= mfd;
- do_div(t1, n_ref);
+ t1 = (t1 - ref * mfi) * mfd;
+ do_div(t1, ref);
mfn = t1;
- debug("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
- ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
- i = 1;
- if (mfn != 0)
+ if (mfn != 0) {
i = gcd(mfd, mfn);
- pll->pd = (u32)pd;
- pll->mfi = (u32)mfi;
- do_div(mfn, i);
- pll->mfn = (u32)mfn;
- do_div(mfd, i);
- pll->mfd = (u32)mfd;
+ mfn /= i;
+ mfd /= i;
+ } else {
+ mfd = 1;
+ }
+ debug("ref=%d, target=%d, pd=%d, mfi=%d, mfn=%d, mfd=%d\n",
+ ref, target, pd, mfi, mfn, mfd);
+ pll->pd = pd;
+ pll->mfi = mfi;
+ pll->mfn = mfn;
+ pll->mfd = mfd;
return 0;
}
return 0;
}
+static int __adjust_core_voltage_stub(u32 freq)
+{
+ return 0;
+}
+int adjust_core_voltage(u32 freq)
+ __attribute__((weak, alias("__adjust_core_voltage_stub")));
+
/* Config CPU clock */
static int config_core_clk(u32 ref, u32 freq)
{
int ret = 0;
struct pll_param pll_param;
+ u32 cur_freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+
+ if (freq == cur_freq)
+ return 0;
memset(&pll_param, 0, sizeof(struct pll_param));
ref / 1000000, ref / 1000 % 1000);
return ret;
}
-
- return config_pll_clk(PLL1_CLOCK, &pll_param);
+ if (freq > cur_freq) {
+ ret = adjust_core_voltage(freq);
+ if (ret < 0) {
+ printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n",
+ cur_freq / 1000000, cur_freq / 1000 % 1000,
+ freq / 1000000, freq / 1000 % 1000);
+ return ret;
+ }
+ ret = config_pll_clk(PLL1_CLOCK, &pll_param);
+ if (ret) {
+ adjust_core_voltage(cur_freq);
+ }
+ } else {
+ ret = config_pll_clk(PLL1_CLOCK, &pll_param);
+ if (ret) {
+ return ret;
+ }
+ ret = adjust_core_voltage(freq);
+ if (ret < 0) {
+ printf("Failed to adjust core voltage for changing ARM clk from %u.%03uMHz to %u.%03uMHz\n",
+ cur_freq / 1000000, cur_freq / 1000 % 1000,
+ freq / 1000000, freq / 1000 % 1000);
+ calc_pll_params(ref, cur_freq, &pll_param);
+ config_pll_clk(PLL1_CLOCK, &pll_param);
+ }
+ }
+ return ret;
}
static int config_nfc_clk(u32 nfc_clk)
pr_clk_val(c, __clk); \
}
-int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_mx5_showclocks(void)
{
unsigned long freq;
return 0;
}
+static struct clk_lookup {
+ const char *name;
+ unsigned int index;
+} mx5_clk_lookup[] = {
+ { "arm", MXC_ARM_CLK, },
+};
+
+int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int i;
+ unsigned long freq;
+ unsigned long ref = ~0UL;
+
+ if (argc < 2) {
+ do_mx5_showclocks();
+ return CMD_RET_SUCCESS;
+ } else if (argc == 2 || argc > 4) {
+ return CMD_RET_USAGE;
+ }
+
+ freq = simple_strtoul(argv[2], NULL, 0);
+ if (freq == 0) {
+ printf("Invalid clock frequency %lu\n", freq);
+ return CMD_RET_FAILURE;
+ }
+ if (argc > 3) {
+ ref = simple_strtoul(argv[3], NULL, 0);
+ }
+ for (i = 0; i < ARRAY_SIZE(mx5_clk_lookup); i++) {
+ if (strcasecmp(argv[1], mx5_clk_lookup[i].name) == 0) {
+ switch (mx5_clk_lookup[i].index) {
+ case MXC_ARM_CLK:
+ if (argc > 3)
+ return CMD_RET_USAGE;
+ ref = CONFIG_SYS_MX5_HCLK;
+ break;
+
+ case MXC_NFC_CLK:
+ if (argc > 3 && ref > 3) {
+ printf("Invalid clock selector value: %lu\n", ref);
+ return CMD_RET_FAILURE;
+ }
+ break;
+ }
+ printf("Setting %s clock to %lu MHz\n",
+ mx5_clk_lookup[i].name, freq);
+ if (mxc_set_clock(ref, freq, mx5_clk_lookup[i].index))
+ break;
+ freq = mxc_get_clock(mx5_clk_lookup[i].index);
+ printf("%s clock set to %lu.%03lu MHz\n",
+ mx5_clk_lookup[i].name,
+ freq / 1000000, freq / 1000 % 1000);
+ return CMD_RET_SUCCESS;
+ }
+ }
+ if (i == ARRAY_SIZE(mx5_clk_lookup)) {
+ printf("clock %s not found; supported clocks are:\n", argv[1]);
+ for (i = 0; i < ARRAY_SIZE(mx5_clk_lookup); i++) {
+ printf("\t%s\n", mx5_clk_lookup[i].name);
+ }
+ } else {
+ printf("Failed to set clock %s to %s MHz\n",
+ argv[1], argv[2]);
+ }
+ return CMD_RET_FAILURE;
+}
+
/***************************************************/
U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
- "display clocks",
- ""
+ clocks, 4, 0, do_clocks,
+ "display/set clocks",
+ " - display clock settings\n"
+ "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"
);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
+int adjust_core_voltage(u32 freq);
void set_usb_phy_clk(void);
void enable_usb_phy1_clk(unsigned char enable);
void enable_usb_phy2_clk(unsigned char enable);
*/
off = fdt_path_offset(blob, backlight_node);
if (off < 0) {
- printf("/backlight node not found in DT\n");
+ printf("%s node not found in DT\n", backlight_node);
return off;
}
}
struct mtd_device *dev;
struct part_info *part_info;
u8 part_num;
- size_t actual;
debug("Initializing mtd_parts\n");
ret = mtdparts_init();
}
debug("Found partition '%s': offset=%08x size=%08x\n",
part, part_info->offset, part_info->size);
- if (part_info->size < len) {
- printf("Warning: partition '%s' smaller than requested size: %u; truncating data to %u byte\n",
- part, len, part_info->size);
+
+ if (part_info->size < len)
len = part_info->size;
- }
+
debug("Reading NAND partition '%s' to %p\n", part, addr);
ret = nand_read_skip_bad(&nand_info[0], part_info->offset, &len,
- &actual, len, addr);
+ NULL, part_info->size, addr);
if (ret) {
printf("Failed to load partition '%s' to %p\n", part, addr);
return ret;
}
- if (actual < len)
- printf("Read only %u of %u bytes due to bad blocks\n",
- actual, len);
debug("Read %u byte from partition '%s' @ offset %08x\n",
len, part, part_info->offset);
return 0;
}
-#ifdef CONFIG_SPLASH_SCREEN_
+#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MTDPARTS)
static int erase_flash(loff_t offs, size_t len)
{
nand_erase_options_t nand_erase_options;
struct part_info *part_info;
u8 part_num;
u_char *addr = (u_char *)gd->fb_base;
- size_t actual;
if (argc > 2)
return CMD_RET_USAGE;
debug("Initializing mtd_parts\n");
ret = mtdparts_init();
if (ret)
- return ret;
+ return CMD_RET_FAILURE;
debug("Trying to find NAND partition '%s'\n", part);
ret = find_dev_and_part(part, &dev, &part_num,
if (ret) {
printf("Failed to find flash partition '%s': %d\n",
part, ret);
-
- return ret;
+ return CMD_RET_FAILURE;
}
debug("Found partition '%s': offset=%08x size=%08x\n",
part, part_info->offset, part_info->size);
}
ret = nand_write_skip_bad(&nand_info[0], part_info->offset,
- &fbsize, &actual, part_info->size,
+ &fbsize, NULL, part_info->size,
addr, WITH_DROP_FFS);
if (ret) {
printf("Failed to write partition '%s'\n", part);
- return ret;
+ return CMD_RET_FAILURE;
}
- if (actual < fbsize)
- printf("Wrote only %u of %u bytes due to bad blocks\n",
- actual, fbsize);
debug("Wrote %u byte from %p to partition '%s' @ offset %08x\n",
fbsize, addr, part, part_info->offset);
+/*
+ * Copyright (C) 2011-2014 Lothar Waßmann <LW@KARO-electronics.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
#include <common.h>
#include <malloc.h>
#include <nand.h>
#include <errno.h>
#include <linux/err.h>
+#include <jffs2/load_kernel.h>
#include <asm/io.h>
#include <asm/sizes.h>
#include <asm/imx-common/regs-gpmi.h>
#include <asm/imx-common/regs-bch.h>
-#define FCB_START_BLOCK 0
-#define NUM_FCB_BLOCKS 1
-#define MAX_FCB_BLOCKS 32768
-
struct mx28_nand_timing {
u8 data_setup;
u8 data_hold;
u32 bb_mark_phys_offset;
};
-struct mx28_dbbt_header {
- u32 checksum;
- u32 fingerprint;
- u32 version;
- u32 number_bb;
- u32 number_pages;
- u8 spare[492];
-};
-
-struct mx28_dbbt {
- u32 nand_number;
- u32 number_bb;
- u32 bb_num[2040 / 4];
-};
-
#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
static nand_info_t *mtd = &nand_info[0];
return bb_mark_offset;
}
+/*
+ * return number of blocks to skip for a contiguous partition
+ * of given # blocks
+ */
+static int find_contig_space(int block, int num_blocks, int max_blocks)
+{
+ int skip = 0;
+ int found = 0;
+ int last = block + max_blocks;
+
+ debug("Searching %u contiguous blocks from %d..%d\n",
+ num_blocks, block, block + max_blocks - 1);
+ for (; block < last; block++) {
+ if (nand_block_isbad(mtd, block * mtd->erasesize)) {
+ skip += found + 1;
+ found = 0;
+ debug("Skipping %u blocks to %u\n",
+ skip, block + 1);
+ } else {
+ found++;
+ if (found >= num_blocks) {
+ debug("Found %u good blocks from %d..%d\n",
+ found, block - found + 1, block);
+ return skip;
+ }
+ }
+ }
+ return -ENOSPC;
+}
+
+#define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n)
+
static struct mx28_fcb *create_fcb(void *buf, int fw1_start_block,
- int fw2_start_block, size_t fw_size)
+ int fw2_start_block, int fw_num_blocks)
{
struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS;
struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS;
fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE);
+ pr_fcb_val(fcb, ecc_block0_type);
+ pr_fcb_val(fcb, ecc_blockn_type);
+ pr_fcb_val(fcb, ecc_block0_size);
+ pr_fcb_val(fcb, ecc_blockn_size);
+
fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
fcb->bch_mode = readl(&bch_base->hw_bch_mode);
fcb->boot_patch = 0;
fcb->patch_sectors = 0;
*/
- fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize;
- fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize);
+ fcb->fw1_start_page = fw1_start_block * fcb->sectors_per_block;
+ fcb->fw1_sectors = fw_num_blocks * fcb->sectors_per_block;
+ pr_fcb_val(fcb, fw1_start_page);
+ pr_fcb_val(fcb, fw1_sectors);
if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
- fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize;
+ fcb->fw2_start_page = fw2_start_block * fcb->sectors_per_block;
fcb->fw2_sectors = fcb->fw1_sectors;
+ pr_fcb_val(fcb, fw2_start_page);
+ pr_fcb_val(fcb, fw2_sectors);
}
fcb->dbbt_search_area = 1;
fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
fcb->bb_mark_phys_offset = mtd->writesize;
+ pr_fcb_val(fcb, bb_mark_byte);
+ pr_fcb_val(fcb, bb_mark_startbit);
+ pr_fcb_val(fcb, bb_mark_phys_offset);
+
fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
return fcb;
}
ret = chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
if (ret) {
printf("Failed to read FCB from page %u: %d\n", page, ret);
- return ret;
+ goto out;
}
- chip->select_chip(mtd, -1);
if (memcmp(buf, ref, mtd->writesize) == 0) {
debug("Found FCB in page %u (%08x)\n",
page, page * mtd->writesize);
ret = 1;
}
+out:
+ chip->select_chip(mtd, -1);
free(buf);
return ret;
}
return ret;
}
- printf("Writing FCB to block %d @ %08x\n", block,
- block * mtd->erasesize);
+ printf("Writing FCB to block %d @ %08llx\n", block,
+ (u64)block * mtd->erasesize);
chip->select_chip(mtd, 0);
ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1);
if (ret) {
return ret;
}
-static size_t count_good_blocks(int start, int end)
-{
- size_t max_len = (end - start + 1);
- int block;
-
- for (block = start; block <= end; block++) {
- if (nand_block_isbad(mtd, block * mtd->erasesize))
- max_len--;
- }
- return max_len;
-}
-
#define chk_overlap(a,b) \
((a##_start_block <= b##_end_block && \
a##_end_block >= b##_start_block) || \
} \
} while (0)
+static int tx28_prog_uboot(void *addr, int start_block, int skip,
+ size_t size, size_t max_len)
+{
+ int ret;
+ nand_erase_options_t erase_opts = { 0, };
+ size_t actual;
+
+ erase_opts.offset = start_block * mtd->erasesize;
+ erase_opts.length = max_len;
+ erase_opts.quiet = 1;
+
+ printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
+ erase_opts.offset + erase_opts.length - 1);
+ ret = nand_erase_opts(mtd, &erase_opts);
+ if (ret) {
+ printf("Failed to erase flash: %d\n", ret);
+ return ret;
+ }
+
+ printf("Programming flash @ %08llx..%08llx from %p\n",
+ (u64)start_block * mtd->erasesize,
+ (u64)start_block * mtd->erasesize + size - 1, addr);
+ actual = size;
+ ret = nand_write_skip_bad(mtd, start_block * mtd->erasesize,
+ &actual, NULL, erase_opts.length, addr,
+ WITH_DROP_FFS);
+ if (ret) {
+ printf("Failed to program flash: %d\n", ret);
+ return ret;
+ }
+ if (actual < size) {
+ printf("Could only write %u of %u bytes\n", actual, size);
+ return -EIO;
+ }
+ return 0;
+}
+
#ifdef CONFIG_ENV_IS_IN_NAND
#ifndef CONFIG_ENV_OFFSET_REDUND
#define TOTAL_ENV_SIZE CONFIG_ENV_RANGE
int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
int ret;
+ const unsigned long fcb_start_block = 0, fcb_end_block = 0;
int erase_size = mtd->erasesize;
int page_size = mtd->writesize;
void *buf;
size_t size = 0;
void *addr = NULL;
struct mx28_fcb *fcb;
- unsigned long fcb_start_block = FCB_START_BLOCK;
- unsigned long num_fcb_blocks = NUM_FCB_BLOCKS;
- unsigned long fcb_end_block;
unsigned long mtd_num_blocks = mtd->size / mtd->erasesize;
#ifdef CONFIG_ENV_IS_IN_NAND
unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize;
DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1;
#endif
int optind;
- int fw1_set = 0;
int fw2_set = 0;
unsigned long fw1_start_block = 0, fw1_end_block;
unsigned long fw2_start_block = 0, fw2_end_block;
unsigned long fw_num_blocks;
- unsigned long extra_blocks = 2;
- nand_erase_options_t erase_opts = { 0, };
+ int fw1_skip, fw2_skip;
+ unsigned long extra_blocks = 0;
size_t max_len1, max_len2;
- size_t actual;
+ struct mtd_device *dev;
+ struct part_info *part_info;
+ struct part_info *redund_part_info;
+ const char *uboot_part = "u-boot";
+ const char *redund_part = NULL;
+ u8 part_num;
+ u8 redund_part_num;
+
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
for (optind = 1; optind < argc; optind++) {
- if (strcmp(argv[optind], "-b") == 0) {
- if (optind >= argc - 1) {
- printf("Option %s requires an argument\n", argv[optind]);
- return -EINVAL;
- }
- optind++;
- fcb_start_block = simple_strtoul(argv[optind], NULL, 0);
- if (fcb_start_block >= mtd_num_blocks) {
- printf("Block number %lu is out of range: 0..%lu\n",
- fcb_start_block, mtd_num_blocks - 1);
- return -EINVAL;
- }
- } else if (strcmp(argv[optind], "-n") == 0) {
- if (optind >= argc - 1) {
- printf("Option %s requires an argument\n", argv[optind]);
- return -EINVAL;
- }
- optind++;
- num_fcb_blocks = simple_strtoul(argv[optind], NULL, 0);
- if (num_fcb_blocks > MAX_FCB_BLOCKS) {
- printf("Extraneous number of FCB blocks; max. allowed: %u\n",
- MAX_FCB_BLOCKS);
- return -EINVAL;
- }
- } else if (strcmp(argv[optind], "-f") == 0) {
+ char *endp;
+
+ if (strcmp(argv[optind], "-f") == 0) {
if (optind >= argc - 1) {
printf("Option %s requires an argument\n",
argv[optind]);
return -EINVAL;
}
optind++;
- fw1_start_block = simple_strtoul(argv[optind], NULL, 0);
+ fw1_start_block = simple_strtoul(argv[optind], &endp, 0);
+ if (*endp != '\0') {
+ uboot_part = argv[optind];
+ continue;
+ }
+ uboot_part = NULL;
if (fw1_start_block >= mtd_num_blocks) {
printf("Block number %lu is out of range: 0..%lu\n",
fw1_start_block, mtd_num_blocks - 1);
return -EINVAL;
}
- fw1_set = 1;
} else if (strcmp(argv[optind], "-r") == 0) {
+ fw2_set = 1;
if (optind < argc - 1 && argv[optind + 1][0] != '-') {
optind++;
fw2_start_block = simple_strtoul(argv[optind],
- NULL, 0);
+ &endp, 0);
+ if (*endp != '\0') {
+ redund_part = argv[optind];
+ continue;
+ }
if (fw2_start_block >= mtd_num_blocks) {
printf("Block number %lu is out of range: 0..%lu\n",
fw2_start_block,
return -EINVAL;
}
}
- fw2_set = 1;
} else if (strcmp(argv[optind], "-e") == 0) {
if (optind >= argc - 1) {
printf("Option %s requires an argument\n",
size = simple_strtoul(file_size, NULL, 16);
printf("Using default file size %08x\n", size);
}
- fcb_end_block = fcb_start_block + num_fcb_blocks - 1;
- if (size > 0)
+ if (size > 0) {
fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize);
- else
- fw_num_blocks = CONFIG_U_BOOT_IMG_SIZE / mtd->erasesize - extra_blocks;
+ } else {
+ fw_num_blocks = part_info->size / mtd->erasesize -
+ extra_blocks;
+ size = fw_num_blocks * mtd->erasesize;
+ }
+
+ if (uboot_part) {
+ ret = find_dev_and_part(uboot_part, &dev, &part_num,
+ &part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ uboot_part, ret);
+ return ret;
+ }
+ fw1_start_block = part_info->offset / mtd->erasesize;
+ max_len1 = part_info->size;
+ } else {
+ max_len1 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
+ }
- if (!fw1_set) {
- fw1_start_block = fcb_end_block + 1;
- fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ if (redund_part) {
+ ret = find_dev_and_part(redund_part, &dev, &redund_part_num,
+ &redund_part_info);
+ if (ret) {
+ printf("Failed to find '%s' partition: %d\n",
+ redund_part, ret);
+ return ret;
+ }
+ fw2_start_block = redund_part_info->offset / mtd->erasesize;
+ max_len2 = redund_part_info->size;
+ } else if (fw2_set) {
+ max_len2 = (fw_num_blocks + extra_blocks) * mtd->erasesize;
} else {
- fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1;
+ max_len2 = 0;
}
- if (fw2_set && fw2_start_block == 0) {
+ fw1_skip = find_contig_space(fw1_start_block, fw_num_blocks,
+ max_len1 / mtd->erasesize);
+ if (fw1_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for fw image\n",
+ fw_num_blocks);
+ if (uboot_part) {
+#ifdef CONFIG_ENV_IS_IN_NAND
+ if (part_info->offset <= CONFIG_ENV_OFFSET + TOTAL_ENV_SIZE) {
+ printf("Use a different partition\n");
+ } else {
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+ }
+#else
+ printf("Increase the size of the '%s' partition\n",
+ uboot_part);
+#endif
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
+ fw1_end_block = fw1_start_block + fw1_skip + fw_num_blocks - 1;
+
+ if (fw2_set && fw2_start_block == 0)
fw2_start_block = fw1_end_block + 1;
- fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ if (fw2_start_block > 0) {
+ fw2_skip = find_contig_space(fw2_start_block, fw_num_blocks,
+ max_len2 / mtd->erasesize);
+ if (fw2_skip < 0) {
+ printf("Could not find %lu contiguous good blocks for redundant fw image\n",
+ fw_num_blocks);
+ if (redund_part) {
+ printf("Increase the size of the '%s' partition or use a different partition\n",
+ redund_part);
+ } else {
+ printf("Increase the number of spare blocks to use with the '-e' option\n");
+ }
+ return -ENOSPC;
+ }
} else {
- fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1;
+ fw2_skip = 0;
}
+ fw2_end_block = fw2_start_block + fw2_skip + fw_num_blocks - 1;
#ifdef CONFIG_ENV_IS_IN_NAND
fail_if_overlap(fcb, env, "FCB", "Environment");
return -ENOMEM;
}
- /* search for bad blocks in FW1 block range */
- max_len1 = count_good_blocks(fw1_start_block, fw1_end_block);
- printf("%u good blocks in %lu..%lu\n",
- max_len1, fw1_start_block, fw1_end_block);
- if (fw_num_blocks > max_len1) {
- printf("Too many bad blocks in FW1 block range: %lu..%lu; max blocks: %u\n",
- fw1_end_block + 1 - fw_num_blocks - extra_blocks,
- fw1_end_block, max_len1);
- return -EINVAL;
- }
-
- /* search for bad blocks in FW2 block range */
- max_len2 = count_good_blocks(fw2_start_block, fw2_end_block);
- if (fw2_start_block > 0 && fw_num_blocks > max_len2) {
- printf("Too many bad blocks in FW2 block range: %lu..%lu\n",
- fw2_end_block + 1 - fw_num_blocks - extra_blocks,
- fw2_end_block);
- return -EINVAL;
- }
-
- fcb = create_fcb(buf, fw1_start_block, fw2_start_block,
- ALIGN(fw_num_blocks * mtd->erasesize, mtd->writesize));
+ fcb = create_fcb(buf, fw1_start_block + fw1_skip,
+ fw2_start_block + fw2_skip, fw_num_blocks);
if (IS_ERR(fcb)) {
printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
+ free(buf);
return PTR_ERR(fcb);
}
encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
ret = write_fcb(buf, fcb_start_block);
+ free(buf);
if (ret) {
printf("Failed to write FCB to block %lu\n", fcb_start_block);
return ret;
}
- printf("Programming U-Boot image from %p to block %lu\n",
- addr, fw1_start_block);
if (size & (page_size - 1)) {
memset(addr + size, 0xff, size & (page_size - 1));
size = ALIGN(size, page_size);
}
- erase_opts.offset = fcb->fw1_start_page * page_size;
- erase_opts.length = (fw1_end_block - fw1_start_block + 1) *
- mtd->erasesize;
- erase_opts.quiet = 1;
-
- printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
- erase_opts.offset + erase_opts.length - 1);
-
- ret = nand_erase_opts(mtd, &erase_opts);
- if (ret) {
- printf("Failed to erase flash: %d\n", ret);
- return ret;
- }
- if (size == 0)
- max_len1 *= mtd->erasesize;
- else
- max_len1 = size;
+ printf("Programming U-Boot image from %p to block %lu @ %08llx\n",
+ addr, fw1_start_block + fw1_skip,
+ (u64)(fw1_start_block + fw1_skip) * mtd->erasesize);
+ ret = tx28_prog_uboot(addr, fw1_start_block, fw1_skip, size,
+ max_len1);
- printf("Programming flash @ %08x..%08x from %p\n",
- fcb->fw1_start_page * page_size,
- fcb->fw1_start_page * page_size + max_len1 - 1, addr);
- ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size,
- &max_len1, &actual, erase_opts.length, addr,
- WITH_DROP_FFS);
- if (ret || actual < size) {
- printf("Failed to program flash: %d\n", ret);
- return ret ?: -EIO;
- }
if (fw2_start_block == 0) {
return ret;
}
- printf("Programming redundant U-Boot image to block %lu\n",
- fw2_start_block);
- erase_opts.offset = fcb->fw2_start_page * page_size;
- erase_opts.length = (fw2_end_block - fw2_start_block + 1) *
- mtd->erasesize;
- printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset,
- erase_opts.offset + erase_opts.length - 1);
-
- ret = nand_erase_opts(mtd, &erase_opts);
- if (ret) {
- printf("Failed to erase flash: %d\n", ret);
- return ret;
- }
- if (size == 0)
- max_len2 *= mtd->erasesize;
- else
- max_len2 = size;
- printf("Programming flash @ %08x..%08x from %p\n",
- fcb->fw2_start_page * page_size,
- fcb->fw2_start_page * page_size + max_len2 - 1, addr);
- ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size,
- &max_len2, &actual, erase_opts.length, addr,
- WITH_DROP_FFS);
- if (ret || actual < size) {
- printf("Failed to program flash: %d\n", ret);
- return ret ?: -EIO;
- }
+ printf("Programming redundant U-Boot image to block %lu @ %08llx\n",
+ fw2_start_block + fw2_skip,
+ (u64)(fw2_start_block + fw2_skip) * mtd->erasesize);
+ ret = tx28_prog_uboot(addr, fw2_start_block, fw2_skip, fw_num_blocks,
+ max_len2);
return ret;
}
U_BOOT_CMD(romupdate, 11, 0, do_update,
"Creates an FCB data structure and writes an U-Boot image to flash",
- "[-b #] [-n #] [-f #] [-r [#]] [<address>] [<length>]\n"
- "\t-b #\tfirst FCB block number (default 0)\n"
- "\t-n #\ttotal number of FCB blocks (default 1)\n"
- "\t-f #\twrite bootloader image at block #\n"
+ "[-f {<part>|block#}] [-r [{<part>|block#}]] [-e #] [<address>] [<length>]\n"
+ "\t-f <part>\twrite bootloader image to partition <part>\n"
+ "\t-f #\twrite bootloader image at block # (decimal)\n"
"\t-r\twrite redundant bootloader image at next free block after first image\n"
- "\t-r #\twrite redundant bootloader image at block #\n"
- "\t-e #\tspecify number of redundant blocks per boot loader image (default 2)\n"
+ "\t-r <part>\twrite redundant bootloader image to partition <part>\n"
+ "\t-r #\twrite redundant bootloader image at block # (decimal)\n"
+ "\t-e #\tspecify number of redundant blocks per boot loader image\n"
+ "\t\tonly valid if -f or -r specify a flash address rather than a partition name\n"
"\t<address>\tRAM address of bootloader image (default: ${fileaddr}\n"
"\t<length>\tlength of bootloader image in RAM (default: ${filesize}"
);
.endif
.endm
-#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val
+#define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
#define MXC_DCD_CMD_SZ_BYTE 1
#define MXC_DCD_CMD_SZ_SHORT 2
#define MXC_DCD_CMD_FLAG_WRITE 0x0
#define MXC_DCD_CMD_FLAG_CLR 0x1
#define MXC_DCD_CMD_FLAG_SET 0x3
-#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
-#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
-#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
-#define MXC_DCD_CMD_WRT(type, flags, next) \
- .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+#define MXC_DCD_START \
+ .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
+dcd_start:
+
+ .macro MXC_DCD_END
+1:
+ .ifgt . - dcd_start - 1768
+ .error "DCD too large!"
+ .endif
+dcd_end:
+ .endm
-#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
- .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+#define MXC_DCD_CMD_WRT(type, flags) \
+1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
+1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
CPU_2_BE_32(addr), CPU_2_BE_32(mask)
-#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
- .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
+1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
-#define MXC_DCD_CMD_NOP() \
- .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+#define MXC_DCD_CMD_NOP() \
+1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
#define DCD_VERSION 0x40
dcd_hdr:
- .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
-dcd_start:
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+ MXC_DCD_START
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0)
/* MR0..3 - CS0 */
+ MXC_DCD_ITEM(0x63fd901c, 0x00008000) /* CON_REQ */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x63fd901c, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
-zq_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
-
- /* Write Leveling */
- MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
- MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val | (1 << 7)) | (1 << 9)) /* MRS: start write leveling */
- MXC_DCD_ITEM(0x63fd901c, 0x00000000)
- MXC_DCD_ITEM(0x63fd9048, 0x00000001)
-wl_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
- MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
- MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd9040, 0x00010000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
/* DQS calibration */
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
-dqs_calib:
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd907c, 0x90000000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
/* WR DL calibration */
- MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+ MXC_DCD_ITEM(0x63fd901c, 0x00008000)
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
-wr_dl_calib: /* 6c4 */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a4, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
/* RD DL calibration */
MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
-rd_dl_calib: /* 70c */
- MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
+
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a0, 0x00000010)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */
MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1)
+ /* DDR calibration done */
MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+ MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd901c, 0x00004000)
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
/* setup NFC pads */
/* MUX_SEL */
MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
-dcd_end:
- .ifgt dcd_end - dcd_start - 1768
- .error "DCD too large!"
- .endif
+ MXC_DCD_END
enum LTC3589_REGS {
LTC3589_SCR1 = 0x07,
+ LTC3589_SCR2 = 0x12,
+ LTC3589_VCCR = 0x20,
LTC3589_CLIRQ = 0x21,
LTC3589_B1DTV1 = 0x23,
LTC3589_B1DTV2 = 0x24,
LTC3589_L2DTV2 = 0x33,
};
-#define LTC3589_PGOOD_MASK (1 << 5)
+#define LTC3589_BnDTV1_PGOOD_MASK (1 << 5)
+#define LTC3589_BnDTV1_SLEW(n) (((n) & 3) << 6)
-#define LTC3589_CLK_RATE_LOW (1 << 5)
+#define LTC3589_CLK_RATE_LOW (1 << 5)
+
+#define LTC3589_SCR2_PGOOD_SHUTDWN (1 << 7)
#define VDD_LDO2_VAL mV_to_regval(vout_to_vref(1325 * 10, 2))
-#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1240 * 10, 3))
+#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1100 * 10, 3))
#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1325 * 10, 4))
#define VDD_BUCK3_VAL mV_to_regval(vout_to_vref(2500 * 10, 5))
u8 val;
} ltc3589_regs[] = {
{ LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
+ { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
- { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
- { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_B1DTV2, VDD_CORE_VAL, },
- { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_B2DTV2, VDD_SOC_VAL, },
- { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_PGOOD_MASK, },
+ { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
{ LTC3589_B3DTV2, VDD_BUCK3_VAL, },
+ /* Select ref 0 for all regulators and enable slew */
+ { LTC3589_VCCR, 0x55, },
+
{ LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
};
return 0;
}
+static struct {
+ u32 max_freq;
+ u32 mV;
+} tx53_core_voltages[] = {
+ { 800000000, 1100, },
+ { 1000000000, 1240, },
+ { 1200000000, 1350, },
+};
+
+int adjust_core_voltage(u32 freq)
+{
+ int ret;
+ int i;
+
+ printf("%s@%d\n", __func__, __LINE__);
+
+ for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
+ if (freq <= tx53_core_voltages[i].max_freq) {
+ int retries = 0;
+ const int max_tries = 10;
+ const int delay_us = 1;
+ u32 mV = tx53_core_voltages[i].mV;
+ u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
+ u8 v;
+
+ printf("regval[%umV]=%02x\n", mV, val);
+
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_B1DTV1, ret);
+ return ret;
+ }
+ printf("Changing reg %02x from %02x to %02x\n",
+ LTC3589_B1DTV1, v, (v & ~0x1f) |
+ mV_to_regval(vout_to_vref(mV * 10, 3)));
+ v &= ~0x1f;
+ v |= mV_to_regval(vout_to_vref(mV * 10, 3));
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, LTC3589_B1DTV1, ret);
+ return ret;
+ }
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ v |= 0x1;
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
+ &v, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ for (retries = 0; retries < max_tries; retries++) {
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
+ LTC3589_VCCR, 1, &v, 1);
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, LTC3589_VCCR, ret);
+ return ret;
+ }
+ if (!(v & 1))
+ break;
+ udelay(delay_us);
+ }
+ if (v & 1) {
+ printf("change of VDDCORE did not complete after %uµs\n",
+ retries * delay_us);
+ return -ETIMEDOUT;
+ }
+
+ printf("VDDCORE set to %umV after %u loops\n",
+ DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
+ 10), retries);
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
int board_early_init_f(void)
{
struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
projects / karo-tx-uboot.git / commitdiff