Merge branch 'master' of git://www.denx.de/git/u-boot-imx
authorTom Rini <trini@ti.com>
Mon, 20 Jan 2014 12:33:42 +0000 (07:33 -0500)
committerTom Rini <trini@ti.com>
Mon, 20 Jan 2014 12:33:42 +0000 (07:33 -0500)
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h

index 009a644..0208cba 100644 (file)
@@ -19,8 +19,6 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 
-#define VDDPU_MASK     (0x1f << 9)
-
 enum ldo_reg {
        LDO_ARM,
        LDO_SOC,
@@ -179,50 +177,11 @@ static void imx_set_wdog_powerdown(bool enable)
        writew(enable, &wdog2->wmcr);
 }
 
-static void imx_set_vddpu_power_down(void)
-{
-       struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-       struct gpc_regs *gpc = (struct gpc_regs *)GPC_BASE_ADDR;
-
-       u32 reg;
-
-       /*
-        * Disable the brown out detection since we are going to be
-        * disabling the LDO.
-        */
-       reg = readl(&anatop->ana_misc2);
-       reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
-       writel(reg, &anatop->ana_misc2);
-
-       /* need to power down xPU in GPC before turning off PU LDO */
-       reg = readl(&gpc->gpu_ctrl);
-       writel(reg | 0x1, &gpc->gpu_ctrl);
-
-       reg = readl(&gpc->ctrl);
-       writel(reg | 0x1, &gpc->ctrl);
-       while (readl(&gpc->ctrl) & 0x1)
-               ;
-
-       /* Mask the ANATOP brown out interrupt in the GPC. */
-       reg = readl(&gpc->imr4);
-       reg |= 0x80000000;
-       writel(reg, &gpc->imr4);
-
-       /* disable VDDPU */
-       writel(VDDPU_MASK, &anatop->reg_core_clr);
-
-       /* Clear the BO interrupt in the ANATOP. */
-       reg = readl(&anatop->ana_misc1);
-       reg |= 0x80000000;
-       writel(reg, &anatop->ana_misc1);
-}
-
 int arch_cpu_init(void)
 {
        init_aips();
 
        imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
-       imx_set_vddpu_power_down();
 
 #ifdef CONFIG_APBH_DMA
        /* Start APBH DMA */
index aede126..7202073 100644 (file)
@@ -890,5 +890,4 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
        (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
 
-#define ANADIG_ANA_MISC2_REG1_BO_EN    (1 << 13)
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
index 7f89865..f2ad6e9 100644 (file)
@@ -663,28 +663,5 @@ struct wdog_regs {
        u16     wmcr;   /* Miscellaneous Control */
 };
 
-struct gpc_regs {
-       u32     ctrl;           /* 0x000 */
-       u32     pgr;            /* 0x004 */
-       u32     imr1;           /* 0x008 */
-       u32     imr2;           /* 0x00c */
-       u32     imr3;           /* 0x010 */
-       u32     imr4;           /* 0x014 */
-       u32     isr1;           /* 0x018 */
-       u32     isr2;           /* 0x01c */
-       u32     isr3;           /* 0x020 */
-       u32     isr4;           /* 0x024 */
-       u32     reserved1[0x86];
-       u32     gpu_ctrl;       /* 0x260 */
-       u32     gpu_pupscr;     /* 0x264 */
-       u32     gpu_pdnscr;     /* 0x268 */
-       u32     gpu_sr;         /* 0x26c */
-       u32     reserved2[0xc];
-       u32     cpu_ctrl;       /* 0x2a0 */
-       u32     cpu_pupscr;     /* 0x2a4 */
-       u32     cpu_pdnscr;     /* 0x2a8 */
-       u32     cpu_sr;         /* 0x2ac */
-};
-
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */