Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 11 Oct 2013 12:47:25 +0000 (14:47 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 11 Oct 2013 12:47:25 +0000 (14:47 +0200)
109 files changed:
MAKEALL
README
arch/arm/cpu/arm925t/config.mk [deleted file]
arch/arm/cpu/arm925t/cpu.c [deleted file]
arch/arm/cpu/arm925t/omap925.c [deleted file]
arch/arm/cpu/arm925t/start.S [deleted file]
arch/arm/cpu/arm925t/timer.c [deleted file]
arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
arch/arm/cpu/arm926ejs/mxs/start.S
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/cpu/armv7/am33xx/sys_info.c
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/cpu/armv7/nonsec_virt.S [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/cpu/armv7/socfpga/Makefile
arch/arm/cpu/armv7/socfpga/spl.c
arch/arm/cpu/armv7/socfpga/system_manager.c [new file with mode: 0644]
arch/arm/cpu/armv7/virt-v7.c [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/ddr_defs.h
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-mx27/imx-regs.h
arch/arm/include/asm/arch-mx6/clock.h
arch/arm/include/asm/arch-mx6/crm_regs.h
arch/arm/include/asm/arch-mx6/iomux.h
arch/arm/include/asm/arch-mx6/mx6dl_pins.h
arch/arm/include/asm/arch-mx6/mx6q_pins.h
arch/arm/include/asm/arch-mx6/mx6sl_pins.h
arch/arm/include/asm/arch-mxs/sys_proto.h
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h
arch/arm/include/asm/arch-socfpga/system_manager.h [new file with mode: 0644]
arch/arm/include/asm/armv7.h
arch/arm/include/asm/gic.h [new file with mode: 0644]
arch/arm/include/asm/omap_common.h
arch/arm/lib/bootm.c
board/altera/socfpga/Makefile
board/altera/socfpga/pinmux_config.c [new file with mode: 0644]
board/altera/socfpga/pinmux_config.h [new file with mode: 0644]
board/armadeus/apf27/Makefile [moved from board/ti/omap1510inn/Makefile with 68% similarity]
board/armadeus/apf27/apf27.c [new file with mode: 0644]
board/armadeus/apf27/apf27.h [new file with mode: 0644]
board/armadeus/apf27/fpga.c [new file with mode: 0644]
board/armadeus/apf27/fpga.h [new file with mode: 0644]
board/armadeus/apf27/lowlevel_init.S [new file with mode: 0644]
board/armltd/vexpress/vexpress_common.c
board/bluegiga/apx4devkit/spl_boot.c
board/boundary/nitrogen6x/nitrogen6x.c
board/creative/xfi3/Makefile [moved from arch/arm/cpu/arm925t/Makefile with 60% similarity]
board/creative/xfi3/spl_boot.c [new file with mode: 0644]
board/creative/xfi3/xfi3.c [new file with mode: 0644]
board/denx/m28evk/m28evk.c
board/denx/m28evk/spl_boot.c
board/freescale/mx23evk/spl_boot.c
board/freescale/mx28evk/iomux.c
board/freescale/mx28evk/mx28evk.c
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/mx6slevk/mx6slevk.c
board/isee/igep0033/board.c
board/olimex/mx23_olinuxino/spl_boot.c
board/phytec/pcm051/board.c
board/sandisk/sansa_fuze_plus/Makefile [new file with mode: 0644]
board/sandisk/sansa_fuze_plus/sfp.c [new file with mode: 0644]
board/sandisk/sansa_fuze_plus/spl_boot.c [new file with mode: 0644]
board/schulercontrol/sc_sps_1/spl_boot.c
board/ti/am335x/board.c
board/ti/omap1510inn/config.mk [deleted file]
board/ti/omap1510inn/lowlevel_init.S [deleted file]
board/ti/omap1510inn/omap1510innovator.c [deleted file]
boards.cfg
doc/README.mxs
doc/README.scrapyard
drivers/mmc/fsl_esdhc.c
drivers/mtd/nand/mxs_nand.c
drivers/net/cpsw.c
drivers/net/fec_mxc.c
drivers/net/fec_mxc.h
drivers/power/pmic/Makefile
drivers/power/pmic/pmic_tps65217.c [new file with mode: 0644]
drivers/power/pmic/pmic_tps65910.c [new file with mode: 0644]
drivers/usb/musb/musb_hcd.c
include/arm925t.h [deleted file]
include/common.h
include/configs/am335x_evm.h
include/configs/apf27.h [new file with mode: 0644]
include/configs/dra7xx_evm.h
include/configs/mx35pdk.h
include/configs/mx6sabresd.h
include/configs/mx6slevk.h
include/configs/omap1510inn.h [deleted file]
include/configs/pcm051.h
include/configs/sansa_fuze_plus.h [new file with mode: 0644]
include/configs/socfpga_cyclone5.h
include/configs/vexpress_ca15_tc2.h
include/configs/wandboard.h
include/configs/xfi3.h [new file with mode: 0644]
include/power/tps65217.h [new file with mode: 0644]
include/power/tps65910.h [new file with mode: 0644]
spl/Makefile
tools/imximage.c
tools/mxsboot.c

diff --git a/MAKEALL b/MAKEALL
index c0d04fb..956f3da 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -353,7 +353,6 @@ LIST_ARM7="$(boards_by_cpu arm720t)"
 
 LIST_ARM9="$(boards_by_cpu arm920t)    \
        $(boards_by_cpu arm926ejs)      \
-       $(boards_by_cpu arm925t)        \
        $(boards_by_cpu arm946es)       \
 "
 
diff --git a/README b/README
index 2fcad7f..0bb1ad5 100644 (file)
--- a/README
+++ b/README
@@ -139,7 +139,6 @@ Directory Hierarchy:
        /at91           Files specific to Atmel AT91RM9200 CPU
        /imx            Files specific to Freescale MC9328 i.MX CPUs
        /s3c24x0        Files specific to Samsung S3C24X0 CPUs
-      /arm925t         Files specific to ARM 925 CPUs
       /arm926ejs       Files specific to ARM 926 CPUs
       /arm1136         Files specific to ARM 1136 CPUs
       /ixp             Files specific to Intel XScale IXP CPUs
diff --git a/arch/arm/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk
deleted file mode 100644 (file)
index 67537dc..0000000
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/arm925t/cpu.c b/arch/arm/cpu/arm925t/cpu.c
deleted file mode 100644 (file)
index d0f8e1e..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <arm925t.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-       /*
-        * this function is called just before we call linux
-        * it prepares the processor for linux
-        *
-        * we turn off caches etc ...
-        */
-
-       disable_interrupts ();
-
-
-       /* turn off I/D-cache */
-       icache_disable();
-       dcache_disable();
-       /* flush I/D-cache */
-       cache_flush();
-
-       return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-       unsigned long i = 0;
-
-       asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
diff --git a/arch/arm/cpu/arm925t/omap925.c b/arch/arm/cpu/arm925t/omap925.c
deleted file mode 100644 (file)
index c0402d1..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <arm925t.h>
-
-#define MIF_CONFIG_REG 0xFFFECC0C
-#define FLASH_GLOBAL_CTRL_NWP 1
-
-void archflashwp (void *archdata, int wp)
-{
-       ulong *fgc = (ulong *) MIF_CONFIG_REG;
-
-       if (wp == 1)
-               *fgc &= ~FLASH_GLOBAL_CTRL_NWP;
-       else
-               *fgc |= FLASH_GLOBAL_CTRL_NWP;
-}
diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S
deleted file mode 100644 (file)
index 1e765b7..0000000
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- *  armboot - Startup Code for ARM925 CPU-core
- *
- *  Copyright (c) 2003  Texas Instruments
- *
- *  ----- Adapted for OMAP1510 from ARM920 code ------
- *
- *  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- *  Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
- *  Copyright (c) 2003 Kshitij  <kshitij@ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:        b       reset
-       ldr     pc, _undefined_instruction
-       ldr     pc, _software_interrupt
-       ldr     pc, _prefetch_abort
-       ldr     pc, _data_abort
-       ldr     pc, _not_used
-       ldr     pc, _irq
-       ldr     pc, _fiq
-
-_undefined_instruction:        .word undefined_instruction
-_software_interrupt:   .word software_interrupt
-_prefetch_abort:       .word prefetch_abort
-_data_abort:           .word data_abort
-_not_used:             .word not_used
-_irq:                  .word irq
-_fiq:                  .word fiq
-
-       .balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup Memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-       .word   CONFIG_SPL_TEXT_BASE
-#else
-       .word   CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-       .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-       .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-       .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-       .word   0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-       .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-       .word   0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-       /*
-        * set the cpu to SVC32 mode
-        */
-       mrs     r0,cpsr
-       bic     r0,r0,#0x1f
-       orr     r0,r0,#0xd3
-       msr     cpsr,r0
-
-       /*
-        * Set up 925T mode
-        */
-       mov r1, #0x81               /* Set ARM925T configuration. */
-       mcr p15, 0, r1, c15, c1, 0  /* Write ARM925T configuration register. */
-
-       /*
-        * turn off the watchdog, unlock/diable sequence
-        */
-       mov  r1, #0xF5
-       ldr  r0, =WDTIM_MODE
-       strh r1, [r0]
-       mov  r1, #0xA0
-       strh r1, [r0]
-
-       /*
-        * mask all IRQs by setting all bits in the INTMR - default
-        */
-       mov r1, #0xffffffff
-       ldr r0, =REG_IHL1_MIR
-       str r1, [r0]
-       ldr r0, =REG_IHL2_MIR
-       str r1, [r0]
-
-       /*
-        * wait for dpll to lock
-        */
-       ldr  r0, =CK_DPLL1
-       mov  r1, #0x10
-       strh r1, [r0]
-poll1:
-       ldrh r1, [r0]
-       ands r1, r1, #0x01
-       beq poll1
-
-       /*
-        * we do sys-critical inits only at reboot,
-        * not when booting from ram!
-        */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-       bl  cpu_init_crit
-#endif
-
-       bl      _main
-
-/*------------------------------------------------------------------------------*/
-
-       .globl  c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-       mov     pc, lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
-       /*
-        * flush v4 I/D caches
-        */
-       mov     r0, #0
-       mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
-       mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
-
-       /*
-        * disable MMU stuff and caches
-        */
-       mrc     p15, 0, r0, c1, c0, 0
-       bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
-       bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
-       orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
-       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
-       mcr     p15, 0, r0, c1, c0, 0
-
-       /*
-        * Go setup Memory and board specific bits prior to relocation.
-        */
-       mov     ip, lr          /* perserve link reg across call */
-       bl      lowlevel_init   /* go setup pll,mux,memory */
-       mov     lr, ip          /* restore link */
-       mov     pc, lr          /* back to my caller */
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE   72
-
-#define S_OLD_R0       68
-#define S_PSR          64
-#define S_PC           60
-#define S_LR           56
-#define S_SP           52
-
-#define S_IP           48
-#define S_FP           44
-#define S_R10          40
-#define S_R9           36
-#define S_R8           32
-#define S_R7           28
-#define S_R6           24
-#define S_R5           20
-#define S_R4           16
-#define S_R3           12
-#define S_R2           8
-#define S_R1           4
-#define S_R0           0
-
-#define MODE_SVC 0x13
-#define I_BIT   0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-       .macro  bad_save_user_regs
-       sub     sp, sp, #S_FRAME_SIZE           @ carve out a frame on current user stack
-       stmia   sp, {r0 - r12}                  @ Save user registers (now in svc mode) r0-r12
-
-       ldr     r2, IRQ_STACK_START_IN
-       ldmia   r2, {r2 - r3}                   @ get values for "aborted" pc and cpsr (into parm regs)
-       add     r0, sp, #S_FRAME_SIZE           @ grab pointer to old stack
-
-       add     r5, sp, #S_SP
-       mov     r1, lr
-       stmia   r5, {r0 - r3}                   @ save sp_SVC, lr_SVC, pc, cpsr
-       mov     r0, sp                          @ save current stack into r0 (param register)
-       .endm
-
-       .macro  irq_save_user_regs
-       sub     sp, sp, #S_FRAME_SIZE
-       stmia   sp, {r0 - r12}                  @ Calling r0-r12
-       add     r8, sp, #S_PC                   @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
-       stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-       str     lr, [r8, #0]                    @ Save calling PC
-       mrs     r6, spsr
-       str     r6, [r8, #4]                    @ Save CPSR
-       str     r0, [r8, #8]                    @ Save OLD_R0
-       mov     r0, sp
-       .endm
-
-       .macro  irq_restore_user_regs
-       ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
-       mov     r0, r0
-       ldr     lr, [sp, #S_PC]                 @ Get PC
-       add     sp, sp, #S_FRAME_SIZE
-       subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
-       .endm
-
-       .macro get_bad_stack
-       ldr     r13, IRQ_STACK_START_IN
-
-       str     lr, [r13]                       @ save caller lr in position 0 of saved stack
-       mrs     lr, spsr                        @ get the spsr
-       str     lr, [r13, #4]                   @ save spsr in position 1 of saved stack
-
-       mov     r13, #MODE_SVC                  @ prepare SVC-Mode
-       @ msr   spsr_c, r13
-       msr     spsr, r13                       @ switch modes, make sure moves will execute
-       mov     lr, pc                          @ capture return pc
-       movs    pc, lr                          @ jump to next instruction & switch modes.
-       .endm
-
-       .macro get_irq_stack                    @ setup IRQ stack
-       ldr     sp, IRQ_STACK_START
-       .endm
-
-       .macro get_fiq_stack                    @ setup FIQ stack
-       ldr     sp, FIQ_STACK_START
-       .endm
-
-/*
- * exception handlers
- */
-       .align  5
-undefined_instruction:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_undefined_instruction
-
-       .align  5
-software_interrupt:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_software_interrupt
-
-       .align  5
-prefetch_abort:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_prefetch_abort
-
-       .align  5
-data_abort:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_data_abort
-
-       .align  5
-not_used:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-       .align  5
-irq:
-       get_irq_stack
-       irq_save_user_regs
-       bl      do_irq
-       irq_restore_user_regs
-
-       .align  5
-fiq:
-       get_fiq_stack
-       /* someone ought to write a more effiction fiq_save_user_regs */
-       irq_save_user_regs
-       bl      do_fiq
-       irq_restore_user_regs
-
-#else
-
-       .align  5
-irq:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_irq
-
-       .align  5
-fiq:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_fiq
-
-#endif
-
-       .align  5
-.globl reset_cpu
-reset_cpu:
-       ldr     r1, rstctl1     /* get clkm1 reset ctl */
-       mov     r3, #0x3        /* dsp_en + arm_rst = global reset */
-       strh    r3, [r1]        /* force reset */
-       mov     r0, r0
-_loop_forever:
-       b       _loop_forever
-rstctl1:
-       .word   0xfffece10
diff --git a/arch/arm/cpu/arm925t/timer.c b/arch/arm/cpu/arm925t/timer.c
deleted file mode 100644 (file)
index e56b576..0000000
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * (C) Copyright 2009
- * 2N Telekomunikace, <www.2n.cz>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+ 
- */
-
-#include <common.h>
-#include <arm925t.h>
-#include <configs/omap1510.h>
-#include <asm/io.h>
-
-#define TIMER_LOAD_VAL 0xffffffff
-#define TIMER_CLOCK    (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
-
-static uint32_t timestamp;
-static uint32_t lastdec;
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int timer_init (void)
-{
-       /* Start the decrementer ticking down from 0xffffffff */
-       __raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM);
-       __raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
-               (CONFIG_SYS_PTV << MPUTIM_PTV_BIT),
-               CONFIG_SYS_TIMERBASE + CNTL_TIMER);
-
-       /* init the timestamp and lastdec value */
-       lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
-                       (TIMER_CLOCK / CONFIG_SYS_HZ);
-       timestamp = 0;         /* start "advancing" time stamp from 0 */
-
-       return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
-       int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-       uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-
-       while (tmo > 0) {
-               now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-               if (last < now) /* count down timer underflow */
-                       tmo -= TIMER_LOAD_VAL - now + last;
-               else
-                       tmo -= last - now;
-               last = now;
-       }
-}
-
-ulong get_timer_masked (void)
-{
-       uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
-                       (TIMER_CLOCK / CONFIG_SYS_HZ);
-       if (lastdec < now)      /* count down timer underflow */
-               timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) -
-                               now + lastdec;
-       else
-               timestamp += lastdec - now;
-       lastdec = now;
-
-       return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-       return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-       return CONFIG_SYS_HZ;
-}
index 8db2a67..629b727 100644 (file)
@@ -38,5 +38,10 @@ int main(void)
        DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
        DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
 
+       DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
+               offsetof(struct system_control_regs, gpcr));
+       DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
+               offsetof(struct system_control_regs, fmcr));
+
        return 0;
 }
index 0392afd..68c30af 100644 (file)
@@ -102,8 +102,9 @@ static uint8_t mxs_get_bootmode_index(void)
        return i;
 }
 
-void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
-                       const unsigned int iomux_size)
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+                        const iomux_cfg_t *iomux_setup,
+                        const unsigned int iomux_size)
 {
        struct mxs_spl_data *data = (struct mxs_spl_data *)
                ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
index f357959..4275c5d 100644 (file)
 
 #include "mxs_init.h"
 
+/**
+ * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
+ *
+ * This function switches the CPU core clock from PLL to 24MHz XTAL
+ * oscilator. This is necessary if the PLL is being reconfigured to
+ * prevent crash of the CPU core.
+ */
 static void mxs_power_clock2xtal(void)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
@@ -24,6 +31,13 @@ static void mxs_power_clock2xtal(void)
                &clkctrl_regs->hw_clkctrl_clkseq_set);
 }
 
+/**
+ * mxs_power_clock2pll() - Switch CPU core clock source to PLL
+ *
+ * This function switches the CPU core clock from 24MHz XTAL oscilator
+ * to PLL. This can only be called once the PLL has re-locked and once
+ * the PLL is stable after reconfiguration.
+ */
 static void mxs_power_clock2pll(void)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
@@ -36,6 +50,13 @@ static void mxs_power_clock2pll(void)
                        CLKCTRL_CLKSEQ_BYPASS_CPU);
 }
 
+/**
+ * mxs_power_set_auto_restart() - Set the auto-restart bit
+ *
+ * This function ungates the RTC block and sets the AUTO_RESTART
+ * bit to work around a design bug on MX28EVK Rev. A .
+ */
 static void mxs_power_set_auto_restart(void)
 {
        struct mxs_rtc_regs *rtc_regs =
@@ -66,6 +87,14 @@ static void mxs_power_set_auto_restart(void)
                ;
 }
 
+/**
+ * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
+ *
+ * This function configures the VDDIO, VDDA and VDDD linear regulators output
+ * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
+ * converter. This is the recommended setting for the case where we use both
+ * linear regulators and DC-DC converter to power the VDDIO rail.
+ */
 static void mxs_power_set_linreg(void)
 {
        struct mxs_power_regs *power_regs =
@@ -85,6 +114,11 @@ static void mxs_power_set_linreg(void)
                        POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 }
 
+/**
+ * mxs_get_batt_volt() - Measure battery input voltage
+ *
+ * This function retrieves the battery input voltage and returns it.
+ */
 static int mxs_get_batt_volt(void)
 {
        struct mxs_power_regs *power_regs =
@@ -96,11 +130,24 @@ static int mxs_get_batt_volt(void)
        return volt;
 }
 
+/**
+ * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
+ *
+ * This function checks if the battery input voltage is higher than 3.6V and
+ * therefore allows the system to successfully boot using this power source.
+ */
 static int mxs_is_batt_ready(void)
 {
        return (mxs_get_batt_volt() >= 3600);
 }
 
+/**
+ * mxs_is_batt_good() - Test if battery is operational at all
+ *
+ * This function starts recharging the battery and tests if the input current
+ * provided by the 5V input recharging the battery is also sufficient to power
+ * the DC-DC converter.
+ */
 static int mxs_is_batt_good(void)
 {
        struct mxs_power_regs *power_regs =
@@ -141,6 +188,15 @@ static int mxs_is_batt_good(void)
        return 0;
 }
 
+/**
+ * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
+ *
+ * This function enables the 5V detection comparator and sets the 5V valid
+ * threshold to 4.4V . We use 4.4V threshold here to make sure that even
+ * under high load, the voltage drop on the 5V input won't be so critical
+ * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
+ * converter and thus making the system crash.
+ */
 static void mxs_power_setup_5v_detect(void)
 {
        struct mxs_power_regs *power_regs =
@@ -153,6 +209,12 @@ static void mxs_power_setup_5v_detect(void)
                        POWER_5VCTRL_PWRUP_VBUS_CMPS);
 }
 
+/**
+ * mxs_src_power_init() - Preconfigure the power block
+ *
+ * This function configures reasonable values for the DC-DC control loop
+ * and battery monitor.
+ */
 static void mxs_src_power_init(void)
 {
        struct mxs_power_regs *power_regs =
@@ -184,6 +246,12 @@ static void mxs_src_power_init(void)
        clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 }
 
+/**
+ * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
+ *
+ * This function configures the necessary parameters for the 4P2 linear
+ * regulator to supply the DC-DC converter from 5V input.
+ */
 static void mxs_power_init_4p2_params(void)
 {
        struct mxs_power_regs *power_regs =
@@ -208,6 +276,12 @@ static void mxs_power_init_4p2_params(void)
                0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
+/**
+ * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
+ * @xfer:      Select if the input shall be enabled or disabled
+ *
+ * This function enables or disables the 4P2 input into the DC-DC converter.
+ */
 static void mxs_enable_4p2_dcdc_input(int xfer)
 {
        struct mxs_power_regs *power_regs =
@@ -304,6 +378,12 @@ static void mxs_enable_4p2_dcdc_input(int xfer)
                                POWER_CTRL_ENIRQ_VDD5V_DROOP);
 }
 
+/**
+ * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
+ *
+ * This function enables the 4P2 regulator and switches the DC-DC converter
+ * to use the 4P2 input.
+ */
 static void mxs_power_init_4p2_regulator(void)
 {
        struct mxs_power_regs *power_regs =
@@ -388,6 +468,12 @@ static void mxs_power_init_4p2_regulator(void)
        writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 }
 
+/**
+ * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
+ *
+ * This function configures the DC-DC converter to be supplied from the 4P2
+ * linear regulator.
+ */
 static void mxs_power_init_dcdc_4p2_source(void)
 {
        struct mxs_power_regs *power_regs =
@@ -410,6 +496,12 @@ static void mxs_power_init_dcdc_4p2_source(void)
        }
 }
 
+/**
+ * mxs_power_enable_4p2() - Power up the 4P2 regulator
+ *
+ * This function drives the process of powering up the 4P2 linear regulator
+ * and switching the DC-DC converter input over to the 4P2 linear regulator.
+ */
 static void mxs_power_enable_4p2(void)
 {
        struct mxs_power_regs *power_regs =
@@ -469,6 +561,14 @@ static void mxs_power_enable_4p2(void)
                        &power_regs->hw_power_charge_clr);
 }
 
+/**
+ * mxs_boot_valid_5v() - Boot from 5V supply
+ *
+ * This function configures the power block to boot from valid 5V input.
+ * This is called only if the 5V is reliable and can properly supply the
+ * CPU. This function proceeds to configure the 4P2 converter to be supplied
+ * from the 5V input.
+ */
 static void mxs_boot_valid_5v(void)
 {
        struct mxs_power_regs *power_regs =
@@ -492,6 +592,11 @@ static void mxs_boot_valid_5v(void)
        mxs_power_enable_4p2();
 }
 
+/**
+ * mxs_powerdown() - Shut down the system
+ *
+ * This function powers down the CPU completely.
+ */
 static void mxs_powerdown(void)
 {
        struct mxs_power_regs *power_regs =
@@ -501,6 +606,12 @@ static void mxs_powerdown(void)
                &power_regs->hw_power_reset);
 }
 
+/**
+ * mxs_batt_boot() - Configure the power block to boot from battery input
+ *
+ * This function configures the power block to boot from the battery voltage
+ * supply.
+ */
 static void mxs_batt_boot(void)
 {
        struct mxs_power_regs *power_regs =
@@ -545,6 +656,14 @@ static void mxs_batt_boot(void)
                0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
+/**
+ * mxs_handle_5v_conflict() - Test if the 5V input is reliable
+ *
+ * This function tests if the 5V input can reliably supply the system. If it
+ * can, then proceed to configuring the system to boot from 5V source, otherwise
+ * try booting from battery supply. If we can not boot from battery supply
+ * either, shut down the system.
+ */
 static void mxs_handle_5v_conflict(void)
 {
        struct mxs_power_regs *power_regs =
@@ -581,6 +700,12 @@ static void mxs_handle_5v_conflict(void)
        }
 }
 
+/**
+ * mxs_5v_boot() - Configure the power block to boot from 5V input
+ *
+ * This function handles configuration of the power block when supplied by
+ * a 5V input.
+ */
 static void mxs_5v_boot(void)
 {
        struct mxs_power_regs *power_regs =
@@ -604,6 +729,12 @@ static void mxs_5v_boot(void)
        mxs_handle_5v_conflict();
 }
 
+/**
+ * mxs_init_batt_bo() - Configure battery brownout threshold
+ *
+ * This function configures the battery input brownout threshold. The value
+ * at which the battery brownout happens is configured to 3.0V in the code.
+ */
 static void mxs_init_batt_bo(void)
 {
        struct mxs_power_regs *power_regs =
@@ -618,6 +749,12 @@ static void mxs_init_batt_bo(void)
        writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 }
 
+/**
+ * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
+ *
+ * This function turns off the VDDD linear regulator and therefore makes
+ * the VDDD rail be supplied only by the DC-DC converter.
+ */
 static void mxs_switch_vddd_to_dcdc_source(void)
 {
        struct mxs_power_regs *power_regs =
@@ -632,6 +769,15 @@ static void mxs_switch_vddd_to_dcdc_source(void)
                POWER_VDDDCTRL_DISABLE_STEPPING);
 }
 
+/**
+ * mxs_power_configure_power_source() - Configure power block source
+ *
+ * This function is the core of the power configuration logic. The function
+ * selects the power block input source and configures the whole power block
+ * accordingly. After the configuration is complete and the system is stable
+ * again, the function switches the CPU clock source back to PLL. Finally,
+ * the function switches the voltage rails to DC-DC converter.
+ */
 static void mxs_power_configure_power_source(void)
 {
        int batt_ready, batt_good;
@@ -676,6 +822,15 @@ static void mxs_power_configure_power_source(void)
 #endif
 }
 
+/**
+ * mxs_enable_output_rail_protection() - Enable power rail protection
+ *
+ * This function enables overload protection on the power rails. This is
+ * triggered if the power rails' voltage drops rapidly due to overload and
+ * in such case, the supply to the powerrail is cut-off, protecting the
+ * CPU from damage. Note that under such condition, the system will likely
+ * crash or misbehave.
+ */
 static void mxs_enable_output_rail_protection(void)
 {
        struct mxs_power_regs *power_regs =
@@ -694,6 +849,13 @@ static void mxs_enable_output_rail_protection(void)
                        POWER_VDDIOCTRL_PWDN_BRNOUT);
 }
 
+/**
+ * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
+ *
+ * This function tests if the VDDIO rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
 static int mxs_get_vddio_power_source_off(void)
 {
        struct mxs_power_regs *power_regs =
@@ -722,6 +884,13 @@ static int mxs_get_vddio_power_source_off(void)
 
 }
 
+/**
+ * mxs_get_vddd_power_source_off() - Get VDDD rail power source
+ *
+ * This function tests if the VDDD rail is supplied by linear regulator
+ * or by the DC-DC converter. Returns 1 if powered by linear regulator,
+ * returns 0 if powered by the DC-DC converter.
+ */
 static int mxs_get_vddd_power_source_off(void)
 {
        struct mxs_power_regs *power_regs =
@@ -810,6 +979,18 @@ static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
 };
 #endif
 
+/**
+ * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
+ * @cfg:               Configuration data of the DC-DC converter rail
+ * @new_target:                New target voltage of the DC-DC converter rail
+ * @new_brownout:      New brownout trigger voltage
+ *
+ * This function configures the output voltage on the DC-DC converter rail.
+ * The rail is selected by the @cfg argument. The new voltage target is
+ * selected by the @new_target and the voltage is specified in mV. The
+ * new brownout value is selected by the @new_brownout argument and the
+ * value is also in mV.
+ */
 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
                                uint32_t new_target, uint32_t new_brownout)
 {
@@ -883,6 +1064,14 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
        }
 }
 
+/**
+ * mxs_setup_batt_detect() - Start the battery voltage measurement logic
+ *
+ * This function starts and configures the LRADC block. This allows the
+ * power initialization code to measure battery voltage and based on this
+ * knowledge, decide whether to boot at all, boot from battery or boot
+ * from 5V input.
+ */
 static void mxs_setup_batt_detect(void)
 {
        mxs_lradc_init();
@@ -890,6 +1079,14 @@ static void mxs_setup_batt_detect(void)
        early_delay(10);
 }
 
+/**
+ * mxs_ungate_power() - Ungate the POWER block
+ *
+ * This function ungates clock to the power block. In case the power block
+ * was still gated at this point, it will not be possible to configure the
+ * block and therefore the power initialization would fail. This function
+ * is only needed on i.MX233, on i.MX28 the power block is always ungated.
+ */
 static void mxs_ungate_power(void)
 {
 #ifdef CONFIG_MX23
@@ -900,6 +1097,12 @@ static void mxs_ungate_power(void)
 #endif
 }
 
+/**
+ * mxs_power_init() - The power block init main function
+ *
+ * This function calls all the power block initialization functions in
+ * proper sequence to start the power block.
+ */
 void mxs_power_init(void)
 {
        struct mxs_power_regs *power_regs =
@@ -933,6 +1136,12 @@ void mxs_power_init(void)
 }
 
 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
+/**
+ * mxs_power_wait_pswitch() - Wait for power switch to be pressed
+ *
+ * This function waits until the power-switch was pressed to start booting
+ * the board.
+ */
 void mxs_power_wait_pswitch(void)
 {
        struct mxs_power_regs *power_regs =
index 94b2b3f..3e454ae 100644 (file)
@@ -152,39 +152,49 @@ _reset:
        /*
         * Store all registers on old stack pointer, this will allow us later to
         * return to the BootROM and let the BootROM load U-Boot into RAM.
+        *
+        * WARNING: Register r0 and r1 are used by the BootROM to pass data
+        *          to the called code. Register r0 will contain arbitrary
+        *          data that are set in the BootStream. In case this code
+        *          was started with CALL instruction, register r1 will contain
+        *          pointer to the return value this function can then set.
+        *          The code below MUST NOT CHANGE register r0 and r1 !
         */
        push    {r0-r12,r14}
 
-       /* save control register c1 */
-       mrc     p15, 0, r0, c1, c0, 0
-       push    {r0}
+       /* Save control register c1 */
+       mrc     p15, 0, r2, c1, c0, 0
+       push    {r2}
 
-       /*
-        * set the cpu to SVC32 mode and store old CPSR register content
-        */
-       mrs     r0,cpsr
-       push    {r0}
-       bic     r0,r0,#0x1f
-       orr     r0,r0,#0xd3
-       msr     cpsr,r0
+       /* Set the cpu to SVC32 mode and store old CPSR register content. */
+       mrs     r2, cpsr
+       push    {r2}
+       bic     r2, r2, #0x1f
+       orr     r2, r2, #0xd3
+       msr     cpsr, r2
 
        bl      board_init_ll
 
+       /* Restore BootROM's CPU mode (especially FIQ). */
+       pop     {r2}
+       msr     cpsr,r2
+
        /*
-        * restore bootrom's cpu mode (especially FIQ)
+        * Restore c1 register. Especially set exception vector location
+        * back to BootROM space which is required by bootrom for USB boot.
         */
-       pop     {r0}
-       msr     cpsr,r0
+       pop     {r2}
+       mcr     p15, 0, r2, c1, c0, 0
+
+       pop     {r0-r12,r14}
 
        /*
-        * restore c1 register
-        * (especially set exception vector location back to
-        * bootrom space which is required by bootrom for USB boot)
+        * In case this code was started by the CALL instruction, the register
+        * r0 is examined by the BootROM after this code returns. The value in
+        * r0 must be set to 0 to indicate successful return.
         */
-       pop     {r0}
-       mcr     p15, 0, r0, c1, c0, 0
+       mov r0, #0
 
-       pop     {r0-r12,r14}
        bx      lr
 
 _hang:
index b723e22..ee4b021 100644 (file)
@@ -20,6 +20,11 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CON
 SOBJS  += lowlevel_init.o
 endif
 
+ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),)
+SOBJS  += nonsec_virt.o
+COBJS  += virt-v7.o
+endif
+
 SRCS   := $(START:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
 START  := $(addprefix $(obj),$(START))
index 2ea3d69..a31bf40 100644 (file)
@@ -27,6 +27,7 @@
 #include <miiphy.h>
 #include <cpsw.h>
 #include <asm/errno.h>
+#include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
@@ -137,6 +138,16 @@ int arch_misc_init(void)
 }
 
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+       do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
 static void rtc32k_enable(void)
 {
        struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
index e5f287b..fabe259 100644 (file)
@@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
        .cm_div_m2_dpll         = CM_WKUP + 0xA0,
 };
 
-const struct dpll_params dpll_mpu = {
+struct dpll_params dpll_mpu_opp100 = {
                CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
+const struct dpll_params dpll_core_opp100 = {
                1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+               MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+               50, OSC-1, -1, -1, 1, 1, 1};
 const struct dpll_params dpll_per = {
                960, OSC-1, 5, -1, -1, -1, -1};
 
index 63afaaa..50eb598 100644 (file)
@@ -17,6 +17,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
+#include <power/tps65910.h>
 
 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
 
@@ -119,3 +120,59 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+       int sil_rev;
+
+       sil_rev = readl(&cdev->deviceid) >> 28;
+
+       if (sil_rev == 1)
+               /* PG 2.0, efuse may not be set. */
+               return MPUPLL_M_800;
+       else if (sil_rev >= 2) {
+               /* Check what the efuse says our max speed is. */
+               int efuse_arm_mpu_max_freq;
+               efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+               switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
+               case AM335X_ZCZ_1000:
+                       return MPUPLL_M_1000;
+               case AM335X_ZCZ_800:
+                       return MPUPLL_M_800;
+               case AM335X_ZCZ_720:
+                       return MPUPLL_M_720;
+               case AM335X_ZCZ_600:
+               case AM335X_ZCE_600:
+                       return MPUPLL_M_600;
+               case AM335X_ZCZ_300:
+               case AM335X_ZCE_300:
+                       return MPUPLL_M_300;
+               }
+       }
+
+       /* PG 1.0 or otherwise unknown, use the PG1.0 max */
+       return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+       /* For PG2.1 and later, we have one set of values. */
+       if (sil_rev >= 2) {
+               switch (frequency) {
+               case MPUPLL_M_1000:
+                       return TPS65910_OP_REG_SEL_1_3_2_5;
+               case MPUPLL_M_800:
+                       return TPS65910_OP_REG_SEL_1_2_6;
+               case MPUPLL_M_720:
+                       return TPS65910_OP_REG_SEL_1_2_0;
+               case MPUPLL_M_600:
+               case MPUPLL_M_300:
+                       return TPS65910_OP_REG_SEL_1_1_3;
+               }
+       }
+
+       /* Default to PG1.0/PG2.0 values. */
+       return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
index 7efb0d2..df11678 100644 (file)
@@ -228,13 +228,13 @@ static u32 get_axi_clk(void)
 
 static u32 get_emi_slow_clk(void)
 {
-       u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
+       u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
 
        cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
        emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
        emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
-       emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
-       emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
+       emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
+       emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
 
        switch (emi_clk_sel) {
        case 0:
@@ -251,7 +251,7 @@ static u32 get_emi_slow_clk(void)
                break;
        }
 
-       return root_freq / (emi_slow_pof + 1);
+       return root_freq / (emi_slow_podf + 1);
 }
 
 #ifdef CONFIG_MX6SL
@@ -282,6 +282,36 @@ static u32 get_mmdc_ch0_clk(void)
        return freq / (podf + 1);
 
 }
+
+int enable_fec_anatop_clock(void)
+{
+       u32 reg = 0;
+       s32 timeout = 100000;
+
+       struct anatop_regs __iomem *anatop =
+               (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+       reg = readl(&anatop->pll_enet);
+       if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
+           (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
+               reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
+               writel(reg, &anatop->pll_enet);
+               while (timeout--) {
+                       if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
+                               break;
+               }
+               if (timeout < 0)
+                       return -ETIMEDOUT;
+       }
+
+       /* Enable FEC clock */
+       reg |= BM_ANADIG_PLL_ENET_ENABLE;
+       reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
+       writel(reg, &anatop->pll_enet);
+
+       return 0;
+}
+
 #else
 static u32 get_mmdc_ch0_clk(void)
 {
@@ -457,7 +487,7 @@ void enable_ipu_clock(void)
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
        int reg;
        reg = readl(&mxc_ccm->CCGR3);
-       reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+       reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
        writel(reg, &mxc_ccm->CCGR3);
 }
 /***************************************************/
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
new file mode 100644 (file)
index 0000000..358348f
--- /dev/null
@@ -0,0 +1,208 @@
+/*
+ * code for switching cores into non-secure state and into HYP mode
+ *
+ * Copyright (c) 2013  Andre Przywara <andre.przywara@linaro.org>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/gic.h>
+#include <asm/armv7.h>
+
+.arch_extension sec
+.arch_extension virt
+
+/* the vector table for secure state and HYP mode */
+_monitor_vectors:
+       .word 0 /* reset */
+       .word 0 /* undef */
+       adr pc, _secure_monitor
+       .word 0
+       .word 0
+       adr pc, _hyp_trap
+       .word 0
+       .word 0
+
+/*
+ * secure monitor handler
+ * U-boot calls this "software interrupt" in start.S
+ * This is executed on a "smc" instruction, we use a "smc #0" to switch
+ * to non-secure state.
+ * We use only r0 and r1 here, due to constraints in the caller.
+ */
+       .align  5
+_secure_monitor:
+       mrc     p15, 0, r1, c1, c1, 0           @ read SCR
+       bic     r1, r1, #0x4e                   @ clear IRQ, FIQ, EA, nET bits
+       orr     r1, r1, #0x31                   @ enable NS, AW, FW bits
+
+#ifdef CONFIG_ARMV7_VIRT
+       mrc     p15, 0, r0, c0, c1, 1           @ read ID_PFR1
+       and     r0, r0, #CPUID_ARM_VIRT_MASK    @ mask virtualization bits
+       cmp     r0, #(1 << CPUID_ARM_VIRT_SHIFT)
+       orreq   r1, r1, #0x100                  @ allow HVC instruction
+#endif
+
+       mcr     p15, 0, r1, c1, c1, 0           @ write SCR (with NS bit set)
+
+#ifdef CONFIG_ARMV7_VIRT
+       mrceq   p15, 0, r0, c12, c0, 1          @ get MVBAR value
+       mcreq   p15, 4, r0, c12, c0, 0          @ write HVBAR
+#endif
+
+       movs    pc, lr                          @ return to non-secure SVC
+
+_hyp_trap:
+       mrs     lr, elr_hyp     @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1
+       mov pc, lr                              @ do no switch modes, but
+                                               @ return to caller
+
+/*
+ * Secondary CPUs start here and call the code for the core specific parts
+ * of the non-secure and HYP mode transition. The GIC distributor specific
+ * code has already been executed by a C function before.
+ * Then they go back to wfi and wait to be woken up by the kernel again.
+ */
+ENTRY(_smp_pen)
+       mrs     r0, cpsr
+       orr     r0, r0, #0xc0
+       msr     cpsr, r0                        @ disable interrupts
+       ldr     r1, =_start
+       mcr     p15, 0, r1, c12, c0, 0          @ set VBAR
+
+       bl      _nonsec_init
+       mov     r12, r0                         @ save GICC address
+#ifdef CONFIG_ARMV7_VIRT
+       bl      _switch_to_hyp
+#endif
+
+       ldr     r1, [r12, #GICC_IAR]            @ acknowledge IPI
+       str     r1, [r12, #GICC_EOIR]           @ signal end of interrupt
+
+       adr     r0, _smp_pen                    @ do not use this address again
+       b       smp_waitloop                    @ wait for IPIs, board specific
+ENDPROC(_smp_pen)
+
+/*
+ * Switch a core to non-secure state.
+ *
+ *  1. initialize the GIC per-core interface
+ *  2. allow coprocessor access in non-secure modes
+ *  3. switch the cpu mode (by calling "smc #0")
+ *
+ * Called from smp_pen by secondary cores and directly by the BSP.
+ * Do not assume that the stack is available and only use registers
+ * r0-r3 and r12.
+ *
+ * PERIPHBASE is used to get the GIC address. This could be 40 bits long,
+ * though, but we check this in C before calling this function.
+ */
+ENTRY(_nonsec_init)
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+       ldr     r2, =CONFIG_ARM_GIC_BASE_ADDRESS
+#else
+       mrc     p15, 4, r2, c15, c0, 0          @ read CBAR
+       bfc     r2, #0, #15                     @ clear reserved bits
+#endif
+       add     r3, r2, #GIC_DIST_OFFSET        @ GIC dist i/f offset
+       mvn     r1, #0                          @ all bits to 1
+       str     r1, [r3, #GICD_IGROUPRn]        @ allow private interrupts
+
+       mrc     p15, 0, r0, c0, c0, 0           @ read MIDR
+       ldr     r1, =MIDR_PRIMARY_PART_MASK
+       and     r0, r0, r1                      @ mask out variant and revision
+
+       ldr     r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK
+       cmp     r0, r1                          @ check for Cortex-A7
+
+       ldr     r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK
+       cmpne   r0, r1                          @ check for Cortex-A15
+
+       movne   r1, #GIC_CPU_OFFSET_A9          @ GIC CPU offset for A9
+       moveq   r1, #GIC_CPU_OFFSET_A15         @ GIC CPU offset for A15/A7
+       add     r3, r2, r1                      @ r3 = GIC CPU i/f addr
+
+       mov     r1, #1                          @ set GICC_CTLR[enable]
+       str     r1, [r3, #GICC_CTLR]            @ and clear all other bits
+       mov     r1, #0xff
+       str     r1, [r3, #GICC_PMR]             @ set priority mask register
+
+       movw    r1, #0x3fff
+       movt    r1, #0x0006
+       mcr     p15, 0, r1, c1, c1, 2           @ NSACR = all copros to non-sec
+
+/* The CNTFRQ register of the generic timer needs to be
+ * programmed in secure state. Some primary bootloaders / firmware
+ * omit this, so if the frequency is provided in the configuration,
+ * we do this here instead.
+ * But first check if we have the generic timer.
+ */
+#ifdef CONFIG_SYS_CLK_FREQ
+       mrc     p15, 0, r0, c0, c1, 1           @ read ID_PFR1
+       and     r0, r0, #CPUID_ARM_GENTIMER_MASK        @ mask arch timer bits
+       cmp     r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
+       ldreq   r1, =CONFIG_SYS_CLK_FREQ
+       mcreq   p15, 0, r1, c14, c0, 0          @ write CNTFRQ
+#endif
+
+       adr     r1, _monitor_vectors
+       mcr     p15, 0, r1, c12, c0, 1          @ set MVBAR to secure vectors
+
+       mrc     p15, 0, ip, c12, c0, 0          @ save secure copy of VBAR
+
+       isb
+       smc     #0                              @ call into MONITOR mode
+
+       mcr     p15, 0, ip, c12, c0, 0          @ write non-secure copy of VBAR
+
+       mov     r1, #1
+       str     r1, [r3, #GICC_CTLR]            @ enable non-secure CPU i/f
+       add     r2, r2, #GIC_DIST_OFFSET
+       str     r1, [r2, #GICD_CTLR]            @ allow private interrupts
+
+       mov     r0, r3                          @ return GICC address
+
+       bx      lr
+ENDPROC(_nonsec_init)
+
+#ifdef CONFIG_SMP_PEN_ADDR
+/* void __weak smp_waitloop(unsigned previous_address); */
+ENTRY(smp_waitloop)
+       wfi
+       ldr     r1, =CONFIG_SMP_PEN_ADDR        @ load start address
+       ldr     r1, [r1]
+       cmp     r0, r1                  @ make sure we dont execute this code
+       beq     smp_waitloop            @ again (due to a spurious wakeup)
+       mov     pc, r1
+ENDPROC(smp_waitloop)
+.weak smp_waitloop
+#endif
+
+ENTRY(_switch_to_hyp)
+       mov     r0, lr
+       mov     r1, sp                          @ save SVC copy of LR and SP
+       isb
+       hvc #0                   @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1
+       mov     sp, r1
+       mov     lr, r0                          @ restore SVC copy of LR and SP
+
+       bx      lr
+ENDPROC(_switch_to_hyp)
index 6b4772b..0ffa03a 100644 (file)
@@ -76,6 +76,9 @@ void spl_board_init(void)
 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
        arch_misc_init();
 #endif
+#ifdef CONFIG_AM33XX
+       am33xx_spl_board_init();
+#endif
 }
 
 int board_mmc_init(bd_t *bis)
index 7580594..ab0c568 100644 (file)
@@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores)
 
        val = optimize_vcore_voltage(&vcores->iva);
        do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
-
-        if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
-               /* Configure LDO SRAM "magic" bits */
-               writel(2, (*prcm)->prm_sldo_core_setup);
-               writel(2, (*prcm)->prm_sldo_mpu_setup);
-               writel(2, (*prcm)->prm_sldo_mm_setup);
-       }
 }
 
 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
index 579818d..5a3d52c 100644 (file)
@@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = {
        .prm_vc_val_bypass = 0x4ae07ba0,
        .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
        .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
-       .prm_sldo_core_setup = 0x4ae07bc4,
-       .prm_sldo_core_ctrl = 0x4ae07bc8,
-       .prm_sldo_mpu_setup = 0x4ae07bcc,
-       .prm_sldo_mpu_ctrl = 0x4ae07bd0,
-       .prm_sldo_mm_setup = 0x4ae07bd4,
-       .prm_sldo_mm_ctrl = 0x4ae07bd8,
 
        /* SCRM stuff, used by some boards */
        .scrm_auxclk0 = 0x4ae0a310,
@@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = {
        .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
        .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
 
-       .prm_sldo_core_setup = 0x4ae07cc4,
-       .prm_sldo_core_ctrl = 0x4ae07cc8,
-       .prm_sldo_mpu_setup = 0x4ae07ccc,
-       .prm_sldo_mpu_ctrl = 0x4ae07cd0,
-       .prm_sldo_mm_setup = 0x4ae07cd4,
-       .prm_sldo_mm_ctrl = 0x4ae07cd8,
        .prm_abbldo_mpu_setup = 0x4ae07cdc,
        .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
 
index 5024fc5..0859e44 100644 (file)
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
 LIB    =  $(obj)lib$(SOC).o
 
 SOBJS  := lowlevel_init.o
-COBJS-y        := misc.o timer.o reset_manager.o
+COBJS-y        := misc.o timer.o reset_manager.o system_manager.o
 COBJS-$(CONFIG_SPL_BUILD) += spl.o
 
 COBJS  := $(COBJS-y)
index 2b9be28..74bceab 100644 (file)
@@ -12,6 +12,7 @@
 #include <image.h>
 #include <asm/arch/reset_manager.h>
 #include <spl.h>
+#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -25,6 +26,11 @@ u32 spl_boot_device(void)
  */
 void spl_board_init(void)
 {
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+       /* configure the pin muxing through system manager */
+       sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
        /* de-assert reset for peripherals and bridges based on handoff */
        reset_deassert_peripherals_handoff();
 
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644 (file)
index 0000000..d96521b
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+       unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+       const unsigned long *pval = sys_mgr_init_table;
+       unsigned long i;
+
+       for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
+               i++, offset += sizeof(unsigned long)) {
+               writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+       }
+}
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
new file mode 100644 (file)
index 0000000..6de7fe7
--- /dev/null
@@ -0,0 +1,173 @@
+/*
+ * (C) Copyright 2013
+ * Andre Przywara, Linaro
+ *
+ * Routines to transition ARMv7 processors from secure into non-secure state
+ * and from non-secure SVC into HYP mode
+ * needed to enable ARMv7 virtualization for current hypervisors
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+
+unsigned long gic_dist_addr;
+
+static unsigned int read_cpsr(void)
+{
+       unsigned int reg;
+
+       asm volatile ("mrs %0, cpsr\n" : "=r" (reg));
+       return reg;
+}
+
+static unsigned int read_id_pfr1(void)
+{
+       unsigned int reg;
+
+       asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
+       return reg;
+}
+
+static unsigned long get_gicd_base_address(void)
+{
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+       return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+#else
+       unsigned midr;
+       unsigned periphbase;
+
+       /* check whether we are an Cortex-A15 or A7.
+        * The actual HYP switch should work with all CPUs supporting
+        * the virtualization extension, but we need the GIC address,
+        * which we know only for sure for those two CPUs.
+        */
+       asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
+       switch (midr & MIDR_PRIMARY_PART_MASK) {
+       case MIDR_CORTEX_A9_R0P1:
+       case MIDR_CORTEX_A15_R0P0:
+       case MIDR_CORTEX_A7_R0P0:
+               break;
+       default:
+               printf("nonsec: could not determine GIC address.\n");
+               return -1;
+       }
+
+       /* get the GIC base address from the CBAR register */
+       asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
+
+       /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+        * encode this). Bail out here since we cannot access this without
+        * enabling paging.
+        */
+       if ((periphbase & 0xff) != 0) {
+               printf("nonsec: PERIPHBASE is above 4 GB, no access.\n");
+               return -1;
+       }
+
+       return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
+#endif
+}
+
+static void kick_secondary_cpus_gic(unsigned long gicdaddr)
+{
+       /* kick all CPUs (except this one) by writing to GICD_SGIR */
+       writel(1U << 24, gicdaddr + GICD_SGIR);
+}
+
+void __weak smp_kick_all_cpus(void)
+{
+       kick_secondary_cpus_gic(gic_dist_addr);
+}
+
+int armv7_switch_hyp(void)
+{
+       unsigned int reg;
+
+       /* check whether we are in HYP mode already */
+       if ((read_cpsr() & 0x1f) == 0x1a) {
+               debug("CPU already in HYP mode\n");
+               return 0;
+       }
+
+       /* check whether the CPU supports the virtualization extensions */
+       reg = read_id_pfr1();
+       if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) {
+               printf("HYP mode: Virtualization extensions not implemented.\n");
+               return -1;
+       }
+
+       /* call the HYP switching code on this CPU also */
+       _switch_to_hyp();
+
+       if ((read_cpsr() & 0x1F) != 0x1a) {
+               printf("HYP mode: switch not successful.\n");
+               return -1;
+       }
+
+       return 0;
+}
+
+int armv7_switch_nonsec(void)
+{
+       unsigned int reg;
+       unsigned itlinesnr, i;
+
+       /* check whether the CPU supports the security extensions */
+       reg = read_id_pfr1();
+       if ((reg & 0xF0) == 0) {
+               printf("nonsec: Security extensions not implemented.\n");
+               return -1;
+       }
+
+       /* the SCR register will be set directly in the monitor mode handler,
+        * according to the spec one should not tinker with it in secure state
+        * in SVC mode. Do not try to read it once in non-secure state,
+        * any access to it will trap.
+        */
+
+       gic_dist_addr = get_gicd_base_address();
+       if (gic_dist_addr == -1)
+               return -1;
+
+       /* enable the GIC distributor */
+       writel(readl(gic_dist_addr + GICD_CTLR) | 0x03,
+              gic_dist_addr + GICD_CTLR);
+
+       /* TYPER[4:0] contains an encoded number of available interrupts */
+       itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f;
+
+       /* set all bits in the GIC group registers to one to allow access
+        * from non-secure state. The first 32 interrupts are private per
+        * CPU and will be set later when enabling the GIC for each core
+        */
+       for (i = 1; i <= itlinesnr; i++)
+               writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
+
+       smp_set_core_boot_addr((unsigned long)_smp_pen, -1);
+       smp_kick_all_cpus();
+
+       /* call the non-sec switching code on this CPU also */
+       _nonsec_init();
+
+       return 0;
+}
index 140379f..02ed595 100644 (file)
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000  1000
+#define MPUPLL_M_800   800
+#define MPUPLL_M_720   720
+#define MPUPLL_M_600   600
+#define MPUPLL_M_550   550
+#define MPUPLL_M_300   300
+
 /* MAIN PLL Fdll = 550 MHz, by default */
 #ifndef CONFIG_SYS_MPUCLK
-#define CONFIG_SYS_MPUCLK      550
+#define CONFIG_SYS_MPUCLK      MPUPLL_M_550
 #endif
 
 #define UART_RESET             (0x1 << 1)
@@ -21,5 +29,7 @@
 #define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
 extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
 
 #endif /* endif _CLOCKS_AM33XX_H_ */
index 73e6db8..52fa128 100644 (file)
 #define AM335X                         0xB944
 #define TI81XX                         0xB81E
 #define DEVICE_ID                      (CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK                 0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300                 0x1FEF
+#define AM335X_ZCZ_600                 0x1FAF
+#define AM335X_ZCZ_720                 0x1F2F
+#define AM335X_ZCZ_800                 0x1E2F
+#define AM335X_ZCZ_1000                        0x1C2F
+#define AM335X_ZCE_300                 0x1FDF
+#define AM335X_ZCE_600                 0x1F9F
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK                   (BIT(0) | BIT(1) | BIT(2)\
@@ -509,6 +519,8 @@ struct ctrl_dev {
        unsigned int macid1h;           /* offset 0x3c */
        unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
+       unsigned int resv5[106];
+       unsigned int efuse_sma;         /* offset 0x1FC */
 };
 
 /* gmii_sel register defines */
index 95f7a9a..fe48b5f 100644 (file)
 #define MT41J512M8RH125_IOCTRL_VALUE           0x18B
 
 /* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x06
-#define K4B2G1646EBIH9_EMIF_TIM1               0x0888A39B
-#define K4B2G1646EBIH9_EMIF_TIM2               0x2A04011A
-#define K4B2G1646EBIH9_EMIF_TIM3               0x501F820F
-#define K4B2G1646EBIH9_EMIF_SDCFG              0x61C24AB2
-#define K4B2G1646EBIH9_EMIF_SDREF              0x0000093B
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x07
+#define K4B2G1646EBIH9_EMIF_TIM1               0x0AAAE51B
+#define K4B2G1646EBIH9_EMIF_TIM2               0x2A1D7FDA
+#define K4B2G1646EBIH9_EMIF_TIM3               0x501F83FF
+#define K4B2G1646EBIH9_EMIF_SDCFG              0x61C052B2
+#define K4B2G1646EBIH9_EMIF_SDREF              0x00000C30
 #define K4B2G1646EBIH9_ZQ_CFG                  0x50074BE4
 #define K4B2G1646EBIH9_DLL_LOCK_DIFF           0x1
-#define K4B2G1646EBIH9_RATIO                   0x40
-#define K4B2G1646EBIH9_INVERT_CLKOUT           0x1
-#define K4B2G1646EBIH9_RD_DQS                  0x3B
-#define K4B2G1646EBIH9_WR_DQS                  0x85
-#define K4B2G1646EBIH9_PHY_FIFO_WE             0x100
-#define K4B2G1646EBIH9_PHY_WR_DATA             0xC1
+#define K4B2G1646EBIH9_RATIO                   0x80
+#define K4B2G1646EBIH9_INVERT_CLKOUT           0x0
+#define K4B2G1646EBIH9_RD_DQS                  0x35
+#define K4B2G1646EBIH9_WR_DQS                  0x3A
+#define K4B2G1646EBIH9_PHY_FIFO_WE             0x97
+#define K4B2G1646EBIH9_PHY_WR_DATA             0x76
 #define K4B2G1646EBIH9_IOCTRL_VALUE            0x18B
 
 /**
index c6070a3..87b7d36 100644 (file)
@@ -10,6 +10,7 @@
 
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
+#include <asm/arch/cpu.h>
 
 #define BOARD_REV_ID   0x0
 
@@ -42,4 +43,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 #ifdef CONFIG_NOR_BOOT
 void enable_norboot_pin_mux(void);
 #endif
+void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
 #endif
index a27145b..92c847e 100644 (file)
@@ -169,7 +169,7 @@ struct iim_regs {
        struct fuse_bank {
                u32 fuse_regs[0x20];
                u32 fuse_rsvd[0xe0];
-       } bank[1];
+       } bank[2];
 };
 
 struct fuse_bank0_regs {
@@ -209,9 +209,13 @@ struct fuse_bank0_regs {
 #define IIM_BASE_ADDR          IMX_IIM_BASE
 #define IMX_FEC_BASE           (0x2b000 + IMX_IO_BASE)
 
+#define IMX_NFC_BASE           (0xD8000000)
 #define IMX_ESD_BASE           (0xD8001000)
 #define IMX_WEIM_BASE          (0xD8002000)
 
+#define NFC_BASE_ADDR          IMX_NFC_BASE
+
+
 /* FMCR System Control bit definition*/
 #define UART4_RXD_CTL  (1 << 25)
 #define UART4_RTS_CTL  (1 << 24)
index c493687..93f29a7 100644 (file)
@@ -50,4 +50,5 @@ void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_ipu_clock(void);
+int enable_fec_anatop_clock(void);
 #endif /* __ASM_ARCH_CLOCK_H */
index 74aefe6..2813593 100644 (file)
@@ -892,7 +892,7 @@ struct mxc_ccm_reg {
 
 #define PLL2_PFD0_FREQ         352000000
 #define PLL2_PFD1_FREQ         594000000
-#define PLL2_PFD2_FREQ         400000000
+#define PLL2_PFD2_FREQ         396000000
 #define PLL2_PFD2_DIV_FREQ     200000000
 #define PLL3_PFD0_FREQ         720000000
 #define PLL3_PFD1_FREQ         540000000
index f4cfd4f..ff13a1e 100644 (file)
 #define IOMUXC_GPR13_SATA_PHY_2_MASK   (0x1f<<2)
 #define IOMUXC_GPR13_SATA_PHY_1_MASK   (3<<0)
 
+#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC_MASK    (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
+                               | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
+
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB     (0<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB     (1<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB     (2<<24)
index c3d0b70..b5df68a 100644 (file)
@@ -235,7 +235,7 @@ enum {
        MX6_PAD_DISP0_DAT1__GPIO_4_22           = IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6   = IOMUX_PAD(0x03C8, 0x00B4, 6, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12       = IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
-       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10  = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10  = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6_PAD_DISP0_DAT10__LCDIF_DAT_10       = IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6       = IOMUX_PAD(0x03CC, 0x00B8, 3, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),
@@ -309,7 +309,7 @@ enum {
        MX6_PAD_DISP0_DAT19__GPIO_5_13          = IOMUX_PAD(0x03F0, 0x00DC, 5, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT19__MMDC_MMDC_DEBUG_24 = IOMUX_PAD(0x03F0, 0x00DC, 6, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT19__WEIM_WEIM_CS_3     = IOMUX_PAD(0x03F0, 0x00DC, 7, 0x0000, 0, 0),
-       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2    = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, 0),
+       MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2    = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
        MX6_PAD_DISP0_DAT2__LCDIF_DAT_2         = IOMUX_PAD(0x03F4, 0x00E0, 1, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT2__ECSPI3_MISO         = IOMUX_PAD(0x03F4, 0x00E0, 2, 0x0000, 0, 0),
        MX6_PAD_DISP0_DAT2__USDHC1_USDHC_DEBUG_2        = IOMUX_PAD(0x03F4, 0x00E0, 3, 0x0000, 0, 0),
@@ -1043,7 +1043,7 @@ enum {
        MX6_PAD_GPIO_1__ESAI1_SCKR              = IOMUX_PAD(0x05E0, 0x0210, 0, 0x083C, 1, 0),
        MX6_PAD_GPIO_1__WDOG2_WDOG_B            = IOMUX_PAD(0x05E0, 0x0210, 1, 0x0000, 0, 0),
        MX6_PAD_GPIO_1__KPP_ROW_5               = IOMUX_PAD(0x05E0, 0x0210, 2, 0x08CC, 1, 0),
-       MX6_PAD_GPIO_1__USBOTG_ID               = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
+       MX6_PAD_GPIO_1__USB_OTG_ID              = IOMUX_PAD(0x05E0, 0x0210, 3, 0x0790, 1, 0),
        MX6_PAD_GPIO_1__PWM2_PWMO               = IOMUX_PAD(0x05E0, 0x0210, 4, 0x0000, 0, 0),
        MX6_PAD_GPIO_1__GPIO_1_1                = IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0),
        MX6_PAD_GPIO_1__USDHC1_CD               = IOMUX_PAD(0x05E0, 0x0210, 6, 0x0000, 0, 0),
index 94df007..fe9a8c3 100644 (file)
@@ -984,6 +984,7 @@ enum {
        MX6_PAD_GPIO_1__ESAI1_SCKR              = IOMUX_PAD(0x05F4, 0x0224, 0, 0x086C, 1, 0),
        MX6_PAD_GPIO_1__WDOG2_WDOG_B            = IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0),
        MX6_PAD_GPIO_1__KPP_ROW_5               = IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0),
+       MX6_PAD_GPIO_1__USB_OTG_ID              = IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, 0),
        MX6_PAD_GPIO_1__PWM2_PWMO               = IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0),
        MX6_PAD_GPIO_1__GPIO_1_1                = IOMUX_PAD(0x05F4, 0x0224, 5, 0x0000, 0, 0),
        MX6_PAD_GPIO_1__USDHC1_CD               = IOMUX_PAD(0x05F4, 0x0224, 6, 0x0000, 0, 0),
index b39a354..5f9c90a 100644 (file)
@@ -18,5 +18,17 @@ enum {
        MX6_PAD_SD2_DAT3__USDHC2_DAT3                           = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
        MX6_PAD_UART1_RXD__UART1_RXD                            = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
        MX6_PAD_UART1_TXD__UART1_TXD                            = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
+
+       MX6_PAD_FEC_MDC__FEC_MDC                                = IOMUX_PAD(0x41c, 0x12c, 0, 0x000, 0, 0),
+       MX6_PAD_FEC_MDIO__FEC_MDIO                              = IOMUX_PAD(0x420, 0x130, 0, 0x6f4, 1, 0),
+       MX6_PAD_FEC_CRS_DV__FEC_RX_DV                           = IOMUX_PAD(0x418, 0x128, 0, 0x704, 1, 0),
+       MX6_PAD_FEC_RXD0__FEC_RX_DATA0                          = IOMUX_PAD(0x42c, 0x13c, 0, 0x6f8, 0, 0),
+       MX6_PAD_FEC_RXD1__FEC_RX_DATA1                          = IOMUX_PAD(0x430, 0x140, 0, 0x6fc, 1, 0),
+       MX6_PAD_FEC_TX_EN__FEC_TX_EN                            = IOMUX_PAD(0x438, 0x148, 0, 0x000, 0, 0),
+       MX6_PAD_FEC_TXD0__FEC_TX_DATA0                          = IOMUX_PAD(0x43c, 0x14c, 0, 0x000, 0, 0),
+       MX6_PAD_FEC_TXD1__FEC_TX_DATA1                          = IOMUX_PAD(0x440, 0x150, 0, 0x000, 0, 0),
+       MX6_PAD_FEC_REF_CLK__FEC_REF_OUT                        = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
+       MX6_PAD_FEC_RX_ER__GPIO_4_19                            = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
+       MX6_PAD_FEC_TX_CLK__GPIO_4_21                           = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
 };
 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
index 1038592..43c7dd6 100644 (file)
@@ -28,8 +28,9 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
 #include <asm/arch/iomux-mx28.h>
 #endif
 
-void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
-                       const unsigned int iomux_size);
+void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
+                        const iomux_cfg_t *iomux_setup,
+                        const unsigned int iomux_size);
 #endif
 
 struct mxs_pair {
index 1182a13..50c4ebd 100644 (file)
@@ -12,5 +12,6 @@
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
+#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
 
 #endif /* _SOCFPGA_BASE_ADDRS_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h
new file mode 100644 (file)
index 0000000..d965d25
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef        _SYSTEM_MANAGER_H_
+#define        _SYSTEM_MANAGER_H_
+
+#ifndef __ASSEMBLY__
+
+void sysmgr_pinmux_init(void);
+
+/* declaration for handoff table type */
+extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
+
+#endif
+
+
+#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
+
+#endif /* _SYSTEM_MANAGER_H_ */
index 392d6a2..395444e 100644 (file)
@@ -7,7 +7,6 @@
  */
 #ifndef ARMV7_H
 #define ARMV7_H
-#include <linux/types.h>
 
 /* Cortex-A9 revisions */
 #define MIDR_CORTEX_A9_R0P1    0x410FC091
 #define MIDR_CORTEX_A15_R0P0   0x410FC0F0
 #define MIDR_CORTEX_A15_R2P2   0x412FC0F2
 
+/* Cortex-A7 revisions */
+#define MIDR_CORTEX_A7_R0P0    0x410FC070
+
+#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
+
+/* ID_PFR1 feature fields */
+#define CPUID_ARM_SEC_SHIFT            4
+#define CPUID_ARM_SEC_MASK             (0xF << CPUID_ARM_SEC_SHIFT)
+#define CPUID_ARM_VIRT_SHIFT           12
+#define CPUID_ARM_VIRT_MASK            (0xF << CPUID_ARM_VIRT_SHIFT)
+#define CPUID_ARM_GENTIMER_SHIFT       16
+#define CPUID_ARM_GENTIMER_MASK                (0xF << CPUID_ARM_GENTIMER_SHIFT)
+
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK                      0xFFFF8000
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET                0
 #define CCSIDR_LINE_SIZE_MASK          0x7
@@ -41,6 +56,9 @@
 #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA     3
 #define ARMV7_CLIDR_CTYPE_UNIFIED              4
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
 /*
  * CP15 Barrier instructions
  * Please note that we have separate barrier instructions in ARMv7
@@ -58,4 +76,17 @@ void v7_outer_cache_inval_all(void);
 void v7_outer_cache_flush_range(u32 start, u32 end);
 void v7_outer_cache_inval_range(u32 start, u32 end);
 
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+
+int armv7_switch_nonsec(void);
+int armv7_switch_hyp(void);
+
+/* defined in assembly file */
+unsigned int _nonsec_init(void);
+void _smp_pen(void);
+void _switch_to_hyp(void);
+#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+
+#endif /* ! __ASSEMBLY__ */
+
 #endif
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
new file mode 100644 (file)
index 0000000..a0891cc
--- /dev/null
@@ -0,0 +1,19 @@
+#ifndef __GIC_V2_H__
+#define __GIC_V2_H__
+
+/* register offsets for the ARM generic interrupt controller (GIC) */
+
+#define GIC_DIST_OFFSET                0x1000
+#define GICD_CTLR              0x0000
+#define GICD_TYPER             0x0004
+#define GICD_IGROUPRn          0x0080
+#define GICD_SGIR              0x0F00
+
+#define GIC_CPU_OFFSET_A9      0x0100
+#define GIC_CPU_OFFSET_A15     0x2000
+#define GICC_CTLR              0x0000
+#define GICC_PMR               0x0004
+#define GICC_IAR               0x000C
+#define GICC_EOIR              0x0010
+
+#endif
index 5e2f027..61fee9f 100644 (file)
@@ -310,12 +310,6 @@ struct prcm_regs {
        u32 prm_vc_val_bypass;
        u32 prm_vc_cfg_i2c_mode;
        u32 prm_vc_cfg_i2c_clk;
-       u32 prm_sldo_core_setup;
-       u32 prm_sldo_core_ctrl;
-       u32 prm_sldo_mpu_setup;
-       u32 prm_sldo_mpu_ctrl;
-       u32 prm_sldo_mm_setup;
-       u32 prm_sldo_mm_ctrl;
        u32 prm_abbldo_mpu_setup;
        u32 prm_abbldo_mpu_ctrl;
 
index eefb456..f476a89 100644 (file)
 #include <asm/bootm.h>
 #include <linux/compiler.h>
 
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#include <asm/armv7.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct tag *params;
@@ -181,6 +185,19 @@ static void setup_end_tag(bd_t *bd)
 
 __weak void setup_board_tags(struct tag **in_params) {}
 
+static void do_nonsec_virt_switch(void)
+{
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+       if (armv7_switch_nonsec() == 0)
+#ifdef CONFIG_ARMV7_VIRT
+               if (armv7_switch_hyp() == 0)
+                       debug("entered HYP mode\n");
+#else
+               debug("entered non-secure state\n");
+#endif
+#endif
+}
+
 /* Subcommand: PREP */
 static void boot_prep_linux(bootm_headers_t *images)
 {
@@ -217,6 +234,7 @@ static void boot_prep_linux(bootm_headers_t *images)
                printf("FDT and ATAGS support not compiled in - hanging\n");
                hang();
        }
+       do_nonsec_virt_switch();
 }
 
 /* Subcommand: GO */
index 101fc7c..9dc45a9 100644 (file)
@@ -10,8 +10,10 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
-COBJS  := socfpga_cyclone5.o
+COBJS-y        := socfpga_cyclone5.o
+COBJS-$(CONFIG_SPL_BUILD) += pinmux_config.o
 
+COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS))
 
diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c
new file mode 100644 (file)
index 0000000..8b09005
--- /dev/null
@@ -0,0 +1,214 @@
+/* This file is generated by Preloader Generator */
+
+#include "pinmux_config.h"
+
+/* pin mux configuration data */
+unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
+       0, /* EMACIO0 - Unused */
+       2, /* EMACIO1 - USB */
+       2, /* EMACIO2 - USB */
+       2, /* EMACIO3 - USB */
+       2, /* EMACIO4 - USB */
+       2, /* EMACIO5 - USB */
+       2, /* EMACIO6 - USB */
+       2, /* EMACIO7 - USB */
+       2, /* EMACIO8 - USB */
+       0, /* EMACIO9 - Unused */
+       2, /* EMACIO10 - USB */
+       2, /* EMACIO11 - USB */
+       2, /* EMACIO12 - USB */
+       2, /* EMACIO13 - USB */
+       0, /* EMACIO14 - N/A */
+       0, /* EMACIO15 - N/A */
+       0, /* EMACIO16 - N/A */
+       0, /* EMACIO17 - N/A */
+       0, /* EMACIO18 - N/A */
+       0, /* EMACIO19 - N/A */
+       3, /* FLASHIO0 - SDMMC */
+       3, /* FLASHIO1 - SDMMC */
+       3, /* FLASHIO2 - SDMMC */
+       3, /* FLASHIO3 - SDMMC */
+       0, /* FLASHIO4 - SDMMC */
+       0, /* FLASHIO5 - SDMMC */
+       0, /* FLASHIO6 - SDMMC */
+       0, /* FLASHIO7 - SDMMC */
+       0, /* FLASHIO8 - SDMMC */
+       3, /* FLASHIO9 - SDMMC */
+       3, /* FLASHIO10 - SDMMC */
+       3, /* FLASHIO11 - SDMMC */
+       3, /* GENERALIO0 - TRACE */
+       3, /* GENERALIO1 - TRACE */
+       3, /* GENERALIO2 - TRACE */
+       3, /* GENERALIO3 - TRACE  */
+       3, /* GENERALIO4 - TRACE  */
+       3, /* GENERALIO5 - TRACE  */
+       3, /* GENERALIO6 - TRACE  */
+       3, /* GENERALIO7 - TRACE  */
+       3, /* GENERALIO8 - TRACE  */
+       3, /* GENERALIO9 - SPIM0 */
+       3, /* GENERALIO10 - SPIM0 */
+       3, /* GENERALIO11 - SPIM0 */
+       3, /* GENERALIO12 - SPIM0 */
+       2, /* GENERALIO13 - CAN0 */
+       2, /* GENERALIO14 - CAN0 */
+       3, /* GENERALIO15 - I2C0 */
+       3, /* GENERALIO16 - I2C0 */
+       2, /* GENERALIO17 - UART0 */
+       2, /* GENERALIO18 - UART0 */
+       0, /* GENERALIO19 - N/A */
+       0, /* GENERALIO20 - N/A */
+       0, /* GENERALIO21 - N/A */
+       0, /* GENERALIO22 - N/A */
+       0, /* GENERALIO23 - N/A */
+       0, /* GENERALIO24 - N/A */
+       0, /* GENERALIO25 - N/A */
+       0, /* GENERALIO26 - N/A */
+       0, /* GENERALIO27 - N/A */
+       0, /* GENERALIO28 - N/A */
+       0, /* GENERALIO29 - N/A */
+       0, /* GENERALIO30 - N/A */
+       0, /* GENERALIO31 - N/A */
+       2, /* MIXED1IO0 - EMAC */
+       2, /* MIXED1IO1 - EMAC */
+       2, /* MIXED1IO2 - EMAC */
+       2, /* MIXED1IO3 - EMAC */
+       2, /* MIXED1IO4 - EMAC */
+       2, /* MIXED1IO5 - EMAC */
+       2, /* MIXED1IO6 - EMAC */
+       2, /* MIXED1IO7 - EMAC */
+       2, /* MIXED1IO8 - EMAC */
+       2, /* MIXED1IO9 - EMAC */
+       2, /* MIXED1IO10 - EMAC */
+       2, /* MIXED1IO11 - EMAC */
+       2, /* MIXED1IO12 - EMAC */
+       2, /* MIXED1IO13 - EMAC */
+       0, /* MIXED1IO14 - Unused */
+       3, /* MIXED1IO15 - QSPI */
+       3, /* MIXED1IO16 - QSPI */
+       3, /* MIXED1IO17 - QSPI */
+       3, /* MIXED1IO18 - QSPI */
+       3, /* MIXED1IO19 - QSPI */
+       3, /* MIXED1IO20 - QSPI */
+       0, /* MIXED1IO21 - GPIO */
+       0, /* MIXED2IO0 - N/A */
+       0, /* MIXED2IO1 - N/A */
+       0, /* MIXED2IO2 - N/A */
+       0, /* MIXED2IO3 - N/A */
+       0, /* MIXED2IO4 - N/A */
+       0, /* MIXED2IO5 - N/A */
+       0, /* MIXED2IO6 - N/A */
+       0, /* MIXED2IO7 - N/A */
+       0, /* GPLINMUX48 */
+       0, /* GPLINMUX49 */
+       0, /* GPLINMUX50 */
+       0, /* GPLINMUX51 */
+       0, /* GPLINMUX52 */
+       0, /* GPLINMUX53 */
+       0, /* GPLINMUX54 */
+       0, /* GPLINMUX55 */
+       0, /* GPLINMUX56 */
+       0, /* GPLINMUX57 */
+       0, /* GPLINMUX58 */
+       0, /* GPLINMUX59 */
+       0, /* GPLINMUX60 */
+       0, /* GPLINMUX61 */
+       0, /* GPLINMUX62 */
+       0, /* GPLINMUX63 */
+       0, /* GPLINMUX64 */
+       0, /* GPLINMUX65 */
+       0, /* GPLINMUX66 */
+       0, /* GPLINMUX67 */
+       0, /* GPLINMUX68 */
+       0, /* GPLINMUX69 */
+       0, /* GPLINMUX70 */
+       1, /* GPLMUX0 */
+       1, /* GPLMUX1 */
+       1, /* GPLMUX2 */
+       1, /* GPLMUX3 */
+       1, /* GPLMUX4 */
+       1, /* GPLMUX5 */
+       1, /* GPLMUX6 */
+       1, /* GPLMUX7 */
+       1, /* GPLMUX8 */
+       1, /* GPLMUX9 */
+       1, /* GPLMUX10 */
+       1, /* GPLMUX11 */
+       1, /* GPLMUX12 */
+       1, /* GPLMUX13 */
+       1, /* GPLMUX14 */
+       1, /* GPLMUX15 */
+       1, /* GPLMUX16 */
+       1, /* GPLMUX17 */
+       1, /* GPLMUX18 */
+       1, /* GPLMUX19 */
+       1, /* GPLMUX20 */
+       1, /* GPLMUX21 */
+       1, /* GPLMUX22 */
+       1, /* GPLMUX23 */
+       1, /* GPLMUX24 */
+       1, /* GPLMUX25 */
+       1, /* GPLMUX26 */
+       1, /* GPLMUX27 */
+       1, /* GPLMUX28 */
+       1, /* GPLMUX29 */
+       1, /* GPLMUX30 */
+       1, /* GPLMUX31 */
+       1, /* GPLMUX32 */
+       1, /* GPLMUX33 */
+       1, /* GPLMUX34 */
+       1, /* GPLMUX35 */
+       1, /* GPLMUX36 */
+       1, /* GPLMUX37 */
+       1, /* GPLMUX38 */
+       1, /* GPLMUX39 */
+       1, /* GPLMUX40 */
+       1, /* GPLMUX41 */
+       1, /* GPLMUX42 */
+       1, /* GPLMUX43 */
+       1, /* GPLMUX44 */
+       1, /* GPLMUX45 */
+       1, /* GPLMUX46 */
+       1, /* GPLMUX47 */
+       1, /* GPLMUX48 */
+       1, /* GPLMUX49 */
+       1, /* GPLMUX50 */
+       1, /* GPLMUX51 */
+       1, /* GPLMUX52 */
+       1, /* GPLMUX53 */
+       1, /* GPLMUX54 */
+       1, /* GPLMUX55 */
+       1, /* GPLMUX56 */
+       1, /* GPLMUX57 */
+       1, /* GPLMUX58 */
+       1, /* GPLMUX59 */
+       1, /* GPLMUX60 */
+       1, /* GPLMUX61 */
+       1, /* GPLMUX62 */
+       1, /* GPLMUX63 */
+       1, /* GPLMUX64 */
+       1, /* GPLMUX65 */
+       1, /* GPLMUX66 */
+       1, /* GPLMUX67 */
+       1, /* GPLMUX68 */
+       1, /* GPLMUX69 */
+       1, /* GPLMUX70 */
+       0, /* NANDUSEFPGA */
+       0, /* UART0USEFPGA */
+       0, /* RGMII1USEFPGA */
+       0, /* SPIS0USEFPGA */
+       0, /* CAN0USEFPGA */
+       0, /* I2C0USEFPGA */
+       0, /* SDMMCUSEFPGA */
+       0, /* QSPIUSEFPGA */
+       0, /* SPIS1USEFPGA */
+       0, /* RGMII0USEFPGA */
+       0, /* UART1USEFPGA */
+       0, /* CAN1USEFPGA */
+       0, /* USB1USEFPGA */
+       0, /* I2C3USEFPGA */
+       0, /* I2C2USEFPGA */
+       0, /* I2C1USEFPGA */
+       0, /* SPIM1USEFPGA */
+       0, /* USB0USEFPGA */
+       0 /* SPIM0USEFPGA */
+};
diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h
new file mode 100644 (file)
index 0000000..f278f2b
--- /dev/null
@@ -0,0 +1,54 @@
+/* This file is generated by Preloader Generator */
+
+#ifndef _PRELOADER_PINMUX_CONFIG_H_
+#define _PRELOADER_PINMUX_CONFIG_H_
+
+/*
+ * State of enabling for which IP connected out through the muxing.
+ * Value 1 mean the IP connection is muxed out
+ */
+#define CONFIG_HPS_EMAC0               (0)
+#define CONFIG_HPS_EMAC1               (1)
+#define CONFIG_HPS_USB0                        (0)
+#define CONFIG_HPS_USB1                        (1)
+#define CONFIG_HPS_NAND                        (0)
+#define CONFIG_HPS_SDMMC               (1)
+#define CONFIG_HPS_QSPI                        (1)
+#define CONFIG_HPS_UART0               (1)
+#define CONFIG_HPS_UART1               (0)
+#define CONFIG_HPS_TRACE               (1)
+#define CONFIG_HPS_I2C0                        (1)
+#define CONFIG_HPS_I2C1                        (0)
+#define CONFIG_HPS_I2C2                        (0)
+#define CONFIG_HPS_I2C3                        (0)
+#define CONFIG_HPS_SPIM0               (1)
+#define CONFIG_HPS_SPIM1               (0)
+#define CONFIG_HPS_SPIS0               (0)
+#define CONFIG_HPS_SPIS1               (0)
+#define CONFIG_HPS_CAN0                        (1)
+#define CONFIG_HPS_CAN1                        (0)
+
+/* IP attribute value (which affected by pin muxing configuration) */
+#define CONFIG_HPS_SDMMC_BUSWIDTH      (4)
+
+/* 1 if the pins are connected out */
+#define CONFIG_HPS_QSPI_CS0            (1)
+#define CONFIG_HPS_QSPI_CS1            (0)
+#define CONFIG_HPS_QSPI_CS2            (0)
+#define CONFIG_HPS_QSPI_CS3            (0)
+
+/* UART */
+/* 1 means the pin is mux out or available */
+#define CONFIG_HPS_UART0_TX            (1)
+#define CONFIG_HPS_UART0_RX            (1)
+#define CONFIG_HPS_UART0_CTS           (0)
+#define CONFIG_HPS_UART0_RTS           (0)
+#define CONFIG_HPS_UART1_TX            (0)
+#define CONFIG_HPS_UART1_RX            (0)
+#define CONFIG_HPS_UART1_CTS           (0)
+#define CONFIG_HPS_UART1_RTS           (0)
+
+/* Pin mux data */
+#define CONFIG_HPS_PINMUX_NUM          (207)
+
+#endif /* _PRELOADER_PINMUX_CONFIG_H_ */
similarity index 68%
rename from board/ti/omap1510inn/Makefile
rename to board/armadeus/apf27/Makefile
index ad5a7eb..5fcda6e 100644 (file)
@@ -1,18 +1,23 @@
 #
-# (C) Copyright 2000-2006
+# (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2012-2013
+# Eric Jarrige <eric.jarrige@armadeus.org>
 #
-# SPDX-License-Identifier:     GPL-2.0+
+# SPDX-License-Identifier:    GPL-2.0+
 #
 
 include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).o
 
-COBJS  := omap1510innovator.o
+COBJS  := apf27.o
 SOBJS  := lowlevel_init.o
+ifdef CONFIG_FPGA
+COBJS  += fpga.o
+endif
 
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS   := $(COBJS:.o=.c) $(SOBJS:.o=.S)
 OBJS   := $(addprefix $(obj),$(COBJS))
 SOBJS  := $(addprefix $(obj),$(SOBJS))
 
@@ -21,7 +26,6 @@ $(LIB):       $(obj).depend $(OBJS) $(SOBJS)
 
 #########################################################################
 
-# defines $(obj).depend target
 include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
new file mode 100644 (file)
index 0000000..30e720d
--- /dev/null
@@ -0,0 +1,256 @@
+/*
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * based on the files by
+ * Sascha Hauer, Pengutronix
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <jffs2/jffs2.h>
+#include <nand.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/errno.h>
+#include "apf27.h"
+#include "crc.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
+ * customer use. The APF27 board uses this fuse to store the board revision:
+ * 0: initial board revision
+ * 1: first revision - Presence of the second RAM chip on the board is blown in
+ *     fuse bank 1 row 9  bit 0 - No hardware change
+ * N: to be defined
+ */
+static u32 get_board_rev(void)
+{
+       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+
+       return readl(&iim->bank[1].fuse_regs[8]);
+}
+
+/*
+ * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
+ * customer use. The APF27 board revision 1 uses the bit 0 to permanently store
+ * the presence of the second RAM chip
+ * 0: AFP27 with 1 RAM of 64 MiB
+ * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
+ */
+static int get_num_ram_bank(void)
+{
+       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+       int nr_dram_banks = 1;
+
+       if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
+               nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
+       else
+               nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
+
+       return nr_dram_banks;
+}
+
+static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
+                           u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
+                           u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
+                           u32 puen, u32 gius)
+{
+       struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
+
+       writel(gpio_dr,   &regs->port[port].gpio_dr);
+       writel(ocr1,      &regs->port[port].ocr1);
+       writel(ocr2,      &regs->port[port].ocr2);
+       writel(iconfa1,   &regs->port[port].iconfa1);
+       writel(iconfa2,   &regs->port[port].iconfa2);
+       writel(iconfb1,   &regs->port[port].iconfb1);
+       writel(iconfb2,   &regs->port[port].iconfb2);
+       writel(icr1,      &regs->port[port].icr1);
+       writel(icr2,      &regs->port[port].icr2);
+       writel(imr,       &regs->port[port].imr);
+       writel(gpio_dir,  &regs->port[port].gpio_dir);
+       writel(gpr,       &regs->port[port].gpr);
+       writel(puen,      &regs->port[port].puen);
+       writel(gius,      &regs->port[port].gius);
+}
+
+#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL,   \
+       ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL,   \
+       ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
+       ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL,     \
+       ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL,     \
+       ACFG_GIUS_##n##_VAL)
+
+static void apf27_iomux_init(void)
+{
+       APF27_PORT_INIT(A);
+       APF27_PORT_INIT(B);
+       APF27_PORT_INIT(C);
+       APF27_PORT_INIT(D);
+       APF27_PORT_INIT(E);
+       APF27_PORT_INIT(F);
+}
+
+static int apf27_devices_init(void)
+{
+       int i;
+       unsigned int mode[] = {
+               PC5_PF_I2C2_DATA,
+               PC6_PF_I2C2_CLK,
+               PD17_PF_I2C_DATA,
+               PD18_PF_I2C_CLK,
+       };
+
+       for (i = 0; i < ARRAY_SIZE(mode); i++)
+               imx_gpio_mode(mode[i]);
+
+#ifdef CONFIG_MXC_UART
+       mx27_uart1_init_pins();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+       mx27_fec_init_pins();
+#endif
+
+#ifdef CONFIG_MXC_MMC
+       mx27_sd2_init_pins();
+       imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
+       gpio_request(PC_PWRON, "pc_pwron");
+       gpio_set_value(PC_PWRON, 1);
+#endif
+       return 0;
+}
+
+static void apf27_setup_csx(void)
+{
+       struct weim_regs *weim = (struct weim_regs *)IMX_WEIM_BASE;
+
+       writel(ACFG_CS0U_VAL, &weim->cs0u);
+       writel(ACFG_CS0L_VAL, &weim->cs0l);
+       writel(ACFG_CS0A_VAL, &weim->cs0a);
+
+       writel(ACFG_CS1U_VAL, &weim->cs1u);
+       writel(ACFG_CS1L_VAL, &weim->cs1l);
+       writel(ACFG_CS1A_VAL, &weim->cs1a);
+
+       writel(ACFG_CS2U_VAL, &weim->cs2u);
+       writel(ACFG_CS2L_VAL, &weim->cs2l);
+       writel(ACFG_CS2A_VAL, &weim->cs2a);
+
+       writel(ACFG_CS3U_VAL, &weim->cs3u);
+       writel(ACFG_CS3L_VAL, &weim->cs3l);
+       writel(ACFG_CS3A_VAL, &weim->cs3a);
+
+       writel(ACFG_CS4U_VAL, &weim->cs4u);
+       writel(ACFG_CS4L_VAL, &weim->cs4l);
+       writel(ACFG_CS4A_VAL, &weim->cs4a);
+
+       writel(ACFG_CS5U_VAL, &weim->cs5u);
+       writel(ACFG_CS5L_VAL, &weim->cs5l);
+       writel(ACFG_CS5A_VAL, &weim->cs5a);
+
+       writel(ACFG_EIM_VAL, &weim->eim);
+}
+
+static void apf27_setup_port(void)
+{
+       struct system_control_regs *system =
+               (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+
+       writel(ACFG_FMCR_VAL, &system->fmcr);
+}
+
+int board_init(void)
+{
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       apf27_setup_csx();
+       apf27_setup_port();
+       apf27_iomux_init();
+       apf27_devices_init();
+#if defined(CONFIG_FPGA)
+       APF27_init_fpga();
+#endif
+
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+       if (get_num_ram_bank() > 1)
+               gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
+                                            PHYS_SDRAM_2_SIZE);
+
+       return 0;
+}
+
+void dram_init_banksize(void)
+{
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size  = get_ram_size((void *)PHYS_SDRAM_1,
+                                               PHYS_SDRAM_1_SIZE);
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+       if (get_num_ram_bank() > 1)
+               gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
+                                            PHYS_SDRAM_2_SIZE);
+       else
+               gd->bd->bi_dram[1].size = 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+       ulong ramtop;
+
+       if (get_num_ram_bank() > 1)
+               ramtop = PHYS_SDRAM_2 + get_ram_size((void *)PHYS_SDRAM_2,
+                                                    PHYS_SDRAM_2_SIZE);
+       else
+               ramtop = PHYS_SDRAM_1 + get_ram_size((void *)PHYS_SDRAM_1,
+                                                    PHYS_SDRAM_1_SIZE);
+
+       return ramtop;
+}
+
+int checkboard(void)
+{
+       printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
+       return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+inline void hang(void)
+{
+       for (;;)
+               ;
+}
+
+void board_init_f(ulong bootflag)
+{
+       /*
+        * copy ourselves from where we are running to where we were
+        * linked at. Use ulong pointers as all addresses involved
+        * are 4-byte-aligned.
+        */
+       ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
+       asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
+       asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
+       asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
+       asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
+       for (dst = start_ptr; dst < end_ptr; dst++)
+               *dst = *(dst+(run_ptr-link_ptr));
+
+       /*
+        * branch to nand_boot's link-time address.
+        */
+       asm volatile("ldr pc, =nand_boot");
+}
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h
new file mode 100644 (file)
index 0000000..64e7e4d
--- /dev/null
@@ -0,0 +1,489 @@
+/*
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __APF27_H
+#define __APF27_H
+
+/* FPGA program pin configuration */
+#define ACFG_FPGA_PWR  (GPIO_PORTF | 19)       /* FPGA prog pin  */
+#define ACFG_FPGA_PRG  (GPIO_PORTF | 11)       /* FPGA prog pin  */
+#define ACFG_FPGA_CLK  (GPIO_PORTF | 15)       /* FPGA clk pin   */
+#define ACFG_FPGA_RDATA        0xD6000000              /* FPGA data addr */
+#define ACFG_FPGA_WDATA        0xD6000000              /* FPGA data addr */
+#define ACFG_FPGA_INIT (GPIO_PORTF | 12)       /* FPGA init pin  */
+#define ACFG_FPGA_DONE (GPIO_PORTF | 9)        /* FPGA done pin  */
+#define ACFG_FPGA_RW   (GPIO_PORTF | 21)       /* FPGA done pin  */
+#define ACFG_FPGA_CS   (GPIO_PORTF | 22)       /* FPGA done pin  */
+#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10)    /* FPGA done pin  */
+#define ACFG_FPGA_RESET        (GPIO_PORTF | 7)        /* FPGA done pin  */
+
+/* MMC pin */
+#define PC_PWRON       (GPIO_PORTF | 16)
+
+/*
+ * MPU CLOCK source before PLL
+ * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
+ */
+#define ACFG_MPCTL0_VAL                0x01EF15D5      /* 399.000 MHz */
+#define ACFG_MPCTL1_VAL                0
+#define CONFIG_MPLL_FREQ       399
+
+#define ACFG_CLK_FREQ  (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
+
+/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
+#define ACFG_SPCTL0_VAL                0x0475206F      /* 299.99937 MHz */
+#define ACFG_SPCTL1_VAL                0
+#define CONFIG_SPLL_FREQ       300             /* MHz */
+
+/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
+#define CONFIG_ARM_FREQ                399     /* up to 400 MHz */
+
+/* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */
+#define CONFIG_HCLK_FREQ       133     /* (ACFG_CLK_FREQ/2) */
+
+#define CONFIG_PERIF1_FREQ     16      /* 16.625 MHz UART, GPT, PWM */
+#define CONFIG_PERIF2_FREQ     33      /* 33.25 MHz CSPI and SDHC */
+#define CONFIG_PERIF3_FREQ     33      /* 33.25 MHz LCD */
+#define CONFIG_PERIF4_FREQ     33      /* 33.25 MHz CSI */
+#define CONFIG_SSI1_FREQ       66      /* 66.50 MHz SSI1 */
+#define CONFIG_SSI2_FREQ       66      /* 66.50 MHz SSI2 */
+#define CONFIG_MSHC_FREQ       66      /* 66.50 MHz MSHC */
+#define CONFIG_H264_FREQ       66      /* 66.50 MHz H264 */
+#define CONFIG_CLK0_DIV                3       /* Divide CLK0 by 4 */
+#define CONFIG_CLK0_EN         1       /* CLK0 enabled */
+
+/* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */
+#define CONFIG_NFC_FREQ                44      /* NFC Clock up to 44 MHz wh 133MHz */
+
+/* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */
+#define CONFIG_USB_FREQ                60      /* 60 MHz */
+
+/*
+ * SDRAM
+ */
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define ACFG_SDRAM_NUM_COL             9  /* 8, 9, 10 or 11
+                                           * column address bits
+                                           */
+#define ACFG_SDRAM_NUM_ROW             13 /* 11, 12 or 13
+                                           * row address bits
+                                           */
+#define ACFG_SDRAM_REFRESH             3  /* 0=OFF 1=2048
+                                           * 2=4096 3=8192 refresh
+                                           */
+#define ACFG_SDRAM_EXIT_PWD            25 /* ns exit power
+                                           * down delay
+                                           */
+#define ACFG_SDRAM_W2R_DELAY           1  /* write to read
+                                           * cycle delay > 0
+                                           */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY          2  /* Load mode register
+                                           * cycle delay 1..4
+                                           */
+#define ACFG_SDRAM_TWR_DELAY           1  /* LPDDR: 0=2ck 1=3ck
+                                           * SDRAM: 0=1ck 1=2ck
+                                           */
+#define ACFG_SDRAM_RAS_DELAY           42 /* ns ACTIVE-to-PRECHARGE delay */
+#define ACFG_SDRAM_RRD_DELAY           12 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY           18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY            70 /* ns Row cycle delay (tRFC
+                                           * refresh to command)
+                                           */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1    0 /* ns clock cycle time
+                                          * estimated fo CL=1
+                                          * 0=force 3 for lpddr
+                                          */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR    0  /* 0=full 1=half 2=quater
+                                           * 3=Eighth 4=Sixteenth
+                                           */
+#define ACFG_SDRAM_DRIVE_STRENGH       0  /* 0=Full-strength 1=half
+                                           * 2=quater 3=Eighth
+                                           */
+#define ACFG_SDRAM_BURST_LENGTH                3  /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS       0  /* 1= single access
+                                           * 0 = Burst mode
+                                           */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
+/* micron 128MB */
+#define ACFG_SDRAM_NUM_COL             9  /* 8, 9, 10 or 11
+                                           * column address bits
+                                           */
+#define ACFG_SDRAM_NUM_ROW             14 /* 11, 12 or 13
+                                           * row address bits
+                                           */
+#define ACFG_SDRAM_REFRESH             3  /* 0=OFF 1=2048
+                                           * 2=4096 3=8192 refresh
+                                           */
+#define ACFG_SDRAM_EXIT_PWD            25 /* ns exit power
+                                           * down delay
+                                           */
+#define ACFG_SDRAM_W2R_DELAY           1  /* write to read
+                                           * cycle delay > 0
+                                           */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY          2  /* Load mode register
+                                           * cycle delay 1..4
+                                           */
+#define ACFG_SDRAM_TWR_DELAY           1  /* LPDDR: 0=2ck 1=3ck
+                                           * SDRAM: 0=1ck 1=2ck
+                                           */
+#define ACFG_SDRAM_RAS_DELAY           42 /* ns ACTIVE-to-PRECHARGE delay */
+#define ACFG_SDRAM_RRD_DELAY           12 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY           18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY            70 /* ns Row cycle delay (tRFC
+                                           * refresh to command)
+                                           */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1    0 /* ns clock cycle time
+                                          * estimated fo CL=1
+                                          * 0=force 3 for lpddr
+                                          */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR    0  /* 0=full 1=half 2=quater
+                                           * 3=Eighth 4=Sixteenth
+                                           */
+#define ACFG_SDRAM_DRIVE_STRENGH       0  /* 0=Full-strength 1=half
+                                           * 2=quater 3=Eighth
+                                           */
+#define ACFG_SDRAM_BURST_LENGTH                3  /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS       0  /* 1= single access
+                                           * 0 = Burst mode
+                                           */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
+/* micron 256MB */
+#define ACFG_SDRAM_NUM_COL             10  /* 8, 9, 10 or 11
+                                            * column address bits
+                                            */
+#define ACFG_SDRAM_NUM_ROW             14 /* 11, 12 or 13
+                                           * row address bits
+                                           */
+#define ACFG_SDRAM_REFRESH             3  /* 0=OFF 1=2048
+                                           * 2=4096 3=8192 refresh
+                                           */
+#define ACFG_SDRAM_EXIT_PWD            25 /* ns exit power
+                                           * down delay
+                                           */
+#define ACFG_SDRAM_W2R_DELAY           1  /* write to read cycle
+                                           * delay > 0
+                                           */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */
+#define ACFG_SDRAM_TMRD_DELAY          2  /* Load mode register
+                                           * cycle delay 1..4
+                                           */
+#define ACFG_SDRAM_TWR_DELAY           1  /* LPDDR: 0=2ck 1=3ck
+                                           * SDRAM: 0=1ck 1=2ck
+                                           */
+#define ACFG_SDRAM_RAS_DELAY           42 /* ns ACTIVE-to-PRECHARGE delay */
+#define ACFG_SDRAM_RRD_DELAY           12 /* ns ACTIVE-to-ACTIVE delay */
+#define ACFG_SDRAM_RCD_DELAY           18 /* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY            70 /* ns Row cycle delay (tRFC
+                                           * refresh to command)
+                                           */
+#define ACFG_SDRAM_CLOCK_CYCLE_CL_1    0 /* ns clock cycle time
+                                          * estimated fo CL=1
+                                          * 0=force 3 for lpddr
+                                          */
+#define ACFG_SDRAM_PARTIAL_ARRAY_SR    0  /* 0=full 1=half 2=quater
+                                           * 3=Eighth 4=Sixteenth
+                                           */
+#define ACFG_SDRAM_DRIVE_STRENGH       0  /* 0=Full-strength
+                                           * 1=half
+                                           * 2=quater
+                                           * 3=Eighth
+                                           */
+#define ACFG_SDRAM_BURST_LENGTH                3  /* 2^N BYTES (N=0..3) */
+#define ACFG_SDRAM_SINGLE_ACCESS       0  /* 1= single access
+                                           * 0 = Burst mode
+                                           */
+#endif
+
+/*
+ * External interface
+ */
+/*
+ * CSCRxU_VAL:
+ * 31| x | x | x x |x x x x| x x | x | x  |x x x x|16
+ *   |SP |WP | BCD |  BCS  | PSZ |PME|SYNC|  DOL  |
+ *
+ * 15| x x  | x x x x x x | x | x x x x | x x x x |0
+ *   | CNC  |     WSC     |EW |   WWS   |   EDC   |
+ *
+ * CSCRxL_VAL:
+ * 31|  x x x x  | x x x x  | x x x x  | x x x x  |16
+ *   |    OEA    |   OEN    |   EBWA   |   EBWN   |
+ * 15|x x x x| x |x x x |x x x x| x | x | x  | x  | 0
+ *   |  CSA  |EBC| DSZ  |  CSN  |PSR|CRE|WRAP|CSEN|
+ *
+ * CSCRxA_VAL:
+ * 31|  x x x x  | x x x x  | x x x x  | x x x x  |16
+ *   |   EBRA    |   EBRN   |   RWA    |   RWN    |
+ * 15| x | x x |x x x|x x|x x|x x| x | x | x  | x | 0
+ *   |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE|
+ */
+
+/* CS0 configuration for 16 bit nor flash */
+#define ACFG_CS0U_VAL  0x0000CC03
+#define ACFG_CS0L_VAL  0xa0330D01
+#define ACFG_CS0A_VAL  0x00220800
+
+#define ACFG_CS1U_VAL  0x00000f00
+#define ACFG_CS1L_VAL  0x00000D01
+#define ACFG_CS1A_VAL  0
+
+#define ACFG_CS2U_VAL  0
+#define ACFG_CS2L_VAL  0
+#define ACFG_CS2A_VAL  0
+
+#define ACFG_CS3U_VAL  0
+#define ACFG_CS3L_VAL  0
+#define ACFG_CS3A_VAL  0
+
+#define ACFG_CS4U_VAL  0
+#define ACFG_CS4L_VAL  0
+#define ACFG_CS4A_VAL  0
+
+/* FPGA 16 bit data bus */
+#define ACFG_CS5U_VAL  0x00000600
+#define ACFG_CS5L_VAL  0x00000D01
+#define ACFG_CS5A_VAL  0
+
+#define ACFG_EIM_VAL   0x00002200
+
+
+/*
+ * FPGA specific settings
+ */
+
+/* CLKO */
+#define ACFG_CCSR_VAL 0x00000305
+/* drive strength CLKO set to 2 */
+#define ACFG_DSCR10_VAL 0x00020000
+/* drive strength A1..A12 set to 2 */
+#define ACFG_DSCR3_VAL 0x02AAAAA8
+/* drive strength ctrl */
+#define ACFG_DSCR7_VAL 0x00020880
+/* drive strength data */
+#define ACFG_DSCR2_VAL 0xAAAAAAAA
+
+
+/*
+ * Default configuration for GPIOs and peripherals
+ */
+#define ACFG_DDIR_A_VAL                0x00000000
+#define ACFG_OCR1_A_VAL                0x00000000
+#define ACFG_OCR2_A_VAL                0x00000000
+#define ACFG_ICFA1_A_VAL       0xFFFFFFFF
+#define ACFG_ICFA2_A_VAL       0xFFFFFFFF
+#define ACFG_ICFB1_A_VAL       0xFFFFFFFF
+#define ACFG_ICFB2_A_VAL       0xFFFFFFFF
+#define ACFG_DR_A_VAL          0x00000000
+#define ACFG_GIUS_A_VAL                0xFFFFFFFF
+#define ACFG_ICR1_A_VAL                0x00000000
+#define ACFG_ICR2_A_VAL                0x00000000
+#define ACFG_IMR_A_VAL         0x00000000
+#define ACFG_GPR_A_VAL         0x00000000
+#define ACFG_PUEN_A_VAL                0xFFFFFFFF
+
+#define ACFG_DDIR_B_VAL                0x00000000
+#define ACFG_OCR1_B_VAL                0x00000000
+#define ACFG_OCR2_B_VAL                0x00000000
+#define ACFG_ICFA1_B_VAL       0xFFFFFFFF
+#define ACFG_ICFA2_B_VAL       0xFFFFFFFF
+#define ACFG_ICFB1_B_VAL       0xFFFFFFFF
+#define ACFG_ICFB2_B_VAL       0xFFFFFFFF
+#define ACFG_DR_B_VAL          0x00000000
+#define ACFG_GIUS_B_VAL                0xFF3FFFF0
+#define ACFG_ICR1_B_VAL                0x00000000
+#define ACFG_ICR2_B_VAL                0x00000000
+#define ACFG_IMR_B_VAL         0x00000000
+#define ACFG_GPR_B_VAL         0x00000000
+#define ACFG_PUEN_B_VAL                0xFFFFFFFF
+
+#define ACFG_DDIR_C_VAL                0x00000000
+#define ACFG_OCR1_C_VAL                0x00000000
+#define ACFG_OCR2_C_VAL                0x00000000
+#define ACFG_ICFA1_C_VAL       0xFFFFFFFF
+#define ACFG_ICFA2_C_VAL       0xFFFFFFFF
+#define ACFG_ICFB1_C_VAL       0xFFFFFFFF
+#define ACFG_ICFB2_C_VAL       0xFFFFFFFF
+#define ACFG_DR_C_VAL          0x00000000
+#define ACFG_GIUS_C_VAL                0xFFFFC07F
+#define ACFG_ICR1_C_VAL                0x00000000
+#define ACFG_ICR2_C_VAL                0x00000000
+#define ACFG_IMR_C_VAL         0x00000000
+#define ACFG_GPR_C_VAL         0x00000000
+#define ACFG_PUEN_C_VAL                0xFFFFFF87
+
+#define ACFG_DDIR_D_VAL                0x00000000
+#define ACFG_OCR1_D_VAL                0x00000000
+#define ACFG_OCR2_D_VAL                0x00000000
+#define ACFG_ICFA1_D_VAL       0xFFFFFFFF
+#define ACFG_ICFA2_D_VAL       0xFFFFFFFF
+#define ACFG_ICFB1_D_VAL       0xFFFFFFFF
+#define ACFG_ICFB2_D_VAL       0xFFFFFFFF
+#define ACFG_DR_D_VAL          0x00000000
+#define ACFG_GIUS_D_VAL                0xFFFFFFFF
+#define ACFG_ICR1_D_VAL                0x00000000
+#define ACFG_ICR2_D_VAL                0x00000000
+#define ACFG_IMR_D_VAL         0x00000000
+#define ACFG_GPR_D_VAL         0x00000000
+#define ACFG_PUEN_D_VAL                0xFFFFFFFF
+
+#define ACFG_DDIR_E_VAL                0x00000000
+#define ACFG_OCR1_E_VAL                0x00000000
+#define ACFG_OCR2_E_VAL                0x00000000
+#define ACFG_ICFA1_E_VAL       0xFFFFFFFF
+#define ACFG_ICFA2_E_VAL       0xFFFFFFFF
+#define ACFG_ICFB1_E_VAL       0xFFFFFFFF
+#define ACFG_ICFB2_E_VAL       0xFFFFFFFF
+#define ACFG_DR_E_VAL          0x00000000
+#define ACFG_GIUS_E_VAL                0xFCFFCCF8
+#define ACFG_ICR1_E_VAL                0x00000000
+#define ACFG_ICR2_E_VAL                0x00000000
+#define ACFG_IMR_E_VAL         0x00000000
+#define ACFG_GPR_E_VAL         0x00000000
+#define ACFG_PUEN_E_VAL                0xFFFFFFFF
+
+#define ACFG_DDIR_F_VAL                0x00000000
+#define ACFG_OCR1_F_VAL                0x00000000
+#define ACFG_OCR2_F_VAL                0x00000000
+#define ACFG_ICFA1_F_VAL       0xFFFFFFFF
+#define ACFG_ICFA2_F_VAL       0xFFFFFFFF
+#define ACFG_ICFB1_F_VAL       0xFFFFFFFF
+#define ACFG_ICFB2_F_VAL       0xFFFFFFFF
+#define ACFG_DR_F_VAL          0x00000000
+#define ACFG_GIUS_F_VAL                0xFF7F8000
+#define ACFG_ICR1_F_VAL                0x00000000
+#define ACFG_ICR2_F_VAL                0x00000000
+#define ACFG_IMR_F_VAL         0x00000000
+#define ACFG_GPR_F_VAL         0x00000000
+#define ACFG_PUEN_F_VAL                0xFFFFFFFF
+
+/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
+#define ACFG_GPCR_VAL          0x0003000F
+
+#define ACFG_ESDMISC_VAL       ESDMISC_LHD+ESDMISC_MDDREN
+
+/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
+#if (CONFIG_NR_DRAM_BANKS == 1)
+#define ACFG_FMCR_VAL 0xFFFFFFF9
+#elif (CONFIG_NR_DRAM_BANKS == 2)
+#define ACFG_FMCR_VAL 0xFFFFFFFB
+#endif
+
+#define ACFG_AIPI1_PSR0_VAL    0x20040304
+#define ACFG_AIPI1_PSR1_VAL    0xDFFBFCFB
+#define ACFG_AIPI2_PSR0_VAL    0x00000000
+#define ACFG_AIPI2_PSR1_VAL    0xFFFFFFFF
+
+/* PCCR enable DMA FEC I2C1 IIM SDHC1 */
+#define ACFG_PCCR0_VAL         0x05070410
+#define ACFG_PCCR1_VAL         0xA14A0608
+
+/*
+ * From here, there should not be any user configuration.
+ * All Equations are automatic
+ */
+
+/* fixme none integer value (7.5ns) => 2*hclock = 15ns */
+#define ACFG_2XHCLK_LGTH       (2000/CONFIG_HCLK_FREQ) /* ns */
+
+/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
+#define CSCR_MASK 0x0300800D
+
+#define ACFG_CSCR_VAL                                          \
+       (CSCR_MASK                                              \
+       |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28)  \
+       |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12)  \
+       |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8))
+
+/* SSIx CLKO NFC H264 MSHC */
+#define ACFG_PCDR0_VAL\
+       (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0)       \
+       |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6)     \
+       |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\
+       |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\
+       |(((CONFIG_CLK0_DIV)&0x07)<<22)\
+       |(((CONFIG_CLK0_EN)&0x01)<<25)\
+       |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26))
+
+/* PERCLKx  */
+#define ACFG_PCDR1_VAL\
+       (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0)     \
+       |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8)     \
+       |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16)    \
+       |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
+
+/* SDRAM controller programming Values */
+#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \
+       (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1))
+#define REG_FIELD_SCL_VAL 3
+#define REG_FIELD_SCLIMX_VAL 0
+#else
+#define REG_FIELD_SCL_VAL\
+       ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \
+               ACFG_2XHCLK_LGTH)
+#define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL
+#endif
+
+#if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH))
+#define REG_FIELD_SRC_VAL 0
+#else
+#define REG_FIELD_SRC_VAL\
+       ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+               ACFG_2XHCLK_LGTH)
+#endif
+
+/* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/
+#define REG_ESDCTL_BASE_CONFIG (0x80020485\
+                               | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\
+                               | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\
+                               | (((ACFG_SDRAM_REFRESH)&0x7)<<13))
+
+#define ACFG_NORMAL_RW_CMD     ((0x0<<28)+REG_ESDCTL_BASE_CONFIG)
+#define ACFG_PRECHARGE_CMD     ((0x1<<28)+REG_ESDCTL_BASE_CONFIG)
+#define ACFG_AUTOREFRESH_CMD   ((0x2<<28)+REG_ESDCTL_BASE_CONFIG)
+#define ACFG_SET_MODE_REG_CMD  ((0x3<<28)+REG_ESDCTL_BASE_CONFIG)
+
+/* ESDRAMC Configuration Registers : force CL=3 to lpddr */
+#define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\
+       | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \
+               ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\
+       | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\
+       | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \
+               ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \
+       | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\
+       | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\
+       | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+               ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \
+       | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+               ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \
+       | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\
+       | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \
+               ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \
+       | (((REG_FIELD_SRC_VAL)&0x0F)<<0))
+
+/* Issue Mode register Command to SDRAM */
+#define ACFG_SDRAM_MODE_REGISTER_VAL\
+       ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\
+       | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\
+       | ((0)<<(3)) /* sequentiql access */ \
+       /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/)
+
+/* Issue Extended Mode register Command to SDRAM */
+#define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\
+       ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\
+       | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\
+       | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2)))
+
+/* Issue Precharge all Command to SDRAM */
+#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10)
+
+#endif /* __APF27_H */
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
new file mode 100644 (file)
index 0000000..0c08c06
--- /dev/null
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2002-2013
+ * Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * based on the files by
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com
+ * and
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <command.h>
+#include <config.h>
+#include "fpga.h"
+#include <spartan3.h>
+#include "apf27.h"
+
+/*
+ * Note that these are pointers to code that is in Flash.  They will be
+ * relocated at runtime.
+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
+ * Just take care about the file size
+ */
+Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
+       fpga_pre_fn,
+       fpga_pgm_fn,
+       fpga_init_fn,
+       NULL,
+       fpga_done_fn,
+       fpga_clk_fn,
+       fpga_cs_fn,
+       fpga_wr_fn,
+       fpga_rdata_fn,
+       fpga_wdata_fn,
+       fpga_busy_fn,
+       fpga_abort_fn,
+       fpga_post_fn,
+};
+
+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+       {Xilinx_Spartan3,
+        slave_parallel,
+        1196128l/8,
+        (void *)&fpga_fns,
+        0,
+        "3s200aft256"}
+};
+
+/*
+ * Initialize GPIO port B before download
+ */
+int fpga_pre_fn(int cookie)
+{
+       /* Initialize GPIO pins */
+       gpio_set_value(ACFG_FPGA_PWR, 1);
+       imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
+       imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
+       imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+       imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+       imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+       imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+       imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
+       gpio_set_value(ACFG_FPGA_RESET, 1);
+       imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+       imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+       gpio_set_value(ACFG_FPGA_PRG, 1);
+       gpio_set_value(ACFG_FPGA_CLK, 1);
+       gpio_set_value(ACFG_FPGA_RW, 1);
+       gpio_set_value(ACFG_FPGA_CS, 1);
+       gpio_set_value(ACFG_FPGA_SUSPEND, 0);
+       gpio_set_value(ACFG_FPGA_PWR, 0);
+       udelay(30000); /*wait until supply started*/
+
+       return cookie;
+}
+
+/*
+ * Set the FPGA's active-low program line to the specified level
+ */
+int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+       debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
+             assert ? "high" : "low");
+       gpio_set_value(ACFG_FPGA_PRG, !assert);
+       return assert;
+}
+
+/*
+ * Set the FPGA's active-high clock line to the specified level
+ */
+int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+       debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
+             assert_clk ? "high" : "low");
+       gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
+       return assert_clk;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+int fpga_init_fn(int cookie)
+{
+       int value;
+       debug("%s:%d: INIT check... ", __func__, __LINE__);
+       value = gpio_get_value(ACFG_FPGA_INIT);
+       /* printf("init value read %x",value); */
+#ifdef CONFIG_SYS_FPGA_IS_PROTO
+       return value;
+#else
+       return !value;
+#endif
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+int fpga_done_fn(int cookie)
+{
+       debug("%s:%d: DONE check... %s", __func__, __LINE__,
+             gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
+       return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
+}
+
+/*
+ * Set the FPGA's wr line to the specified level
+ */
+int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+       debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
+             assert_write ? "high" : "low");
+       gpio_set_value(ACFG_FPGA_RW, !assert_write);
+       return assert_write;
+}
+
+int fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+       debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
+             assert_cs ? "high" : "low");
+       gpio_set_value(ACFG_FPGA_CS, !assert_cs);
+       return assert_cs;
+}
+
+int fpga_rdata_fn(unsigned char *data, int cookie)
+{
+       debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
+             *((char *)ACFG_FPGA_RDATA));
+       *data = (unsigned char)
+               ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
+       return *data;
+}
+
+int fpga_wdata_fn(unsigned char data, int flush, int cookie)
+{
+       debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
+             data);
+       *((unsigned short *)ACFG_FPGA_WDATA) = data;
+       return data;
+}
+
+int fpga_abort_fn(int cookie)
+{
+       return fpga_post_fn(cookie);
+}
+
+
+int fpga_busy_fn(int cookie)
+{
+       return 1;
+}
+
+int fpga_post_fn(int cookie)
+{
+       debug("%s:%d: FPGA POST ", __func__, __LINE__);
+
+       imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
+       imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
+       imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
+       gpio_set_value(ACFG_FPGA_PRG, 1);
+       gpio_set_value(ACFG_FPGA_RESET, 0);
+       imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
+       return cookie;
+}
+
+void apf27_fpga_setup(void)
+{
+       struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
+       struct system_control_regs *system =
+               (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+
+       /* Configure FPGA CLKO */
+       writel(ACFG_CCSR_VAL, &pll->ccsr);
+
+       /* Configure strentgh for FPGA */
+       writel(ACFG_DSCR10_VAL, &system->dscr10);
+       writel(ACFG_DSCR3_VAL, &system->dscr3);
+       writel(ACFG_DSCR7_VAL, &system->dscr7);
+       writel(ACFG_DSCR2_VAL, &system->dscr2);
+}
+
+/*
+ * Initialize the fpga.  Return 1 on success, 0 on failure.
+ */
+void APF27_init_fpga(void)
+{
+       int i;
+
+       apf27_fpga_setup();
+
+       fpga_init();
+
+       for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+               debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
+               fpga_add(fpga_xilinx, &fpga[i]);
+       }
+
+       return;
+}
diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h
new file mode 100644 (file)
index 0000000..84a5244
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2002-2013
+ * Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * based on the files by
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com
+ * and
+ * Keith Outwater, keith_outwater@mvis.com
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+extern void APF27_init_fpga(void);
+
+extern int fpga_pre_fn(int cookie);
+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
+extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
+extern int fpga_init_fn(int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_rdata_fn(unsigned char *data, int cookie);
+extern int fpga_wdata_fn(unsigned char data, int flush, int cookie);
+extern int fpga_abort_fn(int cookie);
+extern int fpga_post_fn(int cookie);
+extern int fpga_busy_fn(int cookie);
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
new file mode 100644 (file)
index 0000000..4293cb1
--- /dev/null
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <config.h>
+#include <generated/asm-offsets.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
+#include "apf27.h"
+
+       .macro init_aipi
+       /*
+        * setup AIPI1 and AIPI2
+        */
+       write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
+       write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
+       write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
+       write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
+
+       /* Change SDRAM signal strengh */
+       ldr r0, =GPCR
+       ldr r1, =ACFG_GPCR_VAL
+       ldr r5, [r0]
+       orr r5, r5, r1
+       str r5, [r0]
+
+       .endm /* init_aipi */
+
+       .macro init_clock
+       ldr r0, =CSCR
+       /* disable MPLL/SPLL first */
+       ldr r1, [r0]
+       bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
+       str r1, [r0]
+
+       /*
+        * pll clock initialization predefined in apf27.h
+        */
+       write32 MPCTL0, ACFG_MPCTL0_VAL
+       write32 SPCTL0, ACFG_SPCTL0_VAL
+
+       write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
+
+       /*
+        * add some delay here
+        */
+       mov r1, #0x1000
+       1:  subs r1, r1, #0x1
+       bne 1b
+
+       /* peripheral clock divider */
+       write32 PCDR0, ACFG_PCDR0_VAL
+       write32 PCDR1, ACFG_PCDR1_VAL
+
+       /* Configure PCCR0 and PCCR1 */
+       write32 PCCR0, ACFG_PCCR0_VAL
+       write32 PCCR1, ACFG_PCCR1_VAL
+
+       .endm /* init_clock */
+
+       .macro init_ddr
+       /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
+       ldr             r0, =IMX_ESD_BASE
+       ldr             r4, =ESDMISC_SDRAM_RDY
+2:     ldr             r1, [r0, #ESDMISC_ROF]
+       ands            r1, r1, r4
+       bpl             2b
+
+       /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
+       ldr             r0, =IMX_ESD_BASE
+       ldr             r4, =ACFG_ESDMISC_VAL
+       orr             r1, r4, #ESDMISC_MDDR_DL_RST
+       str             r1, [r0, #ESDMISC_ROF]
+
+       /* Hold for more than 200ns */
+       ldr             r1, =0x10000
+1:     subs            r1, r1, #0x1
+       bne             1b
+
+       str             r4, [r0]
+
+       ldr             r0, =IMX_ESD_BASE
+       ldr             r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
+       str             r1, [r0, #ESDCFG0_ROF]
+
+       ldr             r0, =IMX_ESD_BASE
+       ldr             r1, =ACFG_PRECHARGE_CMD
+       str             r1, [r0, #ESDCTL0_ROF]
+
+       /* write8(0xA0001000, any value) */
+       ldr             r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
+       strb            r2, [r1]
+
+       ldr             r1, =ACFG_AUTOREFRESH_CMD
+       str             r1, [r0, #ESDCTL0_ROF]
+
+       ldr             r4, =PHYS_SDRAM_1       /* CSD0 base address    */
+
+       ldr             r6,=0x7         /* load loop counter    */
+1:     str             r5,[r4]         /* run auto-refresh cycle to array 0 */
+       subs            r6,r6,#1
+       bne 1b
+
+       ldr             r1, =ACFG_SET_MODE_REG_CMD
+       str             r1, [r0, #ESDCTL0_ROF]
+
+       /* set standard mode register */
+       ldr             r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
+       strb            r2, [r4]
+
+       /* set extended mode register */
+       ldr             r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
+       strb            r5, [r4]
+
+       ldr             r1, =ACFG_NORMAL_RW_CMD
+       str             r1, [r0, #ESDCTL0_ROF]
+
+       /* 2nd sdram */
+       ldr             r0, =IMX_ESD_BASE
+       ldr             r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
+       str             r1, [r0, #ESDCFG1_ROF]
+
+       ldr             r0, =IMX_ESD_BASE
+       ldr             r1, =ACFG_PRECHARGE_CMD
+       str             r1, [r0, #ESDCTL1_ROF]
+
+       /* write8(0xB0001000, any value) */
+       ldr             r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
+       strb            r2, [r1]
+
+       ldr             r1, =ACFG_AUTOREFRESH_CMD
+       str             r1, [r0, #ESDCTL1_ROF]
+
+       ldr             r4, =PHYS_SDRAM_2       /* CSD1 base address */
+
+       ldr             r6,=0x7         /* load loop counter */
+1:     str             r5,[r4]         /* run auto-refresh cycle to array 0 */
+       subs            r6,r6,#1
+       bne 1b
+
+       ldr             r1, =ACFG_SET_MODE_REG_CMD
+       str             r1, [r0, #ESDCTL1_ROF]
+
+       /* set standard mode register */
+       ldr             r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
+       strb            r2, [r4]
+
+       /* set extended mode register */
+       ldr             r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
+       strb            r2, [r4]
+
+       ldr             r1, =ACFG_NORMAL_RW_CMD
+       str             r1, [r0, #ESDCTL1_ROF]
+       .endm /* init_ddr */
+
+.globl lowlevel_init
+lowlevel_init:
+
+       init_aipi
+       init_clock
+#ifdef CONFIG_SPL_BUILD
+       init_ddr
+#endif
+
+       mov     pc, lr
index 4c7a7f4..56febd9 100644 (file)
@@ -256,3 +256,18 @@ ulong get_tbclk(void)
 {
        return (ulong)CONFIG_SYS_HZ;
 }
+
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+/* Setting the address at which secondary cores start from.
+ * Versatile Express uses one address for all cores, so ignore corenr
+ */
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+       /* The SYSFLAGS register on VExpress needs to be cleared first
+        * by writing to the next address, since any writes to the address
+        * at offset 0 will only be ORed in
+        */
+       writel(~0, CONFIG_SYSFLAGS_ADDR + 4);
+       writel(addr, CONFIG_SYSFLAGS_ADDR);
+}
+#endif
index 3b05baa..81419f9 100644 (file)
@@ -132,9 +132,9 @@ const iomux_cfg_t iomux_setup[] = {
        MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
 };
 
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
-       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 
        /* switch LED on */
        gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
index f664f6d..2b61e5d 100644 (file)
@@ -593,6 +593,7 @@ int board_video_skip(void)
                if (!panel) {
                        panel = displays[0].mode.name;
                        printf("No panel detected: default to %s\n", panel);
+                       i = 0;
                }
        } else {
                for (i = 0; i < ARRAY_SIZE(displays); i++) {
@@ -609,9 +610,10 @@ int board_video_skip(void)
                               displays[i].mode.name,
                               displays[i].mode.xres,
                               displays[i].mode.yres);
-               } else
+               } else {
                        printf("LCD %s cannot be configured: %d\n",
                               displays[i].mode.name, ret);
+               }
        } else {
                printf("unsupported panel %s\n", panel);
                ret = -EINVAL;
similarity index 60%
rename from arch/arm/cpu/arm925t/Makefile
rename to board/creative/xfi3/Makefile
index 40d2156..4dc2b48 100644 (file)
@@ -7,21 +7,18 @@
 
 include $(TOPDIR)/config.mk
 
-LIB    = $(obj)lib$(CPU).o
+LIB    = $(obj)lib$(BOARD).o
 
-START  = start.o
+ifndef CONFIG_SPL_BUILD
+COBJS  := xfi3.o
+else
+COBJS  := spl_boot.o
+endif
 
-COBJS  += cpu.o
-COBJS  += omap925.o
-COBJS  += timer.o
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
 
-SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
-START  := $(addprefix $(obj),$(START))
-
-all:   $(obj).depend $(START) $(LIB)
-
-$(LIB):        $(OBJS)
+$(LIB):        $(obj).depend $(OBJS)
        $(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
diff --git a/board/creative/xfi3/spl_boot.c b/board/creative/xfi3/spl_boot.c
new file mode 100644 (file)
index 0000000..af7aa0e
--- /dev/null
@@ -0,0 +1,134 @@
+/*
+ * Creative ZEN X-Fi3 setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define        MUX_CONFIG_EMI  (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define        MUX_CONFIG_SSP  (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define        MUX_CONFIG_LCD  (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+       /* EMI */
+       MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+       MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+       MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+       MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+
+       MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP,
+
+       MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP,
+
+       /* PWM -- FIXME */
+       MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+       /* mDDR configuration values */
+       const uint32_t regs[] = {
+               0x01010001, 0x00010000, 0x01000000, 0x00000001,
+               0x00010101, 0x00000001, 0x00010000, 0x01000001,
+               0x01010000, 0x00000001, 0x07000200, 0x04070203,
+               0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
+               0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
+               0x03061323, 0x0000000a, 0x00080008, 0x00200020,
+               0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+               0x00000000, 0x00000000, 0x00000020, 0x00000000,
+               0x001023cd, 0x20410010, 0x00006665, 0x00000000,
+               0x00000101, 0x00000001, 0x00000000, 0x00000000,
+       };
+       memcpy(dram_vals, regs, sizeof(regs));
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/creative/xfi3/xfi3.c b/board/creative/xfi3/xfi3.c
new file mode 100644 (file)
index 0000000..1d83ea8
--- /dev/null
@@ -0,0 +1,224 @@
+/*
+ * Creative ZEN X-Fi3 board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * Hardware investigation done by:
+ *
+ * Amaury Pouly <amaury.pouly@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+       /* IO0 clock at 480MHz */
+       mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+       /* SSP0 clock at 96MHz */
+       mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int xfi3_mmc_cd(int id)
+{
+       switch (id) {
+       case 0:
+               /* The SSP_DETECT is inverted on this board. */
+               return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+       case 1:
+               /* Phison bridge always present */
+               return 1;
+       default:
+               return 0;
+       }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       int ret;
+
+       /* MicroSD slot */
+       gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+       gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
+       ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
+       if (ret)
+               return ret;
+
+       /* Phison SD-NAND bridge */
+       ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
+
+       return ret;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
+{
+       struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+       const unsigned int timeout = 0x10000;
+
+       if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+                             timeout))
+               return -ETIMEDOUT;
+
+       writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
+               (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
+               &regs->hw_lcdif_transfer_count);
+
+       writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
+              &regs->hw_lcdif_ctrl_clr);
+
+       if (data)
+               writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set);
+
+       writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
+
+       if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29,
+                             timeout))
+               return -ETIMEDOUT;
+
+       writel(payload, &regs->hw_lcdif_data);
+       return mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+                                timeout);
+}
+
+static void mxsfb_write_register(uint32_t reg, uint32_t data)
+{
+       mxsfb_write_byte(reg, 0);
+       mxsfb_write_byte(data, 1);
+}
+
+static const struct {
+       uint8_t         reg;
+       uint8_t         delay;
+       uint16_t        val;
+} lcd_regs[] = {
+       { 0x01, 0,  0x001c },
+       { 0x02, 0,  0x0100 },
+       /* Writing 0x30 to reg. 0x03 flips the LCD */
+       { 0x03, 0,  0x1038 },
+       { 0x08, 0,  0x0808 },
+       /* This can contain 0x111 to rotate the LCD. */
+       { 0x0c, 0,  0x0000 },
+       { 0x0f, 0,  0x0c01 },
+       { 0x20, 0,  0x0000 },
+       { 0x21, 30, 0x0000 },
+       /* Wait 30 mS here */
+       { 0x10, 0,  0x0a00 },
+       { 0x11, 30, 0x1038 },
+       /* Wait 30 mS here */
+       { 0x12, 0,  0x1010 },
+       { 0x13, 0,  0x0050 },
+       { 0x14, 0,  0x4f58 },
+       { 0x30, 0,  0x0000 },
+       { 0x31, 0,  0x00db },
+       { 0x32, 0,  0x0000 },
+       { 0x33, 0,  0x0000 },
+       { 0x34, 0,  0x00db },
+       { 0x35, 0,  0x0000 },
+       { 0x36, 0,  0x00af },
+       { 0x37, 0,  0x0000 },
+       { 0x38, 0,  0x00db },
+       { 0x39, 0,  0x0000 },
+       { 0x50, 0,  0x0000 },
+       { 0x51, 0,  0x0705 },
+       { 0x52, 0,  0x0e0a },
+       { 0x53, 0,  0x0300 },
+       { 0x54, 0,  0x0a0e },
+       { 0x55, 0,  0x0507 },
+       { 0x56, 0,  0x0000 },
+       { 0x57, 0,  0x0003 },
+       { 0x58, 0,  0x090a },
+       { 0x59, 30, 0x0a09 },
+       /* Wait 30 mS here */
+       { 0x07, 30, 0x1017 },
+       /* Wait 40 mS here */
+       { 0x36, 0,  0x00af },
+       { 0x37, 0,  0x0000 },
+       { 0x38, 0,  0x00db },
+       { 0x39, 0,  0x0000 },
+       { 0x20, 0,  0x0000 },
+       { 0x21, 0,  0x0000 },
+};
+
+void board_mxsfb_system_setup(void)
+{
+       struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+       int i;
+
+       /* Switch the LCDIF into System-Mode */
+       writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
+               LCDIF_CTRL_BYPASS_COUNT, &regs->hw_lcdif_ctrl_clr);
+
+       /* Restart the SmartLCD controller */
+       mdelay(50);
+       writel(1, &regs->hw_lcdif_ctrl1_set);
+       mdelay(50);
+       writel(1, &regs->hw_lcdif_ctrl1_clr);
+       mdelay(50);
+       writel(1, &regs->hw_lcdif_ctrl1_set);
+       mdelay(50);
+
+       /* Program the SmartLCD controller */
+       writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, &regs->hw_lcdif_ctrl1_set);
+
+       writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
+              (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
+              (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
+              (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
+              &regs->hw_lcdif_timing);
+
+       /*
+        * OTM2201A init and configuration sequence.
+        */
+       for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
+               mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
+               if (lcd_regs[i].delay)
+                       mdelay(lcd_regs[i].delay);
+       }
+       /* Turn on Framebuffer Upload Mode */
+       mxsfb_write_byte(0x22, 0);
+
+       writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
+              &regs->hw_lcdif_ctrl_set);
+}
+#endif
+
+int board_init(void)
+{
+       /* Adress of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       /* Turn on PWM backlight */
+       gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       usb_eth_initialize(bis);
+       return 0;
+}
index f4453d6..33d38cf 100644 (file)
@@ -116,6 +116,8 @@ int board_eth_init(bd_t *bis)
        int ret;
 
        ret = cpu_eth_init(bis);
+       if (ret)
+               return ret;
 
        clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
                CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
index 525ba6a..5a1010e 100644 (file)
@@ -200,7 +200,7 @@ const iomux_cfg_t iomux_setup[] = {
                (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
 };
 
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
-       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 }
index 054ca0a..603f4dc 100644 (file)
@@ -129,7 +129,7 @@ void mxs_adjust_memory_params(uint32_t *dram_vals)
        dram_vals[HW_DRAM_CTL14] = HW_DRAM_CTL14_CONFIG;
 }
 
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
-       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 }
index 6ca842b..97c2376 100644 (file)
@@ -200,7 +200,7 @@ void mxs_adjust_memory_params(uint32_t *dram_vals)
        dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
 }
 
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
-       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 }
index a307f27..5005fe2 100644 (file)
@@ -103,10 +103,12 @@ int board_eth_init(bd_t *bis)
        int ret;
 
        ret = cpu_eth_init(bis);
+       if (ret)
+               return ret;
 
        /* MX28EVK uses ENET_CLK PAD to drive FEC clock */
        writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
-                                       &clkctrl_regs->hw_clkctrl_enet);
+              &clkctrl_regs->hw_clkctrl_enet);
 
        /* Power-on FECs */
        gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
index 427c83a..9fabef5 100644 (file)
@@ -251,14 +251,12 @@ int board_late_init(void)
 
 int board_eth_init(bd_t *bis)
 {
-       int rc = -ENODEV;
 #if defined(CONFIG_SMC911X)
-       rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+       int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+       if (rc)
+               return rc;
 #endif
-
-       cpu_eth_init(bis);
-
-       return rc;
+       return cpu_eth_init(bis);
 }
 
 #if defined(CONFIG_FSL_ESDHC)
index 1cdf2cb..c55ee87 100644 (file)
@@ -200,7 +200,7 @@ int board_eth_init(bd_t *bis)
        if (ret)
                printf("FEC MXC: %s:failed\n", __func__);
 
-       return 0;
+       return ret;
 }
 
 #define BOARD_REV_B  0x200
index 5db516d..9dbe605 100644 (file)
@@ -234,47 +234,172 @@ int board_phy_config(struct phy_device *phydev)
 }
 
 #if defined(CONFIG_VIDEO_IPUV3)
-static struct fb_videomode const hdmi = {
-       .name           = "HDMI",
-       .refresh        = 60,
-       .xres           = 1024,
-       .yres           = 768,
-       .pixclock       = 15385,
-       .left_margin    = 220,
-       .right_margin   = 40,
-       .upper_margin   = 21,
-       .lower_margin   = 7,
-       .hsync_len      = 60,
-       .vsync_len      = 10,
-       .sync           = FB_SYNC_EXT,
-       .vmode          = FB_VMODE_NONINTERLACED
+struct display_info_t {
+       int     bus;
+       int     addr;
+       int     pixfmt;
+       int     (*detect)(struct display_info_t const *dev);
+       void    (*enable)(struct display_info_t const *dev);
+       struct  fb_videomode mode;
 };
 
-int board_video_skip(void)
+static int detect_hdmi(struct display_info_t const *dev)
 {
-       int ret;
+       struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+       return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
 
-       ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+       imx_enable_hdmi_phy();
+}
 
-       if (ret)
-               printf("HDMI cannot be configured: %d\n", ret);
+static void enable_lvds(struct display_info_t const *dev)
+{
+       struct iomuxc *iomux = (struct iomuxc *)
+                               IOMUXC_BASE_ADDR;
+       u32 reg = readl(&iomux->gpr[2]);
+       reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+              IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
+       writel(reg, &iomux->gpr[2]);
+}
+static struct display_info_t const displays[] = {{
+       .bus    = -1,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = detect_hdmi,
+       .enable = do_enable_hdmi,
+       .mode   = {
+               .name           = "HDMI",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = -1,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .detect = NULL,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "Hannstar-XGA",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} } };
 
-       imx_enable_hdmi_phy();
-       return ret;
+int board_video_skip(void)
+{
+       int i;
+       int ret;
+       char const *panel = getenv("panel");
+       if (!panel) {
+               for (i = 0; i < ARRAY_SIZE(displays); i++) {
+                       struct display_info_t const *dev = displays+i;
+                       if (dev->detect && dev->detect(dev)) {
+                               panel = dev->mode.name;
+                               printf("auto-detected panel %s\n", panel);
+                               break;
+                       }
+               }
+               if (!panel) {
+                       panel = displays[0].mode.name;
+                       printf("No panel detected: default to %s\n", panel);
+                       i = 0;
+               }
+       } else {
+               for (i = 0; i < ARRAY_SIZE(displays); i++) {
+                       if (!strcmp(panel, displays[i].mode.name))
+                               break;
+               }
+       }
+       if (i < ARRAY_SIZE(displays)) {
+               ret = ipuv3_fb_init(&displays[i].mode, 0,
+                                   displays[i].pixfmt);
+               if (!ret) {
+                       displays[i].enable(displays+i);
+                       printf("Display: %s (%ux%u)\n",
+                              displays[i].mode.name,
+                              displays[i].mode.xres,
+                              displays[i].mode.yres);
+               } else
+                       printf("LCD %s cannot be configured: %d\n",
+                              displays[i].mode.name, ret);
+       } else {
+               printf("unsupported panel %s\n", panel);
+               return -EINVAL;
+       }
+
+       return 0;
 }
 
 static void setup_display(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        int reg;
 
        enable_ipu_clock();
        imx_setup_hdmi();
 
+       /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
+       reg = __raw_readl(&mxc_ccm->CCGR3);
+       reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+       writel(reg, &mxc_ccm->CCGR3);
+
+       /* set LDB0, LDB1 clk select to 011/011 */
+       reg = readl(&mxc_ccm->cs2cdr);
+       reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+                | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+       reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+             | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+       writel(reg, &mxc_ccm->cs2cdr);
+
+       reg = readl(&mxc_ccm->cscmr2);
+       reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+       writel(reg, &mxc_ccm->cscmr2);
+
        reg = readl(&mxc_ccm->chsccdr);
        reg |= (CHSCCDR_CLK_SEL_LDB_DI0
                << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+       reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+               << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
        writel(reg, &mxc_ccm->chsccdr);
+
+       reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+            | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+            | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+            | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+            | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
+            | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+            | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
+            | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
+            | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
+       writel(reg, &iomux->gpr[2]);
+
+       reg = readl(&iomux->gpr[3]);
+       reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
+                       | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+           | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+              << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
+       writel(reg, &iomux->gpr[3]);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
@@ -297,7 +422,7 @@ int board_eth_init(bd_t *bis)
        if (ret)
                printf("FEC MXC: %s:failed\n", __func__);
 
-       return 0;
+       return ret;
 }
 
 int board_early_init_f(void)
index 5b6ef81..643fdac 100644 (file)
@@ -18,6 +18,7 @@
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <mmc.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,6 +30,12 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
        PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
+       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
+       PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define ETH_PHY_RESET  IMX_GPIO_NR(4, 21)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -50,11 +57,35 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
        MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const fec_pads[] = {
+       MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+       MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static void setup_iomux_uart(void)
 {
        imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
+static void setup_iomux_fec(void)
+{
+       imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
+
+       /* Reset LAN8720 PHY */
+       gpio_direction_output(ETH_PHY_RESET , 0);
+       udelay(1000);
+       gpio_set_value(ETH_PHY_RESET, 1);
+}
+
 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
        {USDHC2_BASE_ADDR},
 };
@@ -72,6 +103,40 @@ int board_mmc_init(bd_t *bis)
        return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+       int ret;
+
+       setup_iomux_fec();
+
+       ret = cpu_eth_init(bis);
+       if (ret) {
+               printf("FEC MXC: %s:failed\n", __func__);
+               return ret;
+       }
+
+       return 0;
+}
+
+static int setup_fec(void)
+{
+       struct iomuxc_base_regs *iomuxc_regs =
+                               (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+       int ret;
+
+       /* clear gpr1[14], gpr1[18:17] to select anatop clock */
+       clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
+
+       ret = enable_fec_anatop_clock();
+       if (ret)
+               return ret;
+
+       return 0;
+}
+#endif
+
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
@@ -83,6 +148,9 @@ int board_init(void)
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_FEC_MXC
+       setup_fec();
+#endif
        return 0;
 }
 
index 9e91f68..347c128 100644 (file)
@@ -64,7 +64,7 @@ static struct emif_regs ddr3_emif_reg_data = {
 
 #define OSC    (V_OSCK/1000000)
 const struct dpll_params dpll_ddr = {
-               303, OSC-1, 1, -1, -1, -1, -1};
+               400, OSC-1, 1, -1, -1, -1, -1};
 
 const struct dpll_params *get_dpll_ddr_params(void)
 {
@@ -83,7 +83,7 @@ void set_mux_conf_regs(void)
 
 void sdram_init(void)
 {
-       config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+       config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
                   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 }
 #endif
@@ -129,6 +129,7 @@ static struct cpsw_platform_data cpsw_data = {
        .ale_entries            = 1024,
        .host_port_reg_ofs      = 0x108,
        .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
        .mac_control            = (1 << 5),
        .control                = cpsw_control,
        .host_port_num          = 0,
index 0a66303..5272dfa 100644 (file)
@@ -85,7 +85,7 @@ const iomux_cfg_t iomux_setup[] = {
                (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
 };
 
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
-       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 }
index e40b0bd..dafb1eb 100644 (file)
@@ -150,6 +150,7 @@ static struct cpsw_platform_data cpsw_data = {
        .ale_entries            = 1024,
        .host_port_reg_ofs      = 0x108,
        .hw_stats_reg_ofs       = 0x900,
+       .bd_ram_ofs             = 0x2000,
        .mac_control            = (1 << 5),
        .control                = cpsw_control,
        .host_port_num          = 0,
diff --git a/board/sandisk/sansa_fuze_plus/Makefile b/board/sandisk/sansa_fuze_plus/Makefile
new file mode 100644 (file)
index 0000000..571cc07
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+ifndef CONFIG_SPL_BUILD
+COBJS  := sfp.o
+else
+COBJS  := spl_boot.o
+endif
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/sandisk/sansa_fuze_plus/sfp.c b/board/sandisk/sansa_fuze_plus/sfp.c
new file mode 100644 (file)
index 0000000..a3865ad
--- /dev/null
@@ -0,0 +1,388 @@
+/*
+ * SanDisk Sansa Fuze Plus board
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * Hardware investigation done by:
+ *
+ * Amaury Pouly <amaury.pouly@gmail.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+       /* IO0 clock at 480MHz */
+       mxs_set_ioclk(MXC_IOCLK0, 480000);
+
+       /* SSP0 clock at 96MHz */
+       mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       return mxs_dram_init();
+}
+
+#ifdef CONFIG_CMD_MMC
+static int xfi3_mmc_cd(int id)
+{
+       switch (id) {
+       case 0:
+               /* The SSP_DETECT is inverted on this board. */
+               return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+       case 1:
+               /* Internal eMMC always present */
+               return 1;
+       default:
+               return 0;
+       }
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       int ret;
+
+       /* MicroSD slot */
+       gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
+       gpio_direction_output(MX23_PAD_GPMI_D08__GPIO_0_8, 0);
+       ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
+       if (ret)
+               return ret;
+
+       /* Internal eMMC */
+       gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
+       ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
+
+       return ret;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+#define        MUX_CONFIG_LCD  (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+const iomux_cfg_t iomux_lcd_gpio[] = {
+       MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D06__GPIO_1_6 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D07__GPIO_1_7 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D08__GPIO_1_8 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D09__GPIO_1_9 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D10__GPIO_1_10 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D11__GPIO_1_11 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D12__GPIO_1_12 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D13__GPIO_1_13 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D14__GPIO_1_14 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D15__GPIO_1_15 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RS__GPIO_1_19 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_WR__GPIO_1_20 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_CS__GPIO_1_21 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_ENABLE__GPIO_1_23 | MUX_CONFIG_LCD,
+};
+
+const iomux_cfg_t iomux_lcd_lcd[] = {
+       MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+};
+
+static int mxsfb_read_register(uint32_t reg, uint32_t *value)
+{
+       iomux_cfg_t mux;
+       uint32_t val = 0;
+       int i;
+
+       /* Mangle the register offset. */
+       reg = ((reg & 0xff) << 1) | (((reg >> 8) & 0xff) << 10);
+
+       /*
+        * The SmartLCD interface on MX233 can only do WRITE operation
+        * via the LCDIF controller. Implement the READ operation by
+        * fiddling with bits.
+        */
+       mxs_iomux_setup_multiple_pads(iomux_lcd_gpio,
+               ARRAY_SIZE(iomux_lcd_gpio));
+
+       gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1);
+       gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1);
+       gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1);
+       gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
+
+       for (i = 0; i < 18; i++) {
+               mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+               gpio_direction_output(mux, 0);
+       }
+
+       udelay(2);
+       gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 0);
+       udelay(1);
+       gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 0);
+       udelay(1);
+       gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 0);
+       udelay(1);
+
+       for (i = 0; i < 18; i++) {
+               mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+               gpio_direction_output(mux, (reg >> i) & 1);
+       }
+       udelay(1);
+
+       gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1);
+       udelay(3);
+
+       for (i = 0; i < 18; i++) {
+               mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+               gpio_direction_input(mux);
+       }
+       udelay(2);
+
+       gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0);
+       udelay(1);
+       gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1);
+       udelay(1);
+       gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
+       udelay(3);
+       gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0);
+       udelay(2);
+
+       for (i = 0; i < 18; i++) {
+               mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
+               val |= !!gpio_get_value(mux) << i;
+       }
+       udelay(1);
+
+       gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
+       udelay(1);
+       gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1);
+       udelay(1);
+
+       mxs_iomux_setup_multiple_pads(iomux_lcd_lcd,
+               ARRAY_SIZE(iomux_lcd_lcd));
+
+       /* Demangle the register value. */
+       *value = ((val >> 1) & 0xff) | ((val >> 2) & 0xff00);
+
+       writel(val, 0x2000);
+       return 0;
+}
+
+static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
+{
+       struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+       const unsigned int timeout = 0x10000;
+
+       /* What is going on here I do not know. FIXME */
+       payload = ((payload & 0xff) << 1) | (((payload >> 8) & 0xff) << 10);
+
+       if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+                             timeout))
+               return -ETIMEDOUT;
+
+       writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
+               (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
+               &regs->hw_lcdif_transfer_count);
+
+       writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
+               &regs->hw_lcdif_ctrl_clr);
+
+       if (data)
+               writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set);
+
+       writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
+
+       if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29,
+                             timeout))
+               return -ETIMEDOUT;
+
+       writel(payload, &regs->hw_lcdif_data);
+       return mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
+                                timeout);
+}
+
+static void mxsfb_write_register(uint32_t reg, uint32_t data)
+{
+       mxsfb_write_byte(reg, 0);
+       mxsfb_write_byte(data, 1);
+}
+
+static const struct {
+       uint8_t         reg;
+       uint8_t         delay;
+       uint16_t        val;
+} lcd_regs[] = {
+       { 0xe5, 0  , 0x78f0 },
+       { 0xe3, 0  , 0x3008 },
+       { 0xe7, 0  , 0x0012 },
+       { 0xef, 0  , 0x1231 },
+       { 0x00, 0  , 0x0001 },
+       { 0x01, 0  , 0x0100 },
+       { 0x02, 0  , 0x0700 },
+       { 0x03, 0  , 0x1030 },
+       { 0x04, 0  , 0x0000 },
+       { 0x08, 0  , 0x0207 },
+       { 0x09, 0  , 0x0000 },
+       { 0x0a, 0  , 0x0000 },
+       { 0x0c, 0  , 0x0000 },
+       { 0x0d, 0  , 0x0000 },
+       { 0x0f, 0  , 0x0000 },
+       { 0x10, 0  , 0x0000 },
+       { 0x11, 0  , 0x0007 },
+       { 0x12, 0  , 0x0000 },
+       { 0x13, 20 , 0x0000 },
+       /* Wait 20 mS here. */
+       { 0x10, 0  , 0x1290 },
+       { 0x11, 50 , 0x0007 },
+       /* Wait 50 mS here. */
+       { 0x12, 50 , 0x0019 },
+       /* Wait 50 mS here. */
+       { 0x13, 0  , 0x1700 },
+       { 0x29, 50 , 0x0014 },
+       /* Wait 50 mS here. */
+       { 0x20, 0  , 0x0000 },
+       { 0x21, 0  , 0x0000 },
+       { 0x30, 0  , 0x0504 },
+       { 0x31, 0  , 0x0007 },
+       { 0x32, 0  , 0x0006 },
+       { 0x35, 0  , 0x0106 },
+       { 0x36, 0  , 0x0202 },
+       { 0x37, 0  , 0x0504 },
+       { 0x38, 0  , 0x0500 },
+       { 0x39, 0  , 0x0706 },
+       { 0x3c, 0  , 0x0204 },
+       { 0x3d, 0  , 0x0202 },
+       { 0x50, 0  , 0x0000 },
+       { 0x51, 0  , 0x00ef },
+       { 0x52, 0  , 0x0000 },
+       { 0x53, 0  , 0x013f },
+       { 0x60, 0  , 0xa700 },
+       { 0x61, 0  , 0x0001 },
+       { 0x6a, 0  , 0x0000 },
+       { 0x2b, 50 , 0x000d },
+       /* Wait 50 mS here. */
+       { 0x90, 0  , 0x0011 },
+       { 0x92, 0  , 0x0600 },
+       { 0x93, 0  , 0x0003 },
+       { 0x95, 0  , 0x0110 },
+       { 0x97, 0  , 0x0000 },
+       { 0x98, 0  , 0x0000 },
+       { 0x07, 0  , 0x0173 },
+};
+
+void board_mxsfb_system_setup(void)
+{
+       struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+       uint32_t id;
+       int i;
+
+       /* Switch the LCDIF into System-Mode */
+       writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
+               LCDIF_CTRL_BYPASS_COUNT, &regs->hw_lcdif_ctrl_clr);
+
+       /* To program the LCD, switch to 18bit bus + 18bit data. */
+       clrsetbits_le32(&regs->hw_lcdif_ctrl,
+               LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK,
+               LCDIF_CTRL_WORD_LENGTH_18BIT |
+               LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT);
+
+       mxsfb_read_register(0, &id);
+       writel(id, 0x2004);
+
+       /* Restart the SmartLCD controller */
+       mdelay(50);
+       writel(1, &regs->hw_lcdif_ctrl1_set);
+       mdelay(50);
+       writel(1, &regs->hw_lcdif_ctrl1_clr);
+       mdelay(50);
+       writel(1, &regs->hw_lcdif_ctrl1_set);
+       mdelay(50);
+
+       /* Program the SmartLCD controller */
+       writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, &regs->hw_lcdif_ctrl1_set);
+
+       writel((0x02 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
+              (0x02 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
+              (0x02 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
+              (0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
+              &regs->hw_lcdif_timing);
+
+       /*
+        * ILI9325 init and configuration sequence.
+        */
+       for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
+               mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
+               if (lcd_regs[i].delay)
+                       mdelay(lcd_regs[i].delay);
+       }
+       /* Turn on Framebuffer Upload Mode */
+       mxsfb_write_byte(0x22, 0);
+
+       writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
+               &regs->hw_lcdif_ctrl_set);
+
+       /* Operate the framebuffer in 16bit mode. */
+       clrsetbits_le32(&regs->hw_lcdif_ctrl,
+               LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK,
+               LCDIF_CTRL_WORD_LENGTH_16BIT |
+               LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT);
+}
+#endif
+
+int board_init(void)
+{
+       /* Adress of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       /* Turn on PWM backlight */
+       gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
+
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       usb_eth_initialize(bis);
+       return 0;
+}
diff --git a/board/sandisk/sansa_fuze_plus/spl_boot.c b/board/sandisk/sansa_fuze_plus/spl_boot.c
new file mode 100644 (file)
index 0000000..825be82
--- /dev/null
@@ -0,0 +1,140 @@
+/*
+ * SanDisk Sansa Fuze Plus setup
+ *
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx23.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define        MUX_CONFIG_EMI  (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
+#define        MUX_CONFIG_SSP  (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
+#define        MUX_CONFIG_LCD  (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+       /* EMI */
+       MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
+
+       MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+
+       MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+       MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+
+       MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
+       MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
+
+       MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
+       MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D08__GPIO_0_8 | MUX_CONFIG_SSP,
+
+       MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D04__SSP2_DATA4 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D05__SSP2_DATA5 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D06__SSP2_DATA6 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_D07__SSP2_DATA7 | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
+       MX23_PAD_GPMI_WRN__SSP2_SCK |
+               (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
+       MX23_PAD_PWM3__GPIO_1_29 | MUX_CONFIG_SSP,
+
+       /* PWM -- FIXME */
+       MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
+};
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+       /* mDDR configuration values */
+       const uint32_t regs[] = {
+               0x01010001, 0x00010000, 0x01000000, 0x00000001,
+               0x00010101, 0x00000001, 0x00010000, 0x01000001,
+               0x01010000, 0x00000001, 0x07000200, 0x04070203,
+               0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
+               0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
+               0x03061323, 0x0000000a, 0x00080008, 0x00200020,
+               0x00200020, 0x00200020, 0x000003f7, 0x00000000,
+               0x00000000, 0x00000000, 0x00000020, 0x00000000,
+               0x001023cd, 0x20410010, 0x00006665, 0x00000000,
+               0x00000101, 0x00000001, 0x00000000, 0x00000000,
+       };
+       memcpy(dram_vals, regs, sizeof(regs));
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
index 1fe9224..60195c3 100644 (file)
@@ -138,9 +138,9 @@ const iomux_cfg_t iomux_setup[] = {
        MX28_PAD_GPMI_D06__GPIO_0_6 | MUX_CONFIG_LED,
 };
 
-void board_init_ll(void)
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
 {
-       mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
+       mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
 }
 
 void mxs_adjust_memory_params(uint32_t *dram_vals)
index cc04426..c2fc5a6 100644 (file)
@@ -26,6 +26,8 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -244,6 +246,150 @@ const struct dpll_params dpll_ddr_evm_sk = {
 const struct dpll_params dpll_ddr_bone_black = {
                400, OSC-1, 1, -1, -1, -1, -1};
 
+void am33xx_spl_board_init(void)
+{
+       struct am335x_baseboard_id header;
+       int mpu_vdd;
+
+       if (read_eeprom(&header) < 0)
+               puts("Could not get board ID.\n");
+
+       /* Get the frequency */
+       dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+       if (board_is_bone(&header) || board_is_bone_lt(&header)) {
+               /* BeagleBone PMIC Code */
+               int usb_cur_lim;
+
+               /*
+                * Only perform PMIC configurations if board rev > A1
+                * on Beaglebone White
+                */
+               if (board_is_bone(&header) && !strncmp(header.version,
+                                                      "00A1", 4))
+                       return;
+
+               if (i2c_probe(TPS65217_CHIP_PM))
+                       return;
+
+               /*
+                * On Beaglebone White we need to ensure we have AC power
+                * before increasing the frequency.
+                */
+               if (board_is_bone(&header)) {
+                       uchar pmic_status_reg;
+                       if (tps65217_reg_read(TPS65217_STATUS,
+                                             &pmic_status_reg))
+                               return;
+                       if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
+                               puts("No AC power, disabling frequency switch\n");
+                               return;
+                       }
+               }
+
+               /*
+                * Override what we have detected since we know if we have
+                * a Beaglebone Black it supports 1GHz.
+                */
+               if (board_is_bone_lt(&header))
+                       dpll_mpu_opp100.m = MPUPLL_M_1000;
+
+               /*
+                * Increase USB current limit to 1300mA or 1800mA and set
+                * the MPU voltage controller as needed.
+                */
+               if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+                       usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+                       mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+               } else {
+                       usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+                       mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+               }
+
+               if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+                                      TPS65217_POWER_PATH,
+                                      usb_cur_lim,
+                                      TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+                       puts("tps65217_reg_write failure\n");
+
+               /* Set DCDC3 (CORE) voltage to 1.125V */
+               if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+                                           TPS65217_DCDC_VOLT_SEL_1125MV)) {
+                       puts("tps65217_voltage_update failure\n");
+                       return;
+               }
+
+               /* Set CORE Frequencies to OPP100 */
+               do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+               /* Set DCDC2 (MPU) voltage */
+               if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+                       puts("tps65217_voltage_update failure\n");
+                       return;
+               }
+
+               /*
+                * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+                * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+                */
+               if (board_is_bone(&header)) {
+                       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                                              TPS65217_DEFLS1,
+                                              TPS65217_LDO_VOLTAGE_OUT_3_3,
+                                              TPS65217_LDO_MASK))
+                               puts("tps65217_reg_write failure\n");
+               } else {
+                       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                                              TPS65217_DEFLS1,
+                                              TPS65217_LDO_VOLTAGE_OUT_1_8,
+                                              TPS65217_LDO_MASK))
+                               puts("tps65217_reg_write failure\n");
+               }
+
+               if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                                      TPS65217_DEFLS2,
+                                      TPS65217_LDO_VOLTAGE_OUT_3_3,
+                                      TPS65217_LDO_MASK))
+                       puts("tps65217_reg_write failure\n");
+       } else {
+               int sil_rev;
+
+               /*
+                * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+                * MPU frequencies we support we use a CORE voltage of
+                * 1.1375V.  For MPU voltage we need to switch based on
+                * the frequency we are running at.
+                */
+               if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
+                       return;
+
+               /*
+                * Depending on MPU clock and PG we will need a different
+                * VDD to drive at that speed.
+                */
+               sil_rev = readl(&cdev->deviceid) >> 28;
+               mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+                                                     dpll_mpu_opp100.m);
+
+               /* Tell the TPS65910 to use i2c */
+               tps65910_set_i2c_control();
+
+               /* First update MPU voltage. */
+               if (tps65910_voltage_update(MPU, mpu_vdd))
+                       return;
+
+               /* Second, update the CORE voltage. */
+               if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
+                       return;
+
+               /* Set CORE Frequencies to OPP100 */
+               do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+       }
+
+       /* Set MPU Frequency to what we detected now that voltages are set */
+       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
 const struct dpll_params *get_dpll_ddr_params(void)
 {
        struct am335x_baseboard_id header;
diff --git a/board/ti/omap1510inn/config.mk b/board/ti/omap1510inn/config.mk
deleted file mode 100644 (file)
index 67fe0bd..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# TI Innovator board with OMAP1510 (ARM925T) cpu
-# see http://www.ti.com/ for more information on Texas Insturments
-#
-# Innovator has 1 bank of 256 MB SDRAM
-# Physical Address:
-# 1000'0000 to 2000'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000  (mem base + reserved)
-#
-# we load ourself to 1108'0000
-#
-#
-
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/board/ti/omap1510inn/lowlevel_init.S b/board/ti/omap1510inn/lowlevel_init.S
deleted file mode 100644 (file)
index 4d3ec39..0000000
+++ /dev/null
@@ -1,380 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * -- Some bits of code used from rrload's head_OMAP1510.s --
- * Copyright (C) 2002 RidgeRun, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP1510)
-#include <./configs/omap1510.h>
-#endif
-
-#define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
-
-
-_TEXT_BASE:
-       .word   CONFIG_SYS_TEXT_BASE        /* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-
-       /*
-        * Configure 1510 pins functions to match our board.
-        */
-       ldr     r0, REG_PULL_DWN_CTRL_0
-       ldr     r1, VAL_PULL_DWN_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_1
-       ldr     r1, VAL_PULL_DWN_CTRL_1
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_2
-       ldr     r1, VAL_PULL_DWN_CTRL_2
-       str     r1, [r0]
-       ldr     r0, REG_PULL_DWN_CTRL_3
-       ldr     r1, VAL_PULL_DWN_CTRL_3
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_4
-       ldr     r1, VAL_FUNC_MUX_CTRL_4
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_5
-       ldr     r1, VAL_FUNC_MUX_CTRL_5
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_6
-       ldr     r1, VAL_FUNC_MUX_CTRL_6
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_7
-       ldr     r1, VAL_FUNC_MUX_CTRL_7
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_8
-       ldr     r1, VAL_FUNC_MUX_CTRL_8
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_9
-       ldr     r1, VAL_FUNC_MUX_CTRL_9
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_A
-       ldr     r1, VAL_FUNC_MUX_CTRL_A
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_B
-       ldr     r1, VAL_FUNC_MUX_CTRL_B
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_C
-       ldr     r1, VAL_FUNC_MUX_CTRL_C
-       str     r1, [r0]
-       ldr     r0, REG_FUNC_MUX_CTRL_D
-       ldr     r1, VAL_FUNC_MUX_CTRL_D
-       str     r1, [r0]
-       ldr     r0, REG_VOLTAGE_CTRL_0
-       ldr     r1, VAL_VOLTAGE_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_TEST_DBG_CTRL_0
-       ldr     r1, VAL_TEST_DBG_CTRL_0
-       str     r1, [r0]
-       ldr     r0, REG_MOD_CONF_CTRL_0
-       ldr     r1, VAL_MOD_CONF_CTRL_0
-       str     r1, [r0]
-
-       /* Move to 1510 mode */
-       ldr     r0, REG_COMP_MODE_CTRL_0
-       ldr     r1, VAL_COMP_MODE_CTRL_0
-       str     r1, [r0]
-
-       /* Set up Traffic Ctlr*/
-       ldr r0, REG_TC_IMIF_PRIO
-       mov r1, #0x0
-       str r1, [r0]
-       ldr r0, REG_TC_EMIFS_PRIO
-       str r1, [r0]
-       ldr r0, REG_TC_EMIFF_PRIO
-       str r1, [r0]
-
-       ldr r0, REG_TC_EMIFS_CONFIG
-       ldr r1, [r0]
-       bic r1, r1, #0x08   /* clear the global power-down enable PDE bit */
-       bic r1, r1, #0x01   /* write protect flash by clearing the WP bit */
-       str r1, [r0]        /* EMIFS GlB Configuration. (value 0x12 most likely) */
-
-       /* Setup some clock domains */
-       ldr r1, =OMAP1510_CLKS
-       ldr r0, REG_ARM_IDLECT2
-       strh r1, [r0]  /* CLKM, Clock domain control. */
-
-       mov r1, #0x01  /* PER_EN bit */
-       ldr r0, REG_ARM_RSTCT2
-       strh r1, [r0]  /* CLKM; Peripheral reset. */
-
-       /* Set CLKM to Sync-Scalable  */
-       /* I supposidly need to enable the dsp clock before switching */
-       mov r1, #0x1000
-       ldr r0, REG_ARM_SYSST
-       strh r1, [r0]
-       mov r0, #0x400
-1:
-       subs r0, r0, #0x1   /* wait for any bubbles to finish */
-       bne 1b
-
-       ldr r1, VAL_ARM_CKCTL  /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
-       ldr r0, REG_ARM_CKCTL
-       strh r1, [r0]
-
-       /* setup DPLL 1 */
-       ldr r1, VAL_DPLL1_CTL
-       ldr r0, REG_DPLL1_CTL
-       strh r1, [r0]
-       ands r1, r1, #0x10  /* Check if PLL is enabled. */
-       beq lock_end        /* Do not look for lock if BYPASS selected */
-2:
-       ldrh r1, [r0]
-       ands r1, r1, #0x01  /* Check the LOCK bit. */
-       beq 2b              /* ...loop until bit goes hi. */
-lock_end:
-
-       /* Set memory timings corresponding to the new clock speed */
-
-       /* Check execution location to determine current execution location
-        * and branch to appropriate initialization code.
-        */
-       mov r0, #0x10000000                 /* Load physical SDRAM base. */
-       mov r1, pc                          /* Get current execution location. */
-       /* Zero all but top 6 bits of PC, as they alone detect whether an
-        * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
-        * valid range for SDRAM on the OMAP 1510/5910.
-        */
-       and r1, r1, #0xfc000000
-       cmp r1, r0                      /* Compare. */
-       beq skip_sdram                  /* Skip over EMIF-fast initialization
-                                        * if running from SDRAM.
-                                        */
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov r3, #0x1800                        /* value should be checked */
-3:
-       subs r3, r3, #0x1                     /* Decrement count */
-       bne 3b
-
-       /*
-        * Set SDRAM control values. Disable refresh before MRS command.
-        */
-       ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG   /* get good value */
-       bic r3, r0, #0xC                    /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
-       orr r3, r3, #0x8000000              /* (BIT27) Disable CLK when Power down or Self-Refresh */
-       orr r3, r3, #0x4000000              /* BIT26 Power Down Enable */
-       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-       str r3, [r2]                        /* Store the passed value with AR disabled. */
-
-       ldr r1, VAL_TC_EMIFF_MRS            /* get MRS value */
-       ldr r2, REG_TC_EMIFF_MRS            /* Point to MRS register. */
-       str r1, [r2]                        /* Store the passed value.*/
-
-       ldr r2, REG_TC_EMIFF_SDRAM_CONFIG   /* Point to configuration register. */
-       str r0, [r2]                        /* Store the passed value. */
-
-       /*
-        * Delay for SDRAM initialization.
-        */
-       mov r3, #0x1800
-4:
-       subs r3, r3, #1                     /* Decrement count. */
-       bne 4b
-
-skip_sdram:
-
-       /* slow interface */
-       ldr r1, VAL_TC_EMIFS_CS0_CONFIG
-       ldr r0, REG_TC_EMIFS_CS0_CONFIG
-       str r1, [r0] /* Chip Select 0 */
-       ldr r1, VAL_TC_EMIFS_CS1_CONFIG
-       ldr r0, REG_TC_EMIFS_CS1_CONFIG
-       str r1, [r0] /* Chip Select 1 */
-       ldr r1, VAL_TC_EMIFS_CS2_CONFIG
-       ldr r0, REG_TC_EMIFS_CS2_CONFIG
-       str r1, [r0] /* Chip Select 2 */
-       ldr r1, VAL_TC_EMIFS_CS3_CONFIG
-       ldr r0, REG_TC_EMIFS_CS3_CONFIG
-       str r1, [r0] /* Chip Select 3 */
-
- /* Next, Enable the RS232 Line Drivers in the FPGA. */
- /* Also, power on the audio CODEC's amplifier here, */
- /* which will make a noise on the audio output. */
- /* This is done here instead of in the kernel so there */
- /* isn't a loud popping noise at the start of each */
- /* song. */
- /* Also, disable the CODEC's clocks. */
- /* omap1510-HelenP1 [specific] */
-
-       ldr r0, REG_FPGA_POWER
-       mov r1, #0
-       ldr r2, REG_FPGA_DIP_SWITCH
-       ldrb r3, [r2]
-       cmp r3, #0x8
-       movne r1, #0x62     /* Enable the RS232 Line Drivers in the EPLD */
-       strb r1, [r0]
-       ldr r0, REG_FPGA_AUDIO
-       mov r1, #0x0     /* Disable sound driver (CODEC clocks) */
-       strb r1, [r0]
-
-       /* back to arch calling code */
-       mov     pc, lr
-
-/* the literal pools origin */
-       .ltorg
-
-/* OMAP configuration registers */
-REG_FUNC_MUX_CTRL_0:           /* 32 bits */
-       .word 0xfffe1000
-REG_FUNC_MUX_CTRL_1:           /* 32 bits */
-       .word 0xfffe1004
-REG_FUNC_MUX_CTRL_2:           /* 32 bits */
-       .word 0xfffe1008
-REG_COMP_MODE_CTRL_0:          /* 32 bits */
-       .word 0xfffe100c
-REG_FUNC_MUX_CTRL_3:           /* 32 bits */
-       .word 0xfffe1010
-REG_FUNC_MUX_CTRL_4:           /* 32 bits */
-       .word 0xfffe1014
-REG_FUNC_MUX_CTRL_5:           /* 32 bits */
-       .word 0xfffe1018
-REG_FUNC_MUX_CTRL_6:           /* 32 bits */
-       .word 0xfffe101c
-REG_FUNC_MUX_CTRL_7:           /* 32 bits */
-       .word 0xfffe1020
-REG_FUNC_MUX_CTRL_8:           /* 32 bits */
-       .word 0xfffe1024
-REG_FUNC_MUX_CTRL_9:           /* 32 bits */
-       .word 0xfffe1028
-REG_FUNC_MUX_CTRL_A:           /* 32 bits */
-       .word 0xfffe102C
-REG_FUNC_MUX_CTRL_B:           /* 32 bits */
-       .word 0xfffe1030
-REG_FUNC_MUX_CTRL_C:           /* 32 bits */
-       .word 0xfffe1034
-REG_FUNC_MUX_CTRL_D:           /* 32 bits */
-       .word 0xfffe1038
-REG_PULL_DWN_CTRL_0:           /* 32 bits */
-       .word 0xfffe1040
-REG_PULL_DWN_CTRL_1:           /* 32 bits */
-       .word 0xfffe1044
-REG_PULL_DWN_CTRL_2:           /* 32 bits */
-       .word 0xfffe1048
-REG_PULL_DWN_CTRL_3:           /* 32 bits */
-       .word 0xfffe104c
-REG_VOLTAGE_CTRL_0:            /* 32 bits */
-       .word 0xfffe1060
-REG_TEST_DBG_CTRL_0:           /* 32 bits */
-       .word 0xfffe1070
-REG_MOD_CONF_CTRL_0:           /* 32 bits */
-       .word 0xfffe1080
-REG_TC_IMIF_PRIO:              /* 32 bits */
-       .word 0xfffecc00
-REG_TC_EMIFS_PRIO:             /* 32 bits */
-       .word 0xfffecc04
-REG_TC_EMIFF_PRIO:             /* 32 bits */
-       .word 0xfffecc08
-REG_TC_EMIFS_CONFIG:           /* 32 bits */
-       .word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:       /* 32 bits */
-       .word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:       /* 32 bits */
-       .word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:       /* 32 bits */
-       .word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:       /* 32 bits */
-       .word 0xfffecc1c
-REG_TC_EMIFF_SDRAM_CONFIG:     /* 32 bits */
-       .word 0xfffecc20
-REG_TC_EMIFF_MRS:              /* 32 bits */
-       .word 0xfffecc24
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:                 /* 16 bits */
-       .word 0xfffece00
-REG_ARM_IDLECT2:               /* 16 bits */
-       .word 0xfffece08
-REG_ARM_RSTCT2:                        /* 16 bits */
-       .word 0xfffece14
-REG_ARM_SYSST:                 /* 16 bits */
-       .word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:                 /* 16 bits */
-       .word 0xfffecf00
-/* identification code register */
-REG_IDCODE:                    /* 32 bits */
-       .word 0xfffed404
-
-/* Innovator specific */
-REG_FPGA_LED_DIGIT:            /* 8 bits (not used on Innovator) */
-       .word 0x08000003
-REG_FPGA_POWER:                        /* 8 bits */
-       .word 0x08000005
-REG_FPGA_AUDIO:                        /* 8 bits (not used on Innovator) */
-       .word 0x0800000c
-REG_FPGA_DIP_SWITCH:           /* 8 bits (not used on Innovator) */
-       .word 0x0800000e
-
-VAL_COMP_MODE_CTRL_0:
-       .word 0x0000eaef
-VAL_FUNC_MUX_CTRL_4:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_5:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_6:
-       .word 0x00000001
-VAL_FUNC_MUX_CTRL_7:
-       .word 0x00000000
-VAL_FUNC_MUX_CTRL_8:
-       .word 0x10001200
-VAL_FUNC_MUX_CTRL_9:
-       .word 0x01201012
-VAL_FUNC_MUX_CTRL_A:
-       .word 0x00000248
-VAL_FUNC_MUX_CTRL_B:
-       .word 0x00000248
-VAL_FUNC_MUX_CTRL_C:
-       .word 0x09000000
-VAL_FUNC_MUX_CTRL_D:
-       .word 0x00000000
-VAL_PULL_DWN_CTRL_0:
-       .word 0x11a10000
-VAL_PULL_DWN_CTRL_1:
-       .word 0x2e047fff
-VAL_PULL_DWN_CTRL_2:
-       .word 0xffd603a6
-VAL_PULL_DWN_CTRL_3:
-       .word 0x00003e03
-VAL_VOLTAGE_CTRL_0:
-       .word 0x00000007
-VAL_TEST_DBG_CTRL_0:
-       /*  See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
-        *   This slows down internal SRAM accesses.
-        */
-       .word 0x00000007
-VAL_MOD_CONF_CTRL_0:
-       .word 0x0b000008
-VAL_ARM_CKCTL:
-       .word 0x010f
-VAL_DPLL1_CTL:
-       .word 0x2710
-VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
-       .word 0x00001149
-VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
-       .word 0x00004158
-VAL_TC_EMIFS_CS0_CONFIG:
-       .word 0x002130b0
-VAL_TC_EMIFS_CS1_CONFIG:
-       .word 0x0000f559
-VAL_TC_EMIFS_CS2_CONFIG:
-       .word 0x000055f0
-VAL_TC_EMIFS_CS3_CONFIG:
-       .word 0x00003331
-VAL_TC_EMIFF_SDRAM_CONFIG:
-       .word 0x010290fc
-VAL_TC_EMIFF_MRS:
-       .word 0x00000027
diff --git a/board/ti/omap1510inn/omap1510innovator.c b/board/ti/omap1510inn/omap1510innovator.c
deleted file mode 100644 (file)
index a2a33a0..0000000
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void flash__init (void);
-static void ether__init (void);
-
-static inline void delay (unsigned long loops)
-{
-       __asm__ volatile ("1:\n"
-                         "subs %0, %1, #1\n"
-                         "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-       /* arch number of OMAP 1510-Board */
-       gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR;
-
-       /* adress of boot parameters */
-       gd->bd->bi_boot_params = 0x10000100;
-
-/* kk - this speeds up your boot a quite a bit.  However to make it
- *  work, you need make sure your kernel startup flush bug is fixed.
- *  ... rkw ...
- */
-       icache_enable ();
-
-       flash__init ();
-       ether__init ();
-       return 0;
-}
-
-
-int misc_init_r (void)
-{
-       /* volatile ushort *gdir = (ushort *) (GPIO_DIR_CONTROL_REG); */
-       /* volatile ushort *mdir = (ushort *) (MPUIO_DIR_CONTROL_REG); */
-
-       /* setup gpio direction to match board (no floats!) */
-       /**gdir = 0xCFF9; */
-       /**mdir = 0x103F; */
-
-       return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-static void flash__init (void)
-{
-#define CS0_CHIP_SELECT_REG 0xfffecc10
-#define CS3_CHIP_SELECT_REG 0xfffecc1c
-#define EMIFS_GlB_Config_REG 0xfffecc0c
-
-       {
-               unsigned int regval;
-
-               regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG);
-               regval = regval | 0x0001;       /* Turn off write protection for flash devices. */
-               if (regval & 0x0002) {
-                       regval = regval & 0xfffd;       /* Swap CS0 and CS3 so that flash is visible at 0x0 and eeprom at 0x0c000000. */
-                       /* If, instead, you want to reference flash at 0x0c000000, then it seemed the following were necessary. */
-                       /* *((volatile unsigned int *)CS0_CHIP_SELECT_REG) = 0x202090; / * Overrides head.S setting of 0x212090 */
-                       /* *((volatile unsigned int *)CS3_CHIP_SELECT_REG) = 0x202090; / * Let's flash chips be fully functional. */
-               }
-               *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval;
-       }
-}
-
-
-/******************************
- Routine:
- Description:
-******************************/
-static void ether__init (void)
-{
-#define ETH_CONTROL_REG 0x0800000b
-       /* take the Ethernet controller out of reset and wait
-        * for the EEPROM load to complete.
-        */
-       *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-       udelay (3);
-}
-
-
-int dram_init (void)
-{
-       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-       gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-       return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-       int rc = 0;
-#ifdef CONFIG_LAN91C96
-       rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
-       return rc;
-}
-#endif
index e6cc56e..7581a4c 100644 (file)
@@ -196,15 +196,18 @@ Active  arm         arm926ejs      mb86r0x     syteco          jadecpu
 Active  arm         arm926ejs      mx25        freescale       mx25pdk             mx25pdk                              mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg                                                                           Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mx25        karo            tx25                tx25                                 -                                                                                                                                 John Rigby <jcrigby@gmail.com>
 Active  arm         arm926ejs      mx25        syteco          zmx25               zmx25                                -                                                                                                                                 Matthias Weisser <weisserm@arcor.de>
+Active  arm         arm926ejs      mx27        armadeus        apf27               apf27                                -                                                                                                                                 Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org> 
 Active  arm         arm926ejs      mx27        logicpd         imx27lite           imx27lite                            -                                                                                                                                 Wolfgang Denk <wd@denx.de>
 Active  arm         arm926ejs      mx27        logicpd         imx27lite           magnesium                            -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      mxs         bluegiga        apx4devkit          apx4devkit                           apx4devkit                                                                                                                        Lauri Hintsala <lauri.hintsala@bluegiga.com>
+Active  arm         arm926ejs      mxs         creative        xfi3                xfi3                                 -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         denx            m28evk              m28evk                               m28evk                                                                                                                            Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         freescale       mx23evk             mx23evk                              mx23evk                                                                                                                           Otavio Salvador <otavio@ossystems.com.br>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk                              mx28evk:ENV_IS_IN_MMC                                                                                                             Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk_auart_console                mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC                                                                  Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         freescale       mx28evk             mx28evk_nand                         mx28evk:ENV_IS_IN_NAND                                                                                                            Fabio Estevam <fabio.estevam@freescale.com>
 Active  arm         arm926ejs      mxs         olimex          mx23_olinuxino      mx23_olinuxino                       mx23_olinuxino                                                                                                                    Marek Vasut <marek.vasut@gmail.com>
+Active  arm         arm926ejs      mxs         sandisk         sansa_fuze_plus     sansa_fuze_plus                      -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      mxs         schulercontrol  sc_sps_1            sc_sps_1                             -                                                                                                                                 Marek Vasut <marek.vasut@gmail.com>
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815                              -                                                                                                                                 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815_onenand                      nhk8815:BOOT_ONENAND                                                                                                              Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
@@ -1187,7 +1190,6 @@ Active  sparc       leon3          -           gaisler         -
 Active  x86         x86            coreboot    chromebook-x86  coreboot            coreboot-x86                         coreboot:SYS_TEXT_BASE=0x01110000                                                                                                 -
 Orphan  arm         arm1136        mx31        -               imx31_phycore       imx31_phycore_eet                    imx31_phycore:IMX31_PHYCORE_EET                                                                                                   (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 Orphan  arm         arm1136        mx31        freescale       -                   mx31ads                              -                                                                                                                                 (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
-Orphan  arm         arm925t        -           ti              -                   omap1510inn                          -                                                                                                                                 Kshitij Gupta <kshitij@ti.com>
 Orphan  arm         pxa            -           -               -                   lubbock                              -                                                                                                                                 (dead address) Kyle Harris <kharris@nexus-tech.net>
 Orphan  powerpc     74xx_7xx       -           -               evb64260            EVB64260                             EVB64260                                                                                                                          -
 Orphan  powerpc     74xx_7xx       -           -               evb64260            EVB64260_750CX                       EVB64260                                                                                                                          Eran Man <eran@nbase.co.il>
index 5d9e72f..2919bbf 100644 (file)
@@ -63,6 +63,11 @@ copy the binary by hand:
 Make sure the "elftosb" binary can be found in your $PATH, in this case this
 means "/usr/local/bin/" has to be in your $PATH.
 
+Install the 'libssl-dev' package as well. On a Debian-based distribution, this
+package can be installed as follows:
+
+       $ sudo apt-get install libssl-dev
+
 2) Compiling U-Boot for a MXS based board
 -------------------------------------------
 
index 87b1dfe..0f9a486 100644 (file)
@@ -11,7 +11,8 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-CANBT            powerpc     405CR          -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
+omap1510inn      arm         arm925t        -           -           Kshitij Gupta <kshitij@ti.com>
+CANBT            powerpc     405CR          fb8f4fd     2013-08-07  Matthias Fuchs <matthias.fuchs@esd.eu>
 Alaska8220       powerpc     mpc8220        d6ed322     2013-05-11
 Yukon8220        powerpc     mpc8220        d6ed322     2013-05-11
 sorcery          powerpc     mpc8220        d6ed322     2013-05-11
index f87e647..a7170b4 100644 (file)
@@ -518,6 +518,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
                return -1;
 
        mmc = malloc(sizeof(struct mmc));
+       if (!mmc)
+               return -ENOMEM;
 
        sprintf(mmc->name, "FSL_SDHC");
        regs = (struct fsl_esdhc *)cfg->esdhc_base;
index 378f8c5..036c113 100644 (file)
@@ -155,6 +155,9 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
 
                if (page_oob_size == 218)
                        return 16;
+
+               if (page_oob_size == 224)
+                       return 16;
        }
 
        return 0;
index 9bab71a..39240d9 100644 (file)
@@ -568,9 +568,14 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 static void cpsw_slave_update_link(struct cpsw_slave *slave,
                                   struct cpsw_priv *priv, int *link)
 {
-       struct phy_device *phy = priv->phydev;
+       struct phy_device *phy;
        u32 mac_control = 0;
 
+       phy = priv->phydev;
+
+       if (!phy)
+               return;
+
        phy_startup(phy);
        *link = phy->link;
 
@@ -947,6 +952,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
                        dev,
                        slave->data->phy_if);
 
+       if (!phydev)
+               return -1;
+
        phydev->supported &= supported;
        phydev->advertising = phydev->supported;
 
index 690e572..107cd6e 100644 (file)
@@ -453,7 +453,7 @@ static int fec_open(struct eth_device *edev)
         */
        writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
                &fec->eth->ecntrl);
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
        udelay(100);
        /*
         * setup the MII gasket for RMII mode
@@ -794,7 +794,7 @@ static int fec_recv(struct eth_device *dev)
        uint16_t bd_status;
        uint32_t addr, size, end;
        int i;
-       uchar buff[FEC_MAX_PKT_SIZE] __aligned(ARCH_DMA_MINALIGN);
+       ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
 
        /*
         * Check if any critical events have happened
index 4b4f8b7..0717cc6 100644 (file)
@@ -135,7 +135,7 @@ struct ethernet_regs {
 
        uint32_t res14[7];              /* MBAR_ETH + 0x2E4-2FC */
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
        uint16_t miigsk_cfgr;           /* MBAR_ETH + 0x300 */
        uint16_t res15[3];              /* MBAR_ETH + 0x302-306 */
        uint16_t miigsk_enr;            /* MBAR_ETH + 0x308 */
@@ -202,7 +202,7 @@ struct ethernet_regs {
 #define FEC_X_DES_ACTIVE_TDAR          0x01000000
 #define FEC_R_DES_ACTIVE_RDAR          0x01000000
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 /* defines for MIIGSK */
 /* RMII frequency control: 0=50MHz, 1=5MHz */
 #define MIIGSK_CFGR_FRCONT             (1 << 6)
index f054470..11b3d03 100644 (file)
@@ -13,6 +13,8 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
 COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
 COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c
new file mode 100644 (file)
index 0000000..36e9024
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+
+/**
+ * tps65217_reg_read() - Generic function that can read a TPS65217 register
+ * @src_reg:            Source register address
+ * @src_val:            Address of destination variable
+ * @return:             0 for success, not 0 on failure.
+ */
+int tps65217_reg_read(uchar src_reg, uchar *src_val)
+{
+       return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
+}
+
+/**
+ *  tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
+ *                        register or bit field regardless of protection
+ *                        level.
+ *
+ *  @prot_level:          Register password protection.  Use
+ *                        TPS65217_PROT_LEVEL_NONE,
+ *                        TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2
+ *  @dest_reg:            Register address to write.
+ *  @dest_val:            Value to write.
+ *  @mask:                Bit mask (8 bits) to be applied.  Function will only
+ *                        change bits that are set in the bit mask.
+ *
+ *  @return:              0 for success, not 0 on failure, as per the i2c API
+ */
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+                      uchar mask)
+{
+       uchar read_val;
+       uchar xor_reg;
+       int ret;
+
+       /*
+        * If we are affecting only a bit field, read dest_reg and apply the
+        * mask
+        */
+       if (mask != TPS65217_MASK_ALL_BITS) {
+               ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1);
+               if (ret)
+                       return ret;
+               read_val &= (~mask);
+               read_val |= (dest_val & mask);
+               dest_val = read_val;
+       }
+
+       if (prot_level > 0) {
+               xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
+               ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+                               &xor_reg, 1);
+               if (ret)
+                       return ret;
+       }
+
+       ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
+       if (ret)
+               return ret;
+
+       if (prot_level == TPS65217_PROT_LEVEL_2) {
+               ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+                               &xor_reg, 1);
+               if (ret)
+                       return ret;
+
+               ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+/**
+ * tps65217_voltage_update() - Function to change a voltage level, as this
+ *                            is a multi-step process.
+ * @dc_cntrl_reg:             DC voltage control register to change.
+ * @volt_sel:                 New value for the voltage register
+ * @return:                   0 for success, not 0 on failure.
+ */
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
+{
+       if ((dc_cntrl_reg != TPS65217_DEFDCDC1) &&
+           (dc_cntrl_reg != TPS65217_DEFDCDC2) &&
+           (dc_cntrl_reg != TPS65217_DEFDCDC3))
+               return 1;
+
+       /* set voltage level */
+       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
+                              TPS65217_MASK_ALL_BITS))
+               return 1;
+
+       /* set GO bit to initiate voltage transition */
+       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW,
+                              TPS65217_DCDC_GO, TPS65217_DCDC_GO))
+               return 1;
+
+       return 0;
+}
diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c
new file mode 100644 (file)
index 0000000..7ee1160
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <power/tps65910.h>
+
+/*
+ * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
+ *                             interface.
+ * @return:                   0 on success, not 0 on failure
+ */
+int tps65910_set_i2c_control(void)
+{
+       int ret;
+       uchar buf;
+
+       /* VDD1/2 voltage selection register access by control i/f */
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+                      &buf, 1);
+
+       if (ret)
+               return ret;
+
+       buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+       return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+                        &buf, 1);
+}
+
+/*
+ * tps65910_voltage_update() - Voltage switching for MPU frequency switching.
+ * @module:                   mpu - 0, core - 1
+ * @vddx_op_vol_sel:          vdd voltage to set
+ * @return:                   0 on success, not 0 on failure
+ */
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
+{
+       uchar buf;
+       unsigned int reg_offset;
+       int ret;
+
+       if (module == MPU)
+               reg_offset = TPS65910_VDD1_OP_REG;
+       else
+               reg_offset = TPS65910_VDD2_OP_REG;
+
+       /* Select VDDx OP   */
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       buf &= ~TPS65910_OP_REG_CMD_MASK;
+
+       ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       /* Configure VDDx OP  Voltage */
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       buf &= ~TPS65910_OP_REG_SEL_MASK;
+       buf |= vddx_op_vol_sel;
+
+       ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+               return 1;
+
+       return 0;
+}
index 3dc5d6a..41a8126 100644 (file)
@@ -267,7 +267,7 @@ static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
 /*
  * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error.
  */
-static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
+static int wait_until_txep_ready(struct usb_device *dev, u8 ep)
 {
        u16 csr;
        int timeout = CONFIG_MUSB_TIMEOUT;
@@ -299,7 +299,7 @@ static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
 /*
  * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error.
  */
-static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
+static int wait_until_rxep_ready(struct usb_device *dev, u8 ep)
 {
        u16 csr;
        int timeout = CONFIG_MUSB_TIMEOUT;
@@ -1009,7 +1009,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
                        writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr);
 
                        /* Wait until the TxPktRdy bit is cleared */
-                       if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) {
+                       if (wait_until_txep_ready(dev, MUSB_BULK_EP) != 1) {
                                readw(&musbr->txcsr);
                                usb_settoggle(dev, ep, dir_out,
                                (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1);
@@ -1044,7 +1044,7 @@ int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
                        writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
 
                        /* Wait until the RxPktRdy bit is set */
-                       if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) {
+                       if (wait_until_rxep_ready(dev, MUSB_BULK_EP) != 1) {
                                csr = readw(&musbr->rxcsr);
                                usb_settoggle(dev, ep, dir_out,
                                (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
@@ -1217,7 +1217,7 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe,
                        writew(csr | MUSB_RXCSR_H_REQPKT, &musbr->rxcsr);
 
                        /* Wait until the RxPktRdy bit is set */
-                       if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) {
+                       if (wait_until_rxep_ready(dev, MUSB_INTR_EP) != 1) {
                                csr = readw(&musbr->rxcsr);
                                usb_settoggle(dev, ep, dir_out,
                                (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1);
diff --git a/include/arm925t.h b/include/arm925t.h
deleted file mode 100644 (file)
index 3d767b3..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
-/************************************************
- * NAME            : arm925t.h
- * Version  : 23 June 2003                     *
- ************************************************/
-
-#ifndef __ARM925T_H__
-#define __ARM925T_H__
-
-void archflashwp(void *archdata, int wp);
-
-#endif /*__ARM925T_H__*/
index 8addf43..4d2a56d 100644 (file)
@@ -627,6 +627,8 @@ void ft_pci_setup(void *blob, bd_t *bd);
 #endif
 #endif
 
+void smp_set_core_boot_addr(unsigned long addr, int corenr);
+void smp_kick_all_cpus(void);
 
 /* $(CPU)/serial.c */
 int    serial_init   (void);
index 3de30fc..2f06ca2 100644 (file)
@@ -46,7 +46,7 @@
                "nandboot=echo Booting from nand ...; " \
                "run nandargs; " \
                "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
-               "bootm ${loadaddr}\0" \
+               "bootz ${loadaddr}\0" \
        "nandimgsize=0x500000\0"
 #else
 #define NANDARGS ""
@@ -61,8 +61,9 @@
        "fdt_high=0xffffffff\0" \
        "boot_fdt=try\0" \
        "rdaddr=0x81000000\0" \
+       "bootpart=0:2\0" \
        "bootdir=/boot\0" \
-       "bootfile=uImage\0" \
+       "bootfile=zImage\0" \
        "fdtfile=undefined\0" \
        "console=ttyO0,115200n8\0" \
        "optargs=\0" \
@@ -71,7 +72,6 @@
        "mmcdev=0\0" \
        "mmcroot=/dev/mmcblk0p2 ro\0" \
        "mmcrootfstype=ext4 rootwait\0" \
-       "bootpart=0:2\0" \
        "rootpath=/export/rootfs\0" \
        "nfsopts=nolock\0" \
        "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
                "root=${ramroot} " \
                "rootfstype=${ramrootfstype}\0" \
        "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
-       "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+       "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
        "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
        "mmcloados=run mmcargs; " \
                "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
                        "if run loadfdt; then " \
-                               "bootm ${loadaddr} - ${fdtaddr}; " \
+                               "bootz ${loadaddr} - ${fdtaddr}; " \
                        "else " \
                                "if test ${boot_fdt} = try; then " \
-                                       "bootm; " \
+                                       "bootz; " \
                                "else " \
                                        "echo WARN: Cannot load the DT; " \
                                "fi; " \
                        "fi; " \
                "else " \
-                       "bootm; " \
+                       "bootz; " \
                "fi;\0" \
        "mmcboot=mmc dev ${mmcdev}; " \
                "if mmc rescan; then " \
                                "echo Running uenvcmd ...;" \
                                "run uenvcmd;" \
                        "fi;" \
-                       "if run loaduimage; then " \
+                       "if run loadimage; then " \
                                "run mmcloados;" \
                        "fi;" \
                "fi;\0" \
                "run spiargs; " \
                "sf probe ${spibusno}:0; " \
                "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
-               "bootm ${loadaddr}\0" \
+               "bootz ${loadaddr}\0" \
        "netboot=echo Booting from network ...; " \
                "setenv autoload no; " \
                "dhcp; " \
                "tftp ${loadaddr} ${bootfile}; " \
                "tftp ${fdtaddr} ${fdtfile}; " \
                "run netargs; " \
-               "bootm ${loadaddr} - ${fdtaddr}\0" \
+               "bootz ${loadaddr} - ${fdtaddr}\0" \
        "ramboot=echo Booting from ramdisk ...; " \
                "run ramargs; " \
-               "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
+               "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
        "findfdt="\
                "if test $board_name = A335BONE; then " \
                        "setenv fdtfile am335x-bone.dtb; fi; " \
        "run mmcboot;" \
        "setenv mmcdev 1; " \
        "setenv bootpart 1:2; " \
+       "setenv mmcroot /dev/mmcblk1p2 ro; " \
        "run mmcboot;" \
        "run nandboot;"
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
 /* SPL */
 #ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 
 /* CPSW support */
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
new file mode 100644 (file)
index 0000000..e7e258f
--- /dev/null
@@ -0,0 +1,388 @@
+/*
+ *
+ * Configuration settings for the Armadeus Project motherboard APF27
+ *
+ * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_VERSION     10
+#define CONFIG_IDENT_STRING    " apf27 patch 3.10"
+#define CONFIG_BOARD_NAME apf27
+
+/*
+ * SoC configurations
+ */
+#define CONFIG_ARM926EJS               /* this is an ARM926EJS CPU */
+#define CONFIG_MX27                    /* in a Freescale i.MX27 Chip */
+#define CONFIG_MACH_TYPE       1698    /* APF27 */
+#define CONFIG_SYS_GENERIC_BOARD
+
+/*
+ * Enable the call to miscellaneous platform dependent initialization.
+ */
+#define CONFIG_SYS_NO_FLASH    /* to be define before <config_cmd_default.h> */
+
+/*
+ * Board display option
+ */
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET      "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT    "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE    2048
+#define CONFIG_SPL_TEXT_BASE    0xA0000000
+
+/* NAND boot config */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS    0x800
+#define CONFIG_SYS_NAND_U_BOOT_DST     CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_SIZE    CONFIG_SYS_MONITOR_LEN - 0x800
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+
+#define CONFIG_HOSTNAME        CONFIG_BOARD_NAME
+#define CONFIG_ROOTPATH        "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV      /* ask for env variable         */
+#define CONFIG_CMD_BSP         /* Board Specific functions     */
+#define CONFIG_CMD_CACHE       /* icache, dcache               */
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP                /* DHCP Support                 */
+#define CONFIG_CMD_DNS
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT         /* FAT support                  */
+#define CONFIG_CMD_IMX_FUSE    /* imx iim fuse                 */
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII         /* MII support                  */
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS    /* MTD partition support        */
+#define CONFIG_CMD_NAND                /* NAND support                 */
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_CMD_NFS         /* NFS support                  */
+#define CONFIG_CMD_PING                /* ping support                 */
+#define CONFIG_CMD_SETEXPR     /* setexpr support              */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+/*
+ * Memory configurations
+ */
+#define CONFIG_NR_DRAM_POPULATED 1
+#define CONFIG_NR_DRAM_BANKS   2
+
+#define ACFG_SDRAM_MBYTE_SYZE 64
+
+#define PHYS_SDRAM_1                   0xA0000000
+#define PHYS_SDRAM_2                   0xB0000000
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
+#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + (512<<10))
+#define CONFIG_SYS_MEMTEST_START       0xA0000000      /* memtest test area  */
+#define CONFIG_SYS_MEMTEST_END         0xA0300000      /* 3 MiB RAM test */
+
+#define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_SDRAM_BASE  \
+               + PHYS_SDRAM_1_SIZE - 0x0100000)
+
+#define CONFIG_SYS_TEXT_BASE           0xA0000800
+
+/*
+ * FLASH organization
+ */
+#define        ACFG_MONITOR_OFFSET             0x00000000
+#define        CONFIG_SYS_MONITOR_LEN          0x00100000      /* 1MiB */
+#define CONFIG_ENV_IS_IN_NAND
+#define        CONFIG_ENV_OVERWRITE
+#define        CONFIG_ENV_OFFSET               0x00100000      /* NAND offset */
+#define        CONFIG_ENV_SIZE                 0x00020000      /* 128kB  */
+#define CONFIG_ENV_RANGE               0X00080000      /* 512kB */
+#define        CONFIG_ENV_OFFSET_REDUND        \
+               (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)  /* +512kB */
+#define        CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE /* 512kB */
+#define        CONFIG_FIRMWARE_OFFSET          0x00200000
+#define        CONFIG_FIRMWARE_SIZE            0x00080000      /* 512kB  */
+#define        CONFIG_KERNEL_OFFSET            0x00300000
+#define        CONFIG_ROOTFS_OFFSET            0x00800000
+
+#define CONFIG_MTDMAP                  "mxc_nand.0"
+#define MTDIDS_DEFAULT                 "nand0=" CONFIG_MTDMAP
+#define MTDPARTS_DEFAULT       "mtdparts=" CONFIG_MTDMAP \
+                               ":1M(u-boot)ro," \
+                               "512K(env)," \
+                               "512K(env2)," \
+                               "512K(firmware)," \
+                               "512K(dtb)," \
+                               "5M(kernel)," \
+                               "-(rootfs)"
+
+/*
+ * U-Boot general configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT              "BIOS> "        /* prompt string */
+#define CONFIG_SYS_CBSIZE              2048            /* console I/O buffer */
+#define CONFIG_SYS_PBSIZE              \
+                               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+                                               /* Print buffer size */
+#define CONFIG_SYS_MAXARGS             16              /* max command args */
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+                                               /* Boot argument buffer size */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER                 /* enable the "hush" shell */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "    /* secondary prompt string */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_PREBOOT                 "run check_flash check_env;"
+
+
+/*
+ * Boot Linux
+ */
+#define CONFIG_CMDLINE_TAG             /* send commandline to Kernel   */
+#define CONFIG_SETUP_MEMORY_TAGS       /* send memory definition to kernel */
+#define CONFIG_INITRD_TAG              /* send initrd params   */
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BOOTDELAY       5
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define        CONFIG_BOOTFILE         __stringify(CONFIG_BOARD_NAME) "-linux.bin"
+#define CONFIG_BOOTARGS                "console=" __stringify(ACFG_CONSOLE_DEV) "," \
+                       __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
+                       " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
+
+#define ACFG_CONSOLE_DEV       ttySMX0
+#define CONFIG_BOOTCOMMAND     "run ubifsboot"
+#define CONFIG_SYS_AUTOLOAD    "no"
+/*
+ * Default load address for user programs and kernel
+ */
+#define CONFIG_LOADADDR                        0xA0000000
+#define        CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "env_version="          __stringify(CONFIG_ENV_VERSION)         "\0" \
+       "consoledev="           __stringify(ACFG_CONSOLE_DEV)           "\0" \
+       "mtdparts="             MTDPARTS_DEFAULT                        "\0" \
+       "partition=nand0,6\0"                                           \
+       "u-boot_addr="          __stringify(ACFG_MONITOR_OFFSET)        "\0" \
+       "env_addr="             __stringify(CONFIG_ENV_OFFSET)          "\0" \
+       "firmware_addr="        __stringify(CONFIG_FIRMWARE_OFFSET)     "\0" \
+       "firmware_size="        __stringify(CONFIG_FIRMWARE_SIZE)       "\0" \
+       "kernel_addr="          __stringify(CONFIG_KERNEL_OFFSET)       "\0" \
+       "rootfs_addr="          __stringify(CONFIG_ROOTFS_OFFSET)       "\0" \
+       "board_name="           __stringify(CONFIG_BOARD_NAME)          "\0" \
+       "kernel_addr_r=A0000000\0" \
+       "check_env=if test -n ${flash_env_version}; "                   \
+               "then env default env_version; "                        \
+               "else env set flash_env_version ${env_version}; env save; "\
+               "fi; "                                                  \
+               "if itest ${flash_env_version} < ${env_version}; then " \
+                       "echo \"*** Warning - Environment version"      \
+                       " change suggests: run flash_reset_env; reset\"; "\
+                       "env default flash_reset_env; "\
+               "fi; \0"                                                \
+       "check_flash=nand lock; nand unlock ${env_addr}; \0"    \
+       "flash_reset_env=env default -f -a; saveenv; run update_env;"   \
+               "echo Flash environment variables erased!\0"            \
+       "download_uboot=tftpboot ${loadaddr} ${board_name}"             \
+               "-u-boot-with-spl.bin\0"                                \
+       "flash_uboot=nand unlock ${u-boot_addr} ;"                      \
+               "nand erase.part u-boot;"               \
+               "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
+                       "then nand lock; nand unlock ${env_addr};"      \
+                               "echo Flashing of uboot succeed;"       \
+                       "else echo Flashing of uboot failed;"           \
+               "fi; \0"                                                \
+       "update_uboot=run download_uboot flash_uboot\0"                 \
+       "download_env=tftpboot ${loadaddr} ${board_name}"               \
+               "-u-boot-env.txt\0"                             \
+       "flash_env=env import -t ${loadaddr}; env save; \0"             \
+       "update_env=run download_env flash_env\0"                       \
+       "update_all=run update_env update_uboot\0"                      \
+       "unlock_regs=mw 10000008 0; mw 10020008 0\0"                    \
+
+/*
+ * Serial Driver
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_MXC_UART_BASE           UART1_BASE
+
+/*
+ * GPIO
+ */
+#define CONFIG_MXC_GPIO
+
+/*
+ * NOR
+ */
+
+/*
+ * NAND
+ */
+#define CONFIG_NAND_MXC
+
+#define CONFIG_MXC_NAND_REGS_BASE      0xD8000000
+#define CONFIG_SYS_NAND_BASE           CONFIG_MXC_NAND_REGS_BASE
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_NAND_PAGE_SIZE      2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT     CONFIG_SYS_NAND_BLOCK_SIZE / \
+                                               CONFIG_SYS_NAND_PAGE_SIZE
+#define CONFIG_SYS_NAND_SIZE           (256 * 1024 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  11
+#define NAND_MAX_CHIPS                 1
+
+#define CONFIG_FLASH_SHOW_PROGRESS     45
+#define CONFIG_SYS_NAND_QUIET          1
+
+/*
+ * Partitions & Filsystems
+ */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/*
+ * UBIFS
+ */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/*
+ * Ethernet (on SOC imx FEC)
+ */
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_MXC_PHYADDR         0x1f
+#define CONFIG_MII                             /* MII PHY management   */
+
+/*
+ * FPGA
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_FPGA
+#endif
+#define CONFIG_FPGA_COUNT              1
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
+#define CONFIG_SYS_FPGA_WAIT           250 /* 250 ms */
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_CHECK_CTRLC
+#define CONFIG_SYS_FPGA_CHECK_ERROR
+
+/*
+ * Fuses - IIM
+ */
+#ifdef CONFIG_CMD_IMX_FUSE
+#define IIM_MAC_BANK           0
+#define IIM_MAC_ROW            5
+#define IIM0_SCC_KEY           11
+#define IIM1_SUID              1
+#endif
+
+/*
+ * I2C
+ */
+
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE            IMX_I2C1_BASE
+#define CONFIG_SYS_I2C_SPEED           100000  /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_NOPROBES                { }
+
+#ifdef CONFIG_CMD_EEPROM
+# define CONFIG_SYS_I2C_EEPROM_ADDR    0x50    /* EEPROM 24LC02 */
+# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1      /* bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10      /* msec */
+#endif /* CONFIG_CMD_EEPROM */
+#endif /* CONFIG_CMD_I2C */
+
+/*
+ * SD/MMC
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MXC_MMC
+#define CONFIG_MXC_MCI_REGS_BASE       0x10014000
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_RTC_DS1374
+#define CONFIG_SYS_RTC_BUS_NUM         0
+#endif /* CONFIG_CMD_DATE */
+
+/*
+ * Clocks
+ */
+#define        CONFIG_SYS_HZ                   1000    /* Ticks per second */
+
+/*
+ * PLL
+ *
+ *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
+ *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
+ */
+#define CONFIG_MX27_CLK32              32768   /* 32768 or 32000 Hz crystal */
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
+#define PHYS_SDRAM_1_SIZE                      0x04000000 /* 64 MB */
+#define PHYS_SDRAM_2_SIZE                      0x04000000 /* 64 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 128)
+/* micron 128MB */
+#define PHYS_SDRAM_1_SIZE                      0x08000000 /* 128 MB */
+#define PHYS_SDRAM_2_SIZE                      0x08000000 /* 128 MB */
+#endif
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 256)
+/* micron 256MB */
+#define PHYS_SDRAM_1_SIZE                      0x10000000 /* 256 MB */
+#define PHYS_SDRAM_2_SIZE                      0x10000000 /* 256 MB */
+#endif
+
+#endif /* __CONFIG_H */
index 4fbe768..7b120de 100644 (file)
 
 #define CONFIG_DRA7XX
 
-#define CONFIG_ENV_IS_NOWHERE          /* For now. */
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         1       /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET              0xE0000
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_CMD_SAVEENV
 
 #define CONSOLEDEV                     "ttyO0"
 #define CONFIG_CONS_INDEX              1
index 68b225a..a25b20e 100644 (file)
@@ -23,7 +23,6 @@
 
 /* Set TEXT at the beginning of the NOR flash */
 #define CONFIG_SYS_TEXT_BASE   0xA0000000
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
index a3dd74a..3229bc7 100644 (file)
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 #define CONFIG_CONSOLE_DEV             "ttymxc0"
 #define CONFIG_MMCROOT                 "/dev/mmcblk1p2"
+#if defined(CONFIG_MX6Q)
 #define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabresd.dtb"
+#elif defined(CONFIG_MX6DL)
+#define CONFIG_DEFAULT_FDT_FILE        "imx6dl-sabresd.dtb"
+#endif
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 
 #include "mx6sabre_common.h"