static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div, post_div;
+ u32 pll_num, pll_denom;
+ u64 freq;
switch (pll) {
case PLL_ARM:
return infreq * (20 + div * 2);
case PLL_AUDIO:
div = __raw_readl(&anatop->pll_audio);
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
return infreq;
+
+ pll_num = __raw_readl(&anatop->pll_audio_num);
+ pll_denom = __raw_readl(&anatop->pll_audio_denom);
+
post_div = (div & BM_ANADIG_PLL_AUDIO_POST_DIV_SELECT) >>
BP_ANADIG_PLL_AUDIO_POST_DIV_SELECT;
+ if (post_div == 3) {
+ printf("Invalid post divider value for PLL_AUDIO\n");
+ return 0;
+ }
post_div = 1 << (2 - post_div);
div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
- return lldiv((u64)infreq * div, post_div);
+ freq = (u64)infreq * pll_num / pll_denom;
+ freq += infreq * div;
+ return lldiv(freq, post_div);
case PLL_VIDEO:
div = __raw_readl(&anatop->pll_video);
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
return infreq;
+
+ pll_num = __raw_readl(&anatop->pll_video_num);
+ pll_denom = __raw_readl(&anatop->pll_video_denom);
+
post_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ if (post_div == 3) {
+ printf("Invalid post divider value for PLL_VIDEO\n");
+ return 0;
+ }
post_div = 1 << (2 - post_div);
div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
- return lldiv((u64)infreq * div, post_div);
+ freq = (u64)infreq * pll_num / pll_denom;
+ freq += infreq * div;
+ return lldiv(freq, post_div);
case PLL_ENET:
div = __raw_readl(&anatop->pll_enet);
if (div & BM_ANADIG_PLL_ENET_BYPASS)
div = __raw_readl(&anatop->pll_mlb);
if (div & BM_ANADIG_PLL_MLB_BYPASS)
return infreq;
- /* unknown external clock provided on MLB_CLK pin */
+ /* fallthru: unknown external clock provided on MLB_CLK pin */
+ default:
return 0;
}
- return 0;
+ /* NOTREACHED */
}
static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
return root_freq / (emi_slow_podf + 1);
}
-static u32 get_nfc_clk(void)
+static inline unsigned long get_nfc_root_clk(int nfc_clk_sel)
{
- u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
- u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
- MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
- u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
- MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
- int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
- MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
- u32 root_freq;
-
switch (nfc_clk_sel) {
case 0:
- root_freq = mxc_get_pll_pfd(PLL_528, 0);
+ return mxc_get_pll_pfd(PLL_528, 0);
break;
case 1:
- root_freq = decode_pll(PLL_528, MXC_HCLK);
+ return decode_pll(PLL_528, MXC_HCLK);
break;
case 2:
- root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ return decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 3:
- root_freq = mxc_get_pll_pfd(PLL_528, 2);
+ return mxc_get_pll_pfd(PLL_528, 2);
break;
case 4:
- root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
- break;
+ return mxc_get_pll_pfd(PLL_USBOTG, 3);
default:
return 0;
}
+}
+
+static u32 get_nfc_clk(void)
+{
+ u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
+ u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >>
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
+ u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >>
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
+ int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
+ u32 root_freq = get_nfc_root_clk(nfc_clk_sel);
return root_freq / (pred + 1) / (podf + 1);
}
u32 min_err = ~0;
u32 nfc_val = ~0;
u32 freq = freq_khz * 1000;
+ int num_sel = is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) ? 5 : 4;
- for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
+ for (nfc_clk_sel = 0; nfc_clk_sel < num_sel; nfc_clk_sel++) {
u32 act_freq;
u32 err;
- if (ref < 4 && ref != nfc_clk_sel)
+ if (ref < num_sel && ref != nfc_clk_sel)
continue;
switch (nfc_clk_sel) {
case 3:
root_freq = mxc_get_pll_pfd(PLL_528, 2);
break;
+ case 4:
+ root_freq = mxc_get_pll_pfd(PLL_USBOTG, 3);
+ break;
}
if (root_freq < freq)
continue;
podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
act_freq = root_freq / pred / podf;
- err = (freq - act_freq) * 100 / freq;
+ err = (freq - act_freq) / (freq / 1000);
debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
if (act_freq > freq)
}
}
- if (nfc_val == ~0 || min_err > 10)
+ if (nfc_val == ~0 || min_err > 100)
return -EINVAL;
if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
(cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_io_clk(nfc_val);
+#else
__raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
&imx_ccm->cs2cdr);
+#endif
} else {
debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
}
select SOC_MX6UL
select SYS_SDRAM_BUS_WIDTH_16
+config TX6QP
+ bool
+
#
# variables selected depending on module variant
#
config SYS_SDRAM_BUS_WIDTH_32
bool
+config SYS_SDRAM_CHIP_SIZE
+ int "SDRAM chip size in MiB"
+
choice
prompt "TX6 module variant"
select SYS_I2C_MXC
select TX6_EMMC
-config TARGET_TX6Q_1033
- bool "TX6Q-1033"
+config TARGET_TX6Q_1036
+ bool "TX6Q-1036"
select SOC_MX6Q
select SYS_I2C
select SYS_I2C_MXC
select TX6UL
select TX6_EMMC
+config TARGET_TX6QP_8037
+ bool "TX6QP-8037"
+ select SOC_MX6Q
+ select SYS_I2C
+ select SYS_I2C_MXC
+ select TX6_EMMC
+ select TX6QP
+
endchoice
choice
#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
#ifdef PHYS_SDRAM_2_SIZE
-#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
+#define SDRAM_SIZE ((PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) / SZ_1M)
#else
-#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
+#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE / SZ_1M)
#endif
+#define BIT(x) (1 << (x))
+#define CCGR(m) (3 << ((m) * 2))
+
#define CPU_2_BE_32(l) \
((((l) << 24) & 0xFF000000) | \
(((l) << 8) & 0x00FF0000) | \
(((l) >> 8) & 0x0000FF00) | \
(((l) >> 24) & 0x000000FF))
+#ifndef CONFIG_TX6QP
#define CHECK_DCD_ADDR(a) ( \
((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
+#else
+#define CHECK_DCD_ADDR(a) ( \
+ ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
+ ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
+ ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
+ ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
+ ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
+ ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
+ ((a) >= 0x021B8000 && (a) <= 0x021BBFFF) /* EIM registers */ || \
+ ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */ || \
+ ((a) >= 0x00BB0000 && (a) <= 0x00BB003F) /* NoC DDR config */)
+#endif
.macro mxc_dcd_item addr, val
.ifne CHECK_DCD_ADDR(\addr)
#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
+#define NS_TO_CK100(ns) DIV_ROUND_UP(NS_TO_CK(ns), 100)
#define PS_TO_CK(ps) DIV_ROUND_UP(NS_TO_CK(ps), 1000)
.macro CK_VAL, name, clks, offs, max
#error SDRAM clock out of range: 303 .. 800
#endif
+#if SDRAM_SIZE < 2048
+#define ROW_ADDR_BITS 14
+#define COL_ADDR_BITS 10
+
/* MDCFG0 0x0c */
NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
/* MDOR 0x30 */
CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#else
+/* 4096MiB SDRAM: IM4G16D3EABG-125I */
+#define ROW_ADDR_BITS 15
+#define COL_ADDR_BITS 10
+
+/* MDCFG0 0x0c */
+NS_VAL tRFC, 260, 1, 255 /* clks - 1 (0..255) */
+CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP, NS_TO_CK(6), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
+CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
+NS_VAL tFAW, 30, 1, 31 /* clks - 1 (0..31) */
+CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
+
+/* MDCFG1 0x10 */
+CK_VAL tRCD, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
+CK_VAL tRP, NS_TO_CK100(1375), 1, 7 /* clks - 1 (0..7) */ /* 13.75 */
+CK_VAL tRC, NS_TO_CK100(4875), 1, 31 /* clks - 1 (0..31) */ /* 48.75 */
+CK_VAL tRAS, NS_TO_CK(35), 1, 31 /* clks - 1 (0..31) */ /* 35 */
+CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
+NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
+CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
+
+/* MDCFG2 0x14 */
+CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
+CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tRRD, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+
+/* MDOR 0x30 */
+CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
+#endif
+
#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
(PWDT << 8) \
)
-#define ROW_ADDR_BITS 14
-#define COL_ADDR_BITS 10
-
#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
#define DLL_DISABLE 0
#define MMDC1_MDOR 0x021b0030
#define MMDC1_MDASP 0x021b0040
+#define MMDC1_MAARCR 0x021b0400
#define MMDC1_MAPSR 0x021b0404
+#define MMDC1_MADPCR0 0x021b0410
#define MMDC1_MPZQHWCTRL 0x021b0800
#define MMDC1_MPWLGCR 0x021b0808
#endif
#ifdef CONFIG_SOC_MX6Q
+#define IOMUXC_GPR0 0x020e0000
#define IOMUXC_GPR1 0x020e0004
+#define IOMUXC_GPR2 0x020e0008
+#define IOMUXC_GPR3 0x020e000c
+#define IOMUXC_GPR4 0x020e0010
+#define IOMUXC_GPR5 0x020e0014
+#define IOMUXC_GPR6 0x020e0018
+#define IOMUXC_GPR7 0x020e001c
+#define IOMUXC_GPR8 0x020e0020
+#define IOMUXC_GPR9 0x020e0024
+#define IOMUXC_GPR10 0x020e0028
+#define IOMUXC_GPR11 0x020e002c
+#define IOMUXC_GPR12 0x020e0030
+#define IOMUXC_GPR13 0x020e0034
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x020e00a0
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4
#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4
/* RESET_OUT GPIO_7_12 */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0)
-
+#ifndef CONFIG_TX6_EMMC
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+#ifndef CONFIG_TX6QP
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
-
+#else
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x007236c1 */
+#endif
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+#endif
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 (0x00029148) */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 (0x00029148) */
MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
/* enable all relevant clocks... */
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
-#define CCGR(m) (3 << ((m) * 2))
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
- MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
+ MXC_DCD_ITEM(0x020c80a0, 0x00082029) /* set video PLL to 498MHz */
MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
/* IOMUX: */
MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
+#ifdef CONFIG_TX6QP
+ /* enable AXI cache for VDOA/VPU/IPU */
+ MXC_DCD_ITEM(IOMUXC_GPR4, 0xf00000cf)
+ /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+ MXC_DCD_ITEM(IOMUXC_GPR6, 0x77177717)
+ MXC_DCD_ITEM(IOMUXC_GPR7, 0x77177717)
+#endif
/* UART1 pad config */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */
/* DDR3 calibration */
MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
+#ifdef CONFIG_TX6QP
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+ MXC_DCD_ITEM(MMDC1_MAARCR, BIT(25)) /* MMDC reorder disable BOOT_CFG3[5:4] */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+#endif
MXC_DCD_ITEM(MMDC1_MAPSR, 1)
#ifdef DO_DDR_CALIB
#include "pmic.h"
+#ifdef CONFIG_SYS_I2C
static struct {
uchar addr;
pmic_setup_func *init;
+ const char *name;
} i2c_addrs[] = {
#ifdef CONFIG_LTC3676
- { 0x3c, ltc3676_pmic_setup, },
+ { 0x3c, ltc3676_pmic_setup, "LTC3676", },
#endif
#ifdef CONFIG_RN5T618
- { 0x32, rn5t618_pmic_setup, },
+ { 0x32, rn5t618_pmic_setup, "RN5T618", },
#endif
#ifdef CONFIG_RN5T567
- { 0x33, rn5t567_pmic_setup, },
+ { 0x33, rn5t567_pmic_setup, "RN5T567", },
#endif
};
int ret = -ENODEV;
int i;
+ printf("PMIC: ");
+
debug("Probing for I2C dev 0x%02x\n", addr);
for (i = 0; i < ARRAY_SIZE(i2c_addrs); i++) {
u8 i2c_addr = i2c_addrs[i].addr;
break;
}
}
+ printf("%s\n", i == ARRAY_SIZE(i2c_addrs) ? "N/A" : i2c_addrs[i].name);
return ret;
}
+#else
+int tx6_pmic_init(int addr, struct pmic_regs *regs, size_t num_regs)
+{
+ printf("PMIC: N/A\n");
+ return 0;
+}
+#endif
u32 cpurev = get_cpu_rev();
char *cpu_str = "?";
- switch ((cpurev >> 12) & 0xff) {
- case MXC_CPU_MX6SL:
+ if (is_cpu_type(MXC_CPU_MX6SL)) {
cpu_str = "SL";
tx6_mod_suffix = "?";
- break;
- case MXC_CPU_MX6DL:
+ } else if (is_cpu_type(MXC_CPU_MX6DL)) {
cpu_str = "DL";
tx6_mod_suffix = "U";
- break;
- case MXC_CPU_MX6SOLO:
+ } else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
cpu_str = "SOLO";
tx6_mod_suffix = "S";
- break;
- case MXC_CPU_MX6Q:
+ } else if (is_cpu_type(MXC_CPU_MX6Q)) {
cpu_str = "Q";
tx6_mod_suffix = "Q";
- break;
+ } else if (is_cpu_type(MXC_CPU_MX6QP)) {
+ cpu_str = "QP";
+ tx6_mod_suffix = "QP";
}
printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
#define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
static char tx6_mem_table[] = {
- '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
- '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
- '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
- '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
- '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
- '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
- '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
- '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
- '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
- '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
- '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
- '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
+ '4', /* TX6S-8034 256MiB SDRAM 16bit; 128MiB NAND */
+ '1', /* TX6U-8011 512MiB SDRAM 32bit; 128MiB NAND */
+ '0', /* TX6Q-1030/TX6U-8030 1GiB SDRAM 64bit; 128MiB NAND */
+ '?', /* N/A 256MiB SDRAM 16bit; 256MiB NAND */
+ '?', /* N/A 512MiB SDRAM 32bit; 256MiB NAND */
+ '2', /* TX6U-8012 1GiB SDRAM 64bit; 256MiB NAND */
+ '?', /* N/A 256MiB SDRAM 16bit; 4GiB eMMC */
+ '5', /* TX6S-8035 512MiB SDRAM 32bit; 4GiB eMMC */
+ '3', /* TX6U-8033 1GiB SDRAM 64bit; 4GiB eMMC */
+ '?', /* N/A 256MiB SDRAM 16bit; 8GiB eMMC */
+ '?', /* N/A 512MiB SDRAM 32bit; 8GiB eMMC */
+#if defined(CONFIG_TX6_REV) && CONFIG_TX6_REV == 2
+ '0', /* TX6Q-1020 (legacy) 1GiB SDRAM 64bit; 8GiB eMMC */
+#else
+ '6', /* TX6Q-1036 1GiB SDRAM 64bit; 8GiB eMMC */
+#endif
};
static struct {
if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
return '?';
-
+ if (CONFIG_SYS_SDRAM_CHIP_SIZE > 512)
+ return '7';
+ if (mem_idx == 8)
+ return is_cpu_type(MXC_CPU_MX6Q) ? '6' : '3';
return tx6_mem_table[mem_idx];
};
int board_init(void)
{
int ret;
- u32 cpurev = get_cpu_rev();
- int cpu_variant = (cpurev >> 12) & 0xff;
int pmic_id;
debug("%s@%d: \n", __func__, __LINE__);
printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
tx6_mod_suffix,
- cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
+ is_cpu_type(MXC_CPU_MX6Q) ? 1 : 8,
is_lvds(), tx6_get_mod_rev(pmic_id),
tx6_mem_suffix());
void dram_init_banksize(void)
{
- debug("%s@%d: \n", __func__, __LINE__);
-
+ debug("%s@%d: chip_size=%u (%u bit bus width)\n", __func__, __LINE__,
+ CONFIG_SYS_SDRAM_CHIP_SIZE, CONFIG_SYS_SDRAM_BUS_WIDTH);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
if (!lcd_enabled) {
debug("LCD disabled\n");
+ goto disable;
return;
}
debug("Disabling LCD\n");
lcd_enabled = 0;
setenv("splashimage", NULL);
+ goto disable;
return;
}
if (video_mode == NULL) {
debug("Disabling LCD\n");
lcd_enabled = 0;
+ goto disable;
return;
}
vm = video_mode;
fb_mode.xres, fb_mode.yres,
panel_info.vl_col, panel_info.vl_row);
lcd_enabled = 0;
+ goto disable;
return;
}
}
printf(" %s", p->name);
}
printf("\n");
+ goto disable;
return;
}
if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
lcd_enabled = 0;
+ goto disable;
return;
}
panel_info.vl_col = p->xres;
lcd_enabled = 0;
printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
lcd_bus_width);
+ goto disable;
return;
}
if (is_lvds()) {
if (lvds_chan_mask == 0) {
printf("No LVDS channel active\n");
lcd_enabled = 0;
+ goto disable;
return;
}
} else {
debug("Skipping initialization of LCD controller\n");
}
+ return;
+
+disable:
+ lcd_enabled = 0;
+ panel_info.vl_col = 0;
+ panel_info.vl_row = 0;
+
}
#else
#define lcd_enabled 0
#define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
#define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
+#ifdef CONFIG_SYS_I2C_SOFT
#define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
#define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
+#endif
#define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
};
static const struct gpio const tx6ul_gpios[] = {
+#ifdef CONFIG_SYS_I2C_SOFT
/* These two entries are used to forcefully reinitialize the I2C bus */
{ TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
{ TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
-
+#endif
{ TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
{ TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
{ TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
#define GPIO_PSR 8
/* run with default environment */
+#if defined(TX6UL_I2C1_SCL_GPIO) && defined(TX6UL_I2C1_SDA_GPIO)
static void tx6_i2c_recover(void)
{
int i;
}
}
}
+#else
+static inline void tx6_i2c_recover(void)
+{
+}
+#endif
/* placed in section '.data' to prevent overwriting relocation info
* overlayed with bss
u32 cpurev = get_cpu_rev();
char *cpu_str = "?";
- switch ((cpurev >> 12) & 0xff) {
- case MXC_CPU_MX6SL:
+ if (is_cpu_type(MXC_CPU_MX6SL))
cpu_str = "SL";
- break;
- case MXC_CPU_MX6DL:
+ else if (is_cpu_type(MXC_CPU_MX6DL))
cpu_str = "DL";
- break;
- case MXC_CPU_MX6SOLO:
+ else if (is_cpu_type(MXC_CPU_MX6SOLO))
cpu_str = "SOLO";
- break;
- case MXC_CPU_MX6Q:
+ else if (is_cpu_type(MXC_CPU_MX6Q))
cpu_str = "Q";
- break;
- case MXC_CPU_MX6UL:
+ else if (is_cpu_type(MXC_CPU_MX6UL))
cpu_str = "UL";
- break;
- }
printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
cpu_str,
#endif
}
+#ifdef CONFIG_RN5T567
/* PMIC settings */
#define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
#define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
};
static int pmic_addr __maybe_unused = 0x33;
+#endif
int board_init(void)
{
int ret;
+ u32 cpurev = get_cpu_rev();
debug("%s@%d: \n", __func__, __LINE__);
- printf("Board: Ka-Ro TXUL-001%c\n",
+ printf("Board: Ka-Ro TXUL-%c01%c\n",
+ ((cpurev &0xff) > 0x10) ? '5' : '0',
tx6ul_mem_suffix());
get_hab_status();
}
return 0;
}
-#endif /* CONFIG_CMD_MMC */
+#endif /* CONFIG_FSL_ESDHC */
enum {
LED_STATE_INIT = -1,
#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
#endif
+#define CCGR(m) (3 << ((m) * 2))
+
#define CPU_2_BE_32(l) \
((((l) << 24) & 0xFF000000) | \
(((l) << 8) & 0x00FF0000) | \
/* ETN PHY Power */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0)
+#ifndef CONFIG_TX6_EMMC
+ /* switch NFC clock to 99MHz */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14))
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7))
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+#endif
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
-#define CCGR(m) (3 << ((m) * 2))
+
/* enable all relevant clocks... */
MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
/* enable UART clock depending on selected console port */
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TX6_UBOOT_MFG=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TX6_UBOOT_NOENV=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,SECURE_BOOT"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_TX6=y
+CONFIG_TARGET_TX6Q_1036=y
+CONFIG_TX6_UBOOT=y
+CONFIG_BOOTP_DNS=y
+CONFIG_BOOTP_GATEWAY=y
+CONFIG_BOOTP_SUBNETMASK=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_BOOTCE=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_DOS_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_MXC_PHYADDR=0
+CONFIG_IMX_WATCHDOG=y
+CONFIG_LCD=y
+CONFIG_NET=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY_SMSC=y
+CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1033=y
+CONFIG_TARGET_TX6QP_8037=y
CONFIG_TX6_UBOOT=y
CONFIG_BOOTP_DNS=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_PROMPT="TX6QP U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1033=y
+CONFIG_TARGET_TX6QP_8037=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_BOOTP_DNS=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_PROMPT="TX6QP U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1033=y
+CONFIG_TARGET_TX6QP_8037=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_BOOTP_DNS=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_PROMPT="TX6QP U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
-CONFIG_TARGET_TX6Q_1033=y
+CONFIG_TARGET_TX6QP_8037=y
CONFIG_TX6_UBOOT=y
CONFIG_BOOTP_DNS=y
CONFIG_BOOTP_GATEWAY=y
CONFIG_NET=y
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
-CONFIG_SYS_PROMPT="TX6Q U-Boot > "
+CONFIG_SYS_PROMPT="TX6QP U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=1024
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6S U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6DL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
CONFIG_NETDEVICES=y
CONFIG_PHY_SMSC=y
CONFIG_SYS_PROMPT="TX6UL U-Boot > "
+CONFIG_SYS_SDRAM_CHIP_SIZE=512
#define BF(value, field) (((value) << BO_##field) & BM_##field)
#define WRITE_POSTAMBLE_US 2
+#define MXC_OTP_BUSY_TIMEOUT 1000
-static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
+static bool wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
{
- while (readl(®s->ctrl) & BM_CTRL_BUSY)
+ unsigned long start;
+ u32 reg;
+
+ start = get_timer_masked();
+ while ((reg = readl(®s->ctrl)) & BM_CTRL_BUSY) {
udelay(delay_us);
+ if (get_timer(start) > MXC_OTP_BUSY_TIMEOUT)
+ break;
+ }
+ if (!(reg & BM_CTRL_BUSY))
+ return 1;
+ return !(readl(®s->ctrl) & BM_CTRL_BUSY);
}
static void clear_error(struct ocotp_regs *regs)
enable_ocotp_clk(1);
- wait_busy(*regs, 1);
- clear_error(*regs);
+ if (wait_busy(*regs, 1))
+ clear_error(*regs);
+ else
+ return -ETIMEDOUT;
return 0;
}
setup_direct_access(regs, bank, word, false);
writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl);
- wait_busy(regs, 1);
- *val = readl(®s->read_fuse_data);
+ if (wait_busy(regs, 1))
+ *val = readl(®s->read_fuse_data);
+ else
+ *val = ~0;
return finish_access(regs, __func__);
}
*/
static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
{
- uint32_t size;
+ size_t rbd_size, pkt_size;
void *data;
int i;
* Reload the RX descriptors with default values and wipe
* the RX buffers.
*/
- size = roundup(dsize, ARCH_DMA_MINALIGN);
+ pkt_size = roundup(dsize, ARCH_DMA_MINALIGN);
for (i = 0; i < count; i++) {
data = (void *)fec->rbd_base[i].data_pointer;
memset(data, 0, dsize);
flush_dcache_range((unsigned long)data,
- (unsigned long)data + size);
+ (unsigned long)data + pkt_size);
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
fec->rbd_index = 0;
+ rbd_size = roundup(sizeof(struct fec_bd) * count, ARCH_DMA_MINALIGN);
flush_dcache_range((unsigned long)fec->rbd_base,
- (unsigned long)fec->rbd_base + size);
+ (unsigned long)fec->rbd_base + rbd_size);
}
/**
static int fec_alloc_descs(struct fec_priv *fec)
{
- unsigned int size;
+ size_t tbd_size, rbd_size, pkt_size;
int i;
void *data;
/* Allocate TX descriptors. */
- size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
- fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ tbd_size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ fec->tbd_base = memalign(ARCH_DMA_MINALIGN, tbd_size);
if (!fec->tbd_base)
goto err_tx;
/* Allocate RX descriptors. */
- size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
- fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
+ rbd_size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
+ fec->rbd_base = memalign(ARCH_DMA_MINALIGN, rbd_size);
if (!fec->rbd_base)
goto err_rx;
- memset(fec->rbd_base, 0, size);
+ memset(fec->rbd_base, 0, rbd_size);
/* Allocate RX buffers. */
/* Maximum RX buffer size. */
- size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
+ pkt_size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
for (i = 0; i < FEC_RBD_NUM; i++) {
- data = memalign(FEC_DMA_RX_MINALIGN, size);
+ data = memalign(FEC_DMA_RX_MINALIGN, pkt_size);
if (!data) {
printf("%s: error allocating rxbuf %d\n", __func__, i);
goto err_ring;
}
- memset(data, 0, size);
+ memset(data, 0, pkt_size);
fec->rbd_base[i].data_pointer = (uint32_t)data;
fec->rbd_base[i].status = FEC_RBD_EMPTY;
fec->rbd_base[i].data_length = 0;
/* Flush the buffer to memory. */
- flush_dcache_range((unsigned long)data,
- (unsigned long)data + size);
+ flush_dcache_range((uint32_t)data, (uint32_t)data + pkt_size);
}
/* Mark the last RBD to close the ring. */
fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
+ flush_dcache_range((unsigned long)fec->rbd_base, rbd_size);
fec->rbd_index = 0;
fec->tbd_index = 0;
#define CONFIG_SYS_SDRAM_BUS_WIDTH 64
#endif
#endif /* CONFIG_SYS_SDRAM_BUS_WIDTH */
-#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH)
+#ifdef __ASSEMBLY__
+#define _AC(x,s) x
+#else
+#define _AC(x,s) (x##s)
+#endif
+#define UL(x) _AC(x,UL)
+#define PHYS_SDRAM_1_SIZE (UL(CONFIG_SYS_SDRAM_CHIP_SIZE) * SZ_1M \
+ / 32 * CONFIG_SYS_SDRAM_BUS_WIDTH)
+#if PHYS_SDRAM_1_SIZE > SZ_1G
+#define FDT_HIGH_STR "fdt_high=ffffffff\0"
+#else
+#define FDT_HIGH_STR ""
+#endif
+
#ifdef CONFIG_SOC_MX6Q
#define CONFIG_SYS_SDRAM_CLK 528
#else
EMMC_BOOT_PART_STR \
EMMC_BOOT_ACK_STR \
"fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \
- CONFIG_SYS_FDTSAVE_CMD \
+ FDT_HIGH_STR \
+ FDTSAVE_CMD_STR \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"nfsroot=/tftpboot/rootfs\0" \
#define CONFIG_SYS_DEFAULT_BOOT_MODE "nand"
#define CONFIG_SYS_BOOT_CMD_NAND \
"bootcmd_nand=setenv autostart no;run bootargs_ubifs;nboot linux\0"
-#define CONFIG_SYS_FDTSAVE_CMD \
+#define FDTSAVE_CMD_STR \
"fdtsave=fdt resize;nand erase.part dtb" \
";nand write ${fdtaddr} dtb ${fdtsize}\0"
#define MTD_NAME "gpmi-nand"
#define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SYS_BOOT_CMD_NAND ""
-#define CONFIG_SYS_FDTSAVE_CMD \
+#define FDTSAVE_CMD_STR \
"fdtsave=mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} ${emmc_boot_part}" \
";mmc write ${fdtaddr} " xstr(CONFIG_SYS_DTB_BLKNO) " 80" \
";mmc partconf 0 ${emmc_boot_ack} ${emmc_boot_part} 0\0"
#else /* CONFIG_TX6_REV */
/* autodetect which PMIC is present to derive TX6_REV */
#ifdef CONFIG_SOC_MX6UL
+#ifndef CONFIG_TX6_UBOOT_NOENV
+/* NOENV U-Boot is used for initial bootstrap.
+ * Since the TAMPER_PIN_DISABLE fuses have to be programmed
+ * to be able to use the TAMPER pins as GPIO to access the
+ * PMIC I2C bus, this is not possible on virgin hardware.
+ */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C_SOFT_SPEED 400000
#define CONFIG_SOFT_I2C_GPIO_SCL IMX_GPIO_NR(5, 0)
#define CONFIG_SOFT_I2C_GPIO_SDA IMX_GPIO_NR(5, 1)
#define CONFIG_SOFT_I2C_READ_REPEATED_START
-#else
+#endif /* CONFIG_TX6_UBOOT_NOENV */
+#else /* !CONFIG_SOC_MX6UL */
#define CONFIG_LTC3676 /* TX6_REV == 1 */
-#endif
+#endif /* CONFIG_SOC_MX6UL */
#define CONFIG_RN5T567 /* TX6_REV == 3 */
#endif /* CONFIG_TX6_REV */
projects / karo-tx-uboot.git / commitdiff