karo: tx6: don't perform DQS gating calibration

DQS Gating calibration may yield incorrect results due to a bug in the
ROM code. Also preset all relevant timing registers to sane values
before doing the DDR calibration.

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 599911382060b55fd38006d91414e6dd0696a69a..02afb607d811cae49b8cf8c21e55aed270043f01 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -446,8 +446,6 @@ ivt_end:
 #define MMDC1_MPMUR0                           0x021b08b8
 
 #if PHYS_SDRAM_1_WIDTH == 64
-#define MMDC2_MDPDC                            0x021b4004
-
 #define MMDC2_MPWLGCR                          0x021b4808
 #define MMDC2_MPWLDECTRL0                      0x021b480c
 #define MMDC2_MPWLDECTRL1                      0x021b4810
@@ -860,8 +858,41 @@ dcd_hdr:
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
+#endif
+#if PHYS_SDRAM_1_WIDTH > 16
+#define DO_DDR_CALIB
 #endif
        /* SDRAM initialization */
+#define WL_DLY_DQS_VAL 30
+#define WL_DLY_DQS0    (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS1    (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS2    (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS3    (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS4    (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS5    (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
+#define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
+
+       /* ZQ calibration */
+       MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
+       MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
+       MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
+
+       MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
+       MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
+       MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
+       MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
+
+       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x43240334)
+       MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x0324031a)
+       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x43340344)
+       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x03280276)
+
+       MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+       MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+       MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
+       MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
+
        /* MPRDDQBY[0..7]DL */
        MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
        MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
@@ -871,6 +902,9 @@ dcd_hdr:
        MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
        MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
        MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
+#define MPMUR_FRC_MSR  (1 << 11)
+       MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
+       MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
        /* MDMISC */
        MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
@@ -911,7 +945,6 @@ dcd_hdr:
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
 #endif
-
        MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
 
@@ -922,6 +955,7 @@ dcd_hdr:
        MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
        MXC_DCD_ITEM(MMDC1_MAPSR, 1)
 
+#ifdef DO_DDR_CALIB
        /* ZQ calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
@@ -929,66 +963,13 @@ dcd_hdr:
 
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
        MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
-
-#define WL_DLY_DQS_VAL 30
-#define WL_DLY_DQS0    (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS1    (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS2    (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS3    (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS4    (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS5    (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS6    (WL_DLY_DQS_VAL + 0)
-#define WL_DLY_DQS7    (WL_DLY_DQS_VAL + 0)
-       /* Write leveling */
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET)
-       MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_RALAT(~0) | MDMISC_WALAT(~0)) /* increase WALAT/RALAT to max. */
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
-       MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
-       MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
-       MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
-       MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
-
-#if PHYS_SDRAM_1_WIDTH > 16
-#define DO_DDR_CALIB
 #endif
-       /* DQS gating calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
 #if BANK_ADDR_BITS > 1
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
 #endif
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
-       MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
-       MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
-       MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
-       MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
 
-       MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
-
-       MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
-       MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
-       MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
-       MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
-#define MPMUR_FRC_MSR  (1 << 11)
-       MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
-       MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
-#ifdef DO_DDR_CALIB
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, (1 << 30) | (1 << 28) | (0 << 23)) /* choose 32 wait cycles and start DQS calib. */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_ANY_CLR, MMDC1_MPDGCTRL0, 0x10001000)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-#else /* DO_DDR_CALIB */
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
-       MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
-       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
-       MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
-       MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
-       MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
-#endif /* DO_DDR_CALIB */
        MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL)
        /* DRAM_SDQS[0..7] pad config */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
@@ -1008,11 +989,7 @@ dcd_hdr:
        MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
        MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-#else /* DO_DDR_CALIB */
-       MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c)
-       MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a)
-#endif /* DO_DDR_CALIB */
-#ifdef DO_DDR_CALIB
+
        /* Write delay calibration */
        MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
        MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
@@ -1026,11 +1003,6 @@ dcd_hdr:
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
 #endif
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-#else /* DO_DDR_CALIB */
-       MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f)
-       MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f)
-       MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
-       MXC_DCD_ITEM_64(MMDC2_MPMUR0, MPMUR_FRC_MSR)
 #endif /* DO_DDR_CALIB */
        MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
 #if BANK_ADDR_BITS > 1