board/bsc9132qds: Add DSP side tlb and laws

BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

diff --git a/README b/README
index 5fb4c759112e83fab29f84b87fb098f0428f74b7..391880765a0865f05a71efc6dedf40d99e61d7fe 100644 (file)
--- a/README
+++ b/README
@@ -406,10 +406,18 @@ The following options need to be configured:
                This is the value to write into CCSR offset 0x18600
                according to the A004510 workaround.
 
+               CONFIG_SYS_FSL_DSP_DDR_ADDR
+               This value denotes start offset of DDR memory which is
+               connected exclusively to the DSP cores.
+
                CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
                This value denotes start offset of M2 memory
                which is directly connected to the DSP core.
 
+               CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
+               This value denotes start offset of M3 memory which is directly
+               connected to the DSP core.
+
                CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
                This value denotes start offset of DSP CCSR space.
 

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 91fda7ea41206d65d8c669f11bec4eb548a36e97..f94638969564767d435ae4780dab819df1da52f9 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -500,6 +500,10 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_NUM_DDR_CONTROLLERS     2
+#define CONFIG_SYS_FSL_DSP_DDR_ADDR    0x40000000
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
+#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT     0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  3
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_NAND_FSL_IFC

diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index bea1636768d04ec12bba2d7f2a368c71a9d33618..fa51e5992fc53e97f01034ddfa430569546e0e57 100644 (file)
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -82,7 +82,7 @@ enum law_trgt_if {
 #ifndef CONFIG_MPC8641
        LAW_TRGT_IF_PCIE_1 = 0x02,
 #endif
-#if defined(CONFIG_BSC9131)
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
        LAW_TRGT_IF_OCN_DSP = 0x03,
 #else
 #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
@@ -94,7 +94,11 @@ enum law_trgt_if {
        LAW_TRGT_IF_DSP_CCSR = 0x09,
        LAW_TRGT_IF_DDR_INTRLV = 0x0b,
        LAW_TRGT_IF_RIO = 0x0c,
+#if defined(CONFIG_BSC9132)
+       LAW_TRGT_IF_CLASS_DSP = 0x0d,
+#else
        LAW_TRGT_IF_RIO_2 = 0x0d,
+#endif
        LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
        LAW_TRGT_IF_DDR = 0x0f,
        LAW_TRGT_IF_DDR_2 = 0x16,       /* 2nd controller */

diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c
index fed2edf44a8f6d247f6fe176e34b525bff1361d8..e10de9adcf107779dd1719dfdd583e0dac93beef 100644 (file)
--- a/board/freescale/bsc9132qds/law.c
+++ b/board/freescale/bsc9132qds/law.c
@@ -16,6 +16,14 @@ struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_FPGA_BASE_PHYS
        SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
 #endif
+       SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
+               LAW_TRGT_IF_DSP_CCSR),
+       SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M,
+               LAW_TRGT_IF_OCN_DSP),
+       SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K,
+               LAW_TRGT_IF_CLASS_DSP),
+       SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G,
+               LAW_TRGT_IF_CLASS_DSP)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c
index 6d823534166ace2b97eb3381b50ac454b8895260..02655e9bafd68275ffba14cb362341d4a5de22a5 100644 (file)
--- a/board/freescale/bsc9132qds/tlb.c
+++ b/board/freescale/bsc9132qds/tlb.c
@@ -41,6 +41,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 1, BOOKE_PAGESZ_1M, 1),
 
+       /* CCSRBAR (DSP) */
+       SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
+                     CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, MAS3_SW|MAS3_SR,
+                     MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_1M, 1),
+
 #ifndef CONFIG_SPL_BUILD
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,

diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index 1ab68915859bfac3b8f15c2a2dbedd15f1bf05ed..03f3a4f80377ef0093612cee9746821057dd6f04 100644 (file)
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -224,6 +224,10 @@ combinations. this should be removed later
 
 #define CONFIG_SYS_IMMR                CONFIG_SYS_CCSRBAR
 
+/* DSP CCSRBAR */
+#define CONFIG_SYS_FSL_DSP_CCSRBAR     CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS        CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
+
 /*
  * IFC Definitions
  */