#define UART_SYSSTS_OFFSET 0x58
#define UART_RESET (0x1 << 1)
-#define UART_CLK_RUNNING_MASK 0x1
-#define UART_SMART_IDLE_EN (0x1 << 0x3)
+#define UART_RESETDONE (1 << 0)
+#define UART_IDLE_MODE(m) (((m) << 3) & UART_IDLE_MODE_MASK)
+#define UART_IDLE_MODE_MASK (0x3 << 3)
/* Timer Defines */
#define TSICR_REG 0x54
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) (val)
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
/*
* early system init of muxing and clocks.
*/
-void enable_uart0_pin_mux(void)
+static void enable_uart0_pin_mux(void)
{
tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins));
}
-void enable_mmc0_pin_mux(void)
+static void enable_mmc0_pin_mux(void)
{
tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins));
}
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
};
-void s_init(void)
+#ifdef CONFIG_HW_WATCHDOG
+static inline void tx48_wdog_disable(void)
+{
+}
+#else
+static inline void tx48_wdog_disable(void)
{
-#ifndef CONFIG_HW_WATCHDOG
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
/* WDT1 is already running when the bootloader gets control
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
+}
#endif
+
+void s_init(void)
+{
+ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ int timeout = 1000;
+
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
- /* UART softreset */
- u32 regVal;
- struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+ tx48_wdog_disable();
enable_uart0_pin_mux();
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_RESET;
- writel(regVal, &uart_base->uartsyscfg);
- while ((readl(&uart_base->uartsyssts) &
- UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
- ;
+ /* UART softreset */
+ writel(readl(&uart_base->uartsyscfg) | UART_RESET,
+ &uart_base->uartsyscfg);
+ while (!(readl(&uart_base->uartsyssts) & UART_RESETDONE)) {
+ udelay(1);
+ if (timeout-- <= 0)
+ break;
+ }
/* Disable smart idle */
- regVal = readl(&uart_base->uartsyscfg);
- regVal |= UART_SMART_IDLE_EN;
- writel(regVal, &uart_base->uartsyscfg);
+ writel((readl(&uart_base->uartsyscfg) & ~UART_IDLE_MODE_MASK) |
+ UART_IDLE_MODE(1), &uart_base->uartsyscfg);
- /* Initialize the Timer */
- timer_init();
+ gd = &gdata;
preloader_console_init();
+ if (timeout <= 0)
+ printf("Timeout waiting for UART RESET\n");
+
+
+ timer_init();
+
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &tx48_ddr3_data,
&tx48_ddr3_cmd_ctrl_data, &tx48_ddr3_emif_reg_data);
#define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
#define PRM_RSTST_ICEPICK_RST (1 << 9)
-struct prm_device {
- unsigned int prmrstctrl; /* offset 0x00 */
- unsigned int prmrsttime; /* offset 0x04 */
- unsigned int prmrstst; /* offset 0x08 */
- /* ... */
-};
-
static u32 prm_rstst __attribute__((section(".data")));
/*
/* called with default environment! */
int checkboard(void)
{
- struct prm_device *prmdev = (struct prm_device *)PRM_DEVICE;
-
- prm_rstst = readl(&prmdev->prmrstst);
+ prm_rstst = readl(PRM_RSTST);
show_reset_cause(prm_rstst);
#ifdef CONFIG_OF_LIBFDT
void s_init(void)
{
+ /* Nothing to be done here */
}
static struct cpsw_platform_data cpsw_data = {