/u-boot.dtb
/u-boot.sb
/u-boot.geany
-/include/u-boot.lst
#
# Generated files
# Board CPU #
#########################################################################
-Mike Frysinger <vapier@gentoo.org>
+Sonic Zhang <sonic.adi@gmail.com>
Blackfin Team <u-boot-devel@blackfin.uclinux.org>
BF506F-EZKIT BF506
BF538F-EZKIT BF538
BF548-EZKIT BF548
BF561-EZKIT BF561
+ BF609-EZKIT BF609
M.Hasewinkel (MHA) <info@ssv-embedded.de>
Environment variables:
BUILD_NCPUS number of parallel make jobs (default: auto)
CROSS_COMPILE cross-compiler toolchain prefix (default: "")
+ CROSS_COMPILE_<ARCH> cross-compiler toolchain prefix for
+ architecture "ARCH". Substitute "ARCH" for any
+ supported architecture (default: "")
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
BUILD_DIR output build directory (default: ./)
BUILD_NBUILDS number of parallel targets (default: 1)
JOBS=""
fi
-
-if [ "${CROSS_COMPILE}" ] ; then
- MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
-else
- MAKE=make
-fi
-
if [ "${MAKEALL_LOGDIR}" ] ; then
LOG_DIR=${MAKEALL_LOGDIR}
else
echo "$mail"
}
+get_target_arch() {
+ local target=$1
+
+ # Automatic mode
+ local line=`egrep -i "^[[:space:]]*${target}[[:space:]]" boards.cfg`
+
+ if [ -z "${line}" ] ; then echo "" ; return ; fi
+
+ set ${line}
+ echo "$2"
+}
+
list_target() {
if [ "$PRINT_MAINTS" != 'y' ] ; then
echo "$1"
export BUILD_DIR="${output_dir}"
+ target_arch=$(get_target_arch ${target})
+ eval cross_toolchain=\$CROSS_COMPILE_${target_arch^^}
+ if [ "${cross_toolchain}" ] ; then
+ MAKE="make CROSS_COMPILE=${cross_toolchain}"
+ elif [ "${CROSS_COMPILE}" ] ; then
+ MAKE="make CROSS_COMPILE=${CROSS_COMPILE}"
+ else
+ MAKE=make
+ fi
+
${MAKE} distclean >/dev/null
${MAKE} -s ${target}_config
#
VERSION = 2013
-PATCHLEVEL = 01
+PATCHLEVEL = 04
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
fs/fdos/libfdos.o \
fs/jffs2/libjffs2.o \
fs/reiserfs/libreiserfs.o \
+ fs/sandbox/libsandboxfs.o \
fs/ubifs/libubifs.o \
fs/yaffs2/libyaffs2.o \
fs/zfs/libzfs.o
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
else
GEN_UBOOT = \
- UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
- sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
- $$UNDEF_LST $(__OBJS) \
+ $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
endif
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
-# The following line expands into whole rule which generates u-boot.lst,
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
-$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
$(obj)u-boot.lds \
- $(obj)include/u-boot.lst \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
- @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
+ @rm -f $(obj)spl/u-boot-spl.lds
@rm -f $(obj)MLO MLO.byteswap
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
Thumb2 this flag will result in Thumb2 code generated by
GCC.
+ CONFIG_ARM_ERRATA_742230
+ CONFIG_ARM_ERRATA_743622
+ CONFIG_ARM_ERRATA_751472
+
+ If set, the workarounds for these ARM errata are applied early
+ during U-Boot startup. Note that these options force the
+ workarounds to be applied; no CPU-type/version detection
+ exists, unlike the similar options in the Linux kernel. Do not
+ set these options unless they apply!
+
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
CONFIG_CMD_I2C * I2C serial bus support
CONFIG_CMD_IDE * IDE harddisk support
CONFIG_CMD_IMI iminfo
- CONFIG_CMD_IMLS List all found images
+ CONFIG_CMD_IMLS List all images found in NOR flash
+ CONFIG_CMD_IMLS_NAND List all images found in NAND flash
CONFIG_CMD_IMMAP * IMMR dump support
CONFIG_CMD_IMPORTENV * import an environment
CONFIG_CMD_INI * import data from an ini file into the env
CONFIG_CMD_READ * Read raw data from partition
CONFIG_CMD_REGINFO * Register dump
CONFIG_CMD_RUN run command in env variable
+ CONFIG_CMD_SANDBOX * sb command to access sandbox features
CONFIG_CMD_SAVES * save S record dump
CONFIG_CMD_SCSI * SCSI Support
CONFIG_CMD_SDRAM * print SDRAM configuration information
allows for a "silent" boot where a splash screen is
loaded very quickly after power-on.
+ CONFIG_SPLASHIMAGE_GUARD
+
+ If this option is set, then U-Boot will prevent the environment
+ variable "splashimage" from being set to a problematic address
+ (see README.displaying-bmps and README.arm-unaligned-accesses).
+ This option is useful for targets where, due to alignment
+ restrictions, an improperly aligned BMP image will cause a data
+ abort. If you think you will not have problems with unaligned
+ accesses (for example because your toolchain prevents them)
+ there is no need to set this option.
+
CONFIG_SPLASH_SCREEN_ALIGN
If this option is set the splash image can be freely positioned
=> vertically centered image
at x = dspWidth - bmpWidth - 9
+ CONFIG_SPLASH_SCREEN_PREPARE
+
+ If this option is set then the board_splash_screen_prepare()
+ function, which must be defined in your code, is called as part
+ of the splash screen display sequence. It gives the board an
+ opportunity to prepare the splash image data before it is
+ processed and sent to the frame buffer by U-Boot.
+
- Gzip compressed BMP image support: CONFIG_VIDEO_BMP_GZIP
If this option is set, additionally to standard BMP
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
+- CONFIG_ARCH_MAP_SYSMEM
+ Generally U-Boot (and in particular the md command) uses
+ effective address. It is therefore not necessary to regard
+ U-Boot address as virtual addresses that need to be translated
+ to physical addresses. However, sandbox requires this, since
+ it maintains its own little RAM buffer which contains all
+ addressable memory. This option causes some memory accesses
+ to be mapped through map_sysmem() / unmap_sysmem().
+
- CONFIG_USE_ARCH_MEMCPY
CONFIG_USE_ARCH_MEMSET
If these options are used a optimized version of memcpy/memset will
case RCSR_MEM_TYPE_NOR:
return BOOT_DEVICE_NOR;
case RCSR_MEM_TYPE_ONENAND:
- return BOOT_DEVICE_ONE_NAND;
+ return BOOT_DEVICE_ONENAND;
default:
return BOOT_DEVICE_NONE;
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
if (cpu_is_at91sam9x5()) {
switch (extension_id) {
case ARCH_EXID_AT91SAM9G15:
- return CONFIG_SYS_AT91_G15_CPU_NAME;
+ return "AT91SAM9G15";
case ARCH_EXID_AT91SAM9G25:
- return CONFIG_SYS_AT91_G25_CPU_NAME;
+ return "AT91SAM9G25";
case ARCH_EXID_AT91SAM9G35:
- return CONFIG_SYS_AT91_G35_CPU_NAME;
+ return "AT91SAM9G35";
case ARCH_EXID_AT91SAM9X25:
- return CONFIG_SYS_AT91_X25_CPU_NAME;
+ return "AT91SAM9X25";
case ARCH_EXID_AT91SAM9X35:
- return CONFIG_SYS_AT91_X35_CPU_NAME;
+ return "AT91SAM9X35";
default:
- return CONFIG_SYS_AT91_UNKNOWN_CPU;
+ return "Unknown CPU type";
}
} else {
- return CONFIG_SYS_AT91_UNKNOWN_CPU;
+ return "Unknown CPU type";
}
}
#ifndef CONFIG_RMII
/* Only emac0 support MII */
if (has_emac0()) {
- at91_set_b_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
- at91_set_b_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
- at91_set_b_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
- at91_set_b_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
- at91_set_b_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
- at91_set_b_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
- at91_set_b_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
- at91_set_b_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
+ at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */
+ at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */
+ at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */
+ at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */
+ at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */
+ at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */
}
#endif
}
int ret;
ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr);
- if (ret) {
+ if (!ret) {
/*
* There is no MAC address in the environment, so we
* initialize it from the value in the EEPROM.
ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr);
}
if (!ret)
- printf("Failed to set mac address from EEPROM\n");
+ printf("Failed to set mac address from EEPROM: %d\n", ret);
}
#endif /* CONFIG_DRIVER_TI_EMAC */
. = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- . = ALIGN(4);
-
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
. = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
- . = ALIGN(4);
-
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
{
int ret;
- ret = omap_mmc_init(0, 0, 0);
+ ret = omap_mmc_init(0, 0, 0, -1, -1);
if (ret)
return ret;
- return omap_mmc_init(1, 0, 0);
+ return omap_mmc_init(1, 0, 0, -1, -1);
}
#endif
*/
void config_sdram(const struct emif_regs *regs)
{
- writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
- writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
- if (regs->zq_config){
+ if (regs->zq_config) {
+ /*
+ * A value of 0x2800 for the REF CTRL will give us
+ * about 570us for a delay, which will be long enough
+ * to configure things.
+ */
+ writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
writel(regs->zq_config, &emif_reg->emif_zq_config);
writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
}
writel(regs->sdram_config, &emif_reg->emif_sdram_config);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+ writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
}
/**
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text)
+ *(.text*)
+ } >.sram
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+ . = ALIGN(4);
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ .u_boot_list : {
+ KEEP(*(SORT(.u_boot_list*)));
+ } >.sram
+
+ . = ALIGN(4);
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sdram
+}
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
- omap_mmc_init(0, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
break;
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(1, 0, 0, -1, -1);
break;
}
return 0;
#include <asm/arch/sys_proto.h>
#include <asm/utils.h>
#include <asm/omap_gpio.h>
+#include <asm/emif.h>
#ifndef CONFIG_SPL_BUILD
/*
#define puts(s)
#endif
+const u32 sys_clk_array[8] = {
+ 12000000, /* 12 MHz */
+ 13000000, /* 13 MHz */
+ 16800000, /* 16.8 MHz */
+ 19200000, /* 19.2 MHz */
+ 26000000, /* 26 MHz */
+ 27000000, /* 27 MHz */
+ 38400000, /* 38.4 MHz */
+ 20000000, /* 20 MHz */
+};
+
static inline u32 __get_sys_clk_index(void)
{
- u32 ind;
+ s8 ind;
/*
* For ES1 the ROM code calibration of sys clock is not reliable
* due to hw issue. So, use hard-coded value. If this value is not
ind = OMAP_SYS_CLK_IND_38_4_MHZ;
else {
/* SYS_CLKSEL - 1 to match the dpll param array indices */
- ind = (readl(&prcm->cm_sys_clksel) &
+ ind = (readl((*prcm)->cm_sys_clksel) &
CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
+ /*
+ * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
+ * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
+ * NUM_SYS_CLK. So considering the last 3 bits as the index
+ * for the dpll param array.
+ */
+ ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
}
return ind;
}
return sys_clk_array[index];
}
-static inline void do_bypass_dpll(u32 *const base)
+void setup_post_dividers(u32 const base, const struct dpll_params *params)
+{
+ struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+
+ /* Setup post-dividers */
+ if (params->m2 >= 0)
+ writel(params->m2, &dpll_regs->cm_div_m2_dpll);
+ if (params->m3 >= 0)
+ writel(params->m3, &dpll_regs->cm_div_m3_dpll);
+ if (params->m4_h11 >= 0)
+ writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
+ if (params->m5_h12 >= 0)
+ writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
+ if (params->m6_h13 >= 0)
+ writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
+ if (params->m7_h14 >= 0)
+ writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
+ if (params->h21 >= 0)
+ writel(params->h21, &dpll_regs->cm_div_h21_dpll);
+ if (params->h22 >= 0)
+ writel(params->h22, &dpll_regs->cm_div_h22_dpll);
+ if (params->h23 >= 0)
+ writel(params->h23, &dpll_regs->cm_div_h23_dpll);
+ if (params->h24 >= 0)
+ writel(params->h24, &dpll_regs->cm_div_h24_dpll);
+}
+
+static inline void do_bypass_dpll(u32 const base)
{
struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
CM_CLKMODE_DPLL_EN_SHIFT);
}
-static inline void wait_for_bypass(u32 *const base)
+static inline void wait_for_bypass(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
LDELAY)) {
- printf("Bypassing DPLL failed %p\n", base);
+ printf("Bypassing DPLL failed %x\n", base);
}
}
-static inline void do_lock_dpll(u32 *const base)
+static inline void do_lock_dpll(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
}
-static inline void wait_for_lock(u32 *const base)
+static inline void wait_for_lock(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
&dpll_regs->cm_idlest_dpll, LDELAY)) {
- printf("DPLL locking failed for %p\n", base);
+ printf("DPLL locking failed for %x\n", base);
hang();
}
}
-inline u32 check_for_lock(u32 *const base)
+inline u32 check_for_lock(u32 const base)
{
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
return lock;
}
-static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->mpu[sysclk_ind];
+}
+
+const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->core[sysclk_ind];
+}
+
+const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->per[sysclk_ind];
+}
+
+const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->iva[sysclk_ind];
+}
+
+const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->usb[sysclk_ind];
+}
+
+const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
+{
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ u32 sysclk_ind = get_sys_clk_index();
+ return &dpll_data->abe[sysclk_ind];
+#else
+ return dpll_data->abe;
+#endif
+}
+
+static const struct dpll_params *get_ddr_dpll_params
+ (struct dplls const *dpll_data)
+{
+ u32 sysclk_ind = get_sys_clk_index();
+
+ if (!dpll_data->ddr)
+ return NULL;
+ return &dpll_data->ddr[sysclk_ind];
+}
+
+static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
+ if (!params)
+ return;
+
temp = readl(&dpll_regs->cm_clksel_dpll);
if (check_for_lock(base)) {
omap_rev = omap_revision();
sys_clk_khz = get_sys_clk_freq() / 1000;
- core_dpll_params = get_core_dpll_params();
+ core_dpll_params = get_core_dpll_params(*dplls_data);
debug("sys_clk %d\n ", sys_clk_khz * 1000);
*/
if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
mpu_dpll_regs =
- (struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
- bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
- clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+ (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
+ bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
+ clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
- setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+ setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
CM_CLKSEL_DCC_EN_MASK);
}
- setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
- setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
- MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+ params = get_mpu_dpll_params(*dplls_data);
- params = get_mpu_dpll_params();
-
- do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
debug("MPU DPLL locked\n");
}
* Use CLKINP in KHz and adjust the denominator accordingly so
* that we have enough accuracy and at the same time no overflow
*/
- params = get_usb_dpll_params();
+ params = get_usb_dpll_params(*dplls_data);
num = params->m * sys_clk_khz;
den = (params->n + 1) * 250 * 1000;
num += den - 1;
sd_div = num / den;
- clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+ clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
/* Now setup the dpll with the regular function */
- do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
}
#endif
debug("setup_dplls\n");
/* CORE dpll */
- params = get_core_dpll_params(); /* default - safest */
+ params = get_core_dpll_params(*dplls_data); /* default - safest */
/*
* Do not lock the core DPLL now. Just set it up.
* Core DPLL will be locked after setting up EMIF
* using the FREQ_UPDATE method(freq_update_core())
*/
- if (omap_revision() != OMAP5432_ES1_0)
- do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_NO_LOCK, "core");
else
- do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
DPLL_LOCK, "core");
/* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
(CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
(CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
- writel(temp, &prcm->cm_clksel_core);
+ writel(temp, (*prcm)->cm_clksel_core);
debug("Core DPLL configured\n");
/* lock PER dpll */
- params = get_per_dpll_params();
- do_setup_dpll(&prcm->cm_clkmode_dpll_per,
+ params = get_per_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
params, DPLL_LOCK, "per");
debug("PER DPLL locked\n");
#ifdef CONFIG_USB_EHCI_OMAP
setup_usb_dpll();
#endif
+ params = get_ddr_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
+ params, DPLL_LOCK, "ddr");
}
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
const struct dpll_params *params;
/* IVA */
- clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,
+ clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
- params = get_iva_dpll_params();
- do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
+ params = get_iva_dpll_params(*dplls_data);
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
/* Configure ABE dpll */
- params = get_abe_dpll_params();
+ params = get_abe_dpll_params(*dplls_data);
#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
#else
* We need to enable some additional options to achieve
* 196.608MHz from 32768 Hz
*/
- setbits_le32(&prcm->cm_clkmode_dpll_abe,
+ setbits_le32((*prcm)->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
CM_CLKMODE_DPLL_LPMODE_EN_MASK|
CM_CLKMODE_DPLL_REGM4XEN_MASK);
/* Spend 4 REFCLK cycles at each stage */
- clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,
+ clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
CM_CLKMODE_DPLL_RAMP_RATE_MASK,
1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
#endif
/* Select the right reference clk */
- clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,
+ clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
/* Lock the dpll */
- do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
+ do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
}
#endif
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
{
- u32 step;
- int ret = 0;
-
- /* See if we can first get the GPIO if needed */
- if (gpio >= 0)
- ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
- if (ret < 0) {
- printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
- gpio = -1;
- }
-
- /* Pull the GPIO low to select SET0 register, while we program SET1 */
- if (gpio >= 0)
- gpio_direction_output(gpio, 0);
+ u32 offset_code;
- step = volt_mv - TPS62361_BASE_VOLT_MV;
- step /= 10;
+ volt_offset -= pmic->base_offset;
- debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
- if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
- puts("Scaling voltage failed for vdd_mpu from TPS\n");
+ offset_code = (volt_offset + pmic->step - 1) / pmic->step;
- /* Pull the GPIO high to select SET1 register */
- if (gpio >= 0)
- gpio_direction_output(gpio, 1);
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ return offset_code + pmic->start_code;
}
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
{
u32 offset_code;
u32 offset = volt_mv;
+ int ret = 0;
+
+ /* See if we can first get the GPIO if needed */
+ if (pmic->gpio_en)
+ ret = gpio_request(pmic->gpio, "PMIC_GPIO");
+
+ if (ret < 0) {
+ printf("%s: gpio %d request failed %d\n", __func__,
+ pmic->gpio, ret);
+ return;
+ }
+
+ /* Pull the GPIO low to select SET0 register, while we program SET1 */
+ if (pmic->gpio_en)
+ gpio_direction_output(pmic->gpio, 0);
/* convert to uV for better accuracy in the calculations */
offset *= 1000;
- offset_code = get_offset_code(offset);
+ offset_code = get_offset_code(offset, pmic);
debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
offset_code);
if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
vcore_reg, offset_code))
printf("Scaling voltage failed for 0x%x\n", vcore_reg);
+
+ if (pmic->gpio_en)
+ gpio_direction_output(pmic->gpio, 1);
+}
+
+/*
+ * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
+ * We set the maximum voltages allowed here because Smart-Reflex is not
+ * enabled in bootloader. Voltage initialization in the kernel will set
+ * these to the nominal values after enabling Smart-Reflex
+ */
+void scale_vcores(struct vcores_data const *vcores)
+{
+ omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
+
+ do_scale_vcore(vcores->core.addr, vcores->core.value,
+ vcores->core.pmic);
+
+ do_scale_vcore(vcores->mpu.addr, vcores->mpu.value,
+ vcores->mpu.pmic);
+
+ do_scale_vcore(vcores->mm.addr, vcores->mm.value,
+ vcores->mm.pmic);
+
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
+ /* Configure LDO SRAM "magic" bits */
+ writel(2, (*prcm)->prm_sldo_core_setup);
+ writel(2, (*prcm)->prm_sldo_mpu_setup);
+ writel(2, (*prcm)->prm_sldo_mm_setup);
+ }
}
-static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
+static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - %p\n", clkctrl_reg);
+ debug("Enable clock domain - %x\n", clkctrl_reg);
}
-static inline void wait_for_clk_enable(u32 *clkctrl_addr)
+static inline void wait_for_clk_enable(u32 clkctrl_addr)
{
u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
u32 bound = LDELAY;
idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
MODULE_CLKCTRL_IDLEST_SHIFT;
if (--bound == 0) {
- printf("Clock enable failed for 0x%p idlest 0x%x\n",
+ printf("Clock enable failed for 0x%x idlest 0x%x\n",
clkctrl_addr, clkctrl);
return;
}
}
}
-static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
+static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
u32 wait_for_enable)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - %p\n", clkctrl_addr);
+ debug("Enable clock module - %x\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}
const struct dpll_params *core_dpll_params;
u32 omap_rev = omap_revision();
- core_dpll_params = get_core_dpll_params();
+ core_dpll_params = get_core_dpll_params(*dplls_data);
/* Put EMIF clock domain in sw wakeup mode */
- enable_clock_domain(&prcm->cm_memif_clkstctrl,
+ enable_clock_domain((*prcm)->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
- wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
- writel(freq_config1, &prcm->cm_shadow_freq_config1);
+ writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
- &prcm->cm_shadow_freq_config1, LDELAY)) {
+ (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
puts("FREQ UPDATE procedure failed!!");
hang();
}
*/
if (omap_rev != OMAP5430_ES1_0) {
/* Put EMIF clock domain back in hw auto mode */
- enable_clock_domain(&prcm->cm_memif_clkstctrl,
+ enable_clock_domain((*prcm)->cm_memif_clkstctrl,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
- wait_for_clk_enable(&prcm->cm_memif_emif_1_clkctrl);
- wait_for_clk_enable(&prcm->cm_memif_emif_2_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
+ wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
}
}
-void bypass_dpll(u32 *const base)
+void bypass_dpll(u32 const base)
{
do_bypass_dpll(base);
wait_for_bypass(base);
}
-void lock_dpll(u32 *const base)
+void lock_dpll(u32 const base)
{
do_lock_dpll(base);
wait_for_lock(base);
void setup_clocks_for_console(void)
{
/* Do not add any spl_debug prints in this function */
- clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
/* Enable all UARTs - console will be on one of them */
- clrsetbits_le32(&prcm->cm_l4per_uart1_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_uart2_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_uart3_clkctrl,
+ clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
MODULE_CLKCTRL_MODULEMODE_MASK,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
MODULE_CLKCTRL_MODULEMODE_SHIFT);
- clrsetbits_le32(&prcm->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
+ clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
CD_CLKCTRL_CLKTRCTRL_SHIFT);
}
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_hw_auto,
- u32 *const *clk_modules_explicit_en,
+void do_enable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
u8 wait_for_enable)
{
u32 i, max = 100;
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
enable_basic_clocks();
- scale_vcores();
+ scale_vcores(*omap_vcores);
setup_dplls();
#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
setup_non_essential_dplls();
return 0;
}
+/*
+ * Get SDRAM type connected to EMIF.
+ * Assuming similar SDRAM parts are connected to both EMIF's
+ * which is typically the case. So it is sufficient to get
+ * SDRAM type from EMIF1.
+ */
+u32 emif_sdram_type()
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
+
+ return (readl(&emif->emif_sdram_config) &
+ EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
+}
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
static void do_lpddr2_init(u32 base, u32 cs)
{
u32 mr_addr;
+ const struct lpddr2_mr_regs *mr_regs;
+ get_lpddr2_mr_regs(&mr_regs);
/* Wait till device auto initialization is complete */
while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
;
- set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+ set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
/*
* tZQINIT = 1 us
* Enough loops assuming a maximum of 2GHz
sdelay(2000);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
- else
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-
- set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+ set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+ set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
/*
* Enable refresh along with writing MR2
* Encoding of RL in MR2 is (RL - 2)
*/
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, RL_FINAL - 2);
+ set_mr(base, cs, mr_addr, mr_regs->mr2);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR3, 0x1);
+ if (mr_regs->mr3 > 0)
+ set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
}
static void lpddr2_init(u32 base, const struct emif_regs *regs)
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
- /*
- * external phy 6-24 registers do not change with
- * ddr frequency
- */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- }
+ do_ext_phy_settings(base, regs);
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
* OPP to another)
*/
if (!(in_sdram || warm_reset())) {
- if (omap_revision() != OMAP5432_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
lpddr2_init(base, regs);
else
ddr3_init(base, regs);
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 omap_rev = omap_revision();
- if (omap_rev == OMAP5430_ES1_0)
- return;
-
/* reset phy on ES2.0 */
if (omap_rev == OMAP4430_ES2_0)
emif_reset_phy(base);
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
- if (omap_revision() >= OMAP4460_ES1_0) {
+ if (lisa_map_regs->is_ma_present) {
hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)MA_BASE;
void sdram_init(void)
{
u32 in_sdram, size_prog, size_detect;
- u32 omap_rev = omap_revision();
+ u32 sdram_type = emif_sdram_type();
debug(">>sdram_init()\n");
debug("in_sdram = %d\n", in_sdram);
if (!(in_sdram || warm_reset())) {
- if (omap_rev != OMAP5432_ES1_0)
- bypass_dpll(&prcm->cm_clkmode_dpll_core);
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ bypass_dpll((*prcm)->cm_clkmode_dpll_core);
else
- writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+ writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
if (!in_sdram)
}
/* for the shadow registers to take effect */
- if (omap_rev != OMAP5432_ES1_0)
+ if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
freq_update_core();
/* Do some testing after the init */
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/emif.h>
+#include <asm/omap_common.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
void omap_rev_string(void)
{
u32 omap_rev = omap_revision();
+ u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
u32 major_rev = (omap_rev & 0x00000F00) >> 8;
u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
- printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
- minor_rev);
+ if (soc_variant)
+ printf("OMAP");
+ else
+ printf("DRA");
+ printf("%x ES%x.%x\n", omap_variant, major_rev,
+ minor_rev);
}
#ifdef CONFIG_SPL_BUILD
}
#endif
+void __weak srcomp_enable(void)
+{
+}
+
/*
* Routine: s_init
* Description: Does early system init of watchdog, muxing, andclocks
void s_init(void)
{
init_omap_revision();
+ hw_data_init();
+
#ifdef CONFIG_SPL_BUILD
if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
force_emif_self_refresh();
watchdog_init();
set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
+ srcomp_enable();
setup_clocks_for_console();
gd = &gdata;
*/
u32 get_device_type(void)
{
- struct omap_sys_ctrl_regs *ctrl =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- return (readl(&ctrl->control_status) &
+ return (readl((*ctrl)->control_status) &
(DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
}
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
. = ALIGN(4);
__image_copy_end = .;
_end = .;
cycles_low -= 7;
val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) |
(cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT);
- writel(val, &prcm->prm_vc_cfg_i2c_clk);
+ writel(val, (*prcm)->prm_vc_cfg_i2c_clk);
val = CONFIG_OMAP_VC_I2C_HS_MCODE <<
PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT;
/* No HS mode for now */
val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT;
- writel(val, &prcm->prm_vc_cfg_i2c_mode);
+ writel(val, (*prcm)->prm_vc_cfg_i2c_mode);
}
/**
reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT |
reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT |
reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT;
- writel(reg_val, &prcm->prm_vc_val_bypass);
+ writel(reg_val, (*prcm)->prm_vc_val_bypass);
/* Signal VC to send data */
- writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, &prcm->prm_vc_val_bypass);
+ writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT,
+ (*prcm)->prm_vc_val_bypass);
/* Wait on VC to complete transmission */
do {
- reg_val = readl(&prcm->prm_vc_val_bypass) &
+ reg_val = readl((*prcm)->prm_vc_val_bypass) &
PRM_VC_VAL_BYPASS_VALID_BIT;
if (!reg_val)
break;
{
switch (spl_boot_device()) {
case BOOT_DEVICE_MMC1:
- omap_mmc_init(0, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
break;
case BOOT_DEVICE_MMC2:
case BOOT_DEVICE_MMC2_2:
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(1, 0, 0, -1, -1);
break;
}
return 0;
void spl_board_init(void)
{
-#ifdef CONFIG_SPL_NAND_SUPPORT
+#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
gpmc_init();
#endif
#ifdef CONFIG_SPL_I2C_SUPPORT
COBJS += sdram_elpida.o
COBJS += hwinit.o
-COBJS += clocks.o
COBJS += emif.o
+COBJS += prcm-regs.o
+COBJS += hw_data.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+++ /dev/null
-/*
- *
- * Clock initialization for OMAP4
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- *
- * Based on previous work by:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- * Rajendra Nayak <rnayak@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/gpio.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif /* !CONFIG_SPL_BUILD */
-
-struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
-
-const u32 sys_clk_array[8] = {
- 12000000, /* 12 MHz */
- 13000000, /* 13 MHz */
- 16800000, /* 16.8 MHz */
- 19200000, /* 19.2 MHz */
- 26000000, /* 26 MHz */
- 27000000, /* 27 MHz */
- 38400000, /* 38.4 MHz */
-};
-
-/*
- * The M & N values in the following tables are created using the
- * following tool:
- * tools/omap/clocks_get_m_n.c
- * Please use this tool for creating the table for any new frequency.
- */
-
-/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
-static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
- {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
-static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
-static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
- {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
- {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
- {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
- {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
- {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
- {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
- {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
- {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
- {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
- {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
- {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
- {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
- {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
- {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
- {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
- {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
- {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
- {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
- {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
- {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
- {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
- {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
- {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
- {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
- {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
- {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
- {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
- {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
- {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
- {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
- {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
- {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
- {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
- {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
- {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-void setup_post_dividers(u32 *const base, const struct dpll_params *params)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, &dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, &dpll_regs->cm_div_m3_dpll);
- if (params->m4 >= 0)
- writel(params->m4, &dpll_regs->cm_div_m4_dpll);
- if (params->m5 >= 0)
- writel(params->m5, &dpll_regs->cm_div_m5_dpll);
- if (params->m6 >= 0)
- writel(params->m6, &dpll_regs->cm_div_m6_dpll);
- if (params->m7 >= 0)
- writel(params->m7, &dpll_regs->cm_div_m7_dpll);
-}
-
-/*
- * Lock MPU dpll
- *
- * Resulting MPU frequencies:
- * 4430 ES1.0 : 600 MHz
- * 4430 ES2.x : 792 MHz (OPP Turbo)
- * 4460 : 920 MHz (OPP Turbo) - DCC disabled
- */
-const struct dpll_params *get_mpu_dpll_params(void)
-{
- u32 omap_rev, sysclk_ind;
-
- omap_rev = omap_revision();
- sysclk_ind = get_sys_clk_index();
-
- if (omap_rev == OMAP4430_ES1_0)
- return &mpu_dpll_params_1200mhz[sysclk_ind];
- else if (omap_rev < OMAP4460_ES1_0)
- return &mpu_dpll_params_1600mhz[sysclk_ind];
- else
- return &mpu_dpll_params_1400mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_core_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- switch (omap_revision()) {
- case OMAP4430_ES1_0:
- return &core_dpll_params_es1_1524mhz[sysclk_ind];
- case OMAP4430_ES2_0:
- case OMAP4430_SILICON_ID_INVALID:
- /* safest */
- return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
- default:
- return &core_dpll_params_1600mhz[sysclk_ind];
- }
-}
-
-
-const struct dpll_params *get_per_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &per_dpll_params_1536mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_iva_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &iva_dpll_params_1862mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_usb_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &usb_dpll_params_1920mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_abe_dpll_params(void)
-{
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- u32 sysclk_ind = get_sys_clk_index();
- return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
-#else
- return &abe_dpll_params_32k_196608khz;
-#endif
-}
-
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-void scale_vcores(void)
-{
- u32 volt, omap_rev;
-
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
-
- omap_rev = omap_revision();
-
- /*
- * Scale Voltage rails:
- * 1. VDD_CORE
- * 3. VDD_MPU
- * 3. VDD_IVA
- */
- if (omap_rev < OMAP4460_ES1_0) {
- /*
- * OMAP4430:
- * VDD_CORE = TWL6030 VCORE3
- * VDD_MPU = TWL6030 VCORE1
- * VDD_IVA = TWL6030 VCORE2
- */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
-
- /*
- * note on VDD_MPU:
- * Setting a high voltage for Nitro mode as smart reflex is not
- * enabled. We use the maximum possible value in the AVS range
- * because the next higher voltage in the discrete range
- * (code >= 0b111010) is way too high.
- */
- volt = 1325;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
-
- } else {
- /*
- * OMAP4460:
- * VDD_CORE = TWL6030 VCORE1
- * VDD_MPU = TPS62361
- * VDD_IVA = TWL6030 VCORE2
- */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
- /* TPS62361 */
- volt = 1203;
- do_scale_tps62361(TPS62361_VSEL0_GPIO,
- TPS62361_REG_ADDR_SET1, volt);
- /* VCORE 2 - supplies vdd_iva */
- volt = 1200;
- do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
- }
-}
-
-u32 get_offset_code(u32 offset)
-{
- u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
-
- if (omap_revision() == OMAP4430_ES1_0)
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
- else
- offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
-
- offset_code = (offset + step - 1) / step;
-
- /* The code starts at 1 not 0 */
- return ++offset_code;
-}
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- &prcm->cm_l4per_clkstctrl,
- &prcm->cm_l3init_clkstctrl,
- &prcm->cm_memif_clkstctrl,
- &prcm->cm_l4cfg_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- &prcm->cm_l3_2_gpmc_clkctrl,
- &prcm->cm_memif_emif_1_clkctrl,
- &prcm->cm_memif_emif_2_clkctrl,
- &prcm->cm_l4cfg_l4_cfg_clkctrl,
- &prcm->cm_wkup_gpio1_clkctrl,
- &prcm->cm_l4per_gpio2_clkctrl,
- &prcm->cm_l4per_gpio3_clkctrl,
- &prcm->cm_l4per_gpio4_clkctrl,
- &prcm->cm_l4per_gpio5_clkctrl,
- &prcm->cm_l4per_gpio6_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_wkup_gptimer1_clkctrl,
- &prcm->cm_l3init_hsmmc1_clkctrl,
- &prcm->cm_l3init_hsmmc2_clkctrl,
- &prcm->cm_l4per_gptimer2_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_l4per_uart3_clkctrl,
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- /* Enable optional 48M functional clock for USB PHY */
- setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
- USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- &prcm->cm_l3init_hsusbotg_clkctrl,
- &prcm->cm_l3init_usbphy_clkctrl,
- &prcm->cm_l3init_usbphy_clkctrl,
- &prcm->cm_clksel_usb_60mhz,
- &prcm->cm_l3init_hsusbtll_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_l4per_mcspi1_clkctrl,
- &prcm->cm_l4per_i2c1_clkctrl,
- &prcm->cm_l4per_i2c2_clkctrl,
- &prcm->cm_l4per_i2c3_clkctrl,
- &prcm->cm_l4per_i2c4_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
- u32 *const clk_domains_non_essential[] = {
- &prcm->cm_mpu_m3_clkstctrl,
- &prcm->cm_ivahd_clkstctrl,
- &prcm->cm_dsp_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sgx_clkstctrl,
- &prcm->cm1_abe_clkstctrl,
- &prcm->cm_c2c_clkstctrl,
- &prcm->cm_cam_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sdma_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_non_essential[] = {
- &prcm->cm_l3instr_l3_3_clkctrl,
- &prcm->cm_l3instr_l3_instr_clkctrl,
- &prcm->cm_l3instr_intrconn_wp1_clkctrl,
- &prcm->cm_l3init_hsi_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_non_essential[] = {
- &prcm->cm1_abe_aess_clkctrl,
- &prcm->cm1_abe_pdm_clkctrl,
- &prcm->cm1_abe_dmic_clkctrl,
- &prcm->cm1_abe_mcasp_clkctrl,
- &prcm->cm1_abe_mcbsp1_clkctrl,
- &prcm->cm1_abe_mcbsp2_clkctrl,
- &prcm->cm1_abe_mcbsp3_clkctrl,
- &prcm->cm1_abe_slimbus_clkctrl,
- &prcm->cm1_abe_timer5_clkctrl,
- &prcm->cm1_abe_timer6_clkctrl,
- &prcm->cm1_abe_timer7_clkctrl,
- &prcm->cm1_abe_timer8_clkctrl,
- &prcm->cm1_abe_wdt3_clkctrl,
- &prcm->cm_l4per_gptimer9_clkctrl,
- &prcm->cm_l4per_gptimer10_clkctrl,
- &prcm->cm_l4per_gptimer11_clkctrl,
- &prcm->cm_l4per_gptimer3_clkctrl,
- &prcm->cm_l4per_gptimer4_clkctrl,
- &prcm->cm_l4per_hdq1w_clkctrl,
- &prcm->cm_l4per_mcbsp4_clkctrl,
- &prcm->cm_l4per_mcspi2_clkctrl,
- &prcm->cm_l4per_mcspi3_clkctrl,
- &prcm->cm_l4per_mcspi4_clkctrl,
- &prcm->cm_l4per_mmcsd3_clkctrl,
- &prcm->cm_l4per_mmcsd4_clkctrl,
- &prcm->cm_l4per_mmcsd5_clkctrl,
- &prcm->cm_l4per_uart1_clkctrl,
- &prcm->cm_l4per_uart2_clkctrl,
- &prcm->cm_l4per_uart4_clkctrl,
- &prcm->cm_wkup_keyboard_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_cam_iss_clkctrl,
- &prcm->cm_cam_fdif_clkctrl,
- &prcm->cm_dss_dss_clkctrl,
- &prcm->cm_sgx_sgx_clkctrl,
- 0
- };
-
- /* Enable optional functional clock for ISS */
- setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable all optional functional clocks of DSS */
- setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
- do_enable_clocks(clk_domains_non_essential,
- clk_modules_hw_auto_non_essential,
- clk_modules_explicit_en_non_essential,
- 0);
-
- /* Put camera module in no sleep mode */
- clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
- CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
--- /dev/null
+/*
+ *
+ * HW data initialization for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+
+struct prcm_regs const **prcm =
+ (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+ (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+ (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP4_SRAM_SCRATCH_SYS_CTRL;
+
+/*
+ * The M & N values in the following tables are created using the
+ * following tool:
+ * tools/omap/clocks_get_m_n.c
+ * Please use this tool for creating the table for any new frequency.
+ */
+
+/*
+ * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
+ * OMAP4460 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
+ {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
+ * OMAP4430 OPP_TURBO frequency
+ */
+static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/*
+ * dpll locked at 1200 MHz - MPU clk at 600 MHz
+ * OMAP4430 OPP_NOM frequency
+ */
+static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
+ {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4460 OPP_NOM frequency */
+static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4430 ES1 OPP_NOM frequency */
+static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
+ {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OMAP4430 ES2.X OPP_NOM frequency */
+static const struct dpll_params
+ core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
+ {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
+ {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */
+ {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */
+ {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */
+ {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */
+ {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */
+ {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */
+ {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
+ {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+struct dplls omap4430_dplls_es1 = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_es1_1524mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4430_dplls = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap4460_dplls = {
+ .mpu = mpu_dpll_params_1400mhz,
+ .core = core_dpll_params_1600mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct pmic_data twl6030_4430es1 = {
+ .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
+ .step = 12660, /* 10 mV represented in uV */
+ /* The code starts at 1 not 0 */
+ .start_code = 1,
+};
+
+struct pmic_data twl6030 = {
+ .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
+ .step = 12660, /* 10 mV represented in uV */
+ /* The code starts at 1 not 0 */
+ .start_code = 1,
+};
+
+struct pmic_data tps62361 = {
+ .base_offset = TPS62361_BASE_VOLT_MV,
+ .step = 10000, /* 10 mV represented in uV */
+ .start_code = 0,
+ .gpio = TPS62361_VSEL0_GPIO,
+ .gpio_en = 1
+};
+
+struct vcores_data omap4430_volts_es1 = {
+ .mpu.value = 1325,
+ .mpu.addr = SMPS_REG_ADDR_VCORE1,
+ .mpu.pmic = &twl6030_4430es1,
+
+ .core.value = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE3,
+ .core.pmic = &twl6030_4430es1,
+
+ .mm.value = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &twl6030_4430es1,
+};
+
+struct vcores_data omap4430_volts = {
+ .mpu.value = 1325,
+ .mpu.addr = SMPS_REG_ADDR_VCORE1,
+ .mpu.pmic = &twl6030,
+
+ .core.value = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE3,
+ .core.pmic = &twl6030,
+
+ .mm.value = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &twl6030,
+};
+
+struct vcores_data omap4460_volts = {
+ .mpu.value = 1203,
+ .mpu.addr = TPS62361_REG_ADDR_SET1,
+ .mpu.pmic = &tps62361,
+
+ .core.value = 1200,
+ .core.addr = SMPS_REG_ADDR_VCORE1,
+ .core.pmic = &tps62361,
+
+ .mm.value = 1200,
+ .mm.addr = SMPS_REG_ADDR_VCORE2,
+ .mm.pmic = &tps62361,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ (*prcm)->cm_l4per_clkstctrl,
+ (*prcm)->cm_l3init_clkstctrl,
+ (*prcm)->cm_memif_clkstctrl,
+ (*prcm)->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3_gpmc_clkctrl,
+ (*prcm)->cm_memif_emif_1_clkctrl,
+ (*prcm)->cm_memif_emif_2_clkctrl,
+ (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+ (*prcm)->cm_wkup_gpio1_clkctrl,
+ (*prcm)->cm_l4per_gpio2_clkctrl,
+ (*prcm)->cm_l4per_gpio3_clkctrl,
+ (*prcm)->cm_l4per_gpio4_clkctrl,
+ (*prcm)->cm_l4per_gpio5_clkctrl,
+ (*prcm)->cm_l4per_gpio6_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_wkup_gptimer1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc2_clkctrl,
+ (*prcm)->cm_l4per_gptimer2_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_l4per_uart3_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ /* Enable optional 48M functional clock for USB PHY */
+ setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
+ USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3init_hsusbotg_clkctrl,
+ (*prcm)->cm_l3init_usbphy_clkctrl,
+ (*prcm)->cm_l3init_usbphy_clkctrl,
+ (*prcm)->cm_clksel_usb_60mhz,
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_mcspi1_clkctrl,
+ (*prcm)->cm_l4per_i2c1_clkctrl,
+ (*prcm)->cm_l4per_i2c2_clkctrl,
+ (*prcm)->cm_l4per_i2c3_clkctrl,
+ (*prcm)->cm_l4per_i2c4_clkctrl,
+ (*prcm)->cm_l3init_hsusbhost_clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_non_essential_clocks(void)
+{
+ u32 const clk_domains_non_essential[] = {
+ (*prcm)->cm_mpu_m3_clkstctrl,
+ (*prcm)->cm_ivahd_clkstctrl,
+ (*prcm)->cm_dsp_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sgx_clkstctrl,
+ (*prcm)->cm1_abe_clkstctrl,
+ (*prcm)->cm_c2c_clkstctrl,
+ (*prcm)->cm_cam_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sdma_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_non_essential[] = {
+ (*prcm)->cm_l3instr_l3_3_clkctrl,
+ (*prcm)->cm_l3instr_l3_instr_clkctrl,
+ (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
+ (*prcm)->cm_l3init_hsi_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_non_essential[] = {
+ (*prcm)->cm1_abe_aess_clkctrl,
+ (*prcm)->cm1_abe_pdm_clkctrl,
+ (*prcm)->cm1_abe_dmic_clkctrl,
+ (*prcm)->cm1_abe_mcasp_clkctrl,
+ (*prcm)->cm1_abe_mcbsp1_clkctrl,
+ (*prcm)->cm1_abe_mcbsp2_clkctrl,
+ (*prcm)->cm1_abe_mcbsp3_clkctrl,
+ (*prcm)->cm1_abe_slimbus_clkctrl,
+ (*prcm)->cm1_abe_timer5_clkctrl,
+ (*prcm)->cm1_abe_timer6_clkctrl,
+ (*prcm)->cm1_abe_timer7_clkctrl,
+ (*prcm)->cm1_abe_timer8_clkctrl,
+ (*prcm)->cm1_abe_wdt3_clkctrl,
+ (*prcm)->cm_l4per_gptimer9_clkctrl,
+ (*prcm)->cm_l4per_gptimer10_clkctrl,
+ (*prcm)->cm_l4per_gptimer11_clkctrl,
+ (*prcm)->cm_l4per_gptimer3_clkctrl,
+ (*prcm)->cm_l4per_gptimer4_clkctrl,
+ (*prcm)->cm_l4per_hdq1w_clkctrl,
+ (*prcm)->cm_l4per_mcbsp4_clkctrl,
+ (*prcm)->cm_l4per_mcspi2_clkctrl,
+ (*prcm)->cm_l4per_mcspi3_clkctrl,
+ (*prcm)->cm_l4per_mcspi4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd3_clkctrl,
+ (*prcm)->cm_l4per_mmcsd4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd5_clkctrl,
+ (*prcm)->cm_l4per_uart1_clkctrl,
+ (*prcm)->cm_l4per_uart2_clkctrl,
+ (*prcm)->cm_l4per_uart4_clkctrl,
+ (*prcm)->cm_wkup_keyboard_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_cam_iss_clkctrl,
+ (*prcm)->cm_cam_fdif_clkctrl,
+ (*prcm)->cm_dss_dss_clkctrl,
+ (*prcm)->cm_sgx_sgx_clkctrl,
+ 0
+ };
+
+ /* Enable optional functional clock for ISS */
+ setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable all optional functional clocks of DSS */
+ setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
+
+ /* Put camera module in no sleep mode */
+ clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+void hw_data_init(void)
+{
+ u32 omap_rev = omap_revision();
+
+ (*prcm) = &omap4_prcm;
+
+ switch (omap_rev) {
+
+ case OMAP4430_ES1_0:
+ *dplls_data = &omap4430_dplls_es1;
+ *omap_vcores = &omap4430_volts_es1;
+ break;
+
+ case OMAP4430_ES2_0:
+ case OMAP4430_ES2_1:
+ case OMAP4430_ES2_2:
+ case OMAP4430_ES2_3:
+ *dplls_data = &omap4430_dplls;
+ *omap_vcores = &omap4430_volts;
+ break;
+
+ case OMAP4460_ES1_0:
+ case OMAP4460_ES1_1:
+ *dplls_data = &omap4460_dplls;
+ *omap_vcores = &omap4460_volts;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+
+ *ctrl = &omap4_ctrl;
+}
void do_io_settings(void)
{
u32 lpddr2io;
- struct control_lpddr2io_regs *lpddr2io_regs =
- (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
- struct omap_sys_ctrl_regs *const ctrl =
- (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
u32 omap4_rev = omap_revision();
lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
/* EMIF1 */
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- &lpddr2io_regs->control_lpddr2io1_2);
- writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io1_3);
+ (*ctrl)->control_lpddr2io1_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
/* EMIF2 */
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);
- writel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
+ writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
/* No pull for GR10 as per hw team's recommendation */
writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
- &lpddr2io_regs->control_lpddr2io2_2);
- writel(CONTROL_LPDDR2IO_3_VAL, &lpddr2io_regs->control_lpddr2io2_3);
+ (*ctrl)->control_lpddr2io2_2);
+ writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
/*
* Some of these settings (TRIM values) come from eFuse and are
* calibration of the device. Do the software over-ride only if
* the device is not correctly trimmed
*/
- if (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {
+ if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_iva_voltage_ctrl);
+ (*ctrl)->control_ldosram_iva_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_mpu_voltage_ctrl);
+ (*ctrl)->control_ldosram_mpu_voltage_ctrl);
writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
- &ctrl->control_ldosram_core_voltage_ctrl);
+ (*ctrl)->control_ldosram_core_voltage_ctrl);
}
/*
* i. unconditionally for all 4430
* ii. only if un-trimmed for 4460
*/
- if (!readl(&ctrl->control_efuse_1))
- writel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);
+ if (!readl((*ctrl)->control_efuse_1))
+ writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
- if ((omap4_rev < OMAP4460_ES1_0) || !readl(&ctrl->control_efuse_2))
- writel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);
+ if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
+ writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
}
#endif /* CONFIG_SPL_BUILD */
--- /dev/null
+/*
+ *
+ * HW regs data for OMAP4
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap4_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a004100,
+ .cm_clksel_abe = 0x4a004108,
+ .cm_dll_ctrl = 0x4a004110,
+ .cm_clkmode_dpll_core = 0x4a004120,
+ .cm_idlest_dpll_core = 0x4a004124,
+ .cm_autoidle_dpll_core = 0x4a004128,
+ .cm_clksel_dpll_core = 0x4a00412c,
+ .cm_div_m2_dpll_core = 0x4a004130,
+ .cm_div_m3_dpll_core = 0x4a004134,
+ .cm_div_m4_dpll_core = 0x4a004138,
+ .cm_div_m5_dpll_core = 0x4a00413c,
+ .cm_div_m6_dpll_core = 0x4a004140,
+ .cm_div_m7_dpll_core = 0x4a004144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a004148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+ .cm_emu_override_dpll_core = 0x4a004150,
+ .cm_clkmode_dpll_mpu = 0x4a004160,
+ .cm_idlest_dpll_mpu = 0x4a004164,
+ .cm_autoidle_dpll_mpu = 0x4a004168,
+ .cm_clksel_dpll_mpu = 0x4a00416c,
+ .cm_div_m2_dpll_mpu = 0x4a004170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+ .cm_bypclk_dpll_mpu = 0x4a00419c,
+ .cm_clkmode_dpll_iva = 0x4a0041a0,
+ .cm_idlest_dpll_iva = 0x4a0041a4,
+ .cm_autoidle_dpll_iva = 0x4a0041a8,
+ .cm_clksel_dpll_iva = 0x4a0041ac,
+ .cm_div_m4_dpll_iva = 0x4a0041b8,
+ .cm_div_m5_dpll_iva = 0x4a0041bc,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+ .cm_bypclk_dpll_iva = 0x4a0041dc,
+ .cm_clkmode_dpll_abe = 0x4a0041e0,
+ .cm_idlest_dpll_abe = 0x4a0041e4,
+ .cm_autoidle_dpll_abe = 0x4a0041e8,
+ .cm_clksel_dpll_abe = 0x4a0041ec,
+ .cm_div_m2_dpll_abe = 0x4a0041f0,
+ .cm_div_m3_dpll_abe = 0x4a0041f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+ .cm_clkmode_dpll_ddrphy = 0x4a004220,
+ .cm_idlest_dpll_ddrphy = 0x4a004224,
+ .cm_autoidle_dpll_ddrphy = 0x4a004228,
+ .cm_clksel_dpll_ddrphy = 0x4a00422c,
+ .cm_div_m2_dpll_ddrphy = 0x4a004230,
+ .cm_div_m4_dpll_ddrphy = 0x4a004238,
+ .cm_div_m5_dpll_ddrphy = 0x4a00423c,
+ .cm_div_m6_dpll_ddrphy = 0x4a004240,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+ .cm_shadow_freq_config1 = 0x4a004260,
+ .cm_mpu_mpu_clkctrl = 0x4a004320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a004400,
+ .cm_dsp_dsp_clkctrl = 0x4a004420,
+
+ /* cm1.abe */
+ .cm1_abe_clkstctrl = 0x4a004500,
+ .cm1_abe_l4abe_clkctrl = 0x4a004520,
+ .cm1_abe_aess_clkctrl = 0x4a004528,
+ .cm1_abe_pdm_clkctrl = 0x4a004530,
+ .cm1_abe_dmic_clkctrl = 0x4a004538,
+ .cm1_abe_mcasp_clkctrl = 0x4a004540,
+ .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+ .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+ .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+ .cm1_abe_slimbus_clkctrl = 0x4a004560,
+ .cm1_abe_timer5_clkctrl = 0x4a004568,
+ .cm1_abe_timer6_clkctrl = 0x4a004570,
+ .cm1_abe_timer7_clkctrl = 0x4a004578,
+ .cm1_abe_timer8_clkctrl = 0x4a004580,
+ .cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+ /* cm2.ckgen */
+ .cm_clksel_mpu_m3_iss_root = 0x4a008100,
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_scale_fclk = 0x4a008108,
+ .cm_core_dvfs_perf1 = 0x4a008110,
+ .cm_core_dvfs_perf2 = 0x4a008114,
+ .cm_core_dvfs_perf3 = 0x4a008118,
+ .cm_core_dvfs_perf4 = 0x4a00811c,
+ .cm_core_dvfs_current = 0x4a008124,
+ .cm_iva_dvfs_perf_tesla = 0x4a008128,
+ .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+ .cm_iva_dvfs_perf_abe = 0x4a008130,
+ .cm_iva_dvfs_current = 0x4a008138,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_m4_dpll_per = 0x4a008158,
+ .cm_div_m5_dpll_per = 0x4a00815c,
+ .cm_div_m6_dpll_per = 0x4a008160,
+ .cm_div_m7_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_emu_override_dpll_per = 0x4a008170,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_unipro = 0x4a0081c0,
+ .cm_idlest_dpll_unipro = 0x4a0081c4,
+ .cm_autoidle_dpll_unipro = 0x4a0081c8,
+ .cm_clksel_dpll_unipro = 0x4a0081cc,
+ .cm_div_m2_dpll_unipro = 0x4a0081d0,
+ .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+ .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+ /* cm2.core */
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_2_clkstctrl = 0x4a008800,
+ .cm_l3_2_dynamicdep = 0x4a008808,
+ .cm_l3_2_l3_2_clkctrl = 0x4a008820,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_memif_emif_h1_clkctrl = 0x4a008b50,
+ .cm_memif_emif_h2_clkctrl = 0x4a008b58,
+ .cm_memif_dll_h_clkctrl = 0x4a008b60,
+ .cm_c2c_clkstctrl = 0x4a008c00,
+ .cm_c2c_staticdep = 0x4a008c04,
+ .cm_c2c_dynamicdep = 0x4a008c08,
+ .cm_c2c_sad2d_clkctrl = 0x4a008c20,
+ .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+ .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
+ .cm_ivahd_clkstctrl = 0x4a008f00,
+
+ /* cm2.ivahd */
+ .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+ .cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009000,
+ .cm_cam_iss_clkctrl = 0x4a009020,
+ .cm_cam_fdif_clkctrl = 0x4a009028,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009100,
+ .cm_dss_dss_clkctrl = 0x4a009120,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009200,
+ .cm_sgx_sgx_clkctrl = 0x4a009220,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009300,
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+ .cm_l3init_hsi_clkctrl = 0x4a009338,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+ .cm_l3init_p1500_clkctrl = 0x4a009378,
+ .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+ .cm_l3init_usbphy_clkctrl = 0x4a0093e0,
+
+ /* cm2.l4per */
+ .cm_l4per_clkstctrl = 0x4a009400,
+ .cm_l4per_dynamicdep = 0x4a009408,
+ .cm_l4per_adc_clkctrl = 0x4a009420,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009428,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009430,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009438,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009440,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009448,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009450,
+ .cm_l4per_elm_clkctrl = 0x4a009458,
+ .cm_l4per_gpio2_clkctrl = 0x4a009460,
+ .cm_l4per_gpio3_clkctrl = 0x4a009468,
+ .cm_l4per_gpio4_clkctrl = 0x4a009470,
+ .cm_l4per_gpio5_clkctrl = 0x4a009478,
+ .cm_l4per_gpio6_clkctrl = 0x4a009480,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009488,
+ .cm_l4per_hecc1_clkctrl = 0x4a009490,
+ .cm_l4per_hecc2_clkctrl = 0x4a009498,
+ .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0094c0,
+ .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+ .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+ .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
+ .cm_l4per_mgate_clkctrl = 0x4a0094e8,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009500,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009508,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+ .cm_l4per_msprohg_clkctrl = 0x4a009530,
+ .cm_l4per_slimbus2_clkctrl = 0x4a009538,
+ .cm_l4per_uart1_clkctrl = 0x4a009540,
+ .cm_l4per_uart2_clkctrl = 0x4a009548,
+ .cm_l4per_uart3_clkctrl = 0x4a009550,
+ .cm_l4per_uart4_clkctrl = 0x4a009558,
+ .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+ .cm_l4per_i2c5_clkctrl = 0x4a009568,
+ .cm_l4sec_clkstctrl = 0x4a009580,
+ .cm_l4sec_staticdep = 0x4a009584,
+ .cm_l4sec_dynamicdep = 0x4a009588,
+ .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+ .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+ .cm_l4sec_rng_clkctrl = 0x4a0095c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4a30610c,
+ .cm_sys_clksel = 0x4a306110,
+ .cm_wkup_clkstctrl = 0x4a307800,
+ .cm_wkup_l4wkup_clkctrl = 0x4a307820,
+ .cm_wkup_wdtimer1_clkctrl = 0x4a307828,
+ .cm_wkup_wdtimer2_clkctrl = 0x4a307830,
+ .cm_wkup_gpio1_clkctrl = 0x4a307838,
+ .cm_wkup_gptimer1_clkctrl = 0x4a307840,
+ .cm_wkup_gptimer12_clkctrl = 0x4a307848,
+ .cm_wkup_synctimer_clkctrl = 0x4a307850,
+ .cm_wkup_usim_clkctrl = 0x4a307858,
+ .cm_wkup_sarram_clkctrl = 0x4a307860,
+ .cm_wkup_keyboard_clkctrl = 0x4a307878,
+ .cm_wkup_rtc_clkctrl = 0x4a307880,
+ .cm_wkup_bandgap_clkctrl = 0x4a307888,
+ .prm_vc_val_bypass = 0x4a307ba0,
+ .prm_vc_cfg_channel = 0x4a307ba4,
+ .prm_vc_cfg_i2c_mode = 0x4a307ba8,
+ .prm_vc_cfg_i2c_clk = 0x4a307bac,
+};
+
+struct omap_sys_ctrl_regs const omap4_ctrl = {
+ .control_id_code = 0x4A002204,
+ .control_std_fuse_opp_bgap = 0x4a002260,
+ .control_status = 0x4a0022c4,
+ .control_ldosram_iva_voltage_ctrl = 0x4A002320,
+ .control_ldosram_mpu_voltage_ctrl = 0x4A002324,
+ .control_ldosram_core_voltage_ctrl = 0x4A002328,
+ .control_pbiaslite = 0x4A100600,
+ .control_lpddr2io1_0 = 0x4A100638,
+ .control_lpddr2io1_1 = 0x4A10063C,
+ .control_lpddr2io1_2 = 0x4A100640,
+ .control_lpddr2io1_3 = 0x4A100644,
+ .control_lpddr2io2_0 = 0x4A100648,
+ .control_lpddr2io2_1 = 0x4A10064C,
+ .control_lpddr2io2_2 = 0x4A100650,
+ .control_lpddr2io2_3 = 0x4A100654,
+ .control_efuse_1 = 0x4A100700,
+ .control_efuse_2 = 0x4A100704,
+};
.emif_ddr_phy_ctlr_1 = 0x049ff418
};
-/* Dummy registers for OMAP44xx */
-const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80540300
+ .dmm_lisa_map_3 = 0x80540300,
+ .is_ma_present = 0x0
};
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
.dmm_lisa_map_0 = 0xFF020100,
.dmm_lisa_map_1 = 0,
.dmm_lisa_map_2 = 0,
- .dmm_lisa_map_3 = 0x80640300
+ .dmm_lisa_map_3 = 0x80640300,
+ .is_ma_present = 0x0
+};
+
+const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
+ .dmm_lisa_map_0 = 0xFF020100,
+ .dmm_lisa_map_1 = 0,
+ .dmm_lisa_map_2 = 0,
+ .dmm_lisa_map_3 = 0x80640300,
+ .is_ma_present = 0x1
};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
if (omap_rev == OMAP4430_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
- else
+ else if (omap_rev < OMAP4460_ES1_0)
*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
+ else
+ *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
__attribute__((weak, alias("emif_get_device_timings_sdp")));
#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
+
+const struct lpddr2_mr_regs mr_regs = {
+ .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
+ .mr2 = 0x4,
+ .mr3 = -1,
+ .mr10 = MR10_ZQ_ZQINIT,
+ .mr16 = MR16_REF_FULL_ARRAY
+};
+
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
+{
+ *regs = &mr_regs;
+}
LIB = $(obj)lib$(SOC).o
COBJS += hwinit.o
-COBJS += clocks.o
COBJS += emif.o
COBJS += sdram.o
+COBJS += prcm-regs.o
+COBJS += hw_data.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+++ /dev/null
-/*
- *
- * Clock initialization for OMAP5
- *
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- * Sricharan R <r.sricharan@ti.com>
- *
- * Based on previous work by:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- * Rajendra Nayak <rnayak@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/omap_common.h>
-#include <asm/arch/clocks.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/utils.h>
-#include <asm/omap_gpio.h>
-
-#ifndef CONFIG_SPL_BUILD
-/*
- * printing to console doesn't work unless
- * this code is executed from SPL
- */
-#define printf(fmt, args...)
-#define puts(s)
-#endif
-
-struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
-
-const u32 sys_clk_array[8] = {
- 12000000, /* 12 MHz */
- 0, /* NA */
- 16800000, /* 16.8 MHz */
- 19200000, /* 19.2 MHz */
- 26000000, /* 26 MHz */
- 0, /* NA */
- 38400000, /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
- {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
- {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
- {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
- {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
- {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
- {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
- {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
- {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
- {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
-};
-
-static const struct dpll_params
- core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
- {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
- {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
- {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
-};
-
-static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
- {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
- {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
- {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
-};
-
-static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
- {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
- {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
- {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with sys_clk as source */
-static const struct dpll_params
- abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
- {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-/* ABE M & N values with 32K clock as source */
-static const struct dpll_params abe_dpll_params_32k_196608khz = {
- 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
-};
-
-static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
- {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
- {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
- {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
- {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
- {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
-};
-
-void setup_post_dividers(u32 *const base, const struct dpll_params *params)
-{
- struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
-
- /* Setup post-dividers */
- if (params->m2 >= 0)
- writel(params->m2, &dpll_regs->cm_div_m2_dpll);
- if (params->m3 >= 0)
- writel(params->m3, &dpll_regs->cm_div_m3_dpll);
- if (params->h11 >= 0)
- writel(params->h11, &dpll_regs->cm_div_h11_dpll);
- if (params->h12 >= 0)
- writel(params->h12, &dpll_regs->cm_div_h12_dpll);
- if (params->h13 >= 0)
- writel(params->h13, &dpll_regs->cm_div_h13_dpll);
- if (params->h14 >= 0)
- writel(params->h14, &dpll_regs->cm_div_h14_dpll);
- if (params->h22 >= 0)
- writel(params->h22, &dpll_regs->cm_div_h22_dpll);
- if (params->h23 >= 0)
- writel(params->h23, &dpll_regs->cm_div_h23_dpll);
-}
-
-const struct dpll_params *get_mpu_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &mpu_dpll_params_800mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_core_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
-
- /* Configuring the DDR to be at 532mhz */
- return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
-}
-
-const struct dpll_params *get_per_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &per_dpll_params_768mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_iva_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &iva_dpll_params_2330mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_usb_dpll_params(void)
-{
- u32 sysclk_ind = get_sys_clk_index();
- return &usb_dpll_params_1920mhz[sysclk_ind];
-}
-
-const struct dpll_params *get_abe_dpll_params(void)
-{
-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
- u32 sysclk_ind = get_sys_clk_index();
- return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
-#else
- return &abe_dpll_params_32k_196608khz;
-#endif
-}
-
-/*
- * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
- * We set the maximum voltages allowed here because Smart-Reflex is not
- * enabled in bootloader. Voltage initialization in the kernel will set
- * these to the nominal values after enabling Smart-Reflex
- */
-void scale_vcores(void)
-{
- u32 volt_core, volt_mpu, volt_mm;
-
- omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
-
- /* Palmas settings */
- if (omap_revision() != OMAP5432_ES1_0) {
- volt_core = VDD_CORE;
- volt_mpu = VDD_MPU;
- volt_mm = VDD_MM;
- } else {
- volt_core = VDD_CORE_5432;
- volt_mpu = VDD_MPU_5432;
- volt_mm = VDD_MM_5432;
- }
-
- do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
- do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
- do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
-
- if (omap_revision() == OMAP5432_ES1_0) {
- /* Configure LDO SRAM "magic" bits */
- writel(2, &prcm->prm_sldo_core_setup);
- writel(2, &prcm->prm_sldo_mpu_setup);
- writel(2, &prcm->prm_sldo_mm_setup);
- }
-}
-
-u32 get_offset_code(u32 volt_offset)
-{
- u32 offset_code, step = 10000; /* 10 mV represented in uV */
-
- volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
-
- offset_code = (volt_offset + step - 1) / step;
-
- /*
- * Offset codes 1-6 all give the base voltage in Palmas
- * Offset code 0 switches OFF the SMPS
- */
- return offset_code + 6;
-}
-
-/*
- * Enable essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_basic_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- &prcm->cm_l4per_clkstctrl,
- &prcm->cm_l3init_clkstctrl,
- &prcm->cm_memif_clkstctrl,
- &prcm->cm_l4cfg_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- &prcm->cm_l3_2_gpmc_clkctrl,
- &prcm->cm_memif_emif_1_clkctrl,
- &prcm->cm_memif_emif_2_clkctrl,
- &prcm->cm_l4cfg_l4_cfg_clkctrl,
- &prcm->cm_wkup_gpio1_clkctrl,
- &prcm->cm_l4per_gpio2_clkctrl,
- &prcm->cm_l4per_gpio3_clkctrl,
- &prcm->cm_l4per_gpio4_clkctrl,
- &prcm->cm_l4per_gpio5_clkctrl,
- &prcm->cm_l4per_gpio6_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_wkup_gptimer1_clkctrl,
- &prcm->cm_l3init_hsmmc1_clkctrl,
- &prcm->cm_l3init_hsmmc2_clkctrl,
- &prcm->cm_l4per_gptimer2_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_l4per_uart3_clkctrl,
- &prcm->cm_l4per_i2c1_clkctrl,
- 0
- };
-
- /* Enable optional additional functional clock for GPIO4 */
- setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
- GPIO4_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable 96 MHz clock for MMC1 & MMC2 */
- setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
- setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_MASK);
-
- /* Set the correct clock dividers for mmc */
- setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
- setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
- HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-
- /* Select 32KHz clock as the source of GPTIMER1 */
- setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
- GPTIMER1_CLKCTRL_CLKSEL_MASK);
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-
- /* Select 384Mhz for GPU as its the POR for ES1.0 */
- setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_HYD_GCLK_MASK);
- setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
- CLKSEL_GPU_CORE_GCLK_MASK);
-
- /* Enable SCRM OPT clocks for PER and CORE dpll */
- setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_PER_MASK);
- setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
- OPTFCLKEN_SCRM_CORE_MASK);
-}
-
-void enable_basic_uboot_clocks(void)
-{
- u32 *const clk_domains_essential[] = {
- 0
- };
-
- u32 *const clk_modules_hw_auto_essential[] = {
- 0
- };
-
- u32 *const clk_modules_explicit_en_essential[] = {
- &prcm->cm_l4per_mcspi1_clkctrl,
- &prcm->cm_l4per_i2c2_clkctrl,
- &prcm->cm_l4per_i2c3_clkctrl,
- &prcm->cm_l4per_i2c4_clkctrl,
- &prcm->cm_l3init_hsusbtll_clkctrl,
- &prcm->cm_l3init_hsusbhost_clkctrl,
- &prcm->cm_l3init_fsusb_clkctrl,
- 0
- };
-
- do_enable_clocks(clk_domains_essential,
- clk_modules_hw_auto_essential,
- clk_modules_explicit_en_essential,
- 1);
-}
-
-/*
- * Enable non-essential clock domains, modules and
- * do some additional special settings needed
- */
-void enable_non_essential_clocks(void)
-{
- u32 *const clk_domains_non_essential[] = {
- &prcm->cm_mpu_m3_clkstctrl,
- &prcm->cm_ivahd_clkstctrl,
- &prcm->cm_dsp_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sgx_clkstctrl,
- &prcm->cm1_abe_clkstctrl,
- &prcm->cm_c2c_clkstctrl,
- &prcm->cm_cam_clkstctrl,
- &prcm->cm_dss_clkstctrl,
- &prcm->cm_sdma_clkstctrl,
- 0
- };
-
- u32 *const clk_modules_hw_auto_non_essential[] = {
- &prcm->cm_mpu_m3_mpu_m3_clkctrl,
- &prcm->cm_ivahd_ivahd_clkctrl,
- &prcm->cm_ivahd_sl2_clkctrl,
- &prcm->cm_dsp_dsp_clkctrl,
- &prcm->cm_l3instr_l3_3_clkctrl,
- &prcm->cm_l3instr_l3_instr_clkctrl,
- &prcm->cm_l3instr_intrconn_wp1_clkctrl,
- &prcm->cm_l3init_hsi_clkctrl,
- &prcm->cm_l4per_hdq1w_clkctrl,
- 0
- };
-
- u32 *const clk_modules_explicit_en_non_essential[] = {
- &prcm->cm1_abe_aess_clkctrl,
- &prcm->cm1_abe_pdm_clkctrl,
- &prcm->cm1_abe_dmic_clkctrl,
- &prcm->cm1_abe_mcasp_clkctrl,
- &prcm->cm1_abe_mcbsp1_clkctrl,
- &prcm->cm1_abe_mcbsp2_clkctrl,
- &prcm->cm1_abe_mcbsp3_clkctrl,
- &prcm->cm1_abe_slimbus_clkctrl,
- &prcm->cm1_abe_timer5_clkctrl,
- &prcm->cm1_abe_timer6_clkctrl,
- &prcm->cm1_abe_timer7_clkctrl,
- &prcm->cm1_abe_timer8_clkctrl,
- &prcm->cm1_abe_wdt3_clkctrl,
- &prcm->cm_l4per_gptimer9_clkctrl,
- &prcm->cm_l4per_gptimer10_clkctrl,
- &prcm->cm_l4per_gptimer11_clkctrl,
- &prcm->cm_l4per_gptimer3_clkctrl,
- &prcm->cm_l4per_gptimer4_clkctrl,
- &prcm->cm_l4per_mcspi2_clkctrl,
- &prcm->cm_l4per_mcspi3_clkctrl,
- &prcm->cm_l4per_mcspi4_clkctrl,
- &prcm->cm_l4per_mmcsd3_clkctrl,
- &prcm->cm_l4per_mmcsd4_clkctrl,
- &prcm->cm_l4per_mmcsd5_clkctrl,
- &prcm->cm_l4per_uart1_clkctrl,
- &prcm->cm_l4per_uart2_clkctrl,
- &prcm->cm_l4per_uart4_clkctrl,
- &prcm->cm_wkup_keyboard_clkctrl,
- &prcm->cm_wkup_wdtimer2_clkctrl,
- &prcm->cm_cam_iss_clkctrl,
- &prcm->cm_cam_fdif_clkctrl,
- &prcm->cm_dss_dss_clkctrl,
- &prcm->cm_sgx_sgx_clkctrl,
- 0
- };
-
- /* Enable optional functional clock for ISS */
- setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
-
- /* Enable all optional functional clocks of DSS */
- setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
-
- do_enable_clocks(clk_domains_non_essential,
- clk_modules_hw_auto_non_essential,
- clk_modules_explicit_en_non_essential,
- 0);
-
- /* Put camera module in no sleep mode */
- clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
- CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
- MODULE_CLKCTRL_MODULEMODE_SHIFT);
-}
--- /dev/null
+/*
+ *
+ * HW data initialization for OMAP5
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+#include <asm/arch/clocks.h>
+#include <asm/omap_gpio.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+
+struct prcm_regs const **prcm =
+ (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
+struct dplls const **dplls_data =
+ (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
+struct vcores_data const **omap_vcores =
+ (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
+
+/* OPP HIGH FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
+ {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
+static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
+ {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP NOM FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
+ {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES1.0 */
+static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
+ {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* OPP LOW FREQUENCY for ES2.0 */
+static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
+ {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
+ {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+ {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
+ {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
+ {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
+ {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
+ {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
+ {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
+ {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
+ {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
+ {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
+ {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
+ {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
+ {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
+ {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params
+ core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
+ {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
+ {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
+ {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
+ {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
+ {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
+ {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
+ {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
+ {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
+};
+
+static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
+ {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with sys_clk as source */
+static const struct dpll_params
+ abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
+ {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
+};
+
+/* ABE M & N values with 32K clock as source */
+static const struct dpll_params abe_dpll_params_32k_196608khz = {
+ 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
+};
+
+static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
+ {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+ {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+};
+
+static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
+ {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
+ {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
+ {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
+ {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
+ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
+ {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
+ {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
+};
+
+struct dplls omap5_dplls_es1 = {
+ .mpu = mpu_dpll_params_800mhz,
+ .core = core_dpll_params_2128mhz_ddr532,
+ .per = per_dpll_params_768mhz,
+ .iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls omap5_dplls_es2 = {
+ .mpu = mpu_dpll_params_1100mhz,
+ .core = core_dpll_params_2128mhz_ddr532_es2,
+ .per = per_dpll_params_768mhz_es2,
+ .iva = iva_dpll_params_2330mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
+struct dplls dra7xx_dplls = {
+ .mpu = mpu_dpll_params_1ghz,
+ .core = core_dpll_params_2128mhz_ddr532_dra7xx,
+ .per = per_dpll_params_768mhz_dra7xx,
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = ddr_dpll_params_1066mhz,
+};
+
+struct pmic_data palmas = {
+ .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
+ .step = 10000, /* 10 mV represented in uV */
+ /*
+ * Offset codes 1-6 all give the base voltage in Palmas
+ * Offset code 0 switches OFF the SMPS
+ */
+ .start_code = 6,
+};
+
+struct vcores_data omap5430_volts = {
+ .mpu.value = VDD_MPU,
+ .mpu.addr = SMPS_REG_ADDR_12_MPU,
+ .mpu.pmic = &palmas,
+
+ .core.value = VDD_CORE,
+ .core.addr = SMPS_REG_ADDR_8_CORE,
+ .core.pmic = &palmas,
+
+ .mm.value = VDD_MM,
+ .mm.addr = SMPS_REG_ADDR_45_IVA,
+ .mm.pmic = &palmas,
+};
+
+struct vcores_data omap5430_volts_es2 = {
+ .mpu.value = VDD_MPU_ES2,
+ .mpu.addr = SMPS_REG_ADDR_12_MPU,
+ .mpu.pmic = &palmas,
+
+ .core.value = VDD_CORE_ES2,
+ .core.addr = SMPS_REG_ADDR_8_CORE,
+ .core.pmic = &palmas,
+
+ .mm.value = VDD_MM_ES2,
+ .mm.addr = SMPS_REG_ADDR_45_IVA,
+ .mm.pmic = &palmas,
+};
+
+/*
+ * Enable essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_basic_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ (*prcm)->cm_l4per_clkstctrl,
+ (*prcm)->cm_l3init_clkstctrl,
+ (*prcm)->cm_memif_clkstctrl,
+ (*prcm)->cm_l4cfg_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ (*prcm)->cm_l3_gpmc_clkctrl,
+ (*prcm)->cm_memif_emif_1_clkctrl,
+ (*prcm)->cm_memif_emif_2_clkctrl,
+ (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
+ (*prcm)->cm_wkup_gpio1_clkctrl,
+ (*prcm)->cm_l4per_gpio2_clkctrl,
+ (*prcm)->cm_l4per_gpio3_clkctrl,
+ (*prcm)->cm_l4per_gpio4_clkctrl,
+ (*prcm)->cm_l4per_gpio5_clkctrl,
+ (*prcm)->cm_l4per_gpio6_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_wkup_gptimer1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc1_clkctrl,
+ (*prcm)->cm_l3init_hsmmc2_clkctrl,
+ (*prcm)->cm_l4per_gptimer2_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_l4per_uart3_clkctrl,
+ (*prcm)->cm_l4per_i2c1_clkctrl,
+ 0
+ };
+
+ /* Enable optional additional functional clock for GPIO4 */
+ setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
+ GPIO4_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable 96 MHz clock for MMC1 & MMC2 */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_MASK);
+
+ /* Set the correct clock dividers for mmc */
+ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+ setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+ HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+
+ /* Select 32KHz clock as the source of GPTIMER1 */
+ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
+ GPTIMER1_CLKCTRL_CLKSEL_MASK);
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+
+ /* Select 384Mhz for GPU as its the POR for ES1.0 */
+ setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
+ CLKSEL_GPU_HYD_GCLK_MASK);
+ setbits_le32((*prcm)->cm_sgx_sgx_clkctrl,
+ CLKSEL_GPU_CORE_GCLK_MASK);
+
+ /* Enable SCRM OPT clocks for PER and CORE dpll */
+ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+ OPTFCLKEN_SCRM_PER_MASK);
+ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
+ OPTFCLKEN_SCRM_CORE_MASK);
+}
+
+void enable_basic_uboot_clocks(void)
+{
+ u32 const clk_domains_essential[] = {
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_essential[] = {
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_essential[] = {
+ (*prcm)->cm_l4per_mcspi1_clkctrl,
+ (*prcm)->cm_l4per_i2c2_clkctrl,
+ (*prcm)->cm_l4per_i2c3_clkctrl,
+ (*prcm)->cm_l4per_i2c4_clkctrl,
+ (*prcm)->cm_l3init_hsusbtll_clkctrl,
+ (*prcm)->cm_l3init_hsusbhost_clkctrl,
+ (*prcm)->cm_l3init_fsusb_clkctrl,
+ 0
+ };
+
+ do_enable_clocks(clk_domains_essential,
+ clk_modules_hw_auto_essential,
+ clk_modules_explicit_en_essential,
+ 1);
+}
+
+/*
+ * Enable non-essential clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_non_essential_clocks(void)
+{
+ u32 const clk_domains_non_essential[] = {
+ (*prcm)->cm_mpu_m3_clkstctrl,
+ (*prcm)->cm_ivahd_clkstctrl,
+ (*prcm)->cm_dsp_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sgx_clkstctrl,
+ (*prcm)->cm1_abe_clkstctrl,
+ (*prcm)->cm_c2c_clkstctrl,
+ (*prcm)->cm_cam_clkstctrl,
+ (*prcm)->cm_dss_clkstctrl,
+ (*prcm)->cm_sdma_clkstctrl,
+ 0
+ };
+
+ u32 const clk_modules_hw_auto_non_essential[] = {
+ (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
+ (*prcm)->cm_ivahd_ivahd_clkctrl,
+ (*prcm)->cm_ivahd_sl2_clkctrl,
+ (*prcm)->cm_dsp_dsp_clkctrl,
+ (*prcm)->cm_l3instr_l3_3_clkctrl,
+ (*prcm)->cm_l3instr_l3_instr_clkctrl,
+ (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
+ (*prcm)->cm_l3init_hsi_clkctrl,
+ (*prcm)->cm_l4per_hdq1w_clkctrl,
+ 0
+ };
+
+ u32 const clk_modules_explicit_en_non_essential[] = {
+ (*prcm)->cm1_abe_aess_clkctrl,
+ (*prcm)->cm1_abe_pdm_clkctrl,
+ (*prcm)->cm1_abe_dmic_clkctrl,
+ (*prcm)->cm1_abe_mcasp_clkctrl,
+ (*prcm)->cm1_abe_mcbsp1_clkctrl,
+ (*prcm)->cm1_abe_mcbsp2_clkctrl,
+ (*prcm)->cm1_abe_mcbsp3_clkctrl,
+ (*prcm)->cm1_abe_slimbus_clkctrl,
+ (*prcm)->cm1_abe_timer5_clkctrl,
+ (*prcm)->cm1_abe_timer6_clkctrl,
+ (*prcm)->cm1_abe_timer7_clkctrl,
+ (*prcm)->cm1_abe_timer8_clkctrl,
+ (*prcm)->cm1_abe_wdt3_clkctrl,
+ (*prcm)->cm_l4per_gptimer9_clkctrl,
+ (*prcm)->cm_l4per_gptimer10_clkctrl,
+ (*prcm)->cm_l4per_gptimer11_clkctrl,
+ (*prcm)->cm_l4per_gptimer3_clkctrl,
+ (*prcm)->cm_l4per_gptimer4_clkctrl,
+ (*prcm)->cm_l4per_mcspi2_clkctrl,
+ (*prcm)->cm_l4per_mcspi3_clkctrl,
+ (*prcm)->cm_l4per_mcspi4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd3_clkctrl,
+ (*prcm)->cm_l4per_mmcsd4_clkctrl,
+ (*prcm)->cm_l4per_mmcsd5_clkctrl,
+ (*prcm)->cm_l4per_uart1_clkctrl,
+ (*prcm)->cm_l4per_uart2_clkctrl,
+ (*prcm)->cm_l4per_uart4_clkctrl,
+ (*prcm)->cm_wkup_keyboard_clkctrl,
+ (*prcm)->cm_wkup_wdtimer2_clkctrl,
+ (*prcm)->cm_cam_iss_clkctrl,
+ (*prcm)->cm_cam_fdif_clkctrl,
+ (*prcm)->cm_dss_dss_clkctrl,
+ (*prcm)->cm_sgx_sgx_clkctrl,
+ 0
+ };
+
+ /* Enable optional functional clock for ISS */
+ setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
+
+ /* Enable all optional functional clocks of DSS */
+ setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
+
+ do_enable_clocks(clk_domains_non_essential,
+ clk_modules_hw_auto_non_essential,
+ clk_modules_explicit_en_non_essential,
+ 0);
+
+ /* Put camera module in no sleep mode */
+ clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
+ MODULE_CLKCTRL_MODULEMODE_MASK,
+ CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
+ MODULE_CLKCTRL_MODULEMODE_SHIFT);
+}
+
+const struct ctrl_ioregs ioregs_omap5430 = {
+ .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+ .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+ .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+ .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+ .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es1 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
+const struct ctrl_ioregs ioregs_omap5432_es2 = {
+ .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_lpddr2ch = 0x0,
+ .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
+ .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
+ .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+};
+
+void hw_data_init(void)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+
+ case OMAP5430_ES1_0:
+ case OMAP5432_ES1_0:
+ *prcm = &omap5_es1_prcm;
+ *dplls_data = &omap5_dplls_es1;
+ *omap_vcores = &omap5430_volts;
+ *ctrl = &omap5_ctrl;
+ break;
+
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES2_0:
+ *prcm = &omap5_es2_prcm;
+ *dplls_data = &omap5_dplls_es2;
+ *omap_vcores = &omap5430_volts_es2;
+ *ctrl = &omap5_ctrl;
+ break;
+
+ case DRA752_ES1_0:
+ *prcm = &dra7xx_prcm;
+ *dplls_data = &dra7xx_dplls;
+ *omap_vcores = &omap5430_volts_es2;
+ *ctrl = &dra7xx_ctrl;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
+
+void get_ioregs(const struct ctrl_ioregs **regs)
+{
+ u32 omap_rev = omap_revision();
+
+ switch (omap_rev) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ *regs = &ioregs_omap5430;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &ioregs_omap5432_es1;
+ break;
+ case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
+ *regs = &ioregs_omap5432_es2;
+ break;
+
+ default:
+ printf("\n INVALID OMAP REVISION ");
+ }
+}
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
+#include <asm/arch/clocks.h>
#include <asm/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch1_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
- &(ioregs_base->control_ddrch2_1));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_0));
- writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
- &(ioregs_base->control_lpddr2ch1_1));
- writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
- &(ioregs_base->control_ddrio_0));
- writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
- &(ioregs_base->control_ddrio_1));
- writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
- &(ioregs_base->control_ddrio_2));
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddr3ch1_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch1_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch1_1));
-
- writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddr3ch2_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch2_0));
- writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
- &(ioregs_base->control_ddrch2_1));
-
- writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
- &(ioregs_base->control_ddrio_0));
- writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
- &(ioregs_base->control_ddrio_1));
- writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
- &(ioregs_base->control_ddrio_2));
+ const struct ctrl_ioregs *ioregs;
+
+ get_ioregs(&ioregs);
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
+
+ writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
+ writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
+
+ writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
+ writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
+ writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
/* omap5432 does not use lpddr2 */
- writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
- writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
+ writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
- writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- &(ioregs_base->control_emif1_sdram_config_ext));
- writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
- &(ioregs_base->control_emif2_sdram_config_ext));
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif1_sdram_config_ext);
+ writel(ioregs->ctrl_emif_sdram_config_ext,
+ (*ctrl)->control_emif2_sdram_config_ext);
/* Disable DLL select */
- io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+ io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
- &(ioregs_base->control_port_emif1_sdram_config));
+ (*ctrl)->control_port_emif1_sdram_config);
- io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+ io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
- &(ioregs_base->control_port_emif2_sdram_config));
+ (*ctrl)->control_port_emif2_sdram_config);
}
/*
void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(ds_mask << 16) | (ds_mask << 18);
- io_settings = readl(&(ioregs_base->control_smart1io_padconf_0)) &
+ io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
(~mask);
io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
(ds_45_ohm << 18) | (ds_60_ohm << 2);
- writel(io_settings, &(ioregs_base->control_smart1io_padconf_0));
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
/* Impedance settings Mcspi2 */
mask = (ds_mask << 30);
- io_settings = readl(&(ioregs_base->control_smart1io_padconf_1)) &
+ io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 30);
- writel(io_settings, &(ioregs_base->control_smart1io_padconf_1));
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
/* Impedance settings C2C 3,4 */
mask = (ds_mask << 14) | (ds_mask << 16);
- io_settings = readl(&(ioregs_base->control_smart1io_padconf_2)) &
+ io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
(~mask);
io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
- writel(io_settings, &(ioregs_base->control_smart1io_padconf_2));
+ writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
/* Slew rate settings EMMC, C2C 1,2 */
mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl(&(ioregs_base->control_smart2io_padconf_0)) &
+ io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
(~mask);
io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
- writel(io_settings, &(ioregs_base->control_smart2io_padconf_0));
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
/* Slew rate settings hsi2, Mcspi2 */
mask = (sc_mask << 24) | (sc_mask << 28);
- io_settings = readl(&(ioregs_base->control_smart2io_padconf_1)) &
+ io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
(~mask);
io_settings |= (sc_fast << 28) | (sc_fast << 24);
- writel(io_settings, &(ioregs_base->control_smart2io_padconf_1));
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
/* Slew rate settings C2C 3,4 */
mask = (sc_mask << 16) | (sc_mask << 18);
- io_settings = readl(&(ioregs_base->control_smart2io_padconf_2)) &
+ io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
(~mask);
io_settings |= (sc_na << 16) | (sc_na << 18);
- writel(io_settings, &(ioregs_base->control_smart2io_padconf_2));
+ writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
/* impedance and slew rate settings for usb */
mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
- io_settings = readl(&(ioregs_base->control_smart3io_padconf_1)) &
+ io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
(ds_60_ohm << 23) | (sc_fast << 20) |
(sc_fast << 17) | (sc_fast << 14);
- writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
+ writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
- if (omap_revision() <= OMAP5430_ES1_0)
+ if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
/* Efuse settings */
- writel(EFUSE_1, &(ioregs_base->control_efuse_1));
- writel(EFUSE_2, &(ioregs_base->control_efuse_2));
- writel(EFUSE_3, &(ioregs_base->control_efuse_3));
- writel(EFUSE_4, &(ioregs_base->control_efuse_4));
+ writel(EFUSE_1, (*ctrl)->control_efuse_1);
+ writel(EFUSE_2, (*ctrl)->control_efuse_2);
+ writel(EFUSE_3, (*ctrl)->control_efuse_3);
+ writel(EFUSE_4, (*ctrl)->control_efuse_4);
+}
+
+static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
+ {0x45, 0x1}, /* 12 MHz */
+ {-1, -1}, /* 13 MHz */
+ {0x63, 0x2}, /* 16.8 MHz */
+ {0x57, 0x2}, /* 19.2 MHz */
+ {0x20, 0x1}, /* 26 MHz */
+ {-1, -1}, /* 27 MHz */
+ {0x41, 0x3} /* 38.4 MHz */
+};
+
+void srcomp_enable(void)
+{
+ u32 srcomp_value, mul_factor, div_factor, clk_val, i;
+ u32 sysclk_ind = get_sys_clk_index();
+ u32 omap_rev = omap_revision();
+
+ mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
+ div_factor = srcomp_parameters[sysclk_ind].divide_factor;
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &=
+ ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor << DIVIDE_FACTOR_XS_SHIFT);
+ writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
+ clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~PWRDWN_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+
+ while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+ & SRCODE_READ_XS_MASK) >>
+ SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+ } else {
+ srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
+ DIVIDE_FACTOR_XS_MASK);
+ srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
+ (div_factor << DIVIDE_FACTOR_XS_SHIFT);
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ for (i = 0; i < 4; i++) {
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~OVERRIDE_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+
+ clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
+
+ clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+ clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
+ writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
+
+ for (i = 0; i < 4; i++) {
+ while (((readl((*ctrl)->control_srcomp_north_side + i*4)
+ & SRCODE_READ_XS_MASK) >>
+ SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_north_side + i*4);
+ srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value,
+ (*ctrl)->control_srcomp_north_side + i*4);
+ }
+
+ while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
+ SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
+ ;
+
+ srcomp_value =
+ readl((*ctrl)->control_srcomp_east_side_wkup);
+ srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
+ writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
+ }
}
#endif
void config_data_eye_leveling_samples(u32 emif_base)
{
- struct omap_sys_ctrl_regs *ioregs_base =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
- &(ioregs_base->control_emif1_sdram_config_ext));
+ (*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
- &(ioregs_base->control_emif2_sdram_config_ext));
+ (*ctrl)->control_emif2_sdram_config_ext);
}
void init_omap_revision(void)
*/
unsigned int rev = cortex_rev();
- switch (rev) {
- case MIDR_CORTEX_A15_R0P0:
- switch (readl(CONTROL_ID_CODE)) {
- case OMAP5430_CONTROL_ID_CODE_ES1_0:
- *omap_si_rev = OMAP5430_ES1_0;
- break;
- case OMAP5432_CONTROL_ID_CODE_ES1_0:
- default:
- *omap_si_rev = OMAP5432_ES1_0;
- break;
- }
+ switch (readl(CONTROL_ID_CODE)) {
+ case OMAP5430_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5430_ES1_0;
+ if (rev == MIDR_CORTEX_A15_R2P2)
+ *omap_si_rev = OMAP5430_ES2_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = OMAP5432_ES1_0;
+ if (rev == MIDR_CORTEX_A15_R2P2)
+ *omap_si_rev = OMAP5432_ES2_0;
+ break;
+ case OMAP5430_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5430_ES2_0;
+ break;
+ case OMAP5432_CONTROL_ID_CODE_ES2_0:
+ *omap_si_rev = OMAP5432_ES2_0;
+ break;
+ case DRA752_CONTROL_ID_CODE_ES1_0:
+ *omap_si_rev = DRA752_ES1_0;
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
* So use cold reset in case instead.
*/
if (omap_rev == OMAP5430_ES1_0)
- writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
+ writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
else
- writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
+ writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
+}
+
+u32 warm_reset(void)
+{
+ return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}
--- /dev/null
+/*
+ *
+ * HW regs data for OMAP5 Soc
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/omap_common.h>
+
+struct prcm_regs const omap5_es1_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a004100,
+ .cm_clksel_abe = 0x4a004108,
+ .cm_dll_ctrl = 0x4a004110,
+ .cm_clkmode_dpll_core = 0x4a004120,
+ .cm_idlest_dpll_core = 0x4a004124,
+ .cm_autoidle_dpll_core = 0x4a004128,
+ .cm_clksel_dpll_core = 0x4a00412c,
+ .cm_div_m2_dpll_core = 0x4a004130,
+ .cm_div_m3_dpll_core = 0x4a004134,
+ .cm_div_h11_dpll_core = 0x4a004138,
+ .cm_div_h12_dpll_core = 0x4a00413c,
+ .cm_div_h13_dpll_core = 0x4a004140,
+ .cm_div_h14_dpll_core = 0x4a004144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a004148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+ .cm_emu_override_dpll_core = 0x4a004150,
+ .cm_div_h22_dpllcore = 0x4a004154,
+ .cm_div_h23_dpll_core = 0x4a004158,
+ .cm_clkmode_dpll_mpu = 0x4a004160,
+ .cm_idlest_dpll_mpu = 0x4a004164,
+ .cm_autoidle_dpll_mpu = 0x4a004168,
+ .cm_clksel_dpll_mpu = 0x4a00416c,
+ .cm_div_m2_dpll_mpu = 0x4a004170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+ .cm_bypclk_dpll_mpu = 0x4a00419c,
+ .cm_clkmode_dpll_iva = 0x4a0041a0,
+ .cm_idlest_dpll_iva = 0x4a0041a4,
+ .cm_autoidle_dpll_iva = 0x4a0041a8,
+ .cm_clksel_dpll_iva = 0x4a0041ac,
+ .cm_div_h11_dpll_iva = 0x4a0041b8,
+ .cm_div_h12_dpll_iva = 0x4a0041bc,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+ .cm_bypclk_dpll_iva = 0x4a0041dc,
+ .cm_clkmode_dpll_abe = 0x4a0041e0,
+ .cm_idlest_dpll_abe = 0x4a0041e4,
+ .cm_autoidle_dpll_abe = 0x4a0041e8,
+ .cm_clksel_dpll_abe = 0x4a0041ec,
+ .cm_div_m2_dpll_abe = 0x4a0041f0,
+ .cm_div_m3_dpll_abe = 0x4a0041f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+ .cm_clkmode_dpll_ddrphy = 0x4a004220,
+ .cm_idlest_dpll_ddrphy = 0x4a004224,
+ .cm_autoidle_dpll_ddrphy = 0x4a004228,
+ .cm_clksel_dpll_ddrphy = 0x4a00422c,
+ .cm_div_m2_dpll_ddrphy = 0x4a004230,
+ .cm_div_h11_dpll_ddrphy = 0x4a004238,
+ .cm_div_h12_dpll_ddrphy = 0x4a00423c,
+ .cm_div_h13_dpll_ddrphy = 0x4a004240,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+ .cm_shadow_freq_config1 = 0x4a004260,
+ .cm_mpu_mpu_clkctrl = 0x4a004320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a004400,
+ .cm_dsp_dsp_clkctrl = 0x4a004420,
+
+ /* cm1.abe */
+ .cm1_abe_clkstctrl = 0x4a004500,
+ .cm1_abe_l4abe_clkctrl = 0x4a004520,
+ .cm1_abe_aess_clkctrl = 0x4a004528,
+ .cm1_abe_pdm_clkctrl = 0x4a004530,
+ .cm1_abe_dmic_clkctrl = 0x4a004538,
+ .cm1_abe_mcasp_clkctrl = 0x4a004540,
+ .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+ .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+ .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+ .cm1_abe_slimbus_clkctrl = 0x4a004560,
+ .cm1_abe_timer5_clkctrl = 0x4a004568,
+ .cm1_abe_timer6_clkctrl = 0x4a004570,
+ .cm1_abe_timer7_clkctrl = 0x4a004578,
+ .cm1_abe_timer8_clkctrl = 0x4a004580,
+ .cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+ /* cm2.ckgen */
+ .cm_clksel_mpu_m3_iss_root = 0x4a008100,
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_scale_fclk = 0x4a008108,
+ .cm_core_dvfs_perf1 = 0x4a008110,
+ .cm_core_dvfs_perf2 = 0x4a008114,
+ .cm_core_dvfs_perf3 = 0x4a008118,
+ .cm_core_dvfs_perf4 = 0x4a00811c,
+ .cm_core_dvfs_current = 0x4a008124,
+ .cm_iva_dvfs_perf_tesla = 0x4a008128,
+ .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+ .cm_iva_dvfs_perf_abe = 0x4a008130,
+ .cm_iva_dvfs_current = 0x4a008138,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_h11_dpll_per = 0x4a008158,
+ .cm_div_h12_dpll_per = 0x4a00815c,
+ .cm_div_h14_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_emu_override_dpll_per = 0x4a008170,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_unipro = 0x4a0081c0,
+ .cm_idlest_dpll_unipro = 0x4a0081c4,
+ .cm_autoidle_dpll_unipro = 0x4a0081c8,
+ .cm_clksel_dpll_unipro = 0x4a0081cc,
+ .cm_div_m2_dpll_unipro = 0x4a0081d0,
+ .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+ .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+
+ /* cm2.core */
+ .cm_coreaon_bandgap_clkctrl = 0x4a008648,
+ .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_2_clkstctrl = 0x4a008800,
+ .cm_l3_2_dynamicdep = 0x4a008808,
+ .cm_l3_2_l3_2_clkctrl = 0x4a008820,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_memif_emif_h1_clkctrl = 0x4a008b50,
+ .cm_memif_emif_h2_clkctrl = 0x4a008b58,
+ .cm_memif_dll_h_clkctrl = 0x4a008b60,
+ .cm_c2c_clkstctrl = 0x4a008c00,
+ .cm_c2c_staticdep = 0x4a008c04,
+ .cm_c2c_dynamicdep = 0x4a008c08,
+ .cm_c2c_sad2d_clkctrl = 0x4a008c20,
+ .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+ .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+
+ /* cm2.ivahd */
+ .cm_ivahd_clkstctrl = 0x4a008f00,
+ .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+ .cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009000,
+ .cm_cam_iss_clkctrl = 0x4a009020,
+ .cm_cam_fdif_clkctrl = 0x4a009028,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009100,
+ .cm_dss_dss_clkctrl = 0x4a009120,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009200,
+ .cm_sgx_sgx_clkctrl = 0x4a009220,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009300,
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+ .cm_l3init_hsi_clkctrl = 0x4a009338,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
+ .cm_l3init_p1500_clkctrl = 0x4a009378,
+ .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
+ .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+
+ /* cm2.l4per */
+ .cm_l4per_clkstctrl = 0x4a009400,
+ .cm_l4per_dynamicdep = 0x4a009408,
+ .cm_l4per_adc_clkctrl = 0x4a009420,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009428,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009430,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009438,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009440,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009448,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009450,
+ .cm_l4per_elm_clkctrl = 0x4a009458,
+ .cm_l4per_gpio2_clkctrl = 0x4a009460,
+ .cm_l4per_gpio3_clkctrl = 0x4a009468,
+ .cm_l4per_gpio4_clkctrl = 0x4a009470,
+ .cm_l4per_gpio5_clkctrl = 0x4a009478,
+ .cm_l4per_gpio6_clkctrl = 0x4a009480,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009488,
+ .cm_l4per_hecc1_clkctrl = 0x4a009490,
+ .cm_l4per_hecc2_clkctrl = 0x4a009498,
+ .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0094c0,
+ .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
+ .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
+ .cm_l4per_mgate_clkctrl = 0x4a0094e8,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009500,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009508,
+ .cm_l4per_gpio7_clkctrl = 0x4a009510,
+ .cm_l4per_gpio8_clkctrl = 0x4a009518,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
+ .cm_l4per_msprohg_clkctrl = 0x4a009530,
+ .cm_l4per_slimbus2_clkctrl = 0x4a009538,
+ .cm_l4per_uart1_clkctrl = 0x4a009540,
+ .cm_l4per_uart2_clkctrl = 0x4a009548,
+ .cm_l4per_uart3_clkctrl = 0x4a009550,
+ .cm_l4per_uart4_clkctrl = 0x4a009558,
+ .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
+ .cm_l4per_i2c5_clkctrl = 0x4a009568,
+ .cm_l4per_uart5_clkctrl = 0x4a009570,
+ .cm_l4per_uart6_clkctrl = 0x4a009578,
+ .cm_l4sec_clkstctrl = 0x4a009580,
+ .cm_l4sec_staticdep = 0x4a009584,
+ .cm_l4sec_dynamicdep = 0x4a009588,
+ .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
+ .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
+ .cm_l4sec_rng_clkctrl = 0x4a0095c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4ae0610c,
+ .cm_sys_clksel = 0x4ae06110,
+ .cm_wkup_clkstctrl = 0x4ae07800,
+ .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
+ .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
+ .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
+ .cm_wkup_gpio1_clkctrl = 0x4ae07838,
+ .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
+ .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
+ .cm_wkup_synctimer_clkctrl = 0x4ae07850,
+ .cm_wkup_usim_clkctrl = 0x4ae07858,
+ .cm_wkup_sarram_clkctrl = 0x4ae07860,
+ .cm_wkup_keyboard_clkctrl = 0x4ae07878,
+ .cm_wkup_rtc_clkctrl = 0x4ae07880,
+ .cm_wkup_bandgap_clkctrl = 0x4ae07888,
+ .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
+ .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
+ .prm_rstctrl = 0x4ae07b00,
+ .prm_rstst = 0x4ae07b04,
+ .prm_vc_val_bypass = 0x4ae07ba0,
+ .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
+ .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
+ .prm_sldo_core_setup = 0x4ae07bc4,
+ .prm_sldo_core_ctrl = 0x4ae07bc8,
+ .prm_sldo_mpu_setup = 0x4ae07bcc,
+ .prm_sldo_mpu_ctrl = 0x4ae07bd0,
+ .prm_sldo_mm_setup = 0x4ae07bd4,
+ .prm_sldo_mm_ctrl = 0x4ae07bd8,
+};
+
+struct omap_sys_ctrl_regs const omap5_ctrl = {
+ .control_status = 0x4A002134,
+ .control_paconf_global = 0x4A002DA0,
+ .control_paconf_mode = 0x4A002DA4,
+ .control_smart1io_padconf_0 = 0x4A002DA8,
+ .control_smart1io_padconf_1 = 0x4A002DAC,
+ .control_smart1io_padconf_2 = 0x4A002DB0,
+ .control_smart2io_padconf_0 = 0x4A002DB4,
+ .control_smart2io_padconf_1 = 0x4A002DB8,
+ .control_smart2io_padconf_2 = 0x4A002DBC,
+ .control_smart3io_padconf_0 = 0x4A002DC0,
+ .control_smart3io_padconf_1 = 0x4A002DC4,
+ .control_pbias = 0x4A002E00,
+ .control_i2c_0 = 0x4A002E04,
+ .control_camera_rx = 0x4A002E08,
+ .control_hdmi_tx_phy = 0x4A002E0C,
+ .control_uniportm = 0x4A002E10,
+ .control_dsiphy = 0x4A002E14,
+ .control_mcbsplp = 0x4A002E18,
+ .control_usb2phycore = 0x4A002E1C,
+ .control_hdmi_1 = 0x4A002E20,
+ .control_hsi = 0x4A002E24,
+ .control_ddr3ch1_0 = 0x4A002E30,
+ .control_ddr3ch2_0 = 0x4A002E34,
+ .control_ddrch1_0 = 0x4A002E38,
+ .control_ddrch1_1 = 0x4A002E3C,
+ .control_ddrch2_0 = 0x4A002E40,
+ .control_ddrch2_1 = 0x4A002E44,
+ .control_lpddr2ch1_0 = 0x4A002E48,
+ .control_lpddr2ch1_1 = 0x4A002E4C,
+ .control_ddrio_0 = 0x4A002E50,
+ .control_ddrio_1 = 0x4A002E54,
+ .control_ddrio_2 = 0x4A002E58,
+ .control_hyst_1 = 0x4A002E5C,
+ .control_usbb_hsic_control = 0x4A002E60,
+ .control_c2c = 0x4A002E64,
+ .control_core_control_spare_rw = 0x4A002E68,
+ .control_core_control_spare_r = 0x4A002E6C,
+ .control_core_control_spare_r_c0 = 0x4A002E70,
+ .control_srcomp_north_side = 0x4A002E74,
+ .control_srcomp_south_side = 0x4A002E78,
+ .control_srcomp_east_side = 0x4A002E7C,
+ .control_srcomp_west_side = 0x4A002E80,
+ .control_srcomp_code_latch = 0x4A002E84,
+ .control_port_emif1_sdram_config = 0x4AE0C110,
+ .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
+ .control_port_emif2_sdram_config = 0x4AE0C118,
+ .control_emif1_sdram_config_ext = 0x4AE0C144,
+ .control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_smart1nopmio_padconf_0 = 0x4AE0CDA0,
+ .control_smart1nopmio_padconf_1 = 0x4AE0CDA4,
+ .control_padconf_mode = 0x4AE0CDA8,
+ .control_xtal_oscillator = 0x4AE0CDAC,
+ .control_i2c_2 = 0x4AE0CDB0,
+ .control_ckobuffer = 0x4AE0CDB4,
+ .control_wkup_control_spare_rw = 0x4AE0CDB8,
+ .control_wkup_control_spare_r = 0x4AE0CDBC,
+ .control_wkup_control_spare_r_c0 = 0x4AE0CDC0,
+ .control_srcomp_east_side_wkup = 0x4AE0CDC4,
+ .control_efuse_1 = 0x4AE0CDC8,
+ .control_efuse_2 = 0x4AE0CDCC,
+ .control_efuse_3 = 0x4AE0CDD0,
+ .control_efuse_4 = 0x4AE0CDD4,
+ .control_efuse_5 = 0x4AE0CDD8,
+ .control_efuse_6 = 0x4AE0CDDC,
+ .control_efuse_7 = 0x4AE0CDE0,
+ .control_efuse_8 = 0x4AE0CDE4,
+ .control_efuse_9 = 0x4AE0CDE8,
+ .control_efuse_10 = 0x4AE0CDEC,
+ .control_efuse_11 = 0x4AE0CDF0,
+ .control_efuse_12 = 0x4AE0CDF4,
+ .control_efuse_13 = 0x4AE0CDF8,
+};
+
+struct omap_sys_ctrl_regs const dra7xx_ctrl = {
+ .control_status = 0x4A002134,
+ .control_core_mmr_lock1 = 0x4A002540,
+ .control_core_mmr_lock2 = 0x4A002544,
+ .control_core_mmr_lock3 = 0x4A002548,
+ .control_core_mmr_lock4 = 0x4A00254C,
+ .control_core_mmr_lock5 = 0x4A002550,
+ .control_core_control_io1 = 0x4A002554,
+ .control_core_control_io2 = 0x4A002558,
+ .control_paconf_global = 0x4A002DA0,
+ .control_paconf_mode = 0x4A002DA4,
+ .control_smart1io_padconf_0 = 0x4A002DA8,
+ .control_smart1io_padconf_1 = 0x4A002DAC,
+ .control_smart1io_padconf_2 = 0x4A002DB0,
+ .control_smart2io_padconf_0 = 0x4A002DB4,
+ .control_smart2io_padconf_1 = 0x4A002DB8,
+ .control_smart2io_padconf_2 = 0x4A002DBC,
+ .control_smart3io_padconf_0 = 0x4A002DC0,
+ .control_smart3io_padconf_1 = 0x4A002DC4,
+ .control_pbias = 0x4A002E00,
+ .control_i2c_0 = 0x4A002E04,
+ .control_camera_rx = 0x4A002E08,
+ .control_hdmi_tx_phy = 0x4A002E0C,
+ .control_uniportm = 0x4A002E10,
+ .control_dsiphy = 0x4A002E14,
+ .control_mcbsplp = 0x4A002E18,
+ .control_usb2phycore = 0x4A002E1C,
+ .control_hdmi_1 = 0x4A002E20,
+ .control_hsi = 0x4A002E24,
+ .control_ddr3ch1_0 = 0x4A002E30,
+ .control_ddr3ch2_0 = 0x4A002E34,
+ .control_ddrch1_0 = 0x4A002E38,
+ .control_ddrch1_1 = 0x4A002E3C,
+ .control_ddrch2_0 = 0x4A002E40,
+ .control_ddrch2_1 = 0x4A002E44,
+ .control_lpddr2ch1_0 = 0x4A002E48,
+ .control_lpddr2ch1_1 = 0x4A002E4C,
+ .control_ddrio_0 = 0x4A002E50,
+ .control_ddrio_1 = 0x4A002E54,
+ .control_ddrio_2 = 0x4A002E58,
+ .control_hyst_1 = 0x4A002E5C,
+ .control_usbb_hsic_control = 0x4A002E60,
+ .control_c2c = 0x4A002E64,
+ .control_core_control_spare_rw = 0x4A002E68,
+ .control_core_control_spare_r = 0x4A002E6C,
+ .control_core_control_spare_r_c0 = 0x4A002E70,
+ .control_srcomp_north_side = 0x4A002E74,
+ .control_srcomp_south_side = 0x4A002E78,
+ .control_srcomp_east_side = 0x4A002E7C,
+ .control_srcomp_west_side = 0x4A002E80,
+ .control_srcomp_code_latch = 0x4A002E84,
+ .control_padconf_core_base = 0x4A003400,
+ .control_port_emif1_sdram_config = 0x4AE0C110,
+ .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
+ .control_port_emif2_sdram_config = 0x4AE0C118,
+ .control_emif1_sdram_config_ext = 0x4AE0C144,
+ .control_emif2_sdram_config_ext = 0x4AE0C148,
+ .control_padconf_mode = 0x4AE0C5A0,
+ .control_xtal_oscillator = 0x4AE0C5A4,
+ .control_i2c_2 = 0x4AE0C5A8,
+ .control_ckobuffer = 0x4AE0C5AC,
+ .control_wkup_control_spare_rw = 0x4AE0C5B0,
+ .control_wkup_control_spare_r = 0x4AE0C5B4,
+ .control_wkup_control_spare_r_c0 = 0x4AE0C5B8,
+ .control_srcomp_east_side_wkup = 0x4AE0C5BC,
+ .control_efuse_1 = 0x4AE0C5C0,
+ .control_efuse_2 = 0x4AE0C5C4,
+ .control_efuse_3 = 0x4AE0C5C8,
+ .control_efuse_4 = 0x4AE0C5CC,
+ .control_efuse_13 = 0x4AE0C5F0,
+};
+
+struct prcm_regs const omap5_es2_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a004100,
+ .cm_clksel_abe = 0x4a004108,
+ .cm_dll_ctrl = 0x4a004110,
+ .cm_clkmode_dpll_core = 0x4a004120,
+ .cm_idlest_dpll_core = 0x4a004124,
+ .cm_autoidle_dpll_core = 0x4a004128,
+ .cm_clksel_dpll_core = 0x4a00412c,
+ .cm_div_m2_dpll_core = 0x4a004130,
+ .cm_div_m3_dpll_core = 0x4a004134,
+ .cm_div_h11_dpll_core = 0x4a004138,
+ .cm_div_h12_dpll_core = 0x4a00413c,
+ .cm_div_h13_dpll_core = 0x4a004140,
+ .cm_div_h14_dpll_core = 0x4a004144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a004148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
+ .cm_div_h21_dpll_core = 0x4a004150,
+ .cm_div_h22_dpllcore = 0x4a004154,
+ .cm_div_h23_dpll_core = 0x4a004158,
+ .cm_div_h24_dpll_core = 0x4a00415c,
+ .cm_clkmode_dpll_mpu = 0x4a004160,
+ .cm_idlest_dpll_mpu = 0x4a004164,
+ .cm_autoidle_dpll_mpu = 0x4a004168,
+ .cm_clksel_dpll_mpu = 0x4a00416c,
+ .cm_div_m2_dpll_mpu = 0x4a004170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
+ .cm_bypclk_dpll_mpu = 0x4a00419c,
+ .cm_clkmode_dpll_iva = 0x4a0041a0,
+ .cm_idlest_dpll_iva = 0x4a0041a4,
+ .cm_autoidle_dpll_iva = 0x4a0041a8,
+ .cm_clksel_dpll_iva = 0x4a0041ac,
+ .cm_div_h11_dpll_iva = 0x4a0041b8,
+ .cm_div_h12_dpll_iva = 0x4a0041bc,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
+ .cm_bypclk_dpll_iva = 0x4a0041dc,
+ .cm_clkmode_dpll_abe = 0x4a0041e0,
+ .cm_idlest_dpll_abe = 0x4a0041e4,
+ .cm_autoidle_dpll_abe = 0x4a0041e8,
+ .cm_clksel_dpll_abe = 0x4a0041ec,
+ .cm_div_m2_dpll_abe = 0x4a0041f0,
+ .cm_div_m3_dpll_abe = 0x4a0041f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
+ .cm_clkmode_dpll_ddrphy = 0x4a004220,
+ .cm_idlest_dpll_ddrphy = 0x4a004224,
+ .cm_autoidle_dpll_ddrphy = 0x4a004228,
+ .cm_clksel_dpll_ddrphy = 0x4a00422c,
+ .cm_div_m2_dpll_ddrphy = 0x4a004230,
+ .cm_div_h11_dpll_ddrphy = 0x4a004238,
+ .cm_div_h12_dpll_ddrphy = 0x4a00423c,
+ .cm_div_h13_dpll_ddrphy = 0x4a004240,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
+ .cm_shadow_freq_config1 = 0x4a004260,
+ .cm_mpu_mpu_clkctrl = 0x4a004320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a004400,
+ .cm_dsp_dsp_clkctrl = 0x4a004420,
+
+ /* cm1.abe */
+ .cm1_abe_clkstctrl = 0x4a004500,
+ .cm1_abe_l4abe_clkctrl = 0x4a004520,
+ .cm1_abe_aess_clkctrl = 0x4a004528,
+ .cm1_abe_pdm_clkctrl = 0x4a004530,
+ .cm1_abe_dmic_clkctrl = 0x4a004538,
+ .cm1_abe_mcasp_clkctrl = 0x4a004540,
+ .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
+ .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
+ .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
+ .cm1_abe_slimbus_clkctrl = 0x4a004560,
+ .cm1_abe_timer5_clkctrl = 0x4a004568,
+ .cm1_abe_timer6_clkctrl = 0x4a004570,
+ .cm1_abe_timer7_clkctrl = 0x4a004578,
+ .cm1_abe_timer8_clkctrl = 0x4a004580,
+ .cm1_abe_wdt3_clkctrl = 0x4a004588,
+
+
+
+ /* cm2.ckgen */
+ .cm_clksel_mpu_m3_iss_root = 0x4a008100,
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_scale_fclk = 0x4a008108,
+ .cm_core_dvfs_perf1 = 0x4a008110,
+ .cm_core_dvfs_perf2 = 0x4a008114,
+ .cm_core_dvfs_perf3 = 0x4a008118,
+ .cm_core_dvfs_perf4 = 0x4a00811c,
+ .cm_core_dvfs_current = 0x4a008124,
+ .cm_iva_dvfs_perf_tesla = 0x4a008128,
+ .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
+ .cm_iva_dvfs_perf_abe = 0x4a008130,
+ .cm_iva_dvfs_current = 0x4a008138,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_h11_dpll_per = 0x4a008158,
+ .cm_div_h12_dpll_per = 0x4a00815c,
+ .cm_div_h13_dpll_per = 0x4a008160,
+ .cm_div_h14_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_emu_override_dpll_per = 0x4a008170,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_unipro = 0x4a0081c0,
+ .cm_idlest_dpll_unipro = 0x4a0081c4,
+ .cm_autoidle_dpll_unipro = 0x4a0081c8,
+ .cm_clksel_dpll_unipro = 0x4a0081cc,
+ .cm_div_m2_dpll_unipro = 0x4a0081d0,
+ .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
+ .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
+ .cm_coreaon_bandgap_clkctrl = 0x4a008648,
+ .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
+
+ /* cm2.core */
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_2_clkstctrl = 0x4a008800,
+ .cm_l3_2_dynamicdep = 0x4a008808,
+ .cm_l3_2_l3_2_clkctrl = 0x4a008820,
+ .cm_l3_gpmc_clkctrl = 0x4a008828,
+ .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_memif_emif_h1_clkctrl = 0x4a008b50,
+ .cm_memif_emif_h2_clkctrl = 0x4a008b58,
+ .cm_memif_dll_h_clkctrl = 0x4a008b60,
+ .cm_c2c_clkstctrl = 0x4a008c00,
+ .cm_c2c_staticdep = 0x4a008c04,
+ .cm_c2c_dynamicdep = 0x4a008c08,
+ .cm_c2c_sad2d_clkctrl = 0x4a008c20,
+ .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
+ .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+ .cm_l4per_clkstctrl = 0x4a009000,
+ .cm_l4per_dynamicdep = 0x4a009008,
+ .cm_l4per_adc_clkctrl = 0x4a009020,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009028,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009030,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009038,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009040,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009048,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009050,
+ .cm_l4per_elm_clkctrl = 0x4a009058,
+ .cm_l4per_gpio2_clkctrl = 0x4a009060,
+ .cm_l4per_gpio3_clkctrl = 0x4a009068,
+ .cm_l4per_gpio4_clkctrl = 0x4a009070,
+ .cm_l4per_gpio5_clkctrl = 0x4a009078,
+ .cm_l4per_gpio6_clkctrl = 0x4a009080,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009088,
+ .cm_l4per_hecc1_clkctrl = 0x4a009090,
+ .cm_l4per_hecc2_clkctrl = 0x4a009098,
+ .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0090c0,
+ .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
+ .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
+ .cm_l4per_mgate_clkctrl = 0x4a0090e8,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009100,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009108,
+ .cm_l4per_gpio7_clkctrl = 0x4a009110,
+ .cm_l4per_gpio8_clkctrl = 0x4a009118,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
+ .cm_l4per_msprohg_clkctrl = 0x4a009130,
+ .cm_l4per_slimbus2_clkctrl = 0x4a009138,
+ .cm_l4per_uart1_clkctrl = 0x4a009140,
+ .cm_l4per_uart2_clkctrl = 0x4a009148,
+ .cm_l4per_uart3_clkctrl = 0x4a009150,
+ .cm_l4per_uart4_clkctrl = 0x4a009158,
+ .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
+ .cm_l4per_i2c5_clkctrl = 0x4a009168,
+ .cm_l4per_uart5_clkctrl = 0x4a009170,
+ .cm_l4per_uart6_clkctrl = 0x4a009178,
+ .cm_l4sec_clkstctrl = 0x4a009180,
+ .cm_l4sec_staticdep = 0x4a009184,
+ .cm_l4sec_dynamicdep = 0x4a009188,
+ .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
+ .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
+ .cm_l4sec_rng_clkctrl = 0x4a0091c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
+
+ /* cm2.ivahd */
+ .cm_ivahd_clkstctrl = 0x4a009200,
+ .cm_ivahd_ivahd_clkctrl = 0x4a009220,
+ .cm_ivahd_sl2_clkctrl = 0x4a009228,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009300,
+ .cm_cam_iss_clkctrl = 0x4a009320,
+ .cm_cam_fdif_clkctrl = 0x4a009328,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009400,
+ .cm_dss_dss_clkctrl = 0x4a009420,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009500,
+ .cm_sgx_sgx_clkctrl = 0x4a009520,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009600,
+
+ /* cm2.l3init */
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
+ .cm_l3init_hsi_clkctrl = 0x4a009638,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
+ .cm_l3init_p1500_clkctrl = 0x4a009678,
+ .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
+ .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4ae0610c,
+ .cm_sys_clksel = 0x4ae06110,
+ .cm_wkup_clkstctrl = 0x4ae07900,
+ .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
+ .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
+ .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
+ .cm_wkup_gpio1_clkctrl = 0x4ae07938,
+ .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
+ .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
+ .cm_wkup_synctimer_clkctrl = 0x4ae07950,
+ .cm_wkup_usim_clkctrl = 0x4ae07958,
+ .cm_wkup_sarram_clkctrl = 0x4ae07960,
+ .cm_wkup_keyboard_clkctrl = 0x4ae07978,
+ .cm_wkup_rtc_clkctrl = 0x4ae07980,
+ .cm_wkup_bandgap_clkctrl = 0x4ae07988,
+ .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
+ .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
+ .prm_rstctrl = 0x4ae07c00,
+ .prm_rstst = 0x4ae07c04,
+ .prm_vc_val_bypass = 0x4ae07ca0,
+ .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
+ .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
+
+ .prm_sldo_core_setup = 0x4ae07cc4,
+ .prm_sldo_core_ctrl = 0x4ae07cc8,
+ .prm_sldo_mpu_setup = 0x4ae07ccc,
+ .prm_sldo_mpu_ctrl = 0x4ae07cd0,
+ .prm_sldo_mm_setup = 0x4ae07cd4,
+ .prm_sldo_mm_ctrl = 0x4ae07cd8,
+};
+
+struct prcm_regs const dra7xx_prcm = {
+ /* cm1.ckgen */
+ .cm_clksel_core = 0x4a005100,
+ .cm_clksel_abe = 0x4a005108,
+ .cm_dll_ctrl = 0x4a005110,
+ .cm_clkmode_dpll_core = 0x4a005120,
+ .cm_idlest_dpll_core = 0x4a005124,
+ .cm_autoidle_dpll_core = 0x4a005128,
+ .cm_clksel_dpll_core = 0x4a00512c,
+ .cm_div_m2_dpll_core = 0x4a005130,
+ .cm_div_m3_dpll_core = 0x4a005134,
+ .cm_div_h11_dpll_core = 0x4a005138,
+ .cm_div_h12_dpll_core = 0x4a00513c,
+ .cm_div_h13_dpll_core = 0x4a005140,
+ .cm_div_h14_dpll_core = 0x4a005144,
+ .cm_ssc_deltamstep_dpll_core = 0x4a005148,
+ .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c,
+ .cm_div_h21_dpll_core = 0x4a005150,
+ .cm_div_h22_dpllcore = 0x4a005154,
+ .cm_div_h23_dpll_core = 0x4a005158,
+ .cm_div_h24_dpll_core = 0x4a00515c,
+ .cm_clkmode_dpll_mpu = 0x4a005160,
+ .cm_idlest_dpll_mpu = 0x4a005164,
+ .cm_autoidle_dpll_mpu = 0x4a005168,
+ .cm_clksel_dpll_mpu = 0x4a00516c,
+ .cm_div_m2_dpll_mpu = 0x4a005170,
+ .cm_ssc_deltamstep_dpll_mpu = 0x4a005188,
+ .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c,
+ .cm_bypclk_dpll_mpu = 0x4a00519c,
+ .cm_clkmode_dpll_iva = 0x4a0051a0,
+ .cm_idlest_dpll_iva = 0x4a0051a4,
+ .cm_autoidle_dpll_iva = 0x4a0051a8,
+ .cm_clksel_dpll_iva = 0x4a0051ac,
+ .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8,
+ .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc,
+ .cm_bypclk_dpll_iva = 0x4a0051dc,
+ .cm_clkmode_dpll_abe = 0x4a0051e0,
+ .cm_idlest_dpll_abe = 0x4a0051e4,
+ .cm_autoidle_dpll_abe = 0x4a0051e8,
+ .cm_clksel_dpll_abe = 0x4a0051ec,
+ .cm_div_m2_dpll_abe = 0x4a0051f0,
+ .cm_div_m3_dpll_abe = 0x4a0051f4,
+ .cm_ssc_deltamstep_dpll_abe = 0x4a005208,
+ .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c,
+ .cm_clkmode_dpll_ddrphy = 0x4a005210,
+ .cm_idlest_dpll_ddrphy = 0x4a005214,
+ .cm_autoidle_dpll_ddrphy = 0x4a005218,
+ .cm_clksel_dpll_ddrphy = 0x4a00521c,
+ .cm_div_m2_dpll_ddrphy = 0x4a005220,
+ .cm_div_h11_dpll_ddrphy = 0x4a005228,
+ .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c,
+ .cm_clkmode_dpll_dsp = 0x4a005234,
+ .cm_shadow_freq_config1 = 0x4a005260,
+
+ /* cm1.mpu */
+ .cm_mpu_mpu_clkctrl = 0x4a005320,
+
+ /* cm1.dsp */
+ .cm_dsp_clkstctrl = 0x4a005400,
+ .cm_dsp_dsp_clkctrl = 0x4a005420,
+
+ /* cm2.ckgen */
+ .cm_clksel_usb_60mhz = 0x4a008104,
+ .cm_clkmode_dpll_per = 0x4a008140,
+ .cm_idlest_dpll_per = 0x4a008144,
+ .cm_autoidle_dpll_per = 0x4a008148,
+ .cm_clksel_dpll_per = 0x4a00814c,
+ .cm_div_m2_dpll_per = 0x4a008150,
+ .cm_div_m3_dpll_per = 0x4a008154,
+ .cm_div_h11_dpll_per = 0x4a008158,
+ .cm_div_h12_dpll_per = 0x4a00815c,
+ .cm_div_h13_dpll_per = 0x4a008160,
+ .cm_div_h14_dpll_per = 0x4a008164,
+ .cm_ssc_deltamstep_dpll_per = 0x4a008168,
+ .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
+ .cm_clkmode_dpll_usb = 0x4a008180,
+ .cm_idlest_dpll_usb = 0x4a008184,
+ .cm_autoidle_dpll_usb = 0x4a008188,
+ .cm_clksel_dpll_usb = 0x4a00818c,
+ .cm_div_m2_dpll_usb = 0x4a008190,
+ .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
+ .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
+ .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
+ .cm_clkmode_dpll_pcie_ref = 0x4a008200,
+ .cm_clkmode_apll_pcie = 0x4a00821c,
+ .cm_idlest_apll_pcie = 0x4a008220,
+ .cm_div_m2_apll_pcie = 0x4a008224,
+ .cm_clkvcoldo_apll_pcie = 0x4a008228,
+
+ /* cm2.core */
+ .cm_l3_1_clkstctrl = 0x4a008700,
+ .cm_l3_1_dynamicdep = 0x4a008708,
+ .cm_l3_1_l3_1_clkctrl = 0x4a008720,
+ .cm_l3_gpmc_clkctrl = 0x4a008728,
+ .cm_mpu_m3_clkstctrl = 0x4a008900,
+ .cm_mpu_m3_staticdep = 0x4a008904,
+ .cm_mpu_m3_dynamicdep = 0x4a008908,
+ .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
+ .cm_sdma_clkstctrl = 0x4a008a00,
+ .cm_sdma_staticdep = 0x4a008a04,
+ .cm_sdma_dynamicdep = 0x4a008a08,
+ .cm_sdma_sdma_clkctrl = 0x4a008a20,
+ .cm_memif_clkstctrl = 0x4a008b00,
+ .cm_memif_dmm_clkctrl = 0x4a008b20,
+ .cm_memif_emif_fw_clkctrl = 0x4a008b28,
+ .cm_memif_emif_1_clkctrl = 0x4a008b30,
+ .cm_memif_emif_2_clkctrl = 0x4a008b38,
+ .cm_memif_dll_clkctrl = 0x4a008b40,
+ .cm_l4cfg_clkstctrl = 0x4a008d00,
+ .cm_l4cfg_dynamicdep = 0x4a008d08,
+ .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
+ .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
+ .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
+ .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
+ .cm_l3instr_clkstctrl = 0x4a008e00,
+ .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
+ .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
+ .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
+
+ /* cm2.ivahd */
+ .cm_ivahd_clkstctrl = 0x4a008f00,
+ .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
+ .cm_ivahd_sl2_clkctrl = 0x4a008f28,
+
+ /* cm2.cam */
+ .cm_cam_clkstctrl = 0x4a009000,
+ .cm_cam_vip1_clkctrl = 0x4a009020,
+ .cm_cam_vip2_clkctrl = 0x4a009028,
+ .cm_cam_vip3_clkctrl = 0x4a009030,
+ .cm_cam_lvdsrx_clkctrl = 0x4a009038,
+ .cm_cam_csi1_clkctrl = 0x4a009040,
+ .cm_cam_csi2_clkctrl = 0x4a009048,
+
+ /* cm2.dss */
+ .cm_dss_clkstctrl = 0x4a009100,
+ .cm_dss_dss_clkctrl = 0x4a009120,
+
+ /* cm2.sgx */
+ .cm_sgx_clkstctrl = 0x4a009200,
+ .cm_sgx_sgx_clkctrl = 0x4a009220,
+
+ /* cm2.l3init */
+ .cm_l3init_clkstctrl = 0x4a009300,
+
+ /* cm2.l3init */
+ .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
+ .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
+ .cm_l3init_hsusbhost_clkctrl = 0x4a009340,
+ .cm_l3init_hsusbotg_clkctrl = 0x4a009348,
+ .cm_l3init_hsusbtll_clkctrl = 0x4a009350,
+ .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+
+ /* cm2.l4per */
+ .cm_l4per_clkstctrl = 0x4a009700,
+ .cm_l4per_dynamicdep = 0x4a009708,
+ .cm_l4per_gptimer10_clkctrl = 0x4a009728,
+ .cm_l4per_gptimer11_clkctrl = 0x4a009730,
+ .cm_l4per_gptimer2_clkctrl = 0x4a009738,
+ .cm_l4per_gptimer3_clkctrl = 0x4a009740,
+ .cm_l4per_gptimer4_clkctrl = 0x4a009748,
+ .cm_l4per_gptimer9_clkctrl = 0x4a009750,
+ .cm_l4per_elm_clkctrl = 0x4a009758,
+ .cm_l4per_gpio2_clkctrl = 0x4a009760,
+ .cm_l4per_gpio3_clkctrl = 0x4a009768,
+ .cm_l4per_gpio4_clkctrl = 0x4a009770,
+ .cm_l4per_gpio5_clkctrl = 0x4a009778,
+ .cm_l4per_gpio6_clkctrl = 0x4a009780,
+ .cm_l4per_hdq1w_clkctrl = 0x4a009788,
+ .cm_l4per_i2c1_clkctrl = 0x4a0097a0,
+ .cm_l4per_i2c2_clkctrl = 0x4a0097a8,
+ .cm_l4per_i2c3_clkctrl = 0x4a0097b0,
+ .cm_l4per_i2c4_clkctrl = 0x4a0097b8,
+ .cm_l4per_l4per_clkctrl = 0x4a0097c0,
+ .cm_l4per_mcspi1_clkctrl = 0x4a0097f0,
+ .cm_l4per_mcspi2_clkctrl = 0x4a0097f8,
+ .cm_l4per_mcspi3_clkctrl = 0x4a009800,
+ .cm_l4per_mcspi4_clkctrl = 0x4a009808,
+ .cm_l4per_gpio7_clkctrl = 0x4a009810,
+ .cm_l4per_gpio8_clkctrl = 0x4a009818,
+ .cm_l4per_mmcsd3_clkctrl = 0x4a009820,
+ .cm_l4per_mmcsd4_clkctrl = 0x4a009828,
+ .cm_l4per_uart1_clkctrl = 0x4a009840,
+ .cm_l4per_uart2_clkctrl = 0x4a009848,
+ .cm_l4per_uart3_clkctrl = 0x4a009850,
+ .cm_l4per_uart4_clkctrl = 0x4a009858,
+ .cm_l4per_uart5_clkctrl = 0x4a009870,
+ .cm_l4sec_clkstctrl = 0x4a009880,
+ .cm_l4sec_staticdep = 0x4a009884,
+ .cm_l4sec_dynamicdep = 0x4a009888,
+ .cm_l4sec_aes1_clkctrl = 0x4a0098a0,
+ .cm_l4sec_aes2_clkctrl = 0x4a0098a8,
+ .cm_l4sec_des3des_clkctrl = 0x4a0098b0,
+ .cm_l4sec_rng_clkctrl = 0x4a0098c0,
+ .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8,
+ .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8,
+
+ /* l4 wkup regs */
+ .cm_abe_pll_ref_clksel = 0x4ae0610c,
+ .cm_sys_clksel = 0x4ae06110,
+ .cm_wkup_clkstctrl = 0x4ae07800,
+ .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
+ .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
+ .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
+ .cm_wkup_gpio1_clkctrl = 0x4ae07838,
+ .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
+ .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
+ .cm_wkup_sarram_clkctrl = 0x4ae07860,
+ .cm_wkup_keyboard_clkctrl = 0x4ae07878,
+ .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
+ .prm_rstctrl = 0x4ae07d00,
+ .prm_rstst = 0x4ae07d04,
+ .prm_vc_val_bypass = 0x4ae07da0,
+ .prm_vc_cfg_i2c_mode = 0x4ae07db4,
+ .prm_vc_cfg_i2c_clk = 0x4ae07db8,
+};
.emif_ddr_ext_phy_ctrl_5 = 0x04010040
};
+const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
+ .sdram_config_init = 0x80800EBA,
+ .sdram_config = 0x808022BA,
+ .ref_ctrl = 0x0000081A,
+ .sdram_tim1 = 0x772F6873,
+ .sdram_tim2 = 0x304a129a,
+ .sdram_tim3 = 0x02f7e45f,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x100b3215,
+ .temp_alert_config = 0x08000a05,
+ .emif_ddr_phy_ctlr_1_init = 0x0E30400d,
+ .emif_ddr_phy_ctlr_1 = 0x0E30400d,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04020080,
+ .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
+ .emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
+ .emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
+ .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
+};
+
const struct emif_regs emif_regs_266_mhz_2cs = {
.sdram_config_init = 0x80800EBA,
.sdram_config = 0x808022BA,
.emif_rd_wr_exec_thresh = 0x00000305
};
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
+ .sdram_config_init = 0x61851B32,
+ .sdram_config = 0x61851B32,
+ .ref_ctrl = 0x00001035,
+ .sdram_tim1 = 0xCCCF36B3,
+ .sdram_tim2 = 0x308F7FDA,
+ .sdram_tim3 = 0x027F88A8,
+ .read_idle_ctrl = 0x00050000,
+ .zq_config = 0x1007190B,
+ .temp_alert_config = 0x00000000,
+ .emif_ddr_phy_ctlr_1_init = 0x0030400A,
+ .emif_ddr_phy_ctlr_1 = 0x0034400A,
+ .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
+ .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
+ .emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
+ .emif_rd_wr_lvl_rmp_win = 0x00000000,
+ .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
+ .emif_rd_wr_lvl_ctl = 0x00000000,
+ .emif_rd_wr_exec_thresh = 0x40000305
+};
+
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
- .dmm_lisa_map_3 = 0xFF020100
+ .dmm_lisa_map_3 = 0xFF020100,
+ .is_ma_present = 0x1
+};
+
+const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
+ .dmm_lisa_map_0 = 0x0,
+ .dmm_lisa_map_1 = 0x0,
+ .dmm_lisa_map_2 = 0x0,
+ .dmm_lisa_map_3 = 0x80500100,
+ .is_ma_present = 0x1
+};
+
+static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
+{
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ *regs = &emif_regs_532_mhz_2cs;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = &emif_regs_ddr3_532_mhz_1cs;
+ break;
+ case OMAP5430_ES2_0:
+ *regs = &emif_regs_532_mhz_2cs_es2;
+ break;
+ case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
+ default:
+ *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
+ }
+}
+
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+ __attribute__((weak, alias("emif_get_reg_dump_sdp")));
+
+static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
+ **dmm_lisa_regs)
+{
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ case OMAP5432_ES1_0:
+ case OMAP5432_ES2_0:
+ *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
+ break;
+ case DRA752_ES1_0:
+ default:
+ *dmm_lisa_regs = &lisa_map_512M_x_1;
+ }
+
+}
+
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
+ __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
+#else
+
+static const struct lpddr2_device_details dev_4G_S4_details = {
+ .type = LPDDR2_TYPE_S4,
+ .density = LPDDR2_DENSITY_4Gb,
+ .io_width = LPDDR2_IO_WIDTH_32,
+ .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
};
+static void emif_get_device_details_sdp(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+{
+ /* EMIF1 & EMIF2 have identical configuration */
+ *cs0_device_details = dev_4G_S4_details;
+ *cs1_device_details = dev_4G_S4_details;
+}
+
+void emif_get_device_details(u32 emif_nr,
+ struct lpddr2_device_details *cs0_device_details,
+ struct lpddr2_device_details *cs1_device_details)
+ __attribute__((weak, alias("emif_get_device_details_sdp")));
+
+#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x00000077
};
-const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x01004010,
0x00001004,
0x04010040,
0x00000057
};
-static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
-{
- if (omap_revision() == OMAP5432_ES1_0)
- *regs = &emif_regs_ddr3_532_mhz_1cs;
- else
- *regs = &emif_regs_532_mhz_2cs;
-}
-void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
- __attribute__((weak, alias("emif_get_reg_dump_sdp")));
-
-static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
- **dmm_lisa_regs)
-{
- *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
-}
-
-void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
- __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
-
-#else
+const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+ 0x50D4350D,
+ 0x00000D43,
+ 0x04010040,
+ 0x01004010,
+ 0x00001004,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x80080080,
+ 0x00800800,
+ 0x08102040,
+ 0x00000002,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000057
+};
-static const struct lpddr2_device_details dev_4G_S4_details = {
- .type = LPDDR2_TYPE_S4,
- .density = LPDDR2_DENSITY_4Gb,
- .io_width = LPDDR2_IO_WIDTH_32,
- .manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
+const struct lpddr2_mr_regs mr_regs = {
+ .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
+ .mr2 = 0x6,
+ .mr3 = 0x1,
+ .mr10 = MR10_ZQ_ZQINIT,
+ .mr16 = MR16_REF_FULL_ARRAY
};
-static void emif_get_device_details_sdp(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
+static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
{
- /* EMIF1 & EMIF2 have identical configuration */
- *cs0_device_details = dev_4G_S4_details;
- *cs1_device_details = dev_4G_S4_details;
-}
+ switch (omap_revision()) {
+ case OMAP5430_ES1_0:
+ case OMAP5430_ES2_0:
+ *regs = ext_phy_ctrl_const_base;
+ break;
+ case OMAP5432_ES1_0:
+ *regs = ddr3_ext_phy_ctrl_const_base_es1;
+ break;
+ case OMAP5432_ES2_0:
+ case DRA752_ES1_0:
+ default:
+ *regs = ddr3_ext_phy_ctrl_const_base_es2;
-void emif_get_device_details(u32 emif_nr,
- struct lpddr2_device_details *cs0_device_details,
- struct lpddr2_device_details *cs1_device_details)
- __attribute__((weak, alias("emif_get_device_details_sdp")));
+ }
+}
-#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
+{
+ *regs = &mr_regs;
+}
void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
u32 *ext_phy_ctrl_base = 0;
u32 *emif_ext_phy_ctrl_base = 0;
+ const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
* external phy 6-24 registers do not change with
* ddr frequency
*/
+ emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
+ writel(ext_phy_ctrl_const_regs[i],
+ emif_ext_phy_ctrl_base++);
/* Update shadow registers */
- writel(ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
+ writel(ext_phy_ctrl_const_regs[i],
+ emif_ext_phy_ctrl_base++);
}
}
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
#endif
mcr p15, 0, r0, c1, c0, 0
+
+#ifdef CONFIG_ARM_ERRATA_742230
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 4 @ set bit #4
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_743622
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 6 @ set bit #6
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_751472
+ mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
+ orr r0, r0, #1 << 11 @ set bit #11
+ mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
+#endif
+
mov pc, lr @ back to my caller
ENDPROC(cpu_init_cp15)
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
_end = .;
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ ___bssend___ = .;
+ }
+ .bss_end ___bssend___ (OVERLAY) : {
+ KEEP(*(.__bss_end__));
}
/DISCARD/ : { *(.dynstr*) }
--- /dev/null
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : {
+ *(.data*)
+ }
+
+ . = ALIGN(4);
+
+ . = .;
+
+ __image_copy_end = .;
+
+ .rel.dyn : {
+ __rel_dyn_start = .;
+ *(.rel*)
+ __rel_dyn_end = .;
+ }
+
+ .dynsym : {
+ __dynsym_start = .;
+ *(.dynsym)
+ }
+
+ _end = .;
+
+ /*
+ * Deprecated: this MMU section is used by pxa at present but
+ * should not be used by new boards/CPUs.
+ */
+ . = ALIGN(4096);
+ .mmutable : {
+ *(.mmutable)
+ }
+
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ }
+
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
+
+#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
+ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
+#endif
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
*(.mmutable)
}
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ ___bssend___ = .;
+ }
+ .bss_end ___bssend___ (OVERLAY) : {
+ KEEP(*(.__bss_end__));
}
/DISCARD/ : { *(.dynstr*) }
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC1_BASE 0x48060100
#define OMAP_HSMMC2_BASE 0x481D8100
-typedef struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-} hsmmc_t;
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
#endif /* MMC_HOST_DEF_H */
void sdelay(unsigned long);
void gpmc_init(void);
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size);
void omap_nand_switch_ecc(int);
#endif
/*
* Cpu Name
*/
-#define CONFIG_SYS_AT91_G15_CPU_NAME "AT91SAM9G15"
-#define CONFIG_SYS_AT91_G25_CPU_NAME "AT91SAM9G25"
-#define CONFIG_SYS_AT91_G35_CPU_NAME "AT91SAM9G35"
-#define CONFIG_SYS_AT91_X25_CPU_NAME "AT91SAM9X25"
-#define CONFIG_SYS_AT91_X35_CPU_NAME "AT91SAM9X35"
-#define CONFIG_SYS_AT91_UNKNOWN_CPU "Unknown CPU type"
#define ATMEL_CPU_NAME get_cpu_name()
/*
#define gpio_status() gpio_info()
#define GPIO_NAME_SIZE 20
-#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#if defined(CONFIG_SOC_DM644X)
+/* GPIO0 to GPIO53, omit the V3.3 volts one */
+#define MAX_NUM_GPIOS 70
+#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
#define MAX_NUM_GPIOS 128
#else
#define MAX_NUM_GPIOS 144
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
#define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16
+/* LCD display type */
+#define PASSIVE_DISPLAY 0
+#define ACTIVE_DISPLAY 1
+
+/* TFTDATALINES */
+#define LCD_INTERFACE_12_BIT 0
+#define LCD_INTERFACE_16_BIT 1
+#define LCD_INTERFACE_18_BIT 2
+#define LCD_INTERFACE_24_BIT 3
+
+/* Polarity */
+#define DSS_IVS (1 << 12)
+#define DSS_IHS (1 << 13)
+#define DSS_IPC (1 << 14)
+#define DSS_IEO (1 << 15)
+
+/* GFX format */
+#define GFXFORMAT_BITMAP1 (0x0 << 1)
+#define GFXFORMAT_BITMAP2 (0x1 << 1)
+#define GFXFORMAT_BITMAP4 (0x2 << 1)
+#define GFXFORMAT_BITMAP8 (0x3 << 1)
+#define GFXFORMAT_RGB12 (0x4 << 1)
+#define GFXFORMAT_ARGB16 (0x5 << 1)
+#define GFXFORMAT_RGB16 (0x6 << 1)
+#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1)
+#define GFXFORMAT_RGB24_PACKED (0x9 << 1)
+#define GFXFORMAT_ARGB32 (0xC << 1)
+#define GFXFORMAT_RGBA32 (0xD << 1)
+#define GFXFORMAT_RGBx32 (0xE << 1)
+
/* Panel Configuration */
struct panel_config {
u32 timing_h;
u32 data_lines;
u32 load_mode;
u32 panel_color;
+ u32 gfx_format;
void *frame_buffer;
};
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/* T2 Register definitions */
#define T2_BASE 0x48002000
#define OMAP_HSMMC2_BASE 0x480B4000
#define OMAP_HSMMC3_BASE 0x480AD000
-struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-};
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
#endif /* MMC_HOST_DEF_H */
#define BOOT_DEVICE_NONE 0
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_NAND 2
-#define BOOT_DEVICE_ONE_NAND 3
+#define BOOT_DEVICE_ONENAND 3
#define BOOT_DEVICE_MMC2 5 /*emmc*/
#define BOOT_DEVICE_MMC1 6
#define BOOT_DEVICE_XIPWAIT 7
#ifndef _CLOCKS_OMAP4_H_
#define _CLOCKS_OMAP4_H_
#include <common.h>
+#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
#define CM_CLKMODE_DPLL_MPU 0x4A004160
#define CM_CLKSEL_CORE 0x4A004100
-struct omap4_prcm_regs {
- /* cm1.ckgen */
- u32 cm_clksel_core;
- u32 pad001[1];
- u32 cm_clksel_abe;
- u32 pad002[1];
- u32 cm_dll_ctrl;
- u32 pad003[3];
- u32 cm_clkmode_dpll_core;
- u32 cm_idlest_dpll_core;
- u32 cm_autoidle_dpll_core;
- u32 cm_clksel_dpll_core;
- u32 cm_div_m2_dpll_core;
- u32 cm_div_m3_dpll_core;
- u32 cm_div_m4_dpll_core;
- u32 cm_div_m5_dpll_core;
- u32 cm_div_m6_dpll_core;
- u32 cm_div_m7_dpll_core;
- u32 cm_ssc_deltamstep_dpll_core;
- u32 cm_ssc_modfreqdiv_dpll_core;
- u32 cm_emu_override_dpll_core;
- u32 pad004[3];
- u32 cm_clkmode_dpll_mpu;
- u32 cm_idlest_dpll_mpu;
- u32 cm_autoidle_dpll_mpu;
- u32 cm_clksel_dpll_mpu;
- u32 cm_div_m2_dpll_mpu;
- u32 pad005[5];
- u32 cm_ssc_deltamstep_dpll_mpu;
- u32 cm_ssc_modfreqdiv_dpll_mpu;
- u32 pad006[3];
- u32 cm_bypclk_dpll_mpu;
- u32 cm_clkmode_dpll_iva;
- u32 cm_idlest_dpll_iva;
- u32 cm_autoidle_dpll_iva;
- u32 cm_clksel_dpll_iva;
- u32 pad007[2];
- u32 cm_div_m4_dpll_iva;
- u32 cm_div_m5_dpll_iva;
- u32 pad008[2];
- u32 cm_ssc_deltamstep_dpll_iva;
- u32 cm_ssc_modfreqdiv_dpll_iva;
- u32 pad009[3];
- u32 cm_bypclk_dpll_iva;
- u32 cm_clkmode_dpll_abe;
- u32 cm_idlest_dpll_abe;
- u32 cm_autoidle_dpll_abe;
- u32 cm_clksel_dpll_abe;
- u32 cm_div_m2_dpll_abe;
- u32 cm_div_m3_dpll_abe;
- u32 pad010[4];
- u32 cm_ssc_deltamstep_dpll_abe;
- u32 cm_ssc_modfreqdiv_dpll_abe;
- u32 pad011[4];
- u32 cm_clkmode_dpll_ddrphy;
- u32 cm_idlest_dpll_ddrphy;
- u32 cm_autoidle_dpll_ddrphy;
- u32 cm_clksel_dpll_ddrphy;
- u32 cm_div_m2_dpll_ddrphy;
- u32 pad012[1];
- u32 cm_div_m4_dpll_ddrphy;
- u32 cm_div_m5_dpll_ddrphy;
- u32 cm_div_m6_dpll_ddrphy;
- u32 pad013[1];
- u32 cm_ssc_deltamstep_dpll_ddrphy;
- u32 pad014[5];
- u32 cm_shadow_freq_config1;
- u32 pad0141[47];
- u32 cm_mpu_mpu_clkctrl;
-
- /* cm1.dsp */
- u32 pad015[55];
- u32 cm_dsp_clkstctrl;
- u32 pad016[7];
- u32 cm_dsp_dsp_clkctrl;
-
- /* cm1.abe */
- u32 pad017[55];
- u32 cm1_abe_clkstctrl;
- u32 pad018[7];
- u32 cm1_abe_l4abe_clkctrl;
- u32 pad019[1];
- u32 cm1_abe_aess_clkctrl;
- u32 pad020[1];
- u32 cm1_abe_pdm_clkctrl;
- u32 pad021[1];
- u32 cm1_abe_dmic_clkctrl;
- u32 pad022[1];
- u32 cm1_abe_mcasp_clkctrl;
- u32 pad023[1];
- u32 cm1_abe_mcbsp1_clkctrl;
- u32 pad024[1];
- u32 cm1_abe_mcbsp2_clkctrl;
- u32 pad025[1];
- u32 cm1_abe_mcbsp3_clkctrl;
- u32 pad026[1];
- u32 cm1_abe_slimbus_clkctrl;
- u32 pad027[1];
- u32 cm1_abe_timer5_clkctrl;
- u32 pad028[1];
- u32 cm1_abe_timer6_clkctrl;
- u32 pad029[1];
- u32 cm1_abe_timer7_clkctrl;
- u32 pad030[1];
- u32 cm1_abe_timer8_clkctrl;
- u32 pad031[1];
- u32 cm1_abe_wdt3_clkctrl;
-
- /* cm2.ckgen */
- u32 pad032[3805];
- u32 cm_clksel_mpu_m3_iss_root;
- u32 cm_clksel_usb_60mhz;
- u32 cm_scale_fclk;
- u32 pad033[1];
- u32 cm_core_dvfs_perf1;
- u32 cm_core_dvfs_perf2;
- u32 cm_core_dvfs_perf3;
- u32 cm_core_dvfs_perf4;
- u32 pad034[1];
- u32 cm_core_dvfs_current;
- u32 cm_iva_dvfs_perf_tesla;
- u32 cm_iva_dvfs_perf_ivahd;
- u32 cm_iva_dvfs_perf_abe;
- u32 pad035[1];
- u32 cm_iva_dvfs_current;
- u32 pad036[1];
- u32 cm_clkmode_dpll_per;
- u32 cm_idlest_dpll_per;
- u32 cm_autoidle_dpll_per;
- u32 cm_clksel_dpll_per;
- u32 cm_div_m2_dpll_per;
- u32 cm_div_m3_dpll_per;
- u32 cm_div_m4_dpll_per;
- u32 cm_div_m5_dpll_per;
- u32 cm_div_m6_dpll_per;
- u32 cm_div_m7_dpll_per;
- u32 cm_ssc_deltamstep_dpll_per;
- u32 cm_ssc_modfreqdiv_dpll_per;
- u32 cm_emu_override_dpll_per;
- u32 pad037[3];
- u32 cm_clkmode_dpll_usb;
- u32 cm_idlest_dpll_usb;
- u32 cm_autoidle_dpll_usb;
- u32 cm_clksel_dpll_usb;
- u32 cm_div_m2_dpll_usb;
- u32 pad038[5];
- u32 cm_ssc_deltamstep_dpll_usb;
- u32 cm_ssc_modfreqdiv_dpll_usb;
- u32 pad039[1];
- u32 cm_clkdcoldo_dpll_usb;
- u32 pad040[2];
- u32 cm_clkmode_dpll_unipro;
- u32 cm_idlest_dpll_unipro;
- u32 cm_autoidle_dpll_unipro;
- u32 cm_clksel_dpll_unipro;
- u32 cm_div_m2_dpll_unipro;
- u32 pad041[5];
- u32 cm_ssc_deltamstep_dpll_unipro;
- u32 cm_ssc_modfreqdiv_dpll_unipro;
-
- /* cm2.core */
- u32 pad0411[324];
- u32 cm_l3_1_clkstctrl;
- u32 pad042[1];
- u32 cm_l3_1_dynamicdep;
- u32 pad043[5];
- u32 cm_l3_1_l3_1_clkctrl;
- u32 pad044[55];
- u32 cm_l3_2_clkstctrl;
- u32 pad045[1];
- u32 cm_l3_2_dynamicdep;
- u32 pad046[5];
- u32 cm_l3_2_l3_2_clkctrl;
- u32 pad047[1];
- u32 cm_l3_2_gpmc_clkctrl;
- u32 pad048[1];
- u32 cm_l3_2_ocmc_ram_clkctrl;
- u32 pad049[51];
- u32 cm_mpu_m3_clkstctrl;
- u32 cm_mpu_m3_staticdep;
- u32 cm_mpu_m3_dynamicdep;
- u32 pad050[5];
- u32 cm_mpu_m3_mpu_m3_clkctrl;
- u32 pad051[55];
- u32 cm_sdma_clkstctrl;
- u32 cm_sdma_staticdep;
- u32 cm_sdma_dynamicdep;
- u32 pad052[5];
- u32 cm_sdma_sdma_clkctrl;
- u32 pad053[55];
- u32 cm_memif_clkstctrl;
- u32 pad054[7];
- u32 cm_memif_dmm_clkctrl;
- u32 pad055[1];
- u32 cm_memif_emif_fw_clkctrl;
- u32 pad056[1];
- u32 cm_memif_emif_1_clkctrl;
- u32 pad057[1];
- u32 cm_memif_emif_2_clkctrl;
- u32 pad058[1];
- u32 cm_memif_dll_clkctrl;
- u32 pad059[3];
- u32 cm_memif_emif_h1_clkctrl;
- u32 pad060[1];
- u32 cm_memif_emif_h2_clkctrl;
- u32 pad061[1];
- u32 cm_memif_dll_h_clkctrl;
- u32 pad062[39];
- u32 cm_c2c_clkstctrl;
- u32 cm_c2c_staticdep;
- u32 cm_c2c_dynamicdep;
- u32 pad063[5];
- u32 cm_c2c_sad2d_clkctrl;
- u32 pad064[1];
- u32 cm_c2c_modem_icr_clkctrl;
- u32 pad065[1];
- u32 cm_c2c_sad2d_fw_clkctrl;
- u32 pad066[51];
- u32 cm_l4cfg_clkstctrl;
- u32 pad067[1];
- u32 cm_l4cfg_dynamicdep;
- u32 pad068[5];
- u32 cm_l4cfg_l4_cfg_clkctrl;
- u32 pad069[1];
- u32 cm_l4cfg_hw_sem_clkctrl;
- u32 pad070[1];
- u32 cm_l4cfg_mailbox_clkctrl;
- u32 pad071[1];
- u32 cm_l4cfg_sar_rom_clkctrl;
- u32 pad072[49];
- u32 cm_l3instr_clkstctrl;
- u32 pad073[7];
- u32 cm_l3instr_l3_3_clkctrl;
- u32 pad074[1];
- u32 cm_l3instr_l3_instr_clkctrl;
- u32 pad075[5];
- u32 cm_l3instr_intrconn_wp1_clkctrl;
-
-
- /* cm2.ivahd */
- u32 pad076[47];
- u32 cm_ivahd_clkstctrl;
- u32 pad077[7];
- u32 cm_ivahd_ivahd_clkctrl;
- u32 pad078[1];
- u32 cm_ivahd_sl2_clkctrl;
-
- /* cm2.cam */
- u32 pad079[53];
- u32 cm_cam_clkstctrl;
- u32 pad080[7];
- u32 cm_cam_iss_clkctrl;
- u32 pad081[1];
- u32 cm_cam_fdif_clkctrl;
-
- /* cm2.dss */
- u32 pad082[53];
- u32 cm_dss_clkstctrl;
- u32 pad083[7];
- u32 cm_dss_dss_clkctrl;
-
- /* cm2.sgx */
- u32 pad084[55];
- u32 cm_sgx_clkstctrl;
- u32 pad085[7];
- u32 cm_sgx_sgx_clkctrl;
-
- /* cm2.l3init */
- u32 pad086[55];
- u32 cm_l3init_clkstctrl;
-
- /* cm2.l3init */
- u32 pad087[9];
- u32 cm_l3init_hsmmc1_clkctrl;
- u32 pad088[1];
- u32 cm_l3init_hsmmc2_clkctrl;
- u32 pad089[1];
- u32 cm_l3init_hsi_clkctrl;
- u32 pad090[7];
- u32 cm_l3init_hsusbhost_clkctrl;
- u32 pad091[1];
- u32 cm_l3init_hsusbotg_clkctrl;
- u32 pad092[1];
- u32 cm_l3init_hsusbtll_clkctrl;
- u32 pad093[3];
- u32 cm_l3init_p1500_clkctrl;
- u32 pad094[21];
- u32 cm_l3init_fsusb_clkctrl;
- u32 pad095[3];
- u32 cm_l3init_usbphy_clkctrl;
-
- /* cm2.l4per */
- u32 pad096[7];
- u32 cm_l4per_clkstctrl;
- u32 pad097[1];
- u32 cm_l4per_dynamicdep;
- u32 pad098[5];
- u32 cm_l4per_adc_clkctrl;
- u32 pad100[1];
- u32 cm_l4per_gptimer10_clkctrl;
- u32 pad101[1];
- u32 cm_l4per_gptimer11_clkctrl;
- u32 pad102[1];
- u32 cm_l4per_gptimer2_clkctrl;
- u32 pad103[1];
- u32 cm_l4per_gptimer3_clkctrl;
- u32 pad104[1];
- u32 cm_l4per_gptimer4_clkctrl;
- u32 pad105[1];
- u32 cm_l4per_gptimer9_clkctrl;
- u32 pad106[1];
- u32 cm_l4per_elm_clkctrl;
- u32 pad107[1];
- u32 cm_l4per_gpio2_clkctrl;
- u32 pad108[1];
- u32 cm_l4per_gpio3_clkctrl;
- u32 pad109[1];
- u32 cm_l4per_gpio4_clkctrl;
- u32 pad110[1];
- u32 cm_l4per_gpio5_clkctrl;
- u32 pad111[1];
- u32 cm_l4per_gpio6_clkctrl;
- u32 pad112[1];
- u32 cm_l4per_hdq1w_clkctrl;
- u32 pad113[1];
- u32 cm_l4per_hecc1_clkctrl;
- u32 pad114[1];
- u32 cm_l4per_hecc2_clkctrl;
- u32 pad115[1];
- u32 cm_l4per_i2c1_clkctrl;
- u32 pad116[1];
- u32 cm_l4per_i2c2_clkctrl;
- u32 pad117[1];
- u32 cm_l4per_i2c3_clkctrl;
- u32 pad118[1];
- u32 cm_l4per_i2c4_clkctrl;
- u32 pad119[1];
- u32 cm_l4per_l4per_clkctrl;
- u32 pad1191[3];
- u32 cm_l4per_mcasp2_clkctrl;
- u32 pad120[1];
- u32 cm_l4per_mcasp3_clkctrl;
- u32 pad121[1];
- u32 cm_l4per_mcbsp4_clkctrl;
- u32 pad122[1];
- u32 cm_l4per_mgate_clkctrl;
- u32 pad123[1];
- u32 cm_l4per_mcspi1_clkctrl;
- u32 pad124[1];
- u32 cm_l4per_mcspi2_clkctrl;
- u32 pad125[1];
- u32 cm_l4per_mcspi3_clkctrl;
- u32 pad126[1];
- u32 cm_l4per_mcspi4_clkctrl;
- u32 pad127[5];
- u32 cm_l4per_mmcsd3_clkctrl;
- u32 pad128[1];
- u32 cm_l4per_mmcsd4_clkctrl;
- u32 pad129[1];
- u32 cm_l4per_msprohg_clkctrl;
- u32 pad130[1];
- u32 cm_l4per_slimbus2_clkctrl;
- u32 pad131[1];
- u32 cm_l4per_uart1_clkctrl;
- u32 pad132[1];
- u32 cm_l4per_uart2_clkctrl;
- u32 pad133[1];
- u32 cm_l4per_uart3_clkctrl;
- u32 pad134[1];
- u32 cm_l4per_uart4_clkctrl;
- u32 pad135[1];
- u32 cm_l4per_mmcsd5_clkctrl;
- u32 pad136[1];
- u32 cm_l4per_i2c5_clkctrl;
- u32 pad137[5];
- u32 cm_l4sec_clkstctrl;
- u32 cm_l4sec_staticdep;
- u32 cm_l4sec_dynamicdep;
- u32 pad138[5];
- u32 cm_l4sec_aes1_clkctrl;
- u32 pad139[1];
- u32 cm_l4sec_aes2_clkctrl;
- u32 pad140[1];
- u32 cm_l4sec_des3des_clkctrl;
- u32 pad141[1];
- u32 cm_l4sec_pkaeip29_clkctrl;
- u32 pad142[1];
- u32 cm_l4sec_rng_clkctrl;
- u32 pad143[1];
- u32 cm_l4sec_sha2md51_clkctrl;
- u32 pad144[3];
- u32 cm_l4sec_cryptodma_clkctrl;
- u32 pad145[776841];
-
- /* l4 wkup regs */
- u32 pad201[6211];
- u32 cm_abe_pll_ref_clksel;
- u32 cm_sys_clksel;
- u32 pad202[1467];
- u32 cm_wkup_clkstctrl;
- u32 pad203[7];
- u32 cm_wkup_l4wkup_clkctrl;
- u32 pad204;
- u32 cm_wkup_wdtimer1_clkctrl;
- u32 pad205;
- u32 cm_wkup_wdtimer2_clkctrl;
- u32 pad206;
- u32 cm_wkup_gpio1_clkctrl;
- u32 pad207;
- u32 cm_wkup_gptimer1_clkctrl;
- u32 pad208;
- u32 cm_wkup_gptimer12_clkctrl;
- u32 pad209;
- u32 cm_wkup_synctimer_clkctrl;
- u32 pad210;
- u32 cm_wkup_usim_clkctrl;
- u32 pad211;
- u32 cm_wkup_sarram_clkctrl;
- u32 pad212[5];
- u32 cm_wkup_keyboard_clkctrl;
- u32 pad213;
- u32 cm_wkup_rtc_clkctrl;
- u32 pad214;
- u32 cm_wkup_bandgap_clkctrl;
- u32 pad215[197];
- u32 prm_vc_val_bypass;
- u32 prm_vc_cfg_channel;
- u32 prm_vc_cfg_i2c_mode;
- u32 prm_vc_cfg_i2c_clk;
-
-};
-
-struct omap4_scrm_regs {
- u32 revision; /* 0x0000 */
- u32 pad00[63];
- u32 clksetuptime; /* 0x0100 */
- u32 pmicsetuptime; /* 0x0104 */
- u32 pad01[2];
- u32 altclksrc; /* 0x0110 */
- u32 pad02[2];
- u32 c2cclkm; /* 0x011c */
- u32 pad03[56];
- u32 extclkreq; /* 0x0200 */
- u32 accclkreq; /* 0x0204 */
- u32 pwrreq; /* 0x0208 */
- u32 pad04[1];
- u32 auxclkreq0; /* 0x0210 */
- u32 auxclkreq1; /* 0x0214 */
- u32 auxclkreq2; /* 0x0218 */
- u32 auxclkreq3; /* 0x021c */
- u32 auxclkreq4; /* 0x0220 */
- u32 auxclkreq5; /* 0x0224 */
- u32 pad05[3];
- u32 c2cclkreq; /* 0x0234 */
- u32 pad06[54];
- u32 auxclk0; /* 0x0310 */
- u32 auxclk1; /* 0x0314 */
- u32 auxclk2; /* 0x0318 */
- u32 auxclk3; /* 0x031c */
- u32 auxclk4; /* 0x0320 */
- u32 auxclk5; /* 0x0324 */
- u32 pad07[54];
- u32 rsttime_reg; /* 0x0400 */
- u32 pad08[6];
- u32 c2crstctrl; /* 0x041c */
- u32 extpwronrstctrl; /* 0x0420 */
- u32 pad09[59];
- u32 extwarmrstst_reg; /* 0x0510 */
- u32 apewarmrstst_reg; /* 0x0514 */
- u32 pad10[1];
- u32 c2cwarmrstst_reg; /* 0x051C */
-};
-
/* DPLL register offsets */
#define CM_CLKMODE_DPLL 0
#define CM_IDLEST_DPLL 0x4
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
-#define NUM_SYS_CLKS 7
-
-struct dpll_regs {
- u32 cm_clkmode_dpll;
- u32 cm_idlest_dpll;
- u32 cm_autoidle_dpll;
- u32 cm_clksel_dpll;
- u32 cm_div_m2_dpll;
- u32 cm_div_m3_dpll;
- u32 cm_div_m4_dpll;
- u32 cm_div_m5_dpll;
- u32 cm_div_m6_dpll;
- u32 cm_div_m7_dpll;
-};
-
-/* DPLL parameter table */
-struct dpll_params {
- u32 m;
- u32 n;
- s8 m2;
- s8 m3;
- s8 m4;
- s8 m5;
- s8 m6;
- s8 m7;
+struct omap4_scrm_regs {
+ u32 revision; /* 0x0000 */
+ u32 pad00[63];
+ u32 clksetuptime; /* 0x0100 */
+ u32 pmicsetuptime; /* 0x0104 */
+ u32 pad01[2];
+ u32 altclksrc; /* 0x0110 */
+ u32 pad02[2];
+ u32 c2cclkm; /* 0x011c */
+ u32 pad03[56];
+ u32 extclkreq; /* 0x0200 */
+ u32 accclkreq; /* 0x0204 */
+ u32 pwrreq; /* 0x0208 */
+ u32 pad04[1];
+ u32 auxclkreq0; /* 0x0210 */
+ u32 auxclkreq1; /* 0x0214 */
+ u32 auxclkreq2; /* 0x0218 */
+ u32 auxclkreq3; /* 0x021c */
+ u32 auxclkreq4; /* 0x0220 */
+ u32 auxclkreq5; /* 0x0224 */
+ u32 pad05[3];
+ u32 c2cclkreq; /* 0x0234 */
+ u32 pad06[54];
+ u32 auxclk0; /* 0x0310 */
+ u32 auxclk1; /* 0x0314 */
+ u32 auxclk2; /* 0x0318 */
+ u32 auxclk3; /* 0x031c */
+ u32 auxclk4; /* 0x0320 */
+ u32 auxclk5; /* 0x0324 */
+ u32 pad07[54];
+ u32 rsttime_reg; /* 0x0400 */
+ u32 pad08[6];
+ u32 c2crstctrl; /* 0x041c */
+ u32 extpwronrstctrl; /* 0x0420 */
+ u32 pad09[59];
+ u32 extwarmrstst_reg; /* 0x0510 */
+ u32 apewarmrstst_reg; /* 0x0514 */
+ u32 pad10[1];
+ u32 c2cwarmrstst_reg; /* 0x051C */
};
-
-extern struct omap4_prcm_regs *const prcm;
-extern const u32 sys_clk_array[8];
-
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-u32 omap_ddr_clk(void);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 *const base, const struct dpll_params *params);
-u32 get_sys_clk_index(void);
-void enable_basic_clocks(void);
-void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_hw_auto,
- u32 *const *clk_modules_explicit_en,
- u8 wait_for_enable);
-const struct dpll_params *get_mpu_dpll_params(void);
-const struct dpll_params *get_core_dpll_params(void);
-const struct dpll_params *get_per_dpll_params(void);
-const struct dpll_params *get_iva_dpll_params(void);
-const struct dpll_params *get_usb_dpll_params(void);
-const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP4_H_ */
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
-struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-};
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
#endif /* MMC_HOST_DEF_H */
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
-struct omap_sys_ctrl_regs {
- unsigned int pad1[129];
- unsigned int control_id_code; /* 0x4A002204 */
- unsigned int pad11[22];
- unsigned int control_std_fuse_opp_bgap; /* 0x4a002260 */
- unsigned int pad2[24]; /* 0x4a002264 */
- unsigned int control_status; /* 0x4a0022c4 */
- unsigned int pad3[22]; /* 0x4a0022c8 */
- unsigned int control_ldosram_iva_voltage_ctrl; /* 0x4A002320 */
- unsigned int control_ldosram_mpu_voltage_ctrl; /* 0x4A002324 */
- unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
- unsigned int pad4[260277];
- unsigned int control_pbiaslite; /* 0x4A100600 */
- unsigned int pad5[63];
- unsigned int control_efuse_1; /* 0x4A100700 */
- unsigned int control_efuse_2; /* 0x4A100704 */
-};
-
-struct control_lpddr2io_regs {
- unsigned int control_lpddr2io1_0;
- unsigned int control_lpddr2io1_1;
- unsigned int control_lpddr2io1_2;
- unsigned int control_lpddr2io1_3;
- unsigned int control_lpddr2io2_0;
- unsigned int control_lpddr2io2_1;
- unsigned int control_lpddr2io2_2;
- unsigned int control_lpddr2io2_3;
-};
#endif /* __ASSEMBLY__ */
/*
#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP4_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* ROM code defines */
/* Boot device */
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 0xFF
void set_pl310_ctrl_reg(u32 val);
void setup_clocks_for_console(void);
void prcm_init(void);
-void bypass_dpll(u32 *const base);
+void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap4_ddr_clk(void);
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
#include <common.h>
+#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
#define CM_CLKMODE_DPLL_MPU (OMAP54XX_L4_CORE_BASE + 0x4160)
#define CM_CLKSEL_CORE (OMAP54XX_L4_CORE_BASE + 0x4100)
-struct omap5_prcm_regs {
- /* cm1.ckgen */
- u32 cm_clksel_core; /* 4a004100 */
- u32 pad001[1]; /* 4a004104 */
- u32 cm_clksel_abe; /* 4a004108 */
- u32 pad002[1]; /* 4a00410c */
- u32 cm_dll_ctrl; /* 4a004110 */
- u32 pad003[3]; /* 4a004114 */
- u32 cm_clkmode_dpll_core; /* 4a004120 */
- u32 cm_idlest_dpll_core; /* 4a004124 */
- u32 cm_autoidle_dpll_core; /* 4a004128 */
- u32 cm_clksel_dpll_core; /* 4a00412c */
- u32 cm_div_m2_dpll_core; /* 4a004130 */
- u32 cm_div_m3_dpll_core; /* 4a004134 */
- u32 cm_div_h11_dpll_core; /* 4a004138 */
- u32 cm_div_h12_dpll_core; /* 4a00413c */
- u32 cm_div_h13_dpll_core; /* 4a004140 */
- u32 cm_div_h14_dpll_core; /* 4a004144 */
- u32 cm_ssc_deltamstep_dpll_core; /* 4a004148 */
- u32 cm_ssc_modfreqdiv_dpll_core; /* 4a00414c */
- u32 cm_emu_override_dpll_core; /* 4a004150 */
-
- u32 cm_div_h22_dpllcore; /* 4a004154 */
- u32 cm_div_h23_dpll_core; /* 4a004158 */
- u32 pad0041[1]; /* 4a00415c */
- u32 cm_clkmode_dpll_mpu; /* 4a004160 */
- u32 cm_idlest_dpll_mpu; /* 4a004164 */
- u32 cm_autoidle_dpll_mpu; /* 4a004168 */
- u32 cm_clksel_dpll_mpu; /* 4a00416c */
- u32 cm_div_m2_dpll_mpu; /* 4a004170 */
- u32 pad005[5]; /* 4a004174 */
- u32 cm_ssc_deltamstep_dpll_mpu; /* 4a004188 */
- u32 cm_ssc_modfreqdiv_dpll_mpu; /* 4a00418c */
- u32 pad006[3]; /* 4a004190 */
- u32 cm_bypclk_dpll_mpu; /* 4a00419c */
- u32 cm_clkmode_dpll_iva; /* 4a0041a0 */
- u32 cm_idlest_dpll_iva; /* 4a0041a4 */
- u32 cm_autoidle_dpll_iva; /* 4a0041a8 */
- u32 cm_clksel_dpll_iva; /* 4a0041ac */
- u32 pad007[2]; /* 4a0041b0 */
- u32 cm_div_h11_dpll_iva; /* 4a0041b8 */
- u32 cm_div_h12_dpll_iva; /* 4a0041bc */
- u32 pad008[2]; /* 4a0041c0 */
- u32 cm_ssc_deltamstep_dpll_iva; /* 4a0041c8 */
- u32 cm_ssc_modfreqdiv_dpll_iva; /* 4a0041cc */
- u32 pad009[3]; /* 4a0041d0 */
- u32 cm_bypclk_dpll_iva; /* 4a0041dc */
- u32 cm_clkmode_dpll_abe; /* 4a0041e0 */
- u32 cm_idlest_dpll_abe; /* 4a0041e4 */
- u32 cm_autoidle_dpll_abe; /* 4a0041e8 */
- u32 cm_clksel_dpll_abe; /* 4a0041ec */
- u32 cm_div_m2_dpll_abe; /* 4a0041f0 */
- u32 cm_div_m3_dpll_abe; /* 4a0041f4 */
- u32 pad010[4]; /* 4a0041f8 */
- u32 cm_ssc_deltamstep_dpll_abe; /* 4a004208 */
- u32 cm_ssc_modfreqdiv_dpll_abe; /* 4a00420c */
- u32 pad011[4]; /* 4a004210 */
- u32 cm_clkmode_dpll_ddrphy; /* 4a004220 */
- u32 cm_idlest_dpll_ddrphy; /* 4a004224 */
- u32 cm_autoidle_dpll_ddrphy; /* 4a004228 */
- u32 cm_clksel_dpll_ddrphy; /* 4a00422c */
- u32 cm_div_m2_dpll_ddrphy; /* 4a004230 */
- u32 pad012[1]; /* 4a004234 */
- u32 cm_div_h11_dpll_ddrphy; /* 4a004238 */
- u32 cm_div_h12_dpll_ddrphy; /* 4a00423c */
- u32 cm_div_h13_dpll_ddrphy; /* 4a004240 */
- u32 pad013[1]; /* 4a004244 */
- u32 cm_ssc_deltamstep_dpll_ddrphy; /* 4a004248 */
- u32 pad014[5]; /* 4a00424c */
- u32 cm_shadow_freq_config1; /* 4a004260 */
- u32 pad0141[47]; /* 4a004264 */
- u32 cm_mpu_mpu_clkctrl; /* 4a004320 */
-
-
- /* cm1.dsp */
- u32 pad015[55]; /* 4a004324 */
- u32 cm_dsp_clkstctrl; /* 4a004400 */
- u32 pad016[7]; /* 4a004404 */
- u32 cm_dsp_dsp_clkctrl; /* 4a004420 */
-
- /* cm1.abe */
- u32 pad017[55]; /* 4a004424 */
- u32 cm1_abe_clkstctrl; /* 4a004500 */
- u32 pad018[7]; /* 4a004504 */
- u32 cm1_abe_l4abe_clkctrl; /* 4a004520 */
- u32 pad019[1]; /* 4a004524 */
- u32 cm1_abe_aess_clkctrl; /* 4a004528 */
- u32 pad020[1]; /* 4a00452c */
- u32 cm1_abe_pdm_clkctrl; /* 4a004530 */
- u32 pad021[1]; /* 4a004534 */
- u32 cm1_abe_dmic_clkctrl; /* 4a004538 */
- u32 pad022[1]; /* 4a00453c */
- u32 cm1_abe_mcasp_clkctrl; /* 4a004540 */
- u32 pad023[1]; /* 4a004544 */
- u32 cm1_abe_mcbsp1_clkctrl; /* 4a004548 */
- u32 pad024[1]; /* 4a00454c */
- u32 cm1_abe_mcbsp2_clkctrl; /* 4a004550 */
- u32 pad025[1]; /* 4a004554 */
- u32 cm1_abe_mcbsp3_clkctrl; /* 4a004558 */
- u32 pad026[1]; /* 4a00455c */
- u32 cm1_abe_slimbus_clkctrl; /* 4a004560 */
- u32 pad027[1]; /* 4a004564 */
- u32 cm1_abe_timer5_clkctrl; /* 4a004568 */
- u32 pad028[1]; /* 4a00456c */
- u32 cm1_abe_timer6_clkctrl; /* 4a004570 */
- u32 pad029[1]; /* 4a004574 */
- u32 cm1_abe_timer7_clkctrl; /* 4a004578 */
- u32 pad030[1]; /* 4a00457c */
- u32 cm1_abe_timer8_clkctrl; /* 4a004580 */
- u32 pad031[1]; /* 4a004584 */
- u32 cm1_abe_wdt3_clkctrl; /* 4a004588 */
-
- /* cm2.ckgen */
- u32 pad032[3805]; /* 4a00458c */
- u32 cm_clksel_mpu_m3_iss_root; /* 4a008100 */
- u32 cm_clksel_usb_60mhz; /* 4a008104 */
- u32 cm_scale_fclk; /* 4a008108 */
- u32 pad033[1]; /* 4a00810c */
- u32 cm_core_dvfs_perf1; /* 4a008110 */
- u32 cm_core_dvfs_perf2; /* 4a008114 */
- u32 cm_core_dvfs_perf3; /* 4a008118 */
- u32 cm_core_dvfs_perf4; /* 4a00811c */
- u32 pad034[1]; /* 4a008120 */
- u32 cm_core_dvfs_current; /* 4a008124 */
- u32 cm_iva_dvfs_perf_tesla; /* 4a008128 */
- u32 cm_iva_dvfs_perf_ivahd; /* 4a00812c */
- u32 cm_iva_dvfs_perf_abe; /* 4a008130 */
- u32 pad035[1]; /* 4a008134 */
- u32 cm_iva_dvfs_current; /* 4a008138 */
- u32 pad036[1]; /* 4a00813c */
- u32 cm_clkmode_dpll_per; /* 4a008140 */
- u32 cm_idlest_dpll_per; /* 4a008144 */
- u32 cm_autoidle_dpll_per; /* 4a008148 */
- u32 cm_clksel_dpll_per; /* 4a00814c */
- u32 cm_div_m2_dpll_per; /* 4a008150 */
- u32 cm_div_m3_dpll_per; /* 4a008154 */
- u32 cm_div_h11_dpll_per; /* 4a008158 */
- u32 cm_div_h12_dpll_per; /* 4a00815c */
- u32 pad0361[1]; /* 4a008160 */
- u32 cm_div_h14_dpll_per; /* 4a008164 */
- u32 cm_ssc_deltamstep_dpll_per; /* 4a008168 */
- u32 cm_ssc_modfreqdiv_dpll_per; /* 4a00816c */
- u32 cm_emu_override_dpll_per; /* 4a008170 */
- u32 pad037[3]; /* 4a008174 */
- u32 cm_clkmode_dpll_usb; /* 4a008180 */
- u32 cm_idlest_dpll_usb; /* 4a008184 */
- u32 cm_autoidle_dpll_usb; /* 4a008188 */
- u32 cm_clksel_dpll_usb; /* 4a00818c */
- u32 cm_div_m2_dpll_usb; /* 4a008190 */
- u32 pad038[5]; /* 4a008194 */
- u32 cm_ssc_deltamstep_dpll_usb; /* 4a0081a8 */
- u32 cm_ssc_modfreqdiv_dpll_usb; /* 4a0081ac */
- u32 pad039[1]; /* 4a0081b0 */
- u32 cm_clkdcoldo_dpll_usb; /* 4a0081b4 */
- u32 pad040[2]; /* 4a0081b8 */
- u32 cm_clkmode_dpll_unipro; /* 4a0081c0 */
- u32 cm_idlest_dpll_unipro; /* 4a0081c4 */
- u32 cm_autoidle_dpll_unipro; /* 4a0081c8 */
- u32 cm_clksel_dpll_unipro; /* 4a0081cc */
- u32 cm_div_m2_dpll_unipro; /* 4a0081d0 */
- u32 pad041[5]; /* 4a0081d4 */
- u32 cm_ssc_deltamstep_dpll_unipro; /* 4a0081e8 */
- u32 cm_ssc_modfreqdiv_dpll_unipro; /* 4a0081ec */
-
- /* cm2.core */
- u32 pad0411[324]; /* 4a0081f0 */
- u32 cm_l3_1_clkstctrl; /* 4a008700 */
- u32 pad042[1]; /* 4a008704 */
- u32 cm_l3_1_dynamicdep; /* 4a008708 */
- u32 pad043[5]; /* 4a00870c */
- u32 cm_l3_1_l3_1_clkctrl; /* 4a008720 */
- u32 pad044[55]; /* 4a008724 */
- u32 cm_l3_2_clkstctrl; /* 4a008800 */
- u32 pad045[1]; /* 4a008804 */
- u32 cm_l3_2_dynamicdep; /* 4a008808 */
- u32 pad046[5]; /* 4a00880c */
- u32 cm_l3_2_l3_2_clkctrl; /* 4a008820 */
- u32 pad047[1]; /* 4a008824 */
- u32 cm_l3_2_gpmc_clkctrl; /* 4a008828 */
- u32 pad048[1]; /* 4a00882c */
- u32 cm_l3_2_ocmc_ram_clkctrl; /* 4a008830 */
- u32 pad049[51]; /* 4a008834 */
- u32 cm_mpu_m3_clkstctrl; /* 4a008900 */
- u32 cm_mpu_m3_staticdep; /* 4a008904 */
- u32 cm_mpu_m3_dynamicdep; /* 4a008908 */
- u32 pad050[5]; /* 4a00890c */
- u32 cm_mpu_m3_mpu_m3_clkctrl; /* 4a008920 */
- u32 pad051[55]; /* 4a008924 */
- u32 cm_sdma_clkstctrl; /* 4a008a00 */
- u32 cm_sdma_staticdep; /* 4a008a04 */
- u32 cm_sdma_dynamicdep; /* 4a008a08 */
- u32 pad052[5]; /* 4a008a0c */
- u32 cm_sdma_sdma_clkctrl; /* 4a008a20 */
- u32 pad053[55]; /* 4a008a24 */
- u32 cm_memif_clkstctrl; /* 4a008b00 */
- u32 pad054[7]; /* 4a008b04 */
- u32 cm_memif_dmm_clkctrl; /* 4a008b20 */
- u32 pad055[1]; /* 4a008b24 */
- u32 cm_memif_emif_fw_clkctrl; /* 4a008b28 */
- u32 pad056[1]; /* 4a008b2c */
- u32 cm_memif_emif_1_clkctrl; /* 4a008b30 */
- u32 pad057[1]; /* 4a008b34 */
- u32 cm_memif_emif_2_clkctrl; /* 4a008b38 */
- u32 pad058[1]; /* 4a008b3c */
- u32 cm_memif_dll_clkctrl; /* 4a008b40 */
- u32 pad059[3]; /* 4a008b44 */
- u32 cm_memif_emif_h1_clkctrl; /* 4a008b50 */
- u32 pad060[1]; /* 4a008b54 */
- u32 cm_memif_emif_h2_clkctrl; /* 4a008b58 */
- u32 pad061[1]; /* 4a008b5c */
- u32 cm_memif_dll_h_clkctrl; /* 4a008b60 */
- u32 pad062[39]; /* 4a008b64 */
- u32 cm_c2c_clkstctrl; /* 4a008c00 */
- u32 cm_c2c_staticdep; /* 4a008c04 */
- u32 cm_c2c_dynamicdep; /* 4a008c08 */
- u32 pad063[5]; /* 4a008c0c */
- u32 cm_c2c_sad2d_clkctrl; /* 4a008c20 */
- u32 pad064[1]; /* 4a008c24 */
- u32 cm_c2c_modem_icr_clkctrl; /* 4a008c28 */
- u32 pad065[1]; /* 4a008c2c */
- u32 cm_c2c_sad2d_fw_clkctrl; /* 4a008c30 */
- u32 pad066[51]; /* 4a008c34 */
- u32 cm_l4cfg_clkstctrl; /* 4a008d00 */
- u32 pad067[1]; /* 4a008d04 */
- u32 cm_l4cfg_dynamicdep; /* 4a008d08 */
- u32 pad068[5]; /* 4a008d0c */
- u32 cm_l4cfg_l4_cfg_clkctrl; /* 4a008d20 */
- u32 pad069[1]; /* 4a008d24 */
- u32 cm_l4cfg_hw_sem_clkctrl; /* 4a008d28 */
- u32 pad070[1]; /* 4a008d2c */
- u32 cm_l4cfg_mailbox_clkctrl; /* 4a008d30 */
- u32 pad071[1]; /* 4a008d34 */
- u32 cm_l4cfg_sar_rom_clkctrl; /* 4a008d38 */
- u32 pad072[49]; /* 4a008d3c */
- u32 cm_l3instr_clkstctrl; /* 4a008e00 */
- u32 pad073[7]; /* 4a008e04 */
- u32 cm_l3instr_l3_3_clkctrl; /* 4a008e20 */
- u32 pad074[1]; /* 4a008e24 */
- u32 cm_l3instr_l3_instr_clkctrl; /* 4a008e28 */
- u32 pad075[5]; /* 4a008e2c */
- u32 cm_l3instr_intrconn_wp1_clkctrl; /* 4a008e40 */
-
-
- /* cm2.ivahd */
- u32 pad076[47]; /* 4a008e44 */
- u32 cm_ivahd_clkstctrl; /* 4a008f00 */
- u32 pad077[7]; /* 4a008f04 */
- u32 cm_ivahd_ivahd_clkctrl; /* 4a008f20 */
- u32 pad078[1]; /* 4a008f24 */
- u32 cm_ivahd_sl2_clkctrl; /* 4a008f28 */
-
- /* cm2.cam */
- u32 pad079[53]; /* 4a008f2c */
- u32 cm_cam_clkstctrl; /* 4a009000 */
- u32 pad080[7]; /* 4a009004 */
- u32 cm_cam_iss_clkctrl; /* 4a009020 */
- u32 pad081[1]; /* 4a009024 */
- u32 cm_cam_fdif_clkctrl; /* 4a009028 */
-
- /* cm2.dss */
- u32 pad082[53]; /* 4a00902c */
- u32 cm_dss_clkstctrl; /* 4a009100 */
- u32 pad083[7]; /* 4a009104 */
- u32 cm_dss_dss_clkctrl; /* 4a009120 */
-
- /* cm2.sgx */
- u32 pad084[55]; /* 4a009124 */
- u32 cm_sgx_clkstctrl; /* 4a009200 */
- u32 pad085[7]; /* 4a009204 */
- u32 cm_sgx_sgx_clkctrl; /* 4a009220 */
-
- /* cm2.l3init */
- u32 pad086[55]; /* 4a009224 */
- u32 cm_l3init_clkstctrl; /* 4a009300 */
-
- /* cm2.l3init */
- u32 pad087[9]; /* 4a009304 */
- u32 cm_l3init_hsmmc1_clkctrl; /* 4a009328 */
- u32 pad088[1]; /* 4a00932c */
- u32 cm_l3init_hsmmc2_clkctrl; /* 4a009330 */
- u32 pad089[1]; /* 4a009334 */
- u32 cm_l3init_hsi_clkctrl; /* 4a009338 */
- u32 pad090[7]; /* 4a00933c */
- u32 cm_l3init_hsusbhost_clkctrl; /* 4a009358 */
- u32 pad091[1]; /* 4a00935c */
- u32 cm_l3init_hsusbotg_clkctrl; /* 4a009360 */
- u32 pad092[1]; /* 4a009364 */
- u32 cm_l3init_hsusbtll_clkctrl; /* 4a009368 */
- u32 pad093[3]; /* 4a00936c */
- u32 cm_l3init_p1500_clkctrl; /* 4a009378 */
- u32 pad094[21]; /* 4a00937c */
- u32 cm_l3init_fsusb_clkctrl; /* 4a0093d0 */
- u32 pad095[3]; /* 4a0093d4 */
- u32 cm_l3init_ocp2scp1_clkctrl;
-
- /* cm2.l4per */
- u32 pad096[7]; /* 4a0093e4 */
- u32 cm_l4per_clkstctrl; /* 4a009400 */
- u32 pad097[1]; /* 4a009404 */
- u32 cm_l4per_dynamicdep; /* 4a009408 */
- u32 pad098[5]; /* 4a00940c */
- u32 cm_l4per_adc_clkctrl; /* 4a009420 */
- u32 pad100[1]; /* 4a009424 */
- u32 cm_l4per_gptimer10_clkctrl; /* 4a009428 */
- u32 pad101[1]; /* 4a00942c */
- u32 cm_l4per_gptimer11_clkctrl; /* 4a009430 */
- u32 pad102[1]; /* 4a009434 */
- u32 cm_l4per_gptimer2_clkctrl; /* 4a009438 */
- u32 pad103[1]; /* 4a00943c */
- u32 cm_l4per_gptimer3_clkctrl; /* 4a009440 */
- u32 pad104[1]; /* 4a009444 */
- u32 cm_l4per_gptimer4_clkctrl; /* 4a009448 */
- u32 pad105[1]; /* 4a00944c */
- u32 cm_l4per_gptimer9_clkctrl; /* 4a009450 */
- u32 pad106[1]; /* 4a009454 */
- u32 cm_l4per_elm_clkctrl; /* 4a009458 */
- u32 pad107[1]; /* 4a00945c */
- u32 cm_l4per_gpio2_clkctrl; /* 4a009460 */
- u32 pad108[1]; /* 4a009464 */
- u32 cm_l4per_gpio3_clkctrl; /* 4a009468 */
- u32 pad109[1]; /* 4a00946c */
- u32 cm_l4per_gpio4_clkctrl; /* 4a009470 */
- u32 pad110[1]; /* 4a009474 */
- u32 cm_l4per_gpio5_clkctrl; /* 4a009478 */
- u32 pad111[1]; /* 4a00947c */
- u32 cm_l4per_gpio6_clkctrl; /* 4a009480 */
- u32 pad112[1]; /* 4a009484 */
- u32 cm_l4per_hdq1w_clkctrl; /* 4a009488 */
- u32 pad113[1]; /* 4a00948c */
- u32 cm_l4per_hecc1_clkctrl; /* 4a009490 */
- u32 pad114[1]; /* 4a009494 */
- u32 cm_l4per_hecc2_clkctrl; /* 4a009498 */
- u32 pad115[1]; /* 4a00949c */
- u32 cm_l4per_i2c1_clkctrl; /* 4a0094a0 */
- u32 pad116[1]; /* 4a0094a4 */
- u32 cm_l4per_i2c2_clkctrl; /* 4a0094a8 */
- u32 pad117[1]; /* 4a0094ac */
- u32 cm_l4per_i2c3_clkctrl; /* 4a0094b0 */
- u32 pad118[1]; /* 4a0094b4 */
- u32 cm_l4per_i2c4_clkctrl; /* 4a0094b8 */
- u32 pad119[1]; /* 4a0094bc */
- u32 cm_l4per_l4per_clkctrl; /* 4a0094c0 */
- u32 pad1191[3]; /* 4a0094c4 */
- u32 cm_l4per_mcasp2_clkctrl; /* 4a0094d0 */
- u32 pad120[1]; /* 4a0094d4 */
- u32 cm_l4per_mcasp3_clkctrl; /* 4a0094d8 */
- u32 pad121[3]; /* 4a0094dc */
- u32 cm_l4per_mgate_clkctrl; /* 4a0094e8 */
- u32 pad123[1]; /* 4a0094ec */
- u32 cm_l4per_mcspi1_clkctrl; /* 4a0094f0 */
- u32 pad124[1]; /* 4a0094f4 */
- u32 cm_l4per_mcspi2_clkctrl; /* 4a0094f8 */
- u32 pad125[1]; /* 4a0094fc */
- u32 cm_l4per_mcspi3_clkctrl; /* 4a009500 */
- u32 pad126[1]; /* 4a009504 */
- u32 cm_l4per_mcspi4_clkctrl; /* 4a009508 */
- u32 pad127[1]; /* 4a00950c */
- u32 cm_l4per_gpio7_clkctrl; /* 4a009510 */
- u32 pad1271[1]; /* 4a009514 */
- u32 cm_l4per_gpio8_clkctrl; /* 4a009518 */
- u32 pad1272[1]; /* 4a00951c */
- u32 cm_l4per_mmcsd3_clkctrl; /* 4a009520 */
- u32 pad128[1]; /* 4a009524 */
- u32 cm_l4per_mmcsd4_clkctrl; /* 4a009528 */
- u32 pad129[1]; /* 4a00952c */
- u32 cm_l4per_msprohg_clkctrl; /* 4a009530 */
- u32 pad130[1]; /* 4a009534 */
- u32 cm_l4per_slimbus2_clkctrl; /* 4a009538 */
- u32 pad131[1]; /* 4a00953c */
- u32 cm_l4per_uart1_clkctrl; /* 4a009540 */
- u32 pad132[1]; /* 4a009544 */
- u32 cm_l4per_uart2_clkctrl; /* 4a009548 */
- u32 pad133[1]; /* 4a00954c */
- u32 cm_l4per_uart3_clkctrl; /* 4a009550 */
- u32 pad134[1]; /* 4a009554 */
- u32 cm_l4per_uart4_clkctrl; /* 4a009558 */
- u32 pad135[1]; /* 4a00955c */
- u32 cm_l4per_mmcsd5_clkctrl; /* 4a009560 */
- u32 pad136[1]; /* 4a009564 */
- u32 cm_l4per_i2c5_clkctrl; /* 4a009568 */
- u32 pad1371[1]; /* 4a00956c */
- u32 cm_l4per_uart5_clkctrl; /* 4a009570 */
- u32 pad1372[1]; /* 4a009574 */
- u32 cm_l4per_uart6_clkctrl; /* 4a009578 */
- u32 pad1374[1]; /* 4a00957c */
- u32 cm_l4sec_clkstctrl; /* 4a009580 */
- u32 cm_l4sec_staticdep; /* 4a009584 */
- u32 cm_l4sec_dynamicdep; /* 4a009588 */
- u32 pad138[5]; /* 4a00958c */
- u32 cm_l4sec_aes1_clkctrl; /* 4a0095a0 */
- u32 pad139[1]; /* 4a0095a4 */
- u32 cm_l4sec_aes2_clkctrl; /* 4a0095a8 */
- u32 pad140[1]; /* 4a0095ac */
- u32 cm_l4sec_des3des_clkctrl; /* 4a0095b0 */
- u32 pad141[1]; /* 4a0095b4 */
- u32 cm_l4sec_pkaeip29_clkctrl; /* 4a0095b8 */
- u32 pad142[1]; /* 4a0095bc */
- u32 cm_l4sec_rng_clkctrl; /* 4a0095c0 */
- u32 pad143[1]; /* 4a0095c4 */
- u32 cm_l4sec_sha2md51_clkctrl; /* 4a0095c8 */
- u32 pad144[3]; /* 4a0095cc */
- u32 cm_l4sec_cryptodma_clkctrl; /* 4a0095d8 */
- u32 pad145[3660425]; /* 4a0095dc */
-
- /* l4 wkup regs */
- u32 pad201[6211]; /* 4ae00000 */
- u32 cm_abe_pll_ref_clksel; /* 4ae0610c */
- u32 cm_sys_clksel; /* 4ae06110 */
- u32 pad202[1467]; /* 4ae06114 */
- u32 cm_wkup_clkstctrl; /* 4ae07800 */
- u32 pad203[7]; /* 4ae07804 */
- u32 cm_wkup_l4wkup_clkctrl; /* 4ae07820 */
- u32 pad204; /* 4ae07824 */
- u32 cm_wkup_wdtimer1_clkctrl; /* 4ae07828 */
- u32 pad205; /* 4ae0782c */
- u32 cm_wkup_wdtimer2_clkctrl; /* 4ae07830 */
- u32 pad206; /* 4ae07834 */
- u32 cm_wkup_gpio1_clkctrl; /* 4ae07838 */
- u32 pad207; /* 4ae0783c */
- u32 cm_wkup_gptimer1_clkctrl; /* 4ae07840 */
- u32 pad208; /* 4ae07844 */
- u32 cm_wkup_gptimer12_clkctrl; /* 4ae07848 */
- u32 pad209; /* 4ae0784c */
- u32 cm_wkup_synctimer_clkctrl; /* 4ae07850 */
- u32 pad210; /* 4ae07854 */
- u32 cm_wkup_usim_clkctrl; /* 4ae07858 */
- u32 pad211; /* 4ae0785c */
- u32 cm_wkup_sarram_clkctrl; /* 4ae07860 */
- u32 pad212[5]; /* 4ae07864 */
- u32 cm_wkup_keyboard_clkctrl; /* 4ae07878 */
- u32 pad213; /* 4ae0787c */
- u32 cm_wkup_rtc_clkctrl; /* 4ae07880 */
- u32 pad214; /* 4ae07884 */
- u32 cm_wkup_bandgap_clkctrl; /* 4ae07888 */
- u32 pad215[1]; /* 4ae0788c */
- u32 cm_wkupaon_scrm_clkctrl; /* 4ae07890 */
- u32 pad216[195];
- u32 prm_vc_val_bypass; /* 4ae07ba0 */
- u32 pad217[4];
- u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */
- u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */
- u32 pad218[2];
- u32 prm_sldo_core_setup; /* 4ae07bc4 */
- u32 prm_sldo_core_ctrl; /* 4ae07bc8 */
- u32 prm_sldo_mpu_setup; /* 4ae07bcc */
- u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */
- u32 prm_sldo_mm_setup; /* 4ae07bd4 */
- u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */
-};
-
/* DPLL register offsets */
#define CM_CLKMODE_DPLL 0
#define CM_IDLEST_DPLL 0x4
/* CM_MPU_MPU_CLKCTRL */
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
/* CM_WKUPAON_SCRM_CLKCTRL */
#define OPTFCLKEN_SCRM_PER_SHIFT 9
#define OPTFCLKEN_SCRM_CORE_SHIFT 8
#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
+/* CM_COREAON_IO_SRCOMP_CLKCTRL */
+#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
+#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
+
/* Clock frequencies */
#define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000
#define OMAP_SYS_CLK_IND_38_4_MHZ 6
#define SMPS_REG_ADDR_8_CORE 0x37
/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
-#define VDD_MPU 1000
-#define VDD_MM 1000
+/* ES1.0 settings */
+#define VDD_MPU 1040
+#define VDD_MM 1040
#define VDD_CORE 1040
-#define VDD_MPU_5432 1150
-#define VDD_MM_5432 1150
-#define VDD_CORE_5432 1150
+
+#define VDD_MPU_LOW 890
+#define VDD_MM_LOW 890
+#define VDD_CORE_LOW 890
+
+/* ES2.0 settings */
+#define VDD_MPU_ES2 1060
+#define VDD_MM_ES2 1025
+#define VDD_CORE_ES2 1040
+
+#define VDD_MPU_ES2_HIGH 1250
+#define VDD_MM_ES2_OD 1120
+
+#define VDD_MPU_ES2_LOW 880
+#define VDD_MM_ES2_LOW 880
/* Standard offset is 0.5v expressed in uv */
#define PALMAS_SMPS_BASE_VOLT_UV 500000
#define DPLL_NO_LOCK 0
#define DPLL_LOCK 1
-#define NUM_SYS_CLKS 7
-
-struct dpll_regs {
- u32 cm_clkmode_dpll;
- u32 cm_idlest_dpll;
- u32 cm_autoidle_dpll;
- u32 cm_clksel_dpll;
- u32 cm_div_m2_dpll;
- u32 cm_div_m3_dpll;
- u32 cm_div_h11_dpll;
- u32 cm_div_h12_dpll;
- u32 cm_div_h13_dpll;
- u32 cm_div_h14_dpll;
- u32 reserved[3];
- u32 cm_div_h22_dpll;
- u32 cm_div_h23_dpll;
-};
-
-/* DPLL parameter table */
-struct dpll_params {
- u32 m;
- u32 n;
- s8 m2;
- s8 m3;
- s8 h11;
- s8 h12;
- s8 h13;
- s8 h14;
- s8 h22;
- s8 h23;
-};
-
-extern struct omap5_prcm_regs *const prcm;
-extern const u32 sys_clk_array[8];
-
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-u32 omap_ddr_clk(void);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 *const base, const struct dpll_params *params);
-u32 get_sys_clk_index(void);
-void enable_basic_clocks(void);
-void enable_non_essential_clocks(void);
-void enable_basic_uboot_clocks(void);
-void do_enable_clocks(u32 *const *clk_domains,
- u32 *const *clk_modules_hw_auto,
- u32 *const *clk_modules_explicit_en,
- u8 wait_for_enable);
-const struct dpll_params *get_mpu_dpll_params(void);
-const struct dpll_params *get_core_dpll_params(void);
-const struct dpll_params *get_per_dpll_params(void);
-const struct dpll_params *get_iva_dpll_params(void);
-const struct dpll_params *get_usb_dpll_params(void);
-const struct dpll_params *get_abe_dpll_params(void);
#endif /* _CLOCKS_OMAP5_H_ */
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
+#include <asm/omap_mmc.h>
+
/*
* OMAP HSMMC register definitions
*/
#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
-struct hsmmc {
- unsigned char res1[0x10];
- unsigned int sysconfig; /* 0x10 */
- unsigned int sysstatus; /* 0x14 */
- unsigned char res2[0x14];
- unsigned int con; /* 0x2C */
- unsigned char res3[0xD4];
- unsigned int blk; /* 0x104 */
- unsigned int arg; /* 0x108 */
- unsigned int cmd; /* 0x10C */
- unsigned int rsp10; /* 0x110 */
- unsigned int rsp32; /* 0x114 */
- unsigned int rsp54; /* 0x118 */
- unsigned int rsp76; /* 0x11C */
- unsigned int data; /* 0x120 */
- unsigned int pstate; /* 0x124 */
- unsigned int hctl; /* 0x128 */
- unsigned int sysctl; /* 0x12C */
- unsigned int stat; /* 0x130 */
- unsigned int ie; /* 0x134 */
- unsigned char res4[0x8];
- unsigned int capa; /* 0x140 */
-};
-
-/*
- * OMAP HS MMC Bit definitions
- */
-#define MMC_SOFTRESET (0x1 << 1)
-#define RESETDONE (0x1 << 0)
-#define NOOPENDRAIN (0x0 << 0)
-#define OPENDRAIN (0x1 << 0)
-#define OD (0x1 << 0)
-#define INIT_NOINIT (0x0 << 1)
-#define INIT_INITSTREAM (0x1 << 1)
-#define HR_NOHOSTRESP (0x0 << 2)
-#define STR_BLOCK (0x0 << 3)
-#define MODE_FUNC (0x0 << 4)
-#define DW8_1_4BITMODE (0x0 << 5)
-#define MIT_CTO (0x0 << 6)
-#define CDP_ACTIVEHIGH (0x0 << 7)
-#define WPP_ACTIVEHIGH (0x0 << 8)
-#define RESERVED_MASK (0x3 << 9)
-#define CTPL_MMC_SD (0x0 << 11)
-#define BLEN_512BYTESLEN (0x200 << 0)
-#define NBLK_STPCNT (0x0 << 16)
-#define DE_DISABLE (0x0 << 0)
-#define BCE_DISABLE (0x0 << 1)
-#define BCE_ENABLE (0x1 << 1)
-#define ACEN_DISABLE (0x0 << 2)
-#define DDIR_OFFSET (4)
-#define DDIR_MASK (0x1 << 4)
-#define DDIR_WRITE (0x0 << 4)
-#define DDIR_READ (0x1 << 4)
-#define MSBS_SGLEBLK (0x0 << 5)
-#define MSBS_MULTIBLK (0x1 << 5)
-#define RSP_TYPE_OFFSET (16)
-#define RSP_TYPE_MASK (0x3 << 16)
-#define RSP_TYPE_NORSP (0x0 << 16)
-#define RSP_TYPE_LGHT136 (0x1 << 16)
-#define RSP_TYPE_LGHT48 (0x2 << 16)
-#define RSP_TYPE_LGHT48B (0x3 << 16)
-#define CCCE_NOCHECK (0x0 << 19)
-#define CCCE_CHECK (0x1 << 19)
-#define CICE_NOCHECK (0x0 << 20)
-#define CICE_CHECK (0x1 << 20)
-#define DP_OFFSET (21)
-#define DP_MASK (0x1 << 21)
-#define DP_NO_DATA (0x0 << 21)
-#define DP_DATA (0x1 << 21)
-#define CMD_TYPE_NORMAL (0x0 << 22)
-#define INDEX_OFFSET (24)
-#define INDEX_MASK (0x3f << 24)
-#define INDEX(i) (i << 24)
-#define DATI_MASK (0x1 << 1)
-#define CMDI_MASK (0x1 << 0)
-#define DTW_1_BITMODE (0x0 << 1)
-#define DTW_4_BITMODE (0x1 << 1)
-#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
-#define SDBP_PWROFF (0x0 << 8)
-#define SDBP_PWRON (0x1 << 8)
-#define SDVS_1V8 (0x5 << 9)
-#define SDVS_3V0 (0x6 << 9)
-#define ICE_MASK (0x1 << 0)
-#define ICE_STOP (0x0 << 0)
-#define ICS_MASK (0x1 << 1)
-#define ICS_NOTREADY (0x0 << 1)
-#define ICE_OSCILLATE (0x1 << 0)
-#define CEN_MASK (0x1 << 2)
-#define CEN_DISABLE (0x0 << 2)
-#define CEN_ENABLE (0x1 << 2)
-#define CLKD_OFFSET (6)
-#define CLKD_MASK (0x3FF << 6)
-#define DTO_MASK (0xF << 16)
-#define DTO_15THDTO (0xE << 16)
-#define SOFTRESETALL (0x1 << 24)
-#define CC_MASK (0x1 << 0)
-#define TC_MASK (0x1 << 1)
-#define BWR_MASK (0x1 << 4)
-#define BRR_MASK (0x1 << 5)
-#define ERRI_MASK (0x1 << 15)
-#define IE_CC (0x01 << 0)
-#define IE_TC (0x01 << 1)
-#define IE_BWR (0x01 << 4)
-#define IE_BRR (0x01 << 5)
-#define IE_CTO (0x01 << 16)
-#define IE_CCRC (0x01 << 17)
-#define IE_CEB (0x01 << 18)
-#define IE_CIE (0x01 << 19)
-#define IE_DTO (0x01 << 20)
-#define IE_DCRC (0x01 << 21)
-#define IE_DEB (0x01 << 22)
-#define IE_CERR (0x01 << 28)
-#define IE_BADA (0x01 << 29)
-
-#define VS30_3V0SUP (1 << 25)
-#define VS18_1V8SUP (1 << 26)
-
-/* Driver definitions */
-#define MMCSD_SECTOR_SIZE 512
-#define MMC_CARD 0
-#define SD_CARD 1
-#define BYTE_MODE 0
-#define SECTOR_MODE 1
-#define CLK_INITSEQ 0
-#define CLK_400KHZ 1
-#define CLK_MISC 2
-
-#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
-#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
-
-/* Clock Configurations and Macros */
-#define MMC_CLOCK_REFERENCE 96 /* MHz */
-
-#define mmc_reg_out(addr, mask, val)\
- writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
-
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
-
#endif /* MMC_HOST_DEF_H */
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated
+ *
+ * Nishant Kamat <nskamat@ti.com>
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_DRA7XX_H_
+#define _MUX_DRA7XX_H_
+
+#include <asm/types.h>
+
+#define IEN (1 << 18)
+#define IDIS (0 << 18)
+
+#define PTU (3 << 16)
+#define PTD (1 << 16)
+#define PEN (1 << 16)
+#define PDIS (0 << 16)
+
+#define WKEN (1 << 24)
+#define WKDIS (0 << 24)
+
+#define M0 0
+#define M1 1
+#define M2 2
+#define M3 3
+#define M4 4
+#define M5 5
+#define M6 6
+#define M7 7
+#define M8 8
+#define M9 9
+#define M10 10
+#define M11 11
+#define M12 12
+#define M13 13
+#define M14 14
+#define M15 15
+
+#define SAFE_MODE M15
+
+#define GPMC_AD0 0x000
+#define GPMC_AD1 0x004
+#define GPMC_AD2 0x008
+#define GPMC_AD3 0x00C
+#define GPMC_AD4 0x010
+#define GPMC_AD5 0x014
+#define GPMC_AD6 0x018
+#define GPMC_AD7 0x01C
+#define GPMC_AD8 0x020
+#define GPMC_AD9 0x024
+#define GPMC_AD10 0x028
+#define GPMC_AD11 0x02C
+#define GPMC_AD12 0x030
+#define GPMC_AD13 0x034
+#define GPMC_AD14 0x038
+#define GPMC_AD15 0x03C
+#define GPMC_A0 0x040
+#define GPMC_A1 0x044
+#define GPMC_A2 0x048
+#define GPMC_A3 0x04C
+#define GPMC_A4 0x050
+#define GPMC_A5 0x054
+#define GPMC_A6 0x058
+#define GPMC_A7 0x05C
+#define GPMC_A8 0x060
+#define GPMC_A9 0x064
+#define GPMC_A10 0x068
+#define GPMC_A11 0x06C
+#define GPMC_A12 0x070
+#define GPMC_A13 0x074
+#define GPMC_A14 0x078
+#define GPMC_A15 0x07C
+#define GPMC_A16 0x080
+#define GPMC_A17 0x084
+#define GPMC_A18 0x088
+#define GPMC_A19 0x08C
+#define GPMC_A20 0x090
+#define GPMC_A21 0x094
+#define GPMC_A22 0x098
+#define GPMC_A23 0x09C
+#define GPMC_A24 0x0A0
+#define GPMC_A25 0x0A4
+#define GPMC_A26 0x0A8
+#define GPMC_A27 0x0AC
+#define GPMC_CS1 0x0B0
+#define GPMC_CS0 0x0B4
+#define GPMC_CS2 0x0B8
+#define GPMC_CS3 0x0BC
+#define GPMC_CLK 0x0C0
+#define GPMC_ADVN_ALE 0x0C4
+#define GPMC_OEN_REN 0x0C8
+#define GPMC_WEN 0x0CC
+#define GPMC_BEN0 0x0D0
+#define GPMC_BEN1 0x0D4
+#define GPMC_WAIT0 0x0D8
+#define VIN1A_CLK0 0x0DC
+#define VIN1B_CLK1 0x0E0
+#define VIN1A_DE0 0x0E4
+#define VIN1A_FLD0 0x0E8
+#define VIN1A_HSYNC0 0x0EC
+#define VIN1A_VSYNC0 0x0F0
+#define VIN1A_D0 0x0F4
+#define VIN1A_D1 0x0F8
+#define VIN1A_D2 0x0FC
+#define VIN1A_D3 0x100
+#define VIN1A_D4 0x104
+#define VIN1A_D5 0x108
+#define VIN1A_D6 0x10C
+#define VIN1A_D7 0x110
+#define VIN1A_D8 0x114
+#define VIN1A_D9 0x118
+#define VIN1A_D10 0x11C
+#define VIN1A_D11 0x120
+#define VIN1A_D12 0x124
+#define VIN1A_D13 0x128
+#define VIN1A_D14 0x12C
+#define VIN1A_D15 0x130
+#define VIN1A_D16 0x134
+#define VIN1A_D17 0x138
+#define VIN1A_D18 0x13C
+#define VIN1A_D19 0x140
+#define VIN1A_D20 0x144
+#define VIN1A_D21 0x148
+#define VIN1A_D22 0x14C
+#define VIN1A_D23 0x150
+#define VIN2A_CLK0 0x154
+#define VIN2A_DE0 0x158
+#define VIN2A_FLD0 0x15C
+#define VIN2A_HSYNC0 0x160
+#define VIN2A_VSYNC0 0x164
+#define VIN2A_D0 0x168
+#define VIN2A_D1 0x16C
+#define VIN2A_D2 0x170
+#define VIN2A_D3 0x174
+#define VIN2A_D4 0x178
+#define VIN2A_D5 0x17C
+#define VIN2A_D6 0x180
+#define VIN2A_D7 0x184
+#define VIN2A_D8 0x188
+#define VIN2A_D9 0x18C
+#define VIN2A_D10 0x190
+#define VIN2A_D11 0x194
+#define VIN2A_D12 0x198
+#define VIN2A_D13 0x19C
+#define VIN2A_D14 0x1A0
+#define VIN2A_D15 0x1A4
+#define VIN2A_D16 0x1A8
+#define VIN2A_D17 0x1AC
+#define VIN2A_D18 0x1B0
+#define VIN2A_D19 0x1B4
+#define VIN2A_D20 0x1B8
+#define VIN2A_D21 0x1BC
+#define VIN2A_D22 0x1C0
+#define VIN2A_D23 0x1C4
+#define VOUT1_CLK 0x1C8
+#define VOUT1_DE 0x1CC
+#define VOUT1_FLD 0x1D0
+#define VOUT1_HSYNC 0x1D4
+#define VOUT1_VSYNC 0x1D8
+#define VOUT1_D0 0x1DC
+#define VOUT1_D1 0x1E0
+#define VOUT1_D2 0x1E4
+#define VOUT1_D3 0x1E8
+#define VOUT1_D4 0x1EC
+#define VOUT1_D5 0x1F0
+#define VOUT1_D6 0x1F4
+#define VOUT1_D7 0x1F8
+#define VOUT1_D8 0x1FC
+#define VOUT1_D9 0x200
+#define VOUT1_D10 0x204
+#define VOUT1_D11 0x208
+#define VOUT1_D12 0x20C
+#define VOUT1_D13 0x210
+#define VOUT1_D14 0x214
+#define VOUT1_D15 0x218
+#define VOUT1_D16 0x21C
+#define VOUT1_D17 0x220
+#define VOUT1_D18 0x224
+#define VOUT1_D19 0x228
+#define VOUT1_D20 0x22C
+#define VOUT1_D21 0x230
+#define VOUT1_D22 0x234
+#define VOUT1_D23 0x238
+#define MDIO_MCLK 0x23C
+#define MDIO_D 0x240
+#define RMII_MHZ_50_CLK 0x244
+#define UART3_RXD 0x248
+#define UART3_TXD 0x24C
+#define RGMII0_TXC 0x250
+#define RGMII0_TXCTL 0x254
+#define RGMII0_TXD3 0x258
+#define RGMII0_TXD2 0x25C
+#define RGMII0_TXD1 0x260
+#define RGMII0_TXD0 0x264
+#define RGMII0_RXC 0x268
+#define RGMII0_RXCTL 0x26C
+#define RGMII0_RXD3 0x270
+#define RGMII0_RXD2 0x274
+#define RGMII0_RXD1 0x278
+#define RGMII0_RXD0 0x27C
+#define USB1_DRVVBUS 0x280
+#define USB2_DRVVBUS 0x284
+#define GPIO6_14 0x288
+#define GPIO6_15 0x28C
+#define GPIO6_16 0x290
+#define XREF_CLK0 0x294
+#define XREF_CLK1 0x298
+#define XREF_CLK2 0x29C
+#define XREF_CLK3 0x2A0
+#define MCASP1_ACLKX 0x2A4
+#define MCASP1_FSX 0x2A8
+#define MCASP1_ACLKR 0x2AC
+#define MCASP1_FSR 0x2B0
+#define MCASP1_AXR0 0x2B4
+#define MCASP1_AXR1 0x2B8
+#define MCASP1_AXR2 0x2BC
+#define MCASP1_AXR3 0x2C0
+#define MCASP1_AXR4 0x2C4
+#define MCASP1_AXR5 0x2C8
+#define MCASP1_AXR6 0x2CC
+#define MCASP1_AXR7 0x2D0
+#define MCASP1_AXR8 0x2D4
+#define MCASP1_AXR9 0x2D8
+#define MCASP1_AXR10 0x2DC
+#define MCASP1_AXR11 0x2E0
+#define MCASP1_AXR12 0x2E4
+#define MCASP1_AXR13 0x2E8
+#define MCASP1_AXR14 0x2EC
+#define MCASP1_AXR15 0x2F0
+#define MCASP2_ACLKX 0x2F4
+#define MCASP2_FSX 0x2F8
+#define MCASP2_ACLKR 0x2FC
+#define MCASP2_FSR 0x300
+#define MCASP2_AXR0 0x304
+#define MCASP2_AXR1 0x308
+#define MCASP2_AXR2 0x30C
+#define MCASP2_AXR3 0x310
+#define MCASP2_AXR4 0x314
+#define MCASP2_AXR5 0x318
+#define MCASP2_AXR6 0x31C
+#define MCASP2_AXR7 0x320
+#define MCASP3_ACLKX 0x324
+#define MCASP3_FSX 0x328
+#define MCASP3_AXR0 0x32C
+#define MCASP3_AXR1 0x330
+#define MCASP4_ACLKX 0x334
+#define MCASP4_FSX 0x338
+#define MCASP4_AXR0 0x33C
+#define MCASP4_AXR1 0x340
+#define MCASP5_ACLKX 0x344
+#define MCASP5_FSX 0x348
+#define MCASP5_AXR0 0x34C
+#define MCASP5_AXR1 0x350
+#define MMC1_CLK 0x354
+#define MMC1_CMD 0x358
+#define MMC1_DAT0 0x35C
+#define MMC1_DAT1 0x360
+#define MMC1_DAT2 0x364
+#define MMC1_DAT3 0x368
+#define MMC1_SDCD 0x36C
+#define MMC1_SDWP 0x370
+#define GPIO6_10 0x374
+#define GPIO6_11 0x378
+#define MMC3_CLK 0x37C
+#define MMC3_CMD 0x380
+#define MMC3_DAT0 0x384
+#define MMC3_DAT1 0x388
+#define MMC3_DAT2 0x38C
+#define MMC3_DAT3 0x390
+#define MMC3_DAT4 0x394
+#define MMC3_DAT5 0x398
+#define MMC3_DAT6 0x39C
+#define MMC3_DAT7 0x3A0
+#define SPI1_SCLK 0x3A4
+#define SPI1_D1 0x3A8
+#define SPI1_D0 0x3AC
+#define SPI1_CS0 0x3B0
+#define SPI1_CS1 0x3B4
+#define SPI1_CS2 0x3B8
+#define SPI1_CS3 0x3BC
+#define SPI2_SCLK 0x3C0
+#define SPI2_D1 0x3C4
+#define SPI2_D0 0x3C8
+#define SPI2_CS0 0x3CC
+#define DCAN1_TX 0x3D0
+#define DCAN1_RX 0x3D4
+#define DCAN2_TX 0x3D8
+#define DCAN2_RX 0x3DC
+#define UART1_RXD 0x3E0
+#define UART1_TXD 0x3E4
+#define UART1_CTSN 0x3E8
+#define UART1_RTSN 0x3EC
+#define UART2_RXD 0x3F0
+#define UART2_TXD 0x3F4
+#define UART2_CTSN 0x3F8
+#define UART2_RTSN 0x3FC
+#define I2C1_SDA 0x400
+#define I2C1_SCL 0x404
+#define I2C2_SDA 0x408
+#define I2C2_SCL 0x40C
+#define I2C3_SDA 0x410
+#define I2C3_SCL 0x414
+#define WAKEUP0 0x418
+#define WAKEUP1 0x41C
+#define WAKEUP2 0x420
+#define WAKEUP3 0x424
+#define ON_OFF 0x428
+#define RTC_PORZ 0x42C
+#define TMS 0x430
+#define TDI 0x434
+#define TDO 0x438
+#define TCLK 0x43C
+#define TRSTN 0x440
+#define RTCK 0x444
+#define EMU0 0x448
+#define EMU1 0x44C
+#define EMU2 0x450
+#define EMU3 0x454
+#define EMU4 0x458
+#define RESETN 0x45C
+#define NMIN 0x460
+#define RSTOUTN 0x464
+
+#endif /* _MUX_DRA7XX_H_ */
#include <asm/types.h>
-struct pad_conf_entry {
-
- u16 offset;
-
- u16 val;
-
-};
-
#ifdef CONFIG_OFF_PADCONF
#define OFF_PD (1 << 12)
#define OFF_PU (3 << 12)
/* To be verified */
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
+#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
+#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
+#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
/* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#define DEVICE_GP 0x3
-struct omap_sys_ctrl_regs {
- u32 pad0[77]; /* 0x4A002000 */
- u32 control_status; /* 0x4A002134 */
- u32 pad1[794]; /* 0x4A002138 */
- u32 control_paconf_global; /* 0x4A002DA0 */
- u32 control_paconf_mode; /* 0x4A002DA4 */
- u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
- u32 control_smart1io_padconf_1; /* 0x4A002DAC */
- u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
- u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
- u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
- u32 control_smart2io_padconf_2; /* 0x4A002DBC */
- u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
- u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
- u32 pad2[14];
- u32 control_pbias; /* 0x4A002E00 */
- u32 control_i2c_0; /* 0x4A002E04 */
- u32 control_camera_rx; /* 0x4A002E08 */
- u32 control_hdmi_tx_phy; /* 0x4A002E0C */
- u32 control_uniportm; /* 0x4A002E10 */
- u32 control_dsiphy; /* 0x4A002E14 */
- u32 control_mcbsplp; /* 0x4A002E18 */
- u32 control_usb2phycore; /* 0x4A002E1C */
- u32 control_hdmi_1; /*0x4A002E20*/
- u32 control_hsi; /*0x4A002E24*/
- u32 pad3[2];
- u32 control_ddr3ch1_0; /*0x4A002E30*/
- u32 control_ddr3ch2_0; /*0x4A002E34*/
- u32 control_ddrch1_0; /*0x4A002E38*/
- u32 control_ddrch1_1; /*0x4A002E3C*/
- u32 control_ddrch2_0; /*0x4A002E40*/
- u32 control_ddrch2_1; /*0x4A002E44*/
- u32 control_lpddr2ch1_0; /*0x4A002E48*/
- u32 control_lpddr2ch1_1; /*0x4A002E4C*/
- u32 control_ddrio_0; /*0x4A002E50*/
- u32 control_ddrio_1; /*0x4A002E54*/
- u32 control_ddrio_2; /*0x4A002E58*/
- u32 control_hyst_1; /*0x4A002E5C*/
- u32 control_usbb_hsic_control; /*0x4A002E60*/
- u32 control_c2c; /*0x4A002E64*/
- u32 control_core_control_spare_rw; /*0x4A002E68*/
- u32 control_core_control_spare_r; /*0x4A002E6C*/
- u32 control_core_control_spare_r_c0; /*0x4A002E70*/
- u32 control_srcomp_north_side; /*0x4A002E74*/
- u32 control_srcomp_south_side; /*0x4A002E78*/
- u32 control_srcomp_east_side; /*0x4A002E7C*/
- u32 control_srcomp_west_side; /*0x4A002E80*/
- u32 control_srcomp_code_latch; /*0x4A002E84*/
- u32 pad4[3679394];
- u32 control_port_emif1_sdram_config; /*0x4AE0C110*/
- u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/
- u32 control_port_emif2_sdram_config; /*0x4AE0C118*/
- u32 pad5[10];
- u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */
- u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */
- u32 pad6[789];
- u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
- u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
- u32 control_padconf_mode; /* 0x4AE0CDA8 */
- u32 control_xtal_oscillator; /* 0x4AE0CDAC */
- u32 control_i2c_2; /* 0x4AE0CDB0 */
- u32 control_ckobuffer; /* 0x4AE0CDB4 */
- u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
- u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
- u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
- u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
- u32 control_efuse_1; /* 0x4AE0CDC8 */
- u32 control_efuse_2; /* 0x4AE0CDCC */
- u32 control_efuse_3; /* 0x4AE0CDD0 */
- u32 control_efuse_4; /* 0x4AE0CDD4 */
- u32 control_efuse_5; /* 0x4AE0CDD8 */
- u32 control_efuse_6; /* 0x4AE0CDDC */
- u32 control_efuse_7; /* 0x4AE0CDE0 */
- u32 control_efuse_8; /* 0x4AE0CDE4 */
- u32 control_efuse_9; /* 0x4AE0CDE8 */
- u32 control_efuse_10; /* 0x4AE0CDEC */
- u32 control_efuse_11; /* 0x4AE0CDF0 */
- u32 control_efuse_12; /* 0x4AE0CDF4 */
- u32 control_efuse_13; /* 0x4AE0CDF8 */
-};
-
/* Output impedance control */
#define ds_120_ohm 0x0
#define ds_60_ohm 0x1
#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
+#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
+#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
+#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
+#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
+
#define EFUSE_1 0x45145100
#define EFUSE_2 0x45145100
#define EFUSE_3 0x45145100
#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4)
#define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC)
#define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP5_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
+#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x24)
/* Silicon revisions */
#define OMAP4430_SILICON_ID_INVALID 0xFFFFFFFF
#define CH_FLAGS_CHFLASH (0x1 << 2)
#define CH_FLAGS_CHMMCSD (0x1 << 3)
+/* CONTROL_SRCOMP_XXX_SIDE */
+#define OVERRIDE_XS_SHIFT 30
+#define OVERRIDE_XS_MASK (1 << 30)
+#define SRCODE_READ_XS_SHIFT 12
+#define SRCODE_READ_XS_MASK (0xff << 12)
+#define PWRDWN_XS_SHIFT 11
+#define PWRDWN_XS_MASK (1 << 11)
+#define DIVIDE_FACTOR_XS_SHIFT 4
+#define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
+#define MULTIPLY_FACTOR_XS_SHIFT 1
+#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
+#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
+#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
+
#ifndef __ASSEMBLY__
+struct srcomp_params {
+ s8 divide_factor;
+ s8 multiply_factor;
+};
+
struct omap_boot_parameters {
char *boot_message;
unsigned int mem_boot_descriptor;
unsigned char reset_reason;
unsigned char ch_flags;
};
+
+struct ctrl_ioregs {
+ u32 ctrl_ddrch;
+ u32 ctrl_lpddr2ch;
+ u32 ctrl_ddr3ch;
+ u32 ctrl_ddrio_0;
+ u32 ctrl_ddrio_1;
+ u32 ctrl_ddrio_2;
+ u32 ctrl_emif_sdram_config_ext;
+};
#endif /* __ASSEMBLY__ */
#endif
#define BOOT_DEVICE_XIP 1
#define BOOT_DEVICE_XIPWAIT 2
#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONE_NAND 4
+#define BOOT_DEVICE_ONENAND 4
#define BOOT_DEVICE_MMC1 5
#define BOOT_DEVICE_MMC2 6
#define BOOT_DEVICE_MMC2_2 7
#include <asm/io.h>
#include <asm/arch/clocks.h>
#include <asm/omap_common.h>
-#include <asm/arch/mux_omap5.h>
#include <asm/arch/clocks.h>
+struct pad_conf_entry {
+ u32 offset;
+ u32 val;
+};
+
struct omap_sysinfo {
char *board_string;
};
void sdelay(unsigned long);
void setup_clocks_for_console(void);
void prcm_init(void);
-void bypass_dpll(u32 *const base);
+void bypass_dpll(u32 const base);
void freq_update_core(void);
u32 get_sys_clk_freq(void);
u32 omap5_ddr_clk(void);
int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
u32 warm_reset(void);
void force_emif_self_refresh(void);
+void get_ioregs(const struct ctrl_ioregs **regs);
+void srcomp_enable(void);
/*
* This is used to verify if the configuration header
/* Cortex-A15 revisions */
#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
+#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0
#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
+#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7
/* DMM */
#define DMM_BASE 0x4E000040
u32 dmm_lisa_map_1;
u32 dmm_lisa_map_2;
u32 dmm_lisa_map_3;
+ u8 is_ma_present;
};
-extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
-
#define CS0 0
#define CS1 1
/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
#define MR8_IO_WIDTH_SHIFT 0x6
#define MR8_IO_WIDTH_MASK (0x3 << 0x6)
+/* SDRAM TYPE */
+#define EMIF_SDRAM_TYPE_DDR2 0x2
+#define EMIF_SDRAM_TYPE_DDR3 0x3
+#define EMIF_SDRAM_TYPE_LPDDR2 0x4
+
struct lpddr2_addressing {
u8 num_banks;
u8 t_REFI_us_x10;
u32 emif_rd_wr_exec_thresh;
};
+struct lpddr2_mr_regs {
+ s8 mr1;
+ s8 mr2;
+ s8 mr3;
+ s8 mr10;
+ s8 mr16;
+};
+
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })
#endif
void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
+void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs);
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
extern u32 *const T_num;
#endif
void config_data_eye_leveling_samples(u32 emif_base);
+u32 emif_sdram_type(void);
#endif
#ifndef _OMAP_COMMON_H_
#define _OMAP_COMMON_H_
+#include <common.h>
+
+#define NUM_SYS_CLKS 8
+
+struct prcm_regs {
+ /* cm1.ckgen */
+ u32 cm_clksel_core;
+ u32 cm_clksel_abe;
+ u32 cm_dll_ctrl;
+ u32 cm_clkmode_dpll_core;
+ u32 cm_idlest_dpll_core;
+ u32 cm_autoidle_dpll_core;
+ u32 cm_clksel_dpll_core;
+ u32 cm_div_m2_dpll_core;
+ u32 cm_div_m3_dpll_core;
+ u32 cm_div_h11_dpll_core;
+ u32 cm_div_h12_dpll_core;
+ u32 cm_div_h13_dpll_core;
+ u32 cm_div_h14_dpll_core;
+ u32 cm_div_h21_dpll_core;
+ u32 cm_div_h24_dpll_core;
+ u32 cm_ssc_deltamstep_dpll_core;
+ u32 cm_ssc_modfreqdiv_dpll_core;
+ u32 cm_emu_override_dpll_core;
+ u32 cm_div_h22_dpllcore;
+ u32 cm_div_h23_dpll_core;
+ u32 cm_clkmode_dpll_mpu;
+ u32 cm_idlest_dpll_mpu;
+ u32 cm_autoidle_dpll_mpu;
+ u32 cm_clksel_dpll_mpu;
+ u32 cm_div_m2_dpll_mpu;
+ u32 cm_ssc_deltamstep_dpll_mpu;
+ u32 cm_ssc_modfreqdiv_dpll_mpu;
+ u32 cm_bypclk_dpll_mpu;
+ u32 cm_clkmode_dpll_iva;
+ u32 cm_idlest_dpll_iva;
+ u32 cm_autoidle_dpll_iva;
+ u32 cm_clksel_dpll_iva;
+ u32 cm_div_h11_dpll_iva;
+ u32 cm_div_h12_dpll_iva;
+ u32 cm_ssc_deltamstep_dpll_iva;
+ u32 cm_ssc_modfreqdiv_dpll_iva;
+ u32 cm_bypclk_dpll_iva;
+ u32 cm_clkmode_dpll_abe;
+ u32 cm_idlest_dpll_abe;
+ u32 cm_autoidle_dpll_abe;
+ u32 cm_clksel_dpll_abe;
+ u32 cm_div_m2_dpll_abe;
+ u32 cm_div_m3_dpll_abe;
+ u32 cm_ssc_deltamstep_dpll_abe;
+ u32 cm_ssc_modfreqdiv_dpll_abe;
+ u32 cm_clkmode_dpll_ddrphy;
+ u32 cm_idlest_dpll_ddrphy;
+ u32 cm_autoidle_dpll_ddrphy;
+ u32 cm_clksel_dpll_ddrphy;
+ u32 cm_div_m2_dpll_ddrphy;
+ u32 cm_div_h11_dpll_ddrphy;
+ u32 cm_div_h12_dpll_ddrphy;
+ u32 cm_div_h13_dpll_ddrphy;
+ u32 cm_ssc_deltamstep_dpll_ddrphy;
+ u32 cm_clkmode_dpll_dsp;
+ u32 cm_shadow_freq_config1;
+ u32 cm_mpu_mpu_clkctrl;
+
+ /* cm1.dsp */
+ u32 cm_dsp_clkstctrl;
+ u32 cm_dsp_dsp_clkctrl;
+
+ /* cm1.abe */
+ u32 cm1_abe_clkstctrl;
+ u32 cm1_abe_l4abe_clkctrl;
+ u32 cm1_abe_aess_clkctrl;
+ u32 cm1_abe_pdm_clkctrl;
+ u32 cm1_abe_dmic_clkctrl;
+ u32 cm1_abe_mcasp_clkctrl;
+ u32 cm1_abe_mcbsp1_clkctrl;
+ u32 cm1_abe_mcbsp2_clkctrl;
+ u32 cm1_abe_mcbsp3_clkctrl;
+ u32 cm1_abe_slimbus_clkctrl;
+ u32 cm1_abe_timer5_clkctrl;
+ u32 cm1_abe_timer6_clkctrl;
+ u32 cm1_abe_timer7_clkctrl;
+ u32 cm1_abe_timer8_clkctrl;
+ u32 cm1_abe_wdt3_clkctrl;
+
+ /* cm2.ckgen */
+ u32 cm_clksel_mpu_m3_iss_root;
+ u32 cm_clksel_usb_60mhz;
+ u32 cm_scale_fclk;
+ u32 cm_core_dvfs_perf1;
+ u32 cm_core_dvfs_perf2;
+ u32 cm_core_dvfs_perf3;
+ u32 cm_core_dvfs_perf4;
+ u32 cm_core_dvfs_current;
+ u32 cm_iva_dvfs_perf_tesla;
+ u32 cm_iva_dvfs_perf_ivahd;
+ u32 cm_iva_dvfs_perf_abe;
+ u32 cm_iva_dvfs_current;
+ u32 cm_clkmode_dpll_per;
+ u32 cm_idlest_dpll_per;
+ u32 cm_autoidle_dpll_per;
+ u32 cm_clksel_dpll_per;
+ u32 cm_div_m2_dpll_per;
+ u32 cm_div_m3_dpll_per;
+ u32 cm_div_h11_dpll_per;
+ u32 cm_div_h12_dpll_per;
+ u32 cm_div_h13_dpll_per;
+ u32 cm_div_h14_dpll_per;
+ u32 cm_ssc_deltamstep_dpll_per;
+ u32 cm_ssc_modfreqdiv_dpll_per;
+ u32 cm_emu_override_dpll_per;
+ u32 cm_clkmode_dpll_usb;
+ u32 cm_idlest_dpll_usb;
+ u32 cm_autoidle_dpll_usb;
+ u32 cm_clksel_dpll_usb;
+ u32 cm_div_m2_dpll_usb;
+ u32 cm_ssc_deltamstep_dpll_usb;
+ u32 cm_ssc_modfreqdiv_dpll_usb;
+ u32 cm_clkdcoldo_dpll_usb;
+ u32 cm_clkmode_dpll_pcie_ref;
+ u32 cm_clkmode_apll_pcie;
+ u32 cm_idlest_apll_pcie;
+ u32 cm_div_m2_apll_pcie;
+ u32 cm_clkvcoldo_apll_pcie;
+ u32 cm_clkmode_dpll_unipro;
+ u32 cm_idlest_dpll_unipro;
+ u32 cm_autoidle_dpll_unipro;
+ u32 cm_clksel_dpll_unipro;
+ u32 cm_div_m2_dpll_unipro;
+ u32 cm_ssc_deltamstep_dpll_unipro;
+ u32 cm_ssc_modfreqdiv_dpll_unipro;
+
+ /* cm2.core */
+ u32 cm_coreaon_bandgap_clkctrl;
+ u32 cm_coreaon_io_srcomp_clkctrl;
+ u32 cm_l3_1_clkstctrl;
+ u32 cm_l3_1_dynamicdep;
+ u32 cm_l3_1_l3_1_clkctrl;
+ u32 cm_l3_2_clkstctrl;
+ u32 cm_l3_2_dynamicdep;
+ u32 cm_l3_2_l3_2_clkctrl;
+ u32 cm_l3_gpmc_clkctrl;
+ u32 cm_l3_2_ocmc_ram_clkctrl;
+ u32 cm_mpu_m3_clkstctrl;
+ u32 cm_mpu_m3_staticdep;
+ u32 cm_mpu_m3_dynamicdep;
+ u32 cm_mpu_m3_mpu_m3_clkctrl;
+ u32 cm_sdma_clkstctrl;
+ u32 cm_sdma_staticdep;
+ u32 cm_sdma_dynamicdep;
+ u32 cm_sdma_sdma_clkctrl;
+ u32 cm_memif_clkstctrl;
+ u32 cm_memif_dmm_clkctrl;
+ u32 cm_memif_emif_fw_clkctrl;
+ u32 cm_memif_emif_1_clkctrl;
+ u32 cm_memif_emif_2_clkctrl;
+ u32 cm_memif_dll_clkctrl;
+ u32 cm_memif_emif_h1_clkctrl;
+ u32 cm_memif_emif_h2_clkctrl;
+ u32 cm_memif_dll_h_clkctrl;
+ u32 cm_c2c_clkstctrl;
+ u32 cm_c2c_staticdep;
+ u32 cm_c2c_dynamicdep;
+ u32 cm_c2c_sad2d_clkctrl;
+ u32 cm_c2c_modem_icr_clkctrl;
+ u32 cm_c2c_sad2d_fw_clkctrl;
+ u32 cm_l4cfg_clkstctrl;
+ u32 cm_l4cfg_dynamicdep;
+ u32 cm_l4cfg_l4_cfg_clkctrl;
+ u32 cm_l4cfg_hw_sem_clkctrl;
+ u32 cm_l4cfg_mailbox_clkctrl;
+ u32 cm_l4cfg_sar_rom_clkctrl;
+ u32 cm_l3instr_clkstctrl;
+ u32 cm_l3instr_l3_3_clkctrl;
+ u32 cm_l3instr_l3_instr_clkctrl;
+ u32 cm_l3instr_intrconn_wp1_clkctrl;
+
+ /* cm2.ivahd */
+ u32 cm_ivahd_clkstctrl;
+ u32 cm_ivahd_ivahd_clkctrl;
+ u32 cm_ivahd_sl2_clkctrl;
+
+ /* cm2.cam */
+ u32 cm_cam_clkstctrl;
+ u32 cm_cam_iss_clkctrl;
+ u32 cm_cam_fdif_clkctrl;
+ u32 cm_cam_vip1_clkctrl;
+ u32 cm_cam_vip2_clkctrl;
+ u32 cm_cam_vip3_clkctrl;
+ u32 cm_cam_lvdsrx_clkctrl;
+ u32 cm_cam_csi1_clkctrl;
+ u32 cm_cam_csi2_clkctrl;
+
+ /* cm2.dss */
+ u32 cm_dss_clkstctrl;
+ u32 cm_dss_dss_clkctrl;
+
+ /* cm2.sgx */
+ u32 cm_sgx_clkstctrl;
+ u32 cm_sgx_sgx_clkctrl;
+
+ /* cm2.l3init */
+ u32 cm_l3init_clkstctrl;
+
+ /* cm2.l3init */
+ u32 cm_l3init_hsmmc1_clkctrl;
+ u32 cm_l3init_hsmmc2_clkctrl;
+ u32 cm_l3init_hsi_clkctrl;
+ u32 cm_l3init_hsusbhost_clkctrl;
+ u32 cm_l3init_hsusbotg_clkctrl;
+ u32 cm_l3init_hsusbtll_clkctrl;
+ u32 cm_l3init_p1500_clkctrl;
+ u32 cm_l3init_fsusb_clkctrl;
+ u32 cm_l3init_ocp2scp1_clkctrl;
+
+ /* cm2.l4per */
+ u32 cm_l4per_clkstctrl;
+ u32 cm_l4per_dynamicdep;
+ u32 cm_l4per_adc_clkctrl;
+ u32 cm_l4per_gptimer10_clkctrl;
+ u32 cm_l4per_gptimer11_clkctrl;
+ u32 cm_l4per_gptimer2_clkctrl;
+ u32 cm_l4per_gptimer3_clkctrl;
+ u32 cm_l4per_gptimer4_clkctrl;
+ u32 cm_l4per_gptimer9_clkctrl;
+ u32 cm_l4per_elm_clkctrl;
+ u32 cm_l4per_gpio2_clkctrl;
+ u32 cm_l4per_gpio3_clkctrl;
+ u32 cm_l4per_gpio4_clkctrl;
+ u32 cm_l4per_gpio5_clkctrl;
+ u32 cm_l4per_gpio6_clkctrl;
+ u32 cm_l4per_hdq1w_clkctrl;
+ u32 cm_l4per_hecc1_clkctrl;
+ u32 cm_l4per_hecc2_clkctrl;
+ u32 cm_l4per_i2c1_clkctrl;
+ u32 cm_l4per_i2c2_clkctrl;
+ u32 cm_l4per_i2c3_clkctrl;
+ u32 cm_l4per_i2c4_clkctrl;
+ u32 cm_l4per_l4per_clkctrl;
+ u32 cm_l4per_mcasp2_clkctrl;
+ u32 cm_l4per_mcasp3_clkctrl;
+ u32 cm_l4per_mgate_clkctrl;
+ u32 cm_l4per_mcspi1_clkctrl;
+ u32 cm_l4per_mcspi2_clkctrl;
+ u32 cm_l4per_mcspi3_clkctrl;
+ u32 cm_l4per_mcspi4_clkctrl;
+ u32 cm_l4per_gpio7_clkctrl;
+ u32 cm_l4per_gpio8_clkctrl;
+ u32 cm_l4per_mmcsd3_clkctrl;
+ u32 cm_l4per_mmcsd4_clkctrl;
+ u32 cm_l4per_msprohg_clkctrl;
+ u32 cm_l4per_slimbus2_clkctrl;
+ u32 cm_l4per_uart1_clkctrl;
+ u32 cm_l4per_uart2_clkctrl;
+ u32 cm_l4per_uart3_clkctrl;
+ u32 cm_l4per_uart4_clkctrl;
+ u32 cm_l4per_mmcsd5_clkctrl;
+ u32 cm_l4per_i2c5_clkctrl;
+ u32 cm_l4per_uart5_clkctrl;
+ u32 cm_l4per_uart6_clkctrl;
+ u32 cm_l4sec_clkstctrl;
+ u32 cm_l4sec_staticdep;
+ u32 cm_l4sec_dynamicdep;
+ u32 cm_l4sec_aes1_clkctrl;
+ u32 cm_l4sec_aes2_clkctrl;
+ u32 cm_l4sec_des3des_clkctrl;
+ u32 cm_l4sec_pkaeip29_clkctrl;
+ u32 cm_l4sec_rng_clkctrl;
+ u32 cm_l4sec_sha2md51_clkctrl;
+ u32 cm_l4sec_cryptodma_clkctrl;
+
+ /* l4 wkup regs */
+ u32 cm_abe_pll_ref_clksel;
+ u32 cm_sys_clksel;
+ u32 cm_wkup_clkstctrl;
+ u32 cm_wkup_l4wkup_clkctrl;
+ u32 cm_wkup_wdtimer1_clkctrl;
+ u32 cm_wkup_wdtimer2_clkctrl;
+ u32 cm_wkup_gpio1_clkctrl;
+ u32 cm_wkup_gptimer1_clkctrl;
+ u32 cm_wkup_gptimer12_clkctrl;
+ u32 cm_wkup_synctimer_clkctrl;
+ u32 cm_wkup_usim_clkctrl;
+ u32 cm_wkup_sarram_clkctrl;
+ u32 cm_wkup_keyboard_clkctrl;
+ u32 cm_wkup_rtc_clkctrl;
+ u32 cm_wkup_bandgap_clkctrl;
+ u32 cm_wkupaon_scrm_clkctrl;
+ u32 cm_wkupaon_io_srcomp_clkctrl;
+ u32 prm_rstctrl;
+ u32 prm_rstst;
+ u32 prm_vc_val_bypass;
+ u32 prm_vc_cfg_i2c_mode;
+ u32 prm_vc_cfg_i2c_clk;
+ u32 prm_sldo_core_setup;
+ u32 prm_sldo_core_ctrl;
+ u32 prm_sldo_mpu_setup;
+ u32 prm_sldo_mpu_ctrl;
+ u32 prm_sldo_mm_setup;
+ u32 prm_sldo_mm_ctrl;
+
+ u32 cm_div_m4_dpll_core;
+ u32 cm_div_m5_dpll_core;
+ u32 cm_div_m6_dpll_core;
+ u32 cm_div_m7_dpll_core;
+ u32 cm_div_m4_dpll_iva;
+ u32 cm_div_m5_dpll_iva;
+ u32 cm_div_m4_dpll_ddrphy;
+ u32 cm_div_m5_dpll_ddrphy;
+ u32 cm_div_m6_dpll_ddrphy;
+ u32 cm_div_m4_dpll_per;
+ u32 cm_div_m5_dpll_per;
+ u32 cm_div_m6_dpll_per;
+ u32 cm_div_m7_dpll_per;
+ u32 cm_l3instr_intrconn_wp1_clkct;
+ u32 cm_l3init_usbphy_clkctrl;
+ u32 cm_l4per_mcbsp4_clkctrl;
+ u32 prm_vc_cfg_channel;
+};
+
+struct omap_sys_ctrl_regs {
+ u32 control_status;
+ u32 control_core_mmr_lock1;
+ u32 control_core_mmr_lock2;
+ u32 control_core_mmr_lock3;
+ u32 control_core_mmr_lock4;
+ u32 control_core_mmr_lock5;
+ u32 control_core_control_io1;
+ u32 control_core_control_io2;
+ u32 control_id_code;
+ u32 control_std_fuse_opp_bgap;
+ u32 control_ldosram_iva_voltage_ctrl;
+ u32 control_ldosram_mpu_voltage_ctrl;
+ u32 control_ldosram_core_voltage_ctrl;
+ u32 control_padconf_core_base;
+ u32 control_paconf_global;
+ u32 control_paconf_mode;
+ u32 control_smart1io_padconf_0;
+ u32 control_smart1io_padconf_1;
+ u32 control_smart1io_padconf_2;
+ u32 control_smart2io_padconf_0;
+ u32 control_smart2io_padconf_1;
+ u32 control_smart2io_padconf_2;
+ u32 control_smart3io_padconf_0;
+ u32 control_smart3io_padconf_1;
+ u32 control_pbias;
+ u32 control_i2c_0;
+ u32 control_camera_rx;
+ u32 control_hdmi_tx_phy;
+ u32 control_uniportm;
+ u32 control_dsiphy;
+ u32 control_mcbsplp;
+ u32 control_usb2phycore;
+ u32 control_hdmi_1;
+ u32 control_hsi;
+ u32 control_ddr3ch1_0;
+ u32 control_ddr3ch2_0;
+ u32 control_ddrch1_0;
+ u32 control_ddrch1_1;
+ u32 control_ddrch2_0;
+ u32 control_ddrch2_1;
+ u32 control_lpddr2ch1_0;
+ u32 control_lpddr2ch1_1;
+ u32 control_ddrio_0;
+ u32 control_ddrio_1;
+ u32 control_ddrio_2;
+ u32 control_lpddr2io1_0;
+ u32 control_lpddr2io1_1;
+ u32 control_lpddr2io1_2;
+ u32 control_lpddr2io1_3;
+ u32 control_lpddr2io2_0;
+ u32 control_lpddr2io2_1;
+ u32 control_lpddr2io2_2;
+ u32 control_lpddr2io2_3;
+ u32 control_hyst_1;
+ u32 control_usbb_hsic_control;
+ u32 control_c2c;
+ u32 control_core_control_spare_rw;
+ u32 control_core_control_spare_r;
+ u32 control_core_control_spare_r_c0;
+ u32 control_srcomp_north_side;
+ u32 control_srcomp_south_side;
+ u32 control_srcomp_east_side;
+ u32 control_srcomp_west_side;
+ u32 control_srcomp_code_latch;
+ u32 control_pbiaslite;
+ u32 control_port_emif1_sdram_config;
+ u32 control_port_emif1_lpddr2_nvm_config;
+ u32 control_port_emif2_sdram_config;
+ u32 control_emif1_sdram_config_ext;
+ u32 control_emif2_sdram_config_ext;
+ u32 control_smart1nopmio_padconf_0;
+ u32 control_smart1nopmio_padconf_1;
+ u32 control_padconf_mode;
+ u32 control_xtal_oscillator;
+ u32 control_i2c_2;
+ u32 control_ckobuffer;
+ u32 control_wkup_control_spare_rw;
+ u32 control_wkup_control_spare_r;
+ u32 control_wkup_control_spare_r_c0;
+ u32 control_srcomp_east_side_wkup;
+ u32 control_efuse_1;
+ u32 control_efuse_2;
+ u32 control_efuse_3;
+ u32 control_efuse_4;
+ u32 control_efuse_5;
+ u32 control_efuse_6;
+ u32 control_efuse_7;
+ u32 control_efuse_8;
+ u32 control_efuse_9;
+ u32 control_efuse_10;
+ u32 control_efuse_11;
+ u32 control_efuse_12;
+ u32 control_efuse_13;
+ u32 control_padconf_wkup_base;
+};
+
+struct dpll_params {
+ u32 m;
+ u32 n;
+ s8 m2;
+ s8 m3;
+ s8 m4_h11;
+ s8 m5_h12;
+ s8 m6_h13;
+ s8 m7_h14;
+ s8 h21;
+ s8 h22;
+ s8 h23;
+ s8 h24;
+};
+
+struct dpll_regs {
+ u32 cm_clkmode_dpll;
+ u32 cm_idlest_dpll;
+ u32 cm_autoidle_dpll;
+ u32 cm_clksel_dpll;
+ u32 cm_div_m2_dpll;
+ u32 cm_div_m3_dpll;
+ u32 cm_div_m4_h11_dpll;
+ u32 cm_div_m5_h12_dpll;
+ u32 cm_div_m6_h13_dpll;
+ u32 cm_div_m7_h14_dpll;
+ u32 reserved[2];
+ u32 cm_div_h21_dpll;
+ u32 cm_div_h22_dpll;
+ u32 cm_div_h23_dpll;
+ u32 cm_div_h24_dpll;
+};
+
+struct dplls {
+ const struct dpll_params *mpu;
+ const struct dpll_params *core;
+ const struct dpll_params *per;
+ const struct dpll_params *abe;
+ const struct dpll_params *iva;
+ const struct dpll_params *usb;
+ const struct dpll_params *ddr;
+};
+
+struct pmic_data {
+ u32 base_offset;
+ u32 step;
+ u32 start_code;
+ unsigned gpio;
+ int gpio_en;
+};
+
+struct volts {
+ u32 value;
+ u32 addr;
+ struct pmic_data *pmic;
+};
+
+struct vcores_data {
+ struct volts mpu;
+ struct volts core;
+ struct volts mm;
+};
+
+extern struct prcm_regs const **prcm;
+extern struct prcm_regs const omap5_es1_prcm;
+extern struct prcm_regs const omap5_es2_prcm;
+extern struct prcm_regs const omap4_prcm;
+extern struct prcm_regs const dra7xx_prcm;
+extern struct dplls const **dplls_data;
+extern struct vcores_data const **omap_vcores;
+extern const u32 sys_clk_array[8];
+extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const omap4_ctrl;
+extern struct omap_sys_ctrl_regs const omap5_ctrl;
+extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
+
+void hw_data_init(void);
+
+const struct dpll_params *get_mpu_dpll_params(struct dplls const *);
+const struct dpll_params *get_core_dpll_params(struct dplls const *);
+const struct dpll_params *get_per_dpll_params(struct dplls const *);
+const struct dpll_params *get_iva_dpll_params(struct dplls const *);
+const struct dpll_params *get_usb_dpll_params(struct dplls const *);
+const struct dpll_params *get_abe_dpll_params(struct dplls const *);
+
+void do_enable_clocks(u32 const *clk_domains,
+ u32 const *clk_modules_hw_auto,
+ u32 const *clk_modules_explicit_en,
+ u8 wait_for_enable);
+
+void setup_post_dividers(u32 const base,
+ const struct dpll_params *params);
+u32 omap_ddr_clk(void);
+u32 get_sys_clk_index(void);
+void enable_basic_clocks(void);
+void enable_basic_uboot_clocks(void);
+void enable_non_essential_clocks(void);
+void scale_vcores(struct vcores_data const *);
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
+
/* Max value for DPLL multiplier M */
#define OMAP_DPLL_MAX_N 127
#define OMAP5430_SILICON_ID_INVALID 0
#define OMAP5430_ES1_0 0x54300100
#define OMAP5432_ES1_0 0x54320100
+#define OMAP5430_ES2_0 0x54300200
+#define OMAP5432_ES2_0 0x54320200
+
+/* DRA7XX */
+#define DRA752_ES1_0 0x07520100
#endif /* _OMAP_COMMON_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef OMAP_MMC_H_
+#define OMAP_MMC_H_
+
+struct hsmmc {
+ unsigned char res1[0x10];
+ unsigned int sysconfig; /* 0x10 */
+ unsigned int sysstatus; /* 0x14 */
+ unsigned char res2[0x14];
+ unsigned int con; /* 0x2C */
+ unsigned char res3[0xD4];
+ unsigned int blk; /* 0x104 */
+ unsigned int arg; /* 0x108 */
+ unsigned int cmd; /* 0x10C */
+ unsigned int rsp10; /* 0x110 */
+ unsigned int rsp32; /* 0x114 */
+ unsigned int rsp54; /* 0x118 */
+ unsigned int rsp76; /* 0x11C */
+ unsigned int data; /* 0x120 */
+ unsigned int pstate; /* 0x124 */
+ unsigned int hctl; /* 0x128 */
+ unsigned int sysctl; /* 0x12C */
+ unsigned int stat; /* 0x130 */
+ unsigned int ie; /* 0x134 */
+ unsigned char res4[0x8];
+ unsigned int capa; /* 0x140 */
+};
+
+/*
+ * OMAP HS MMC Bit definitions
+ */
+#define MMC_SOFTRESET (0x1 << 1)
+#define RESETDONE (0x1 << 0)
+#define NOOPENDRAIN (0x0 << 0)
+#define OPENDRAIN (0x1 << 0)
+#define OD (0x1 << 0)
+#define INIT_NOINIT (0x0 << 1)
+#define INIT_INITSTREAM (0x1 << 1)
+#define HR_NOHOSTRESP (0x0 << 2)
+#define STR_BLOCK (0x0 << 3)
+#define MODE_FUNC (0x0 << 4)
+#define DW8_1_4BITMODE (0x0 << 5)
+#define MIT_CTO (0x0 << 6)
+#define CDP_ACTIVEHIGH (0x0 << 7)
+#define WPP_ACTIVEHIGH (0x0 << 8)
+#define RESERVED_MASK (0x3 << 9)
+#define CTPL_MMC_SD (0x0 << 11)
+#define BLEN_512BYTESLEN (0x200 << 0)
+#define NBLK_STPCNT (0x0 << 16)
+#define DE_DISABLE (0x0 << 0)
+#define BCE_DISABLE (0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
+#define ACEN_DISABLE (0x0 << 2)
+#define DDIR_OFFSET (4)
+#define DDIR_MASK (0x1 << 4)
+#define DDIR_WRITE (0x0 << 4)
+#define DDIR_READ (0x1 << 4)
+#define MSBS_SGLEBLK (0x0 << 5)
+#define MSBS_MULTIBLK (0x1 << 5)
+#define RSP_TYPE_OFFSET (16)
+#define RSP_TYPE_MASK (0x3 << 16)
+#define RSP_TYPE_NORSP (0x0 << 16)
+#define RSP_TYPE_LGHT136 (0x1 << 16)
+#define RSP_TYPE_LGHT48 (0x2 << 16)
+#define RSP_TYPE_LGHT48B (0x3 << 16)
+#define CCCE_NOCHECK (0x0 << 19)
+#define CCCE_CHECK (0x1 << 19)
+#define CICE_NOCHECK (0x0 << 20)
+#define CICE_CHECK (0x1 << 20)
+#define DP_OFFSET (21)
+#define DP_MASK (0x1 << 21)
+#define DP_NO_DATA (0x0 << 21)
+#define DP_DATA (0x1 << 21)
+#define CMD_TYPE_NORMAL (0x0 << 22)
+#define INDEX_OFFSET (24)
+#define INDEX_MASK (0x3f << 24)
+#define INDEX(i) (i << 24)
+#define DATI_MASK (0x1 << 1)
+#define CMDI_MASK (0x1 << 0)
+#define DTW_1_BITMODE (0x0 << 1)
+#define DTW_4_BITMODE (0x1 << 1)
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
+#define SDBP_PWROFF (0x0 << 8)
+#define SDBP_PWRON (0x1 << 8)
+#define SDVS_1V8 (0x5 << 9)
+#define SDVS_3V0 (0x6 << 9)
+#define ICE_MASK (0x1 << 0)
+#define ICE_STOP (0x0 << 0)
+#define ICS_MASK (0x1 << 1)
+#define ICS_NOTREADY (0x0 << 1)
+#define ICE_OSCILLATE (0x1 << 0)
+#define CEN_MASK (0x1 << 2)
+#define CEN_DISABLE (0x0 << 2)
+#define CEN_ENABLE (0x1 << 2)
+#define CLKD_OFFSET (6)
+#define CLKD_MASK (0x3FF << 6)
+#define DTO_MASK (0xF << 16)
+#define DTO_15THDTO (0xE << 16)
+#define SOFTRESETALL (0x1 << 24)
+#define CC_MASK (0x1 << 0)
+#define TC_MASK (0x1 << 1)
+#define BWR_MASK (0x1 << 4)
+#define BRR_MASK (0x1 << 5)
+#define ERRI_MASK (0x1 << 15)
+#define IE_CC (0x01 << 0)
+#define IE_TC (0x01 << 1)
+#define IE_BWR (0x01 << 4)
+#define IE_BRR (0x01 << 5)
+#define IE_CTO (0x01 << 16)
+#define IE_CCRC (0x01 << 17)
+#define IE_CEB (0x01 << 18)
+#define IE_CIE (0x01 << 19)
+#define IE_DTO (0x01 << 20)
+#define IE_DCRC (0x01 << 21)
+#define IE_DEB (0x01 << 22)
+#define IE_CERR (0x01 << 28)
+#define IE_BADA (0x01 << 29)
+
+#define VS30_3V0SUP (1 << 25)
+#define VS18_1V8SUP (1 << 26)
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE 512
+#define MMC_CARD 0
+#define SD_CARD 1
+#define BYTE_MODE 0
+#define SECTOR_MODE 1
+#define CLK_INITSEQ 0
+#define CLK_400KHZ 1
+#define CLK_MISC 2
+
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE 96 /* MHz */
+
+#define mmc_reg_out(addr, mask, val)\
+ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
+ int wp_gpio);
+
+
+#endif /* OMAP_MMC_H_ */
SOBJS-y += crt0.o
ifndef CONFIG_SPL_BUILD
+COBJS-y += bss.o
COBJS-y += board.o
COBJS-y += bootm.o
COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
--- /dev/null
+/*
+ * Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/**
+ * These two symbols are declared in a C file so that the linker
+ * uses R_ARM_RELATIVE relocation, rather than the R_ARM_ABS32 one
+ * it would use if the symbols were defined in the linker file.
+ * Using only R_ARM_RELATIVE relocation ensures that references to
+ * the symbols are correct after as well as before relocation.
+ *
+ * We need a 0-byte-size type for these symbols, and the compiler
+ * does not allow defining objects of C type 'void'. Using an empty
+ * struct is allowed by the compiler, but causes gcc versions 4.4 and
+ * below to complain about aliasing. Therefore we use the next best
+ * thing: zero-sized arrays, which are both 0-byte-size and exempt from
+ * aliasing warnings.
+ */
+
+char __bss_start[0] __attribute__((used, section(".__bss_start")));
+char __bss_end__[0] __attribute__((used, section(".__bss_end__")));
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
/* The malloc area is right below the monitor image in RAM */
mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
- malloc_bin_reloc();
dma_alloc_init();
enable_interrupts();
/* Reset upon a double exception rather than just hanging.
* Do not do bfin_read on SWRST as that will reset status bits.
*/
+# ifdef SWRST
bfin_write_SWRST(DOUBLE_FAULT);
+# endif
#endif
serial_early_puts("Board init flash\n");
#elif defined(SICA_IMASK0)
bfin_write_SICA_IMASK0(0);
bfin_write_SICA_IMASK1(0);
-#else
+#elif defined(SIC_IMASK)
bfin_write_SIC_IMASK(0);
#endif
/* Set up a dummy NMI handler if needed. */
(struct gpio_port_t *)PORTH_FER,
(struct gpio_port_t *)PORTI_FER,
(struct gpio_port_t *)PORTJ_FER,
+#elif defined(CONFIG_BF60x)
+ (struct gpio_port_t *)PORTA_FER,
+ (struct gpio_port_t *)PORTB_FER,
+ (struct gpio_port_t *)PORTC_FER,
+ (struct gpio_port_t *)PORTD_FER,
+ (struct gpio_port_t *)PORTE_FER,
+ (struct gpio_port_t *)PORTF_FER,
+ (struct gpio_port_t *)PORTG_FER,
#else
# error no gpio arrays defined
#endif
else
gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
SSYNC();
+#elif defined(CONFIG_BF60x)
+ if (usage == GPIO_USAGE)
+ gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio);
+ else
+ gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio);
+ SSYNC();
#endif
}
}
}
}
-#elif defined(CONFIG_BF54x)
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
inline void portmux_setup(unsigned short per)
{
u32 pmux;
# define portmux_setup(...) do { } while (0)
#endif
-#ifndef CONFIG_BF54x
+#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
/***********************************************************
*
* FUNCTIONS: Blackfin General Purpose Ports Access Functions
* be requested and used by several drivers
*/
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
if (!((per & P_MAYSHARE) && get_portmux(per) == P_FUNCT2MUX(per))) {
#else
if (!(per & P_MAYSHARE)) {
gpio, get_label(gpio));
return -EBUSY;
}
-#ifndef CONFIG_BF54x
+#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
else { /* Reset POLAR setting when acquiring a gpio for the first time */
set_gpio_polar(gpio, 0);
}
static inline void __bfin_gpio_direction_input(unsigned gpio)
{
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
#endif
+#if defined(CONFIG_BF60x)
+ gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio);
+#else
gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
+#endif
}
int bfin_gpio_direction_input(unsigned gpio)
local_irq_save(flags);
+#if defined(CONFIG_BF60x)
+ gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio);
+#else
gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
+#endif
gpio_set_value(gpio, value);
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio);
#else
gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
int bfin_gpio_get_value(unsigned gpio)
{
-#ifdef CONFIG_BF54x
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF60x)
return (1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)));
#else
unsigned long flags;
#include <asm/blackfin.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/mach-common/bits/uart.h>
#define BUG() while (1) { asm volatile("emuexcpt;"); }
#include "serial.h"
+#ifndef __ADSPBF60x__
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#else /* __ADSPBF60x__ */
+#include <asm/mach-common/bits/cgu.h>
+
+#define CONFIG_BFIN_GET_DCLK_M \
+ ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
+
+#ifndef CONFIG_DMC_DDRCFG
+#if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
+ (CONFIG_BFIN_GET_DCLK_M != 133) && \
+ (CONFIG_BFIN_GET_DCLK_M != 150) && \
+ (CONFIG_BFIN_GET_DCLK_M != 166) && \
+ (CONFIG_BFIN_GET_DCLK_M != 200) && \
+ (CONFIG_BFIN_GET_DCLK_M != 225) && \
+ (CONFIG_BFIN_GET_DCLK_M != 250))
+#error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
+#endif
+#endif
+
+/* DMC control bits */
+#define SRREQ 0x8
+
+/* DMC status bits */
+#define IDLE 0x1
+#define MEMINITDONE 0x4
+#define SRACK 0x8
+#define PDACK 0x10
+#define DPDACK 0x20
+#define DLLCALDONE 0x2000
+#define PENDREF 0xF0000
+#define PHYRDPHASE 0xF00000
+#define PHYRDPHASE_OFFSET 20
+
+/* DMC DLL control bits */
+#define DLLCALRDCNT 0xFF
+#define DATACYC_OFFSET 8
+
+struct ddr_config {
+ u32 ddr_clk;
+ u32 dmc_ddrctl;
+ u32 dmc_ddrcfg;
+ u32 dmc_ddrtr0;
+ u32 dmc_ddrtr1;
+ u32 dmc_ddrtr2;
+ u32 dmc_ddrmr;
+ u32 dmc_ddrmr1;
+};
+
+static struct ddr_config ddr_config_table[] = {
+ [0] = {
+ .ddr_clk = 125, /* 125MHz */
+ .dmc_ddrctl = 0x00000904,
+ .dmc_ddrcfg = 0x00000422,
+ .dmc_ddrtr0 = 0x20705212,
+ .dmc_ddrtr1 = 0x201003CF,
+ .dmc_ddrtr2 = 0x00320107,
+ .dmc_ddrmr = 0x00000422,
+ .dmc_ddrmr1 = 0x4,
+ },
+ [1] = {
+ .ddr_clk = 133, /* 133MHz */
+ .dmc_ddrctl = 0x00000904,
+ .dmc_ddrcfg = 0x00000422,
+ .dmc_ddrtr0 = 0x20806313,
+ .dmc_ddrtr1 = 0x2013040D,
+ .dmc_ddrtr2 = 0x00320108,
+ .dmc_ddrmr = 0x00000632,
+ .dmc_ddrmr1 = 0x4,
+ },
+ [2] = {
+ .ddr_clk = 150, /* 150MHz */
+ .dmc_ddrctl = 0x00000904,
+ .dmc_ddrcfg = 0x00000422,
+ .dmc_ddrtr0 = 0x20A07323,
+ .dmc_ddrtr1 = 0x20160492,
+ .dmc_ddrtr2 = 0x00320209,
+ .dmc_ddrmr = 0x00000632,
+ .dmc_ddrmr1 = 0x4,
+ },
+ [3] = {
+ .ddr_clk = 166, /* 166MHz */
+ .dmc_ddrctl = 0x00000904,
+ .dmc_ddrcfg = 0x00000422,
+ .dmc_ddrtr0 = 0x20A07323,
+ .dmc_ddrtr1 = 0x2016050E,
+ .dmc_ddrtr2 = 0x00320209,
+ .dmc_ddrmr = 0x00000632,
+ .dmc_ddrmr1 = 0x4,
+ },
+ [4] = {
+ .ddr_clk = 200, /* 200MHz */
+ .dmc_ddrctl = 0x00000904,
+ .dmc_ddrcfg = 0x00000422,
+ .dmc_ddrtr0 = 0x20a07323,
+ .dmc_ddrtr1 = 0x2016050f,
+ .dmc_ddrtr2 = 0x00320509,
+ .dmc_ddrmr = 0x00000632,
+ .dmc_ddrmr1 = 0x4,
+ },
+ [5] = {
+ .ddr_clk = 225, /* 225MHz */
+ .dmc_ddrctl = 0x00000904,
+ .dmc_ddrcfg = 0x00000422,
+ .dmc_ddrtr0 = 0x20E0A424,
+ .dmc_ddrtr1 = 0x302006DB,
+ .dmc_ddrtr2 = 0x0032020D,
+ .dmc_ddrmr = 0x00000842,
+ .dmc_ddrmr1 = 0x4,
+ },
+ [6] = {
+ .ddr_clk = 250, /* 250MHz */
+ .dmc_ddrctl = 0x00000904,
+ .dmc_ddrcfg = 0x00000422,
+ .dmc_ddrtr0 = 0x20E0A424,
+ .dmc_ddrtr1 = 0x3020079E,
+ .dmc_ddrtr2 = 0x0032050D,
+ .dmc_ddrmr = 0x00000842,
+ .dmc_ddrmr1 = 0x4,
+ },
+};
+#endif /* __ADSPBF60x__ */
+
__attribute__((always_inline))
static inline void serial_init(void)
{
- uint32_t uart_base = UART_DLL;
+ uint32_t uart_base = UART_BASE;
-#ifdef __ADSPBF54x__
+#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
# ifdef BFIN_BOOT_UART_USE_RTS
# define BFIN_UART_USE_RTS 1
# else
size_t i;
/* force RTS rather than relying on auto RTS */
+#if BFIN_UART_HW_VER < 4
bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
+#else
+ bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
+ FCPOL);
+#endif
/* Wait for the line to clear up. We cannot rely on UART
* registers as none of them reflect the status of the RSR.
#endif
if (BFIN_DEBUG_EARLY_SERIAL) {
- int ucen = bfin_read16(&pUART->gctl) & UCEN;
+ int enabled = serial_early_enabled(uart_base);
+
serial_early_init(uart_base);
/* If the UART is off, that means we need to program
* the baud rate ourselves initially.
*/
- if (ucen != UCEN)
+ if (!enabled)
serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
}
}
__attribute__((always_inline))
static inline void serial_deinit(void)
{
-#ifdef __ADSPBF54x__
- uint32_t uart_base = UART_DLL;
+#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
+ uint32_t uart_base = UART_BASE;
if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
/* clear forced RTS rather than relying on auto RTS */
+#if BFIN_UART_HW_VER < 4
bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
+#else
+ bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
+ ~FCPOL);
+#endif
}
#endif
}
__attribute__((always_inline))
static inline void serial_putc(char c)
{
- uint32_t uart_base = UART_DLL;
+ uint32_t uart_base = UART_BASE;
if (!BFIN_DEBUG_EARLY_SERIAL)
return;
if (c == '\n')
serial_putc('\r');
- bfin_write16(&pUART->thr, c);
+ bfin_write(&pUART->thr, c);
- while (!(bfin_read16(&pUART->lsr) & TEMT))
+ while (!(_lsr_read(pUART) & TEMT))
continue;
}
# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
#endif
+#ifdef __ADSPBF60x__
+
+#ifndef CONFIG_CGU_CTL_VAL
+# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
+#endif
+
+#ifndef CONFIG_CGU_DIV_VAL
+# define CONFIG_CGU_DIV_VAL \
+ ((CONFIG_CCLK_DIV << CSEL_P) | \
+ (CONFIG_SCLK0_DIV << S0SEL_P) | \
+ (CONFIG_SCLK_DIV << SYSSEL_P) | \
+ (CONFIG_SCLK1_DIV << S1SEL_P) | \
+ (CONFIG_DCLK_DIV << DSEL_P) | \
+ (CONFIG_OCLK_DIV << OSEL_P))
+#endif
+
+#else /* __ADSPBF60x__ */
+
/* PLL_DIV defines */
#ifndef CONFIG_PLL_DIV_VAL
# if (CONFIG_CCLK_DIV == 1)
# endif
#endif
+#endif /* __ADSPBF60x__ */
+
__attribute__((always_inline)) static inline void
program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
{
/* Save the clock pieces that are used in baud rate calculation */
if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
serial_putc('b');
+#ifdef __ADSPBF60x__
+ *sdivB = bfin_read_CGU_DIV();
+ *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
+ *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
+#else
*sdivB = bfin_read_PLL_DIV() & 0xf;
*vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+#endif
*divB = serial_early_get_div();
serial_putc('c');
}
*/
if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
serial_putc('e');
+#ifdef __ADSPBF60x__
+ bfin_write_SEC_GCTL(0x2);
+ SSYNC();
+ bfin_write_SEC_FCTL(0xc1);
+ bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
+
+ bfin_write_SEC_CCTL(0x2);
+ SSYNC();
+ bfin_write_SEC_GCTL(0x1);
+ bfin_write_SEC_CCTL(0x1);
+#endif
bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
+#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
bfin_write_WDOG_CTL(0);
+#endif
serial_putc('f');
}
#endif
* boot. Once we switch over to u-boot's SPI flash driver, we'll
* increase the speed appropriately.
*/
+#ifdef SPI_BAUD
if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
serial_putc('h');
if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
serial_putc('i');
}
+#endif
serial_putc('j');
}
if (!CONFIG_MEM_SIZE)
return false;
+#ifdef __ADSPBF60x__
+ /* resume from hibernate, return false let ddr initialize */
+ if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
+ serial_putc('b');
+ return false;
+ }
+
+#else /* __ADSPBF60x__ */
+
/* If external memory is enabled, put it into self refresh first. */
#if defined(EBIU_RSTCTL)
if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
}
#endif
+#endif /* __ADSPBF60x__ */
serial_putc('c');
return false;
serial_putc('a');
+#ifdef __ADSPBF60x__
+ if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+ bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
+ SSYNC();
+ while (!(bfin_read_DMC0_STAT() & SRACK))
+ continue;
+ }
+
+ /* Don't set the same value of MSEL and DF to CGU_CTL */
+ if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
+ != CONFIG_CGU_CTL_VAL) {
+ bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
+ bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
+ while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
+ !(bfin_read_CGU_STAT() & PLLLK))
+ continue;
+ }
+
+ bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
+ while (bfin_read_CGU_STAT() & CLKSALGN)
+ continue;
+
+ if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+ bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
+ SSYNC();
+ while (bfin_read_DMC0_STAT() & SRACK)
+ continue;
+ }
+
+#else /* __ADSPBF60x__ */
+
vr_ctl = bfin_read_VR_CTL();
serial_putc('b');
#elif defined(SICA_IWR0)
bfin_write_SICA_IWR0(1);
bfin_write_SICA_IWR1(0);
-#else
+#elif defined(SIC_IWR)
bfin_write_SIC_IWR(1);
#endif
#elif defined(SICA_IWR0)
bfin_write_SICA_IWR0(-1);
bfin_write_SICA_IWR1(-1);
-#else
+#elif defined(SIC_IWR)
bfin_write_SIC_IWR(-1);
#endif
serial_putc('n');
}
+#endif /* __ADSPBF60x__ */
+
serial_putc('o');
return vr_ctl;
* for dividing which means we'd generate a libgcc reference.
*/
if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
- serial_putc('b');
unsigned int sdivR, vcoR;
- sdivR = bfin_read_PLL_DIV() & 0xf;
- vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
int dividend = sdivB * divB * vcoR;
int divisor = vcoB * sdivR;
unsigned int quotient;
+
+ serial_putc('b');
+
+#ifdef __ADSPBF60x__
+ sdivR = bfin_read_CGU_DIV();
+ sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
+ vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
+#else
+ sdivR = bfin_read_PLL_DIV() & 0xf;
+ vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
+#endif
+
for (quotient = 0; dividend > 0; ++quotient)
dividend -= divisor;
- serial_early_put_div(UART_DLL, quotient - ANOMALY_05000230);
+ serial_early_put_div(quotient - ANOMALY_05000230);
serial_putc('c');
}
serial_putc('b');
+#ifdef __ADSPBF60x__
+ int dlldatacycle;
+ int dll_ctl;
+ int i = 0;
+
+ if (CONFIG_BFIN_GET_DCLK_M == 125)
+ i = 0;
+ else if (CONFIG_BFIN_GET_DCLK_M == 133)
+ i = 1;
+ else if (CONFIG_BFIN_GET_DCLK_M == 150)
+ i = 2;
+ else if (CONFIG_BFIN_GET_DCLK_M == 166)
+ i = 3;
+ else if (CONFIG_BFIN_GET_DCLK_M == 200)
+ i = 4;
+ else if (CONFIG_BFIN_GET_DCLK_M == 225)
+ i = 5;
+ else if (CONFIG_BFIN_GET_DCLK_M == 250)
+ i = 6;
+
+#if 0
+ for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
+ if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
+ break;
+#endif
+
+#ifndef CONFIG_DMC_DDRCFG
+ bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
+#else
+ bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
+#endif
+#ifndef CONFIG_DMC_DDRTR0
+ bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
+#else
+ bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
+#endif
+#ifndef CONFIG_DMC_DDRTR1
+ bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
+#else
+ bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
+#endif
+#ifndef CONFIG_DMC_DDRTR2
+ bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
+#else
+ bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
+#endif
+#ifndef CONFIG_DMC_DDRMR
+ bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
+#else
+ bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
+#endif
+#ifndef CONFIG_DMC_DDREMR1
+ bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
+#else
+ bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
+#endif
+#ifndef CONFIG_DMC_DDRCTL
+ bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
+#else
+ bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
+#endif
+
+ SSYNC();
+ while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
+ continue;
+
+ dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
+ PHYRDPHASE_OFFSET;
+ dll_ctl = bfin_read_DMC0_DLLCTL();
+ dll_ctl &= 0x0ff;
+ bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
+
+ SSYNC();
+ while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
+ continue;
+ serial_putc('!');
+
+#else /* __ADSPBF60x__ */
+
/* Program the external memory controller before we come out of
* self-refresh. This only works with our SDRAM controller.
*/
# endif
#endif
+#endif /* __ADSPBF60x__ */
serial_putc('e');
}
return;
serial_putc('b');
+#ifdef __ADSPBF60x__
+ if (bfin_read32(DPM0_RESTORE0) != 0) {
+ uint32_t reg = bfin_read_DMC0_CTL();
+ reg &= ~0x8;
+ bfin_write_DMC0_CTL(reg);
+
+ while ((bfin_read_DMC0_STAT() & 0x8))
+ continue;
+ while (!(bfin_read_DMC0_STAT() & 0x1))
+ continue;
+
+ serial_putc('z');
+ uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
+ SSYNC(); /* make sure memory controller is done */
+ if (hibernate_magic[0] == 0xDEADBEEF) {
+ serial_putc('c');
+ SSYNC();
+ bfin_write_EVT15(hibernate_magic[1]);
+ bfin_write_IMASK(EVT_IVG15);
+ __asm__ __volatile__ (
+ /* load reti early to avoid anomaly 281 */
+ "reti = %2;"
+ /* clear hibernate magic */
+ "[%0] = %1;"
+ /* load stack pointer */
+ "SP = [%0 + 8];"
+ /* lower ourselves from reset ivg to ivg15 */
+ "raise 15;"
+ "nop;nop;nop;"
+ "rti;"
+ :
+ : "p"(hibernate_magic),
+ "d"(0x2000 /* jump.s 0 */),
+ "d"(0xffa00000)
+ );
+ }
+
+ }
+#else
/* Are we coming out of hibernate (suspend to memory) ?
* The memory layout is:
* 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
*/
if (ANOMALY_05000307 || vr_ctl & 0x8000) {
uint32_t *hibernate_magic = 0;
- __builtin_bfin_ssync(); /* make sure memory controller is done */
+
+ SSYNC();
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('c');
bfin_write_EVT15(hibernate_magic[1]);
}
serial_putc('d');
}
+#endif
serial_putc('e');
}
# define serial_putc(c)
#endif
+#ifndef __ADSPBF60x__
+
#ifndef CONFIG_EBIU_RSTCTL_VAL
# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
#endif
# error invalid EBIU_DDRQUE value: must not set reserved bits
#endif
+#endif /* __ADSPBF60x__ */
+
__attribute__((always_inline)) static inline void
program_async_controller(ADI_BOOT_DATA *bs)
{
serial_putc('a');
+#ifdef __ADSPBF60x__
/* Program the async banks controller. */
+#ifdef EBIU_AMGCTL
bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
+#endif
serial_putc('b');
#endif
serial_putc('c');
+
+#else /* __ADSPBF60x__ */
+ /* Program the static memory controller. */
+# ifdef CONFIG_SMC_GCTL_VAL
+ bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B0CTL_VAL
+ bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B0TIM_VAL
+ bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B0ETIM_VAL
+ bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B1CTL_VAL
+ bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B1TIM_VAL
+ bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B1ETIM_VAL
+ bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B2CTL_VAL
+ bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B2TIM_VAL
+ bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B2ETIM_VAL
+ bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B3CTL_VAL
+ bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
+# endif
+# ifdef CONFIG_SMC_B3TIM_VAL
+ bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
+# endif
+# ifdef CONFIG_SMC_B3ETIM_VAL
+ bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
+# endif
+
+#endif
+ serial_putc('d');
}
#endif
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
+#ifdef SWRST
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
* much as possible. This code is in L1, so it won't trigger
: "a" (15 * 1)
: "LC1", "LB1", "LT1"
);
+#endif
while (1)
+#if defined(__ADSPBF60x__)
+ bfin_write_RCU0_CTL(0x1);
+#else
/* Issue core reset */
asm("raise 1");
+#endif
}
/* We need to trampoline ourselves up into L1 since our linker
#include <serial.h>
#include <linux/compiler.h>
#include <asm/blackfin.h>
-#include <asm/mach-common/bits/uart.h>
DECLARE_GLOBAL_DATA_PTR;
#include "serial.h"
#ifdef CONFIG_DEBUG_SERIAL
-static uint16_t cached_lsr[256];
-static uint16_t cached_rbr[256];
+static uart_lsr_t cached_lsr[256];
+static uart_lsr_t cached_rbr[256];
static size_t cache_count;
/* The LSR is read-to-clear on some parts, so we have to make sure status
* works around anomaly 05000099 at the same time by keeping a cumulative
* tally of all the status bits.
*/
-static uint16_t uart_lsr_save;
-static uint16_t uart_lsr_read(uint32_t uart_base)
+static uart_lsr_t uart_lsr_save;
+static uart_lsr_t uart_lsr_read(uint32_t uart_base)
{
- uint16_t lsr = bfin_read(&pUART->lsr);
+ uart_lsr_t lsr = _lsr_read(pUART);
uart_lsr_save |= (lsr & (OE|PE|FE|BI));
return lsr | uart_lsr_save;
}
static void uart_lsr_clear(uint32_t uart_base)
{
uart_lsr_save = 0;
- bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
+ _lsr_write(pUART, -1);
}
#else
/* When debugging is disabled, we only care about the DR bit, so if other
* bits get set/cleared, we don't really care since we don't read them
* anyways (and thus anomaly 05000099 is irrelevant).
*/
-static inline uint16_t uart_lsr_read(uint32_t uart_base)
+static inline uart_lsr_t uart_lsr_read(uint32_t uart_base)
{
- return bfin_read(&pUART->lsr);
+ return _lsr_read(pUART);
}
static void uart_lsr_clear(uint32_t uart_base)
{
- bfin_write(&pUART->lsr, bfin_read(&pUART->lsr) | -1);
+ _lsr_write(pUART, -1);
}
#endif
#ifdef CONFIG_DEBUG_SERIAL
/* grab & clear the LSR */
- uint16_t uart_lsr_val = uart_lsr_read(uart_base);
+ uart_lsr_t uart_lsr_val = uart_lsr_read(uart_base);
cached_lsr[cache_count] = uart_lsr_val;
cached_rbr[cache_count] = uart_rbr_val;
cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
if (uart_lsr_val & (OE|PE|FE|BI)) {
- uint16_t dll, dlh;
printf("\n[SERIAL ERROR]\n");
- ACCESS_LATCH();
- dll = bfin_read(&pUART->dll);
- dlh = bfin_read(&pUART->dlh);
- ACCESS_PORT_IER();
- printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
do {
--cache_count;
printf("\t%3zu: RBR=0x%02x LSR=0x%02x\n", cache_count,
# define LOOP(x)
#endif
+#if BFIN_UART_HW_VER < 4
+
LOOP(
static void uart_loop(uint32_t uart_base, int state)
{
}
)
+#else
+
+LOOP(
+static void uart_loop(uint32_t uart_base, int state)
+{
+ u32 control;
+
+ /* Drain the TX fifo first so bytes don't come back */
+ while (!(uart_lsr_read(uart_base) & TEMT))
+ continue;
+
+ control = bfin_read(&pUART->control);
+ if (state)
+ control |= LOOP_ENA | MRTS;
+ else
+ control &= ~(LOOP_ENA | MRTS);
+ bfin_write(&pUART->control, control);
+}
+)
+
+#endif
+
#ifdef CONFIG_SYS_BFIN_UART
static void uart_puts(uint32_t uart_base, const char *s)
LOOP(.loop = uart##n##_loop) \
};
-#ifdef UART0_DLL
+#ifdef UART0_RBR
DECL_BFIN_UART(0)
#endif
-#ifdef UART1_DLL
+#ifdef UART1_RBR
DECL_BFIN_UART(1)
#endif
-#ifdef UART2_DLL
+#ifdef UART2_RBR
DECL_BFIN_UART(2)
#endif
-#ifdef UART3_DLL
+#ifdef UART3_RBR
DECL_BFIN_UART(3)
#endif
void bfin_serial_initialize(void)
{
-#ifdef UART0_DLL
+#ifdef UART0_RBR
serial_register(&bfin_serial0_device);
#endif
-#ifdef UART1_DLL
+#ifdef UART1_RBR
serial_register(&bfin_serial1_device);
#endif
-#ifdef UART2_DLL
+#ifdef UART2_RBR
serial_register(&bfin_serial2_device);
#endif
-#ifdef UART3_DLL
+#ifdef UART3_RBR
serial_register(&bfin_serial3_device);
#endif
}
/* Symbol for our assembly to call. */
void serial_set_baud(uint32_t baud)
{
- serial_early_set_baud(UART_DLL, baud);
+ serial_early_set_baud(UART_BASE, baud);
}
/* Symbol for common u-boot code to call.
/* Symbol for our assembly to call. */
void serial_initialize(void)
{
- serial_early_init(UART_DLL);
+ serial_early_init(UART_BASE);
}
/* Symbol for common u-boot code to call. */
{
serial_initialize();
serial_setbrg();
- uart_lsr_clear(UART_DLL);
+ uart_lsr_clear(UART_BASE);
return 0;
}
int serial_tstc(void)
{
- return uart_tstc(UART_DLL);
+ return uart_tstc(UART_BASE);
}
int serial_getc(void)
{
- return uart_getc(UART_DLL);
+ return uart_getc(UART_BASE);
}
void serial_putc(const char c)
{
- uart_putc(UART_DLL, c);
+ uart_putc(UART_BASE, c);
}
void serial_puts(const char *s)
LOOP(
void serial_loop(int state)
{
- uart_loop(UART_DLL, state);
+ uart_loop(UART_BASE, state);
}
)
* any functions defined here must be always_inline since
* initcode cannot have function calls.
*
- * Copyright (c) 2004-2007 Analog Devices Inc.
+ * Copyright (c) 2004-2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#define __BFIN_CPU_SERIAL_H__
#include <asm/blackfin.h>
-#include <asm/mach-common/bits/uart.h>
+#include <asm/portmux.h>
#ifndef CONFIG_UART_CONSOLE
# define CONFIG_UART_CONSOLE 0
# define BFIN_DEBUG_EARLY_SERIAL 0
#endif
-#ifndef __ASSEMBLY__
-
-#include <asm/portmux.h>
-
-#define LOB(x) ((x) & 0xFF)
-#define HIB(x) (((x) >> 8) & 0xFF)
-
-#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
+#if defined(__ADSPBF60x__)
+# define BFIN_UART_HW_VER 4
+#elif defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
# define BFIN_UART_HW_VER 2
#else
# define BFIN_UART_HW_VER 1
#endif
-/*
- * All Blackfin system MMRs are padded to 32bits even if the register
- * itself is only 16bits. So use a helper macro to streamline this.
- */
-#define __BFP(m) u16 m; u16 __pad_##m
-struct bfin_mmr_serial {
-#if BFIN_UART_HW_VER == 2
- __BFP(dll);
- __BFP(dlh);
- __BFP(gctl);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- __BFP(ier_set);
- __BFP(ier_clear);
- __BFP(thr);
- __BFP(rbr);
-#else
- union {
- u16 dll;
- u16 thr;
- const u16 rbr;
- };
- const u16 __spad0;
- union {
- u16 dlh;
- u16 ier;
- };
- const u16 __spad1;
- const __BFP(iir);
- __BFP(lcr);
- __BFP(mcr);
- __BFP(lsr);
- __BFP(msr);
- __BFP(scr);
- const u32 __spad2;
- __BFP(gctl);
-#endif
-};
-#undef __BFP
-
#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
-#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
-#ifndef UART_DLL
-# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE)
-#else
-# define UART0_DLL UART_DLL
-# if CONFIG_UART_CONSOLE != 0
-# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
-# endif
-#endif
#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
-#if BFIN_UART_HW_VER == 2
-# define ACCESS_LATCH()
-# define ACCESS_PORT_IER()
+#ifndef __ASSEMBLY__
+__attribute__((always_inline))
+static inline void serial_do_portmux(void);
+#endif
+
+#if BFIN_UART_HW_VER < 4
+# include "serial1.h"
#else
-# define ACCESS_LATCH() \
- bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB)
-# define ACCESS_PORT_IER() \
- bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB)
+# include "serial4.h"
#endif
+#ifndef __ASSEMBLY__
+
__attribute__((always_inline))
static inline void serial_do_portmux(void)
{
return;
}
-#if defined(__ADSPBF50x__)
-# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
- bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \
- bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
- switch (CONFIG_UART_CONSOLE) {
- case 0: DO_MUX(G, 7, 7, 12, 13); break; /* Port G; mux 7; PG12 and PG13 */
- case 1: DO_MUX(F, 3, 3, 6, 7); break; /* Port F; mux 3; PF6 and PF7 */
- }
- SSYNC();
-#elif defined(__ADSPBF51x__)
-# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
- bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
- bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
- switch (CONFIG_UART_CONSOLE) {
- case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */
- case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */
- }
- SSYNC();
-#elif defined(__ADSPBF52x__)
-# define DO_MUX(port, mux, tx, rx) \
- bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
- bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
- switch (CONFIG_UART_CONSOLE) {
- case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */
- case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */
- }
- SSYNC();
-#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
- const uint16_t func[] = { PFDE, PFTE, };
- bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
- bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
- (1 << P_IDENT(P_UART(RX))) |
- (1 << P_IDENT(P_UART(TX))));
- SSYNC();
-#elif defined(__ADSPBF54x__)
-# define DO_MUX(port, tx, rx) \
- bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
- bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
- switch (CONFIG_UART_CONSOLE) {
- case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */
- case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */
- case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */
- case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */
- }
- SSYNC();
-#elif defined(__ADSPBF561__)
- /* UART pins could be GPIO, but they aren't pin muxed. */
-#else
-# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
-# error "missing portmux logic for UART"
-# endif
-#endif
-}
-
-__attribute__((always_inline))
-static inline int uart_init(uint32_t uart_base)
-{
- /* always enable UART -- avoids anomalies 05000309 and 05000350 */
- bfin_write(&pUART->gctl, UCEN);
-
- /* Set LCR to Word Lengh 8-bit word select */
- bfin_write(&pUART->lcr, WLS_8);
-
- SSYNC();
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline int serial_early_init(uint32_t uart_base)
-{
- /* handle portmux crap on different Blackfins */
- serial_do_portmux();
-
- return uart_init(uart_base);
-}
-
-__attribute__((always_inline))
-static inline int serial_early_uninit(uint32_t uart_base)
-{
- /* disable the UART by clearing UCEN */
- bfin_write(&pUART->gctl, 0);
-
- return 0;
-}
-
-__attribute__((always_inline))
-static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor)
-{
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- /* Program the divisor to get the baud rate we want */
- bfin_write(&pUART->dll, LOB(divisor));
- bfin_write(&pUART->dlh, HIB(divisor));
- SSYNC();
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-}
-
-__attribute__((always_inline))
-static inline uint16_t serial_early_get_div(void)
-{
- uint32_t uart_base = UART_DLL;
-
- /* Set DLAB in LCR to Access DLL and DLH */
- ACCESS_LATCH();
- SSYNC();
-
- uint8_t dll = bfin_read(&pUART->dll);
- uint8_t dlh = bfin_read(&pUART->dlh);
- uint16_t divisor = (dlh << 8) | dll;
-
- /* Clear DLAB in LCR to Access THR RBR IER */
- ACCESS_PORT_IER();
- SSYNC();
-
- return divisor;
-}
-
-/* We cannot use get_sclk() early on as it uses caches in external memory */
-#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
-# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
-{
- /* Translate from baud into divisor in terms of SCLK. The
- * weird multiplication is to make sure we over sample just
- * a little rather than under sample the incoming signals.
- */
- serial_early_put_div(uart_base,
- (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
+ serial_early_do_portmux();
}
#ifndef BFIN_IN_INITCODE
--- /dev/null
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ * any functions defined here must be always_inline since
+ * initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL1_H__
+#define __BFIN_CPU_SERIAL1_H__
+
+#include <asm/mach-common/bits/uart.h>
+
+#ifndef __ASSEMBLY__
+
+#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
+#ifdef UART_DLL
+# define UART0_DLL UART_DLL
+# if CONFIG_UART_CONSOLE != 0
+# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
+# endif
+#endif
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+#define LOB(x) ((x) & 0xFF)
+#define HIB(x) (((x) >> 8) & 0xFF)
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits. So use a helper macro to streamline this.
+ */
+struct bfin_mmr_serial {
+#if BFIN_UART_HW_VER == 2
+ u16 dll;
+ u16 __pad_0;
+ u16 dlh;
+ u16 __pad_1;
+ u16 gctl;
+ u16 __pad_2;
+ u16 lcr;
+ u16 __pad_3;
+ u16 mcr;
+ u16 __pad_4;
+ u16 lsr;
+ u16 __pad_5;
+ u16 msr;
+ u16 __pad_6;
+ u16 scr;
+ u16 __pad_7;
+ u16 ier_set;
+ u16 __pad_8;
+ u16 ier_clear;
+ u16 __pad_9;
+ u16 thr;
+ u16 __pad_10;
+ u16 rbr;
+ u16 __pad_11;
+#else
+ union {
+ u16 dll;
+ u16 thr;
+ const u16 rbr;
+ };
+ const u16 __spad0;
+ union {
+ u16 dlh;
+ u16 ier;
+ };
+ const u16 __spad1;
+ const u16 iir;
+ u16 __pad_0;
+ u16 lcr;
+ u16 __pad_1;
+ u16 mcr;
+ u16 __pad_2;
+ u16 lsr;
+ u16 __pad_3;
+ u16 msr;
+ u16 __pad_4;
+ u16 scr;
+ u16 __pad_5;
+ const u32 __spad2;
+ u16 gctl;
+ u16 __pad_6;
+#endif
+};
+
+#define uart_lsr_t uint32_t
+#define _lsr_read(p) bfin_read(&p->lsr)
+#define _lsr_write(p, v) bfin_write(&p->lsr, v)
+
+#if BFIN_UART_HW_VER == 2
+# define ACCESS_LATCH()
+# define ACCESS_PORT_IER()
+#else
+# define ACCESS_LATCH() bfin_write_or(&pUART->lcr, DLAB)
+# define ACCESS_PORT_IER() bfin_write_and(&pUART->lcr, ~DLAB)
+#endif
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+ int mux_func, int port_pin)
+{
+ switch (port) {
+#if defined(__ADSPBF54x__)
+ case 'B':
+ bfin_write_PORTB_MUX((bfin_read_PORTB_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTB_FER(bfin_read_PORTB_FER() | port_pin);
+ break;
+ case 'E':
+ bfin_write_PORTE_MUX((bfin_read_PORTE_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTE_FER(bfin_read_PORTE_FER() | port_pin);
+ break;
+#endif
+#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF52x__)
+ case 'F':
+ bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() | port_pin);
+ break;
+ case 'G':
+ bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTG_FER(bfin_read_PORTG_FER() | port_pin);
+ break;
+ case 'H':
+ bfin_write_PORTH_MUX((bfin_read_PORTH_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTH_FER(bfin_read_PORTH_FER() | port_pin);
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF50x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PG12); /* TX: G; mux 7; func 1; PG12 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PG13); /* RX: G; mux 7; func 1; PG13 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_1, PF7); /* TX: F; mux 3; func 1; PF6 */
+ serial_early_do_mach_portmux('F', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_1, PF6); /* RX: F; mux 3; func 1; PF7 */
+ break;
+ }
+#elif defined(__ADSPBF51x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_2, PG9); /* TX: G; mux 5; func 2; PG9 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_2, PG10); /* RX: G; mux 5; func 2; PG10 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_2, PH7); /* TX: H; mux 3; func 2; PH6 */
+ serial_early_do_mach_portmux('H', PORT_x_MUX_3_MASK,
+ PORT_x_MUX_3_FUNC_2, PH6); /* RX: H; mux 3; func 2; PH7 */
+ break;
+ }
+#elif defined(__ADSPBF52x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+ PORT_x_MUX_2_FUNC_3, PG7); /* TX: G; mux 2; func 3; PG7 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_2_MASK,
+ PORT_x_MUX_2_FUNC_3, PG8); /* RX: G; mux 2; func 3; PG8 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_3, PF14); /* TX: F; mux 5; func 3; PF14 */
+ serial_early_do_mach_portmux('F', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_3, PF15); /* RX: F; mux 5; func 3; PF15 */
+ break;
+ }
+#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
+ const uint16_t func[] = { PFDE, PFTE, };
+ bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
+ bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
+ (1 << P_IDENT(P_UART(RX))) |
+ (1 << P_IDENT(P_UART(TX))));
+#elif defined(__ADSPBF54x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('E', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PE7); /* TX: E; mux 7; func 1; PE7 */
+ serial_early_do_mach_portmux('E', PORT_x_MUX_8_MASK,
+ PORT_x_MUX_8_FUNC_1, PE8); /* RX: E; mux 8; func 1; PE8 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('H', PORT_x_MUX_0_MASK,
+ PORT_x_MUX_0_FUNC_1, PH0); /* TX: H; mux 0; func 1; PH0 */
+ serial_early_do_mach_portmux('H', PORT_x_MUX_1_MASK,
+ PORT_x_MUX_1_FUNC_1, PH1); /* RX: H; mux 1; func 1; PH1 */
+ break;
+ case 2:
+ serial_early_do_mach_portmux('B', PORT_x_MUX_4_MASK,
+ PORT_x_MUX_4_FUNC_1, PB4); /* TX: B; mux 4; func 1; PB4 */
+ serial_early_do_mach_portmux('B', PORT_x_MUX_5_MASK,
+ PORT_x_MUX_5_FUNC_1, PB5); /* RX: B; mux 5; func 1; PB5 */
+ break;
+ case 3:
+ serial_early_do_mach_portmux('B', PORT_x_MUX_6_MASK,
+ PORT_x_MUX_6_FUNC_1, PB6); /* TX: B; mux 6; func 1; PB6 */
+ serial_early_do_mach_portmux('B', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_1, PB7); /* RX: B; mux 7; func 1; PB7 */
+ break;
+ }
+#elif defined(__ADSPBF561__)
+ /* UART pins could be GPIO, but they aren't pin muxed. */
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+# error "missing portmux logic for UART"
+# endif
+#endif
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint32_t uart_sclk(void)
+{
+#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
+ /* We cannot use get_sclk() early on as it uses
+ * caches in external memory
+ */
+ return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV;
+#else
+ return get_sclk();
+#endif
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+ /* always enable UART -- avoids anomalies 05000309 and 05000350 */
+ bfin_write(&pUART->gctl, UCEN);
+
+ /* Set LCR to Word Lengh 8-bit word select */
+ bfin_write(&pUART->lcr, WLS_8);
+
+ SSYNC();
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+ /* handle portmux crap on different Blackfins */
+ serial_do_portmux();
+
+ return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+ /* disable the UART by clearing UCEN */
+ bfin_write(&pUART->gctl, 0);
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_enabled(uint32_t uart_base)
+{
+ return bfin_read(&pUART->gctl) & UCEN;
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+ /* Translate from baud into divisor in terms of SCLK. The
+ * weird multiplication is to make sure we over sample just
+ * a little rather than under sample the incoming signals.
+ */
+ uint16_t divisor = (uart_sclk() + (baud * 8)) / (baud * 16) -
+ ANOMALY_05000230;
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ /* Program the divisor to get the baud rate we want */
+ bfin_write(&pUART->dll, LOB(divisor));
+ bfin_write(&pUART->dlh, HIB(divisor));
+ SSYNC();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint16_t divisor)
+{
+ uint32_t uart_base = UART_BASE;
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ /* Program the divisor to get the baud rate we want */
+ bfin_write(&pUART->dll, LOB(divisor));
+ bfin_write(&pUART->dlh, HIB(divisor));
+ SSYNC();
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint16_t serial_early_get_div(void)
+{
+ uint32_t uart_base = UART_BASE;
+
+ /* Set DLAB in LCR to Access DLL and DLH */
+ ACCESS_LATCH();
+ SSYNC();
+
+ uint8_t dll = bfin_read(&pUART->dll);
+ uint8_t dlh = bfin_read(&pUART->dlh);
+ uint16_t divisor = (dlh << 8) | dll;
+
+ /* Clear DLAB in LCR to Access THR RBR IER */
+ ACCESS_PORT_IER();
+ SSYNC();
+
+ return divisor;
+}
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * serial.h - common serial defines for early debug and serial driver.
+ * any functions defined here must be always_inline since
+ * initcode cannot have function calls.
+ *
+ * Copyright (c) 2004-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_CPU_SERIAL4_H__
+#define __BFIN_CPU_SERIAL4_H__
+
+#include <asm/mach-common/bits/uart4.h>
+
+#ifndef __ASSEMBLY__
+
+#define MMR_UART(n) _PASTE_UART(n, UART, REVID)
+#define UART_BASE MMR_UART(CONFIG_UART_CONSOLE)
+
+struct bfin_mmr_serial {
+ u32 revid;
+ u32 control;
+ u32 status;
+ u32 scr;
+ u32 clock;
+ u32 emask;
+ u32 emaskst;
+ u32 emaskcl;
+ u32 rbr;
+ u32 thr;
+ u32 taip;
+ u32 tsr;
+ u32 rsr;
+ u32 txdiv_cnt;
+ u32 rxdiv_cnt;
+};
+#define uart_lsr_t uint32_t
+#define _lsr_read(p) bfin_read(&p->status)
+#define _lsr_write(p, v) bfin_write(&p->status, v)
+
+__attribute__((always_inline))
+static inline void serial_early_do_mach_portmux(char port, int mux_mask,
+ int mux_func, int port_pin)
+{
+ switch (port) {
+ case 'D':
+ bfin_write_PORTD_MUX((bfin_read_PORTD_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTD_FER_SET(port_pin);
+ break;
+ case 'G':
+ bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() &
+ ~mux_mask) | mux_func);
+ bfin_write_PORTG_FER_SET(port_pin);
+ break;
+ }
+}
+
+__attribute__((always_inline))
+static inline void serial_early_do_portmux(void)
+{
+#if defined(__ADSPBF60x__)
+ switch (CONFIG_UART_CONSOLE) {
+ case 0:
+ serial_early_do_mach_portmux('D', PORT_x_MUX_7_MASK,
+ PORT_x_MUX_7_FUNC_2, PD7); /* TX: D; mux 7; func 2; PD7 */
+ serial_early_do_mach_portmux('D', PORT_x_MUX_8_MASK,
+ PORT_x_MUX_8_FUNC_2, PD8); /* RX: D; mux 8; func 2; PD8 */
+ break;
+ case 1:
+ serial_early_do_mach_portmux('G', PORT_x_MUX_15_MASK,
+ PORT_x_MUX_15_FUNC_1, PG15); /* TX: G; mux 15; func 1; PG15 */
+ serial_early_do_mach_portmux('G', PORT_x_MUX_14_MASK,
+ PORT_x_MUX_14_FUNC_1, PG14); /* RX: G; mux 14; func 1; PG14 */
+ break;
+ }
+#else
+# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
+# error "missing portmux logic for UART"
+# endif
+#endif
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline uint32_t uart_sclk(void)
+{
+#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
+ /* We cannot use get_sclk() early on as it uses caches in
+ * external memory
+ */
+ return CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV /
+ CONFIG_SCLK0_DIV;
+#else
+ return get_sclk0();
+#endif
+}
+
+__attribute__((always_inline))
+static inline int uart_init(uint32_t uart_base)
+{
+ /* always enable UART to 8-bit mode */
+ bfin_write(&pUART->control, UEN | UMOD_UART | WLS_8);
+
+ SSYNC();
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_init(uint32_t uart_base)
+{
+ /* handle portmux crap on different Blackfins */
+ serial_do_portmux();
+
+ return uart_init(uart_base);
+}
+
+__attribute__((always_inline))
+static inline int serial_early_uninit(uint32_t uart_base)
+{
+ /* disable the UART by clearing UEN */
+ bfin_write(&pUART->control, 0);
+
+ return 0;
+}
+
+__attribute__((always_inline))
+static inline int serial_early_enabled(uint32_t uart_base)
+{
+ return bfin_read(&pUART->control) & UEN;
+}
+
+__attribute__((always_inline))
+static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
+{
+ uint32_t divisor = uart_sclk() / (baud * 16);
+
+ /* Program the divisor to get the baud rate we want */
+ bfin_write(&pUART->clock, divisor);
+ SSYNC();
+}
+
+__attribute__((always_inline))
+static inline void serial_early_put_div(uint32_t divisor)
+{
+ uint32_t uart_base = UART_BASE;
+ bfin_write(&pUART->clock, divisor);
+}
+
+__attribute__((always_inline))
+static inline uint32_t serial_early_get_div(void)
+{
+ uint32_t uart_base = UART_BASE;
+ return bfin_read(&pUART->clock);
+}
+
+#endif
+
+#endif
p5.h = HI(COREMMR_BASE);
#ifdef CONFIG_HW_WATCHDOG
+#ifndef __ADSPBF60x__
# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
# define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
# endif
[p4 + (WDOG_CNT - SYSMMR_BASE)] = r0;
/* fire up the watchdog - R0.L above needs to be 0x0000 */
W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0;
+#endif
#endif
/* Turn on the serial for debugging the init process */
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
} >ram_data
.text_l1 :
#ifdef __ADSPBF561__
# include "mach-bf561/BF561_cdef.h"
#endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_cdef.h"
+#endif
#endif /* __MACH_CDEF_BLACKFIN__ */
# include "mach-bf561/anomaly.h"
# include "mach-bf561/def_local.h"
#endif
+#ifdef __ADSPBF609__
+# include "mach-bf609/BF609_def.h"
+# include "mach-bf609/anomaly.h"
+# include "mach-bf609/def_local.h"
+#endif
#endif /* __MACH_DEF_BLACKFIN__ */
extern u_long get_vco(void);
extern u_long get_cclk(void);
extern u_long get_sclk(void);
+extern u_long get_sclk0(void);
+extern u_long get_sclk1(void);
+extern u_long get_dclk(void);
# define bfin_revid() (bfin_read_CHIPID() >> 28)
#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */
#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */
#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */
+#define BFIN_BOOT_RSI_MASTER 14 /* boot ldr from rsi */
+#define BFIN_BOOT_LP_SLAVE 15 /* boot ldr from link port */
#ifndef __ASSEMBLY__
static inline const char *get_bfin_boot_mode(int bfin_boot)
case BFIN_BOOT_16HOST_DMA: return "16bit dma";
case BFIN_BOOT_8HOST_DMA: return "8bit dma";
case BFIN_BOOT_NAND: return "nand flash";
+ case BFIN_BOOT_RSI_MASTER: return "rsi master";
+ case BFIN_BOOT_LP_SLAVE: return "link port slave";
default: return "INVALID";
}
}
#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
/* Data Attibutes*/
-
-#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
+#if defined(__ADSPBF60x__)
+#define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
+ CPLB_USER_RD | CPLB_VALID)
+#else
+#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
+ CPLB_USER_RD | CPLB_VALID)
+#endif
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
#endif
#ifdef CONFIG_DCACHE_WB /*Write Back Policy */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#if defined(__ADSPBF60x__)
+#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
+ CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
+ CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
+ CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
+ CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#else /*Write Through */
-#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#if defined(__ADSPBF60x__)
+#define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
+ CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
+ CPLB_USER_WR | CPLB_VALID | \
+ ANOMALY_05000158_WORKAROUND)
+#else
+#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
+ CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
+ CPLB_USER_WR | CPLB_VALID | \
+ ANOMALY_05000158_WORKAROUND)
+#endif
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
#ifndef _BLACKFIN_DMA_H_
#define _BLACKFIN_DMA_H_
+#include <linux/types.h>
+#ifdef __ADSPBF60x__
+#include <asm/mach-common/bits/dde.h>
+#else
#include <asm/mach-common/bits/dma.h>
+#endif
struct dmasg_large {
void *next_desc_addr;
} __attribute__((packed));
struct dma_register {
+#ifdef __ADSPBF60x__
+ void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
+ u32 start_addr; /* DMA Start address register */
+ u32 config; /* DMA Configuration register */
+
+ u32 x_count; /* DMA x_count register */
+ s32 x_modify; /* DMA x_modify register */
+ u32 y_count; /* DMA y_count register */
+ s32 y_modify; /* DMA y_modify register */
+ u32 __pad0[2];
+
+ void *curr_desc_ptr; /* DMA Curr Descriptor Pointer register */
+ void *prev_desc_ptr; /* DMA Prev Descriptor Pointer register */
+ void *curr_addr; /* DMA Current Address Pointer register */
+ u32 status; /* DMA irq status register */
+ u32 curr_x_count; /* DMA Current x-count register */
+ u32 curr_y_count; /* DMA Current y-count register */
+ u32 __pad1[2];
+
+ u32 bw_limit; /* DMA Bandwidth Limit Count */
+ u32 curr_bw_limit; /* DMA curr Bandwidth Limit Count */
+ u32 bw_monitor; /* DMA Bandwidth Monitor Count */
+ u32 curr_bw_monitor; /* DMA curr Bandwidth Monitor Count */
+#else
void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
- unsigned long start_addr; /* DMA Start address register */
+ u32 start_addr; /* DMA Start address register */
- unsigned short cfg; /* DMA Configuration register */
- unsigned short dummy1; /* DMA Configuration register */
+ u16 config; /* DMA Configuration register */
+ u16 dummy1; /* DMA Configuration register */
- unsigned long reserved;
+ u32 reserved;
- unsigned short x_count; /* DMA x_count register */
- unsigned short dummy2;
+ u16 x_count; /* DMA x_count register */
+ u16 dummy2;
- short x_modify; /* DMA x_modify register */
- unsigned short dummy3;
+ s16 x_modify; /* DMA x_modify register */
+ u16 dummy3;
- unsigned short y_count; /* DMA y_count register */
- unsigned short dummy4;
+ u16 y_count; /* DMA y_count register */
+ u16 dummy4;
- short y_modify; /* DMA y_modify register */
- unsigned short dummy5;
+ s16 y_modify; /* DMA y_modify register */
+ u16 dummy5;
- void *curr_desc_ptr; /* DMA Current Descriptor Pointer
- register */
- unsigned long curr_addr_ptr; /* DMA Current Address Pointer
- register */
- unsigned short irq_status; /* DMA irq status register */
- unsigned short dummy6;
+ void *curr_desc_ptr; /* DMA Current Descriptor Pointer register */
- unsigned short peripheral_map; /* DMA peripheral map register */
- unsigned short dummy7;
+ u32 curr_addr_ptr; /* DMA Current Address Pointer register */
- unsigned short curr_x_count; /* DMA Current x-count register */
- unsigned short dummy8;
+ u16 status; /* DMA irq status register */
+ u16 dummy6;
- unsigned long reserved2;
+ u16 peripheral_map; /* DMA peripheral map register */
+ u16 dummy7;
- unsigned short curr_y_count; /* DMA Current y-count register */
- unsigned short dummy9;
+ u16 curr_x_count; /* DMA Current x-count register */
+ u16 dummy8;
- unsigned long reserved3;
+ u32 reserved2;
+ u16 curr_y_count; /* DMA Current y-count register */
+ u16 dummy9;
+
+ u32 reserved3;
+#endif
};
#endif
#ifndef __ASSEMBLY__
-#ifndef CONFIG_BF54x
+#if !defined(CONFIG_BF54x) && !defined(CONFIG_BF60x)
void set_gpio_dir(unsigned, unsigned short);
void set_gpio_inen(unsigned, unsigned short);
void set_gpio_polar(unsigned, unsigned short);
#define UART_LSR 0xFFC00414
#define UART_SCR 0xFFC0041C
#define UART_RBR 0xFFC00400 /* Receive Buffer */
+#define UART0_RBR UART_RBR
#define UART_GCTL 0xFFC00424
#define SPT0_TX_CONFIG0 0xFFC00800
#define SPT0_TX_CONFIG1 0xFFC00804
#define PPI1_FRAME 0xFFC01310
#define UART_THR 0xFFC00400
#define UART_RBR 0xFFC00400
+#define UART0_RBR UART_RBR
#define UART_DLL 0xFFC00400
#define UART_DLH 0xFFC00404
#define UART_IER 0xFFC00404
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF609_proc__
+#define __BFIN_CDEF_ADSP_BF609_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#define bfin_read_CGU_STAT() bfin_read32(CGU_STAT)
+#define bfin_read_CGU_CLKOUTSEL() bfin_read32(CGU_CLKOUTSEL)
+#define bfin_read_CGU_CTL() bfin_read32(CGU_CTL)
+#define bfin_write_CGU_CTL(val) bfin_write32(CGU_CTL, val)
+#define bfin_read_CGU_DIV() bfin_read32(CGU_DIV)
+#define bfin_write_CGU_DIV(val) bfin_write32(CGU_DIV, val)
+
+#define bfin_read_RCU0_CTL() bfin_read32(RCU0_CTL)
+#define bfin_write_RCU0_CTL(val) bfin_write32(RCU0_CTL, val)
+
+#define bfin_read_CHIPID() bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
+
+#define bfin_read_DMC0_CFG() bfin_read32(DMC0_CFG)
+#define bfin_write_DMC0_CFG(val) bfin_write32(DMC0_CFG, val)
+#define bfin_read_DMC0_TR0() bfin_read32(DMC0_TR0)
+#define bfin_write_DMC0_TR0(val) bfin_write32(DMC0_TR0, val)
+#define bfin_read_DMC0_TR1() bfin_read32(DMC0_TR1)
+#define bfin_write_DMC0_TR1(val) bfin_write32(DMC0_TR1, val)
+#define bfin_read_DMC0_TR2() bfin_read32(DMC0_TR2)
+#define bfin_write_DMC0_TR2(val) bfin_write32(DMC0_TR2, val)
+#define bfin_read_DMC0_MR() bfin_read32(DMC0_MR)
+#define bfin_write_DMC0_MR(val) bfin_write32(DMC0_MR, val)
+#define bfin_read_DMC0_EMR1() bfin_read32(DMC0_EMR1)
+#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
+#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
+#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
+#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
+#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
+#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
+#define bfin_write_DMC0_DLLCTL(val) bfin_write32(DMC0_DLLCTL, val)
+
+#define bfin_read_SEC_CCTL() bfin_read32(SEC0_CCTL0)
+#define bfin_write_SEC_CCTL(val) bfin_write32(SEC0_CCTL0, val)
+#define bfin_read_SEC_GCTL() bfin_read32(SEC0_GCTL)
+#define bfin_write_SEC_GCTL(val) bfin_write32(SEC0_GCTL, val)
+
+#define bfin_read_SEC_FCTL() bfin_read32(SEC0_FCTL)
+#define bfin_write_SEC_FCTL(val) bfin_write32(SEC0_FCTL, val)
+#define bfin_read_SEC_SCTL(sid) bfin_read32((SEC0_SCTL0 + (sid) * 8))
+#define bfin_write_SEC_SCTL(sid, val) bfin_write32((SEC0_SCTL0 \
+ + (sid) * 8), val)
+
+#define bfin_read_SMC_GCTL() bfin_read32(SMC_GCTL)
+#define bfin_write_SMC_GCTL(val) bfin_write32(SMC_GCTL, val)
+#define bfin_read_SMC_GSTAT() bfin_read32(SMC_GSTAT)
+#define bfin_read_SMC_B0CTL() bfin_read32(SMC_B0CTL)
+#define bfin_write_SMC_B0CTL(val) bfin_write32(SMC_B0CTL, val)
+#define bfin_read_SMC_B0TIM() bfin_read32(SMC_B0TIM)
+#define bfin_write_SMC_B0TIM(val) bfin_write32(SMC_B0TIM, val)
+#define bfin_read_SMC_B0ETIM() bfin_read32(SMC_B0ETIM)
+#define bfin_write_SMC_B0ETIM(val) bfin_write32(SMC_B0ETIM, val)
+#define bfin_read_SMC_B1CTL() bfin_read32(SMC_B1CTL)
+#define bfin_write_SMC_B1CTL(val) bfin_write32(SMC_B1CTL, val)
+#define bfin_read_SMC_B1TIM() bfin_read32(SMC_B1TIM)
+#define bfin_write_SMC_B1TIM(val) bfin_write32(SMC_B1TIM, val)
+#define bfin_read_SMC_B1ETIM() bfin_read32(SMC_B1ETIM)
+#define bfin_write_SMC_B1ETIM(val) bfin_write32(SMC_B1ETIM, val)
+#define bfin_read_SMC_B2CTL() bfin_read32(SMC_B2CTL)
+#define bfin_write_SMC_B2CTL(val) bfin_write32(SMC_B2CTL, val)
+#define bfin_read_SMC_B2TIM() bfin_read32(SMC_B2TIM)
+#define bfin_write_SMC_B2TIM(val) bfin_write32(SMC_B2TIM, val)
+#define bfin_read_SMC_B2ETIM() bfin_read32(SMC_B2ETIM)
+#define bfin_write_SMC_B2ETIM(val) bfin_write32(SMC_B2ETIM, val)
+#define bfin_read_SMC_B3CTL() bfin_read32(SMC_B3CTL)
+#define bfin_write_SMC_B3CTL(val) bfin_write32(SMC_B3CTL, val)
+#define bfin_read_SMC_B3TIM() bfin_read32(SMC_B3TIM)
+#define bfin_write_SMC_B3TIM(val) bfin_write32(SMC_B3TIM, val)
+#define bfin_read_SMC_B3ETIM() bfin_read32(SMC_B3ETIM)
+#define bfin_write_SMC_B3ETIM(val) bfin_write32(SMC_B3ETIM, val)
+
+#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLL_OSC)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLL_OSC, val)
+#define bfin_write_USB_VBUS_CTL(val) bfin_write8(USB_VBUS_CTL, val)
+#define bfin_read_USB_DMA_INTERRUPT() bfin_read8(USB_DMA_IRQ)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write8(USB_DMA_IRQ, val)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write8(USB_PHY_CTL, val)
+#define bfin_read_USB_APHY_CNTRL() bfin_read8(USB_PHY_CTL)
+
+#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_NXT)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_NXT, val)
+#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_ADDRSTART)
+#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_ADDRSTART, val)
+#define bfin_read_DMA10_CONFIG() bfin_read32(DMA10_CFG)
+#define bfin_write_DMA10_CONFIG(val) bfin_write32(DMA10_CFG, val)
+#define bfin_read_DMA10_X_COUNT() bfin_read32(DMA10_XCNT)
+#define bfin_write_DMA10_X_COUNT(val) bfin_write32(DMA10_XCNT, val)
+#define bfin_read_DMA10_X_MODIFY() bfin_read32(DMA10_XMOD)
+#define bfin_write_DMA10_X_MODIFY(val) bfin_write32(DMA10_XMOD, val)
+#define bfin_read_DMA10_Y_COUNT() bfin_read32(DMA10_YCNT)
+#define bfin_write_DMA10_Y_COUNT(val) bfin_write32(DMA10_YCNT, val)
+#define bfin_read_DMA10_Y_MODIFY() bfin_read32(DMA10_YMOD)
+#define bfin_write_DMA10_Y_MODIFY(val) bfin_write32(DMA10_YMOD, val)
+#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_DSCPTR_CUR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_DSCPTR_CUR, val)
+#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_ADDR_CUR)
+#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_ADDR_CUR, val)
+#define bfin_read_DMA10_IRQ_STATUS() bfin_read32(DMA10_STAT)
+#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write32(DMA10_STAT, val)
+#define bfin_read_DMA10_CURR_X_COUNT() bfin_read32(DMA10_XCNT_CUR)
+#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write32(DMA10_XCNT_CUR, val)
+#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read32(DMA10_YCNT_CUR)
+#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write32(DMA10_YCNT_CUR, val)
+
+#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_CTL() bfin_read32(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val) bfin_write32(WDOG_CTL, val)
+#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
+#define bfin_read_SPI_BAUD() bfin_read32(SPI0_CLK)
+#define bfin_write_SPI_BAUD(val) bfin_write32(SPI0_CLK, val)
+
+#define bfin_read_PORTD_FER() bfin_read32(PORTD_FER)
+#define bfin_write_PORTD_FER_SET(val) bfin_write32(PORTD_FER_SET, val)
+#define bfin_write_PORTD_FER_CLR(val) bfin_write32(PORTD_FER_CLR, val)
+#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
+#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
+#define bfin_read_PORTG_FER() bfin_read32(PORTG_FER)
+#define bfin_write_PORTG_FER_SET(val) bfin_write32(PORTG_FER_SET, val)
+#define bfin_write_PORTG_FER_CLR(val) bfin_write32(PORTG_FER_CLR, val)
+#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
+
+#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
+#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
+#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
+#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
+#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
+#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
+#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
+#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
+#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
+#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
+#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
+#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
+#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
+#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
+#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
+#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
+#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
+#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
+#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
+#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
+#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
+#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
+#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
+#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
+#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
+#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
+#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
+#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
+#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
+#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
+#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
+#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
+#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
+#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
+#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
+#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
+#define bfin_read_RSI_BLKSZ() bfin_read16(RSI_BLKSZ)
+#define bfin_write_RSI_BLKSZ(val) bfin_write16(RSI_BLKSZ, val)
+#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
+#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
+#define bfin_read_RSI_ESTAT() bfin_read32(RSI_ESTAT)
+#define bfin_write_RSI_ESTAT(val) bfin_write32(RSI_ESTAT, val)
+#define bfin_read_RSI_EMASK() bfin_read32(RSI_EMASK)
+#define bfin_write_RSI_EMASK(val) bfin_write32(RSI_EMASK, val)
+#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
+#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
+#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
+#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
+#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
+#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
+#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
+#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
+#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
+#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
+#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
+#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF609_proc__ */
--- /dev/null
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF609_proc__
+#define __BFIN_DEF_ADSP_BF609_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */
+#define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */
+#define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */
+#define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */
+#define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */
+#define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */
+#define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */
+#define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */
+#define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */
+#define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */
+#define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */
+#define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */
+#define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */
+#define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */
+#define RSI_IMSK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */
+#define RSI_IMSK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */
+#define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */
+#define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 contains bit to dis CCS gen */
+#define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */
+#define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Ack Timeout Register */
+#define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */
+#define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */
+#define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */
+#define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */
+#define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */
+#define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */
+#define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */
+#define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Id Register */
+#define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Id Register */
+#define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Id Register */
+#define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Id Register */
+
+#define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */
+#define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */
+
+#define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */
+#define UART0_CTL 0xFFC02004 /* UART0 Control Register */
+#define UART0_STAT 0xFFC02008 /* UART0 Status Register */
+#define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */
+#define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */
+#define UART0_IMSK 0xFFC02014 /* UART0 Interrupt Mask Register */
+#define UART0_IMSK_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */
+#define UART0_IMSK_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */
+#define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */
+#define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */
+#define UART0_TAIP 0xFFC02028 /* UART0 TX Address/Insert Pulse Reg */
+#define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */
+#define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */
+#define UART0_TXCNT 0xFFC02034 /* UART0 Transmit Counter Register */
+#define UART0_RXCNT 0xFFC02038 /* UART0 Receive Counter Register */
+#define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */
+#define UART1_CTL 0xFFC02404 /* UART1 Control Register */
+#define UART1_STAT 0xFFC02408 /* UART1 Status Register */
+#define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */
+#define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */
+#define UART1_IMSK 0xFFC02414 /* UART1 Interrupt Mask Register */
+#define UART1_IMSK_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */
+#define UART1_IMSK_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */
+#define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */
+#define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */
+#define UART1_TAIP 0xFFC02428 /* UART1 TX Address/Insert Pulse Reg */
+#define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */
+#define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */
+#define UART1_TXCNT 0xFFC02434 /* UART1 Transmit Counter Register */
+#define UART1_RXCNT 0xFFC02438 /* UART1 Receive Counter Register */
+
+#define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable */
+#define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set */
+#define PORTA_FER_CLR 0xFFC03008 /* PORTA Port x Function Enable Clear */
+#define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control */
+#define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable */
+#define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set */
+#define PORTB_FER_CLR 0xFFC03088 /* PORTB Port x Function Enable Clear */
+#define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control */
+#define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable */
+#define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set */
+#define PORTC_FER_CLR 0xFFC03108 /* PORTC Port x Function Enable Clear */
+#define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control */
+#define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable */
+#define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set */
+#define PORTD_FER_CLR 0xFFC03188 /* PORTD Port x Function Enable Clear */
+#define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control */
+#define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable */
+#define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set */
+#define PORTE_FER_CLR 0xFFC03208 /* PORTE Port x Function Enable Clear */
+#define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control */
+#define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable */
+#define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set */
+#define PORTF_FER_CLR 0xFFC03288 /* PORTF Port x Function Enable Clear */
+#define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control */
+#define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable */
+#define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set */
+#define PORTG_FER_CLR 0xFFC03308 /* PORTG Port x Function Enable Clear */
+#define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control */
+
+#define SMC_GCTL 0xFFC16004 /* SMC Control Register */
+#define SMC_GSTAT 0xFFC16008 /* SMC Status Register */
+#define SMC_B0CTL 0xFFC1600C /* SMC Bank0 Control Register */
+#define SMC_B0TIM 0xFFC16010 /* SMC Bank0 Timing Register */
+#define SMC_B0ETIM 0xFFC16014 /* SMC Bank0 Extended Timing Register */
+#define SMC_B1CTL 0xFFC1601C /* SMC BANK1 Control Register */
+#define SMC_B1TIM 0xFFC16020 /* SMC BANK1 Timing Register */
+#define SMC_B1ETIM 0xFFC16024 /* SMC BANK1 Extended Timing Register */
+#define SMC_B2CTL 0xFFC1602C /* SMC BANK2 Control Register */
+#define SMC_B2TIM 0xFFC16030 /* SMC BANK2 Timing Register */
+#define SMC_B2ETIM 0xFFC16034 /* SMC BANK2 Extended Timing Register */
+#define SMC_B3CTL 0xFFC1603C /* SMC BANK3 Control Register */
+#define SMC_B3TIM 0xFFC16040 /* SMC BANK3 Timing Register */
+#define SMC_B3ETIM 0xFFC16044 /* SMC BANK3 Extended Timing Register */
+
+#define WDOG_CTL 0xFFC17000 /* WDOG0 Control Register */
+#define WDOG_CNT 0xFFC17004 /* WDOG0 Count Register */
+#define WDOG_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */
+#define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */
+#define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */
+#define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */
+
+#define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */
+#define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */
+
+#define DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Desc */
+#define DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buf */
+#define DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */
+#define DMA10_XCNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
+#define DMA10_XMOD 0xFFC05010 /* DMA10 Inner Loop Address Increment */
+#define DMA10_YCNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value */
+#define DMA10_YMOD 0xFFC05018 /* DMA10 Outer Loop Address Increment */
+#define DMA10_DSCPTR_CUR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
+#define DMA10_DSCPTR_PRV 0xFFC05028 /* DMA10 Previous Initial Desc Pointer */
+#define DMA10_ADDR_CUR 0xFFC0502C /* DMA10 Current Address */
+#define DMA10_STAT 0xFFC05030 /* DMA10 Status Register */
+#define DMA10_XCNT_CUR 0xFFC05034 /* DMA10 Curr Count(1D) or intra-row(2D)*/
+#define DMA10_YCNT_CUR 0xFFC05038 /* DMA10 Curr Row Count (2D only) */
+#define DMA10_BWLCNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
+#define DMA10_BWLCNT_CUR 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
+#define DMA10_BWMCNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
+#define DMA10_BWMCNT_CUR 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current*/
+
+#define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT
+#define DMA21_DSCPTR_NXT 0xFFC09000 /* DMA21 Pointer to Next Initial Desc */
+#define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT
+#define DMA22_DSCPTR_NXT 0xFFC09080 /* DMA22 Pointer to Next Initial Desc */
+
+#define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */
+#define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */
+#define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */
+#define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */
+#define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */
+#define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */
+#define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */
+#define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */
+#define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */
+#define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */
+#define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */
+#define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */
+#define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */
+#define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */
+#define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */
+#define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */
+#define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */
+
+#define SEC0_CCTL0 0xFFCA4400 /* SEC0 Core Control Register n */
+#define SEC0_CCTL1 0xFFCA4440 /* SEC0 Core Control Register n */
+#define SEC0_FCTL 0xFFCA4010 /* SEC0 Fault Control Register */
+#define SEC0_GCTL 0xFFCA4000 /* SEC0 Global Control Register */
+#define SEC0_SCTL0 0xFFCA4800 /* SEC0 IRQ Source Control Register n */
+
+#define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */
+#define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */
+#define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */
+#define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */
+#define RCU0_SIDIS 0xFFCA6010 /* RCU0 Sys Interface Disable Register */
+#define RCU0_SISTAT 0xFFCA6014 /* RCU0 Sys Interface Status Register */
+#define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */
+#define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */
+#define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */
+#define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */
+
+#define CGU_CTL 0xFFCA8000 /* CGU0 Control Register */
+#define CGU_STAT 0xFFCA8004 /* CGU0 Status Register */
+#define CGU_DIV 0xFFCA8008 /* CGU0 Divisor Register */
+#define CGU_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */
+
+#define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */
+#define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */
+#define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable */
+#define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable */
+#define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status */
+#define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Stat Sticky */
+#define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable */
+#define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */
+#define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */
+#define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */
+#define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */
+#define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */
+#define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */
+#define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */
+#define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */
+#define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */
+#define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */
+#define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */
+#define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */
+#define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */
+#define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */
+#define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */
+#define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */
+#define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */
+#define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */
+#define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */
+#define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */
+#define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */
+
+#define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode*/
+#define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */
+#define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */
+#define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */
+#define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */
+
+
+#define CHIPID 0xffc00014
+/* CHIPID Masks */
+#define CHIPID_VERSION 0xF0000000
+#define CHIPID_FAMILY 0x0FFFF000
+#define CHIPID_MANUFACTURE 0x00000FFE
+
+#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000->0xFF803FFF Data Bank A SRAM */
+#define L1_DATA_A_SRAM_SIZE 0x8000
+#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
+#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000->0xFF903FFF Data Bank B SRAM */
+#define L1_DATA_B_SRAM_SIZE 0x4000
+#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
+
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000->0xFFA07FFF Inst Bank A SRAM */
+#define L1_INST_SRAM_SIZE 0x8000
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF609_proc__ */
--- /dev/null
+/*
+ * Copyright 2004-2012 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
+ */
+
+/* This file should be up to date with:
+ * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
+ */
+
+#if __SILICON_REVISION__ < 0
+# error will not work on BF609 silicon version
+#endif
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
+#define ANOMALY_16000003 (1)
+/* The EPPI Data Enable (DEN) Signal is Not Functional */
+#define ANOMALY_16000004 (1)
+/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
+#define ANOMALY_16000005 (1)
+/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
+#define ANOMALY_16000006 (1)
+/* DDR2 Memory Reads May Fail Intermittently */
+#define ANOMALY_16000007 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
+#define ANOMALY_16000008 (1)
+/* TestSET Instruction Cannot Be Interrupted */
+#define ANOMALY_16000009 (1)
+/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
+#define ANOMALY_16000010 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_16000011 (1)
+/* Speculative Fetches of Indirect-Pointer Inst Can Cause False Hw Errors */
+#define ANOMALY_16000012 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_16000013 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_16000014 (1)
+/* Multi-Issue Inst with dsp32shiftimm in slot1 and P in slot2 Not Supported */
+#define ANOMALY_16000015 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_16000017 (1)
+/* RSI Boot Cleanup Routine Does Not Clear Registers */
+#define ANOMALY_16000018 (1)
+/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
+#define ANOMALY_16000019 (1)
+/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
+#define ANOMALY_16000020 (1)
+/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hb/Wk Sequence */
+#define ANOMALY_16000021 (1)
+/* Boot Code Fails to Enable Parity Fault Detection */
+#define ANOMALY_16000022 (1)
+/* USB DMA interrupt status do not show the DMA channel intr in the DMA ISR */
+#define ANOMALY_16000027 (1)
+/* Interrupted Core Reads of MMRs May Cause Data Loss */
+#define ANOMALY_16000030 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000189 (0)
+#define ANOMALY_05000198 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000244 (0)
+#define ANOMALY_05000261 (0)
+#define ANOMALY_05000263 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
+#define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000311 (0)
+#define ANOMALY_05000312 (0)
+#define ANOMALY_05000323 (0)
+#define ANOMALY_05000353 (1)
+#define ANOMALY_05000363 (0)
+#define ANOMALY_05000386 (0)
+#define ANOMALY_05000480 (0)
+#define ANOMALY_05000481 (1)
+
+/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
+#define ANOMALY_05000491 ANOMALY_16000008
+#define ANOMALY_05000477 ANOMALY_16000009
+#define ANOMALY_05000443 ANOMALY_16000010
+#define ANOMALY_05000461 ANOMALY_16000011
+#define ANOMALY_05000426 ANOMALY_16000012
+#define ANOMALY_05000310 ANOMALY_16000013
+#define ANOMALY_05000245 ANOMALY_16000014
+#define ANOMALY_05000074 ANOMALY_16000015
+#define ANOMALY_05000416 ANOMALY_16000017
+
+
+#endif
--- /dev/null
+#include "gpio.h"
+#include "portmux.h"
+#include "ports.h"
+
+#define CONFIG_BF60x 1 /* Linux glue */
--- /dev/null
+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 112
+
+#define GPIO_PA0 0
+#define GPIO_PA1 1
+#define GPIO_PA2 2
+#define GPIO_PA3 3
+#define GPIO_PA4 4
+#define GPIO_PA5 5
+#define GPIO_PA6 6
+#define GPIO_PA7 7
+#define GPIO_PA8 8
+#define GPIO_PA9 9
+#define GPIO_PA10 10
+#define GPIO_PA11 11
+#define GPIO_PA12 12
+#define GPIO_PA13 13
+#define GPIO_PA14 14
+#define GPIO_PA15 15
+#define GPIO_PB0 16
+#define GPIO_PB1 17
+#define GPIO_PB2 18
+#define GPIO_PB3 19
+#define GPIO_PB4 20
+#define GPIO_PB5 21
+#define GPIO_PB6 22
+#define GPIO_PB7 23
+#define GPIO_PB8 24
+#define GPIO_PB9 25
+#define GPIO_PB10 26
+#define GPIO_PB11 27
+#define GPIO_PB12 28
+#define GPIO_PB13 29
+#define GPIO_PB14 30
+#define GPIO_PB15 31
+#define GPIO_PC0 32
+#define GPIO_PC1 33
+#define GPIO_PC2 34
+#define GPIO_PC3 35
+#define GPIO_PC4 36
+#define GPIO_PC5 37
+#define GPIO_PC6 38
+#define GPIO_PC7 39
+#define GPIO_PC8 40
+#define GPIO_PC9 41
+#define GPIO_PC10 42
+#define GPIO_PC11 43
+#define GPIO_PC12 44
+#define GPIO_PC13 45
+#define GPIO_PC14 46
+#define GPIO_PC15 47
+#define GPIO_PD0 48
+#define GPIO_PD1 49
+#define GPIO_PD2 50
+#define GPIO_PD3 51
+#define GPIO_PD4 52
+#define GPIO_PD5 53
+#define GPIO_PD6 54
+#define GPIO_PD7 55
+#define GPIO_PD8 56
+#define GPIO_PD9 57
+#define GPIO_PD10 58
+#define GPIO_PD11 59
+#define GPIO_PD12 60
+#define GPIO_PD13 61
+#define GPIO_PD14 62
+#define GPIO_PD15 63
+#define GPIO_PE0 64
+#define GPIO_PE1 65
+#define GPIO_PE2 66
+#define GPIO_PE3 67
+#define GPIO_PE4 68
+#define GPIO_PE5 69
+#define GPIO_PE6 70
+#define GPIO_PE7 71
+#define GPIO_PE8 72
+#define GPIO_PE9 73
+#define GPIO_PE10 74
+#define GPIO_PE11 75
+#define GPIO_PE12 76
+#define GPIO_PE13 77
+#define GPIO_PE14 78
+#define GPIO_PE15 79
+#define GPIO_PF0 80
+#define GPIO_PF1 81
+#define GPIO_PF2 82
+#define GPIO_PF3 83
+#define GPIO_PF4 84
+#define GPIO_PF5 85
+#define GPIO_PF6 86
+#define GPIO_PF7 87
+#define GPIO_PF8 88
+#define GPIO_PF9 89
+#define GPIO_PF10 90
+#define GPIO_PF11 91
+#define GPIO_PF12 92
+#define GPIO_PF13 93
+#define GPIO_PF14 94
+#define GPIO_PF15 95
+#define GPIO_PG0 96
+#define GPIO_PG1 97
+#define GPIO_PG2 98
+#define GPIO_PG3 99
+#define GPIO_PG4 100
+#define GPIO_PG5 101
+#define GPIO_PG6 102
+#define GPIO_PG7 103
+#define GPIO_PG8 104
+#define GPIO_PG9 105
+#define GPIO_PG10 106
+#define GPIO_PG11 107
+#define GPIO_PG12 108
+#define GPIO_PG13 109
+#define GPIO_PG14 110
+#define GPIO_PG15 111
+
+#ifndef __ASSEMBLY__
+
+struct gpio_port_t {
+ unsigned long port_fer;
+ unsigned long port_fer_set;
+ unsigned long port_fer_clear;
+ unsigned long data;
+ unsigned long data_set;
+ unsigned long data_clear;
+ unsigned long dir;
+ unsigned long dir_set;
+ unsigned long dir_clear;
+ unsigned long inen;
+ unsigned long inen_set;
+ unsigned long inen_clear;
+ unsigned long port_mux;
+ unsigned long toggle;
+ unsigned long polar;
+ unsigned long polar_set;
+ unsigned long polar_clear;
+ unsigned long lock;
+ unsigned long spare;
+ unsigned long revid;
+};
+
+#endif
+
+#endif /* _MACH_GPIO_H_ */
--- /dev/null
+/*
+ * Copyright 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_PORTMUX_H_
+#define _MACH_PORTMUX_H_
+
+#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
+
+/* EMAC RMII Port Mux */
+#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
+#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
+#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
+#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
+#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
+#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
+#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
+#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
+#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
+#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
+#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
+
+#define P_RMII0 {\
+ P_MII0_ETxD0, \
+ P_MII0_ETxD1, \
+ P_MII0_ETxEN, \
+ P_MII0_ERxD0, \
+ P_MII0_ERxD1, \
+ P_MII0_ERxER, \
+ P_MII0_TxCLK, \
+ P_MII0_PHYINT, \
+ P_MII0_CRS, \
+ P_MII0_MDC, \
+ P_PTP0_PPS, \
+ P_PTP1_PPS, \
+ P_MII0_MDIO, 0}
+
+#define P_MII1_MDC (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
+#define P_MII1_MDIO (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
+#define P_MII1_ETxD0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
+#define P_MII1_ERxD0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
+#define P_MII1_ETxD1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
+#define P_MII1_ERxD1 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
+#define P_MII1_ETxEN (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
+#define P_MII1_PHYINT (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
+#define P_MII1_CRS (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
+#define P_MII1_ERxER (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
+#define P_MII1_TxCLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
+
+#define P_RMII1 {\
+ P_MII1_ETxD0, \
+ P_MII1_ETxD1, \
+ P_MII1_ETxEN, \
+ P_MII1_ERxD0, \
+ P_MII1_ERxD1, \
+ P_MII1_ERxER, \
+ P_MII1_TxCLK, \
+ P_MII1_PHYINT, \
+ P_MII1_CRS, \
+ P_MII1_MDC, \
+ P_MII1_MDIO, 0}
+
+/* PPI Port Mux */
+#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
+#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
+#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
+#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
+#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
+#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
+#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
+#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
+#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
+#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
+#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
+#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
+#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
+#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
+#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
+#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
+#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
+#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
+#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
+#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
+#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
+#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
+#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
+#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
+#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(1))
+#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(1))
+#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
+#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
+
+#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(1))
+#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
+#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(1))
+#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(1))
+#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(1))
+#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
+#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(1))
+#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(1))
+#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(1))
+#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(1))
+#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(1))
+#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(1))
+#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(1))
+#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(1))
+#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(1))
+#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(1))
+#define P_PPI1_D16 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
+#define P_PPI1_D17 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
+#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(1))
+#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(1))
+#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
+#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(1))
+
+#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(1))
+#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
+#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(1))
+#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(1))
+#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(1))
+#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
+#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(1))
+#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(1))
+#define P_PPI2_D8 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(1))
+#define P_PPI2_D9 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
+#define P_PPI2_D10 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(1))
+#define P_PPI2_D11 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(1))
+#define P_PPI2_D12 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(1))
+#define P_PPI2_D13 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
+#define P_PPI2_D14 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(1))
+#define P_PPI2_D15 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(1))
+#define P_PPI2_D16 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(1))
+#define P_PPI2_D17 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
+#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(1))
+#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(1))
+#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(1))
+#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(1))
+
+/* SPI Port Mux */
+#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
+#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
+#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
+#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
+#define P_SPI0_RDY (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
+#define P_SPI0_D2 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
+#define P_SPI0_D3 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
+
+#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
+#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
+#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
+#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PC15) | P_FUNCT(0))
+#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
+#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
+#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
+
+#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
+#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
+#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
+#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
+#define P_SPI1_RDY (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
+#define P_SPI1_D2 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
+#define P_SPI1_D3 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
+
+#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
+#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
+#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
+#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
+#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
+#define P_SPI1_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
+#define P_SPI1_SSEL7 (P_DEFINED | P_IDENT(GPIO_PC14) | P_FUNCT(0))
+
+#define GPIO_DEFAULT_BOOT_SPI_CS
+#define P_DEFAULT_BOOT_SPI_CS
+
+/* UART Port Mux */
+#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
+#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
+#define P_UART0_RTS (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
+#define P_UART0_CTS (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
+
+#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
+#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
+#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
+#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
+
+/* Timer */
+#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(3))
+#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(2))
+#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
+#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
+#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
+#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
+#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
+#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
+#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
+
+/* RSI */
+#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
+#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
+#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
+#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(2))
+#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(2))
+#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(2))
+#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(2))
+#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(2))
+#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
+#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
+
+/* PTP */
+#define P_PTP0_PPS (P_DEFINED | P_IDENT(GPIO_PB15) | P_FUNCT(0))
+#define P_PTP0_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP0_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+
+#define P_PTP1_PPS (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
+#define P_PTP1_CLKIN (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(2))
+#define P_PTP1_AUXIN (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(2))
+
+/* SMC Port Mux */
+#define P_A3 (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
+#define P_A4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
+#define P_A5 (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
+#define P_A6 (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
+#define P_A7 (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
+#define P_A8 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
+#define P_A9 (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
+#define P_A10 (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
+#define P_A11 (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
+#define P_A12 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
+#define P_A13 (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
+#define P_A14 (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
+#define P_A15 (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
+#define P_A16 (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
+#define P_A17 (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
+#define P_A18 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
+#define P_A19 (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
+#define P_A20 (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
+#define P_A21 (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
+#define P_A22 (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
+#define P_A23 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
+#define P_A24 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
+#define P_A25 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
+#define P_NORCK (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
+
+#define P_AMS1 (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
+#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
+#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
+
+#define P_ABE0 (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(1))
+#define P_ABE1 (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(1))
+
+/* CAN */
+#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
+#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
+
+#endif /* _MACH_PORTMUX_H_ */
--- /dev/null
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+/* PORTx_MUX Masks */
+#define PORT_x_MUX_0_MASK 0x00000003
+#define PORT_x_MUX_1_MASK 0x0000000C
+#define PORT_x_MUX_2_MASK 0x00000030
+#define PORT_x_MUX_3_MASK 0x000000C0
+#define PORT_x_MUX_4_MASK 0x00000300
+#define PORT_x_MUX_5_MASK 0x00000C00
+#define PORT_x_MUX_6_MASK 0x00003000
+#define PORT_x_MUX_7_MASK 0x0000C000
+#define PORT_x_MUX_8_MASK 0x00030000
+#define PORT_x_MUX_9_MASK 0x000C0000
+#define PORT_x_MUX_10_MASK 0x00300000
+#define PORT_x_MUX_11_MASK 0x00C00000
+#define PORT_x_MUX_12_MASK 0x03000000
+#define PORT_x_MUX_13_MASK 0x0C000000
+#define PORT_x_MUX_14_MASK 0x30000000
+#define PORT_x_MUX_15_MASK 0xC0000000
+
+#define PORT_x_MUX_FUNC_1 (0x0)
+#define PORT_x_MUX_FUNC_2 (0x1)
+#define PORT_x_MUX_FUNC_3 (0x2)
+#define PORT_x_MUX_FUNC_4 (0x3)
+#define PORT_x_MUX_0_FUNC_1 (PORT_x_MUX_FUNC_1 << 0)
+#define PORT_x_MUX_0_FUNC_2 (PORT_x_MUX_FUNC_2 << 0)
+#define PORT_x_MUX_0_FUNC_3 (PORT_x_MUX_FUNC_3 << 0)
+#define PORT_x_MUX_0_FUNC_4 (PORT_x_MUX_FUNC_4 << 0)
+#define PORT_x_MUX_1_FUNC_1 (PORT_x_MUX_FUNC_1 << 2)
+#define PORT_x_MUX_1_FUNC_2 (PORT_x_MUX_FUNC_2 << 2)
+#define PORT_x_MUX_1_FUNC_3 (PORT_x_MUX_FUNC_3 << 2)
+#define PORT_x_MUX_1_FUNC_4 (PORT_x_MUX_FUNC_4 << 2)
+#define PORT_x_MUX_2_FUNC_1 (PORT_x_MUX_FUNC_1 << 4)
+#define PORT_x_MUX_2_FUNC_2 (PORT_x_MUX_FUNC_2 << 4)
+#define PORT_x_MUX_2_FUNC_3 (PORT_x_MUX_FUNC_3 << 4)
+#define PORT_x_MUX_2_FUNC_4 (PORT_x_MUX_FUNC_4 << 4)
+#define PORT_x_MUX_3_FUNC_1 (PORT_x_MUX_FUNC_1 << 6)
+#define PORT_x_MUX_3_FUNC_2 (PORT_x_MUX_FUNC_2 << 6)
+#define PORT_x_MUX_3_FUNC_3 (PORT_x_MUX_FUNC_3 << 6)
+#define PORT_x_MUX_3_FUNC_4 (PORT_x_MUX_FUNC_4 << 6)
+#define PORT_x_MUX_4_FUNC_1 (PORT_x_MUX_FUNC_1 << 8)
+#define PORT_x_MUX_4_FUNC_2 (PORT_x_MUX_FUNC_2 << 8)
+#define PORT_x_MUX_4_FUNC_3 (PORT_x_MUX_FUNC_3 << 8)
+#define PORT_x_MUX_4_FUNC_4 (PORT_x_MUX_FUNC_4 << 8)
+#define PORT_x_MUX_5_FUNC_1 (PORT_x_MUX_FUNC_1 << 10)
+#define PORT_x_MUX_5_FUNC_2 (PORT_x_MUX_FUNC_2 << 10)
+#define PORT_x_MUX_5_FUNC_3 (PORT_x_MUX_FUNC_3 << 10)
+#define PORT_x_MUX_5_FUNC_4 (PORT_x_MUX_FUNC_4 << 10)
+#define PORT_x_MUX_6_FUNC_1 (PORT_x_MUX_FUNC_1 << 12)
+#define PORT_x_MUX_6_FUNC_2 (PORT_x_MUX_FUNC_2 << 12)
+#define PORT_x_MUX_6_FUNC_3 (PORT_x_MUX_FUNC_3 << 12)
+#define PORT_x_MUX_6_FUNC_4 (PORT_x_MUX_FUNC_4 << 12)
+#define PORT_x_MUX_7_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
+#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
+#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
+#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
+#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
+#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
+#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
+#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
+#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
+#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
+#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
+#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
+#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
+#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
+#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
+#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
+#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
+#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
+#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
+#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
+#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
+#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
+#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
+#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
+#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
+#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
+#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
+#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
+#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
+#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
+#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
+#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
+#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
+#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
+#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
+#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
+
+#include "../mach-common/bits/ports-a.h"
+#include "../mach-common/bits/ports-b.h"
+#include "../mach-common/bits/ports-c.h"
+#include "../mach-common/bits/ports-d.h"
+#include "../mach-common/bits/ports-e.h"
+#include "../mach-common/bits/ports-f.h"
+#include "../mach-common/bits/ports-g.h"
+
+#endif
--- /dev/null
+/*
+ * CGU Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_CGU__
+#define __BFIN_PERIPHERAL_CGU__
+
+/* CGU_CTL Masks */
+#define DF (1 << 0)
+#define MSEL (0x7f << MSEL_P)
+#define WIDLE (1 << WIDLE_P)
+#define LOCK (1 << LOCK_P)
+
+#define DF_P 0
+#define MSEL_P 8
+#define WIDLE_P 30
+#define LOCK_P 31
+#define MSEL_MASK 0x7F00
+#define DF_MASK 0x1
+
+/* CGU_STAT Masks */
+#define PLLEN (1 << 0)
+#define PLLBP (1 << 1)
+#define PLLLK (1 << 2)
+#define CLKSALGN (1 << 3)
+#define CCBF0EN (1 << 4)
+#define CCBF1EN (1 << 5)
+#define SCBF0EN (1 << 6)
+#define SCBF1EN (1 << 7)
+#define DCBFEN (1 << 8)
+#define OCBFEN (1 << 9)
+#define ADRERR (1 << 16)
+#define LWERR (1 << 17)
+#define DIVERR (1 << 18)
+#define WDFMSERR (1 << 19)
+#define WDIVERR (1 << 20)
+#define PLLLKERR (1 << 21)
+
+/* CGU_DIV Masks */
+#define CSEL (0x1f << CSEL_P)
+#define S0SEL (3 << S0SEL_P)
+#define SYSSEL (0x1f << SYSSEL_P)
+#define S1SEL (3 << S1SEL_P)
+#define DSEL (0x1f << DSEL_P)
+#define OSEL (0x7f << OSEL_P)
+#define ALGN (1 << ALGN_P)
+#define UPDT (1 << UPDT_P)
+#define LOCK (1 << LOCK_P)
+
+#define CSEL_P 0
+#define S0SEL_P 5
+#define SYSSEL_P 8
+#define S1SEL_P 13
+#define DSEL_P 16
+#define OSEL_P 22
+#define ALGN_P 29
+#define UPDT_P 30
+#define LOCK_P 31
+
+/* CGU_CLKOUTSEL Masks */
+#define CLKOUTSEL (0xf << 0)
+#define USBCLKSEL (0x3f << 16)
+#define LOCK (1 << LOCK_P)
+
+#define LOCK_P 31
+
+#define CLKOUTSEL_CLKIN 0x0
+#define CLKOUTSEL_CCLK 0x1
+#define CLKOUTSEL_SYSCLK 0x2
+#define CLKOUTSEL_SCLK0 0x3
+#define CLKOUTSEL_SCLK1 0x4
+#define CLKOUTSEL_DCLK 0x5
+#define CLKOUTSEL_USB_PLL 0x6
+#define CLKOUTSEL_OUTCLK 0x7
+#define CLKOUTSEL_USB_CLKIN 0x8
+#define CLKOUTSEL_WDOG 0x9
+#define CLKOUTSEL_PMON 0xA
+#define CLKOUTSEL_GND 0xB
+
+#endif
--- /dev/null
+/*
+ * Distributed DMA Engine (DDE) Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_DDE__
+#define __BFIN_PERIPHERAL_DDE__
+
+/* DMA_CONFIG Masks */
+#define DMAEN (1 << DMAEN_P) /* DMA Channel Enable */
+#define WNR (1 << WNR_P) /* Channel Direction (W/R*) */
+#define SYNC (1 << SYNC_P) /* Sync Work Unit Transitions */
+#define CADDR (1 << CADDR_P) /* Use Current Address */
+#define PSIZE (7 << PSIZE_P) /* Peripheral Word Size */
+#define PSIZE_1 (0 << PSIZE_P)
+#define PSIZE_2 (1 << PSIZE_P)
+#define PSIZE_4 (2 << PSIZE_P)
+#define PSIZE_8 (3 << PSIZE_P)
+#define MSIZE (7 << MSIZE_P) /* Memory Transfer Size */
+#define MSIZE_1 (0 << MSIZE_P)
+#define MSIZE_2 (1 << MSIZE_P)
+#define MSIZE_4 (2 << MSIZE_P)
+#define MSIZE_8 (3 << MSIZE_P)
+#define MSIZE_16 (4 << MSIZE_P)
+#define MSIZE_32 (5 << MSIZE_P)
+#define FLOW (7 << FLOW_P) /* Next Operation */
+#define FLOW_STOP (0 << FLOW_P) /* Stop Mode */
+#define FLOW_AUTO (1 << FLOW_P) /* Autobuffer Mode */
+#define FLOW_DSCL (4 << FLOW_P) /* Descriptor List */
+#define FLOW_DSCA (5 << FLOW_P) /* Descriptor Array */
+#define FLOW_DSDL (6 << FLOW_P) /* Descriptor On Demand List */
+#define FLOW_DSDA (7 << FLOW_P) /* Descriptor On Demand Array */
+#define NDSIZE (7 << NDSIZE_P) /* Next Descriptor Set Size */
+#define NDSIZE_1 (0 << NDSIZE_P)
+#define NDSIZE_2 (1 << NDSIZE_P)
+#define NDSIZE_3 (2 << NDSIZE_P)
+#define NDSIZE_4 (3 << NDSIZE_P)
+#define NDSIZE_5 (4 << NDSIZE_P)
+#define NDSIZE_6 (5 << NDSIZE_P)
+#define NDSIZE_7 (6 << NDSIZE_P)
+#define DI_EN_X (1 << INT_P)
+#define DI_EN_Y (2 << INT_P)
+#define DI_EN_P (3 << INT_P)
+#define DI_EN (DI_EN_X)
+#define DI_XCOUNT_EN (1 << INT_P) /* xcount expires interrupt */
+#define TRIG (3 << TRIG_P) /* Generate Trigger */
+#define TOVEN (1 << TOVEN_P)
+#define DESCIDCPY (1 << DESCIDCPY_P)
+#define TWOD (1 << TWOD_P)
+#define PDRF (1 << PDRF_P)
+
+#define DMAEN_P 0
+#define WNR_P 1
+#define SYNC_P 2
+#define CADDR_P 3
+#define PSIZE_P 4
+#define MSIZE_P 8
+#define FLOW_P 12
+#define TWAIT_P 15
+#define NDSIZE_P 16
+#define INT_P 20
+#define TRIG_P 22
+#define TOVEN_P 24
+#define DESCIDCPY_P 25
+#define TWOD_P 26
+#define PDRF_P 28
+
+/* DMA_STATUS Masks */
+#define DMA_DONE (1 << DMA_DONE_P) /* Work Unit/Row Done */
+#define DMA_ERR (1 << DMA_ERR_P) /* Error Interrupt */
+#define DMA_PIRQ (1 << DMA_PIRQ_P) /* Peri Intr Request */
+#define DMA_ERRC (7 << DMA_ERRC_P) /* Error Cause */
+#define DMA_RUN (7 << DMA_RUN_P) /* Run Status */
+#define DMA_PBWIDTH (3 << DMA_PBWIDTH_P) /* Peri Bus Width */
+#define DMA_MBWIDTH (3 << DMA_MBWIDTH_P) /* Memory Bus Width */
+#define DMA_FIFOFILL (7 << DMA_FIFOFILL_P) /* FIFO Fill Status */
+#define DMA_TWAIT (1 << DMA_TWAIT_P) /* Trigger Wait Stat */
+
+#define DMA_DONE_P 0
+#define DMA_ERR_P 1
+#define DMA_PIRQ_P 2
+#define DMA_ERRC_P 4
+#define DMA_RUN_P 8
+#define DMA_PBWIDTH_P 12
+#define DMA_MBWIDTH_P 14
+#define DMA_FIFOFILL_P 16
+#define DMA_TWAIT_P 20
+
+#endif
#define DMAEN 0x0001 /* DMA Channel Enable */
#define WNR 0x0002 /* Channel Direction (W/R*) */
#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
+
+#ifdef CONFIG_BF60x
+
+#define PSIZE_8 0x00000000 /* Transfer Word Size = 16 */
+#define PSIZE_16 0x00000010 /* Transfer Word Size = 16 */
+#define PSIZE_32 0x00000020 /* Transfer Word Size = 32 */
+#define PSIZE_64 0x00000030 /* Transfer Word Size = 32 */
+#define WDSIZE_16 0x00000100 /* Transfer Word Size = 16 */
+#define WDSIZE_32 0x00000200 /* Transfer Word Size = 32 */
+#define WDSIZE_64 0x00000300 /* Transfer Word Size = 32 */
+#define WDSIZE_128 0x00000400 /* Transfer Word Size = 32 */
+#define WDSIZE_256 0x00000500 /* Transfer Word Size = 32 */
+#define DMA2D 0x04000000 /* DMA Mode (2D/1D*) */
+#define RESTART 0x00000004 /* DMA Buffer Clear SYNC */
+#define DI_EN_X 0x00100000 /* Data Int Enable in X count */
+#define DI_EN_Y 0x00200000 /* Data Int Enable in Y count */
+#define DI_EN_P 0x00300000 /* Data Int Enable in Peri */
+#define DI_EN DI_EN_X /* Data Int Enable */
+#define NDSIZE_0 0x00000000 /* Next Desc Size = 0 */
+#define NDSIZE_1 0x00010000 /* Next Desc Size = 1 */
+#define NDSIZE_2 0x00020000 /* Next Desc Size = 2 */
+#define NDSIZE_3 0x00030000 /* Next Desc Size = 3 */
+#define NDSIZE_4 0x00040000 /* Next Desc Size = 4 */
+#define NDSIZE_5 0x00050000 /* Next Desc Size = 5 */
+#define NDSIZE_6 0x00060000 /* Next Desc Size = 6 */
+#define NDSIZE 0x00070000 /* Next Desc Size */
+#define NDSIZE_OFFSET 16 /* Next Desc Size Offset */
+#define DMAFLOW_LIST 0x00004000 /* Desc List Mode */
+#define DMAFLOW_ARRAY 0x00005000 /* Desc Array Mode */
+#define DMAFLOW_LIST_DEMAND 0x00006000 /* Desc Demand List Mode */
+#define DMAFLOW_ARRAY_DEMAND 0x00007000 /* Desc Demand Array Mode */
+#define DMA_RUN_DFETCH 0x00000100 /* DMA Channel Run (DFETCH) */
+#define DMA_RUN 0x00000200 /* DMA Channel Run */
+#define DMA_RUN_WAIT_TRIG 0x00000300 /* DMA Channel Run (WAIT TRIG)*/
+#define DMA_RUN_WAIT_ACK 0x00000400 /* DMA Channel Run (WAIT ACK) */
+
+#else
+
#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
+#define PSIZE_16 WDSIZE_16
+#define PSIZE_32 WDSIZE_32
#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
#define RESTART 0x0020 /* DMA Buffer Clear */
#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
#define DI_EN 0x0080 /* Data Interrupt Enable */
#define NDSIZE 0x0F00 /* Next Descriptor bitmask */
-#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 */
#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
-#define FLOW_STOP 0x0000 /* Stop Mode */
-#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
#define DMAEN_P 0 /* Channel Enable */
#define WNR_P 1 /* Channel Direction (W/R*) */
+#define WDSIZE_P 2 /* Transfer Word Size */
#define DMA2D_P 4 /* 2D/1D* Mode */
#define RESTART_P 5 /* Restart */
#define DI_SEL_P 6 /* Data Interrupt Select */
#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
+#endif
+#define DMAFLOW 0x7000 /* Flow Control */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+
#define DMA_DONE_P 0 /* DMA Done Indicator */
#define DMA_ERR_P 1 /* DMA Error Indicator */
#define DFETCH_P 2 /* Descriptor Fetch Indicator */
#define DMA_RUN_P 3 /* DMA Running Indicator */
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
-#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
+#define CTYPE 0x0040 /* DMA Channel Type (Mem/Peri) */
+#define CTYPE_P 6 /* DMA Channel Type BIT POSITION */
#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
#endif
#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
-#define PAGE_SIZE_MASK 0x00030000 /* the bits for the page_size field */
+#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
+#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
+#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
+#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
+#define PAGE_SIZE_MASK 0x00070000 /* page_size field mask */
#define PAGE_SIZE_SHIFT 16
#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
+#define MSEL_P 9
+
/* PLL_DIV Masks */
#define SSEL 0x000F /* System Select */
#define CSEL 0x0030 /* Core Select */
#define CCLK_DIV4 CSEL_DIV4
#define CCLK_DIV8 CSEL_DIV8
+#define SSEL_P 0
+#define CSEL_P 4
+
/* PLL_STAT Masks */
#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
#define FULL_ON 0x0002 /* Processor In Full On Mode */
#define CMD_INT_E 0x100 /* Command Interrupt */
#define CMD_PEND_E 0x200 /* Command Pending */
#define CMD_E 0x400 /* Command Enable */
+#ifdef RSI_BLKSZ
+#define CMD_CRC_CHECK_D 0x800 /* CRC Check is disabled */
+#define CMD_DATA0_BUSY 0x1000 /* Check Busy State on DATA0 */
+#endif
/* Bit masks for SDH_PWR_CTL */
+#ifndef RSI_BLKSZ
#define PWR_ON 0x3 /* Power On */
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define ROD_CTL 0x80 /* Rod Control */
+#endif
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define PWR_SV_E 0x200 /* Power Save Enable */
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
-#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
+#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
+#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
+#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
+#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
+#ifdef RSI_BLKSZ
+#define CARD_TYPE_MASK 0xe000 /* Card type mask */
+#define CARD_TYPE_OFFSET 13 /* Card type offset */
+#define CARD_TYPE_SDIO 0
+#define CARD_TYPE_eMMC 1
+#define CARD_TYPE_SD 2
+#define CARD_TYPE_CEATA 3
+#endif
/* Bit masks for SDH_RESP_CMD */
#define RESP_CMD 0x3f /* Response Command */
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+#ifndef RSI_BLKSZ
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+#else
+
+/* Bit masks for SDH_BLK_SIZE */
+#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
+#endif
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define SD_CARD_DET 0x10 /* SD Card Detect */
+#define SD_CARD_BUSYMODE 0x80000000 /* Card is in Busy mode */
+#define SD_CARD_SLPMODE 0x40000000 /* Card in Sleep Mode */
+#define SD_CARD_READY 0x00020000 /* Card Ready */
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
-#define SCD_MSK 0x40 /* Mask Card Detect */
+#define SCD_MSK 0x10 /* Mask Card Detect */
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define SD_RST 0x10 /* SDMMC Reset */
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
+#ifndef RSI_BLKSZ
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
+#else
+#define PWR_ON 0x600 /* Power On */
+#define SD_CMD_OD 0x800 /* Open Drain Output */
+#define BOOT_EN 0x1000 /* Boot Enable */
+#define BOOT_MODE 0x2000 /* Alternate Boot Mode */
+#define BOOT_ACK_EN 0x4000 /* Boot ACK is expected */
+#endif
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
--- /dev/null
+/*
+ * Analog Devices bfin_spi3 controller driver
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _SPI_CHANNEL_H_
+#define _SPI_CHANNEL_H_
+
+#include <linux/types.h>
+
+/* SPI_CONTROL */
+#define SPI_CTL_EN 0x00000001 /* Enable */
+#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
+#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
+#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
+#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
+#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
+#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
+#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in transfers */
+#define SPI_CTL_EMISO 0x00000100 /*Enable MISO */
+#define SPI_CTL_SIZE 0x00000600 /*Word Transfer Size */
+#define SPI_CTL_SIZE08 0x00000000 /*SIZE: 8 bits */
+#define SPI_CTL_SIZE16 0x00000200 /*SIZE: 16 bits */
+#define SPI_CTL_SIZE32 0x00000400 /*SIZE: 32 bits */
+#define SPI_CTL_LSBF 0x00001000 /*LSB First */
+#define SPI_CTL_FCEN 0x00002000 /*Flow-Control Enable */
+#define SPI_CTL_FCCH 0x00004000 /*Flow-Control Channel Selection */
+#define SPI_CTL_FCPL 0x00008000 /*Flow-Control Polarity */
+#define SPI_CTL_FCWM 0x00030000 /*Flow-Control Water-Mark */
+#define SPI_CTL_FIFO0 0x00000000 /*FCWM: Tx empty or Rx Full */
+#define SPI_CTL_FIFO1 0x00010000 /*FCWM: Tx empty or Rx full (>=75%) */
+#define SPI_CTL_FIFO2 0x00020000 /*FCWM: Tx empty or Rx full (>=50%) */
+#define SPI_CTL_FMODE 0x00040000 /*Fast-mode Enable */
+#define SPI_CTL_MIOM 0x00300000 /*Multiple I/O Mode */
+#define SPI_CTL_MIO_DIS 0x00000000 /*MIOM: Disable */
+#define SPI_CTL_MIO_DUAL 0x00100000 /*MIOM: Enable DIOM (Dual I/O Mode) */
+#define SPI_CTL_MIO_QUAD 0x00200000 /*MIOM: Enable QUAD (Quad SPI Mode) */
+#define SPI_CTL_SOSI 0x00400000 /*Start on MOSI */
+/* SPI_RX_CONTROL */
+#define SPI_RXCTL_REN 0x00000001 /*Receive Channel Enable */
+#define SPI_RXCTL_RTI 0x00000004 /*Receive Transfer Initiate */
+#define SPI_RXCTL_RWCEN 0x00000008 /*Receive Word Counter Enable */
+#define SPI_RXCTL_RDR 0x00000070 /*Receive Data Request */
+#define SPI_RXCTL_RDR_DIS 0x00000000 /*RDR: Disabled */
+#define SPI_RXCTL_RDR_NE 0x00000010 /*RDR: RFIFO not empty */
+#define SPI_RXCTL_RDR_25 0x00000020 /*RDR: RFIFO 25% full */
+#define SPI_RXCTL_RDR_50 0x00000030 /*RDR: RFIFO 50% full */
+#define SPI_RXCTL_RDR_75 0x00000040 /*RDR: RFIFO 75% full */
+#define SPI_RXCTL_RDR_FULL 0x00000050 /*RDR: RFIFO full */
+#define SPI_RXCTL_RDO 0x00000100 /*Receive Data Over-Run */
+#define SPI_RXCTL_RRWM 0x00003000 /*FIFO Regular Water-Mark */
+#define SPI_RXCTL_RWM_0 0x00000000 /*RRWM: RFIFO Empty */
+#define SPI_RXCTL_RWM_25 0x00001000 /*RRWM: RFIFO 25% full */
+#define SPI_RXCTL_RWM_50 0x00002000 /*RRWM: RFIFO 50% full */
+#define SPI_RXCTL_RWM_75 0x00003000 /*RRWM: RFIFO 75% full */
+#define SPI_RXCTL_RUWM 0x00070000 /*FIFO Urgent Water-Mark */
+#define SPI_RXCTL_UWM_DIS 0x00000000 /*RUWM: Disabled */
+#define SPI_RXCTL_UWM_25 0x00010000 /*RUWM: RFIFO 25% full */
+#define SPI_RXCTL_UWM_50 0x00020000 /*RUWM: RFIFO 50% full */
+#define SPI_RXCTL_UWM_75 0x00030000 /*RUWM: RFIFO 75% full */
+#define SPI_RXCTL_UWM_FULL 0x00040000 /*RUWM: RFIFO full */
+/* SPI_TX_CONTROL */
+#define SPI_TXCTL_TEN 0x00000001 /*Transmit Channel Enable */
+#define SPI_TXCTL_TTI 0x00000004 /*Transmit Transfer Initiate */
+#define SPI_TXCTL_TWCEN 0x00000008 /*Transmit Word Counter Enable */
+#define SPI_TXCTL_TDR 0x00000070 /*Transmit Data Request */
+#define SPI_TXCTL_TDR_DIS 0x00000000 /*TDR: Disabled */
+#define SPI_TXCTL_TDR_NF 0x00000010 /*TDR: TFIFO not full */
+#define SPI_TXCTL_TDR_25 0x00000020 /*TDR: TFIFO 25% empty */
+#define SPI_TXCTL_TDR_50 0x00000030 /*TDR: TFIFO 50% empty */
+#define SPI_TXCTL_TDR_75 0x00000040 /*TDR: TFIFO 75% empty */
+#define SPI_TXCTL_TDR_EMPTY 0x00000050 /*TDR: TFIFO empty */
+#define SPI_TXCTL_TDU 0x00000100 /*Transmit Data Under-Run */
+#define SPI_TXCTL_TRWM 0x00003000 /*FIFO Regular Water-Mark */
+#define SPI_TXCTL_RWM_FULL 0x00000000 /*TRWM: TFIFO full */
+#define SPI_TXCTL_RWM_25 0x00001000 /*TRWM: TFIFO 25% empty */
+#define SPI_TXCTL_RWM_50 0x00002000 /*TRWM: TFIFO 50% empty */
+#define SPI_TXCTL_RWM_75 0x00003000 /*TRWM: TFIFO 75% empty */
+#define SPI_TXCTL_TUWM 0x00070000 /*FIFO Urgent Water-Mark */
+#define SPI_TXCTL_UWM_DIS 0x00000000 /*TUWM: Disabled */
+#define SPI_TXCTL_UWM_25 0x00010000 /*TUWM: TFIFO 25% empty */
+#define SPI_TXCTL_UWM_50 0x00020000 /*TUWM: TFIFO 50% empty */
+#define SPI_TXCTL_UWM_75 0x00030000 /*TUWM: TFIFO 75% empty */
+#define SPI_TXCTL_UWM_EMPTY 0x00040000 /*TUWM: TFIFO empty */
+/* SPI_CLOCK */
+#define SPI_CLK_BAUD 0x0000FFFF /*Baud Rate */
+/* SPI_DELAY */
+#define SPI_DLY_STOP 0x000000FF /*Transfer delay time */
+#define SPI_DLY_LEADX 0x00000100 /*Extended (1 SCK) LEAD Control */
+#define SPI_DLY_LAGX 0x00000200 /*Extended (1 SCK) LAG control */
+/* SPI_SSEL */
+#define SPI_SLVSEL_SSE1 0x00000002 /*SPISSEL1 Enable */
+#define SPI_SLVSEL_SSE2 0x00000004 /*SPISSEL2 Enable */
+#define SPI_SLVSEL_SSE3 0x00000008 /*SPISSEL3 Enable */
+#define SPI_SLVSEL_SSE4 0x00000010 /*SPISSEL4 Enable */
+#define SPI_SLVSEL_SSE5 0x00000020 /*SPISSEL5 Enable */
+#define SPI_SLVSEL_SSE6 0x00000040 /*SPISSEL6 Enable */
+#define SPI_SLVSEL_SSE7 0x00000080 /*SPISSEL7 Enable */
+#define SPI_SLVSEL_SSEL1 0x00000200 /*SPISSEL1 Value */
+#define SPI_SLVSEL_SSEL2 0x00000400 /*SPISSEL2 Value */
+#define SPI_SLVSEL_SSEL3 0x00000800 /*SPISSEL3 Value */
+#define SPI_SLVSEL_SSEL4 0x00001000 /*SPISSEL4 Value */
+#define SPI_SLVSEL_SSEL5 0x00002000 /*SPISSEL5 Value */
+#define SPI_SLVSEL_SSEL6 0x00004000 /*SPISSEL6 Value */
+#define SPI_SLVSEL_SSEL7 0x00008000 /*SPISSEL7 Value */
+/* SPI_RWC */
+#define SPI_RWC_VALUE 0x0000FFFF /*Received Word-Count */
+/* SPI_RWCR */
+#define SPI_RWCR_VALUE 0x0000FFFF /*Received Word-Count Reload */
+/* SPI_TWC */
+#define SPI_TWC_VALUE 0x0000FFFF /*Transmitted Word-Count */
+/* SPI_TWCR */
+#define SPI_TWCR_VALUE 0x0000FFFF /*Transmitted Word-Count Reload */
+/* SPI_IMASK */
+#define SPI_IMSK_RUWM 0x00000002 /*Receive Water-Mark Interrupt Mask */
+#define SPI_IMSK_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */
+#define SPI_IMSK_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */
+#define SPI_IMSK_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */
+#define SPI_IMSK_TCM 0x00000040 /*Transmit Collision Interrupt Mask */
+#define SPI_IMSK_MFM 0x00000080 /*Mode Fault Interrupt Mask */
+#define SPI_IMSK_RSM 0x00000100 /*Receive Start Interrupt Mask */
+#define SPI_IMSK_TSM 0x00000200 /*Transmit Start Interrupt Mask */
+#define SPI_IMSK_RFM 0x00000400 /*Receive Finish Interrupt Mask */
+#define SPI_IMSK_TFM 0x00000800 /*Transmit Finish Interrupt Mask */
+/* SPI_IMASKCL */
+#define SPI_IMSK_CLR_RUW 0x00000002 /*Receive Water-Mark Interrupt Mask */
+#define SPI_IMSK_CLR_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */
+#define SPI_IMSK_CLR_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */
+#define SPI_IMSK_CLR_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */
+#define SPI_IMSK_CLR_TCM 0x00000040 /*Transmit Collision Interrupt Mask */
+#define SPI_IMSK_CLR_MFM 0x00000080 /*Mode Fault Interrupt Mask */
+#define SPI_IMSK_CLR_RSM 0x00000100 /*Receive Start Interrupt Mask */
+#define SPI_IMSK_CLR_TSM 0x00000200 /*Transmit Start Interrupt Mask */
+#define SPI_IMSK_CLR_RFM 0x00000400 /*Receive Finish Interrupt Mask */
+#define SPI_IMSK_CLR_TFM 0x00000800 /*Transmit Finish Interrupt Mask */
+/* SPI_IMASKST */
+#define SPI_IMSK_SET_RUWM 0x00000002 /*Receive Water-Mark Interrupt Mask */
+#define SPI_IMSK_SET_TUWM 0x00000004 /*Transmit Water-Mark Interrupt Mask */
+#define SPI_IMSK_SET_ROM 0x00000010 /*Receive Over-Run Interrupt Mask */
+#define SPI_IMSK_SET_TUM 0x00000020 /*Transmit Under-Run Interrupt Mask */
+#define SPI_IMSK_SET_TCM 0x00000040 /*Transmit Collision Interrupt Mask */
+#define SPI_IMSK_SET_MFM 0x00000080 /*Mode Fault Interrupt Mask */
+#define SPI_IMSK_SET_RSM 0x00000100 /*Receive Start Interrupt Mask */
+#define SPI_IMSK_SET_TSM 0x00000200 /*Transmit Start Interrupt Mask */
+#define SPI_IMSK_SET_RFM 0x00000400 /*Receive Finish Interrupt Mask */
+#define SPI_IMSK_SET_TFM 0x00000800 /*Transmit Finish Interrupt Mask */
+/* SPI_STATUS */
+#define SPI_STAT_SPIF 0x00000001 /*SPI Finished */
+#define SPI_STAT_RUWM 0x00000002 /*Receive Water-Mark Breached */
+#define SPI_STAT_TUWM 0x00000004 /*Transmit Water-Mark Breached */
+#define SPI_STAT_ROE 0x00000010 /*Receive Over-Run Indication */
+#define SPI_STAT_TUE 0x00000020 /*Transmit Under-Run Indication */
+#define SPI_STAT_TCE 0x00000040 /*Transmit Collision Indication */
+#define SPI_STAT_MODF 0x00000080 /*Mode Fault Indication */
+#define SPI_STAT_RS 0x00000100 /*Receive Start Indication */
+#define SPI_STAT_TS 0x00000200 /*Transmit Start Indication */
+#define SPI_STAT_RF 0x00000400 /*Receive Finish Indication */
+#define SPI_STAT_TF 0x00000800 /*Transmit Finish Indication */
+#define SPI_STAT_RFS 0x00007000 /*SPI_RFIFO status */
+#define SPI_STAT_RFIFO_EMPTY 0x00000000 /*RFS: RFIFO Empty */
+#define SPI_STAT_RFIFO_25 0x00001000 /*RFS: RFIFO 25% Full */
+#define SPI_STAT_RFIFO_50 0x00002000 /*RFS: RFIFO 50% Full */
+#define SPI_STAT_RFIFO_75 0x00003000 /*RFS: RFIFO 75% Full */
+#define SPI_STAT_RFIFO_FULL 0x00004000 /*RFS: RFIFO Full */
+#define SPI_STAT_TFS 0x00070000 /*SPI_TFIFO status */
+#define SPI_STAT_TFIFO_FULL 0x00000000 /*TFS: TFIFO full */
+#define SPI_STAT_TFIFO_25 0x00010000 /*TFS: TFIFO 25% empty */
+#define SPI_STAT_TFIFO_50 0x00020000 /*TFS: TFIFO 50% empty */
+#define SPI_STAT_TFIFO_75 0x00030000 /*TFS: TFIFO 75% empty */
+#define SPI_STAT_TFIFO_EMPTY 0x00040000 /*TFS: TFIFO empty */
+#define SPI_STAT_FCS 0x00100000 /*Flow-Control Stall Indication */
+#define SPI_STAT_RFE 0x00400000 /*SPI_RFIFO Empty */
+#define SPI_STAT_TFF 0x00800000 /*SPI_TFIFO Full */
+/* SPI_ILAT */
+#define SPI_ILAT_RUWMI 0x00000002 /*Receive Water Mark Interrupt */
+#define SPI_ILAT_TUWMI 0x00000004 /*Transmit Water Mark Interrupt */
+#define SPI_ILAT_ROI 0x00000010 /*Receive Over-Run Indication */
+#define SPI_ILAT_TUI 0x00000020 /*Transmit Under-Run Indication */
+#define SPI_ILAT_TCI 0x00000040 /*Transmit Collision Indication */
+#define SPI_ILAT_MFI 0x00000080 /*Mode Fault Indication */
+#define SPI_ILAT_RSI 0x00000100 /*Receive Start Indication */
+#define SPI_ILAT_TSI 0x00000200 /*Transmit Start Indication */
+#define SPI_ILAT_RFI 0x00000400 /*Receive Finish Indication */
+#define SPI_ILAT_TFI 0x00000800 /*Transmit Finish Indication */
+/* SPI_ILATCL */
+#define SPI_ILAT_CLR_RUWMI 0x00000002 /*Receive Water Mark Interrupt */
+#define SPI_ILAT_CLR_TUWMI 0x00000004 /*Transmit Water Mark Interrupt */
+#define SPI_ILAT_CLR_ROI 0x00000010 /*Receive Over-Run Indication */
+#define SPI_ILAT_CLR_TUI 0x00000020 /*Transmit Under-Run Indication */
+#define SPI_ILAT_CLR_TCI 0x00000040 /*Transmit Collision Indication */
+#define SPI_ILAT_CLR_MFI 0x00000080 /*Mode Fault Indication */
+#define SPI_ILAT_CLR_RSI 0x00000100 /*Receive Start Indication */
+#define SPI_ILAT_CLR_TSI 0x00000200 /*Transmit Start Indication */
+#define SPI_ILAT_CLR_RFI 0x00000400 /*Receive Finish Indication */
+#define SPI_ILAT_CLR_TFI 0x00000800 /*Transmit Finish Indication */
+
+/*
+ * bfin spi3 registers layout
+ */
+struct bfin_spi_regs {
+ u32 revid;
+ u32 control;
+ u32 rx_control;
+ u32 tx_control;
+ u32 clock;
+ u32 delay;
+ u32 ssel;
+ u32 rwc;
+ u32 rwcr;
+ u32 twc;
+ u32 twcr;
+ u32 reserved0;
+ u32 emask;
+ u32 emaskcl;
+ u32 emaskst;
+ u32 reserved1;
+ u32 status;
+ u32 elat;
+ u32 elatcl;
+ u32 reserved2;
+ u32 rfifo;
+ u32 reserved3;
+ u32 tfifo;
+};
+
+#endif /* _SPI_CHANNEL_H_ */
--- /dev/null
+/*
+ * UART4 Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_UART4__
+#define __BFIN_PERIPHERAL_UART4__
+
+/* UART_CONTROL */
+#define UEN (1 << 0)
+#define LOOP_ENA (1 << 1)
+#define UMOD (3 << 4)
+#define UMOD_UART (0 << 4)
+#define UMOD_MDB (1 << 4)
+#define UMOD_IRDA (1 << 4)
+#define WLS (3 << 8)
+#define WLS_5 (0 << 8)
+#define WLS_6 (1 << 8)
+#define WLS_7 (2 << 8)
+#define WLS_8 (3 << 8)
+#define STB (1 << 12)
+#define STBH (1 << 13)
+#define PEN (1 << 14)
+#define EPS (1 << 15)
+#define STP (1 << 16)
+#define FPE (1 << 17)
+#define FFE (1 << 18)
+#define SB (1 << 19)
+#define FCPOL (1 << 22)
+#define RPOLC (1 << 23)
+#define TPOLC (1 << 24)
+#define MRTS (1 << 25)
+#define XOFF (1 << 26)
+#define ARTS (1 << 27)
+#define ACTS (1 << 28)
+#define RFIT (1 << 29)
+#define RFRT (1 << 30)
+
+/* UART_STATUS */
+#define DR (1 << 0)
+#define OE (1 << 1)
+#define PE (1 << 2)
+#define FE (1 << 3)
+#define BI (1 << 4)
+#define THRE (1 << 5)
+#define TEMT (1 << 7)
+#define TFI (1 << 8)
+#define ASTKY (1 << 9)
+#define ADDR (1 << 10)
+#define RO (1 << 11)
+#define SCTS (1 << 12)
+#define CTS (1 << 16)
+#define RFCS (1 << 17)
+
+/* UART_EMASK */
+#define ERBFI (1 << 0)
+#define ETBEI (1 << 1)
+#define ELSI (1 << 2)
+#define EDSSI (1 << 3)
+#define EDTPTI (1 << 4)
+#define ETFI (1 << 5)
+#define ERFCI (1 << 6)
+#define EAWI (1 << 7)
+#define ERXS (1 << 8)
+#define ETXS (1 << 9)
+
+#endif
#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
+#if defined(__ADSPBF60x__)
+#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
+#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
+#else
+#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
+#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
+#endif
void init_cplbtables(void)
{
volatile uint32_t *ICPLB_ADDR, *ICPLB_DATA;
icplb_add(0xFFA00000, L1_IMEMORY);
dcplb_add(0xFF800000, L1_DMEMORY);
++i;
+#if defined(__ADSPBF60x__)
+ icplb_add(0x0, 0x0);
+ dcplb_add(CONFIG_SYS_FLASH_BASE, SDRAM_EBIU);
+ ++i;
+#endif
if (CONFIG_MEM_SIZE) {
uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
}
}
+#ifndef __ADSPBF60x__
icplb_add(0x20000000, SDRAM_INON_CHBL);
dcplb_add(0x20000000, SDRAM_EBIU);
++i;
+#endif
/* Add entries for the rest of external RAM up to the bootrom */
extern_memory = 0;
++i;
#endif
- while (i < 16 && extern_memory < (CONFIG_SYS_MONITOR_BASE & CPLB_PAGE_MASK)) {
+ while (i < 16 && extern_memory <
+ (CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
icplb_add(extern_memory, SDRAM_IGENERIC);
dcplb_add(extern_memory, SDRAM_DGENERIC);
- extern_memory += CPLB_PAGE_SIZE;
+ extern_memory += CPLB_EX_PAGE_SIZE;
++i;
}
while (i < 16) {
printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
+#if defined(__ADSPBF60x__)
+ printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
+ printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
+ printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
+#else
printf("System: %s MHz\n", strmhz(buf, get_sclk()));
+#endif
if (CONFIG_MEM_SIZE) {
printf("RAM: ");
#include <common.h>
#include <asm/blackfin.h>
+#ifdef PLL_CTL
+# include <asm/mach-common/bits/pll.h>
+# define pll_is_bypassed() (bfin_read_PLL_STAT() & DF)
+#else
+# include <asm/mach-common/bits/cgu.h>
+# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
+# define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
+# define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
+#endif
+
/* Get the voltage input multiplier */
-static u_long cached_vco_pll_ctl, cached_vco;
u_long get_vco(void)
{
- u_long msel;
+ static u_long cached_vco_pll_ctl, cached_vco;
+
+ u_long msel, pll_ctl;
- u_long pll_ctl = bfin_read_PLL_CTL();
+ pll_ctl = bfin_read_PLL_CTL();
if (pll_ctl == cached_vco_pll_ctl)
return cached_vco;
else
cached_vco_pll_ctl = pll_ctl;
- msel = (pll_ctl >> 9) & 0x3F;
+ msel = (pll_ctl & MSEL) >> MSEL_P;
if (0 == msel)
- msel = 64;
+ msel = (MSEL >> MSEL_P) + 1;
cached_vco = CONFIG_CLKIN_HZ;
- cached_vco >>= (1 & pll_ctl); /* DF bit */
+ cached_vco >>= (pll_ctl & DF);
cached_vco *= msel;
return cached_vco;
}
/* Get the Core clock */
-static u_long cached_cclk_pll_div, cached_cclk;
u_long get_cclk(void)
{
- u_long csel, ssel;
+ static u_long cached_cclk_pll_div, cached_cclk;
+ u_long div, csel, ssel;
- if (bfin_read_PLL_STAT() & 0x1)
+ if (pll_is_bypassed())
return CONFIG_CLKIN_HZ;
- ssel = bfin_read_PLL_DIV();
- if (ssel == cached_cclk_pll_div)
+ div = bfin_read_PLL_DIV();
+ if (div == cached_cclk_pll_div)
return cached_cclk;
else
- cached_cclk_pll_div = ssel;
+ cached_cclk_pll_div = div;
- csel = ((ssel >> 4) & 0x03);
- ssel &= 0xf;
+ csel = (div & CSEL) >> CSEL_P;
+#ifndef CGU_DIV
+ ssel = (div & SSEL) >> SSEL_P;
if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
cached_cclk = get_vco() / ssel;
else
cached_cclk = get_vco() >> csel;
+#else
+ cached_cclk = get_vco() / csel;
+#endif
return cached_cclk;
}
/* Get the System clock */
+#ifdef CGU_DIV
+
static u_long cached_sclk_pll_div, cached_sclk;
+static u_long cached_sclk0, cached_sclk1, cached_dclk;
+static u_long _get_sclk(u_long *cache)
+{
+ u_long div, ssel;
+
+ if (pll_is_bypassed())
+ return CONFIG_CLKIN_HZ;
+
+ div = bfin_read_PLL_DIV();
+ if (div == cached_sclk_pll_div)
+ return *cache;
+ else
+ cached_sclk_pll_div = div;
+
+ ssel = (div & SYSSEL) >> SYSSEL_P;
+ cached_sclk = get_vco() / ssel;
+
+ ssel = (div & S0SEL) >> S0SEL_P;
+ cached_sclk0 = cached_sclk / ssel;
+
+ ssel = (div & S1SEL) >> S1SEL_P;
+ cached_sclk1 = cached_sclk / ssel;
+
+ ssel = (div & DSEL) >> DSEL_P;
+ cached_dclk = get_vco() / ssel;
+
+ return *cache;
+}
+
u_long get_sclk(void)
{
- u_long ssel;
+ return _get_sclk(&cached_sclk);
+}
+
+u_long get_sclk0(void)
+{
+ return _get_sclk(&cached_sclk0);
+}
+
+u_long get_sclk1(void)
+{
+ return _get_sclk(&cached_sclk1);
+}
+
+u_long get_dclk(void)
+{
+ return _get_sclk(&cached_dclk);
+}
+#else
+
+u_long get_sclk(void)
+{
+ static u_long cached_sclk_pll_div, cached_sclk;
+ u_long div, ssel;
- if (bfin_read_PLL_STAT() & 0x1)
+ if (pll_is_bypassed())
return CONFIG_CLKIN_HZ;
- ssel = bfin_read_PLL_DIV();
- if (ssel == cached_sclk_pll_div)
+ div = bfin_read_PLL_DIV();
+ if (div == cached_sclk_pll_div)
return cached_sclk;
else
- cached_sclk_pll_div = ssel;
-
- ssel &= 0xf;
+ cached_sclk_pll_div = div;
+ ssel = (div & SSEL) >> SSEL_P;
cached_sclk = get_vco() / ssel;
+
return cached_sclk;
}
+
+#endif
#include <config.h>
#include <asm/blackfin.h>
#include <asm/io.h>
-#include <asm/mach-common/bits/dma.h>
+#include <asm/dma.h>
char *strcpy(char *dest, const char *src)
{
return __res1;
}
-#ifdef bfin_write_MDMA1_D0_IRQ_STATUS
-# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
-# define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA1_D0_START_ADDR
-# define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA1_D0_X_COUNT
-# define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA1_D0_X_MODIFY
-# define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA1_D0_CONFIG
-# define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA1_S0_START_ADDR
-# define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA1_S0_X_COUNT
-# define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA1_S0_X_MODIFY
-# define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA1_S0_CONFIG
-# define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA1_D0_IRQ_STATUS
-# define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA1_D0_IRQ_STATUS
+#ifdef MDMA1_D0_NEXT_DESC_PTR
+# define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
+# define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
#endif
+
+static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count,
+ unsigned long *dshift, unsigned long *bpos)
+{
+ unsigned long limit;
+
+#ifdef MSIZE
+ limit = 6;
+ *dshift = MSIZE_P;
+#else
+ limit = 3;
+ *dshift = WDSIZE_P;
+#endif
+
+ *bpos = min(limit, ffs(ldst | lsrc | count)) - 1;
+}
+
/* This version misbehaves for count values of 0 and 2^16+.
* Perhaps we should detect that ? Nowhere do we actually
* use dma memcpy for those types of lengths though ...
*/
void dma_memcpy_nocache(void *dst, const void *src, size_t count)
{
- uint16_t wdsize, mod;
+ struct dma_register *mdma_d0 = (void *)MDMA_D0_NEXT_DESC_PTR;
+ struct dma_register *mdma_s0 = (void *)MDMA_S0_NEXT_DESC_PTR;
+ unsigned long ldst = (unsigned long)dst;
+ unsigned long lsrc = (unsigned long)src;
+ unsigned long dshift, bpos;
+ uint32_t dsize, mod;
/* Disable DMA in case it's still running (older u-boot's did not
* always turn them off). Do it before the if statement below so
* we can be cheap and not do a SSYNC() due to the forced abort.
*/
- bfin_write_MDMA_D0_CONFIG(0);
- bfin_write_MDMA_S0_CONFIG(0);
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
+ bfin_write(&mdma_d0->config, 0);
+ bfin_write(&mdma_s0->config, 0);
+ bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
/* Scratchpad cannot be a DMA source or destination */
- if (((unsigned long)src >= L1_SRAM_SCRATCH &&
- (unsigned long)src < L1_SRAM_SCRATCH_END) ||
- ((unsigned long)dst >= L1_SRAM_SCRATCH &&
- (unsigned long)dst < L1_SRAM_SCRATCH_END))
+ if ((lsrc >= L1_SRAM_SCRATCH && lsrc < L1_SRAM_SCRATCH_END) ||
+ (ldst >= L1_SRAM_SCRATCH && ldst < L1_SRAM_SCRATCH_END))
hang();
- if (((unsigned long)dst | (unsigned long)src | count) & 0x1) {
- wdsize = WDSIZE_8;
- mod = 1;
- } else if (((unsigned long)dst | (unsigned long)src | count) & 0x2) {
- wdsize = WDSIZE_16;
- count >>= 1;
- mod = 2;
- } else {
- wdsize = WDSIZE_32;
- count >>= 2;
- mod = 4;
- }
+ dma_calc_size(ldst, lsrc, count, &dshift, &bpos);
+ dsize = bpos << dshift;
+ count >>= bpos;
+ mod = 1 << bpos;
+
+#ifdef PSIZE
+ dsize |= min(3, bpos) << PSIZE_P;
+#endif
/* Copy sram functions from sdram to sram */
/* Setup destination start address */
- bfin_write_MDMA_D0_START_ADDR(dst);
+ bfin_write(&mdma_d0->start_addr, ldst);
/* Setup destination xcount */
- bfin_write_MDMA_D0_X_COUNT(count);
+ bfin_write(&mdma_d0->x_count, count);
/* Setup destination xmodify */
- bfin_write_MDMA_D0_X_MODIFY(mod);
+ bfin_write(&mdma_d0->x_modify, mod);
/* Setup Source start address */
- bfin_write_MDMA_S0_START_ADDR(src);
+ bfin_write(&mdma_s0->start_addr, lsrc);
/* Setup Source xcount */
- bfin_write_MDMA_S0_X_COUNT(count);
+ bfin_write(&mdma_s0->x_count, count);
/* Setup Source xmodify */
- bfin_write_MDMA_S0_X_MODIFY(mod);
+ bfin_write(&mdma_s0->x_modify, mod);
/* Enable source DMA */
- bfin_write_MDMA_S0_CONFIG(wdsize | DMAEN);
- bfin_write_MDMA_D0_CONFIG(wdsize | DMAEN | WNR | DI_EN);
+ bfin_write(&mdma_s0->config, dsize | DMAEN);
+ bfin_write(&mdma_d0->config, dsize | DMAEN | WNR | DI_EN);
SSYNC();
- while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
+ while (!(bfin_read(&mdma_d0->status) & DMA_DONE))
continue;
- bfin_write_MDMA_D0_IRQ_STATUS(DMA_RUN | DMA_DONE | DMA_ERR);
- bfin_write_MDMA_D0_CONFIG(0);
- bfin_write_MDMA_S0_CONFIG(0);
+ bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
+ bfin_write(&mdma_d0->config, 0);
+ bfin_write(&mdma_s0->config, 0);
}
/* We should do a dcache invalidate on the destination after the dma, but since
* we lack such hardware capability, we'll flush/invalidate the destination
/* The Malloc area is immediately below the monitor copy in DRAM */
mem_malloc_init (CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
- malloc_bin_reloc ();
#if !defined(CONFIG_SYS_NO_FLASH)
puts ("Flash: ");
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
.bss ALIGN(0x4):
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
--- /dev/null
+#include <asm-generic/errno.h>
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
- malloc_bin_reloc();
#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
/* INIT DATA sections - "Small" data (see the gcc -G option)
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
_edata = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(8);
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
# MA 02111-1307 USA
PLATFORM_CPPFLAGS += -DCONFIG_SANDBOX -D__SANDBOX__ -U_FORTIFY_SOURCE
+PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM
PLATFORM_LIBS += -lrt
* MA 02111-1307 USA
*/
+#include <dirent.h>
#include <errno.h>
#include <fcntl.h>
#include <getopt.h>
+#include <stdio.h>
#include <stdlib.h>
+#include <string.h>
#include <termios.h>
#include <time.h>
#include <unistd.h>
return read(fd, buf, count);
}
+ssize_t os_read_no_block(int fd, void *buf, size_t count)
+{
+ const int flags = fcntl(fd, F_GETFL, 0);
+
+ fcntl(fd, F_SETFL, flags | O_NONBLOCK);
+ return os_read(fd, buf, count);
+}
+
ssize_t os_write(int fd, const void *buf, size_t count)
{
return write(fd, buf, count);
return 0;
}
+
+void os_dirent_free(struct os_dirent_node *node)
+{
+ struct os_dirent_node *next;
+
+ while (node) {
+ next = node->next;
+ free(node);
+ node = next;
+ }
+}
+
+int os_dirent_ls(const char *dirname, struct os_dirent_node **headp)
+{
+ struct dirent entry, *result;
+ struct os_dirent_node *head, *node, *next;
+ struct stat buf;
+ DIR *dir;
+ int ret;
+ char *fname;
+ int len;
+
+ *headp = NULL;
+ dir = opendir(dirname);
+ if (!dir)
+ return -1;
+
+ /* Create a buffer for the maximum filename length */
+ len = sizeof(entry.d_name) + strlen(dirname) + 2;
+ fname = malloc(len);
+ if (!fname) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ for (node = head = NULL;; node = next) {
+ ret = readdir_r(dir, &entry, &result);
+ if (ret || !result)
+ break;
+ next = malloc(sizeof(*node) + strlen(entry.d_name) + 1);
+ if (!next) {
+ os_dirent_free(head);
+ ret = -ENOMEM;
+ goto done;
+ }
+ strcpy(next->name, entry.d_name);
+ switch (entry.d_type) {
+ case DT_REG:
+ next->type = OS_FILET_REG;
+ break;
+ case DT_DIR:
+ next->type = OS_FILET_DIR;
+ break;
+ case DT_LNK:
+ next->type = OS_FILET_LNK;
+ break;
+ }
+ next->size = 0;
+ snprintf(fname, len, "%s/%s", dirname, next->name);
+ if (!stat(fname, &buf))
+ next->size = buf.st_size;
+ if (node)
+ node->next = next;
+ if (!head)
+ head = node;
+ }
+ *headp = head;
+
+done:
+ closedir(dir);
+ return ret;
+}
+
+const char *os_dirent_typename[OS_FILET_COUNT] = {
+ " ",
+ "SYM",
+ "DIR",
+ "???",
+};
+
+const char *os_dirent_get_typename(enum os_dirent_t type)
+{
+ if (type >= 0 && type < OS_FILET_COUNT)
+ return os_dirent_typename[type];
+
+ return os_dirent_typename[OS_FILET_UNKNOWN];
+}
+
+ssize_t os_get_filesize(const char *fname)
+{
+ struct stat buf;
+ int ret;
+
+ ret = stat(fname, &buf);
+ if (ret)
+ return ret;
+ return buf.st_size;
+}
* never return.
*/
board_init_f(0);
+
+ /* NOTREACHED - board_init_f() does not return */
+ return 0;
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
__u_boot_sandbox_option_start = .;
{
}
+
+/* For sandbox, we want addresses to point into our RAM buffer */
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ return map_physmem(paddr, len, MAP_WRBACK);
+}
+
+static inline void unmap_sysmem(const void *vaddr)
+{
+}
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
PROVIDE (reloc_dst_end = .);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
PROVIDE (reloc_dst_end = .);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
PROVIDE (reloc_dst_end = .);
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE,
CONFIG_SYS_MALLOC_END - CONFIG_SYS_MALLOC_BASE);
- malloc_bin_reloc();
#if !defined(CONFIG_SYS_NO_FLASH)
puts("Flash: ");
void show_boot_progress(int val)
{
#if MIN_PORT80_KCLOCKS_DELAY
- static uint32_t prev_stamp;
- static uint32_t base;
-
/*
* Scale the time counter reading to avoid using 64 bit arithmetics.
* Can't use get_timer() here becuase it could be not yet
* initialized or even implemented.
*/
- if (!prev_stamp) {
- base = rdtsc() / 1000;
- prev_stamp = 0;
+ if (!gd->arch.tsc_prev) {
+ gd->arch.tsc_base_kclocks = rdtsc() / 1000;
+ gd->arch.tsc_prev = 0;
} else {
uint32_t now;
do {
- now = rdtsc() / 1000 - base;
- } while (now < (prev_stamp + MIN_PORT80_KCLOCKS_DELAY));
- prev_stamp = now;
+ now = rdtsc() / 1000 - gd->arch.tsc_base_kclocks;
+ } while (now < (gd->arch.tsc_prev + MIN_PORT80_KCLOCKS_DELAY));
+ gd->arch.tsc_prev = now;
}
#endif
outb(val, 0x80);
* address, and how far U-Boot is moved by relocation are set in the global
* data structure.
*/
-int calculate_relocation_address(void)
+ulong board_get_usable_ram_top(ulong total_size)
{
- const uint64_t uboot_size = (uintptr_t)&__bss_end -
- (uintptr_t)&__text_start;
- const uint64_t total_size = uboot_size + CONFIG_SYS_MALLOC_LEN +
- CONFIG_SYS_STACK_SIZE;
uintptr_t dest_addr = 0;
int i;
continue;
/* Use this address if it's the largest so far. */
- if (end - uboot_size > dest_addr)
+ if (end > dest_addr)
dest_addr = end;
}
/* If no suitable area was found, return an error. */
if (!dest_addr)
- return 1;
+ panic("No available memory found for relocation");
- dest_addr -= uboot_size;
- dest_addr &= ~((1 << 12) - 1);
- gd->relocaddr = dest_addr;
- gd->reloc_off = dest_addr - (uintptr_t)&__text_start;
- gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN;
-
- return 0;
+ return (ulong)dest_addr;
}
int dram_init_f(void)
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
}
+
+void dcache_enable(void)
+{
+ enable_caches();
+}
+
+void dcache_disable(void)
+{
+ disable_caches();
+}
+
+void icache_enable(void)
+{
+}
+
+void icache_disable(void)
+{
+}
+
+int icache_status(void)
+{
+ return 1;
+}
*/
u64 get_ticks(void)
{
- static u64 tick_base;
u64 now_tick = rdtsc();
- if (!tick_base)
- tick_base = now_tick;
+ if (!gd->arch.tsc_base)
+ gd->arch.tsc_base = now_tick;
- return now_tick - tick_base;
+ return now_tick - gd->arch.tsc_base;
}
#define PLATFORM_INFO_MSR 0xce
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
. = ALIGN(4);
.data : { *(.data*) }
- . = ALIGN(4);
- .dynsym : { *(.dynsym*) }
-
. = ALIGN(4);
.hash : { *(.hash*) }
__data_end = .;
. = ALIGN(4);
- __bss_start = ABSOLUTE(.);
- .bss (NOLOAD) : { *(.bss) }
- . = ALIGN(4);
- __bss_end = ABSOLUTE(.);
+ .dynsym : { *(.dynsym*) }
. = ALIGN(4);
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
+ . = ALIGN(4);
+ _end = .;
+
+ . = ALIGN(4);
+
+ __end = .;
+ .bss __rel_dyn_start (OVERLAY) : {
+ __bss_start = .;
+ *(.bss)
+ *(COM*)
+ . = ALIGN(4);
+ __bss_end = .;
+ }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/* Architecture-specific global data */
struct arch_global_data {
struct global_data *gd_addr; /* Location of Global Data */
+ uint64_t tsc_base; /* Initial value returned by rdtsc() */
+ uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
+ uint32_t tsc_prev; /* For show_boot_progress() */
+ void *new_fdt; /* Relocated FDT */
};
#endif
int status_led_set_r(void);
int set_load_addr_r(void);
int init_func_spi(void);
+int find_fdt(void);
+int prepare_fdt(void);
#endif /* !_INIT_HELPERS_H_ */
#include <common.h>
int copy_uboot_to_ram(void);
+int copy_fdt_to_ram(void);
int clear_bss(void);
int do_elf_reloc_fixups(void);
extern ulong __rel_dyn_end;
extern ulong __bss_start;
extern ulong __bss_end;
+extern ulong _end;
/* cpu/.../cpu.c */
int x86_cpu_init_r(void);
*/
#include <common.h>
+#include <fdtdec.h>
#include <watchdog.h>
#include <stdio_dev.h>
#include <asm/u-boot-x86.h>
init_fnc_t *init_sequence_f_r[] = {
init_cache_f_r,
copy_uboot_to_ram,
+ copy_fdt_to_ram,
clear_bss,
do_elf_reloc_fixups,
void board_init_f(ulong boot_flags)
{
+ gd->fdt_blob = gd->arch.new_fdt = NULL;
gd->flags = boot_flags;
do_init_loop(init_sequence_f);
*/
#include <common.h>
#include <command.h>
+#include <fdtdec.h>
#include <stdio_dev.h>
#include <version.h>
#include <malloc.h>
return 0;
}
-__weak int calculate_relocation_address(void)
+/* Get the top of usable RAM */
+__weak ulong board_get_usable_ram_top(ulong total_size)
{
- ulong text_start = (ulong)&__text_start;
- ulong bss_end = (ulong)&__bss_end;
+ return gd->ram_size;
+}
+
+int calculate_relocation_address(void)
+{
+ const ulong uboot_size = (uintptr_t)&__bss_end -
+ (uintptr_t)&__text_start;
+ ulong total_size;
ulong dest_addr;
+ ulong fdt_size = 0;
+#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
+ if (gd->fdt_blob)
+ fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+#endif
+ total_size = ALIGN(uboot_size, 1 << 12) + CONFIG_SYS_MALLOC_LEN +
+ CONFIG_SYS_STACK_SIZE + fdt_size;
+
+ dest_addr = board_get_usable_ram_top(total_size);
/*
* NOTE: All destination address are rounded down to 16-byte
* boundary to satisfy various worst-case alignment
* requirements
*/
-
- /* Stack is at top of available memory */
- dest_addr = gd->ram_size;
-
- /* U-Boot is at the top */
- dest_addr -= (bss_end - text_start);
dest_addr &= ~15;
+
+#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
+ /*
+ * If the device tree is sitting immediate above our image then we
+ * must relocate it. If it is embedded in the data section, then it
+ * will be relocated with other data.
+ */
+ if (gd->fdt_blob) {
+ dest_addr -= fdt_size;
+ gd->arch.new_fdt = (void *)dest_addr;
+ dest_addr &= ~15;
+ }
+#endif
+ /* U-Boot is below the FDT */
+ dest_addr -= uboot_size;
+ dest_addr &= ~((1 << 12) - 1);
gd->relocaddr = dest_addr;
- gd->reloc_off = (dest_addr - text_start);
+ gd->reloc_off = dest_addr - (uintptr_t)&__text_start;
/* Stack is at the bottom, so it can grow down */
gd->start_addr_sp = dest_addr - CONFIG_SYS_MALLOC_LEN;
gd->fdt_blob = _binary_dt_dtb_start;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
- gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);
+ gd->fdt_blob = (ulong *)&_end;
#endif
/* Allow the early environment to override the fdt address */
gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
*/
#include <common.h>
#include <environment.h>
+#include <fdtdec.h>
#include <serial.h>
#include <kgdb.h>
#include <scsi.h>
*/
#include <common.h>
+#include <libfdt.h>
#include <malloc.h>
#include <asm/u-boot-x86.h>
#include <asm/relocate.h>
return 0;
}
+int copy_fdt_to_ram(void)
+{
+ if (gd->arch.new_fdt) {
+ ulong fdt_size;
+
+ fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+ memcpy(gd->arch.new_fdt, gd->fdt_blob, fdt_size);
+ debug("Relocated fdt from %p to %p, size %lx\n",
+ gd->fdt_blob, gd->arch.new_fdt, fdt_size);
+ gd->fdt_blob = gd->arch.new_fdt;
+ }
+
+ return 0;
+}
+
int clear_bss(void)
{
ulong dst_addr = (ulong)&__bss_start + gd->reloc_off;
return 0;
}
+/*
+ * This function has more error checking than you might expect. Please see
+ * the commit message for more informaiton.
+ */
int do_elf_reloc_fixups(void)
{
Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
- Elf32_Addr *offset_ptr_rom;
+ Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
Elf32_Addr *offset_ptr_ram;
/* The size of the region of u-boot that runs out of RAM. */
offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */
- if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE) {
+ if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+ offset_ptr_rom > last_offset) {
/* Switch to the in-RAM version */
offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
*offset_ptr_ram <=
(CONFIG_SYS_TEXT_BASE + size)) {
*offset_ptr_ram += gd->reloc_off;
+ } else {
+ debug(" %p: rom reloc %x, ram %p, value %x,"
+ " limit %lx\n", re_src,
+ re_src->r_offset, offset_ptr_ram,
+ *offset_ptr_ram,
+ CONFIG_SYS_TEXT_BASE + size);
}
+ } else {
+ debug(" %p: rom reloc %x, last %p\n", re_src,
+ re_src->r_offset, last_offset);
}
+ last_offset = offset_ptr_rom;
+
} while (++re_src < re_end);
return 0;
static struct timer_isr_function *first_timer_isr;
static unsigned long system_ticks;
-static uint64_t base_value;
/*
* register_timer_isr() allows multiple architecture and board specific
void timer_set_tsc_base(uint64_t new_base)
{
- base_value = new_base;
+ gd->arch.tsc_base = new_base;
}
uint64_t timer_get_tsc(void)
uint64_t time_now;
time_now = rdtsc();
- if (!base_value)
- base_value = time_now;
+ if (!gd->arch.tsc_base)
+ gd->arch.tsc_base = time_now;
- return time_now - base_value;
+ return time_now - gd->arch.tsc_base;
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
*(.text*)
}
- . = ALIGN (4);
+ . = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- . = ALIGN (4);
+ . = ALIGN(4);
.data : {
*(.data*)
}
- . = ALIGN (4);
+ . = ALIGN(4);
.got : {
*(.got)
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN (4);
*(.dynsym)
}
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ _end = .;
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- _end = .;
+ ___bssend___ = .;
}
- __bss_end__ =.;
+ .bss_end ___bssend___ (OVERLAY) : {
+ KEEP(*(.__bss_end__));
+ }
+
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
*(.text*)
}
- . = ALIGN (4);
+ . = ALIGN(4);
.rodata : {
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- . = ALIGN (4);
+ . = ALIGN(4);
.data : {
*(.data*)
}
- . = ALIGN (4);
+ . = ALIGN(4);
.got : {
*(.got)
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN (4);
*(.dynsym)
}
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ _end = .;
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- _end = .;
+ ___bssend___ = .;
}
- __bss_end__ =.;
+ .bss_end ___bssend___ (OVERLAY) : {
+ KEEP(*(.__bss_end__));
+ }
+
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN (4);
*(.dynsym)
}
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ _end = .;
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- _end = .;
+ ___bssend___ = .;
}
- __bss_end__ =.;
+ .bss_end ___bssend___ (OVERLAY) : {
+ KEEP(*(.__bss_end__));
+ }
+
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- } >.sram
- . = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
/* INIT DATA sections - "Small" data (see the gcc -G option)
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
int board_init(void)
{
+#ifdef CONFIG_AT91SAM9G20EK_2MMC
+ /* arch number of AT91SAM9G20EK_2MMC-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK_2MMC;
+#else
#ifdef CONFIG_AT91SAM9G20EK
- /* arch number of AT91SAM9260EK-Board */
+ /* arch number of AT91SAM9G20EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
#else
/* arch number of AT91SAM9260EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
+#endif
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
--- /dev/null
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_BFIN_SOFT_SWITCH) += soft_switch.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include <asm/portmux.h>
+#include "soft_switch.h"
+
+int checkboard(void)
+{
+ printf("Board: ADI BF609 EZ-Kit board\n");
+ printf(" Support: http://blackfin.uclinux.org/\n");
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ static const unsigned short pins[] = {
+ P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+ P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+ P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
+ };
+ peripheral_request_list(pins, "smc0");
+
+ return 0;
+}
+
+#ifdef CONFIG_DESIGNWARE_ETH
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+
+ if (CONFIG_DW_PORTS & 1) {
+ static const unsigned short pins[] = P_RMII0;
+ if (!peripheral_request_list(pins, "emac0"))
+ ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
+ }
+ if (CONFIG_DW_PORTS & 2) {
+ static const unsigned short pins[] = P_RMII1;
+ if (!peripheral_request_list(pins, "emac1"))
+ ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
+ }
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_BFIN_SDH
+int board_mmc_init(bd_t *bis)
+{
+ return bfin_mmc_init(bis);
+}
+#endif
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+ printf("other init\n");
+ return setup_board_switches();
+}
/dts-v1/;
-/include/ "coreboot.dtsi"
+/include/ ARCH_CPU_DTS
/ {
#address-cells = <1>;
LIB = $(obj)lib$(BOARD).o
COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
+COBJS-$(CONFIG_LCD) += display.o
COBJS := cm_t35.o leds.o $(COBJS-y)
#include <net.h>
#include <i2c.h>
#include <usb.h>
+#include <mmc.h>
#include <twl4030.h>
#include <linux/compiler.h>
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
+ /* DVI enable */
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
+
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
}
#ifdef CONFIG_GENERIC_MMC
+int board_mmc_getcd(struct mmc *mmc)
+{
+ u8 val;
+
+ if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, &val, TWL4030_BASEADD_GPIO))
+ return -1;
+
+ return !(val & 1);
+}
+
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ return omap_mmc_init(0, 0, 0, -1, 59);
}
#endif
--- /dev/null
+/*
+ * (C) Copyright 2012 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Nikita Kiryanov <nikita@compulab.co.il>
+ *
+ * Parsing code based on linux/drivers/video/pxafb.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <stdio_dev.h>
+#include <asm/arch/dss.h>
+#include <lcd.h>
+#include <asm/arch-omap3/dss.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum display_type {
+ NONE,
+ DVI,
+ DVI_CUSTOM,
+};
+
+#define CMAP_ADDR 0x80100000
+
+/*
+ * The frame buffer is allocated before we have the chance to parse user input.
+ * To make sure enough memory is allocated for all resolutions, we define
+ * vl_{col | row} to the maximal resolution supported by OMAP3.
+ */
+vidinfo_t panel_info = {
+ .vl_col = 1400,
+ .vl_row = 1050,
+ .vl_bpix = LCD_BPP,
+ .cmap = (ushort *)CMAP_ADDR,
+};
+
+static struct panel_config panel_cfg;
+static enum display_type lcd_def;
+
+/*
+ * A note on DVI presets;
+ * U-Boot can convert 8 bit BMP data to 16 bit BMP data, and OMAP DSS can
+ * convert 16 bit data into 24 bit data. Thus, GFXFORMAT_RGB16 allows us to
+ * support two BMP types with one setting.
+ */
+static const struct panel_config preset_dvi_640X480 = {
+ .lcd_size = PANEL_LCD_SIZE(640, 480),
+ .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96),
+ .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2),
+ .divisor = 12 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_800X600 = {
+ .lcd_size = PANEL_LCD_SIZE(800, 600),
+ .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128),
+ .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4),
+ .divisor = 8 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1024X768 = {
+ .lcd_size = PANEL_LCD_SIZE(1024, 768),
+ .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136),
+ .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6),
+ .divisor = 5 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1152X864 = {
+ .lcd_size = PANEL_LCD_SIZE(1152, 864),
+ .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128),
+ .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3),
+ .divisor = 3 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X960 = {
+ .lcd_size = PANEL_LCD_SIZE(1280, 960),
+ .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112),
+ .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3),
+ .divisor = 3 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+static const struct panel_config preset_dvi_1280X1024 = {
+ .lcd_size = PANEL_LCD_SIZE(1280, 1024),
+ .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112),
+ .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3),
+ .divisor = 3 | (1 << 16),
+ .data_lines = LCD_INTERFACE_24_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
+/*
+ * set_resolution_params()
+ *
+ * Due to usage of multiple display related APIs resolution data is located in
+ * more than one place. This function updates them all.
+ */
+static void set_resolution_params(int x, int y)
+{
+ panel_cfg.lcd_size = PANEL_LCD_SIZE(x, y);
+ panel_info.vl_col = x;
+ panel_info.vl_row = y;
+ lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+}
+
+static void set_preset(const struct panel_config preset, int x_res, int y_res)
+{
+ panel_cfg = preset;
+ set_resolution_params(x_res, y_res);
+}
+
+static enum display_type set_dvi_preset(const struct panel_config preset,
+ int x_res, int y_res)
+{
+ set_preset(preset, x_res, y_res);
+ return DVI;
+}
+
+/*
+ * parse_mode() - parse the mode parameter of custom lcd settings
+ *
+ * @mode: <res_x>x<res_y>
+ *
+ * Returns -1 on error, 0 on success.
+ */
+static int parse_mode(const char *mode)
+{
+ unsigned int modelen = strlen(mode);
+ int res_specified = 0;
+ unsigned int xres = 0, yres = 0;
+ int yres_specified = 0;
+ int i;
+
+ for (i = modelen - 1; i >= 0; i--) {
+ switch (mode[i]) {
+ case 'x':
+ if (!yres_specified) {
+ yres = simple_strtoul(&mode[i + 1], NULL, 0);
+ yres_specified = 1;
+ } else {
+ goto done_parsing;
+ }
+
+ break;
+ case '0' ... '9':
+ break;
+ default:
+ goto done_parsing;
+ }
+ }
+
+ if (i < 0 && yres_specified) {
+ xres = simple_strtoul(mode, NULL, 0);
+ res_specified = 1;
+ }
+
+done_parsing:
+ if (res_specified) {
+ set_resolution_params(xres, yres);
+ } else {
+ printf("LCD: invalid mode: %s\n", mode);
+ return -1;
+ }
+
+ return 0;
+}
+
+#define PIXEL_CLK_NUMERATOR (26 * 432 / 39)
+/*
+ * parse_pixclock() - Parse the pixclock parameter of custom lcd settings
+ *
+ * @pixclock: the desired pixel clock
+ *
+ * Returns -1 on error, 0 on success.
+ *
+ * Handling the pixel_clock:
+ *
+ * Pixel clock is defined in the OMAP35x TRM as follows:
+ * pixel_clock =
+ * (SYS_CLK * 2 * PRCM.CM_CLKSEL2_PLL[18:8]) /
+ * (DSS.DISPC_DIVISOR[23:16] * DSS.DISPC_DIVISOR[6:0] *
+ * PRCM.CM_CLKSEL_DSS[4:0] * (PRCM.CM_CLKSEL2_PLL[6:0] + 1))
+ *
+ * In practice, this means that in order to set the
+ * divisor for the desired pixel clock one needs to
+ * solve the following equation:
+ *
+ * 26 * 432 / (39 * <pixel_clock>) = DSS.DISPC_DIVISOR[6:0]
+ *
+ * NOTE: the explicit equation above is reduced. Do not
+ * try to infer anything from these numbers.
+ */
+static int parse_pixclock(char *pixclock)
+{
+ int divisor, pixclock_val;
+ char *pixclk_start = pixclock;
+
+ pixclock_val = simple_strtoul(pixclock, &pixclock, 10);
+ divisor = DIV_ROUND_UP(PIXEL_CLK_NUMERATOR, pixclock_val);
+ /* 0 and 1 are illegal values for PCD */
+ if (divisor <= 1)
+ divisor = 2;
+
+ panel_cfg.divisor = divisor | (1 << 16);
+ if (pixclock[0] != '\0') {
+ printf("LCD: invalid value for pixclock:%s\n", pixclk_start);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * parse_setting() - parse a single setting of custom lcd parameters
+ *
+ * @setting: The custom lcd setting <name>:<value>
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_setting(char *setting)
+{
+ int num_val;
+ char *setting_start = setting;
+
+ if (!strncmp(setting, "mode:", 5)) {
+ return parse_mode(setting + 5);
+ } else if (!strncmp(setting, "pixclock:", 9)) {
+ return parse_pixclock(setting + 9);
+ } else if (!strncmp(setting, "left:", 5)) {
+ num_val = simple_strtoul(setting + 5, &setting, 0);
+ panel_cfg.timing_h |= DSS_HBP(num_val);
+ } else if (!strncmp(setting, "right:", 6)) {
+ num_val = simple_strtoul(setting + 6, &setting, 0);
+ panel_cfg.timing_h |= DSS_HFP(num_val);
+ } else if (!strncmp(setting, "upper:", 6)) {
+ num_val = simple_strtoul(setting + 6, &setting, 0);
+ panel_cfg.timing_v |= DSS_VBP(num_val);
+ } else if (!strncmp(setting, "lower:", 6)) {
+ num_val = simple_strtoul(setting + 6, &setting, 0);
+ panel_cfg.timing_v |= DSS_VFP(num_val);
+ } else if (!strncmp(setting, "hsynclen:", 9)) {
+ num_val = simple_strtoul(setting + 9, &setting, 0);
+ panel_cfg.timing_h |= DSS_HSW(num_val);
+ } else if (!strncmp(setting, "vsynclen:", 9)) {
+ num_val = simple_strtoul(setting + 9, &setting, 0);
+ panel_cfg.timing_v |= DSS_VSW(num_val);
+ } else if (!strncmp(setting, "hsync:", 6)) {
+ if (simple_strtoul(setting + 6, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IHS;
+ else
+ panel_cfg.pol_freq &= ~DSS_IHS;
+ } else if (!strncmp(setting, "vsync:", 6)) {
+ if (simple_strtoul(setting + 6, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IVS;
+ else
+ panel_cfg.pol_freq &= ~DSS_IVS;
+ } else if (!strncmp(setting, "outputen:", 9)) {
+ if (simple_strtoul(setting + 9, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IEO;
+ else
+ panel_cfg.pol_freq &= ~DSS_IEO;
+ } else if (!strncmp(setting, "pixclockpol:", 12)) {
+ if (simple_strtoul(setting + 12, &setting, 0) == 0)
+ panel_cfg.pol_freq |= DSS_IPC;
+ else
+ panel_cfg.pol_freq &= ~DSS_IPC;
+ } else if (!strncmp(setting, "active", 6)) {
+ panel_cfg.panel_type = ACTIVE_DISPLAY;
+ return 0; /* Avoid sanity check below */
+ } else if (!strncmp(setting, "passive", 7)) {
+ panel_cfg.panel_type = PASSIVE_DISPLAY;
+ return 0; /* Avoid sanity check below */
+ } else if (!strncmp(setting, "display:", 8)) {
+ if (!strncmp(setting + 8, "dvi", 3)) {
+ lcd_def = DVI_CUSTOM;
+ return 0; /* Avoid sanity check below */
+ }
+ } else {
+ printf("LCD: unknown option %s\n", setting_start);
+ return -1;
+ }
+
+ if (setting[0] != '\0') {
+ printf("LCD: invalid value for %s\n", setting_start);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * env_parse_customlcd() - parse custom lcd params from an environment variable.
+ *
+ * @custom_lcd_params: The environment variable containing the lcd params.
+ *
+ * Returns -1 on failure, 0 on success.
+ */
+static int parse_customlcd(char *custom_lcd_params)
+{
+ char params_cpy[160];
+ char *setting;
+
+ strncpy(params_cpy, custom_lcd_params, 160);
+ setting = strtok(params_cpy, ",");
+ while (setting) {
+ if (parse_setting(setting) < 0)
+ return -1;
+
+ setting = strtok(NULL, ",");
+ }
+
+ /* Currently we don't support changing this via custom lcd params */
+ panel_cfg.data_lines = LCD_INTERFACE_24_BIT;
+ panel_cfg.gfx_format = GFXFORMAT_RGB16; /* See dvi predefines note */
+
+ return 0;
+}
+
+/*
+ * env_parse_displaytype() - parse display type.
+ *
+ * Parses the environment variable "displaytype", which contains the
+ * name of the display type or preset, in which case it applies its
+ * configurations.
+ *
+ * Returns the type of display that was specified.
+ */
+static enum display_type env_parse_displaytype(char *displaytype)
+{
+ if (!strncmp(displaytype, "dvi640x480", 10))
+ return set_dvi_preset(preset_dvi_640X480, 640, 480);
+ else if (!strncmp(displaytype, "dvi800x600", 10))
+ return set_dvi_preset(preset_dvi_800X600, 800, 600);
+ else if (!strncmp(displaytype, "dvi1024x768", 11))
+ return set_dvi_preset(preset_dvi_1024X768, 1024, 768);
+ else if (!strncmp(displaytype, "dvi1152x864", 11))
+ return set_dvi_preset(preset_dvi_1152X864, 1152, 864);
+ else if (!strncmp(displaytype, "dvi1280x960", 11))
+ return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
+ else if (!strncmp(displaytype, "dvi1280x1024", 12))
+ return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
+
+ return NONE;
+}
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+void *lcd_base;
+short console_col;
+short console_row;
+void *lcd_console_address;
+
+void lcd_ctrl_init(void *lcdbase)
+{
+ struct prcm *prcm = (struct prcm *)PRCM_BASE;
+ char *custom_lcd;
+ char *displaytype = getenv("displaytype");
+
+ if (displaytype == NULL)
+ return;
+
+ lcd_def = env_parse_displaytype(displaytype);
+ /* If we did not recognize the preset, check if it's an env variable */
+ if (lcd_def == NONE) {
+ custom_lcd = getenv(displaytype);
+ if (custom_lcd == NULL || parse_customlcd(custom_lcd) < 0)
+ return;
+ }
+
+ panel_cfg.frame_buffer = lcdbase;
+ omap3_dss_panel_config(&panel_cfg);
+ /*
+ * Pixel clock is defined with many divisions and only few
+ * multiplications of the system clock. Since DSS FCLK divisor is set
+ * to 16 by default, we need to set it to a smaller value, like 3
+ * (chosen via trial and error).
+ */
+ clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
+}
+
+void lcd_enable(void)
+{
+ if (lcd_def == DVI || lcd_def == DVI_CUSTOM) {
+ gpio_direction_output(54, 0); /* Turn on DVI */
+ omap3_dss_enable();
+ }
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD))
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- } >.sram
-
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.data.rel.ro)
}
- . = ALIGN(4);
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
. = ALIGN(4);
__rel_dyn_start = .;
__rel_dyn_end = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN (4);
*(.dynsym)
}
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
+ _end = .;
+
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
- _end = .;
+ ___bssend___ = .;
}
- __bss_end__ =.;
+ .bss_end ___bssend___ (OVERLAY) : {
+ KEEP(*(.__bss_end__));
+ }
+
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
_end = .;
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
+ .bss_start __rel_dyn_start (OVERLAY) : {
+ KEEP(*(.__bss_start));
+ }
+
+ .bss __bss_start (OVERLAY) : {
+ *(.bss*)
. = ALIGN(4);
- __bss_end__ = .;
+ ___bssend___ = .;
+ }
+ .bss_end ___bssend___ (OVERLAY) : {
+ KEEP(*(.__bss_end__));
}
/DISCARD/ : { *(.bss*) }
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
.data :
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
.data :
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
.data :
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
.data :
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
.data :
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
.lcd_size = PANEL_LCD_SIZE(800, 480),
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
int board_video_init(void)
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
#include "post.h"
#endif
#include "common.h"
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
#include <i2c.h>
-#endif
#if !defined(CONFIG_MPC83xx)
static void i2c_write_start_seq(void);
}
#endif
-
-#if !defined(MACH_TYPE_KM_KIRKWOOD)
-int ethernet_present(void)
-{
- struct km_bec_fpga *base =
- (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
-
- return in_8(&base->bprth) & PIGGY_PRESENT;
-}
-#endif
-
int board_eth_init(bd_t *bis)
{
if (ethernet_present())
return 0;
}
+static int calculate_mac_offset(unsigned char *valbuf, unsigned char *buf,
+ int offset)
+{
+ unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
+
+ if (offset == 0)
+ return 0;
+
+ val += offset;
+ buf[4] = (val >> 16) & 0xff;
+ buf[5] = (val >> 8) & 0xff;
+ buf[6] = val & 0xff;
+ sprintf((char *)valbuf, "%pM", buf + 1);
+ return 0;
+}
+
static int ivm_analyze_block2(unsigned char *buf, int len)
{
unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
sprintf((char *)valbuf, "%pM", buf + 1);
ivm_set_value("IVM_MacAddress", (char *)valbuf);
/* if an offset is defined, add it */
-#if defined(CONFIG_PIGGY_MAC_ADRESS_OFFSET)
- if (CONFIG_PIGGY_MAC_ADRESS_OFFSET > 0) {
- unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6];
-
- val += CONFIG_PIGGY_MAC_ADRESS_OFFSET;
- buf[4] = (val >> 16) & 0xff;
- buf[5] = (val >> 8) & 0xff;
- buf[6] = val & 0xff;
- sprintf((char *)valbuf, "%pM", buf + 1);
- }
-#endif
+ calculate_mac_offset(buf, valbuf, CONFIG_PIGGY_MAC_ADRESS_OFFSET);
#ifdef MACH_TYPE_KM_KIRKWOOD
setenv((char *)"ethaddr", (char *)valbuf);
#else
if (getenv("ethaddr") == NULL)
setenv((char *)"ethaddr", (char *)valbuf);
#endif
-
+#ifdef CONFIG_KMVECT1
+/* KMVECT1 has two ethernet interfaces */
+ if (getenv("eth1addr") == NULL) {
+ calculate_mac_offset(buf, valbuf, 1);
+ setenv((char *)"eth1addr", (char *)valbuf);
+ }
+#endif
/* IVM_MacCount */
count = (buf[10] << 24) +
(buf[11] << 16) +
#if defined(CONFIG_I2C_MUX)
/* First init the Bus, select the Bus */
-#if defined(CONFIG_SYS_I2C_IVM_BUS)
- dev = i2c_mux_ident_muxstring((uchar *)CONFIG_SYS_I2C_IVM_BUS);
-#else
buf = (unsigned char *) getenv("EEprom_ivm");
if (buf != NULL)
dev = i2c_mux_ident_muxstring(buf);
-#endif
if (dev == NULL) {
printf("Error couldnt add Bus for IVM\n");
return -1;
}
i2c_set_bus_num(dev->busid);
#endif
-
- buf = (unsigned char *) getenv("EEprom_ivm_addr");
- if (buf != NULL) {
- ret = strict_strtoul((char *)buf, 16, &dev_addr);
- if (ret != 0)
- return -3;
- }
-
/* add deblocking here */
i2c_make_abort();
}
#endif
+int ethernet_present(void)
+{
+ struct km_bec_fpga *base =
+ (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
/*
* Early board initalization.
*/
static int board_init_i2c_busses(void)
{
I2C_MUX_DEVICE *dev = NULL;
- uchar *buf;
+ uchar *dtt_bus = (uchar *)"pca9547:70:a";
/* Set up the Bus for the DTTs */
- buf = (unsigned char *) getenv("dtt_bus");
- if (buf != NULL)
- dev = i2c_mux_ident_muxstring(buf);
- if (dev == NULL) {
+ dev = i2c_mux_ident_muxstring(dtt_bus);
+ if (dev == NULL)
printf("Error couldn't add Bus for DTT\n");
- printf("please setup dtt_bus to where your\n");
- printf("DTT is found.\n");
- }
+
return 0;
}
};
#endif
+static int piggy_present(void)
+{
+ struct km_bec_fpga __iomem *base =
+ (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+
+ return in_8(&base->bprth) & PIGGY_PRESENT;
+}
+
+#if defined(CONFIG_KMVECT1)
+int ethernet_present(void)
+{
+ /* ethernet port connected to simple switch without piggy */
+ return 1;
+}
+#else
+int ethernet_present(void)
+{
+ return piggy_present();
+}
+#endif
+
+
int board_early_init_r(void)
{
struct km_bec_fpga *base =
return 0;
}
+#if defined(CONFIG_KMVECT1)
+#include <mv88e6352.h>
+/* Marvell MV88E6122 switch configuration */
+static struct mv88e_sw_reg extsw_conf[] = {
+ /* port 1, FRONT_MDI, autoneg */
+ { PORT(1), PORT_PHY, NO_SPEED_FOR },
+ { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ { PHY(1), PHY_1000_CTRL, NO_ADV },
+ { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+ { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+ FULL_DUPLEX },
+ /* port 2, unused */
+ { PORT(2), PORT_CTRL, PORT_DIS },
+ { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+ { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+ /* port 3, BP_MII (CPU), PHY mode, 100BASE */
+ { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */
+ { PORT(4), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(4), PORT_PHY, SPEED_1000_FOR },
+ { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */
+ { PORT(5), PORT_STATUS, NO_PHY_DETECT },
+ { PORT(5), PORT_PHY, SPEED_1000_FOR },
+ { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+ /*
+ * Errata Fix: 1.9V Output from Internal 1.8V Regulator,
+ * acc . MV-S300889-00D.pdf , clause 4.5
+ */
+ { PORT(5), 0x1A, 0xADB1 },
+ /* port 6, unused, this port has no phy */
+ { PORT(6), PORT_CTRL, PORT_DIS },
+};
+#endif
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMVECT1)
+ struct km_bec_fpga __iomem *base =
+ (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
+ u8 tmp_reg;
+
+ /* Release mv88e6122 from reset */
+ tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */
+ out_8(&base->res1[0], tmp_reg); /* GP28 as output */
+ tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */
+ out_8(&base->gprt3, tmp_reg);
+
+ /* configure MV88E6122 switch */
+ char *name = "UEC2";
+
+ if (miiphy_set_current_dev(name))
+ return 0;
+
+ mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+ ARRAY_SIZE(extsw_conf));
+
+ mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+
+ if (piggy_present()) {
+ setenv("ethact", "UEC2");
+ setenv("netdev", "eth1");
+ puts("using PIGGY for network boot\n");
+ } else {
+ setenv("netdev", "eth0");
+ puts("using frontport for network boot\n");
+ }
+#endif
+
#if defined(CONFIG_KMCOGE5NE)
struct bfticu_iomap *base =
(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
{
puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
- if (ethernet_present())
+ if (piggy_present())
puts(" with PIGGY.");
puts("\n");
return 0;
altbootcmd=run ${subbootcmds}
bootcmd=run ${subbootcmds}
-configure=km_setboardid && saveenv && reset
+configure=run set_uimage; km_setboardid && saveenv && reset
subbootcmds=tftpfdt tftpkernel nfsargs add_default boot
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${toolchain}/${arch}
-tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage
+tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
toolchain=/opt/eldk
rootfssize=0
+set_uimage=printenv uimage || setenv uimage uImage
bootcmd=run ${subbootcmds}
subbootcmds=tftpfdt tftpkernel setrootfsaddr tftpramfs flashargs add_default addpanic addramfs boot
nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}
-configure=km_setboardid && saveenv && reset
+configure=run set_uimage; km_setboardid && saveenv && reset
rootfsfile=${hostname}/rootfsImage
setrootfsaddr=setexpr value ${pnvramaddr} - ${rootfssize} && setenv rootfsaddr 0x${value}
-tftpkernel=tftpboot ${load_addr_r} ${hostname}/uImage
+tftpkernel=tftpboot ${load_addr_r} ${hostname}/${uimage}
tftpramfs=tftpboot ${rootfsaddr} ${hostname}/rootfsImage
+set_uimage=printenv uimage || setenv uimage uImage
. = .;
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
*/
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
.rodata : {
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = .;
PROVIDE (_egot = .);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
PROVIDE (reloc_dst_end = .);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
PROVIDE (reloc_dst_end = .);
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
} >.sram
. = ALIGN(4);
. = align(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = align(4);
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
int spl_start_uboot(void)
{
int val = 0;
- if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) {
- gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY);
- val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY);
- gpio_free(CONFIG_SPL_OS_BOOT_KEY);
+ if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
+ gpio_direction_input(SPL_OS_BOOT_KEY);
+ val = gpio_get_value(SPL_OS_BOOT_KEY);
+ gpio_free(SPL_OS_BOOT_KEY);
}
return val;
}
#define XR16L2751_UART1_BASE 0x21000000
#define XR16L2751_UART2_BASE 0x23000000
+/* GPIO used to select between U-Boot and kernel */
+#define SPL_OS_BOOT_KEY 55
/*
* IEN - Input Enable
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
},
{
.timing_h = PANEL_TIMING_H(20, 192, 4),
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
.panel_color = 0,
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
}
};
#endif
!defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- return omap_mmc_init(0, 0, 0);
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
return !strncmp(header.config, "SKU#02", 6);
}
-static int board_is_gp_evm(void)
+static int __maybe_unused board_is_gp_evm(void)
{
return !strncmp("A33515BB", header.name, 8);
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
- .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */
+ .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
static const struct panel_config dvid_cfg_xm = {
.panel_type = 0x01, /* TFT */
.data_lines = 0x03, /* 24 Bit RGB */
.load_mode = 0x02, /* Frame Mode */
- .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */
+ .panel_color = DVI_BEAGLE_ORANGE_COL, /* ORANGE */
+ .gfx_format = GFXFORMAT_RGB24_UNPACKED,
};
#endif
--- /dev/null
+#
+# (C) Copyright 2013
+# Texas Instruments, <www.ti.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := evm.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * Based on previous work by:
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl6035.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
+
+#include "mux_data.h"
+
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/arch/ehci.h>
+#include <asm/ehci-omap.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct omap_sysinfo sysinfo = {
+ "Board: DRA7xx\n"
+};
+
+/**
+ * @brief board_init
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ gpmc_init();
+ gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+/**
+ * @brief misc_init_r - Configure EVM board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ return 0;
+}
+
+static void do_set_mux32(u32 base,
+ struct pad_conf_entry const *array, int size)
+{
+ int i;
+ struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
+
+ for (i = 0; i < size; i++, pad++)
+ writel(pad->val, base + pad->offset);
+}
+
+void set_muxconf_regs_essential(void)
+{
+ do_set_mux32((*ctrl)->control_padconf_core_base,
+ core_padconf_array_essential,
+ sizeof(core_padconf_array_essential) /
+ sizeof(struct pad_conf_entry));
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * Sricharan R <r.sricharan@ti.com>
+ * Nishant Kamat <nskamat@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MUX_DATA_DRA7XX_H_
+#define _MUX_DATA_DRA7XX_H_
+
+#include <asm/arch/mux_dra7xx.h>
+
+const struct pad_conf_entry core_padconf_array_essential[] = {
+ {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */
+ {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */
+ {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */
+ {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */
+ {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */
+ {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */
+ {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */
+ {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */
+ {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */
+ {UART1_TXD, (M0)}, /* UART1_TXD */
+ {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */
+ {UART1_RTSN, (M0)}, /* UART1_RTSN */
+ {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */
+ {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */
+};
+#endif /* _MUX_DATA_DRA7XX_H_ */
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#ifdef CONFIG_GENERIC_MMC
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- omap_mmc_init(1, 0, 0);
+ omap_mmc_init(0, 0, 0, -1, -1);
+ omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0, 0, 0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
int spl_start_uboot(void)
{
int val = 0;
- if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) {
- gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY);
- val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY);
- gpio_free(CONFIG_SPL_OS_BOOT_KEY);
+ if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
+ gpio_direction_input(SPL_OS_BOOT_KEY);
+ val = gpio_get_value(SPL_OS_BOOT_KEY);
+ gpio_free(SPL_OS_BOOT_KEY);
}
return !val;
}
"NAND",
};
+/* GPIO used to select between U-Boot and kernel */
+#define SPL_OS_BOOT_KEY 26
+
/*
* IEN - Input Enable
* IDIS - Input Disable
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
*(.data)
}
- .u_boot_list : {
- #include <u-boot.lst>
- }
-
. = ALIGN(4);
.rel.dyn : {
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ KEEP(*(SORT(.u_boot_list*)));
}
at91sam9g20ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0
at91sam9g20ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1
at91sam9g20ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH
+at91sam9g20ek_2mmc_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH
at91sam9m10g45ek_nandflash arm arm926ejs at91sam9m10g45ek atmel at91 at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH
at91sam9rlek_dataflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH
at91sam9rlek_nandflash arm arm926ejs at91sam9rlek atmel at91 at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH
am335x_evm_uart3 arm armv7 am335x ti am33xx am335x_evm:SERIAL4,CONS_INDEX=4
am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5
am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6
+am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT
pcm051 arm armv7 pcm051 phytec am33xx pcm051
highbank arm armv7 highbank - highbank
mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
omap4_panda arm armv7 panda ti omap4
omap4_sdp4430 arm armv7 sdp4430 ti omap4
omap5_evm arm armv7 omap5_evm ti omap5
+dra7xx_evm arm armv7 dra7xx ti omap5
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
origen arm armv7 origen samsung exynos
bf548-ezkit blackfin blackfin
bf561-acvilon blackfin blackfin
bf561-ezkit blackfin blackfin
+bf609-ezkit blackfin blackfin
blackstamp blackfin blackfin
blackvme blackfin blackfin
br4 blackfin blackfin
TQM834x powerpc mpc83xx tqm834x tqc
suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3
kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1
-tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,TUGE1
-tuxx1 powerpc mpc83xx km83xx keymile
-kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,KMSUPX5
+tuge1 powerpc mpc83xx km83xx keymile - tuxx1:TUGE1
+tuxx1 powerpc mpc83xx km83xx keymile - tuxx1:TUXX1
+kmopti2 powerpc mpc83xx km83xx keymile - tuxx1:KMOPTI2
+kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KMSUPX5
sbc8548 powerpc mpc85xx sbc8548 - - sbc8548
sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE
COBJS-$(CONFIG_CMD_READ) += cmd_read.o
COBJS-$(CONFIG_CMD_REGINFO) += cmd_reginfo.o
COBJS-$(CONFIG_CMD_REISER) += cmd_reiser.o
+COBJS-$(CONFIG_SANDBOX) += cmd_sandbox.o
COBJS-$(CONFIG_CMD_SATA) += cmd_sata.o
COBJS-$(CONFIG_CMD_SF) += cmd_sf.o
COBJS-$(CONFIG_CMD_SCSI) += cmd_scsi.o
#include <flash.h>
#include <mtd/cfi_flash.h>
extern flash_info_t flash_info[]; /* info for FLASH chips */
+#endif
+
+#if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND)
static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
+#include <linux/err.h>
+#include <nand.h>
+
#ifdef CONFIG_SILENT_CONSOLE
static void fixup_silent_linux(void);
#endif
/* Don't start if "autostart" is set to "no" */
if (((s = getenv("autostart")) != NULL) && (strcmp(s, "no") == 0)) {
- char buf[32];
- sprintf(buf, "%lX", images.os.image_len);
- setenv("filesize", buf);
+ setenv_hex("filesize", images.os.image_len);
return 0;
}
appl = (int (*)(int, char * const []))(ulong)ntohl(images.ep);
case BOOTM_STATE_RAMDISK:
{
ulong rd_len = images.rd_end - images.rd_start;
- char str[17];
ret = boot_ramdisk_high(&images.lmb, images.rd_start,
rd_len, &images.initrd_start, &images.initrd_end);
if (ret)
return ret;
- sprintf(str, "%lx", images.initrd_start);
- setenv("initrd_start", str);
- sprintf(str, "%lx", images.initrd_end);
- setenv("initrd_end", str);
+ setenv_hex("initrd_start", images.initrd_start);
+ setenv_hex("initrd_end", images.initrd_end);
}
break;
#endif
"issued in the order below (it's ok to not issue all sub-commands):\n"
"\tstart [addr [arg ...]]\n"
"\tloados - load OS image\n"
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC)
+#if defined(CONFIG_SYS_BOOT_RAMDISK_HIGH)
"\tramdisk - relocate initrd, set env initrd_start/initrd_end\n"
#endif
#if defined(CONFIG_OF_LIBFDT)
/* imls - list all images found in flash */
/*******************************************************************/
#if defined(CONFIG_CMD_IMLS)
-static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_imls_nor(void)
{
flash_info_t *info;
int i, j;
}
next_bank: ;
}
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_IMLS_NAND)
+static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
+ size_t len)
+{
+ void *imgdata;
+ int ret;
+
+ imgdata = malloc(len);
+ if (!imgdata) {
+ printf("May be a Legacy Image at NAND device %d offset %08llX:\n",
+ nand_dev, off);
+ printf(" Low memory(cannot allocate memory for image)\n");
+ return -ENOMEM;
+ }
+
+ ret = nand_read_skip_bad(nand, off, &len,
+ imgdata);
+ if (ret < 0 && ret != -EUCLEAN) {
+ free(imgdata);
+ return ret;
+ }
+
+ if (!image_check_hcrc(imgdata)) {
+ free(imgdata);
+ return 0;
+ }
+
+ printf("Legacy Image at NAND device %d offset %08llX:\n",
+ nand_dev, off);
+ image_print_contents(imgdata);
+
+ puts(" Verifying Checksum ... ");
+ if (!image_check_dcrc(imgdata))
+ puts("Bad Data CRC\n");
+ else
+ puts("OK\n");
+
+ free(imgdata);
+
+ return 0;
+}
+
+static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
+ size_t len)
+{
+ void *imgdata;
+ int ret;
+
+ imgdata = malloc(len);
+ if (!imgdata) {
+ printf("May be a FIT Image at NAND device %d offset %08llX:\n",
+ nand_dev, off);
+ printf(" Low memory(cannot allocate memory for image)\n");
+ return -ENOMEM;
+ }
+
+ ret = nand_read_skip_bad(nand, off, &len,
+ imgdata);
+ if (ret < 0 && ret != -EUCLEAN) {
+ free(imgdata);
+ return ret;
+ }
+
+ if (!fit_check_format(imgdata)) {
+ free(imgdata);
+ return 0;
+ }
+
+ printf("FIT Image at NAND device %d offset %08llX:\n", nand_dev, off);
+
+ fit_print_contents(imgdata);
+ free(imgdata);
+
+ return 0;
+}
+
+static int do_imls_nand(void)
+{
+ nand_info_t *nand;
+ int nand_dev = nand_curr_device;
+ size_t len;
+ loff_t off;
+ u32 buffer[16];
+
+ if (nand_dev < 0 || nand_dev >= CONFIG_SYS_MAX_NAND_DEVICE) {
+ puts("\nNo NAND devices available\n");
+ return -ENODEV;
+ }
+
+ printf("\n");
+
+ for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
+ nand = &nand_info[nand_dev];
+ if (!nand->name || !nand->size)
+ continue;
+
+ for (off = 0; off < nand->size; off += nand->erasesize) {
+ const image_header_t *header;
+ int ret;
+
+ if (nand_block_isbad(nand, off))
+ continue;
+
+ len = sizeof(buffer);
+
+ ret = nand_read(nand, off, &len, (u8 *)buffer);
+ if (ret < 0 && ret != -EUCLEAN) {
+ printf("NAND read error %d at offset %08llX\n",
+ ret, off);
+ continue;
+ }
+
+ switch (genimg_get_format(buffer)) {
+ case IMAGE_FORMAT_LEGACY:
+ header = (const image_header_t *)buffer;
+
+ len = image_get_image_size(header);
+ nand_imls_legacyimage(nand, nand_dev, off, len);
+ break;
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ len = fit_get_size(buffer);
+ nand_imls_fitimage(nand, nand_dev, off, len);
+ break;
+#endif
+ }
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_IMLS) || defined(CONFIG_CMD_IMLS_NAND)
+static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret_nor = 0, ret_nand = 0;
+
+#if defined(CONFIG_CMD_IMLS)
+ ret_nor = do_imls_nor();
+#endif
+
+#if defined(CONFIG_CMD_IMLS_NAND)
+ ret_nand = do_imls_nand();
+#endif
+
+ if (ret_nor)
+ return ret_nor;
+
+ if (ret_nand)
+ return ret_nand;
return (0);
}
imls, 1, 1, do_imls,
"list all images found in flash",
"\n"
- " - Prints information about all images found at sector\n"
- " boundaries in flash."
+ " - Prints information about all images found at sector/block\n"
+ " boundaries in nor/nand flash."
);
#endif
const struct cbfs_cachenode *file;
unsigned long offset;
unsigned long count;
- char buf[12];
long size;
if (argc < 3) {
printf("\n%ld bytes read\n", size);
- sprintf(buf, "%lX", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
return 0;
}
size = cramfs_load ((char *) offset, &part, filename);
if (size > 0) {
- char buf[10];
printf("### CRAMFS load complete: %d bytes loaded to 0x%lx\n",
size, offset);
- sprintf(buf, "%x", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
} else {
printf("### CRAMFS LOAD ERROR<%x> for %s!\n", size, filename);
}
* defaults to 0x4200
*/
tmp = getenv("bootaddr");
- if (tmp)
+ if (!tmp)
bootaddr = CONFIG_SYS_VXWORKS_BOOT_ADDR;
else
bootaddr = simple_strtoul(tmp, NULL, 16);
char *name;
char *ep;
int size;
- char buf [12];
int drive = CONFIG_SYS_FDC_DRIVE_NUMBER;
/* pre-set load_addr */
}
flush_cache (load_addr, size);
- sprintf(buf, "%x", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
printf("Floppy DOS load complete: %d bytes loaded to 0x%lx\n",
size, load_addr);
void set_working_fdt_addr(void *addr)
{
- char buf[17];
-
working_fdt = addr;
-
- sprintf(buf, "%lx", (unsigned long)addr);
- setenv("fdtaddr", buf);
+ setenv_addr("fdtaddr", addr);
}
/*
}
if (subcmd[0] == 's') {
/* get the num nodes at this level */
- char buf[11];
-
- sprintf(buf, "%d", curIndex + 1);
- setenv(var, buf);
+ setenv_ulong(var, curIndex + 1);
} else {
/* node index not found */
printf("libfdt node not found\n");
#include <part_efi.h>
#include <exports.h>
#include <linux/ctype.h>
+#include <div64.h>
#ifndef CONFIG_PARTITION_UUIDS
#error CONFIG_PARTITION_UUIDS must be enabled for CONFIG_CMD_GPT to be enabled
int p_count;
disk_partition_t *parts;
int errno = 0;
+ uint64_t size_ll, start_ll;
debug("%s: MMC lba num: 0x%x %d\n", __func__,
(unsigned int)dev_desc->lba, (unsigned int)dev_desc->lba);
}
if (extract_env(val, &p))
p = val;
- parts[i].size = ustrtoul(p, &p, 0);
- parts[i].size /= dev_desc->blksz;
+ size_ll = ustrtoull(p, &p, 0);
+ parts[i].size = lldiv(size_ll, dev_desc->blksz);
free(val);
/* start address */
if (val) { /* start address is optional */
if (extract_env(val, &p))
p = val;
- parts[i].start = ustrtoul(p, &p, 0);
- parts[i].start /= dev_desc->blksz;
+ start_ll = ustrtoull(p, &p, 0);
+ parts[i].start = lldiv(start_ll, dev_desc->blksz);
free(val);
}
}
#include <common.h>
#include <command.h>
#include <hash.h>
+#include <linux/ctype.h>
static int do_hash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ char *s;
#ifdef CONFIG_HASH_VERIFY
- int verify = 0;
+ int flags = HASH_FLAG_ENV;
+ if (argc < 4)
+ return CMD_RET_USAGE;
if (!strcmp(argv[1], "-v")) {
- verify = 1;
+ flags |= HASH_FLAG_VERIFY;
argc--;
argv++;
}
+#else
+ const int flags = HASH_FLAG_ENV;
#endif
/* Move forward to 'algorithm' parameter */
argc--;
argv++;
- return hash_command(*argv, verify, cmdtp, flag, argc - 1, argv + 1);
+ for (s = *argv; *s; s++)
+ *s = tolower(*s);
+ return hash_command(*argv, flags, cmdtp, flag, argc - 1, argv + 1);
}
#ifdef CONFIG_HASH_VERIFY
);
/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
-ll_entry_declare(cmd_tbl_t, question_mark, cmd, cmd) = {
+ll_entry_declare(cmd_tbl_t, question_mark, cmd) = {
"?", CONFIG_SYS_MAXARGS, 1, do_help,
"alias for 'help'",
#ifdef CONFIG_SYS_LONGHELP
}
if (size > 0) {
- char buf[10];
printf("### %s load complete: %d bytes loaded to 0x%lx\n",
fsname, size, offset);
- sprintf(buf, "%x", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
} else {
printf("### %s LOAD ERROR<%x> for %s!\n", fsname, size, filename);
}
int type; /* return code for record type */
ulong addr; /* load address from S-Record */
ulong size; /* number of bytes transferred */
- char buf[32];
ulong store_addr;
ulong start_addr = ~0;
ulong end_addr = 0;
start_addr, end_addr, size, size
);
flush_cache(start_addr, size);
- sprintf(buf, "%lX", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
return (addr);
case SREC_START:
break;
static ulong load_serial_bin(ulong offset)
{
int size, i;
- char buf[32];
set_kerm_bin_mode((ulong *) offset);
size = k_recv();
flush_cache(offset, size);
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
- sprintf(buf, "%X", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
return offset;
}
static ulong load_serial_ymodem(ulong offset)
{
int size;
- char buf[32];
int err;
int res;
connection_info_t info;
flush_cache(offset, size);
printf("## Total Size = 0x%08x = %d Bytes\n", size, size);
- sprintf(buf, "%X", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
return offset;
}
" - save S-Record file over serial line with offset 'off' and size 'size'"
);
#endif /* CONFIG_SYS_LOADS_BAUD_CHANGE */
-#endif
-#endif
+#endif /* CONFIG_CMD_SAVES */
+#endif /* CONFIG_CMD_LOADS */
#if defined(CONFIG_CMD_LOADB)
" with offset 'off' and baudrate 'baud'"
);
-#endif
+#endif /* CONFIG_CMD_LOADB */
/* -------------------------------------------------------------------- */
"[on|off]"
);
-#endif
+#endif /* CONFIG_CMD_HWFLOW */
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
#endif
+#include <hash.h>
#include <watchdog.h>
+#include <asm/io.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_MEMTEST_SCRATCH
+#define CONFIG_SYS_MEMTEST_SCRATCH 0
+#endif
+
static int mod_mem(cmd_tbl_t *, int, int, int, char * const []);
/* Display values from last command.
# endif
{
+ ulong bytes = size * length;
+ const void *buf = map_sysmem(addr, bytes);
+
/* Print the lines. */
- print_buffer(addr, (void*)addr, size, length, DISP_LINE_LEN/size);
- addr += size*length;
+ print_buffer(addr, buf, size, length, DISP_LINE_LEN / size);
+ addr += bytes;
+ unmap_sysmem(buf);
}
#endif
{
ulong addr, writeval, count;
int size;
+ void *buf;
+ ulong bytes;
if ((argc < 3) || (argc > 4))
return CMD_RET_USAGE;
count = 1;
}
+ bytes = size * count;
+ buf = map_sysmem(addr, bytes);
while (count-- > 0) {
if (size == 4)
- *((ulong *)addr) = (ulong )writeval;
+ *((ulong *)buf) = (ulong)writeval;
else if (size == 2)
- *((ushort *)addr) = (ushort)writeval;
+ *((ushort *)buf) = (ushort)writeval;
else
- *((u_char *)addr) = (u_char)writeval;
- addr += size;
+ *((u_char *)buf) = (u_char)writeval;
+ buf += size;
}
+ unmap_sysmem(buf);
return 0;
}
static int do_mem_cmp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr1, addr2, count, ngood;
+ ulong addr1, addr2, count, ngood, bytes;
int size;
int rcode = 0;
const char *type;
+ const void *buf1, *buf2, *base;
if (argc != 4)
return CMD_RET_USAGE;
}
#endif
+ bytes = size * count;
+ base = buf1 = map_sysmem(addr1, bytes);
+ buf2 = map_sysmem(addr2, bytes);
for (ngood = 0; ngood < count; ++ngood) {
ulong word1, word2;
if (size == 4) {
- word1 = *(ulong *)addr1;
- word2 = *(ulong *)addr2;
+ word1 = *(ulong *)buf1;
+ word2 = *(ulong *)buf2;
} else if (size == 2) {
- word1 = *(ushort *)addr1;
- word2 = *(ushort *)addr2;
+ word1 = *(ushort *)buf1;
+ word2 = *(ushort *)buf2;
} else {
- word1 = *(u_char *)addr1;
- word2 = *(u_char *)addr2;
+ word1 = *(u_char *)buf1;
+ word2 = *(u_char *)buf2;
}
if (word1 != word2) {
+ ulong offset = buf1 - base;
+
printf("%s at 0x%08lx (%#0*lx) != %s at 0x%08lx (%#0*lx)\n",
- type, addr1, size, word1,
- type, addr2, size, word2);
+ type, (ulong)(addr1 + offset), size, word1,
+ type, (ulong)(addr2 + offset), size, word2);
rcode = 1;
break;
}
- addr1 += size;
- addr2 += size;
+ buf1 += size;
+ buf2 += size;
/* reset watchdog from time to time */
if ((ngood % (64 << 10)) == 0)
WATCHDOG_RESET();
}
+ unmap_sysmem(buf1);
+ unmap_sysmem(buf2);
printf("Total of %ld %s(s) were the same\n", ngood, type);
return rcode;
static int do_mem_cp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr, dest, count;
+ ulong addr, dest, count, bytes;
int size;
+ const void *src;
+ void *buf;
if (argc != 4)
return CMD_RET_USAGE;
}
#endif
+ bytes = size * count;
+ buf = map_sysmem(addr, bytes);
+ src = map_sysmem(addr, bytes);
while (count-- > 0) {
if (size == 4)
- *((ulong *)dest) = *((ulong *)addr);
+ *((ulong *)buf) = *((ulong *)src);
else if (size == 2)
- *((ushort *)dest) = *((ushort *)addr);
+ *((ushort *)buf) = *((ushort *)src);
else
- *((u_char *)dest) = *((u_char *)addr);
- addr += size;
- dest += size;
+ *((u_char *)buf) = *((u_char *)src);
+ src += size;
+ buf += size;
/* reset watchdog from time to time */
if ((count % (64 << 10)) == 0)
static int do_mem_loop(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- ulong addr, length, i;
+ ulong addr, length, i, bytes;
int size;
volatile uint *longp;
volatile ushort *shortp;
volatile u_char *cp;
+ const void *buf;
if (argc < 3)
return CMD_RET_USAGE;
- /* Check for a size spefication.
+ /*
+ * Check for a size specification.
* Defaults to long if no or incorrect specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
*/
length = simple_strtoul(argv[2], NULL, 16);
+ bytes = size * length;
+ buf = map_sysmem(addr, bytes);
+
/* We want to optimize the loops to run as fast as possible.
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
if (size == 4) {
- longp = (uint *)addr;
+ longp = (uint *)buf;
for (;;)
i = *longp;
}
if (size == 2) {
- shortp = (ushort *)addr;
+ shortp = (ushort *)buf;
for (;;)
i = *shortp;
}
- cp = (u_char *)addr;
+ cp = (u_char *)buf;
for (;;)
i = *cp;
}
if (size == 4) {
for (;;) {
- longp = (uint *)addr;
+ longp = (uint *)buf;
i = length;
while (i-- > 0)
*longp++;
}
if (size == 2) {
for (;;) {
- shortp = (ushort *)addr;
+ shortp = (ushort *)buf;
i = length;
while (i-- > 0)
*shortp++;
}
}
for (;;) {
- cp = (u_char *)addr;
+ cp = (u_char *)buf;
i = length;
while (i-- > 0)
*cp++;
}
+ unmap_sysmem(buf);
}
#ifdef CONFIG_LOOPW
int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr, length, i, data;
+ ulong addr, length, i, data, bytes;
int size;
volatile uint *longp;
volatile ushort *shortp;
volatile u_char *cp;
+ void *buf;
if (argc < 4)
return CMD_RET_USAGE;
- /* Check for a size spefication.
+ /*
+ * Check for a size specification.
* Defaults to long if no or incorrect specification.
*/
if ((size = cmd_get_data_size(argv[0], 4)) < 0)
/* data to write */
data = simple_strtoul(argv[3], NULL, 16);
+ bytes = size * length;
+ buf = map_sysmem(addr, bytes);
+
/* We want to optimize the loops to run as fast as possible.
* If we have only one object, just run infinite loops.
*/
if (length == 1) {
if (size == 4) {
- longp = (uint *)addr;
+ longp = (uint *)buf;
for (;;)
*longp = data;
}
if (size == 2) {
- shortp = (ushort *)addr;
+ shortp = (ushort *)buf;
for (;;)
*shortp = data;
}
- cp = (u_char *)addr;
+ cp = (u_char *)buf;
for (;;)
*cp = data;
}
if (size == 4) {
for (;;) {
- longp = (uint *)addr;
+ longp = (uint *)buf;
i = length;
while (i-- > 0)
*longp++ = data;
}
if (size == 2) {
for (;;) {
- shortp = (ushort *)addr;
+ shortp = (ushort *)buf;
i = length;
while (i-- > 0)
*shortp++ = data;
}
}
for (;;) {
- cp = (u_char *)addr;
+ cp = (u_char *)buf;
i = length;
while (i-- > 0)
*cp++ = data;
}
#endif /* CONFIG_LOOPW */
-/*
- * Perform a memory test. A more complete alternative test can be
- * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
- * interrupted by ctrl-c or by a failure of one of the sub-tests.
- */
-static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
+ vu_long *dummy)
{
- vu_long *addr, *start, *end;
- ulong val;
- ulong readback;
- ulong errs = 0;
- int iterations = 1;
- int iteration_limit;
-
-#if defined(CONFIG_SYS_ALT_MEMTEST)
- vu_long len;
- vu_long offset;
- vu_long test_offset;
- vu_long pattern;
- vu_long temp;
- vu_long anti_pattern;
- vu_long num_words;
-#if defined(CONFIG_SYS_MEMTEST_SCRATCH)
- vu_long *dummy = (vu_long*)CONFIG_SYS_MEMTEST_SCRATCH;
-#else
- vu_long *dummy = NULL; /* yes, this is address 0x0, not NULL */
-#endif
- int j;
-
+ vu_long *addr;
+ ulong errs = 0;
+ ulong val, readback;
+ int j;
+ vu_long offset;
+ vu_long test_offset;
+ vu_long pattern;
+ vu_long temp;
+ vu_long anti_pattern;
+ vu_long num_words;
static const ulong bitpattern[] = {
0x00000001, /* single bit */
0x00000003, /* two adjacent bits */
0x00000055, /* four non-adjacent bits */
0xaaaaaaaa, /* alternating 1/0 */
};
-#else
- ulong incr;
- ulong pattern;
-#endif
-
- if (argc > 1)
- start = (ulong *)simple_strtoul(argv[1], NULL, 16);
- else
- start = (ulong *)CONFIG_SYS_MEMTEST_START;
- if (argc > 2)
- end = (ulong *)simple_strtoul(argv[2], NULL, 16);
- else
- end = (ulong *)(CONFIG_SYS_MEMTEST_END);
-
- if (argc > 3)
- pattern = (ulong)simple_strtoul(argv[3], NULL, 16);
- else
- pattern = 0;
-
- if (argc > 4)
- iteration_limit = (ulong)simple_strtoul(argv[4], NULL, 16);
- else
- iteration_limit = 0;
-
-#if defined(CONFIG_SYS_ALT_MEMTEST)
- printf ("Testing %08x ... %08x:\n", (uint)start, (uint)end);
- debug("%s:%d: start 0x%p end 0x%p\n",
- __FUNCTION__, __LINE__, start, end);
-
- for (;;) {
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
-
-
- if (iteration_limit && iterations > iteration_limit) {
- printf("Tested %d iteration(s) with %lu errors.\n",
- iterations-1, errs);
- return errs != 0;
- }
-
- printf("Iteration: %6d\r", iterations);
- debug("\n");
- iterations++;
-
- /*
- * Data line test: write a pattern to the first
- * location, write the 1's complement to a 'parking'
- * address (changes the state of the data bus so a
- * floating bus doen't give a false OK), and then
- * read the value back. Note that we read it back
- * into a variable because the next time we read it,
- * it might be right (been there, tough to explain to
- * the quality guys why it prints a failure when the
- * "is" and "should be" are obviously the same in the
- * error message).
- *
- * Rather than exhaustively testing, we test some
- * patterns by shifting '1' bits through a field of
- * '0's and '0' bits through a field of '1's (i.e.
- * pattern and ~pattern).
- */
- addr = start;
- for (j = 0; j < sizeof(bitpattern)/sizeof(bitpattern[0]); j++) {
- val = bitpattern[j];
- for(; val != 0; val <<= 1) {
- *addr = val;
- *dummy = ~val; /* clear the test data off of the bus */
+ num_words = (end_addr - start_addr) / sizeof(vu_long);
+
+ /*
+ * Data line test: write a pattern to the first
+ * location, write the 1's complement to a 'parking'
+ * address (changes the state of the data bus so a
+ * floating bus doesn't give a false OK), and then
+ * read the value back. Note that we read it back
+ * into a variable because the next time we read it,
+ * it might be right (been there, tough to explain to
+ * the quality guys why it prints a failure when the
+ * "is" and "should be" are obviously the same in the
+ * error message).
+ *
+ * Rather than exhaustively testing, we test some
+ * patterns by shifting '1' bits through a field of
+ * '0's and '0' bits through a field of '1's (i.e.
+ * pattern and ~pattern).
+ */
+ addr = buf;
+ for (j = 0; j < sizeof(bitpattern) / sizeof(bitpattern[0]); j++) {
+ val = bitpattern[j];
+ for (; val != 0; val <<= 1) {
+ *addr = val;
+ *dummy = ~val; /* clear the test data off the bus */
readback = *addr;
- if(readback != val) {
- printf ("FAILURE (data line): "
- "expected %08lx, actual %08lx\n",
- val, readback);
- errs++;
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
+ if (readback != val) {
+ printf("FAILURE (data line): "
+ "expected %08lx, actual %08lx\n",
+ val, readback);
+ errs++;
+ if (ctrlc())
+ return -1;
}
*addr = ~val;
*dummy = val;
readback = *addr;
- if(readback != ~val) {
- printf ("FAILURE (data line): "
- "Is %08lx, should be %08lx\n",
- readback, ~val);
- errs++;
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
+ if (readback != ~val) {
+ printf("FAILURE (data line): "
+ "Is %08lx, should be %08lx\n",
+ readback, ~val);
+ errs++;
+ if (ctrlc())
+ return -1;
}
- }
}
+ }
- /*
- * Based on code whose Original Author and Copyright
- * information follows: Copyright (c) 1998 by Michael
- * Barr. This software is placed into the public
- * domain and may be used for any purpose. However,
- * this notice must not be changed or removed and no
- * warranty is either expressed or implied by its
- * publication or distribution.
- */
+ /*
+ * Based on code whose Original Author and Copyright
+ * information follows: Copyright (c) 1998 by Michael
+ * Barr. This software is placed into the public
+ * domain and may be used for any purpose. However,
+ * this notice must not be changed or removed and no
+ * warranty is either expressed or implied by its
+ * publication or distribution.
+ */
- /*
- * Address line test
- *
- * Description: Test the address bus wiring in a
- * memory region by performing a walking
- * 1's test on the relevant bits of the
- * address and checking for aliasing.
- * This test will find single-bit
- * address failures such as stuck -high,
- * stuck-low, and shorted pins. The base
- * address and size of the region are
- * selected by the caller.
- *
- * Notes: For best results, the selected base
- * address should have enough LSB 0's to
- * guarantee single address bit changes.
- * For example, to test a 64-Kbyte
- * region, select a base address on a
- * 64-Kbyte boundary. Also, select the
- * region size as a power-of-two if at
- * all possible.
- *
- * Returns: 0 if the test succeeds, 1 if the test fails.
- */
- len = ((ulong)end - (ulong)start)/sizeof(vu_long);
- pattern = (vu_long) 0xaaaaaaaa;
- anti_pattern = (vu_long) 0x55555555;
+ /*
+ * Address line test
+
+ * Description: Test the address bus wiring in a
+ * memory region by performing a walking
+ * 1's test on the relevant bits of the
+ * address and checking for aliasing.
+ * This test will find single-bit
+ * address failures such as stuck-high,
+ * stuck-low, and shorted pins. The base
+ * address and size of the region are
+ * selected by the caller.
+
+ * Notes: For best results, the selected base
+ * address should have enough LSB 0's to
+ * guarantee single address bit changes.
+ * For example, to test a 64-Kbyte
+ * region, select a base address on a
+ * 64-Kbyte boundary. Also, select the
+ * region size as a power-of-two if at
+ * all possible.
+ *
+ * Returns: 0 if the test succeeds, 1 if the test fails.
+ */
+ pattern = (vu_long) 0xaaaaaaaa;
+ anti_pattern = (vu_long) 0x55555555;
- debug("%s:%d: length = 0x%.8lx\n",
- __FUNCTION__, __LINE__,
- len);
- /*
- * Write the default pattern at each of the
- * power-of-two offsets.
- */
- for (offset = 1; offset < len; offset <<= 1) {
- start[offset] = pattern;
- }
+ debug("%s:%d: length = 0x%.8lx\n", __func__, __LINE__, num_words);
+ /*
+ * Write the default pattern at each of the
+ * power-of-two offsets.
+ */
+ for (offset = 1; offset < num_words; offset <<= 1)
+ addr[offset] = pattern;
- /*
- * Check for address bits stuck high.
- */
- test_offset = 0;
- start[test_offset] = anti_pattern;
+ /*
+ * Check for address bits stuck high.
+ */
+ test_offset = 0;
+ addr[test_offset] = anti_pattern;
- for (offset = 1; offset < len; offset <<= 1) {
- temp = start[offset];
- if (temp != pattern) {
- printf ("\nFAILURE: Address bit stuck high @ 0x%.8lx:"
+ for (offset = 1; offset < num_words; offset <<= 1) {
+ temp = addr[offset];
+ if (temp != pattern) {
+ printf("\nFAILURE: Address bit stuck high @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx\n",
- (ulong)&start[offset], pattern, temp);
+ start_addr + offset, pattern, temp);
errs++;
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
- }
+ if (ctrlc())
+ return -1;
}
- start[test_offset] = pattern;
- WATCHDOG_RESET();
+ }
+ addr[test_offset] = pattern;
+ WATCHDOG_RESET();
- /*
- * Check for addr bits stuck low or shorted.
- */
- for (test_offset = 1; test_offset < len; test_offset <<= 1) {
- start[test_offset] = anti_pattern;
+ /*
+ * Check for addr bits stuck low or shorted.
+ */
+ for (test_offset = 1; test_offset < num_words; test_offset <<= 1) {
+ addr[test_offset] = anti_pattern;
- for (offset = 1; offset < len; offset <<= 1) {
- temp = start[offset];
+ for (offset = 1; offset < num_words; offset <<= 1) {
+ temp = addr[offset];
if ((temp != pattern) && (offset != test_offset)) {
- printf ("\nFAILURE: Address bit stuck low or shorted @"
- " 0x%.8lx: expected 0x%.8lx, actual 0x%.8lx\n",
- (ulong)&start[offset], pattern, temp);
- errs++;
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
+ printf("\nFAILURE: Address bit stuck low or"
+ " shorted @ 0x%.8lx: expected 0x%.8lx,"
+ " actual 0x%.8lx\n",
+ start_addr + offset, pattern, temp);
+ errs++;
+ if (ctrlc())
+ return -1;
}
- }
- start[test_offset] = pattern;
}
+ addr[test_offset] = pattern;
+ }
- /*
- * Description: Test the integrity of a physical
- * memory device by performing an
- * increment/decrement test over the
- * entire region. In the process every
- * storage bit in the device is tested
- * as a zero and a one. The base address
- * and the size of the region are
- * selected by the caller.
- *
- * Returns: 0 if the test succeeds, 1 if the test fails.
- */
- num_words = ((ulong)end - (ulong)start)/sizeof(vu_long) + 1;
+ /*
+ * Description: Test the integrity of a physical
+ * memory device by performing an
+ * increment/decrement test over the
+ * entire region. In the process every
+ * storage bit in the device is tested
+ * as a zero and a one. The base address
+ * and the size of the region are
+ * selected by the caller.
+ *
+ * Returns: 0 if the test succeeds, 1 if the test fails.
+ */
+ num_words++;
- /*
- * Fill memory with a known pattern.
- */
- for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
- WATCHDOG_RESET();
- start[offset] = pattern;
- }
+ /*
+ * Fill memory with a known pattern.
+ */
+ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
+ WATCHDOG_RESET();
+ addr[offset] = pattern;
+ }
- /*
- * Check each location and invert it for the second pass.
- */
- for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
- WATCHDOG_RESET();
- temp = start[offset];
- if (temp != pattern) {
- printf ("\nFAILURE (read/write) @ 0x%.8lx:"
+ /*
+ * Check each location and invert it for the second pass.
+ */
+ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
+ WATCHDOG_RESET();
+ temp = addr[offset];
+ if (temp != pattern) {
+ printf("\nFAILURE (read/write) @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx)\n",
- (ulong)&start[offset], pattern, temp);
+ start_addr + offset, pattern, temp);
errs++;
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
- }
-
- anti_pattern = ~pattern;
- start[offset] = anti_pattern;
+ if (ctrlc())
+ return -1;
}
- /*
- * Check each location for the inverted pattern and zero it.
- */
- for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
- WATCHDOG_RESET();
- anti_pattern = ~pattern;
- temp = start[offset];
- if (temp != anti_pattern) {
- printf ("\nFAILURE (read/write): @ 0x%.8lx:"
+ anti_pattern = ~pattern;
+ addr[offset] = anti_pattern;
+ }
+
+ /*
+ * Check each location for the inverted pattern and zero it.
+ */
+ for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
+ WATCHDOG_RESET();
+ anti_pattern = ~pattern;
+ temp = addr[offset];
+ if (temp != anti_pattern) {
+ printf("\nFAILURE (read/write): @ 0x%.8lx:"
" expected 0x%.8lx, actual 0x%.8lx)\n",
- (ulong)&start[offset], anti_pattern, temp);
+ start_addr + offset, anti_pattern, temp);
errs++;
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
- }
- start[offset] = 0;
+ if (ctrlc())
+ return -1;
}
+ addr[offset] = 0;
}
-#else /* The original, quickie test */
- incr = 1;
- for (;;) {
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
-
- if (iteration_limit && iterations > iteration_limit) {
- printf("Tested %d iteration(s) with %lu errors.\n",
- iterations-1, errs);
- return errs != 0;
- }
- ++iterations;
-
- printf ("\rPattern %08lX Writing..."
- "%12s"
- "\b\b\b\b\b\b\b\b\b\b",
- pattern, "");
-
- for (addr=start,val=pattern; addr<end; addr++) {
- WATCHDOG_RESET();
- *addr = val;
- val += incr;
- }
-
- puts ("Reading...");
+ return 0;
+}
- for (addr=start,val=pattern; addr<end; addr++) {
- WATCHDOG_RESET();
- readback = *addr;
- if (readback != val) {
- printf ("\nMem error @ 0x%08X: "
- "found %08lX, expected %08lX\n",
- (uint)(uintptr_t)addr, readback, val);
- errs++;
- if (ctrlc()) {
- putc ('\n');
- return 1;
- }
- }
- val += incr;
- }
+static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
+ vu_long pattern, int iteration)
+{
+ vu_long *end;
+ vu_long *addr;
+ ulong errs = 0;
+ ulong incr, length;
+ ulong val, readback;
+ /* Alternate the pattern */
+ incr = 1;
+ if (iteration & 1) {
+ incr = -incr;
/*
* Flip the pattern each time to make lots of zeros and
* then, the next time, lots of ones. We decrement
* the "negative" patterns and increment the "positive"
* patterns to preserve this feature.
*/
- if(pattern & 0x80000000) {
+ if (pattern & 0x80000000)
pattern = -pattern; /* complement & increment */
- }
- else {
+ else
pattern = ~pattern;
+ }
+ length = (end_addr - start_addr) / sizeof(ulong);
+ end = buf + length;
+ printf("\rPattern %08lX Writing..."
+ "%12s"
+ "\b\b\b\b\b\b\b\b\b\b",
+ pattern, "");
+
+ for (addr = buf, val = pattern; addr < end; addr++) {
+ WATCHDOG_RESET();
+ *addr = val;
+ val += incr;
+ }
+
+ puts("Reading...");
+
+ for (addr = buf, val = pattern; addr < end; addr++) {
+ WATCHDOG_RESET();
+ readback = *addr;
+ if (readback != val) {
+ ulong offset = addr - buf;
+
+ printf("\nMem error @ 0x%08X: "
+ "found %08lX, expected %08lX\n",
+ (uint)(uintptr_t)(start_addr + offset),
+ readback, val);
+ errs++;
+ if (ctrlc())
+ return -1;
}
- incr = -incr;
+ val += incr;
}
+
+ return 0;
+}
+
+/*
+ * Perform a memory test. A more complete alternative test can be
+ * configured using CONFIG_SYS_ALT_MEMTEST. The complete test loops until
+ * interrupted by ctrl-c or by a failure of one of the sub-tests.
+ */
+static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ ulong start, end;
+ vu_long *buf, *dummy;
+ int iteration_limit;
+ int ret;
+ ulong errs = 0; /* number of errors, or -1 if interrupted */
+ ulong pattern;
+ int iteration;
+#if defined(CONFIG_SYS_ALT_MEMTEST)
+ const int alt_test = 1;
+#else
+ const int alt_test = 0;
#endif
- return 0; /* not reached */
+
+ if (argc > 1)
+ start = simple_strtoul(argv[1], NULL, 16);
+ else
+ start = CONFIG_SYS_MEMTEST_START;
+
+ if (argc > 2)
+ end = simple_strtoul(argv[2], NULL, 16);
+ else
+ end = CONFIG_SYS_MEMTEST_END;
+
+ if (argc > 3)
+ pattern = (ulong)simple_strtoul(argv[3], NULL, 16);
+ else
+ pattern = 0;
+
+ if (argc > 4)
+ iteration_limit = (ulong)simple_strtoul(argv[4], NULL, 16);
+ else
+ iteration_limit = 0;
+
+ printf("Testing %08x ... %08x:\n", (uint)start, (uint)end);
+ debug("%s:%d: start %#08lx end %#08lx\n", __func__, __LINE__,
+ start, end);
+
+ buf = map_sysmem(start, end - start);
+ dummy = map_sysmem(CONFIG_SYS_MEMTEST_SCRATCH, sizeof(vu_long));
+ for (iteration = 0;
+ !iteration_limit || iteration < iteration_limit;
+ iteration++) {
+ if (ctrlc()) {
+ errs = -1UL;
+ break;
+ }
+
+ printf("Iteration: %6d\r", iteration + 1);
+ debug("\n");
+ if (alt_test) {
+ errs = mem_test_alt(buf, start, end, dummy);
+ } else {
+ errs = mem_test_quick(buf, start, end, pattern,
+ iteration);
+ }
+ if (errs == -1UL)
+ break;
+ }
+
+ /*
+ * Work-around for eldk-4.2 which gives this warning if we try to
+ * case in the unmap_sysmem() call:
+ * warning: initialization discards qualifiers from pointer target type
+ */
+ {
+ void *vbuf = (void *)buf;
+ void *vdummy = (void *)dummy;
+
+ unmap_sysmem(vbuf);
+ unmap_sysmem(vdummy);
+ }
+
+ if (errs == -1UL) {
+ /* Memory test was aborted - write a newline to finish off */
+ putc('\n');
+ ret = 1;
+ } else {
+ printf("Tested %d iteration(s) with %lu errors.\n",
+ iteration, errs);
+ ret = errs != 0;
+ }
+
+ return ret; /* not reached */
}
{
ulong addr, i;
int nbytes, size;
+ void *ptr = NULL;
if (argc != 2)
return CMD_RET_USAGE;
* the next value. A non-converted value exits.
*/
do {
+ ptr = map_sysmem(addr, size);
printf("%08lx:", addr);
if (size == 4)
- printf(" %08x", *((uint *)addr));
+ printf(" %08x", *((uint *)ptr));
else if (size == 2)
- printf(" %04x", *((ushort *)addr));
+ printf(" %04x", *((ushort *)ptr));
else
- printf(" %02x", *((u_char *)addr));
+ printf(" %02x", *((u_char *)ptr));
nbytes = readline (" ? ");
if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
reset_cmd_timeout();
#endif
if (size == 4)
- *((uint *)addr) = i;
+ *((uint *)ptr) = i;
else if (size == 2)
- *((ushort *)addr) = i;
+ *((ushort *)ptr) = i;
else
- *((u_char *)addr) = i;
+ *((u_char *)ptr) = i;
if (incrflag)
addr += size;
}
}
} while (nbytes);
+ if (ptr)
+ unmap_sysmem(ptr);
mm_last_addr = addr;
mm_last_size = size;
#ifdef CONFIG_CMD_CRC32
-#ifndef CONFIG_CRC32_VERIFY
-
static int do_mem_crc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong addr, length;
- ulong crc;
- ulong *ptr;
-
- if (argc < 3)
- return CMD_RET_USAGE;
-
- addr = simple_strtoul (argv[1], NULL, 16);
- addr += base_address;
-
- length = simple_strtoul (argv[2], NULL, 16);
-
- crc = crc32_wd (0, (const uchar *) addr, length, CHUNKSZ_CRC32);
-
- printf ("CRC32 for %08lx ... %08lx ==> %08lx\n",
- addr, addr + length - 1, crc);
-
- if (argc > 3) {
- ptr = (ulong *) simple_strtoul (argv[3], NULL, 16);
- *ptr = crc;
- }
-
- return 0;
-}
-
-#else /* CONFIG_CRC32_VERIFY */
-
-int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr, length;
- ulong crc;
- ulong *ptr;
- ulong vcrc;
- int verify;
+ int flags = 0;
int ac;
char * const *av;
- if (argc < 3) {
-usage:
+ if (argc < 3)
return CMD_RET_USAGE;
- }
av = argv + 1;
ac = argc - 1;
+#ifdef CONFIG_HASH_VERIFY
if (strcmp(*av, "-v") == 0) {
- verify = 1;
+ flags |= HASH_FLAG_VERIFY;
av++;
ac--;
- if (ac < 3)
- goto usage;
- } else
- verify = 0;
-
- addr = simple_strtoul(*av++, NULL, 16);
- addr += base_address;
- length = simple_strtoul(*av++, NULL, 16);
-
- crc = crc32_wd (0, (const uchar *) addr, length, CHUNKSZ_CRC32);
-
- if (!verify) {
- printf ("CRC32 for %08lx ... %08lx ==> %08lx\n",
- addr, addr + length - 1, crc);
- if (ac > 2) {
- ptr = (ulong *) simple_strtoul (*av++, NULL, 16);
- *ptr = crc;
- }
- } else {
- vcrc = simple_strtoul(*av++, NULL, 16);
- if (vcrc != crc) {
- printf ("CRC32 for %08lx ... %08lx ==> %08lx != %08lx ** ERROR **\n",
- addr, addr + length - 1, crc, vcrc);
- return 1;
- }
}
+#endif
- return 0;
-
+ return hash_command("crc32", flags, cmdtp, flag, ac, av);
}
-#endif /* CONFIG_CRC32_VERIFY */
#endif
mmc_init(mmc);
+ if ((state == MMC_WRITE || state == MMC_ERASE)) {
+ if (mmc_getwp(mmc) == 1) {
+ printf("Error: card is write protected!\n");
+ return 1;
+ }
+ }
+
switch (state) {
case MMC_READ:
n = mmc->block_dev.block_read(curr_device, blk,
*/
static void index_partitions(void)
{
- char buf[16];
u16 mtddevnum;
struct part_info *part;
struct list_head *dentry;
dev = list_entry(dentry, struct mtd_device, link);
if (dev == current_mtd_dev) {
mtddevnum += current_mtd_partnum;
- sprintf(buf, "%d", mtddevnum);
- setenv("mtddevnum", buf);
+ setenv_ulong("mtddevnum", mtddevnum);
break;
}
mtddevnum += dev->num_parts;
{
nand_info_t *nand = &nand_info[idx];
struct nand_chip *chip = nand->priv;
- char buf[32];
printf("Device %d: ", idx);
if (chip->numchips > 1)
printf(" Erase size %8d b\n", nand->erasesize);
/* Set geometry info */
- sprintf(buf, "%x", nand->writesize);
- setenv("nand_writesize", buf);
-
- sprintf(buf, "%x", nand->oobsize);
- setenv("nand_oobsize", buf);
-
- sprintf(buf, "%x", nand->erasesize);
- setenv("nand_erasesize", buf);
+ setenv_hex("nand_writesize", nand->writesize);
+ setenv_hex("nand_oobsize", nand->oobsize);
+ setenv_hex("nand_erasesize", nand->erasesize);
}
static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
size_t rwsize;
ulong pagecount = 1;
int read;
- int raw;
+ int raw = 0;
if (argc < 4)
goto usage;
}
/**
- * Set an environment variable to an address in hex
+ * Set an environment variable to an value in hex
*
* @param varname Environmet variable to set
- * @param addr Value to set it to
+ * @param value Value to set it to
* @return 0 if ok, 1 on error
*/
-int setenv_addr(const char *varname, const void *addr)
+int setenv_hex(const char *varname, ulong value)
{
char str[17];
- sprintf(str, "%lx", (uintptr_t)addr);
+ sprintf(str, "%lx", value);
return setenv(varname, str);
}
else
buffer[0] = '\0';
- readline_into_buffer("edit: ", buffer, 0);
+ if (readline_into_buffer("edit: ", buffer, 0) < 0)
+ return 1;
return setenv(argv[1], buffer);
}
envp->flags = ACTIVE_FLAG;
#endif
}
- sprintf(buf, "%zX", (size_t)(len + offsetof(env_t, data)));
- setenv("filesize", buf);
+ setenv_hex("filesize", len + offsetof(env_t, data));
return 0;
#elif defined(CONFIG_BLACKFIN)
puts("\nSystem Configuration registers\n");
-
+#ifndef __ADSPBF60x__
puts("\nPLL Registers\n");
printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif
+#else
+ puts("\nCGU Registers\n");
+ printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n",
+ bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
+ printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n",
+ bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());
+ puts("\nSMC DDR Registers\n");
+ printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n",
+ bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
+ printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n",
+ bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
+ printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n",
+ bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
+ printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n",
+ bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
+ printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
+#endif
#endif /* CONFIG_BLACKFIN */
return 0;
ulong addr = 0, filelen;
disk_partition_t info;
block_dev_desc_t *dev_desc = NULL;
- char buf [12];
unsigned long count;
char *addr_str;
load_addr = addr;
printf ("\n%ld bytes read\n", filelen);
- sprintf(buf, "%lX", filelen);
- setenv("filesize", buf);
+ setenv_hex("filesize", filelen);
return filelen;
}
--- /dev/null
+/*
+ * Copyright (c) 2012, Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fs.h>
+
+static int do_sandbox_load(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_load(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX, 16);
+}
+
+static int do_sandbox_ls(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ return do_ls(cmdtp, flag, argc, argv, FS_TYPE_SANDBOX);
+}
+
+static cmd_tbl_t cmd_sandbox_sub[] = {
+ U_BOOT_CMD_MKENT(load, 3, 0, do_sandbox_load, "", ""),
+ U_BOOT_CMD_MKENT(ls, 3, 0, do_sandbox_ls, "", ""),
+};
+
+static int do_sandbox(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ cmd_tbl_t *c;
+
+ /* Skip past 'sandbox' */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], cmd_sandbox_sub,
+ ARRAY_SIZE(cmd_sandbox_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ sb, 6, 1, do_sandbox,
+ "Miscellaneous sandbox commands",
+ "load host <addr> <filename> [<bytes> <offset>] - load a file from host\n"
+ "sb ls host <filename> - save a file to host"
+);
static int do_setexpr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong a, b;
- char buf[16];
+ ulong value;
int w;
/* Validate arguments */
a = get_arg(argv[2], w);
if (argc == 3) {
- sprintf(buf, "%lx", a);
- setenv(argv[1], buf);
+ setenv_hex(argv[1], a);
return 0;
}
b = get_arg(argv[4], w);
switch (argv[3][0]) {
- case '|': sprintf(buf, "%lx", (a | b)); break;
- case '&': sprintf(buf, "%lx", (a & b)); break;
- case '+': sprintf(buf, "%lx", (a + b)); break;
- case '^': sprintf(buf, "%lx", (a ^ b)); break;
- case '-': sprintf(buf, "%lx", (a - b)); break;
- case '*': sprintf(buf, "%lx", (a * b)); break;
- case '/': sprintf(buf, "%lx", (a / b)); break;
- case '%': sprintf(buf, "%lx", (a % b)); break;
+ case '|':
+ value = a | b;
+ break;
+ case '&':
+ value = a & b;
+ break;
+ case '+':
+ value = a + b;
+ break;
+ case '^':
+ value = a ^ b;
+ break;
+ case '-':
+ value = a - b;
+ break;
+ case '*':
+ value = a * b;
+ break;
+ case '/':
+ value = a / b;
+ break;
+ case '%':
+ value = a % b;
+ break;
default:
printf("invalid op\n");
return 1;
}
- setenv(argv[1], buf);
+ setenv_hex(argv[1], value);
return 0;
}
int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int verify = 0;
+ int flags = HASH_FLAG_ENV;
int ac;
char * const *av;
ac = argc - 1;
#ifdef CONFIG_SHA1SUM_VERIFY
if (strcmp(*av, "-v") == 0) {
- verify = 1;
+ flags |= HASH_FLAG_VERIFY;
av++;
ac--;
}
#endif
- return hash_command("sha1", verify, cmdtp, flag, ac, av);
+ return hash_command("sha1", flags, cmdtp, flag, ac, av);
}
#ifdef CONFIG_SHA1SUM_VERIFY
U_BOOT_CMD(
spl, 6 , 1, do_spl, "SPL configuration",
- "export <img=atags|fdt> [kernel_addr] [initrd_addr] "
- "[fdt_addr if <img> = fdt] - export a kernel parameter image\n"
- "\t initrd_img can be set to \"-\" if fdt_addr without initrd img is"
- "used");
+ "export <img=atags|fdt> [kernel_addr] [initrd_addr] [fdt_addr]\n"
+ "\timg\t\t\"atags\" or \"fdt\"\n"
+ "\tkernel_addr\taddress where a kernel image is stored.\n"
+ "\t\t\tkernel is loaded as part of the boot process, but it is not started.\n"
+ "\tinitrd_addr\taddress of initial ramdisk\n"
+ "\t\t\tcan be set to \"-\" if fdt_addr without initrd_addr is used.\n"
+ "\tfdt_addr\tin case of fdt, the address of the device tree.\n"
+ );
{
unsigned long src, dst;
unsigned long src_len = ~0UL, dst_len = ~0UL;
- char buf[32];
switch (argc) {
case 4:
return 1;
printf("Uncompressed size: %ld = 0x%lX\n", src_len, src_len);
- sprintf(buf, "%lX", src_len);
- setenv("filesize", buf);
+ setenv_hex("filesize", src_len);
return 0;
}
ulong data, len, count;
int verify;
int part = 0;
- char pbuf[10];
image_header_t *hdr;
#if defined(CONFIG_FIT)
const char *uname = NULL;
puts("OK\n");
}
- sprintf(pbuf, "%8lx", data);
- setenv("fileaddr", pbuf);
- sprintf(pbuf, "%8lx", len);
- setenv("filesize", pbuf);
+ setenv_hex("fileaddr", data);
+ setenv_hex("filesize", len);
return 0;
}
load_addr = addr;
printf("%llu bytes read\n", zfile.size);
- sprintf(buf, "%llX", zfile.size);
- setenv("filesize", buf);
+ setenv_hex("filesize", zfile.size);
return 0;
}
{
unsigned long src, dst;
unsigned long src_len, dst_len = ~0UL;
- char buf[32];
switch (argc) {
case 5:
return 1;
printf("Compressed size: %ld = 0x%lX\n", dst_len, dst_len);
- sprintf(buf, "%lX", dst_len);
- setenv("filesize", buf);
+ setenv_hex("filesize", dst_len);
return 0;
}
};
#ifdef CONFIG_NEEDS_MANUAL_RELOC
-void malloc_bin_reloc (void)
+static void malloc_bin_reloc(void)
{
mbinptr *p = &av_[2];
size_t i;
for (i = 2; i < ARRAY_SIZE(av_); ++i, ++p)
*p = (mbinptr)((ulong)*p + gd->reloc_off);
}
+#else
+static inline void malloc_bin_reloc(void) {}
#endif
ulong mem_malloc_start = 0;
mem_malloc_brk = start;
memset((void *)mem_malloc_start, 0, size);
+
+ malloc_bin_reloc();
}
/* field-extraction macros */
void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
+ int read1_fail = 0, read2_fail = 0;
int crc1_ok = 0, crc2_ok = 0;
env_t *ep, *tmp_env1, *tmp_env2;
goto done;
}
- if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1))
- puts("No Valid Environment Area found\n");
+ read1_fail = readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1);
+ read2_fail = readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2);
- if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2))
- puts("No Valid Redundant Environment Area found\n");
+ if (read1_fail && read2_fail)
+ puts("*** Error - No Valid Environment Area found\n");
+ else if (read1_fail || read2_fail)
+ puts("*** Warning - some problems detected "
+ "reading environment; recovered successfully\n");
- crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc;
- crc2_ok = crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc;
+ crc1_ok = !read1_fail &&
+ (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc);
+ crc2_ok = !read2_fail &&
+ (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc);
if (!crc1_ok && !crc2_ok) {
set_default_env("!bad CRC");
#include <hash.h>
#include <sha1.h>
#include <sha256.h>
+#include <asm/io.h>
/*
* These are the hash algorithms we support. Chips which support accelerated
- * crypto could perhaps add named version of these algorithms here.
+ * crypto could perhaps add named version of these algorithms here. Note that
+ * algorithm names must be in lower case.
*/
static struct hash_algo hash_algo[] = {
-#ifdef CONFIG_SHA1
+ /*
+ * This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise
+ * it bloats the code for boards which use SHA1 but not the 'hash'
+ * or 'sha1sum' commands.
+ */
+#ifdef CONFIG_CMD_SHA1SUM
{
- "SHA1",
+ "sha1",
SHA1_SUM_LEN,
sha1_csum_wd,
CHUNKSZ_SHA1,
},
+#define MULTI_HASH
#endif
#ifdef CONFIG_SHA256
{
- "SHA256",
+ "sha256",
SHA256_SUM_LEN,
sha256_csum_wd,
CHUNKSZ_SHA256,
},
+#define MULTI_HASH
#endif
+ {
+ "crc32",
+ 4,
+ crc32_wd_buf,
+ CHUNKSZ_CRC32,
+ },
};
+#if defined(CONFIG_HASH_VERIFY) || defined(CONFIG_CMD_HASH)
+#define MULTI_HASH
+#endif
+
+/* Try to minimize code size for boards that don't want much hashing */
+#ifdef MULTI_HASH
+#define multi_hash() 1
+#else
+#define multi_hash() 0
+#endif
+
/**
* store_result: Store the resulting sum to an address or variable
*
* @algo: Hash algorithm being used
* @sum: Hash digest (algo->digest_size bytes)
* @dest: Destination, interpreted as a hex address if it starts
- * with * or otherwise as an environment variable.
+ * with * (or allow_env_vars is 0) or otherwise as an
+ * environment variable.
+ * @allow_env_vars: non-zero to permit storing the result to an
+ * variable environment
*/
static void store_result(struct hash_algo *algo, const u8 *sum,
- const char *dest)
+ const char *dest, int allow_env_vars)
{
unsigned int i;
+ int env_var = 0;
- if (*dest == '*') {
- u8 *ptr;
+ /*
+ * If environment variables are allowed, then we assume that 'dest'
+ * is an environment variable, unless it starts with *, in which
+ * case we assume it is an address. If not allowed, it is always an
+ * address. This is to support the crc32 command.
+ */
+ if (allow_env_vars) {
+ if (*dest == '*')
+ dest++;
+ else
+ env_var = 1;
+ }
- ptr = (u8 *)simple_strtoul(dest + 1, NULL, 16);
- memcpy(ptr, sum, algo->digest_size);
- } else {
+ if (env_var) {
char str_output[HASH_MAX_DIGEST_SIZE * 2 + 1];
char *str_ptr = str_output;
}
str_ptr = '\0';
setenv(dest, str_output);
+ } else {
+ ulong addr;
+ void *buf;
+
+ addr = simple_strtoul(dest, NULL, 16);
+ buf = map_sysmem(addr, algo->digest_size);
+ memcpy(buf, sum, algo->digest_size);
+ unmap_sysmem(buf);
}
}
* Otherwise we assume it is an environment variable, and
* look up its value (it must contain a hex digest).
* @vsum: Returns binary digest value (algo->digest_size bytes)
+ * @allow_env_vars: non-zero to permit storing the result to an environment
+ * variable. If 0 then verify_str is assumed to be an
+ * address, and the * prefix is not expected.
* @return 0 if ok, non-zero on error
*/
-static int parse_verify_sum(struct hash_algo *algo, char *verify_str, u8 *vsum)
+static int parse_verify_sum(struct hash_algo *algo, char *verify_str, u8 *vsum,
+ int allow_env_vars)
{
- if (*verify_str == '*') {
- u8 *ptr;
+ int env_var = 0;
+
+ /* See comment above in store_result() */
+ if (allow_env_vars) {
+ if (*verify_str == '*')
+ verify_str++;
+ else
+ env_var = 1;
+ }
- ptr = (u8 *)simple_strtoul(verify_str + 1, NULL, 16);
- memcpy(vsum, ptr, algo->digest_size);
+ if (env_var) {
+ ulong addr;
+ void *buf;
+
+ addr = simple_strtoul(verify_str, NULL, 16);
+ buf = map_sysmem(addr, algo->digest_size);
+ memcpy(vsum, buf, algo->digest_size);
} else {
unsigned int i;
char *vsum_str;
int i;
for (i = 0; i < ARRAY_SIZE(hash_algo); i++) {
- if (!strcasecmp(name, hash_algo[i].name))
+ if (!strcmp(name, hash_algo[i].name))
return &hash_algo[i];
}
printf("%02x", output[i]);
}
-int hash_command(const char *algo_name, int verify, cmd_tbl_t *cmdtp, int flag,
+int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- struct hash_algo *algo;
ulong addr, len;
- u8 output[HASH_MAX_DIGEST_SIZE];
- u8 vsum[HASH_MAX_DIGEST_SIZE];
if (argc < 2)
return CMD_RET_USAGE;
- algo = find_hash_algo(algo_name);
- if (!algo) {
- printf("Unknown hash algorithm '%s'\n", algo_name);
- return CMD_RET_USAGE;
- }
addr = simple_strtoul(*argv++, NULL, 16);
len = simple_strtoul(*argv++, NULL, 16);
- argc -= 2;
- if (algo->digest_size > HASH_MAX_DIGEST_SIZE) {
- puts("HASH_MAX_DIGEST_SIZE exceeded\n");
- return 1;
- }
+ if (multi_hash()) {
+ struct hash_algo *algo;
+ u8 output[HASH_MAX_DIGEST_SIZE];
+ u8 vsum[HASH_MAX_DIGEST_SIZE];
+ void *buf;
- algo->hash_func_ws((const unsigned char *)addr, len, output,
- algo->chunk_size);
+ algo = find_hash_algo(algo_name);
+ if (!algo) {
+ printf("Unknown hash algorithm '%s'\n", algo_name);
+ return CMD_RET_USAGE;
+ }
+ argc -= 2;
- /* Try to avoid code bloat when verify is not needed */
+ if (algo->digest_size > HASH_MAX_DIGEST_SIZE) {
+ puts("HASH_MAX_DIGEST_SIZE exceeded\n");
+ return 1;
+ }
+
+ buf = map_sysmem(addr, len);
+ algo->hash_func_ws(buf, len, output, algo->chunk_size);
+ unmap_sysmem(buf);
+
+ /* Try to avoid code bloat when verify is not needed */
#ifdef CONFIG_HASH_VERIFY
- if (verify) {
+ if (flags & HASH_FLAG_VERIFY) {
#else
- if (0) {
+ if (0) {
#endif
- if (!argc)
- return CMD_RET_USAGE;
- if (parse_verify_sum(algo, *argv, vsum)) {
- printf("ERROR: %s does not contain a valid %s sum\n",
- *argv, algo->name);
- return 1;
- }
- if (memcmp(output, vsum, algo->digest_size) != 0) {
- int i;
+ if (!argc)
+ return CMD_RET_USAGE;
+ if (parse_verify_sum(algo, *argv, vsum,
+ flags & HASH_FLAG_ENV)) {
+ printf("ERROR: %s does not contain a valid "
+ "%s sum\n", *argv, algo->name);
+ return 1;
+ }
+ if (memcmp(output, vsum, algo->digest_size) != 0) {
+ int i;
+ show_hash(algo, addr, len, output);
+ printf(" != ");
+ for (i = 0; i < algo->digest_size; i++)
+ printf("%02x", vsum[i]);
+ puts(" ** ERROR **\n");
+ return 1;
+ }
+ } else {
show_hash(algo, addr, len, output);
- printf(" != ");
- for (i = 0; i < algo->digest_size; i++)
- printf("%02x", vsum[i]);
- puts(" ** ERROR **\n");
- return 1;
+ printf("\n");
+
+ if (argc) {
+ store_result(algo, output, *argv,
+ flags & HASH_FLAG_ENV);
+ }
}
+
+ /* Horrible code size hack for boards that just want crc32 */
} else {
- show_hash(algo, addr, len, output);
- printf("\n");
+ ulong crc;
+ ulong *ptr;
+
+ crc = crc32_wd(0, (const uchar *)addr, len, CHUNKSZ_CRC32);
- if (argc)
- store_result(algo, output, *argv);
+ printf("CRC32 for %08lx ... %08lx ==> %08lx\n",
+ addr, addr + len - 1, crc);
+
+ if (argc > 3) {
+ ptr = (ulong *)simple_strtoul(argv[3], NULL, 16);
+ *ptr = crc;
+ }
}
return 0;
#include <image.h>
#endif /* !USE_HOSTCC*/
+#include <u-boot/crc.h>
+
static const table_entry_t uimage_arch[] = {
{ IH_ARCH_INVALID, NULL, "Invalid ARCH", },
{ IH_ARCH_ALPHA, "alpha", "Alpha", },
{ -1, "", "", },
};
-uint32_t crc32(uint32_t, const unsigned char *, uint);
-uint32_t crc32_wd(uint32_t, const unsigned char *, uint, uint);
#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE) || defined(USE_HOSTCC)
static void genimg_print_time(time_t timestamp);
#endif
#include <common.h>
#include <command.h>
#include <stdarg.h>
+#include <search.h>
+#include <env_callback.h>
#include <linux/types.h>
#include <stdio_dev.h>
#if defined(CONFIG_POST)
}
#endif
+#ifdef CONFIG_SPLASH_SCREEN_PREPARE
+static inline int splash_screen_prepare(void)
+{
+ return board_splash_screen_prepare();
+}
+#else
+static inline int splash_screen_prepare(void)
+{
+ return 0;
+}
+#endif
+
static void *lcd_logo(void)
{
#ifdef CONFIG_SPLASH_SCREEN
int x = 0, y = 0;
do_splash = 0;
+ if (splash_screen_prepare())
+ return (void *)gd->fb_base;
+
addr = simple_strtoul (s, NULL, 16);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
s = getenv("splashpos");
#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */
}
+#ifdef CONFIG_SPLASHIMAGE_GUARD
+static int on_splashimage(const char *name, const char *value, enum env_op op,
+ int flags)
+{
+ ulong addr;
+ int aligned;
+
+ if (op == env_op_delete)
+ return 0;
+
+ addr = simple_strtoul(value, NULL, 16);
+ /* See README.displaying-bmps */
+ aligned = (addr % 4 == 2);
+ if (!aligned) {
+ printf("Invalid splashimage value. Value must be 16 bit aligned, but not 32 bit aligned\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+U_BOOT_ENV_CALLBACK(splashimage, on_splashimage);
+#endif
+
void lcd_position_cursor(unsigned col, unsigned row)
{
console_col = min(col, CONSOLE_COLS - 1);
COBJS-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+COBJS-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
endif
spl_nand_load_image();
break;
#endif
+#ifdef CONFIG_SPL_ONENAND_SUPPORT
+ case BOOT_DEVICE_ONENAND:
+ spl_onenand_load_image();
+ break;
+#endif
#ifdef CONFIG_SPL_NOR_SUPPORT
case BOOT_DEVICE_NOR:
spl_nor_load_image();
--- /dev/null
+/*
+ * Copyright (C) 2013
+ * ISEE 2007 SL - Enric Balletbo i Serra <eballetbo@iseebcn.com>
+ *
+ * Based on common/spl/spl_nand.c
+ * Copyright (C) 2011
+ * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <config.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <onenand_uboot.h>
+
+void spl_onenand_load_image(void)
+{
+ struct image_header *header;
+
+ debug("spl: onenand\n");
+
+ /*use CONFIG_SYS_TEXT_BASE as temporary storage area */
+ header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
+ /* Load u-boot */
+ onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
+ CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header);
+ spl_parse_image_header(header);
+ onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS,
+ spl_image.size, (void *)spl_image.load_addr);
+}
#########################################################################
-include $(TOPDIR)/helper.mk
-
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
int part;
disk_partition_t tmpinfo;
+ /*
+ * For now, we have a special case for sandbox, since there is no
+ * real block device support.
+ */
+ if (0 == strcmp(ifname, "host")) {
+ *dev_desc = NULL;
+ info->start = info->size = info->blksz = 0;
+ info->bootable = 0;
+ strcpy((char *)info->type, BOOT_PART_TYPE);
+ strcpy((char *)info->name, "Sandbox host");
+#ifdef CONFIG_PARTITION_UUIDS
+ info->uuid[0] = 0;
+#endif
+
+ return 0;
+ }
+
/* If no dev_part_str, use bootdevice environment variable */
if (!dev_part_str || !strlen(dev_part_str) ||
!strcmp(dev_part_str, "-"))
**** Behind the scene ******
-The structure created is named with a special prefix (__u_boot_list_cmd_)
-and placed by the linker in a special section.
+The structure created is named with a special prefix and placed by
+the linker in a special section using the linker lists mechanism
+(see include/linker_lists.h)
This makes it possible for the final link to extract all commands
compiled into any object code and construct a static array so the
-command can be found in an array starting at _u_boot_list_cmd__start.
+command array can be iterated over using the linker lists macros.
-To ensure that the linker does not discard these symbols when linking
-full U-Boot we generate a list of all the commands we have built (based
-on the sections mentioned above) and use that to force the linker to
-first enter the symbol as undefined in the output object so that there
-is then a need for the symbol to be kept (this is the UNDEF_SYM logic in
-the Makefile).
+The linker lists feature ensures that the linker does not discard
+these symbols when linking full U-Boot even though they are not
+referenced in the source code as such.
If a new board is defined do not forget to define the command section
by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these
3 lines:
.u_boot_list : {
- #include "u-boot.lst";
+ KEEP(*(SORT(.u_boot_list*)));
}
--- /dev/null
+If you are experiencing hangups/data-aborts when trying to display a BMP image,
+the following might be relevant to your situation...
+
+Some architectures cannot handle unaligned memory accesses, and an attempt to
+perform one will lead to a data abort. On such architectures it is necessary to
+make sure all data is properly aligned, and in many situations simply choosing
+a 32 bit aligned address is enough to ensure proper alignment. This is not
+always the case when dealing with data that has an internal layout such as a
+BMP image:
+
+BMP images have a header that starts with 2 byte-size fields followed by mostly
+32 bit fields. The packed struct that represents this header can be seen below:
+
+typedef struct bmp_header {
+ /* Header */
+ char signature[2];
+ __u32 file_size;
+ __u32 reserved;
+ __u32 data_offset;
+ ... etc
+} __attribute__ ((packed)) bmp_header_t;
+
+When placed in an aligned address such as 0x80a00000, char signature offsets
+the __u32 fields into unaligned addresses (in our example 0x80a00002,
+0x80a00006, and so on...). When these fields are accessed by U-Boot, a 32 bit
+access is generated at a non-32-bit-aligned address, causing a data abort.
+The proper alignment for BMP images is therefore: 32-bit-aligned-address + 2.
--- /dev/null
+U-Boot Falcon Mode
+====================
+
+Introduction
+------------
+
+This document provides an overview of how to add support for Falcon Mode
+to a board.
+
+Falcon Mode is introduced to speed up the booting process, allowing
+to boot a Linux kernel (or whatever image) without a full blown U-Boot.
+
+Falcon Mode relies on the SPL framework. In fact, to make booting faster,
+U-Boot is split into two parts: the SPL (Secondary Program Loader) and U-Boot
+image. In most implementations, SPL is used to start U-Boot when booting from
+a mass storage, such as NAND or SD-Card. SPL has now support for other media,
+and can generally be seen as a way to start an image performing the minimum
+required initialization. SPL mainly initializes the RAM controller, and then
+copies U-Boot image into the memory.
+
+The Falcon Mode extends this way allowing to start the Linux kernel directly
+from SPL. A new command is added to U-Boot to prepare the parameters that SPL
+must pass to the kernel, using ATAGS or Device Tree.
+
+In normal mode, these parameters are generated each time before
+loading the kernel, passing to Linux the address in memory where
+the parameters can be read.
+With Falcon Mode, this snapshot can be saved into persistent storage and SPL is
+informed to load it before running the kernel.
+
+To boot the kernel, these steps under a Falcon-aware U-Boot are required:
+
+1. Boot the board into U-Boot.
+Use the "spl export" command to generate the kernel parameters area or the DT.
+U-Boot runs as when it boots the kernel, but stops before passing the control
+to the kernel.
+
+2. Save the prepared snapshot into persistent media.
+The address where to save it must be configured into board configuration
+file (CONFIG_CMD_SPL_NAND_OFS for NAND).
+
+3. Boot the board into Falcon Mode. SPL will load the kernel and copy
+the parameters which are saved in the persistent area to the required address.
+
+It is required to implement a custom mechanism to select if SPL loads U-Boot
+or another image.
+
+The value of a GPIO is a simple way to operate the selection, as well as
+reading a character from the SPL console if CONFIG_SPL_CONSOLE is set.
+
+Falcon Mode is generally activated by setting CONFIG_SPL_OS_BOOT. This tells
+SPL that U-Boot is not the only available image that SPL is able to start.
+
+Configuration
+----------------------------
+CONFIG_CMD_SPL Enable the "spl export" command.
+ The command "spl export" is then available in U-Boot
+ mode
+CONFIG_SYS_SPL_ARGS_ADDR Address in RAM where the parameters must be
+ copied by SPL.
+ In most cases, it is <start_of_ram> + 0x100
+
+CONFIG_SYS_NAND_SPL_KERNEL_OFFS Offset in NAND where the kernel is stored
+
+CONFIG_CMD_SPL_NAND_OFS Offset in NAND where the parameters area was saved.
+
+CONFIG_CMD_SPL_WRITE_SIZE Size of the parameters area to be copied
+
+CONFIG_SPL_OS_BOOT Activate Falcon Mode.
+
+Function that a board must implement
+------------------------------------
+
+void spl_board_prepare_for_linux(void) : optional
+ Called from SPL before starting the kernel
+
+spl_start_uboot() : required
+ Returns "0" if SPL should start the kernel, "1" if U-Boot
+ must be started.
+
+
+Using spl command
+-----------------
+
+spl - SPL configuration
+
+Usage:
+
+spl export <img=atags|fdt> [kernel_addr] [initrd_addr] [fdt_addr ]
+
+img : "atags" or "fdt"
+kernel_addr : kernel is loaded as part of the boot process, but it is not started.
+ This is the address where a kernel image is stored.
+initrd_addr : Address of initial ramdisk
+ can be set to "-" if fdt_addr without initrd_addr is used
+fdt_addr : in case of fdt, the address of the device tree.
+
+The spl export command does not write to a storage media. The user is
+responsible to transfer the gathered information (assembled ATAGS list
+or prepared FDT) from temporary storage in RAM into persistant storage
+after each run of 'spl export'. Unfortunately the position of temporary
+storage can not be predicted nor provided at commandline, it depends
+highly on your system setup and your provided data (ATAGS or FDT).
+However at the end of an succesful 'spl export' run it will print the
+RAM address of temporary storage.
+Now the user have to save the generated BLOB from that printed address
+to the pre-defined address in persistent storage
+(CONFIG_CMD_SPL_NAND_OFS in case of NAND).
+The following example shows how to prepare the data for Falcon Mode on
+twister board with ATAGS BLOB.
+
+The "spl export" command is prepared to work with ATAGS and FDT. However,
+using FDT is at the moment untested. The ppc port (see a3m071 example
+later) prepares the fdt blob with the fdt command instead.
+
+
+Usage on the twister board:
+--------------------------------
+
+Using mtd names with the following (default) configuration
+for mtdparts:
+
+device nand0 <omap2-nand.0>, # parts = 9
+ #: name size offset mask_flags
+ 0: MLO 0x00080000 0x00000000 0
+ 1: u-boot 0x00100000 0x00080000 0
+ 2: env1 0x00040000 0x00180000 0
+ 3: env2 0x00040000 0x001c0000 0
+ 4: kernel 0x00600000 0x00200000 0
+ 5: bootparms 0x00040000 0x00800000 0
+ 6: splashimg 0x00200000 0x00840000 0
+ 7: mini 0x02800000 0x00a40000 0
+ 8: rootfs 0x1cdc0000 0x03240000 0
+
+
+twister => nand read 82000000 kernel
+
+NAND read: device 0 offset 0x200000, size 0x600000
+ 6291456 bytes read: OK
+
+Now the kernel is in RAM at address 0x82000000
+
+twister => spl export atags 0x82000000
+## Booting kernel from Legacy Image at 82000000 ...
+ Image Name: Linux-3.5.0-rc4-14089-gda0b7f4
+ Image Type: ARM Linux Kernel Image (uncompressed)
+ Data Size: 3654808 Bytes = 3.5 MiB
+ Load Address: 80008000
+ Entry Point: 80008000
+ Verifying Checksum ... OK
+ Loading Kernel Image ... OK
+OK
+cmdline subcommand not supported
+bdt subcommand not supported
+Argument image is now in RAM at: 0x80000100
+
+The result can be checked at address 0x80000100:
+
+twister => md 0x80000100
+80000100: 00000005 54410001 00000000 00000000 ......AT........
+80000110: 00000000 00000067 54410009 746f6f72 ....g.....ATroot
+80000120: 65642f3d 666e2f76 77722073 73666e20 =/dev/nfs rw nfs
+
+The parameters generated with this step can be saved into NAND at the offset
+0x800000 (value for twister for CONFIG_CMD_SPL_NAND_OFS)
+
+nand erase.part bootparms
+nand write 0x80000100 bootparms 0x4000
+
+Now the parameters are stored into the NAND flash at the address
+CONFIG_CMD_SPL_NAND_OFS (=0x800000).
+
+Next time, the board can be started into Falcon Mode moving the
+setting the gpio (on twister gpio 55 is used) to kernel mode.
+
+The kernel is loaded directly by the SPL without passing through U-Boot.
+
+Example with FDT: a3m071 board
+-------------------------------
+
+To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
+prepard/patched first. U-Boot usually inserts some dynamic values into
+the DT binary (blob), e.g. autodetected memory size, MAC addresses,
+clocks speeds etc. To generate this patched DT blob, you can use
+the following command:
+
+1. Load fdt blob to SDRAM:
+=> tftp 1800000 a3m071/a3m071.dtb
+
+2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
+=> run mtdargs addip2 addtty
+
+3. Use "fdt" commands to patch the DT blob:
+=> fdt addr 1800000
+=> fdt boardsetup
+=> fdt chosen
+
+4. Display patched DT blob (optional):
+=> fdt print
+
+5. Save fdt to NOR flash:
+=> erase fc060000 fc07ffff
+=> cp.b 1800000 fc060000 10000
+...
+
+
+Falcon Mode was presented at the RMLL 2012. Slides are available at:
+
+http://schedule2012.rmll.info/IMG/pdf/LSM2012_UbootFalconMode_Babic.pdf
alias scottwood Scott Wood <scottwood@freescale.com>
alias sjg Simon Glass <sjg@chromium.org>
alias smcnutt Scott McNutt <smcnutt@psyent.com>
+alias sonic Sonic Zhang <sonic.adi@gmail.com>
alias stroese Stefan Roese <sr@denx.de>
alias vapier Mike Frysinger <vapier@gentoo.org>
alias wd Wolfgang Denk <wd@denx.de>
alias avr32 uboot, abiessmann
-alias bfin uboot, vapier
+alias bfin uboot, vapier, sonic
alias blackfin bfin
alias m68k uboot, jasonjin
COBJS-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
COBJS-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
+COBJS-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
COBJS-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o
char name[GPIO_NAME_SIZE];
} gpio_registry[MAX_NUM_GPIOS];
+#if defined(CONFIG_SOC_DA8XX)
#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
#if defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
{ pinmux(0), 1, 0 },
{ pinmux(0), 1, 1 },
};
-#else
+#else /* CONFIG_SOC_DA8XX && CONFIG_SOC_DA850 */
static const struct pinmux_config gpio_pinmux[] = {
{ pinmux(1), 8, 7 }, /* GP0[0] */
{ pinmux(1), 8, 6 },
{ pinmux(18), 8, 3 },
{ pinmux(18), 8, 2 },
};
-#endif
+#endif /* CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850 */
+#else /* !CONFIG_SOC_DA8XX */
+#define davinci_configure_pin_mux(a, b)
+#endif /* CONFIG_SOC_DA8XX */
int gpio_request(unsigned gpio, const char *label)
{
dev->set_ios = host_set_ios;
dev->init = mmc_host_reset;
dev->getcd = NULL;
+ dev->getwp = NULL;
dev->host_caps = host->caps;
dev->voltages = host->voltages;
dev->f_min = host->clock_min;
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>
-#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
-# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
-# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
+#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__)
# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
+# if defined(__ADSPBF60x__)
+# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
+# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
+# define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR
+# define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT
+# define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY
+# define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG
+# else
+# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
+# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
+# endif
# define PORTMUX_PINS \
{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
#elif defined(__ADSPBF54x__)
sdh_cmd |= CMD_RSP;
if (flags & MMC_RSP_136)
sdh_cmd |= CMD_L_RSP;
+#ifdef RSI_BLKSZ
+ sdh_cmd |= CMD_DATA0_BUSY;
+#endif
bfin_write_SDH_ARGUMENT(arg);
bfin_write_SDH_COMMAND(sdh_cmd);
bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
+#ifdef RSI_BLKSZ
+ /* wait till card ready */
+ while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
+ continue;
+ bfin_write_RSI_ESTAT(SD_CARD_READY);
+#endif
return ret;
}
{
u16 data_ctl = 0;
u16 dma_cfg = 0;
- int ret = 0;
unsigned long data_size = data->blocksize * data->blocks;
/* Don't support write yet. */
if (data->flags & MMC_DATA_WRITE)
return UNUSABLE_ERR;
+#ifndef RSI_BLKSZ
data_ctl |= ((ffs(data_size) - 1) << 4);
+#else
+ bfin_write_SDH_BLK_SIZE(data_size);
+#endif
data_ctl |= DTX_DIR;
bfin_write_SDH_DATA_CTL(data_ctl);
- dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
+ dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN;
bfin_write_SDH_DATA_TIMER(-1);
/* kick off transfer */
bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
- return ret;
+ return 0;
}
u32 status;
int ret = 0;
+ if (data) {
+ ret = sdh_setup_data(mmc, data);
+ if (ret)
+ return ret;
+ }
+
ret = sdh_send_cmd(mmc, cmd);
if (ret) {
+ bfin_write_SDH_COMMAND(0);
+ bfin_write_DMA_CONFIG(0);
+ bfin_write_SDH_DATA_CTL(0);
+ SSYNC();
printf("sending CMD%d failed\n", cmd->cmdidx);
return ret;
}
+
if (data) {
- ret = sdh_setup_data(mmc, data);
do {
udelay(1);
status = bfin_read_SDH_STATUS();
if (mmc->bus_width == 4) {
cfg = bfin_read_SDH_CFG();
- cfg &= ~0x80;
- cfg |= 0x40;
+#ifndef RSI_BLKSZ
+ cfg &= ~PD_SDDAT3;
+#endif
+ cfg |= PUP_SDDAT3;
bfin_write_SDH_CFG(cfg);
- clk_ctl |= WIDE_BUS;
+ clk_ctl |= WIDE_BUS_4;
}
bfin_write_SDH_CLK_CTL(clk_ctl);
sdh_set_clk(mmc->clock);
static int bfin_sdh_init(struct mmc *mmc)
{
const unsigned short pins[] = PORTMUX_PINS;
- u16 pwr_ctl = 0;
+ int ret;
/* Initialize sdh controller */
- peripheral_request_list(pins, "bfin_sdh");
+ ret = peripheral_request_list(pins, "bfin_sdh");
+ if (ret < 0)
+ return ret;
#if defined(__ADSPBF54x__)
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
#endif
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
/* Disable card detect pin */
bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
-
- pwr_ctl |= ROD_CTL;
- pwr_ctl |= PWR_ON;
- bfin_write_SDH_PWR_CTL(pwr_ctl);
+#ifndef RSI_BLKSZ
+ bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL);
+#else
+ bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON);
+#endif
return 0;
}
mmc->set_ios = bfin_sdh_set_ios;
mmc->init = bfin_sdh_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
mmc->host_caps = MMC_MODE_4BIT;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->set_ios = dmmc_set_ios;
mmc->init = dmmc_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
mmc->f_min = 200000;
mmc->f_max = 25000000;
mmc->set_ios = esdhc_set_ios;
mmc->init = esdhc_init;
mmc->getcd = esdhc_getcd;
+ mmc->getwp = NULL;
voltage_caps = 0;
caps = regs->hostcapblt;
mmc->set_ios = ftsdc010_set_ios;
mmc->init = ftsdc010_core_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->set_ios = mci_set_ios;
mmc->init = mci_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
/* need to be able to pass these in on a board by board basis */
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
static struct list_head mmc_devices;
static int cur_dev_num = -1;
+int __weak board_mmc_getwp(struct mmc *mmc)
+{
+ return -1;
+}
+
+int mmc_getwp(struct mmc *mmc)
+{
+ int wp;
+
+ wp = board_mmc_getwp(mmc);
+
+ if ((wp < 0) && mmc->getwp)
+ wp = mmc->getwp(mmc);
+
+ return wp;
+}
+
int __board_mmc_getcd(struct mmc *mmc) {
return -1;
}
mmc->set_ios = mmc_spi_set_ios;
mmc->init = mmc_spi_init_p;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
mmc->host_caps = MMC_MODE_SPI;
mmc->voltages = MMC_SPI_VOLTAGE;
mmc->set_ios = mxcmci_set_ios;
mmc->init = mxcmci_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
mmc->host_caps = MMC_MODE_4BIT;
host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
mmc->set_ios = mxsmmc_set_ios;
mmc->init = mxsmmc_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
mmc->priv = priv;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#include <twl4030.h>
#include <twl6030.h>
#include <twl6035.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#define SYSCTL_SRC (1 << 25)
#define SYSCTL_SRD (1 << 26)
+struct omap_hsmmc_data {
+ struct hsmmc *base_addr;
+ int cd_gpio;
+ int wp_gpio;
+};
+
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int siz);
-static struct mmc hsmmc_dev[2];
+static struct mmc hsmmc_dev[3];
+static struct omap_hsmmc_data hsmmc_dev_data[3];
+
+#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
+ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
+static int omap_mmc_setup_gpio_in(int gpio, const char *label)
+{
+ if (!gpio_is_valid(gpio))
+ return -1;
+
+ if (gpio_request(gpio, label) < 0)
+ return -1;
+
+ if (gpio_direction_input(gpio) < 0)
+ return -1;
+
+ return gpio;
+}
+
+static int omap_mmc_getcd(struct mmc *mmc)
+{
+ int cd_gpio = ((struct omap_hsmmc_data *)mmc->priv)->cd_gpio;
+ return gpio_get_value(cd_gpio);
+}
+
+static int omap_mmc_getwp(struct mmc *mmc)
+{
+ int wp_gpio = ((struct omap_hsmmc_data *)mmc->priv)->wp_gpio;
+ return gpio_get_value(wp_gpio);
+}
+#else
+static inline int omap_mmc_setup_gpio_in(int gpio, const char *label)
+{
+ return -1;
+}
+
+#define omap_mmc_getcd NULL
+#define omap_mmc_getwp NULL
+#endif
#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
u32 value = 0;
- struct omap_sys_ctrl_regs *const ctrl =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
-
- value = readl(&ctrl->control_pbiaslite);
+ value = readl((*ctrl)->control_pbiaslite);
value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
- writel(value, &ctrl->control_pbiaslite);
+ writel(value, (*ctrl)->control_pbiaslite);
/* set VMMC to 3V */
twl6030_power_mmc_init();
- value = readl(&ctrl->control_pbiaslite);
+ value = readl((*ctrl)->control_pbiaslite);
value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
- writel(value, &ctrl->control_pbiaslite);
+ writel(value, (*ctrl)->control_pbiaslite);
}
#endif
static void omap5_pbias_config(struct mmc *mmc)
{
u32 value = 0;
- struct omap_sys_ctrl_regs *const ctrl =
- (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
- value = readl(&ctrl->control_pbias);
+ value = readl((*ctrl)->control_pbias);
value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, &ctrl->control_pbias);
+ writel(value, (*ctrl)->control_pbias);
twl6035_mmc1_poweron_ldo();
- value = readl(&ctrl->control_pbias);
+ value = readl((*ctrl)->control_pbias);
value &= ~SDCARD_BIAS_HIZ_MODE;
value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
- writel(value, &ctrl->control_pbias);
+ writel(value, (*ctrl)->control_pbias);
- value = readl(&ctrl->control_pbias);
+ value = readl((*ctrl)->control_pbias);
if (value & (1 << 23)) {
value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
value |= SDCARD_BIAS_HIZ_MODE;
- writel(value, &ctrl->control_pbias);
+ writel(value, (*ctrl)->control_pbias);
}
}
#endif
static int mmc_init_setup(struct mmc *mmc)
{
- struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
+ struct hsmmc *mmc_base;
unsigned int reg_val;
unsigned int dsor;
ulong start;
+ mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
mmc_board_init(mmc);
writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
+ struct hsmmc *mmc_base;
unsigned int flags, mmc_stat;
ulong start;
+ mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
start = get_timer(0);
while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
if (get_timer(0) - start > MAX_RETRY_MS) {
static void mmc_set_ios(struct mmc *mmc)
{
- struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
+ struct hsmmc *mmc_base;
unsigned int dsor = 0;
ulong start;
+ mmc_base = ((struct omap_hsmmc_data *)mmc->priv)->base_addr;
/* configue bus width */
switch (mmc->bus_width) {
case 8:
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}
-int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
+ int wp_gpio)
{
- struct mmc *mmc;
-
- mmc = &hsmmc_dev[dev_index];
+ struct mmc *mmc = &hsmmc_dev[dev_index];
+ struct omap_hsmmc_data *priv_data = &hsmmc_dev_data[dev_index];
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
- mmc->getcd = NULL;
+ mmc->getcd = omap_mmc_getcd;
+ mmc->getwp = omap_mmc_getwp;
+ mmc->priv = priv_data;
switch (dev_index) {
case 0:
- mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
+ priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
- mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
+ priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
- mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
+ priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
break;
#endif
default:
- mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
+ priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
+ priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
+ priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC) & ~host_caps_mask;
mmc->set_ios = sdhci_set_ios;
mmc->init = sdhci_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
mmc->set_ios = sh_mmcif_set_ios;
mmc->init = sh_mmcif_init;
mmc->getcd = NULL;
+ mmc->getwp = NULL;
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
host->clk = CONFIG_SH_MMCIF_CLK;
mmc->priv = host;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->getcd = tegra_mmc_getcd;
+ mmc->getwp = NULL;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = 0;
int board_nand_init(struct nand_chip *nand)
{
+#if defined(CONFIG_NAND_ECC_BCH)
+ nand->ecc.mode = NAND_ECC_SOFT_BCH;
+#else
nand->ecc.mode = NAND_ECC_SOFT;
+#endif
/* Reference hardware control function */
nand->cmd_ctrl = kpn_nand_hwcontrol;
/* select the NAND device */
chip->select_chip(mtd, 0);
+ /* check the Lock Tight Status */
+ chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, 0);
+ if (chip->read_byte(mtd) & NAND_LOCK_STATUS_TIGHT) {
+ printf("nand_lock: Device is locked tight!\n");
+ ret = -1;
+ goto out;
+ }
+
chip->cmdfunc(mtd,
(tight ? NAND_CMD_LOCK_TIGHT : NAND_CMD_LOCK),
-1, -1);
ret = -1;
}
+ out:
/* de-select the NAND device */
chip->select_chip(mtd, -1);
return ret;
goto out;
}
+ /* check the Lock Tight Status */
+ page = (int)(start >> chip->page_shift);
+ chip->cmdfunc(mtd, NAND_CMD_LOCK_STATUS, -1, page & chip->pagemask);
+ if (chip->read_byte(mtd) & NAND_LOCK_STATUS_TIGHT) {
+ printf("nand_unlock: Device is locked tight!\n");
+ ret = -1;
+ goto out;
+ }
+
if ((start & (mtd->erasesize - 1)) != 0) {
printf("nand_unlock: Start address must be beginning of "
"nand block!\n");
length -= mtd->erasesize;
/* submit address of first page to unlock */
- page = (int)(start >> chip->page_shift);
chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
/* submit ADDRESS of LAST page to unlock */
void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst)
{
uint32_t *addr = (uint32_t *)dst;
- uint32_t total_pages;
+ uint32_t to_page;
uint32_t block;
uint32_t page, rpage;
enum onenand_spl_pagesize pagesize;
* pulling further unwanted functions into the SPL.
*/
if (pagesize == 2048) {
- total_pages = DIV_ROUND_UP(size, 2048);
page = offs / 2048;
+ to_page = page + DIV_ROUND_UP(size, 2048);
} else {
- total_pages = DIV_ROUND_UP(size, 4096);
page = offs / 4096;
+ to_page = page + DIV_ROUND_UP(size, 4096);
}
- for (; page <= total_pages; page++) {
+ for (; page <= to_page; page++) {
block = page / ONENAND_PAGES_PER_BLOCK;
rpage = page & (ONENAND_PAGES_PER_BLOCK - 1);
ret = onenand_spl_read_page(block, rpage, addr, pagesize);
- if (ret) {
- total_pages += ONENAND_PAGES_PER_BLOCK;
+ if (ret)
page += ONENAND_PAGES_PER_BLOCK - 1;
- } else {
+ else
addr += pagesize / 4;
- }
}
}
struct cpsw_slave *slaves;
struct phy_device *phydev;
struct mii_dev *bus;
+
+ u32 mdio_link;
+ u32 phy_mask;
};
static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
for_each_slave(slave, priv)
cpsw_slave_update_link(slave, priv, &link);
-
+ priv->mdio_link = readl(&mdio_regs->link);
return link;
}
+static int cpsw_check_link(struct cpsw_priv *priv)
+{
+ u32 link = 0;
+
+ link = __raw_readl(&mdio_regs->link) & priv->phy_mask;
+ if ((link) && (link == priv->mdio_link))
+ return 1;
+
+ return cpsw_update_link(priv);
+}
+
static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
{
if (priv->host_port == 0)
cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port);
+
+ priv->phy_mask |= 1 << slave->data->phy_id;
}
static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
int len;
int timeout = CPDMA_TIMEOUT;
- if (!cpsw_update_link(priv))
+ if (!cpsw_check_link(priv))
return -EIO;
flush_dcache_range((unsigned long)packet,
int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
- char env_addr[32];
#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
rc = fman_upload_firmware(index, ®->fm_imem, addr);
if (rc)
return rc;
- sprintf(env_addr, "0x%lx", (long unsigned int)addr);
- setenv("fman_ucode", env_addr);
+ setenv_addr("fman_ucode", addr);
fm_init_muram(index, ®->muram);
fm_init_qmi(®->fm_qmi_common);
#include <serial.h>
#include <linux/compiler.h>
+/*
+ *
+ * serial_buf: A buffer that holds keyboard characters for the
+ * Sandbox U-boot.
+ *
+ * invariants:
+ * serial_buf_write == serial_buf_read -> empty buffer
+ * (serial_buf_write + 1) % 16 == serial_buf_read -> full buffer
+ */
+static char serial_buf[16];
+static unsigned int serial_buf_write;
+static unsigned int serial_buf_read;
+
static int sandbox_serial_init(void)
{
os_tty_raw(0);
os_write(1, str, strlen(str));
}
-static int sandbox_serial_getc(void)
+static unsigned int increment_buffer_index(unsigned int index)
+{
+ return (index + 1) % ARRAY_SIZE(serial_buf);
+}
+
+static int sandbox_serial_tstc(void)
{
- char buf;
+ const unsigned int next_index =
+ increment_buffer_index(serial_buf_write);
ssize_t count;
- count = os_read(0, &buf, 1);
- return count == 1 ? buf : 0;
+ os_usleep(100);
+ if (next_index == serial_buf_read)
+ return 1; /* buffer full */
+
+ count = os_read_no_block(0, &serial_buf[serial_buf_write], 1);
+ if (count == 1)
+ serial_buf_write = next_index;
+ return serial_buf_write != serial_buf_read;
}
-static int sandbox_serial_tstc(void)
+static int sandbox_serial_getc(void)
{
- return 0;
+ int result;
+
+ while (!sandbox_serial_tstc())
+ ; /* buffer empty */
+
+ result = serial_buf[serial_buf_read];
+ serial_buf_read = increment_buffer_index(serial_buf_read);
+ return result;
}
static struct serial_device sandbox_serial_drv = {
_serial_setbrg(dev_index);
}
+#if defined(CONFIG_SYS_NS16550_COM1)
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device eserial1_device =
INIT_ESERIAL_STRUCTURE(1, "eserial0");
+#endif
+#if defined(CONFIG_SYS_NS16550_COM2)
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device eserial2_device =
INIT_ESERIAL_STRUCTURE(2, "eserial1");
+#endif
+#if defined(CONFIG_SYS_NS16550_COM3)
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device eserial3_device =
INIT_ESERIAL_STRUCTURE(3, "eserial2");
+#endif
+#if defined(CONFIG_SYS_NS16550_COM4)
DECLARE_ESERIAL_FUNCTIONS(4);
struct serial_device eserial4_device =
INIT_ESERIAL_STRUCTURE(4, "eserial3");
+#endif
+#if defined(CONFIG_SYS_NS16550_COM5)
DECLARE_ESERIAL_FUNCTIONS(5);
struct serial_device eserial5_device =
INIT_ESERIAL_STRUCTURE(5, "eserial4");
+#endif
+#if defined(CONFIG_SYS_NS16550_COM6)
DECLARE_ESERIAL_FUNCTIONS(6);
struct serial_device eserial6_device =
INIT_ESERIAL_STRUCTURE(6, "eserial5");
+#endif
__weak struct serial_device *default_serial_console(void)
{
COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
+COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
--- /dev/null
+/*
+ * Analog Devices SPI3 controller driver
+ *
+ * Copyright (c) 2011 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
+#include <asm/mach-common/bits/spi6xx.h>
+
+struct bfin_spi_slave {
+ struct spi_slave slave;
+ u32 control, clock;
+ struct bfin_spi_regs *regs;
+ int cs_pol;
+};
+
+#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
+
+#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
+#ifdef CONFIG_BFIN_SPI_GPIO_CS
+# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
+#else
+# define is_gpio_cs(cs) 0
+#endif
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ if (is_gpio_cs(cs))
+ return gpio_is_valid(gpio_cs(cs));
+ else
+ return (cs >= 1 && cs <= MAX_CTRL_CS);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_set_value(cs, bss->cs_pol);
+ } else {
+ u32 ssel;
+ ssel = bfin_read32(&bss->regs->ssel);
+ ssel |= 1 << slave->cs;
+ if (bss->cs_pol)
+ ssel |= (1 << 8) << slave->cs;
+ else
+ ssel &= ~((1 << 8) << slave->cs);
+ bfin_write32(&bss->regs->ssel, ssel);
+ }
+
+ SSYNC();
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_set_value(cs, !bss->cs_pol);
+ } else {
+ u32 ssel;
+ ssel = bfin_read32(&bss->regs->ssel);
+ if (bss->cs_pol)
+ ssel &= ~((1 << 8) << slave->cs);
+ else
+ ssel |= (1 << 8) << slave->cs;
+ /* deassert cs */
+ bfin_write32(&bss->regs->ssel, ssel);
+ SSYNC();
+ /* disable cs */
+ ssel &= ~(1 << slave->cs);
+ bfin_write32(&bss->regs->ssel, ssel);
+ }
+
+ SSYNC();
+}
+
+void spi_init()
+{
+}
+
+#define SPI_PINS(n) \
+ { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
+static unsigned short pins[][5] = {
+#ifdef SPI0_REGBASE
+ [0] = SPI_PINS(0),
+#endif
+#ifdef SPI1_REGBASE
+ [1] = SPI_PINS(1),
+#endif
+#ifdef SPI2_REGBASE
+ [2] = SPI_PINS(2),
+#endif
+};
+
+#define SPI_CS_PINS(n) \
+ { \
+ P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
+ P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
+ P_SPI##n##_SSEL7, \
+ }
+static const unsigned short cs_pins[][7] = {
+#ifdef SPI0_REGBASE
+ [0] = SPI_CS_PINS(0),
+#endif
+#ifdef SPI1_REGBASE
+ [1] = SPI_CS_PINS(1),
+#endif
+#ifdef SPI2_REGBASE
+ [2] = SPI_CS_PINS(2),
+#endif
+};
+
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+ ulong sclk;
+ u32 clock;
+
+ sclk = get_sclk1();
+ clock = sclk / hz;
+ if (clock)
+ clock--;
+ bss->clock = clock;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct bfin_spi_slave *bss;
+ u32 reg_base;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
+ debug("%s: invalid bus %u\n", __func__, bus);
+ return NULL;
+ }
+ switch (bus) {
+#ifdef SPI0_REGBASE
+ case 0:
+ reg_base = SPI0_REGBASE;
+ break;
+#endif
+#ifdef SPI1_REGBASE
+ case 1:
+ reg_base = SPI1_REGBASE;
+ break;
+#endif
+#ifdef SPI2_REGBASE
+ case 2:
+ reg_base = SPI2_REGBASE;
+ break;
+#endif
+ default:
+ return NULL;
+ }
+
+ bss = malloc(sizeof(*bss));
+ if (!bss)
+ return NULL;
+
+ bss->slave.bus = bus;
+ bss->slave.cs = cs;
+ bss->regs = (struct bfin_spi_regs *)reg_base;
+ bss->control = SPI_CTL_EN | SPI_CTL_MSTR;
+ if (mode & SPI_CPHA)
+ bss->control |= SPI_CTL_CPHA;
+ if (mode & SPI_CPOL)
+ bss->control |= SPI_CTL_CPOL;
+ if (mode & SPI_LSB_FIRST)
+ bss->control |= SPI_CTL_LSBF;
+ bss->control &= ~SPI_CTL_ASSEL;
+ bss->cs_pol = mode & SPI_CS_HIGH ? 1 : 0;
+ spi_set_speed(&bss->slave, max_hz);
+
+ return &bss->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+ free(bss);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+ if (is_gpio_cs(slave->cs)) {
+ unsigned int cs = gpio_cs(slave->cs);
+ gpio_request(cs, "bfin-spi");
+ gpio_direction_output(cs, !bss->cs_pol);
+ pins[slave->bus][0] = P_DONTCARE;
+ } else
+ pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
+ peripheral_request_list(pins[slave->bus], "bfin-spi");
+
+ bfin_write32(&bss->regs->control, bss->control);
+ bfin_write32(&bss->regs->clock, bss->clock);
+ bfin_write32(&bss->regs->delay, 0x0);
+ bfin_write32(&bss->regs->rx_control, SPI_RXCTL_REN);
+ bfin_write32(&bss->regs->tx_control, SPI_TXCTL_TEN | SPI_TXCTL_TTI);
+ SSYNC();
+
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+ struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
+ debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+ peripheral_free_list(pins[slave->bus]);
+ if (is_gpio_cs(slave->cs))
+ gpio_free(gpio_cs(slave->cs));
+
+ bfin_write32(&bss->regs->rx_control, 0x0);
+ bfin_write32(&bss->regs->tx_control, 0x0);
+ bfin_write32(&bss->regs->control, 0x0);
+ SSYNC();
+}
+
+#ifndef CONFIG_BFIN_SPI_IDLE_VAL
+# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
+#endif
+
+static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
+ uint bytes)
+{
+ /* discard invalid rx data and empty rfifo */
+ while (!(bfin_read32(&bss->regs->status) & SPI_STAT_RFE))
+ bfin_read32(&bss->regs->rfifo);
+
+ while (bytes--) {
+ u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
+ debug("%s: tx:%x ", __func__, value);
+ bfin_write32(&bss->regs->tfifo, value);
+ SSYNC();
+ while (bfin_read32(&bss->regs->status) & SPI_STAT_RFE)
+ if (ctrlc())
+ return -1;
+ value = bfin_read32(&bss->regs->rfifo);
+ if (rx)
+ *rx++ = value;
+ debug("rx:%x\n", value);
+ }
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+ void *din, unsigned long flags)
+{
+ struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+ const u8 *tx = dout;
+ u8 *rx = din;
+ uint bytes = bitlen / 8;
+ int ret = 0;
+
+ debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
+ slave->bus, slave->cs, bitlen, bytes, flags);
+
+ if (bitlen == 0)
+ goto done;
+
+ /* we can only do 8 bit transfers */
+ if (bitlen % 8) {
+ flags |= SPI_XFER_END;
+ goto done;
+ }
+
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(slave);
+
+ ret = spi_pio_xfer(bss, tx, rx, bytes);
+
+ done:
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(slave);
+
+ return ret;
+}
if (!panel_cfg->frame_buffer)
return;
- writel(8 << GFX_FORMAT_SHIFT | GFX_ENABLE, &dispc->gfx_attributes);
+ writel(panel_cfg->gfx_format | GFX_ENABLE, &dispc->gfx_attributes);
writel(1, &dispc->gfx_row_inc);
writel(1, &dispc->gfx_pixel_inc);
writel(panel_cfg->lcd_size, &dispc->gfx_size);
AOBJS =
COBJS-$(CONFIG_FS_EXT4) := ext4fs.o ext4_common.o dev.o
-COBJS-$(CONFIG_EXT4_WRITE) += ext4_journal.o crc16.o
+COBJS-$(CONFIG_EXT4_WRITE) += ext4_write.o ext4_journal.o crc16.o
SRCS := $(AOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y))
--- /dev/null
+/*
+ * (C) Copyright 2011 - 2012 Samsung Electronics
+ * EXT4 filesystem implementation in Uboot by
+ * Uma Shankar <uma.shankar@samsung.com>
+ * Manjunatha C Achar <a.manjunatha@samsung.com>
+ *
+ * ext4ls and ext4load : Based on ext2 ls and load support in Uboot.
+ * Ext4 read optimization taken from Open-Moko
+ * Qi bootloader
+ *
+ * (C) Copyright 2004
+ * esd gmbh <www.esd-electronics.com>
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+ *
+ * based on code from grub2 fs/ext2.c and fs/fshelp.c by
+ * GRUB -- GRand Unified Bootloader
+ * Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+ *
+ * ext4write : Based on generic ext4 protocol.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include <common.h>
+#include <linux/stat.h>
+#include <div64.h>
+#include "ext4_common.h"
+
+static void ext4fs_update(void)
+{
+ short i;
+ ext4fs_update_journal();
+ struct ext_filesystem *fs = get_fs();
+
+ /* update super block */
+ put_ext4((uint64_t)(SUPERBLOCK_SIZE),
+ (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
+
+ /* update block groups */
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ fs->bgd[i].bg_checksum = ext4fs_checksum_update(i);
+ put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz),
+ fs->blk_bmaps[i], fs->blksz);
+ }
+
+ /* update inode table groups */
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz),
+ fs->inode_bmaps[i], fs->blksz);
+ }
+
+ /* update the block group descriptor table */
+ put_ext4((uint64_t)(fs->gdtable_blkno * fs->blksz),
+ (struct ext2_block_group *)fs->gdtable,
+ (fs->blksz * fs->no_blk_pergdt));
+
+ ext4fs_dump_metadata();
+
+ gindex = 0;
+ gd_index = 0;
+}
+
+int ext4fs_get_bgdtable(void)
+{
+ int status;
+ int grp_desc_size;
+ struct ext_filesystem *fs = get_fs();
+ grp_desc_size = sizeof(struct ext2_block_group);
+ fs->no_blk_pergdt = (fs->no_blkgrp * grp_desc_size) / fs->blksz;
+ if ((fs->no_blkgrp * grp_desc_size) % fs->blksz)
+ fs->no_blk_pergdt++;
+
+ /* allocate memory for gdtable */
+ fs->gdtable = zalloc(fs->blksz * fs->no_blk_pergdt);
+ if (!fs->gdtable)
+ return -ENOMEM;
+ /* read the group descriptor table */
+ status = ext4fs_devread(fs->gdtable_blkno * fs->sect_perblk, 0,
+ fs->blksz * fs->no_blk_pergdt, fs->gdtable);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_gdt(fs->gdtable)) {
+ printf("Error in ext4fs_log_gdt\n");
+ return -1;
+ }
+
+ return 0;
+fail:
+ free(fs->gdtable);
+ fs->gdtable = NULL;
+
+ return -1;
+}
+
+static void delete_single_indirect_block(struct ext2_inode *inode)
+{
+ struct ext2_block_group *bgd = NULL;
+ static int prev_bg_bmap_idx = -1;
+ long int blknr;
+ int remainder;
+ int bg_idx;
+ int status;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ /* get block group descriptor table */
+ bgd = (struct ext2_block_group *)fs->gdtable;
+
+ /* deleting the single indirect block associated with inode */
+ if (inode->b.blocks.indir_block != 0) {
+ debug("SIPB releasing %u\n", inode->b.blocks.indir_block);
+ blknr = inode->b.blocks.indir_block;
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+ ext4fs_devread(bgd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal
+ (journal_buffer, bgd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+fail:
+ free(journal_buffer);
+}
+
+static void delete_double_indirect_block(struct ext2_inode *inode)
+{
+ int i;
+ short status;
+ static int prev_bg_bmap_idx = -1;
+ long int blknr;
+ int remainder;
+ int bg_idx;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int *di_buffer = NULL;
+ unsigned int *DIB_start_addr = NULL;
+ struct ext2_block_group *bgd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ /* get the block group descriptor table */
+ bgd = (struct ext2_block_group *)fs->gdtable;
+
+ if (inode->b.blocks.double_indir_block != 0) {
+ di_buffer = zalloc(fs->blksz);
+ if (!di_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ DIB_start_addr = (unsigned int *)di_buffer;
+ blknr = inode->b.blocks.double_indir_block;
+ status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
+ (char *)di_buffer);
+ for (i = 0; i < fs->blksz / sizeof(int); i++) {
+ if (*di_buffer == 0)
+ break;
+
+ debug("DICB releasing %u\n", *di_buffer);
+ if (fs->blksz != 1024) {
+ bg_idx = (*di_buffer) / blk_per_grp;
+ } else {
+ bg_idx = (*di_buffer) / blk_per_grp;
+ remainder = (*di_buffer) % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(*di_buffer,
+ fs->blk_bmaps[bg_idx], bg_idx);
+ di_buffer++;
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status = ext4fs_devread(bgd[bg_idx].block_id
+ * fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ bgd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+
+ /* removing the parent double indirect block */
+ blknr = inode->b.blocks.double_indir_block;
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(bgd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ bgd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ debug("DIPB releasing %ld\n", blknr);
+ }
+fail:
+ free(DIB_start_addr);
+ free(journal_buffer);
+}
+
+static void delete_triple_indirect_block(struct ext2_inode *inode)
+{
+ int i, j;
+ short status;
+ static int prev_bg_bmap_idx = -1;
+ long int blknr;
+ int remainder;
+ int bg_idx;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int *tigp_buffer = NULL;
+ unsigned int *tib_start_addr = NULL;
+ unsigned int *tip_buffer = NULL;
+ unsigned int *tipb_start_addr = NULL;
+ struct ext2_block_group *bgd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ /* get block group descriptor table */
+ bgd = (struct ext2_block_group *)fs->gdtable;
+
+ if (inode->b.blocks.triple_indir_block != 0) {
+ tigp_buffer = zalloc(fs->blksz);
+ if (!tigp_buffer) {
+ printf("No memory\n");
+ return;
+ }
+ tib_start_addr = (unsigned int *)tigp_buffer;
+ blknr = inode->b.blocks.triple_indir_block;
+ status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
+ (char *)tigp_buffer);
+ for (i = 0; i < fs->blksz / sizeof(int); i++) {
+ if (*tigp_buffer == 0)
+ break;
+ debug("tigp buffer releasing %u\n", *tigp_buffer);
+
+ tip_buffer = zalloc(fs->blksz);
+ if (!tip_buffer)
+ goto fail;
+ tipb_start_addr = (unsigned int *)tip_buffer;
+ status = ext4fs_devread((*tigp_buffer) *
+ fs->sect_perblk, 0, fs->blksz,
+ (char *)tip_buffer);
+ for (j = 0; j < fs->blksz / sizeof(int); j++) {
+ if (*tip_buffer == 0)
+ break;
+ if (fs->blksz != 1024) {
+ bg_idx = (*tip_buffer) / blk_per_grp;
+ } else {
+ bg_idx = (*tip_buffer) / blk_per_grp;
+
+ remainder = (*tip_buffer) % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+
+ ext4fs_reset_block_bmap(*tip_buffer,
+ fs->blk_bmaps[bg_idx],
+ bg_idx);
+
+ tip_buffer++;
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+ ext4fs_devread(
+ bgd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ bgd[bg_idx].
+ block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+ free(tipb_start_addr);
+ tipb_start_addr = NULL;
+
+ /*
+ * removing the grand parent blocks
+ * which is connected to inode
+ */
+ if (fs->blksz != 1024) {
+ bg_idx = (*tigp_buffer) / blk_per_grp;
+ } else {
+ bg_idx = (*tigp_buffer) / blk_per_grp;
+
+ remainder = (*tigp_buffer) % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(*tigp_buffer,
+ fs->blk_bmaps[bg_idx], bg_idx);
+
+ tigp_buffer++;
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status =
+ ext4fs_devread(bgd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ bgd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+
+ /* removing the grand parent triple indirect block */
+ blknr = inode->b.blocks.triple_indir_block;
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(bgd[bg_idx].block_id *
+ fs->sect_perblk, 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(journal_buffer,
+ bgd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ debug("tigp buffer itself releasing %ld\n", blknr);
+ }
+fail:
+ free(tib_start_addr);
+ free(tipb_start_addr);
+ free(journal_buffer);
+}
+
+static int ext4fs_delete_file(int inodeno)
+{
+ struct ext2_inode inode;
+ short status;
+ int i;
+ int remainder;
+ long int blknr;
+ int bg_idx;
+ int ibmap_idx;
+ char *read_buffer = NULL;
+ char *start_block_address = NULL;
+ unsigned int no_blocks;
+
+ static int prev_bg_bmap_idx = -1;
+ unsigned int inodes_per_block;
+ long int blkno;
+ unsigned int blkoff;
+ unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
+ unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group;
+ struct ext2_inode *inode_buffer = NULL;
+ struct ext2_block_group *bgd = NULL;
+ struct ext_filesystem *fs = get_fs();
+ char *journal_buffer = zalloc(fs->blksz);
+ if (!journal_buffer)
+ return -ENOMEM;
+ /* get the block group descriptor table */
+ bgd = (struct ext2_block_group *)fs->gdtable;
+ status = ext4fs_read_inode(ext4fs_root, inodeno, &inode);
+ if (status == 0)
+ goto fail;
+
+ /* read the block no allocated to a file */
+ no_blocks = inode.size / fs->blksz;
+ if (inode.size % fs->blksz)
+ no_blocks++;
+
+ if (le32_to_cpu(inode.flags) & EXT4_EXTENTS_FL) {
+ struct ext2fs_node *node_inode =
+ zalloc(sizeof(struct ext2fs_node));
+ if (!node_inode)
+ goto fail;
+ node_inode->data = ext4fs_root;
+ node_inode->ino = inodeno;
+ node_inode->inode_read = 0;
+ memcpy(&(node_inode->inode), &inode, sizeof(struct ext2_inode));
+
+ for (i = 0; i < no_blocks; i++) {
+ blknr = read_allocated_block(&(node_inode->inode), i);
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
+ bg_idx);
+ debug("EXT4_EXTENTS Block releasing %ld: %d\n",
+ blknr, bg_idx);
+
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ status =
+ ext4fs_devread(bgd[bg_idx].block_id *
+ fs->sect_perblk, 0,
+ fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ bgd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+ if (node_inode) {
+ free(node_inode);
+ node_inode = NULL;
+ }
+ } else {
+
+ delete_single_indirect_block(&inode);
+ delete_double_indirect_block(&inode);
+ delete_triple_indirect_block(&inode);
+
+ /* read the block no allocated to a file */
+ no_blocks = inode.size / fs->blksz;
+ if (inode.size % fs->blksz)
+ no_blocks++;
+ for (i = 0; i < no_blocks; i++) {
+ blknr = read_allocated_block(&inode, i);
+ if (fs->blksz != 1024) {
+ bg_idx = blknr / blk_per_grp;
+ } else {
+ bg_idx = blknr / blk_per_grp;
+ remainder = blknr % blk_per_grp;
+ if (!remainder)
+ bg_idx--;
+ }
+ ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
+ bg_idx);
+ debug("ActualB releasing %ld: %d\n", blknr, bg_idx);
+
+ bgd[bg_idx].free_blocks++;
+ fs->sb->free_blocks++;
+ /* journal backup */
+ if (prev_bg_bmap_idx != bg_idx) {
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(bgd[bg_idx].block_id
+ * fs->sect_perblk,
+ 0, fs->blksz,
+ journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer,
+ bgd[bg_idx].block_id))
+ goto fail;
+ prev_bg_bmap_idx = bg_idx;
+ }
+ }
+ }
+
+ /* from the inode no to blockno */
+ inodes_per_block = fs->blksz / fs->inodesz;
+ ibmap_idx = inodeno / inode_per_grp;
+
+ /* get the block no */
+ inodeno--;
+ blkno = __le32_to_cpu(bgd[ibmap_idx].inode_table_id) +
+ (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block;
+
+ /* get the offset of the inode */
+ blkoff = ((inodeno) % inodes_per_block) * fs->inodesz;
+
+ /* read the block no containing the inode */
+ read_buffer = zalloc(fs->blksz);
+ if (!read_buffer)
+ goto fail;
+ start_block_address = read_buffer;
+ status = ext4fs_devread(blkno * fs->sect_perblk,
+ 0, fs->blksz, read_buffer);
+ if (status == 0)
+ goto fail;
+
+ if (ext4fs_log_journal(read_buffer, blkno))
+ goto fail;
+
+ read_buffer = read_buffer + blkoff;
+ inode_buffer = (struct ext2_inode *)read_buffer;
+ memset(inode_buffer, '\0', sizeof(struct ext2_inode));
+
+ /* write the inode to original position in inode table */
+ if (ext4fs_put_metadata(start_block_address, blkno))
+ goto fail;
+
+ /* update the respective inode bitmaps */
+ inodeno++;
+ ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx);
+ bgd[ibmap_idx].free_inodes++;
+ fs->sb->free_inodes++;
+ /* journal backup */
+ memset(journal_buffer, '\0', fs->blksz);
+ status = ext4fs_devread(bgd[ibmap_idx].inode_id *
+ fs->sect_perblk, 0, fs->blksz, journal_buffer);
+ if (status == 0)
+ goto fail;
+ if (ext4fs_log_journal(journal_buffer, bgd[ibmap_idx].inode_id))
+ goto fail;
+
+ ext4fs_update();
+ ext4fs_deinit();
+
+ if (ext4fs_init() != 0) {
+ printf("error in File System init\n");
+ goto fail;
+ }
+
+ free(start_block_address);
+ free(journal_buffer);
+
+ return 0;
+fail:
+ free(start_block_address);
+ free(journal_buffer);
+
+ return -1;
+}
+
+int ext4fs_init(void)
+{
+ short status;
+ int i;
+ unsigned int real_free_blocks = 0;
+ struct ext_filesystem *fs = get_fs();
+
+ /* populate fs */
+ fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root);
+ fs->inodesz = INODE_SIZE_FILESYSTEM(ext4fs_root);
+ fs->sect_perblk = fs->blksz / SECTOR_SIZE;
+
+ /* get the superblock */
+ fs->sb = zalloc(SUPERBLOCK_SIZE);
+ if (!fs->sb)
+ return -ENOMEM;
+ if (!ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
+ (char *)fs->sb))
+ goto fail;
+
+ /* init journal */
+ if (ext4fs_init_journal())
+ goto fail;
+
+ /* get total no of blockgroups */
+ fs->no_blkgrp = (uint32_t)ext4fs_div_roundup(
+ (ext4fs_root->sblock.total_blocks -
+ ext4fs_root->sblock.first_data_block),
+ ext4fs_root->sblock.blocks_per_group);
+
+ /* get the block group descriptor table */
+ fs->gdtable_blkno = ((EXT2_MIN_BLOCK_SIZE == fs->blksz) + 1);
+ if (ext4fs_get_bgdtable() == -1) {
+ printf("Error in getting the block group descriptor table\n");
+ goto fail;
+ }
+ fs->bgd = (struct ext2_block_group *)fs->gdtable;
+
+ /* load all the available bitmap block of the partition */
+ fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *));
+ if (!fs->blk_bmaps)
+ goto fail;
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ fs->blk_bmaps[i] = zalloc(fs->blksz);
+ if (!fs->blk_bmaps[i])
+ goto fail;
+ }
+
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ status =
+ ext4fs_devread(fs->bgd[i].block_id * fs->sect_perblk, 0,
+ fs->blksz, (char *)fs->blk_bmaps[i]);
+ if (status == 0)
+ goto fail;
+ }
+
+ /* load all the available inode bitmap of the partition */
+ fs->inode_bmaps = zalloc(fs->no_blkgrp * sizeof(unsigned char *));
+ if (!fs->inode_bmaps)
+ goto fail;
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ fs->inode_bmaps[i] = zalloc(fs->blksz);
+ if (!fs->inode_bmaps[i])
+ goto fail;
+ }
+
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ status = ext4fs_devread(fs->bgd[i].inode_id * fs->sect_perblk,
+ 0, fs->blksz,
+ (char *)fs->inode_bmaps[i]);
+ if (status == 0)
+ goto fail;
+ }
+
+ /*
+ * check filesystem consistency with free blocks of file system
+ * some time we observed that superblock freeblocks does not match
+ * with the blockgroups freeblocks when improper
+ * reboot of a linux kernel
+ */
+ for (i = 0; i < fs->no_blkgrp; i++)
+ real_free_blocks = real_free_blocks + fs->bgd[i].free_blocks;
+ if (real_free_blocks != fs->sb->free_blocks)
+ fs->sb->free_blocks = real_free_blocks;
+
+ return 0;
+fail:
+ ext4fs_deinit();
+
+ return -1;
+}
+
+void ext4fs_deinit(void)
+{
+ int i;
+ struct ext2_inode inode_journal;
+ struct journal_superblock_t *jsb;
+ long int blknr;
+ struct ext_filesystem *fs = get_fs();
+
+ /* free journal */
+ char *temp_buff = zalloc(fs->blksz);
+ if (temp_buff) {
+ ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
+ &inode_journal);
+ blknr = read_allocated_block(&inode_journal,
+ EXT2_JOURNAL_SUPERBLOCK);
+ ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
+ temp_buff);
+ jsb = (struct journal_superblock_t *)temp_buff;
+ jsb->s_start = cpu_to_be32(0);
+ put_ext4((uint64_t) (blknr * fs->blksz),
+ (struct journal_superblock_t *)temp_buff, fs->blksz);
+ free(temp_buff);
+ }
+ ext4fs_free_journal();
+
+ /* get the superblock */
+ ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, (char *)fs->sb);
+ fs->sb->feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER;
+ put_ext4((uint64_t)(SUPERBLOCK_SIZE),
+ (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
+ free(fs->sb);
+ fs->sb = NULL;
+
+ if (fs->blk_bmaps) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ free(fs->blk_bmaps[i]);
+ fs->blk_bmaps[i] = NULL;
+ }
+ free(fs->blk_bmaps);
+ fs->blk_bmaps = NULL;
+ }
+
+ if (fs->inode_bmaps) {
+ for (i = 0; i < fs->no_blkgrp; i++) {
+ free(fs->inode_bmaps[i]);
+ fs->inode_bmaps[i] = NULL;
+ }
+ free(fs->inode_bmaps);
+ fs->inode_bmaps = NULL;
+ }
+
+
+ free(fs->gdtable);
+ fs->gdtable = NULL;
+ fs->bgd = NULL;
+ /*
+ * reinitiliazed the global inode and
+ * block bitmap first execution check variables
+ */
+ fs->first_pass_ibmap = 0;
+ fs->first_pass_bbmap = 0;
+ fs->curr_inode_no = 0;
+ fs->curr_blkno = 0;
+}
+
+static int ext4fs_write_file(struct ext2_inode *file_inode,
+ int pos, unsigned int len, char *buf)
+{
+ int i;
+ int blockcnt;
+ int log2blocksize = LOG2_EXT2_BLOCK_SIZE(ext4fs_root);
+ unsigned int filesize = __le32_to_cpu(file_inode->size);
+ struct ext_filesystem *fs = get_fs();
+ int previous_block_number = -1;
+ int delayed_start = 0;
+ int delayed_extent = 0;
+ int delayed_next = 0;
+ char *delayed_buf = NULL;
+
+ /* Adjust len so it we can't read past the end of the file. */
+ if (len > filesize)
+ len = filesize;
+
+ blockcnt = ((len + pos) + fs->blksz - 1) / fs->blksz;
+
+ for (i = pos / fs->blksz; i < blockcnt; i++) {
+ long int blknr;
+ int blockend = fs->blksz;
+ int skipfirst = 0;
+ blknr = read_allocated_block(file_inode, i);
+ if (blknr < 0)
+ return -1;
+
+ blknr = blknr << log2blocksize;
+
+ if (blknr) {
+ if (previous_block_number != -1) {
+ if (delayed_next == blknr) {
+ delayed_extent += blockend;
+ delayed_next += blockend >> SECTOR_BITS;
+ } else { /* spill */
+ put_ext4((uint64_t) (delayed_start *
+ SECTOR_SIZE),
+ delayed_buf,
+ (uint32_t) delayed_extent);
+ previous_block_number = blknr;
+ delayed_start = blknr;
+ delayed_extent = blockend;
+ delayed_buf = buf;
+ delayed_next = blknr +
+ (blockend >> SECTOR_BITS);
+ }
+ } else {
+ previous_block_number = blknr;
+ delayed_start = blknr;
+ delayed_extent = blockend;
+ delayed_buf = buf;
+ delayed_next = blknr +
+ (blockend >> SECTOR_BITS);
+ }
+ } else {
+ if (previous_block_number != -1) {
+ /* spill */
+ put_ext4((uint64_t) (delayed_start *
+ SECTOR_SIZE), delayed_buf,
+ (uint32_t) delayed_extent);
+ previous_block_number = -1;
+ }
+ memset(buf, 0, fs->blksz - skipfirst);
+ }
+ buf += fs->blksz - skipfirst;
+ }
+ if (previous_block_number != -1) {
+ /* spill */
+ put_ext4((uint64_t) (delayed_start * SECTOR_SIZE),
+ delayed_buf, (uint32_t) delayed_extent);
+ previous_block_number = -1;
+ }
+
+ return len;
+}
+
+int ext4fs_write(const char *fname, unsigned char *buffer,
+ unsigned long sizebytes)
+{
+ int ret = 0;
+ struct ext2_inode *file_inode = NULL;
+ unsigned char *inode_buffer = NULL;
+ int parent_inodeno;
+ int inodeno;
+ time_t timestamp = 0;
+
+ uint64_t bytes_reqd_for_file;
+ unsigned int blks_reqd_for_file;
+ unsigned int blocks_remaining;
+ int existing_file_inodeno;
+ char *temp_ptr = NULL;
+ long int itable_blkno;
+ long int parent_itable_blkno;
+ long int blkoff;
+ struct ext2_sblock *sblock = &(ext4fs_root->sblock);
+ unsigned int inodes_per_block;
+ unsigned int ibmap_idx;
+ struct ext_filesystem *fs = get_fs();
+ ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256);
+ memset(filename, 0x00, sizeof(filename));
+
+ g_parent_inode = zalloc(sizeof(struct ext2_inode));
+ if (!g_parent_inode)
+ goto fail;
+
+ if (ext4fs_init() != 0) {
+ printf("error in File System init\n");
+ return -1;
+ }
+ inodes_per_block = fs->blksz / fs->inodesz;
+ parent_inodeno = ext4fs_get_parent_inode_num(fname, filename, F_FILE);
+ if (parent_inodeno == -1)
+ goto fail;
+ if (ext4fs_iget(parent_inodeno, g_parent_inode))
+ goto fail;
+ /* check if the filename is already present in root */
+ existing_file_inodeno = ext4fs_filename_check(filename);
+ if (existing_file_inodeno != -1) {
+ ret = ext4fs_delete_file(existing_file_inodeno);
+ fs->first_pass_bbmap = 0;
+ fs->curr_blkno = 0;
+
+ fs->first_pass_ibmap = 0;
+ fs->curr_inode_no = 0;
+ if (ret)
+ goto fail;
+ }
+ /* calucalate how many blocks required */
+ bytes_reqd_for_file = sizebytes;
+ blks_reqd_for_file = lldiv(bytes_reqd_for_file, fs->blksz);
+ if (do_div(bytes_reqd_for_file, fs->blksz) != 0) {
+ blks_reqd_for_file++;
+ debug("total bytes for a file %u\n", blks_reqd_for_file);
+ }
+ blocks_remaining = blks_reqd_for_file;
+ /* test for available space in partition */
+ if (fs->sb->free_blocks < blks_reqd_for_file) {
+ printf("Not enough space on partition !!!\n");
+ goto fail;
+ }
+
+ ext4fs_update_parent_dentry(filename, &inodeno, FILETYPE_REG);
+ /* prepare file inode */
+ inode_buffer = zalloc(fs->inodesz);
+ if (!inode_buffer)
+ goto fail;
+ file_inode = (struct ext2_inode *)inode_buffer;
+ file_inode->mode = S_IFREG | S_IRWXU |
+ S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH;
+ /* ToDo: Update correct time */
+ file_inode->mtime = timestamp;
+ file_inode->atime = timestamp;
+ file_inode->ctime = timestamp;
+ file_inode->nlinks = 1;
+ file_inode->size = sizebytes;
+
+ /* Allocate data blocks */
+ ext4fs_allocate_blocks(file_inode, blocks_remaining,
+ &blks_reqd_for_file);
+ file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) / SECTOR_SIZE;
+
+ temp_ptr = zalloc(fs->blksz);
+ if (!temp_ptr)
+ goto fail;
+ ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group;
+ inodeno--;
+ itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
+ (inodeno % __le32_to_cpu(sblock->inodes_per_group)) /
+ inodes_per_block;
+ blkoff = (inodeno % inodes_per_block) * fs->inodesz;
+ ext4fs_devread(itable_blkno * fs->sect_perblk, 0, fs->blksz, temp_ptr);
+ if (ext4fs_log_journal(temp_ptr, itable_blkno))
+ goto fail;
+
+ memcpy(temp_ptr + blkoff, inode_buffer, fs->inodesz);
+ if (ext4fs_put_metadata(temp_ptr, itable_blkno))
+ goto fail;
+ /* copy the file content into data blocks */
+ if (ext4fs_write_file(file_inode, 0, sizebytes, (char *)buffer) == -1) {
+ printf("Error in copying content\n");
+ goto fail;
+ }
+ ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group;
+ parent_inodeno--;
+ parent_itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
+ (parent_inodeno %
+ __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
+ blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz;
+ if (parent_itable_blkno != itable_blkno) {
+ memset(temp_ptr, '\0', fs->blksz);
+ ext4fs_devread(parent_itable_blkno * fs->sect_perblk,
+ 0, fs->blksz, temp_ptr);
+ if (ext4fs_log_journal(temp_ptr, parent_itable_blkno))
+ goto fail;
+
+ memcpy(temp_ptr + blkoff, g_parent_inode,
+ sizeof(struct ext2_inode));
+ if (ext4fs_put_metadata(temp_ptr, parent_itable_blkno))
+ goto fail;
+ free(temp_ptr);
+ } else {
+ /*
+ * If parent and child fall in same inode table block
+ * both should be kept in 1 buffer
+ */
+ memcpy(temp_ptr + blkoff, g_parent_inode,
+ sizeof(struct ext2_inode));
+ gd_index--;
+ if (ext4fs_put_metadata(temp_ptr, itable_blkno))
+ goto fail;
+ free(temp_ptr);
+ }
+ ext4fs_update();
+ ext4fs_deinit();
+
+ fs->first_pass_bbmap = 0;
+ fs->curr_blkno = 0;
+ fs->first_pass_ibmap = 0;
+ fs->curr_inode_no = 0;
+ free(inode_buffer);
+ free(g_parent_inode);
+ g_parent_inode = NULL;
+
+ return 0;
+fail:
+ ext4fs_deinit();
+ free(inode_buffer);
+ free(g_parent_inode);
+ g_parent_inode = NULL;
+
+ return -1;
+}
*/
#include <common.h>
-#include <malloc.h>
#include <ext_common.h>
#include <ext4fs.h>
-#include <linux/stat.h>
-#include <linux/time.h>
-#include <asm/byteorder.h>
-#include <div64.h>
#include "ext4_common.h"
int ext4fs_symlinknest;
return ext4fs_read_file(ext4fs_file, 0, len, buf);
}
-#if defined(CONFIG_EXT4_WRITE)
-static void ext4fs_update(void)
+int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
+ disk_partition_t *fs_partition)
{
- short i;
- ext4fs_update_journal();
- struct ext_filesystem *fs = get_fs();
+ ext4fs_set_blk_dev(fs_dev_desc, fs_partition);
- /* update super block */
- put_ext4((uint64_t)(SUPERBLOCK_SIZE),
- (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
-
- /* update block groups */
- for (i = 0; i < fs->no_blkgrp; i++) {
- fs->bgd[i].bg_checksum = ext4fs_checksum_update(i);
- put_ext4((uint64_t)(fs->bgd[i].block_id * fs->blksz),
- fs->blk_bmaps[i], fs->blksz);
- }
-
- /* update inode table groups */
- for (i = 0; i < fs->no_blkgrp; i++) {
- put_ext4((uint64_t) (fs->bgd[i].inode_id * fs->blksz),
- fs->inode_bmaps[i], fs->blksz);
- }
-
- /* update the block group descriptor table */
- put_ext4((uint64_t)(fs->gdtable_blkno * fs->blksz),
- (struct ext2_block_group *)fs->gdtable,
- (fs->blksz * fs->no_blk_pergdt));
-
- ext4fs_dump_metadata();
-
- gindex = 0;
- gd_index = 0;
-}
-
-int ext4fs_get_bgdtable(void)
-{
- int status;
- int grp_desc_size;
- struct ext_filesystem *fs = get_fs();
- grp_desc_size = sizeof(struct ext2_block_group);
- fs->no_blk_pergdt = (fs->no_blkgrp * grp_desc_size) / fs->blksz;
- if ((fs->no_blkgrp * grp_desc_size) % fs->blksz)
- fs->no_blk_pergdt++;
-
- /* allocate memory for gdtable */
- fs->gdtable = zalloc(fs->blksz * fs->no_blk_pergdt);
- if (!fs->gdtable)
- return -ENOMEM;
- /* read the group descriptor table */
- status = ext4fs_devread(fs->gdtable_blkno * fs->sect_perblk, 0,
- fs->blksz * fs->no_blk_pergdt, fs->gdtable);
- if (status == 0)
- goto fail;
-
- if (ext4fs_log_gdt(fs->gdtable)) {
- printf("Error in ext4fs_log_gdt\n");
+ if (!ext4fs_mount(fs_partition->size)) {
+ ext4fs_close();
return -1;
}
return 0;
-fail:
- free(fs->gdtable);
- fs->gdtable = NULL;
-
- return -1;
-}
-
-static void delete_single_indirect_block(struct ext2_inode *inode)
-{
- struct ext2_block_group *bgd = NULL;
- static int prev_bg_bmap_idx = -1;
- long int blknr;
- int remainder;
- int bg_idx;
- int status;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
- struct ext_filesystem *fs = get_fs();
- char *journal_buffer = zalloc(fs->blksz);
- if (!journal_buffer) {
- printf("No memory\n");
- return;
- }
- /* get block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
-
- /* deleting the single indirect block associated with inode */
- if (inode->b.blocks.indir_block != 0) {
- debug("SIPB releasing %u\n", inode->b.blocks.indir_block);
- blknr = inode->b.blocks.indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
- remainder = blknr % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- status =
- ext4fs_devread(bgd[bg_idx].block_id *
- fs->sect_perblk, 0, fs->blksz,
- journal_buffer);
- if (status == 0)
- goto fail;
- if (ext4fs_log_journal
- (journal_buffer, bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- }
-fail:
- free(journal_buffer);
-}
-
-static void delete_double_indirect_block(struct ext2_inode *inode)
-{
- int i;
- short status;
- static int prev_bg_bmap_idx = -1;
- long int blknr;
- int remainder;
- int bg_idx;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
- unsigned int *di_buffer = NULL;
- unsigned int *DIB_start_addr = NULL;
- struct ext2_block_group *bgd = NULL;
- struct ext_filesystem *fs = get_fs();
- char *journal_buffer = zalloc(fs->blksz);
- if (!journal_buffer) {
- printf("No memory\n");
- return;
- }
- /* get the block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
-
- if (inode->b.blocks.double_indir_block != 0) {
- di_buffer = zalloc(fs->blksz);
- if (!di_buffer) {
- printf("No memory\n");
- return;
- }
- DIB_start_addr = (unsigned int *)di_buffer;
- blknr = inode->b.blocks.double_indir_block;
- status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
- (char *)di_buffer);
- for (i = 0; i < fs->blksz / sizeof(int); i++) {
- if (*di_buffer == 0)
- break;
-
- debug("DICB releasing %u\n", *di_buffer);
- if (fs->blksz != 1024) {
- bg_idx = (*di_buffer) / blk_per_grp;
- } else {
- bg_idx = (*di_buffer) / blk_per_grp;
- remainder = (*di_buffer) % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(*di_buffer,
- fs->blk_bmaps[bg_idx], bg_idx);
- di_buffer++;
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- status = ext4fs_devread(bgd[bg_idx].block_id
- * fs->sect_perblk, 0,
- fs->blksz,
- journal_buffer);
- if (status == 0)
- goto fail;
-
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- }
-
- /* removing the parent double indirect block */
- blknr = inode->b.blocks.double_indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
- remainder = blknr % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(bgd[bg_idx].block_id *
- fs->sect_perblk, 0, fs->blksz,
- journal_buffer);
- if (status == 0)
- goto fail;
-
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- debug("DIPB releasing %ld\n", blknr);
- }
-fail:
- free(DIB_start_addr);
- free(journal_buffer);
-}
-
-static void delete_triple_indirect_block(struct ext2_inode *inode)
-{
- int i, j;
- short status;
- static int prev_bg_bmap_idx = -1;
- long int blknr;
- int remainder;
- int bg_idx;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
- unsigned int *tigp_buffer = NULL;
- unsigned int *tib_start_addr = NULL;
- unsigned int *tip_buffer = NULL;
- unsigned int *tipb_start_addr = NULL;
- struct ext2_block_group *bgd = NULL;
- struct ext_filesystem *fs = get_fs();
- char *journal_buffer = zalloc(fs->blksz);
- if (!journal_buffer) {
- printf("No memory\n");
- return;
- }
- /* get block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
-
- if (inode->b.blocks.triple_indir_block != 0) {
- tigp_buffer = zalloc(fs->blksz);
- if (!tigp_buffer) {
- printf("No memory\n");
- return;
- }
- tib_start_addr = (unsigned int *)tigp_buffer;
- blknr = inode->b.blocks.triple_indir_block;
- status = ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
- (char *)tigp_buffer);
- for (i = 0; i < fs->blksz / sizeof(int); i++) {
- if (*tigp_buffer == 0)
- break;
- debug("tigp buffer releasing %u\n", *tigp_buffer);
-
- tip_buffer = zalloc(fs->blksz);
- if (!tip_buffer)
- goto fail;
- tipb_start_addr = (unsigned int *)tip_buffer;
- status = ext4fs_devread((*tigp_buffer) *
- fs->sect_perblk, 0, fs->blksz,
- (char *)tip_buffer);
- for (j = 0; j < fs->blksz / sizeof(int); j++) {
- if (*tip_buffer == 0)
- break;
- if (fs->blksz != 1024) {
- bg_idx = (*tip_buffer) / blk_per_grp;
- } else {
- bg_idx = (*tip_buffer) / blk_per_grp;
-
- remainder = (*tip_buffer) % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
-
- ext4fs_reset_block_bmap(*tip_buffer,
- fs->blk_bmaps[bg_idx],
- bg_idx);
-
- tip_buffer++;
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- status =
- ext4fs_devread(
- bgd[bg_idx].block_id *
- fs->sect_perblk, 0,
- fs->blksz,
- journal_buffer);
- if (status == 0)
- goto fail;
-
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].
- block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- }
- free(tipb_start_addr);
- tipb_start_addr = NULL;
-
- /*
- * removing the grand parent blocks
- * which is connected to inode
- */
- if (fs->blksz != 1024) {
- bg_idx = (*tigp_buffer) / blk_per_grp;
- } else {
- bg_idx = (*tigp_buffer) / blk_per_grp;
-
- remainder = (*tigp_buffer) % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(*tigp_buffer,
- fs->blk_bmaps[bg_idx], bg_idx);
-
- tigp_buffer++;
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status =
- ext4fs_devread(bgd[bg_idx].block_id *
- fs->sect_perblk, 0,
- fs->blksz, journal_buffer);
- if (status == 0)
- goto fail;
-
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- }
-
- /* removing the grand parent triple indirect block */
- blknr = inode->b.blocks.triple_indir_block;
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
- remainder = blknr % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx], bg_idx);
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(bgd[bg_idx].block_id *
- fs->sect_perblk, 0, fs->blksz,
- journal_buffer);
- if (status == 0)
- goto fail;
-
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- debug("tigp buffer itself releasing %ld\n", blknr);
- }
-fail:
- free(tib_start_addr);
- free(tipb_start_addr);
- free(journal_buffer);
-}
-
-static int ext4fs_delete_file(int inodeno)
-{
- struct ext2_inode inode;
- short status;
- int i;
- int remainder;
- long int blknr;
- int bg_idx;
- int ibmap_idx;
- char *read_buffer = NULL;
- char *start_block_address = NULL;
- unsigned int no_blocks;
-
- static int prev_bg_bmap_idx = -1;
- unsigned int inodes_per_block;
- long int blkno;
- unsigned int blkoff;
- unsigned int blk_per_grp = ext4fs_root->sblock.blocks_per_group;
- unsigned int inode_per_grp = ext4fs_root->sblock.inodes_per_group;
- struct ext2_inode *inode_buffer = NULL;
- struct ext2_block_group *bgd = NULL;
- struct ext_filesystem *fs = get_fs();
- char *journal_buffer = zalloc(fs->blksz);
- if (!journal_buffer)
- return -ENOMEM;
- /* get the block group descriptor table */
- bgd = (struct ext2_block_group *)fs->gdtable;
- status = ext4fs_read_inode(ext4fs_root, inodeno, &inode);
- if (status == 0)
- goto fail;
-
- /* read the block no allocated to a file */
- no_blocks = inode.size / fs->blksz;
- if (inode.size % fs->blksz)
- no_blocks++;
-
- if (le32_to_cpu(inode.flags) & EXT4_EXTENTS_FL) {
- struct ext2fs_node *node_inode =
- zalloc(sizeof(struct ext2fs_node));
- if (!node_inode)
- goto fail;
- node_inode->data = ext4fs_root;
- node_inode->ino = inodeno;
- node_inode->inode_read = 0;
- memcpy(&(node_inode->inode), &inode, sizeof(struct ext2_inode));
-
- for (i = 0; i < no_blocks; i++) {
- blknr = read_allocated_block(&(node_inode->inode), i);
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
- remainder = blknr % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
- bg_idx);
- debug("EXT4_EXTENTS Block releasing %ld: %d\n",
- blknr, bg_idx);
-
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
-
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- status =
- ext4fs_devread(bgd[bg_idx].block_id *
- fs->sect_perblk, 0,
- fs->blksz, journal_buffer);
- if (status == 0)
- goto fail;
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- }
- if (node_inode) {
- free(node_inode);
- node_inode = NULL;
- }
- } else {
-
- delete_single_indirect_block(&inode);
- delete_double_indirect_block(&inode);
- delete_triple_indirect_block(&inode);
-
- /* read the block no allocated to a file */
- no_blocks = inode.size / fs->blksz;
- if (inode.size % fs->blksz)
- no_blocks++;
- for (i = 0; i < no_blocks; i++) {
- blknr = read_allocated_block(&inode, i);
- if (fs->blksz != 1024) {
- bg_idx = blknr / blk_per_grp;
- } else {
- bg_idx = blknr / blk_per_grp;
- remainder = blknr % blk_per_grp;
- if (!remainder)
- bg_idx--;
- }
- ext4fs_reset_block_bmap(blknr, fs->blk_bmaps[bg_idx],
- bg_idx);
- debug("ActualB releasing %ld: %d\n", blknr, bg_idx);
-
- bgd[bg_idx].free_blocks++;
- fs->sb->free_blocks++;
- /* journal backup */
- if (prev_bg_bmap_idx != bg_idx) {
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(bgd[bg_idx].block_id
- * fs->sect_perblk,
- 0, fs->blksz,
- journal_buffer);
- if (status == 0)
- goto fail;
- if (ext4fs_log_journal(journal_buffer,
- bgd[bg_idx].block_id))
- goto fail;
- prev_bg_bmap_idx = bg_idx;
- }
- }
- }
-
- /* from the inode no to blockno */
- inodes_per_block = fs->blksz / fs->inodesz;
- ibmap_idx = inodeno / inode_per_grp;
-
- /* get the block no */
- inodeno--;
- blkno = __le32_to_cpu(bgd[ibmap_idx].inode_table_id) +
- (inodeno % __le32_to_cpu(inode_per_grp)) / inodes_per_block;
-
- /* get the offset of the inode */
- blkoff = ((inodeno) % inodes_per_block) * fs->inodesz;
-
- /* read the block no containing the inode */
- read_buffer = zalloc(fs->blksz);
- if (!read_buffer)
- goto fail;
- start_block_address = read_buffer;
- status = ext4fs_devread(blkno * fs->sect_perblk,
- 0, fs->blksz, read_buffer);
- if (status == 0)
- goto fail;
-
- if (ext4fs_log_journal(read_buffer, blkno))
- goto fail;
-
- read_buffer = read_buffer + blkoff;
- inode_buffer = (struct ext2_inode *)read_buffer;
- memset(inode_buffer, '\0', sizeof(struct ext2_inode));
-
- /* write the inode to original position in inode table */
- if (ext4fs_put_metadata(start_block_address, blkno))
- goto fail;
-
- /* update the respective inode bitmaps */
- inodeno++;
- ext4fs_reset_inode_bmap(inodeno, fs->inode_bmaps[ibmap_idx], ibmap_idx);
- bgd[ibmap_idx].free_inodes++;
- fs->sb->free_inodes++;
- /* journal backup */
- memset(journal_buffer, '\0', fs->blksz);
- status = ext4fs_devread(bgd[ibmap_idx].inode_id *
- fs->sect_perblk, 0, fs->blksz, journal_buffer);
- if (status == 0)
- goto fail;
- if (ext4fs_log_journal(journal_buffer, bgd[ibmap_idx].inode_id))
- goto fail;
-
- ext4fs_update();
- ext4fs_deinit();
-
- if (ext4fs_init() != 0) {
- printf("error in File System init\n");
- goto fail;
- }
-
- free(start_block_address);
- free(journal_buffer);
-
- return 0;
-fail:
- free(start_block_address);
- free(journal_buffer);
-
- return -1;
-}
-
-int ext4fs_init(void)
-{
- short status;
- int i;
- unsigned int real_free_blocks = 0;
- struct ext_filesystem *fs = get_fs();
-
- /* populate fs */
- fs->blksz = EXT2_BLOCK_SIZE(ext4fs_root);
- fs->inodesz = INODE_SIZE_FILESYSTEM(ext4fs_root);
- fs->sect_perblk = fs->blksz / SECTOR_SIZE;
-
- /* get the superblock */
- fs->sb = zalloc(SUPERBLOCK_SIZE);
- if (!fs->sb)
- return -ENOMEM;
- if (!ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE,
- (char *)fs->sb))
- goto fail;
-
- /* init journal */
- if (ext4fs_init_journal())
- goto fail;
-
- /* get total no of blockgroups */
- fs->no_blkgrp = (uint32_t)ext4fs_div_roundup(
- (ext4fs_root->sblock.total_blocks -
- ext4fs_root->sblock.first_data_block),
- ext4fs_root->sblock.blocks_per_group);
-
- /* get the block group descriptor table */
- fs->gdtable_blkno = ((EXT2_MIN_BLOCK_SIZE == fs->blksz) + 1);
- if (ext4fs_get_bgdtable() == -1) {
- printf("Error in getting the block group descriptor table\n");
- goto fail;
- }
- fs->bgd = (struct ext2_block_group *)fs->gdtable;
-
- /* load all the available bitmap block of the partition */
- fs->blk_bmaps = zalloc(fs->no_blkgrp * sizeof(char *));
- if (!fs->blk_bmaps)
- goto fail;
- for (i = 0; i < fs->no_blkgrp; i++) {
- fs->blk_bmaps[i] = zalloc(fs->blksz);
- if (!fs->blk_bmaps[i])
- goto fail;
- }
-
- for (i = 0; i < fs->no_blkgrp; i++) {
- status =
- ext4fs_devread(fs->bgd[i].block_id * fs->sect_perblk, 0,
- fs->blksz, (char *)fs->blk_bmaps[i]);
- if (status == 0)
- goto fail;
- }
-
- /* load all the available inode bitmap of the partition */
- fs->inode_bmaps = zalloc(fs->no_blkgrp * sizeof(unsigned char *));
- if (!fs->inode_bmaps)
- goto fail;
- for (i = 0; i < fs->no_blkgrp; i++) {
- fs->inode_bmaps[i] = zalloc(fs->blksz);
- if (!fs->inode_bmaps[i])
- goto fail;
- }
-
- for (i = 0; i < fs->no_blkgrp; i++) {
- status = ext4fs_devread(fs->bgd[i].inode_id * fs->sect_perblk,
- 0, fs->blksz,
- (char *)fs->inode_bmaps[i]);
- if (status == 0)
- goto fail;
- }
-
- /*
- * check filesystem consistency with free blocks of file system
- * some time we observed that superblock freeblocks does not match
- * with the blockgroups freeblocks when improper
- * reboot of a linux kernel
- */
- for (i = 0; i < fs->no_blkgrp; i++)
- real_free_blocks = real_free_blocks + fs->bgd[i].free_blocks;
- if (real_free_blocks != fs->sb->free_blocks)
- fs->sb->free_blocks = real_free_blocks;
-
- return 0;
-fail:
- ext4fs_deinit();
-
- return -1;
-}
-
-void ext4fs_deinit(void)
-{
- int i;
- struct ext2_inode inode_journal;
- struct journal_superblock_t *jsb;
- long int blknr;
- struct ext_filesystem *fs = get_fs();
-
- /* free journal */
- char *temp_buff = zalloc(fs->blksz);
- if (temp_buff) {
- ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
- &inode_journal);
- blknr = read_allocated_block(&inode_journal,
- EXT2_JOURNAL_SUPERBLOCK);
- ext4fs_devread(blknr * fs->sect_perblk, 0, fs->blksz,
- temp_buff);
- jsb = (struct journal_superblock_t *)temp_buff;
- jsb->s_start = cpu_to_be32(0);
- put_ext4((uint64_t) (blknr * fs->blksz),
- (struct journal_superblock_t *)temp_buff, fs->blksz);
- free(temp_buff);
- }
- ext4fs_free_journal();
-
- /* get the superblock */
- ext4fs_devread(SUPERBLOCK_SECTOR, 0, SUPERBLOCK_SIZE, (char *)fs->sb);
- fs->sb->feature_incompat &= ~EXT3_FEATURE_INCOMPAT_RECOVER;
- put_ext4((uint64_t)(SUPERBLOCK_SIZE),
- (struct ext2_sblock *)fs->sb, (uint32_t)SUPERBLOCK_SIZE);
- free(fs->sb);
- fs->sb = NULL;
-
- if (fs->blk_bmaps) {
- for (i = 0; i < fs->no_blkgrp; i++) {
- free(fs->blk_bmaps[i]);
- fs->blk_bmaps[i] = NULL;
- }
- free(fs->blk_bmaps);
- fs->blk_bmaps = NULL;
- }
-
- if (fs->inode_bmaps) {
- for (i = 0; i < fs->no_blkgrp; i++) {
- free(fs->inode_bmaps[i]);
- fs->inode_bmaps[i] = NULL;
- }
- free(fs->inode_bmaps);
- fs->inode_bmaps = NULL;
- }
-
-
- free(fs->gdtable);
- fs->gdtable = NULL;
- fs->bgd = NULL;
- /*
- * reinitiliazed the global inode and
- * block bitmap first execution check variables
- */
- fs->first_pass_ibmap = 0;
- fs->first_pass_bbmap = 0;
- fs->curr_inode_no = 0;
- fs->curr_blkno = 0;
-}
-
-static int ext4fs_write_file(struct ext2_inode *file_inode,
- int pos, unsigned int len, char *buf)
-{
- int i;
- int blockcnt;
- int log2blocksize = LOG2_EXT2_BLOCK_SIZE(ext4fs_root);
- unsigned int filesize = __le32_to_cpu(file_inode->size);
- struct ext_filesystem *fs = get_fs();
- int previous_block_number = -1;
- int delayed_start = 0;
- int delayed_extent = 0;
- int delayed_next = 0;
- char *delayed_buf = NULL;
-
- /* Adjust len so it we can't read past the end of the file. */
- if (len > filesize)
- len = filesize;
-
- blockcnt = ((len + pos) + fs->blksz - 1) / fs->blksz;
-
- for (i = pos / fs->blksz; i < blockcnt; i++) {
- long int blknr;
- int blockend = fs->blksz;
- int skipfirst = 0;
- blknr = read_allocated_block(file_inode, i);
- if (blknr < 0)
- return -1;
-
- blknr = blknr << log2blocksize;
-
- if (blknr) {
- if (previous_block_number != -1) {
- if (delayed_next == blknr) {
- delayed_extent += blockend;
- delayed_next += blockend >> SECTOR_BITS;
- } else { /* spill */
- put_ext4((uint64_t) (delayed_start *
- SECTOR_SIZE),
- delayed_buf,
- (uint32_t) delayed_extent);
- previous_block_number = blknr;
- delayed_start = blknr;
- delayed_extent = blockend;
- delayed_buf = buf;
- delayed_next = blknr +
- (blockend >> SECTOR_BITS);
- }
- } else {
- previous_block_number = blknr;
- delayed_start = blknr;
- delayed_extent = blockend;
- delayed_buf = buf;
- delayed_next = blknr +
- (blockend >> SECTOR_BITS);
- }
- } else {
- if (previous_block_number != -1) {
- /* spill */
- put_ext4((uint64_t) (delayed_start *
- SECTOR_SIZE), delayed_buf,
- (uint32_t) delayed_extent);
- previous_block_number = -1;
- }
- memset(buf, 0, fs->blksz - skipfirst);
- }
- buf += fs->blksz - skipfirst;
- }
- if (previous_block_number != -1) {
- /* spill */
- put_ext4((uint64_t) (delayed_start * SECTOR_SIZE),
- delayed_buf, (uint32_t) delayed_extent);
- previous_block_number = -1;
- }
-
- return len;
}
-int ext4fs_write(const char *fname, unsigned char *buffer,
- unsigned long sizebytes)
+int ext4_read_file(const char *filename, void *buf, int offset, int len)
{
- int ret = 0;
- struct ext2_inode *file_inode = NULL;
- unsigned char *inode_buffer = NULL;
- int parent_inodeno;
- int inodeno;
- time_t timestamp = 0;
-
- uint64_t bytes_reqd_for_file;
- unsigned int blks_reqd_for_file;
- unsigned int blocks_remaining;
- int existing_file_inodeno;
- char *temp_ptr = NULL;
- long int itable_blkno;
- long int parent_itable_blkno;
- long int blkoff;
- struct ext2_sblock *sblock = &(ext4fs_root->sblock);
- unsigned int inodes_per_block;
- unsigned int ibmap_idx;
- struct ext_filesystem *fs = get_fs();
- ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256);
- memset(filename, 0x00, sizeof(filename));
+ int file_len;
+ int len_read;
- g_parent_inode = zalloc(sizeof(struct ext2_inode));
- if (!g_parent_inode)
- goto fail;
-
- if (ext4fs_init() != 0) {
- printf("error in File System init\n");
+ if (offset != 0) {
+ printf("** Cannot support non-zero offset **\n");
return -1;
}
- inodes_per_block = fs->blksz / fs->inodesz;
- parent_inodeno = ext4fs_get_parent_inode_num(fname, filename, F_FILE);
- if (parent_inodeno == -1)
- goto fail;
- if (ext4fs_iget(parent_inodeno, g_parent_inode))
- goto fail;
- /* check if the filename is already present in root */
- existing_file_inodeno = ext4fs_filename_check(filename);
- if (existing_file_inodeno != -1) {
- ret = ext4fs_delete_file(existing_file_inodeno);
- fs->first_pass_bbmap = 0;
- fs->curr_blkno = 0;
-
- fs->first_pass_ibmap = 0;
- fs->curr_inode_no = 0;
- if (ret)
- goto fail;
- }
- /* calucalate how many blocks required */
- bytes_reqd_for_file = sizebytes;
- blks_reqd_for_file = lldiv(bytes_reqd_for_file, fs->blksz);
- if (do_div(bytes_reqd_for_file, fs->blksz) != 0) {
- blks_reqd_for_file++;
- debug("total bytes for a file %u\n", blks_reqd_for_file);
- }
- blocks_remaining = blks_reqd_for_file;
- /* test for available space in partition */
- if (fs->sb->free_blocks < blks_reqd_for_file) {
- printf("Not enough space on partition !!!\n");
- goto fail;
- }
- ext4fs_update_parent_dentry(filename, &inodeno, FILETYPE_REG);
- /* prepare file inode */
- inode_buffer = zalloc(fs->inodesz);
- if (!inode_buffer)
- goto fail;
- file_inode = (struct ext2_inode *)inode_buffer;
- file_inode->mode = S_IFREG | S_IRWXU |
- S_IRGRP | S_IROTH | S_IXGRP | S_IXOTH;
- /* ToDo: Update correct time */
- file_inode->mtime = timestamp;
- file_inode->atime = timestamp;
- file_inode->ctime = timestamp;
- file_inode->nlinks = 1;
- file_inode->size = sizebytes;
-
- /* Allocate data blocks */
- ext4fs_allocate_blocks(file_inode, blocks_remaining,
- &blks_reqd_for_file);
- file_inode->blockcnt = (blks_reqd_for_file * fs->blksz) / SECTOR_SIZE;
-
- temp_ptr = zalloc(fs->blksz);
- if (!temp_ptr)
- goto fail;
- ibmap_idx = inodeno / ext4fs_root->sblock.inodes_per_group;
- inodeno--;
- itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
- (inodeno % __le32_to_cpu(sblock->inodes_per_group)) /
- inodes_per_block;
- blkoff = (inodeno % inodes_per_block) * fs->inodesz;
- ext4fs_devread(itable_blkno * fs->sect_perblk, 0, fs->blksz, temp_ptr);
- if (ext4fs_log_journal(temp_ptr, itable_blkno))
- goto fail;
-
- memcpy(temp_ptr + blkoff, inode_buffer, fs->inodesz);
- if (ext4fs_put_metadata(temp_ptr, itable_blkno))
- goto fail;
- /* copy the file content into data blocks */
- if (ext4fs_write_file(file_inode, 0, sizebytes, (char *)buffer) == -1) {
- printf("Error in copying content\n");
- goto fail;
- }
- ibmap_idx = parent_inodeno / ext4fs_root->sblock.inodes_per_group;
- parent_inodeno--;
- parent_itable_blkno = __le32_to_cpu(fs->bgd[ibmap_idx].inode_table_id) +
- (parent_inodeno %
- __le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
- blkoff = (parent_inodeno % inodes_per_block) * fs->inodesz;
- if (parent_itable_blkno != itable_blkno) {
- memset(temp_ptr, '\0', fs->blksz);
- ext4fs_devread(parent_itable_blkno * fs->sect_perblk,
- 0, fs->blksz, temp_ptr);
- if (ext4fs_log_journal(temp_ptr, parent_itable_blkno))
- goto fail;
-
- memcpy(temp_ptr + blkoff, g_parent_inode,
- sizeof(struct ext2_inode));
- if (ext4fs_put_metadata(temp_ptr, parent_itable_blkno))
- goto fail;
- free(temp_ptr);
- } else {
- /*
- * If parent and child fall in same inode table block
- * both should be kept in 1 buffer
- */
- memcpy(temp_ptr + blkoff, g_parent_inode,
- sizeof(struct ext2_inode));
- gd_index--;
- if (ext4fs_put_metadata(temp_ptr, itable_blkno))
- goto fail;
- free(temp_ptr);
+ file_len = ext4fs_open(filename);
+ if (file_len < 0) {
+ printf("** File not found %s **\n", filename);
+ return -1;
}
- ext4fs_update();
- ext4fs_deinit();
- fs->first_pass_bbmap = 0;
- fs->curr_blkno = 0;
- fs->first_pass_ibmap = 0;
- fs->curr_inode_no = 0;
- free(inode_buffer);
- free(g_parent_inode);
- g_parent_inode = NULL;
+ if (len == 0)
+ len = file_len;
- return 0;
-fail:
- ext4fs_deinit();
- free(inode_buffer);
- free(g_parent_inode);
- g_parent_inode = NULL;
+ len_read = ext4fs_read(buf, len);
- return -1;
+ return len_read;
}
-#endif
{
return file_fat_read_at(filename, 0, buffer, maxsize);
}
+
+int fat_read_file(const char *filename, void *buf, int offset, int len)
+{
+ int len_read;
+
+ len_read = file_fat_read_at(filename, offset, buf, len);
+ if (len_read == -1) {
+ printf("** Unable to read file %s **\n", filename);
+ return -1;
+ }
+
+ return len_read;
+}
+
+void fat_close(void)
+{
+}
#include <ext4fs.h>
#include <fat.h>
#include <fs.h>
+#include <sandboxfs.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
static disk_partition_t fs_partition;
static int fs_type = FS_TYPE_ANY;
-static inline int fs_ls_unsupported(const char *dirname)
+static inline int fs_probe_unsupported(block_dev_desc_t *fs_dev_desc,
+ disk_partition_t *fs_partition)
{
printf("** Unrecognized filesystem type **\n");
return -1;
}
-static inline int fs_read_unsupported(const char *filename, ulong addr,
- int offset, int len)
-{
- printf("** Unrecognized filesystem type **\n");
- return -1;
-}
-
-#ifdef CONFIG_FS_FAT
-static int fs_probe_fat(void)
-{
- return fat_set_blk_dev(fs_dev_desc, &fs_partition);
-}
-
-static void fs_close_fat(void)
-{
-}
-
-#define fs_ls_fat file_fat_ls
-
-static int fs_read_fat(const char *filename, ulong addr, int offset, int len)
-{
- int len_read;
-
- len_read = file_fat_read_at(filename, offset,
- (unsigned char *)addr, len);
- if (len_read == -1) {
- printf("** Unable to read file %s **\n", filename);
- return -1;
- }
-
- return len_read;
-}
-#else
-static inline int fs_probe_fat(void)
+static inline int fs_ls_unsupported(const char *dirname)
{
return -1;
}
-static inline void fs_close_fat(void)
-{
-}
-
-#define fs_ls_fat fs_ls_unsupported
-#define fs_read_fat fs_read_unsupported
-#endif
-
-#ifdef CONFIG_FS_EXT4
-static int fs_probe_ext(void)
-{
- ext4fs_set_blk_dev(fs_dev_desc, &fs_partition);
-
- if (!ext4fs_mount(fs_partition.size)) {
- ext4fs_close();
- return -1;
- }
-
- return 0;
-}
-
-static void fs_close_ext(void)
-{
- ext4fs_close();
-}
-
-#define fs_ls_ext ext4fs_ls
-
-static int fs_read_ext(const char *filename, ulong addr, int offset, int len)
-{
- int file_len;
- int len_read;
-
- if (offset != 0) {
- printf("** Cannot support non-zero offset **\n");
- return -1;
- }
-
- file_len = ext4fs_open(filename);
- if (file_len < 0) {
- printf("** File not found %s **\n", filename);
- ext4fs_close();
- return -1;
- }
-
- if (len == 0)
- len = file_len;
-
- len_read = ext4fs_read((char *)addr, len);
- ext4fs_close();
-
- if (len_read != len) {
- printf("** Unable to read file %s **\n", filename);
- return -1;
- }
-
- return len_read;
-}
-#else
-static inline int fs_probe_ext(void)
+static inline int fs_read_unsupported(const char *filename, void *buf,
+ int offset, int len)
{
return -1;
}
-static inline void fs_close_ext(void)
+static inline void fs_close_unsupported(void)
{
}
-#define fs_ls_ext fs_ls_unsupported
-#define fs_read_ext fs_read_unsupported
-#endif
-
-static struct {
+struct fstype_info {
int fstype;
- int (*probe)(void);
-} fstypes[] = {
+ int (*probe)(block_dev_desc_t *fs_dev_desc,
+ disk_partition_t *fs_partition);
+ int (*ls)(const char *dirname);
+ int (*read)(const char *filename, void *buf, int offset, int len);
+ void (*close)(void);
+};
+
+static struct fstype_info fstypes[] = {
+#ifdef CONFIG_FS_FAT
{
.fstype = FS_TYPE_FAT,
- .probe = fs_probe_fat,
+ .probe = fat_set_blk_dev,
+ .close = fat_close,
+ .ls = file_fat_ls,
+ .read = fat_read_file,
},
+#endif
+#ifdef CONFIG_FS_EXT4
{
.fstype = FS_TYPE_EXT,
- .probe = fs_probe_ext,
+ .probe = ext4fs_probe,
+ .close = ext4fs_close,
+ .ls = ext4fs_ls,
+ .read = ext4_read_file,
+ },
+#endif
+#ifdef CONFIG_SANDBOX
+ {
+ .fstype = FS_TYPE_SANDBOX,
+ .probe = sandbox_fs_set_blk_dev,
+ .close = sandbox_fs_close,
+ .ls = sandbox_fs_ls,
+ .read = fs_read_sandbox,
+ },
+#endif
+ {
+ .fstype = FS_TYPE_ANY,
+ .probe = fs_probe_unsupported,
+ .close = fs_close_unsupported,
+ .ls = fs_ls_unsupported,
+ .read = fs_read_unsupported,
},
};
+static struct fstype_info *fs_get_info(int fstype)
+{
+ struct fstype_info *info;
+ int i;
+
+ for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes) - 1; i++, info++) {
+ if (fstype == info->fstype)
+ return info;
+ }
+
+ /* Return the 'unsupported' sentinel */
+ return info;
+}
+
int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype)
{
+ struct fstype_info *info;
int part, i;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
static int relocated;
if (!relocated) {
- for (i = 0; i < ARRAY_SIZE(fstypes); i++)
- fstypes[i].probe += gd->reloc_off;
+ for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes);
+ i++, info++) {
+ info->probe += gd->reloc_off;
+ info->close += gd->reloc_off;
+ info->ls += gd->reloc_off;
+ info->read += gd->reloc_off;
+ }
relocated = 1;
}
#endif
if (part < 0)
return -1;
- for (i = 0; i < ARRAY_SIZE(fstypes); i++) {
- if ((fstype != FS_TYPE_ANY) && (fstype != fstypes[i].fstype))
+ for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes); i++, info++) {
+ if (fstype != FS_TYPE_ANY && info->fstype != FS_TYPE_ANY &&
+ fstype != info->fstype)
continue;
- if (!fstypes[i].probe()) {
- fs_type = fstypes[i].fstype;
+ if (!info->probe(fs_dev_desc, &fs_partition)) {
+ fs_type = info->fstype;
return 0;
}
}
- printf("** Unrecognized filesystem type **\n");
return -1;
}
static void fs_close(void)
{
- switch (fs_type) {
- case FS_TYPE_FAT:
- fs_close_fat();
- break;
- case FS_TYPE_EXT:
- fs_close_ext();
- break;
- default:
- break;
- }
+ struct fstype_info *info = fs_get_info(fs_type);
+
+ info->close();
fs_type = FS_TYPE_ANY;
}
{
int ret;
- switch (fs_type) {
- case FS_TYPE_FAT:
- ret = fs_ls_fat(dirname);
- break;
- case FS_TYPE_EXT:
- ret = fs_ls_ext(dirname);
- break;
- default:
- ret = fs_ls_unsupported(dirname);
- break;
- }
+ struct fstype_info *info = fs_get_info(fs_type);
+ ret = info->ls(dirname);
+
+ fs_type = FS_TYPE_ANY;
fs_close();
return ret;
int fs_read(const char *filename, ulong addr, int offset, int len)
{
+ struct fstype_info *info = fs_get_info(fs_type);
+ void *buf;
int ret;
- switch (fs_type) {
- case FS_TYPE_FAT:
- ret = fs_read_fat(filename, addr, offset, len);
- break;
- case FS_TYPE_EXT:
- ret = fs_read_ext(filename, addr, offset, len);
- break;
- default:
- ret = fs_read_unsupported(filename, addr, offset, len);
- break;
- }
+ /*
+ * We don't actually know how many bytes are being read, since len==0
+ * means read the whole file.
+ */
+ buf = map_sysmem(addr, len);
+ ret = info->read(filename, buf, offset, len);
+ unmap_sysmem(buf);
+ /* If we requested a specific number of bytes, check we got it */
+ if (ret >= 0 && len && ret != len) {
+ printf("** Unable to read file %s **\n", filename);
+ ret = -1;
+ }
fs_close();
return ret;
unsigned long bytes;
unsigned long pos;
int len_read;
- char buf[12];
unsigned long time;
if (argc < 2)
}
puts("\n");
- sprintf(buf, "0x%x", len_read);
- setenv("filesize", buf);
+ setenv_hex("filesize", len_read);
return 0;
}
--- /dev/null
+#
+# Copyright (c) 2012, Google Inc.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Pavel Bartusek, Sysgo Real-Time Solutions AG, pba@sysgo.de
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libsandboxfs.o
+
+COBJS-$(CONFIG_SANDBOX) := sandboxfs.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS-y))
+
+all: $(LIB) $(AOBJS)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (c) 2012, Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fs.h>
+#include <os.h>
+
+int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info)
+{
+ return 0;
+}
+
+long sandbox_fs_read_at(const char *filename, unsigned long pos,
+ void *buffer, unsigned long maxsize)
+{
+ ssize_t size;
+ int fd, ret;
+
+ fd = os_open(filename, OS_O_RDONLY);
+ if (fd < 0)
+ return fd;
+ ret = os_lseek(fd, pos, OS_SEEK_SET);
+ if (ret == -1) {
+ os_close(fd);
+ return ret;
+ }
+ if (!maxsize)
+ maxsize = os_get_filesize(filename);
+ size = os_read(fd, buffer, maxsize);
+ os_close(fd);
+
+ return size;
+}
+
+int sandbox_fs_ls(const char *dirname)
+{
+ struct os_dirent_node *head, *node;
+ int ret;
+
+ ret = os_dirent_ls(dirname, &head);
+ if (ret)
+ return ret;
+
+ for (node = head; node; node = node->next) {
+ printf("%s %10lu %s\n", os_dirent_get_typename(node->type),
+ node->size, node->name);
+ }
+
+ return 0;
+}
+
+void sandbox_fs_close(void)
+{
+}
+
+int fs_read_sandbox(const char *filename, void *buf, int offset, int len)
+{
+ int len_read;
+
+ len_read = sandbox_fs_read_at(filename, offset, buf, len);
+ if (len_read == -1) {
+ printf("** Unable to read file %s **\n", filename);
+ return -1;
+ }
+
+ return len_read;
+}
.get_sb = ubifs_get_sb,
};
-int ubifs_mount(char *vol_name)
+int ubifs_mount(char *name)
{
int flags;
- char name[80] = "ubi:";
void *data;
struct vfsmount *mnt;
int ret;
* Mount in read-only mode
*/
flags = MS_RDONLY;
- strcat(name, vol_name);
data = NULL;
mnt = NULL;
ret = ubifs_get_sb(&ubifs_fs_type, flags, name, data, mnt);
int i;
int count;
int last_block_size = 0;
- char buf [10];
c->ubi = ubi_open_volume(c->vi.ubi_num, c->vi.vol_id, UBI_READONLY);
/* ubifs_findfile will resolve symlinks, so we know that we get
if (err)
printf("Error reading file '%s'\n", filename);
else {
- sprintf(buf, "%X", size);
- setenv("filesize", buf);
+ setenv_hex("filesize", size);
printf("Done\n");
}
+++ /dev/null
-#
-# Copyright (C) 2012 Marek Vasut <marex@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-#########################################################################
-
-##
-# make_u_boot_list - Generate contents of u_boot_list section
-# 1: The name of the resulting file (usually u-boot.lst)
-# 2: Files to analyze for possible u_boot_list entries
-#
-# This function generates the contents of the u_boot_list section,
-# including all the border symbols for it's subsections. The operation
-# of this function is as follows, numbering goes per lines:
-#
-# 1) Dump the ELF header sections from all files supplied via $(2)
-# 2) Filter out all other stuff that does not belong into .u_boot_list
-# section.
-# 3) Fix up the lines so that the resulting output is is in format
-# ".u_boot_list.*".
-# 4) Remove the last .something$, since that only contains the name
-# of the variable to be put into a subsection. This name is irelevant
-# for generation of border symbols, thus of no interest, remove it.
-# 5) Take each line and for every dot "." in that line, print the whole
-# line until that dot "." . This is important so that we have all
-# parent border symbols generated as well.
-# 6) Load every line and firstly append "\a" at the end and print the
-# line. Next, append "@" at the end and print the line. Finally,
-# append "~" at the end of line. This will make sense in conjunction
-# with 6) and 7).
-# 7) Sort the lines. It is imperative to use LC_COLLATE=C here because
-# with this, the "\a" symbol is first and "~" symbol is last. Any
-# other symbols fall inbetween. Symbols like "@", which marks the
-# end of current line (representing current section) and ".", which
-# means the line continues and thus represents subsection.
-# 8) With such ordering, all lines ending with "\a" will float at the
-# begining of all lines with the same prefix. Thus it is easy to
-# replace "\a" with __start and make it the __start border symbol.
-# Very similarly for "~", which will be always at the bottom and so
-# can be replaced by "__end" and made into the __end border symbol.
-# Finally, every line ending with "@" symbol will be transformed
-# into " *(SORT(${line}*)); " format, which in the linker parlance
-# will allow it to trap all symbols relevant to the subsection.
-#
-define make_u_boot_list
-$(1): $(2)
- $(OBJDUMP) -h $(2) | \
- sed -n -e '/.*\.u_boot_list[^ ]\+/ ! {d;n}' \
- -e 's/.*\(\.u_boot_list[^ ]\+\).*$$$$/\1/' \
- -e 's/\.[^\.]\+$$$$//' \
- -e ':s /^.\+$$$$/ { p;s/^\(.*\)\.[^\.]*$$$$/\1/;b s }' | \
- sed -n -e 'h;s/$$$$/\a/p;g;s/$$$$/@/p;g;s/$$$$/~/p;' | \
- LC_COLLATE=C sort -u | \
- sed -n -e '/\a$$$$/ { s/\./_/g;s/\a$$$$/__start = .;/p; }'\
- -e '/~$$$$/ { s/\./_/g;s/~$$$$/__end = .;/p; }'\
- -e '/@$$$$/ { s/\(.*\)@$$$$/*(SORT(\1.*));/p }' > $(1)
-endef
_usage, _help, NULL)
#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
- ll_entry_declare(cmd_tbl_t, _name, cmd, cmd) = \
+ ll_entry_declare(cmd_tbl_t, _name, cmd) = \
U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
_usage, _help, _comp);
phys_size_t initdram (int);
int display_options (void);
void print_size(unsigned long long, const char *);
-int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen);
+int print_buffer(ulong addr, const void *data, uint width, uint count,
+ uint linelen);
/* common/main.c */
void main_loop (void);
int saveenv (void);
int setenv (const char *, const char *);
int setenv_ulong(const char *varname, ulong value);
-int setenv_addr(const char *varname, const void *addr);
+int setenv_hex(const char *varname, ulong value);
+/**
+ * setenv_addr - Set an environment variable to an address in hex
+ *
+ * @varname: Environmet variable to set
+ * @addr: Value to set it to
+ * @return 0 if ok, 1 on error
+ */
+static inline int setenv_addr(const char *varname, const void *addr)
+{
+ return setenv_hex(varname, (ulong)addr);
+}
+
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
# include <asm/setup.h>
int cpu_release(int nr, int argc, char * const argv[]);
#endif
+/* Define a null map_sysmem() if the architecture doesn't use it */
+# ifndef CONFIG_ARCH_MAP_SYSMEM
+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
+{
+ return (void *)(uintptr_t)paddr;
+}
+
+static inline void unmap_sysmem(const void *vaddr)
+{
+}
+# endif
+
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_PPC
#define CONFIG_CMD_RARP /* rarpboot support */
#define CONFIG_CMD_READ /* Read data from partition */
#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SANDBOX /* sb command to access sandbox features */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SAVES /* save S record dump */
#define CONFIG_CMD_SCSI /* SCSI Support */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_BOOTDELAY 1
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
"if test $board_name = A335X_SK; then " \
"setenv fdtfile am335x-evmsk.dtb; fi\0" \
+#endif
+
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x80000
#define CONFIG_SPL_MUSB_NEW_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_AM33XX_BCH
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/*
- * Disable UART, CPSW ethernet support and extra environment settings so we
- * will fit within 101KiB.
+ * Disable CPSW SPL support so we fit within the 101KiB limit.
*/
#undef CONFIG_SPL_ETH_SUPPORT
-#undef CONFIG_SPL_YMODEM_SUPPORT
-#undef CONFIG_EXTRA_ENV_SETTINGS
#endif
/*
"root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \
"bootcmd_nand=" \
"run bootargs_nand && ubi part root 2048 && " \
- "ubifsmount rootfs && ubifsload 41000000 boot/uImage && " \
+ "ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \
"bootm 41000000\0" \
"bootargs_mmc=" \
"setenv bootargs ${kernelargs} " \
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
/*
* Memory Configuration
*/
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#endif
/* DataFlash */
+#ifndef CONFIG_AT91SAM9G20EK_2MMC
#define CONFIG_ATMEL_DATAFLASH_SPI
#define CONFIG_HAS_DATAFLASH 1
#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
#define AT91_SPI_CLK 15000000
+#endif
#ifdef CONFIG_AT91SAM9G20EK
#define DATAFLASH_TCSS (0x22 << 16)
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
-#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
- "root=/dev/mtdblock5 " \
- "mtdparts=atmel_nand:128k(bootstrap)ro," \
- "256k(uboot)ro,128k(env1)ro," \
- "128k(env2)ro,2M(linux),-(root) " \
- "rw rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk " \
+ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
+ "256k(env),256k(env_redundant),256k(spare)," \
+ "512k(dtb),6M(kernel)ro,-(rootfs) " \
+ "root=/dev/mtdblock7 rw rootfstype=jffs2"
#endif
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
-#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
- "root=/dev/mtdblock5 " \
- "mtdparts=atmel_nand:128k(bootstrap)ro," \
- "256k(uboot)ro,128k(env1)ro," \
- "128k(env2)ro,2M(linux),-(root) " \
- "rw rootfstype=jffs2"
-
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk " \
+ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
+ "256k(env),256k(env_redundant),256k(spare)," \
+ "512k(dtb),6M(kernel)ro,-(rootfs) " \
+ "root=/dev/mtdblock7 rw rootfstype=jffs2"
#endif
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
/*
* Hardware drivers
*/
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
-#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
-#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
- "root=/dev/mtdblock5 " \
- "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
- "rw rootfstype=jffs2"
-
+#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk " \
+ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
+ "256k(env),256k(env_redundant),256k(spare)," \
+ "512k(dtb),6M(kernel)ro,-(rootfs) " \
+ "root=/dev/mtdblock7 rw rootfstype=jffs2"
#endif
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_CMD_BOOTZ
#define CONFIG_OF_LIBFDT
/* general purpose I/O */
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x60000
-#define CONFIG_ENV_OFFSET_REDUND 0x80000
+#define CONFIG_ENV_OFFSET 0xc0000
+#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_ENV_SIZE 0x20000
-#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \
+#define CONFIG_BOOTCOMMAND \
+ "nand read 0x70000000 0x200000 0x300000;" \
"bootm 0x70000000"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk " \
- "root=/dev/mtdblock5 " \
- "mtdparts=atmel_nand:128k(bootstrap)ro," \
- "256k(uboot)ro,128k(env1)ro,128k(env2)ro," \
- "2M@1M(linux),-(root) " \
- "rw rootfstype=jffs2"
+ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
+ "256k(env),256k(env_redundant),256k(spare)," \
+ "512k(dtb),6M(kernel)ro,-(rootfs) " \
+ "root=/dev/mtdblock7 rw rootfstype=jffs2"
#define CONFIG_BAUDRATE 115200
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
#define CONFIG_ATMEL_LEGACY
#define CONFIG_AT91_GPIO 1
#define CONFIG_AT91_GPIO_PULLUP 1
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_CMD_BOOTZ
#define CONFIG_OF_LIBFDT
/* general purpose I/O */
"root=/dev/mmcblk0p2 " \
"rw rootfstype=ext4 rootwait"
#else
-#define CONFIG_BOOTARGS "mem=128M console=ttyS0,115200 " \
- "mtdparts=atmel_nand:" \
- "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \
- "root=/dev/mtdblock1 rw " \
- "rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"
+#define CONFIG_BOOTARGS \
+ "console=ttyS0,115200 earlyprintk " \
+ "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
+ "256k(env),256k(env_redundant),256k(spare)," \
+ "512k(dtb),6M(kernel)ro,-(rootfs) " \
+ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw"
#endif
#define CONFIG_BAUDRATE 115200
--- /dev/null
+/*
+ * U-boot - Configuration file for BF609 EZ-Kit board
+ */
+
+#ifndef __CONFIG_BF609_EZKIT_H__
+#define __CONFIG_BF609_EZKIT_H__
+
+#include <asm/config-pre.h>
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU bf609-0.0
+#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
+
+
+/* For ez-board version 1.0, else undef this */
+#define CONFIG_BFIN_BOARD_VERSION_1_0
+
+/*
+ * Clock Settings
+ * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ * SCLK = (CLKIN * VCO_MULT) / SYSCLK_DIV
+ * SCLK0 = SCLK / SCLK0_DIV
+ * SCLK1 = SCLK / SCLK1_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz */
+#define CONFIG_CLKIN_HZ (25000000)
+/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
+/* 1 = CLKIN / 2 */
+#define CONFIG_CLKIN_HALF (0)
+
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
+/* Values can range from 0-127 (where 0 means 128) */
+#define CONFIG_VCO_MULT (20)
+
+/* CCLK_DIV controls the core clock divider */
+/* Values can range from 0-31 (where 0 means 32) */
+#define CONFIG_CCLK_DIV (1)
+/* SCLK_DIV controls the system clock divider */
+/* Values can range from 0-31 (where 0 means 32) */
+#define CONFIG_SCLK_DIV (4)
+/* Values can range from 0-7 (where 0 means 8) */
+#define CONFIG_SCLK0_DIV (1)
+#define CONFIG_SCLK1_DIV (1)
+/* DCLK_DIV controls the DDR clock divider */
+/* Values can range from 0-31 (where 0 means 32) */
+#define CONFIG_DCLK_DIV (2)
+/* OCLK_DIV controls the output clock divider */
+/* Values can range from 0-127 (where 0 means 128) */
+#define CONFIG_OCLK_DIV (16)
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_SIZE 128
+
+#define CONFIG_SMC_GCTL_VAL 0x00000010
+#define CONFIG_SMC_B0CTL_VAL 0x01007011
+#define CONFIG_SMC_B0TIM_VAL 0x08170977
+#define CONFIG_SMC_B0ETIM_VAL 0x00092231
+
+#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+
+#define CONFIG_HW_WATCHDOG
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK
+#define CONFIG_NETCONSOLE
+#define CONFIG_NET_MULTI
+#define CONFIG_HOSTNAME "bf609-ezkit"
+#define CONFIG_DESIGNWARE_ETH
+#define CONFIG_DW_PORTS 1
+#define CONFIG_DW_AUTONEG
+#define CONFIG_DW_ALTDESCRIPTOR
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_MII
+
+/* i2c Settings */
+#define CONFIG_BFIN_TWI_I2C
+#define CONFIG_HARD_I2C
+
+/*
+ * Flash Settings
+ */
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#define CONFIG_SYS_FLASH_CFI_WIDTH 2
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE 0xb0000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 131
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI6XX
+#define CONFIG_ENV_SPI_MAX_HZ 25000000
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET 0x10000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET 0x60000
+#define CONFIG_ENV_SIZE 0x20000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_OFFSET 0x8000
+#define CONFIG_ENV_SIZE 0x8000
+#define CONFIG_ENV_SECT_SIZE 0x8000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0xB0100000\0"
+
+/*
+ * SDH Settings
+ */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_BFIN_SDH
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_UART_CONSOLE 0
+
+#define CONFIG_CMD_MEMORY
+
+#define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 20*1024*1024 + 4)
+#define CONFIG_BFIN_SOFT_SWITCH
+
+#if 0
+#define CONFIG_UART_MEM 1024
+#undef CONFIG_UART_CONSOLE
+#undef CONFIG_JTAG_CONSOLE
+#undef CONFIG_UART_CONSOLE_IS_JTAG
+#endif
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+#endif
*/
#ifndef _CONFIG_CMD_DEFAULT_H
# include <config_cmd_default.h>
-# if ADI_CMDS_NETWORK
+# ifdef ADI_CMDS_NETWORK
# define CONFIG_CMD_DHCP
# define CONFIG_BOOTP_SUBNETMASK
# define CONFIG_BOOTP_GATEWAY
# endif
# ifdef CONFIG_RTC_BFIN
# define CONFIG_CMD_DATE
-# if ADI_CMDS_NETWORK
+# ifdef ADI_CMDS_NETWORK
# define CONFIG_CMD_SNTP
# endif
# endif
"nand erase 0 0x40000;" \
"nand write $(loadaddr) 0 0x40000"
# else
-# define UBOOT_ENV_UPDATE \
+# ifndef UBOOT_ENV_UPDATE
+# define UBOOT_ENV_UPDATE \
"protect off 0x20000000 +$(filesize);" \
"erase 0x20000000 +$(filesize);" \
"cp.b $(loadaddr) 0x20000000 $(filesize)"
+# endif
# endif
# ifdef CONFIG_NETCONSOLE
# define NETCONSOLE_ENV \
"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
"kernel_addr_r=80600000\0" \
"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
- "ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \
+ "ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
"ubifsload ${kernel_addr_r} boot/uImage\0" \
"fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
"img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
#define STATUS_LED_BOOT STATUS_LED_BIT
#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
+#define CONFIG_SPLASHIMAGE_GUARD
+
/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
#endif
+/* Display Configuration */
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_VIDEO_OMAP3
+#define LCD_BPP LCD_COLOR16
+
+#define CONFIG_LCD
+
#endif /* __CONFIG_H */
#define CONFIG_ZBOOT_32
#define CONFIG_PHYSMEM
+#define CONFIG_LMB
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+#define CONFIG_DEFAULT_DEVICE_TREE link
+
/*-----------------------------------------------------------------------
* Watchdog Configuration
*/
/* SPL OS boot options */
#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_OS_BOOT_KEY 26
#define CONFIG_CMD_SPL
#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
"ubi part root; " \
- "ubifsmount root; " \
+ "ubifsmount ubi:root; " \
"ubifsload 0x800000 ${kernel}; " \
"ubifsload 0x1100000 ${initrd}; " \
"bootm 0x800000 0x1100000"
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Lokesh Vutla <lokeshvutla@ti.com>
+ *
+ * Configuration settings for the TI DRA7XX board.
+ * See omap5_common.h for omap5 common settings.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_DRA7XX_EVM_H
+#define __CONFIG_DRA7XX_EVM_H
+
+#include <configs/omap5_common.h>
+
+#define CONFIG_DRA7XX /* in a TI DRA7XX core */
+#define CONFIG_SYS_PROMPT "DRA752 EVM # "
+
+#endif /* __CONFIG_DRA7XX_EVM_H */
"bootm ${kernel_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "nand_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "nand_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
"ubifsload ${kernel_addr_r} /boot/uImage;" \
"ubifsumount; run nandargs addip addtty " \
"addmtd addmisc addmem;clrlogo;" \
"bootm ${kernel_addr_r}\0" \
- "nand_nandrw=ubi part nand0,${as};ubifsmount rootfs;" \
+ "nand_nandrw=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
"ubifsload ${kernel_addr_r} /boot/uImage;" \
"ubifsumount; run nandrwargs addip addtty " \
"addmtd addmisc addmem;clrlogo;" \
"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load_magic=if sf probe 0;then sf " \
"read c0000000 0x10000 0x60000;fi\0" \
- "load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
+ "load_nand=ubi part nand0,${as};ubifsmount ubi:rootfs;" \
"if ubifsload c0000014 /boot/u-boot.bin;" \
"then mw c0000008 ${filesize};else echo Error reading" \
" u-boot from nand!;fi\0" \
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
"ubi part root; " \
- "ubifsmount root; " \
+ "ubifsmount ubi:root; " \
"ubifsload 0x800000 ${kernel}; " \
"ubifsload 0x1100000 ${initrd}; " \
"bootm 0x800000 0x1100000"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
"ubi part rootfs; " \
- "ubifsmount rootfs; " \
+ "ubifsmount ubi:rootfs; " \
"ubifsload 0x800000 ${kernel}; " \
"bootm 0x800000"
"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
+#ifdef CONFIG_NAND_ECC_BCH
+#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0"
+#define CONFIG_KM_ECC_MODE " eccmode=bch"
+#else
+#define CONFIG_KM_UIMAGE_NAME "uImage\0"
+#define CONFIG_KM_ECC_MODE
+#endif
+
/*
* boottargets
* - set 'subbootcmds'
":${hostname}:${netdev}:off3" \
" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \
" mem=${kernelmem} init=${init}" \
+ CONFIG_KM_ECC_MODE \
" phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\
" " CONFIG_KM_UBI_LINUX_MTD " " \
CONFIG_KM_DEF_BOOT_ARGS_CPU \
*/
#define CONFIG_KM_DEF_ENV_FLASH_BOOT \
"cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \
- "cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \
+ "cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0" \
"ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR) \
" bootfs${boot_bank}\0" \
+ "uimage=" CONFIG_KM_UIMAGE_NAME \
CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
/*
#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
-#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
+#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
#define CONFIG_CMD_DIAG 1
/* include common defines/options for all 83xx Keymile boards */
/* at end of uboot partition, before env */
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000
-#define CONFIG_MISC_INIT_R
-
/*
* System IO Config
*/
/* include common defines/options for all 83xx Keymile boards */
#include "km83xx-common.h"
-#define CONFIG_MISC_INIT_R
-
/*
* System IO Config
*/
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
+#if !defined(CONFIG_MPC8309)
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
+#endif
#ifdef CONFIG_UEC_ETH1
-#if defined(CONFIG_MPC8309)
-#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
-#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
-#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
-#else
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
-#endif
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
CONFIG_KM_DEF_ARCH \
- "dtt_bus=pca9547:70:a\0" \
"EEprom_ivm=pca9547:70:9\0" \
"newenv=" \
"prot off 0xF00C0000 +0x40000 && " \
#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
#define CONFIG_CMD_NAND
+#define CONFIG_NAND_ECC_BCH
+#define CONFIG_BCH
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MISC_INIT_R
-#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
"ext2load mmc1 0 ${loadaddr} autoboot.scr; then " \
"source ${loadaddr}; " \
"fi; " \
- "ubi part boot && ubifsmount boot && ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
+ "ubi part boot && ubifsmount ubi:boot && " \
+ "ubifsload ${loadaddr} uImage && bootm ${loadaddr}"
#define CONFIG_AUTO_COMPLETE 1
/*
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
-
+#define CONFIG_CMD_BOOTZ
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
--- /dev/null
+/*
+ * (C) Copyright 2013
+ * Texas Instruments Incorporated.
+ * Sricharan R <r.sricharan@ti.com>
+ *
+ * Derived from OMAP4 done by:
+ * Aneesh V <aneesh@ti.com>
+ *
+ * TI OMAP5 AND DRA7XX common configuration settings
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_OMAP5_COMMON_H
+#define __CONFIG_OMAP5_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_OMAP54XX /* which is a 54XX */
+#define CONFIG_OMAP_GPIO
+
+/* Get CPU defs */
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap.h>
+
+/* Display CPU and Board Info */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 19200000 /* Clock output from T2 */
+#define V_SCLK V_OSCK
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128k
+ * Malloc - add 256k
+ */
+#define CONFIG_ENV_SIZE (128 << 10)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
+/* Vector Base */
+#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_DRIVER_OMAP34XX_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+
+/* MMC */
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET 0xE0000
+#define CONFIG_CMD_SAVEENV
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* Flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* Cache */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_CACHELINE_SHIFT 6
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_SAVEENV
+
+/* Disabled commands */
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*
+ * Environment setup
+ */
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyO2,115200n8\0" \
+ "usbtty=cdc_acm\0" \
+ "vram=16M\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "vram=${vram} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc${mmcdev} ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/*
+ * memtest setup
+ */
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+
+/* Use General purpose timer 1 */
+#define CONFIG_SYS_TIMERBASE GPT2_BASE
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * SDRAM Memory Map
+ * Even though we use two CS all the memory
+ * is mapped to one contiguous block
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40300350
+#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SPL_DISPLAY_PRINT
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 80E7FFC0--0x80E80000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x80E80000
+
+/*
+ * BSS and malloc area 64MB into memory to allow enough
+ * space for the kernel at the beginning of memory
+ */
+#define CONFIG_SPL_BSS_START_ADDR 0x84000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#endif /* __CONFIG_OMAP5_COMMON_H */
/*
- * (C) Copyright 2010
+ * (C) Copyright 2013
* Texas Instruments Incorporated.
* Sricharan R <r.sricharan@ti.com>
*
- * Derived from OMAP4 done by:
- * Aneesh V <aneesh@ti.com>
- *
* Configuration settings for the TI EVM5430 board.
+ * See omap5_common.h for omap5 common settings.
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_ARMV7 /* This is an ARM V7 CPU core */
-#define CONFIG_OMAP /* in a TI OMAP core */
-#define CONFIG_OMAP54XX /* which is a 54XX */
-#define CONFIG_OMAP5430 /* which is in a 5430 */
-#define CONFIG_5430EVM /* working with EVM */
-#define CONFIG_OMAP_GPIO
-
-/* Get CPU defs */
-#include <asm/arch/cpu.h>
-#include <asm/arch/omap.h>
-
-/* Display CPU and Board Info */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Clock Defines */
-#define V_OSCK 19200000 /* Clock output from T2 */
-#define V_SCLK V_OSCK
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-/*
- * Size of malloc() pool
- * Total Size Environment - 128k
- * Malloc - add 256k
- */
-#define CONFIG_ENV_SIZE (128 << 10)
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
-/* Vector Base */
-#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
-
-/*
- * Hardware drivers
- */
-
-/*
- * serial port - NS16550 compatible
- */
-#define V_NS16550_CLK 48000000
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
-#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-#define CONFIG_CONS_INDEX 3
-#define CONFIG_SYS_NS16550_COM3 UART3_BASE
+#ifndef __CONFIG_OMAP5_EVM_H
+#define __CONFIG_OMAP5_EVM_H
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-/* I2C */
-#define CONFIG_HARD_I2C
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 1
-#define CONFIG_DRIVER_OMAP34XX_I2C
-#define CONFIG_I2C_MULTI_BUS
+#include <configs/omap5_common.h>
/* TWL6035 */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_TWL6035_POWER
#endif
-/* MMC */
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_DOS_PARTITION
-
-/* MMC ENV related defines */
-#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
-#define CONFIG_ENV_OFFSET 0xE0000
-#define CONFIG_CMD_SAVEENV
-
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-
-/* Flash */
-#define CONFIG_SYS_NO_FLASH
-
-/* Cache */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_SYS_CACHELINE_SHIFT 6
-
-/* commands to include */
-#include <config_cmd_default.h>
-
-/* Enabled commands */
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_SAVEENV
-
-/* Disabled commands */
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
-#undef CONFIG_CMD_IMLS /* List all found images */
-
-/*
- * Environment setup
- */
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "usbtty=cdc_acm\0" \
- "vram=16M\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext3 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "vram=${vram} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_AUTO_COMPLETE 1
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "OMAP5430 EVM # "
-#define CONFIG_SYS_CBSIZE 256
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
-
-/*
- * memtest setup
- */
-#define CONFIG_SYS_MEMTEST_START 0x80000000
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
-
-/* Default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x80000000
-
-/* Use General purpose timer 1 */
-#define CONFIG_SYS_TIMERBASE GPT2_BASE
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-#define CONFIG_SYS_HZ 1000
-
-/*
- * SDRAM Memory Map
- * Even though we use two CS all the memory
- * is mapped to one contiguous block
- */
-#define CONFIG_NR_DRAM_BANKS 1
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
- GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-
-/* Defines for SDRAM init */
-#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
-#endif
-
-/* Defines for SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_TEXT_BASE 0x40300350
-#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */
-#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SPL_DISPLAY_PRINT
-
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
-#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
-
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
-
-/*
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 80E7FFC0--0x80E80000 should not be used for any
- * other needs.
- */
-#define CONFIG_SYS_TEXT_BASE 0x80E80000
-
-/*
- * BSS and malloc area 64MB into memory to allow enough
- * space for the kernel at the beginning of memory
- */
-#define CONFIG_SPL_BSS_START_ADDR 0x84000000
-#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
-#define CONFIG_SYS_SPL_MALLOC_START 0x84100000
-#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
-#endif /* __CONFIG_H */
+#endif /* __CONFIG_OMAP5_EVM_H */
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
#define CONFIG_OF_LIBFDT
#define CONFIG_LMB
+#define CONFIG_FS_FAT
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+
#define CONFIG_SYS_VSNPRINTF
#define CONFIG_CMD_GPIO
#define CONFIG_SYS_HZ 1000
/* Memory things - we don't really want a memory test */
-#define CONFIG_SYS_LOAD_ADDR 0x10000000
-#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_LOAD_ADDR 0x00000000
+#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
#define CONFIG_PHYS_64BIT
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_HASH
+#define CONFIG_HASH_VERIFY
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+#define CONFIG_CMD_SANDBOX
+
#define CONFIG_BOOTARGS ""
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
+/*
+ * QE UEC ethernet configuration
+ */
+#if defined(CONFIG_KMVECT1)
+#define CONFIG_MV88E6352_SWITCH
+#define CONFIG_KM_MVEXTSW_ADDR 0x10
+
+/* ethernet port connected to simple switch 88e6122 (UEC0) */
+#define CONFIG_UEC_ETH1
+#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
+
+#define CONFIG_FIXED_PHY 0xFFFFFFFF
+#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
+#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
+ {devnum, speed, duplex}
+#define CONFIG_SYS_FIXED_PHY_PORTS \
+ CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
+
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
+#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
+#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
+
+/* ethernet port connected to piggy (UEC2) */
+#define CONFIG_HAS_ETH1
+#define CONFIG_UEC_ETH2
+#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */
+#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12
+#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR 0
+#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
+#endif /* CONFIG_KMVECT1 */
+
#endif /* __CONFIG_H */
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
+/*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_742230
+#define CONFIG_ARM_ERRATA_751472
+
/*
* NS16550 Configuration
*/
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
+/*
+ * Errata configuration
+ */
+#define CONFIG_ARM_ERRATA_743622
+#define CONFIG_ARM_ERRATA_751472
+
/*
* NS16550 Configuration
*/
"bootm ${loadaddr}\0" \
"loaduimage_ubi=mtd default; " \
"ubi part fs; " \
- "ubifsmount root; " \
+ "ubifsmount ubi:root; " \
"ubifsload ${loadaddr} /boot/uImage\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
- * (C) Copyright 2010-2012
+ * (C) Copyright 2010-2013
* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
* Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
*
/*
* High Level Configuration Options
*/
-#ifdef CONFIG_KMSUPX5
+#if defined(CONFIG_KMSUPX5)
#define CONFIG_KM_BOARD_NAME "kmsupx5"
#define CONFIG_HOSTNAME kmsupx5
-#elif defined CONFIG_TUGE1
+#elif defined(CONFIG_TUGE1)
#define CONFIG_KM_BOARD_NAME "tuge1"
#define CONFIG_HOSTNAME tuge1
-#else
-#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */
+#elif defined(CONFIG_TUXX1) /* TUXX1 board (tuxa1/tuda1) specific */
#define CONFIG_KM_BOARD_NAME "tuxx1"
#define CONFIG_HOSTNAME tuxx1
+#elif defined(CONFIG_KMOPTI2)
+#define CONFIG_KM_BOARD_NAME "kmopti2"
+#define CONFIG_HOSTNAME kmopti2
+#else
+#error ("Board not supported")
#endif
#define CONFIG_SYS_TEXT_BASE 0xF0000000
#define CONFIG_SYS_APP1_BASE 0xA0000000 /* PAXG */
#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
-#ifndef CONFIG_KM_DISABLE_APP2
+#if defined(CONFIG_TUXX1) || defined(CONFIG_KMOPTI2)
#define CONFIG_SYS_APP2_BASE 0xB0000000 /* PINC3 */
#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
#endif
/*
* Init Local Bus Memory Controller:
- *
- * Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1 KMSUPX4
- * ---- --- ------- ------ ----- ---------------------------------------
- * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF
- * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused
+ * Device on
+ * Bank Bus Machine PortSz Size TUDA1 TUXA1 TUGE1 KMSUPX4 KMOPTI2
+ * ---- --- ------- ------ ----- ---------------------------------------
+ * 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF PAXE
+ * 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused OPI2(16 bit)
*
*/
OR_GPCM_TRLX_SET | \
OR_GPCM_EHTR_CLEAR | \
OR_GPCM_EAD)
-#ifndef CONFIG_KM_DISABLE_APP2
+#if defined(CONFIG_TUXX1)
/*
* Configuration for C3 on the local bus
*/
MxMR_WLFx_2X)
#endif
+#if defined(CONFIG_KMOPTI2)
+/*
+ * Configuration for C3 on the local bus
+ */
+#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
+#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \
+ BR_PS_16 | \
+ BR_MS_GPCM | \
+ BR_V)
+#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \
+ OR_GPCM_SCY_4 | \
+ OR_GPCM_TRLX_CLEAR | \
+ OR_GPCM_EHTR_CLEAR)
+#endif
+
/*
* MMU Setup
*/
BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#ifdef CONFIG_KM_DISABLE_APP2
+#if defined(CONFIG_TUGE1) || defined(CONFIG_KMSUPX5)
#define CONFIG_SYS_IBAT6L (0)
#define CONFIG_SYS_IBAT6U (0)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
0x600000)
#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_OS_BOOT_KEY 55
#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
#define CONFIG_SPL_BOARD_INIT
"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
" addcon addmisc addmtd;" \
"bootm ${kernel_addr} - ${dtb_addr}\0" \
- "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \
+ "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
"ubifsload ${dtb_addr} ${dtb_fs};\0" \
"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
#define SILENT_CALLBACK
#endif
+#ifdef CONFIG_SPLASHIMAGE_GUARD
+#define SPLASHIMAGE_CALLBACK "splashimage:splashimage,"
+#else
+#define SPLASHIMAGE_CALLBACK
+#endif
+
/*
* This list of callback bindings is static, but may be overridden by defining
* a new association in the ".callbacks" environment variable.
"bootfile:bootfile," \
"loadaddr:loadaddr," \
SILENT_CALLBACK \
+ SPLASHIMAGE_CALLBACK \
"stdin:console,stdout:console,stderr:console," \
CONFIG_ENV_CALLBACK_LIST_STATIC
}
#else
#define U_BOOT_ENV_CALLBACK(name, callback) \
- ll_entry_declare(struct env_clbk_tbl, name, env_clbk, env_clbk) = \
+ ll_entry_declare(struct env_clbk_tbl, name, env_clbk) = \
{#name, callback}
#endif
long simple_strtol(const char *cp,char **endp,unsigned int base);
int strcmp(const char * cs,const char * ct);
unsigned long ustrtoul(const char *cp, char **endp, unsigned int base);
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base);
#if defined(CONFIG_CMD_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
int ext4fs_devread(int sector, int byte_offset, int byte_len, char *buf);
void ext4fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
long int read_allocated_block(struct ext2_inode *inode, int fileblock);
+int ext4fs_probe(block_dev_desc_t *fs_dev_desc,
+ disk_partition_t *fs_partition);
+int ext4_read_file(const char *filename, void *buf, int offset, int len);
#endif
int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
int file_fat_write(const char *filename, void *buffer, unsigned long maxsize);
+int fat_read_file(const char *filename, void *buf, int offset, int len);
+void fat_close(void);
#endif /* _FAT_H_ */
#define FS_TYPE_ANY 0
#define FS_TYPE_FAT 1
#define FS_TYPE_EXT 2
+#define FS_TYPE_SANDBOX 3
/*
* Tell the fs layer which block device an partition to use for future
#ifndef _HASH_H
#define _HASH_H
-#ifdef CONFIG_SHA1SUM_VERIFY
+#if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY)
#define CONFIG_HASH_VERIFY
#endif
*/
#define HASH_MAX_DIGEST_SIZE 32
+enum {
+ HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
+ HASH_FLAG_ENV = 1 << 1, /* Allow env vars */
+};
+
/**
* hash_command: Process a hash command for a particular algorithm
*
* This common function is used to implement specific hash commands.
*
- * @algo_name: Hash algorithm being used
- * @verify: Non-zero to enable verify mode
+ * @algo_name: Hash algorithm being used (lower case!)
+ * @flags: Flags value (HASH_FLAG_...)
* @cmdtp: Pointer to command table entry
* @flag: Some flags normally 0 (see CMD_FLAG_.. above)
* @argc: Number of arguments (arg 0 must be the command text)
* @argv: Arguments
*/
-int hash_command(const char *algo_name, int verify, cmd_tbl_t *cmdtp, int flag,
+int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[]);
#endif
extern void lcd_ctrl_init (void *lcdbase);
extern void lcd_enable (void);
+extern int board_splash_screen_prepare(void);
/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
extern void lcd_setcolreg (ushort regno,
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
+
+/*
+ * There is no use in including this from ASM files, but that happens
+ * anyway, e.g. PPC kgdb.S includes command.h which incluse us.
+ * So just don't define anything when included from ASM.
+ */
+
+#if !defined(__ASSEMBLY__)
+
+/**
+ * A linker list is constructed by grouping together linker input
+ * sections, each containning one entry of the list. Each input section
+ * contains a constant initialized variable which holds the entry's
+ * content. Linker list input sections are constructed from the list
+ * and entry names, plus a prefix which allows grouping all lists
+ * together. Assuming _list and _entry are the list and entry names,
+ * then the corresponding input section name is
+ *
+ * _u_boot_list + _2_ + @_list + _2_ + @_entry
+ *
+ * and the C variable name is
+ *
+ * .u_boot_list_ + 2_ + @_list + _2_ + @_entry
+ *
+ * This ensures uniqueness for both input section and C variable name.
+ *
+ * Note that the names differ only in the first character, "." for the
+ * setion and "_" for the variable, so that the linker cannot confuse
+ * section and symbol names. From now on, both names will be referred
+ * to as
+ *
+ * %u_boot_list_ + 2_ + @_list + _2_ + @_entry
+ *
+ * Entry variables need never be referred to directly.
+ *
+ * The naming scheme for input sections allows grouping all linker lists
+ * into a single linker output section and grouping all entries for a
+ * single list.
+ *
+ * Note the two '_2_' constant components in the names: their presence
+ * allows putting a start and end symbols around a list, by mapping
+ * these symbols to sections names with components "1" (before) and
+ * "3" (after) instead of "2" (within).
+ * Start and end symbols for a list can generally be defined as
+ *
+ * %u_boot_list_2_ + @_list + _1_...
+ * %u_boot_list_2_ + @_list + _3_...
+ *
+ * Start and end symbols for the whole of the linker lists area can be
+ * defined as
+ *
+ * %u_boot_list_1_...
+ * %u_boot_list_3_...
+ *
+ * Here is an example of the sorted sections which result from a list
+ * "array" made up of three entries : "first", "second" and "third",
+ * iterated at least once.
+ *
+ * .u_boot_list_2_array_1
+ * .u_boot_list_2_array_2_first
+ * .u_boot_list_2_array_2_second
+ * .u_boot_list_2_array_2_third
+ * .u_boot_list_2_array_3
+ *
+ * If lists must be divided into sublists (e.g. for iterating only on
+ * part of a list), one can simply give the list a name of the form
+ * 'outer_2_inner', where 'outer' is the global list name and 'inner'
+ * is the sub-list name. Iterators for the whole list should use the
+ * global list name ("outer"); iterators for only a sub-list should use
+ * the full sub-list name ("outer_2_inner").
+ *
+ * Here is an example of the sections generated from a global list
+ * named "drivers", two sub-lists named "i2c" and "pci", and iterators
+ * defined for the whole list and each sub-list:
+ *
+ * %u_boot_list_2_drivers_1
+ * %u_boot_list_2_drivers_2_i2c_1
+ * %u_boot_list_2_drivers_2_i2c_2_first
+ * %u_boot_list_2_drivers_2_i2c_2_first
+ * %u_boot_list_2_drivers_2_i2c_2_second
+ * %u_boot_list_2_drivers_2_i2c_2_third
+ * %u_boot_list_2_drivers_2_i2c_3
+ * %u_boot_list_2_drivers_2_pci_1
+ * %u_boot_list_2_drivers_2_pci_2_first
+ * %u_boot_list_2_drivers_2_pci_2_second
+ * %u_boot_list_2_drivers_2_pci_2_third
+ * %u_boot_list_2_drivers_2_pci_3
+ * %u_boot_list_2_drivers_3
+ */
+
#ifndef __LINKER_LISTS_H__
#define __LINKER_LISTS_H__
* ll_entry_declare() - Declare linker-generated array entry
* @_type: Data type of the entry
* @_name: Name of the entry
- * @_section_u: Subsection of u_boot_list in which this entry is placed
- * (with underscores instead of dots, for name concatenation)
- * @_section_d: Subsection of u_boot_list in which this entry is placed
- * (with dots, for section concatenation)
+ * @_list: name of the list. Should contain only characters allowed
+ * in a C variable name!
*
* This macro declares a variable that is placed into a linker-generated
* array. This is a basic building block for more advanced use of linker-
* generated arrays. The user is expected to build their own macro wrapper
* around this one.
*
- * A variable declared using this macro must be compile-time initialized
- * and is as such placed into subsection of special section, .u_boot_list.
- * The subsection is specified by the _section_[u,d] parameter, see below.
- * The base name of the variable is _name, yet the actual variable is
- * declared as concatenation of
- *
- * %_u_boot_list_ + @_section_u + _ + @_name
- *
- * which ensures name uniqueness. This variable shall never be refered
- * directly though.
+ * A variable declared using this macro must be compile-time initialized.
*
* Special precaution must be made when using this macro:
- * 1) The _type must not contain the "static" keyword, otherwise the entry
- * is not generated.
*
- * 2) The @_section_u and @_section_d variables must match, the only difference
- * is that in @_section_u is every dot "." character present in @_section_d
- * replaced by a single underscore "_" character in @_section_u. The actual
- * purpose of these parameters is to select proper subsection in the global
- * .u_boot_list section.
+ * 1) The _type must not contain the "static" keyword, otherwise the
+ * entry is generated and can be iterated but is listed in the map
+ * file and cannot be retrieved by name.
*
- * 3) In case a section is declared that contains some array elements AND a
- * subsection of this section is declared and contains some elements, it is
- * imperative that the elements are of the same type.
+ * 2) In case a section is declared that contains some array elements AND
+ * a subsection of this section is declared and contains some elements,
+ * it is imperative that the elements are of the same type.
*
* 4) In case an outer section is declared that contains some array elements
- * AND am inner subsection of this section is declared and contains some
+ * AND an inner subsection of this section is declared and contains some
* elements, then when traversing the outer section, even the elements of
* the inner sections are present in the array.
*
* .y = 4,
* };
*/
-#define ll_entry_declare(_type, _name, _section_u, _section_d) \
- _type _u_boot_list_##_section_u##_##_name __attribute__(( \
- unused, aligned(4), \
- section(".u_boot_list."#_section_d"."#_name)))
+#define ll_entry_declare(_type, _name, _list) \
+ _type _u_boot_list_2_##_list##_2_##_name __aligned(4) \
+ __attribute__((unused, \
+ section(".u_boot_list_2_"#_list"_2_"#_name)))
+
+/**
+ * We need a 0-byte-size type for iterator symbols, and the compiler
+ * does not allow defining objects of C type 'void'. Using an empty
+ * struct is allowed by the compiler, but causes gcc versions 4.4 and
+ * below to complain about aliasing. Therefore we use the next best
+ * thing: zero-sized arrays, which are both 0-byte-size and exempt from
+ * aliasing warnings.
+ */
/**
* ll_entry_start() - Point to first entry of linker-generated array
* @_type: Data type of the entry
- * @_section_u: Subsection of u_boot_list in which this entry is placed
- * (with underscores instead of dots)
+ * @_list: Name of the list in which this entry is placed
*
* This function returns (_type *) pointer to the very first entry of a
* linker-generated array placed into subsection of .u_boot_list section
- * specified by _section_u argument.
+ * specified by _list argument.
+ *
+ * Since this macro defines an array start symbol, its leftmost index
+ * must be 2 and its rightmost index must be 1.
*
* Example:
* struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
*/
-#define ll_entry_start(_type, _section_u) \
- ({ \
- extern _type _u_boot_list_##_section_u##__start; \
- _type *_ll_result = &_u_boot_list_##_section_u##__start;\
- _ll_result; \
- })
+#define ll_entry_start(_type, _list) \
+({ \
+ static char start[0] __aligned(4) __attribute__((unused, \
+ section(".u_boot_list_2_"#_list"_1"))); \
+ (_type *)&start; \
+})
/**
- * ll_entry_count() - Return the number of elements in linker-generated array
+ * ll_entry_end() - Point after last entry of linker-generated array
* @_type: Data type of the entry
- * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * @_list: Name of the list in which this entry is placed
* (with underscores instead of dots)
*
+ * This function returns (_type *) pointer after the very last entry of
+ * a linker-generated array placed into subsection of .u_boot_list
+ * section specified by _list argument.
+ *
+ * Since this macro defines an array end symbol, its leftmost index
+ * must be 2 and its rightmost index must be 3.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_entry_end(struct my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_end(_type, _list) \
+({ \
+ static char end[0] __aligned(4) __attribute__((unused, \
+ section(".u_boot_list_2_"#_list"_3"))); \
+ (_type *)&end; \
+})
+/**
+ * ll_entry_count() - Return the number of elements in linker-generated array
+ * @_type: Data type of the entry
+ * @_list: Name of the list of which the number of elements is computed
+ *
* This function returns the number of elements of a linker-generated array
- * placed into subsection of .u_boot_list section specified by _section_u
+ * placed into subsection of .u_boot_list section specified by _list
* argument. The result is of an unsigned int type.
*
* Example:
* for (i = 0; i < count; i++, msc++)
* printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y);
*/
-#define ll_entry_count(_type, _section_u) \
+#define ll_entry_count(_type, _list) \
({ \
- extern _type _u_boot_list_##_section_u##__start; \
- extern _type _u_boot_list_##_section_u##__end; \
- unsigned int _ll_result = \
- &_u_boot_list_##_section_u##__end - \
- &_u_boot_list_##_section_u##__start; \
+ _type *start = ll_entry_start(_type, _list); \
+ _type *end = ll_entry_end(_type, _list); \
+ unsigned int _ll_result = end - start; \
_ll_result; \
})
-
/**
* ll_entry_get() - Retrieve entry from linker-generated array by name
* @_type: Data type of the entry
* @_name: Name of the entry
- * @_section_u: Subsection of u_boot_list in which this entry is placed
- * (with underscores instead of dots)
+ * @_list: Name of the list in which this entry is placed
*
* This function returns a pointer to a particular entry in LG-array
* identified by the subsection of u_boot_list where the entry resides
* ...
* struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub);
*/
-#define ll_entry_get(_type, _name, _section_u) \
+#define ll_entry_get(_type, _name, _list) \
({ \
- extern _type _u_boot_list_##_section_u##_##_name; \
- _type *_ll_result = &_u_boot_list_##_section_u##_##_name;\
+ extern _type _u_boot_list_2_##_list##_2_##_name; \
+ _type *_ll_result = \
+ &_u_boot_list_2_##_list##_2_##_name; \
_ll_result; \
})
+/**
+ * ll_start() - Point to first entry of first linker-generated array
+ * @_type: Data type of the entry
+ *
+ * This function returns (_type *) pointer to the very first entry of
+ * the very first linker-generated array.
+ *
+ * Since this macro defines the start of the linker-generated arrays,
+ * its leftmost index must be 1.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_start(struct my_sub_cmd);
+ */
+#define ll_start(_type) \
+({ \
+ static char start[0] __aligned(4) __attribute__((unused, \
+ section(".u_boot_list_1"))); \
+ (_type *)&start; \
+})
+
+/**
+ * ll_entry_end() - Point after last entry of last linker-generated array
+ * @_type: Data type of the entry
+ *
+ * This function returns (_type *) pointer after the very last entry of
+ * the very last linker-generated array.
+ *
+ * Since this macro defines the end of the linker-generated arrays,
+ * its leftmost index must be 3.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_end(struct my_sub_cmd);
+ */
+#define ll_end(_type) \
+({ \
+ static char end[0] __aligned(4) __attribute__((unused, \
+ section(".u_boot_list_3"))); \
+ (_type *)&end; \
+})
+
+#endif /* __ASSEMBLY__ */
+
#endif /* __LINKER_LISTS_H__ */
extern ulong mem_malloc_brk;
void mem_malloc_init(ulong start, ulong size);
-void malloc_bin_reloc(void);
#ifdef __cplusplus
}; /* end of extern "C" */
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
int (*getcd)(struct mmc *mmc);
+ int (*getwp)(struct mmc *mmc);
uint b_max;
};
int board_mmc_getcd(struct mmc *mmc);
int mmc_switch_part(int dev_num, unsigned int part_num);
int mmc_getcd(struct mmc *mmc);
+int mmc_getwp(struct mmc *mmc);
void spl_mmc_load(void) __noreturn;
#ifdef CONFIG_GENERIC_MMC
*/
ssize_t os_read(int fd, void *buf, size_t count);
+/**
+ * Access to the OS read() system call with non-blocking access
+ *
+ * \param fd File descriptor as returned by os_open()
+ * \param buf Buffer to place data
+ * \param count Number of bytes to read
+ * \return number of bytes read, or -1 on error
+ */
+ssize_t os_read_no_block(int fd, void *buf, size_t count);
+
/**
* Access to the OS write() system call
*
*/
int os_parse_args(struct sandbox_state *state, int argc, char *argv[]);
+/*
+ * Types of directory entry that we support. See also os_dirent_typename in
+ * the C file.
+ */
+enum os_dirent_t {
+ OS_FILET_REG, /* Regular file */
+ OS_FILET_LNK, /* Symbolic link */
+ OS_FILET_DIR, /* Directory */
+ OS_FILET_UNKNOWN, /* Something else */
+
+ OS_FILET_COUNT,
+};
+
+/** A directory entry node, containing information about a single dirent */
+struct os_dirent_node {
+ struct os_dirent_node *next; /* Pointer to next node, or NULL */
+ ulong size; /* Size of file in bytes */
+ enum os_dirent_t type; /* Type of entry */
+ char name[0]; /* Name of entry */
+};
+
+/**
+ * Get a directionry listing
+ *
+ * This allocates and returns a linked list containing the directory listing.
+ *
+ * @param dirname Directory to examine
+ * @param headp Returns pointer to head of linked list, or NULL if none
+ * @return 0 if ok, -ve on error
+ */
+int os_dirent_ls(const char *dirname, struct os_dirent_node **headp);
+
+/**
+ * Get the name of a directory entry type
+ *
+ * @param type Type to cehck
+ * @return string containing the name of that type, or "???" if none/invalid
+ */
+const char *os_dirent_get_typename(enum os_dirent_t type);
+
+/**
+ * Get the size of a file
+ *
+ * @param fname Filename to check
+ * @return size of file, or -1 if an error ocurred
+ */
+ssize_t os_get_filesize(const char *fname);
+
#endif
--- /dev/null
+/*
+ * Copyright (c) 2012, Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __SANDBOX_FS__
+#define __SANDBOX_FS__
+
+int sandbox_fs_set_blk_dev(block_dev_desc_t *rbdd, disk_partition_t *info);
+
+long sandbox_fs_read_at(const char *filename, unsigned long pos,
+ void *buffer, unsigned long maxsize);
+
+void sandbox_fs_close(void);
+int sandbox_fs_ls(const char *dirname);
+int fs_read_sandbox(const char *filename, void *buf, int offset, int len);
+
+#endif
/* NAND SPL functions */
void spl_nand_load_image(void);
+/* OneNAND SPL functions */
+void spl_onenand_load_image(void);
+
/* NOR SPL functions */
void spl_nor_load_image(void);
uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint);
+/**
+ * crc32_wd_buf - Perform CRC32 on a buffer and return result in buffer
+ *
+ * @input: Input buffer
+ * @ilen: Input buffer length
+ * @output: Place to put checksum result (4 bytes)
+ * @chunk_sz: Trigger watchdog after processing this many bytes
+ */
+void crc32_wd_buf(const unsigned char *input, uint ilen,
+ unsigned char *output, uint chunk_sz);
+
#endif /* _UBOOT_CRC_H */
return crc;
}
+
+void crc32_wd_buf(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz)
+{
+ uint32_t crc;
+
+ crc = crc32_wd(0, input, ilen, chunk_sz);
+ memcpy(output, &crc, sizeof(crc));
+}
*/
#define MAX_LINE_LENGTH_BYTES (64)
#define DEFAULT_LINE_LENGTH_BYTES (16)
-int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen)
+int print_buffer(ulong addr, const void *data, uint width, uint count,
+ uint linelen)
{
/* linebuf as a union causes proper alignment */
union linebuf {
return result;
}
+unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base)
+{
+ unsigned long long result = simple_strtoull(cp, endp, base);
+ switch (**endp) {
+ case 'G':
+ result *= 1024;
+ /* fall through */
+ case 'M':
+ result *= 1024;
+ /* fall through */
+ case 'K':
+ case 'k':
+ result *= 1024;
+ if ((*endp)[1] == 'i') {
+ if ((*endp)[2] == 'B')
+ (*endp) += 3;
+ else
+ (*endp) += 2;
+ }
+ }
+ return result;
+}
+
unsigned long long simple_strtoull(const char *cp, char **endp,
unsigned int base)
{
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $@
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ *(SORT(.u_boot_list*));
}
. = ALIGN(4);
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $@
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
+$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
-ansi -D__ASSEMBLY__ -P - <$< >$@
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ *(SORT(.u_boot_list*));
}
. = ALIGN(4);
. = ALIGN(4);
.u_boot_list : {
- #include <u-boot.lst>
+ *(SORT(.u_boot_list*));
}
. = ALIGN(4);
case NETLOOP_SUCCESS:
net_cleanup_loop();
if (NetBootFileXferSize > 0) {
- char buf[20];
printf("Bytes transferred = %ld (%lx hex)\n",
NetBootFileXferSize,
NetBootFileXferSize);
- sprintf(buf, "%lX", NetBootFileXferSize);
- setenv("filesize", buf);
-
- sprintf(buf, "%lX", (unsigned long)load_addr);
- setenv("fileaddr", buf);
+ setenv_hex("filesize", NetBootFileXferSize);
+ setenv_hex("fileaddr", load_addr);
}
if (protocol != NETCONS)
eth_halt();
u-boot-spl.bin
u-boot-spl.lds
u-boot-spl.map
-u-boot.lst
LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-spl.lds
endif
ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot.lds
+ LDSCRIPT := $(TOPDIR)/arch/$(ARCH)/cpu/u-boot-spl.lds
endif
ifeq ($(wildcard $(LDSCRIPT)),)
$(error could not find linker script)
$(LIBS): depend
$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
-# The following line expands into whole rule which generates u-boot.lst,
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(obj)u-boot.lst, $(LIBS)))
-$(obj)u-boot-spl.lds: $(LDSCRIPT) $(obj)u-boot.lst depend
+$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
depend: $(obj).depend
-# Configuration file for fw_(printenv/saveenv) utility.
+# Configuration file for fw_(printenv/setenv) utility.
# Up to two entries are valid, in this case the redundant
# environment sector is assumed present.
# Notice, that the "Number of sectors" is ignored on NOR and SPI-dataflash.
projects / karo-tx-uboot.git / commitdiff