ARM: Introduce erratum workaround for 798870

Add workaround for Cortex-A15 ARM erratum 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Implementations for SoC families such as Exynos, OMAP5/DRA7 etc
will be widely different.

Every SoC has slightly different manner of setting up access to L2ACLR
and similar registers since the Secure Monitor handling of Secure
Monitor Call(smc) is diverse. Hence an weak function is introduced
which may be overriden to implement SoC specific accessor implementation.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/README b/README
index 0ea483a02c265f15abd9bbd6abfb4bb1dd083374..3c23d164bd84e07aba2d3b6cd5a8d4383772619d 100644 (file)
--- a/README
+++ b/README
@@ -690,6 +690,130 @@ The following options need to be configured:
                exists, unlike the similar options in the Linux kernel. Do not
                set these options unless they apply!
 
+               NOTE: The following can be machine specific errata. These
+               do have ability to provide rudimentary version and machine
+               specific checks, but expect no product checks.
+               CONFIG_ARM_ERRATA_798870
+
+- Tegra SoC options:
+               CONFIG_TEGRA_SUPPORT_NON_SECURE
+
+               Support executing U-Boot in non-secure (NS) mode. Certain
+               impossible actions will be skipped if the CPU is in NS mode,
+               such as ARM architectural timer initialization.
+
+- Driver Model
+               Driver model is a new framework for devices in U-Boot
+               introduced in early 2014. U-Boot is being progressively
+               moved over to this. It offers a consistent device structure,
+               supports grouping devices into classes and has built-in
+               handling of platform data and device tree.
+
+               To enable transition to driver model in a relatively
+               painful fashion, each subsystem can be independently
+               switched between the legacy/ad-hoc approach and the new
+               driver model using the options below. Also, many uclass
+               interfaces include compatibility features which may be
+               removed once the conversion of that subsystem is complete.
+               As a result, the API provided by the subsystem may in fact
+               not change with driver model.
+
+               See doc/driver-model/README.txt for more information.
+
+               CONFIG_DM
+
+               Enable driver model. This brings in the core support,
+               including scanning of platform data on start-up. If
+               CONFIG_OF_CONTROL is enabled, the device tree will be
+               scanned also when available.
+
+               CONFIG_CMD_DM
+
+               Enable driver model test commands. These allow you to print
+               out the driver model tree and the uclasses.
+
+               CONFIG_DM_DEMO
+
+               Enable some demo devices and the 'demo' command. These are
+               really only useful for playing around while trying to
+               understand driver model in sandbox.
+
+               CONFIG_SPL_DM
+
+               Enable driver model in SPL. You will need to provide a
+               suitable malloc() implementation. If you are not using the
+               full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START,
+               consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you
+               must provide CONFIG_SYS_MALLOC_F_LEN to set the size.
+               In most cases driver model will only allocate a few uclasses
+               and devices in SPL, so 1KB should be enable. See
+               CONFIG_SYS_MALLOC_F_LEN for more details on how to enable
+               it.
+
+               CONFIG_DM_SERIAL
+
+               Enable driver model for serial. This replaces
+               drivers/serial/serial.c with the serial uclass, which
+               implements serial_putc() etc. The uclass interface is
+               defined in include/serial.h.
+
+               CONFIG_DM_GPIO
+
+               Enable driver model for GPIO access. The standard GPIO
+               interface (gpio_get_value(), etc.) is then implemented by
+               the GPIO uclass. Drivers provide methods to query the
+               particular GPIOs that they provide. The uclass interface
+               is defined in include/asm-generic/gpio.h.
+
+               CONFIG_DM_SPI
+
+               Enable driver model for SPI. The SPI slave interface
+               (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
+               the SPI uclass. Drivers provide methods to access the SPI
+               buses that they control. The uclass interface is defined in
+               include/spi.h. The existing spi_slave structure is attached
+               as 'parent data' to every slave on each bus. Slaves
+               typically use driver-private data instead of extending the
+               spi_slave structure.
+
+               CONFIG_DM_SPI_FLASH
+
+               Enable driver model for SPI flash. This SPI flash interface
+               (spi_flash_probe(), spi_flash_write(), etc.) is then
+               implemented by the SPI flash uclass. There is one standard
+               SPI flash driver which knows how to probe most chips
+               supported by U-Boot. The uclass interface is defined in
+               include/spi_flash.h, but is currently fully compatible
+               with the old interface to avoid confusion and duplication
+               during the transition parent. SPI and SPI flash must be
+               enabled together (it is not possible to use driver model
+               for one and not the other).
+
+               CONFIG_DM_CROS_EC
+
+               Enable driver model for the Chrome OS EC interface. This
+               allows the cros_ec SPI driver to operate with CONFIG_DM_SPI
+               but otherwise makes few changes. Since cros_ec also supports
+               I2C and LPC (which don't support driver model yet), a full
+               conversion is not yet possible.
+
+
+               ** Code size options: The following options are enabled by
+               default except in SPL. Enable them explicitly to get these
+               features in SPL.
+
+               CONFIG_DM_WARN
+
+               Enable the dm_warn() function. This can use up quite a bit
+               of space for its strings.
+
+               CONFIG_DM_STDIO
+
+               Enable registering a serial device with the stdio library.
+
+               CONFIG_DM_DEVICE_REMOVE
+
+               Enable removing of devices.
 
 - Linux Kernel Interface:
                CONFIG_CLOCKS_IN_MHZ

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 50d3495a0e48306b1e8f276bf0792f3a6d1de05e..0857f6c518947b383199c84b36981eef6a704901 100644 (file)
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -9,7 +9,7 @@ extra-y := start.o
 
 obj-y  += cache_v7.o
 
-obj-y  += cpu.o
+obj-y  += cpu.o cp15.o
 obj-y  += syslib.o
 
 ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_SOC_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)