Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging
authorWolfgang Denk <wd@denx.de>
Sat, 1 Sep 2012 22:44:09 +0000 (00:44 +0200)
committerWolfgang Denk <wd@denx.de>
Sat, 1 Sep 2012 22:44:09 +0000 (00:44 +0200)
* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
  tx25: Use generic gpio_* calls
  config: Always use GNU ld
  tools: add kwboot binary to .gitignore file
  fdt: Include arch specific gpio.h instead of asm-generic/gpio.h
  serial: CONSOLE macro is not used

Conflicts:
board/karo/tx25/tx25.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
595 files changed:
.gitignore
CREDITS
MAINTAINERS
MAKEALL
Makefile
README
arch/arm/cpu/arm1136/mx35/generic.c
arch/arm/cpu/arm1136/mx35/iomux.c
arch/arm/cpu/arm1176/bcm2835/Makefile [new file with mode: 0644]
arch/arm/cpu/arm1176/bcm2835/config.mk [new file with mode: 0644]
arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S [new file with mode: 0644]
arch/arm/cpu/arm1176/bcm2835/reset.c [new file with mode: 0644]
arch/arm/cpu/arm1176/bcm2835/timer.c [new file with mode: 0644]
arch/arm/cpu/arm1176/cpu.c
arch/arm/cpu/arm720t/cpu.c
arch/arm/cpu/arm720t/interrupts.c
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm720t/tegra20/Makefile [new file with mode: 0644]
arch/arm/cpu/arm720t/tegra20/board.h [new file with mode: 0644]
arch/arm/cpu/arm720t/tegra20/config.mk [moved from board/isee/igep0030/config.mk with 66% similarity]
arch/arm/cpu/arm720t/tegra20/cpu.c [moved from arch/arm/cpu/armv7/tegra2/ap20.c with 63% similarity]
arch/arm/cpu/arm720t/tegra20/cpu.h [new file with mode: 0644]
arch/arm/cpu/arm720t/tegra20/spl.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/at91/Makefile
arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/at91/clock.c
arch/arm/cpu/arm926ejs/at91/cpu.c
arch/arm/cpu/arm926ejs/davinci/Makefile
arch/arm/cpu/arm926ejs/davinci/cpu.c
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
arch/arm/cpu/arm926ejs/davinci/psc.c
arch/arm/cpu/arm926ejs/davinci/reset.S [deleted file]
arch/arm/cpu/arm926ejs/davinci/reset.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/davinci/spl.c
arch/arm/cpu/arm926ejs/mx25/generic.c
arch/arm/cpu/arm926ejs/mx27/generic.c
arch/arm/cpu/arm926ejs/mxs/Makefile [moved from arch/arm/cpu/arm926ejs/mx28/Makefile with 97% similarity]
arch/arm/cpu/arm926ejs/mxs/clock.c [moved from arch/arm/cpu/arm926ejs/mx28/clock.c with 89% similarity]
arch/arm/cpu/arm926ejs/mxs/iomux.c [moved from arch/arm/cpu/arm926ejs/mx28/iomux.c with 94% similarity]
arch/arm/cpu/arm926ejs/mxs/mxs.c [moved from arch/arm/cpu/arm926ejs/mx28/mx28.c with 69% similarity]
arch/arm/cpu/arm926ejs/mxs/mxs_init.h [moved from arch/arm/cpu/arm926ejs/mx28/mx28_init.h with 81% similarity]
arch/arm/cpu/arm926ejs/mxs/spl_boot.c [moved from arch/arm/cpu/arm926ejs/mx28/spl_boot.c with 85% similarity]
arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c [moved from arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c with 91% similarity]
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c [moved from arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c with 83% similarity]
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c [moved from arch/arm/cpu/arm926ejs/mx28/spl_power_init.c with 81% similarity]
arch/arm/cpu/arm926ejs/mxs/start.S [moved from arch/arm/cpu/arm926ejs/mx28/start.S with 82% similarity]
arch/arm/cpu/arm926ejs/mxs/timer.c [moved from arch/arm/cpu/arm926ejs/mx28/timer.c with 93% similarity]
arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd [moved from board/denx/m28evk/u-boot.bd with 100% similarity]
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds [moved from arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds with 97% similarity]
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/cpu/armv7/config.mk
arch/arm/cpu/armv7/cpu.c
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/exynos/power.c
arch/arm/cpu/armv7/exynos/soc.c
arch/arm/cpu/armv7/exynos/system.c
arch/arm/cpu/armv7/highbank/Makefile
arch/arm/cpu/armv7/highbank/bootcount.c [deleted file]
arch/arm/cpu/armv7/imx-common/Makefile
arch/arm/cpu/armv7/imx-common/cmd_bmode.c [new file with mode: 0644]
arch/arm/cpu/armv7/imx-common/cpu.c
arch/arm/cpu/armv7/imx-common/timer.c
arch/arm/cpu/armv7/lowlevel_init.S [moved from arch/sh/include/asm/clk.h with 57% similarity]
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/cpu/armv7/mx5/soc.c
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
arch/arm/cpu/armv7/s5p-common/pwm.c
arch/arm/cpu/armv7/s5p-common/timer.c
arch/arm/cpu/armv7/start.S
arch/arm/cpu/armv7/tegra20/Makefile [moved from arch/arm/cpu/armv7/tegra2/Makefile with 69% similarity]
arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c [moved from arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c with 94% similarity]
arch/arm/cpu/armv7/tegra20/config.mk [moved from arch/arm/cpu/armv7/tegra2/config.mk with 74% similarity]
arch/arm/cpu/armv7/tegra20/usb.c [moved from arch/arm/cpu/armv7/tegra2/usb.c with 99% similarity]
arch/arm/cpu/armv7/u8500/Makefile
arch/arm/cpu/armv7/u8500/clock.c
arch/arm/cpu/armv7/u8500/cpu.c [new file with mode: 0644]
arch/arm/cpu/armv7/u8500/prcmu.c [moved from board/st-ericsson/u8500/prcmu.c with 58% similarity]
arch/arm/cpu/ixp/cpu.c
arch/arm/cpu/tegra20-common/Makefile [new file with mode: 0644]
arch/arm/cpu/tegra20-common/ap20.c [new file with mode: 0644]
arch/arm/cpu/tegra20-common/board.c [moved from arch/arm/cpu/armv7/tegra2/board.c with 79% similarity]
arch/arm/cpu/tegra20-common/clock.c [moved from arch/arm/cpu/armv7/tegra2/clock.c with 99% similarity]
arch/arm/cpu/tegra20-common/crypto.c [moved from arch/arm/cpu/armv7/tegra2/crypto.c with 100% similarity]
arch/arm/cpu/tegra20-common/crypto.h [moved from arch/arm/cpu/armv7/tegra2/crypto.h with 100% similarity]
arch/arm/cpu/tegra20-common/emc.c [moved from arch/arm/cpu/armv7/tegra2/emc.c with 99% similarity]
arch/arm/cpu/tegra20-common/funcmux.c [moved from arch/arm/cpu/armv7/tegra2/funcmux.c with 99% similarity]
arch/arm/cpu/tegra20-common/lowlevel_init.S [moved from arch/arm/cpu/armv7/tegra2/lowlevel_init.S with 100% similarity]
arch/arm/cpu/tegra20-common/pinmux.c [moved from arch/arm/cpu/armv7/tegra2/pinmux.c with 99% similarity]
arch/arm/cpu/tegra20-common/pmu.c [moved from arch/arm/cpu/armv7/tegra2/pmu.c with 98% similarity]
arch/arm/cpu/tegra20-common/sys_info.c [moved from arch/arm/cpu/armv7/tegra2/sys_info.c with 98% similarity]
arch/arm/cpu/tegra20-common/timer.c [moved from arch/arm/cpu/armv7/tegra2/timer.c with 98% similarity]
arch/arm/cpu/tegra20-common/warmboot.c [moved from arch/arm/cpu/armv7/tegra2/warmboot.c with 95% similarity]
arch/arm/cpu/tegra20-common/warmboot_avp.c [moved from arch/arm/cpu/armv7/tegra2/warmboot_avp.c with 98% similarity]
arch/arm/cpu/tegra20-common/warmboot_avp.h [moved from arch/arm/cpu/armv7/tegra2/warmboot_avp.h with 100% similarity]
arch/arm/include/asm/arch-am33xx/common_def.h [deleted file]
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/ddr_defs.h
arch/arm/include/asm/arch-am33xx/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/hardware.h
arch/arm/include/asm/arch-am33xx/mmc_host_def.h
arch/arm/include/asm/arch-am33xx/omap.h
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-at91/at91sam9_matrix.h
arch/arm/include/asm/arch-at91/at91sam9x5.h [new file with mode: 0644]
arch/arm/include/asm/arch-at91/at91sam9x5_matrix.h [new file with mode: 0644]
arch/arm/include/asm/arch-at91/hardware.h
arch/arm/include/asm/arch-bcm2835/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-bcm2835/timer.h [new file with mode: 0644]
arch/arm/include/asm/arch-bcm2835/wdog.h [new file with mode: 0644]
arch/arm/include/asm/arch-davinci/da8xx-usb.h [moved from drivers/usb/musb/da8xx.h with 96% similarity]
arch/arm/include/asm/arch-davinci/hardware.h
arch/arm/include/asm/arch-davinci/pinmux_defs.h
arch/arm/include/asm/arch-exynos/clk.h
arch/arm/include/asm/arch-exynos/clock.h
arch/arm/include/asm/arch-exynos/cpu.h
arch/arm/include/asm/arch-exynos/dmc.h
arch/arm/include/asm/arch-exynos/dp.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/dp_info.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/fb.h
arch/arm/include/asm/arch-exynos/gpio.h
arch/arm/include/asm/arch-exynos/power.h
arch/arm/include/asm/arch-exynos/pwm_backlight.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-imx/imx-regs.h
arch/arm/include/asm/arch-mx25/gpio.h
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx27/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx27/imx-regs.h
arch/arm/include/asm/arch-mx27/regs-rtc.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx31/gpio.h
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/clock.h
arch/arm/include/asm/arch-mx35/crm_regs.h
arch/arm/include/asm/arch-mx35/gpio.h
arch/arm/include/asm/arch-mx35/imx-regs.h
arch/arm/include/asm/arch-mx35/mx35_pins.h
arch/arm/include/asm/arch-mx35/sys_proto.h
arch/arm/include/asm/arch-mx5/clock.h
arch/arm/include/asm/arch-mx5/gpio.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx5/iomux-mx51.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx6/gpio.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/iomux.h [new file with mode: 0644]
arch/arm/include/asm/arch-mxs/clock.h [moved from arch/arm/include/asm/arch-mx28/clock.h with 100% similarity]
arch/arm/include/asm/arch-mxs/dma.h [moved from arch/arm/include/asm/arch-mx28/dma.h with 98% similarity]
arch/arm/include/asm/arch-mxs/gpio.h [moved from arch/arm/include/asm/arch-mx28/gpio.h with 100% similarity]
arch/arm/include/asm/arch-mxs/imx-regs.h [moved from arch/arm/include/asm/arch-mx28/imx-regs.h with 97% similarity]
arch/arm/include/asm/arch-mxs/iomux-mx28.h [moved from arch/arm/include/asm/arch-mx28/iomux-mx28.h with 100% similarity]
arch/arm/include/asm/arch-mxs/iomux.h [moved from arch/arm/include/asm/arch-mx28/iomux.h with 100% similarity]
arch/arm/include/asm/arch-mxs/regs-apbh.h [moved from arch/arm/include/asm/arch-mx28/regs-apbh.h with 77% similarity]
arch/arm/include/asm/arch-mxs/regs-base.h [moved from arch/arm/include/asm/arch-mx28/regs-base.h with 100% similarity]
arch/arm/include/asm/arch-mxs/regs-bch.h [moved from arch/arm/include/asm/arch-mx28/regs-bch.h with 92% similarity]
arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h [moved from arch/arm/include/asm/arch-mx28/regs-clkctrl.h with 88% similarity]
arch/arm/include/asm/arch-mxs/regs-common.h [moved from arch/arm/include/asm/arch-mx28/regs-common.h with 78% similarity]
arch/arm/include/asm/arch-mxs/regs-digctl.h [moved from arch/arm/include/asm/arch-mx28/regs-digctl.h with 77% similarity]
arch/arm/include/asm/arch-mxs/regs-gpmi.h [moved from arch/arm/include/asm/arch-mx28/regs-gpmi.h with 95% similarity]
arch/arm/include/asm/arch-mxs/regs-i2c.h [moved from arch/arm/include/asm/arch-mx28/regs-i2c.h with 94% similarity]
arch/arm/include/asm/arch-mxs/regs-lcdif.h [moved from arch/arm/include/asm/arch-mx28/regs-lcdif.h with 84% similarity]
arch/arm/include/asm/arch-mxs/regs-lradc.h [moved from arch/arm/include/asm/arch-mx28/regs-lradc.h with 96% similarity]
arch/arm/include/asm/arch-mxs/regs-ocotp.h [moved from arch/arm/include/asm/arch-mx28/regs-ocotp.h with 71% similarity]
arch/arm/include/asm/arch-mxs/regs-pinctrl.h [moved from arch/arm/include/asm/arch-mx28/regs-pinctrl.h with 93% similarity]
arch/arm/include/asm/arch-mxs/regs-power.h [moved from arch/arm/include/asm/arch-mx28/regs-power.h with 97% similarity]
arch/arm/include/asm/arch-mxs/regs-rtc.h [moved from arch/arm/include/asm/arch-mx28/regs-rtc.h with 91% similarity]
arch/arm/include/asm/arch-mxs/regs-ssp.h [moved from arch/arm/include/asm/arch-mx28/regs-ssp.h with 95% similarity]
arch/arm/include/asm/arch-mxs/regs-timrot.h [moved from arch/arm/include/asm/arch-mx28/regs-timrot.h with 90% similarity]
arch/arm/include/asm/arch-mxs/regs-usb.h [moved from arch/arm/include/asm/arch-mx28/regs-usb.h with 99% similarity]
arch/arm/include/asm/arch-mxs/regs-usbphy.h [moved from arch/arm/include/asm/arch-mx28/regs-usbphy.h with 94% similarity]
arch/arm/include/asm/arch-mxs/sys_proto.h [moved from arch/arm/include/asm/arch-mx28/sys_proto.h with 78% similarity]
arch/arm/include/asm/arch-omap3/mem.h
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/arch-tegra20/ap20.h [moved from arch/arm/include/asm/arch-tegra2/ap20.h with 98% similarity]
arch/arm/include/asm/arch-tegra20/apb_misc.h [moved from arch/arm/include/asm/arch-tegra2/apb_misc.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/board.h [moved from arch/arm/include/asm/arch-tegra2/board.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/clk_rst.h [moved from arch/arm/include/asm/arch-tegra2/clk_rst.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/clock.h [moved from arch/arm/include/asm/arch-tegra2/clock.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/emc.h [moved from arch/arm/include/asm/arch-tegra2/emc.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/flow.h [moved from arch/arm/include/asm/arch-tegra2/flow.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/funcmux.h [moved from arch/arm/include/asm/arch-tegra2/funcmux.h with 97% similarity]
arch/arm/include/asm/arch-tegra20/fuse.h [moved from arch/arm/include/asm/arch-tegra2/fuse.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/gp_padctrl.h [moved from arch/arm/include/asm/arch-tegra2/gp_padctrl.h with 98% similarity]
arch/arm/include/asm/arch-tegra20/gpio.h [moved from arch/arm/include/asm/arch-tegra2/gpio.h with 99% similarity]
arch/arm/include/asm/arch-tegra20/hardware.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/mmc.h [moved from arch/arm/include/asm/arch-tegra2/mmc.h with 84% similarity]
arch/arm/include/asm/arch-tegra20/pinmux.h [moved from arch/arm/include/asm/arch-tegra2/pinmux.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/pmc.h [moved from arch/arm/include/asm/arch-tegra2/pmc.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/pmu.h [moved from arch/arm/include/asm/arch-tegra2/pmu.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/scu.h [moved from arch/arm/include/asm/arch-tegra2/scu.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/sdram_param.h [moved from arch/arm/include/asm/arch-tegra2/sdram_param.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/sys_proto.h [moved from arch/arm/include/asm/arch-tegra2/sys_proto.h with 93% similarity]
arch/arm/include/asm/arch-tegra20/tegra20.h [moved from arch/arm/include/asm/arch-tegra2/tegra2.h with 87% similarity]
arch/arm/include/asm/arch-tegra20/tegra_i2c.h [moved from arch/arm/include/asm/arch-tegra2/tegra_i2c.h with 99% similarity]
arch/arm/include/asm/arch-tegra20/tegra_spi.h [moved from arch/arm/include/asm/arch-tegra2/tegra_spi.h with 96% similarity]
arch/arm/include/asm/arch-tegra20/timer.h [moved from arch/arm/include/asm/arch-tegra2/timer.h with 92% similarity]
arch/arm/include/asm/arch-tegra20/uart-spi-switch.h [moved from arch/arm/include/asm/arch-tegra2/uart-spi-switch.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/uart.h [moved from arch/arm/include/asm/arch-tegra2/uart.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/usb.h [moved from arch/arm/include/asm/arch-tegra2/usb.h with 100% similarity]
arch/arm/include/asm/arch-tegra20/warmboot.h [moved from arch/arm/include/asm/arch-tegra2/warmboot.h with 100% similarity]
arch/arm/include/asm/arch-u8500/clock.h
arch/arm/include/asm/arch-u8500/db8500_gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-u8500/db8500_pincfg.h [new file with mode: 0644]
arch/arm/include/asm/arch-u8500/hardware.h
arch/arm/include/asm/arch-u8500/prcmu.h [moved from board/st-ericsson/u8500/prcmu-fw.h with 55% similarity]
arch/arm/include/asm/arch-u8500/sys_proto.h
arch/arm/include/asm/emif.h
arch/arm/include/asm/imx-common/boot_mode.h [new file with mode: 0644]
arch/arm/include/asm/imx-common/gpio.h [new file with mode: 0644]
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/omap_common.h
arch/arm/lib/Makefile
arch/blackfin/cpu/Makefile
arch/nds32/include/asm/u-boot.h
arch/nds32/lib/board.c
arch/powerpc/cpu/mpc5xxx/cpu_init.c
arch/powerpc/lib/Makefile
arch/sh/include/asm/cpu_sh7706.h
arch/sh/include/asm/cpu_sh7710.h
arch/sh/include/asm/cpu_sh7720.h
arch/sh/include/asm/cpu_sh7722.h
arch/sh/include/asm/cpu_sh7723.h
arch/sh/include/asm/cpu_sh7724.h
arch/sh/include/asm/cpu_sh7734.h
arch/sh/include/asm/cpu_sh7750.h
arch/sh/include/asm/cpu_sh7757.h
arch/sh/include/asm/cpu_sh7763.h
arch/sh/include/asm/cpu_sh7780.h
arch/sh/include/asm/cpu_sh7785.h
arch/sh/lib/time.c
board/BuS/eb_cpux9k2/cpux9k2.c
board/BuS/vl_ma2sc/vl_ma2sc.c
board/CarMediaLab/flea3/flea3.c
board/armltd/vexpress/ca9x4_ct_vxp.c
board/atmel/at91sam9261ek/at91sam9261ek.c
board/atmel/at91sam9263ek/at91sam9263ek.c
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/atmel/at91sam9rlek/at91sam9rlek.c
board/atmel/at91sam9x5ek/Makefile [new file with mode: 0644]
board/atmel/at91sam9x5ek/at91sam9x5ek.c [new file with mode: 0644]
board/atmel/at91sam9x5ek/config.mk [new file with mode: 0644]
board/avionic-design/common/tamonten.c
board/avionic-design/dts/tegra20-medcom.dts [moved from board/avionic-design/dts/tegra2-medcom.dts with 100% similarity]
board/avionic-design/dts/tegra20-plutux.dts [moved from board/avionic-design/dts/tegra2-plutux.dts with 100% similarity]
board/avionic-design/dts/tegra20-tec.dts [moved from board/avionic-design/dts/tegra2-tec.dts with 100% similarity]
board/avionic-design/medcom/Makefile
board/avionic-design/plutux/Makefile
board/avionic-design/tec/Makefile
board/bluegiga/apx4devkit/Makefile [moved from board/o2dnt/Makefile with 90% similarity]
board/bluegiga/apx4devkit/apx4devkit.c [new file with mode: 0644]
board/bluegiga/apx4devkit/spl_boot.c [new file with mode: 0644]
board/calao/sbc35_a9g20/sbc35_a9g20.c
board/calao/tny_a9260/tny_a9260.c
board/cm_t35/cm_t35.c
board/compal/dts/tegra20-paz00.dts [moved from board/compal/dts/tegra2-paz00.dts with 100% similarity]
board/compal/paz00/Makefile
board/compal/paz00/paz00.c
board/compulab/dts/tegra20-trimslice.dts [moved from board/compulab/dts/tegra2-trimslice.dts with 100% similarity]
board/compulab/trimslice/Makefile
board/compulab/trimslice/trimslice.c
board/davinci/da8xxevm/da850evm.c
board/davinci/da8xxevm/hawkboard-ais-nand.cfg [new file with mode: 0644]
board/davinci/da8xxevm/hawkboard.c
board/denx/m28evk/m28evk.c
board/denx/m28evk/spl_boot.c
board/efikamx/efikamx.c [deleted file]
board/enbw/enbw_cmc/enbw_cmc.c
board/esg/ima3-mx53/ima3-mx53.c
board/eukrea/cpuat91/cpuat91.c
board/freescale/mx28evk/iomux.c
board/freescale/mx28evk/mx28evk.c
board/freescale/mx28evk/u-boot.bd [deleted file]
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx51evk/mx51evk.c
board/freescale/mx53ard/mx53ard.c
board/freescale/mx53evk/mx53evk.c
board/freescale/mx53loco/mx53loco.c
board/freescale/mx53smd/mx53smd.c
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/genesi/mx51_efikamx/Makefile [moved from board/efikamx/Makefile with 100% similarity]
board/genesi/mx51_efikamx/efikamx-usb.c [moved from board/efikamx/efikamx-usb.c with 99% similarity]
board/genesi/mx51_efikamx/efikamx.c [new file with mode: 0644]
board/genesi/mx51_efikamx/imximage_mx.cfg [moved from board/efikamx/imximage_mx.cfg with 71% similarity]
board/genesi/mx51_efikamx/imximage_sb.cfg [moved from board/efikamx/imximage_sb.cfg with 80% similarity]
board/htkw/mcx/mcx.c
board/htkw/mcx/mcx.h
board/ifm/o2dnt2/Makefile [new file with mode: 0644]
board/ifm/o2dnt2/o2dnt2.c [new file with mode: 0644]
board/isee/igep0020/config.mk [deleted file]
board/isee/igep0020/igep0020.c
board/isee/igep0020/igep0020.h
board/isee/igep0030/igep0030.c
board/isee/igep0030/igep0030.h
board/karo/tx25/tx25.c
board/keymile/km_arm/km_arm.c
board/logicpd/imx27lite/imx27lite.c
board/nvidia/common/board.c
board/nvidia/common/emc.c
board/nvidia/common/uart-spi-switch.c
board/nvidia/dts/tegra20-harmony.dts [moved from board/nvidia/dts/tegra2-harmony.dts with 92% similarity]
board/nvidia/dts/tegra20-seaboard.dts [moved from board/nvidia/dts/tegra2-seaboard.dts with 100% similarity]
board/nvidia/dts/tegra20-ventana.dts [moved from board/nvidia/dts/tegra2-ventana.dts with 92% similarity]
board/nvidia/dts/tegra20-whistler.dts [moved from board/nvidia/dts/tegra2-whistler.dts with 94% similarity]
board/nvidia/harmony/harmony.c
board/nvidia/seaboard/seaboard.c
board/nvidia/whistler/whistler.c
board/o2dnt/flash.c [deleted file]
board/o2dnt/o2dnt.c [deleted file]
board/omicron/calimain/calimain.c
board/raspberrypi/rpi_b/Makefile [new file with mode: 0644]
board/raspberrypi/rpi_b/rpi_b.c [new file with mode: 0644]
board/samsung/smdk5250/Makefile
board/samsung/smdk5250/clock_init.c
board/samsung/smdk5250/clock_init.h [new file with mode: 0644]
board/samsung/smdk5250/dmc_common.c [new file with mode: 0644]
board/samsung/smdk5250/dmc_init.c [deleted file]
board/samsung/smdk5250/dmc_init_ddr3.c [new file with mode: 0644]
board/samsung/smdk5250/setup.h
board/samsung/smdk5250/smdk5250-uboot-spl.lds [new file with mode: 0644]
board/samsung/smdk5250/smdk5250.c
board/samsung/smdk5250/smdk5250_spl.c [new file with mode: 0644]
board/schulercontrol/sc_sps_1/Makefile [new file with mode: 0644]
board/schulercontrol/sc_sps_1/sc_sps_1.c [new file with mode: 0644]
board/schulercontrol/sc_sps_1/spl_boot.c [new file with mode: 0644]
board/st-ericsson/snowball/Makefile [new file with mode: 0644]
board/st-ericsson/snowball/db8500_pins.h [new file with mode: 0644]
board/st-ericsson/snowball/snowball.c [new file with mode: 0644]
board/st-ericsson/u8500/Makefile
board/st-ericsson/u8500/u8500_href.c
board/syteco/zmx25/zmx25.c
board/taskit/stamp9g20/Makefile [new file with mode: 0644]
board/taskit/stamp9g20/led.c [new file with mode: 0644]
board/taskit/stamp9g20/stamp9g20.c [new file with mode: 0644]
board/ti/am335x/Makefile
board/ti/am335x/evm.c [deleted file]
board/ti/am335x/mux.c
board/ti/beagle/beagle.c
board/ttcontrol/vision2/vision2.c
boards.cfg
common/cmd_spi.c
doc/README.atmel_pmecc [new file with mode: 0644]
doc/README.m28
doc/README.mx28evk
doc/git-mailrc
drivers/bootcount/Makefile [new file with mode: 0644]
drivers/bootcount/bootcount.c [moved from arch/powerpc/lib/bootcount.c with 82% similarity]
drivers/bootcount/bootcount_at91.c [new file with mode: 0644]
drivers/bootcount/bootcount_blackfin.c [moved from arch/blackfin/cpu/bootcount.c with 100% similarity]
drivers/bootcount/bootcount_davinci.c [new file with mode: 0644]
drivers/bootcount/bootcount_ram.c [new file with mode: 0644]
drivers/dma/apbh_dma.c
drivers/gpio/Makefile
drivers/gpio/bcm2835_gpio.c [new file with mode: 0644]
drivers/gpio/db8500_gpio.c [new file with mode: 0644]
drivers/gpio/mxc_gpio.c
drivers/gpio/mxs_gpio.c
drivers/gpio/omap_gpio.c [moved from arch/arm/cpu/armv7/omap-common/gpio.c with 100% similarity]
drivers/gpio/tegra_gpio.c
drivers/i2c/mxs_i2c.c
drivers/i2c/omap24xx_i2c.c
drivers/i2c/tegra_i2c.c
drivers/input/Makefile
drivers/mmc/Makefile
drivers/mmc/arm_pl180_mmci.c
drivers/mmc/arm_pl180_mmci.h
drivers/mmc/fsl_esdhc.c
drivers/mmc/mxsmmc.c
drivers/mmc/spl_mmc_load.c [new file with mode: 0644]
drivers/mmc/tegra_mmc.c
drivers/mmc/tegra_mmc.h
drivers/mtd/cfi_flash.c
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/atmel_nand_ecc.h
drivers/mtd/nand/mxs_nand.c
drivers/mtd/nand/omap_gpmc.c
drivers/mtd/spi/spansion.c
drivers/mtd/spi/stmicro.c
drivers/mtd/spi/winbond.c
drivers/net/Makefile
drivers/net/cpsw.c [new file with mode: 0644]
drivers/net/macb.c
drivers/rtc/Makefile
drivers/rtc/ds1337.c
drivers/rtc/imxdi.c [new file with mode: 0644]
drivers/rtc/mx27rtc.c [new file with mode: 0644]
drivers/rtc/mxsrtc.c
drivers/serial/atmel_usart.c
drivers/serial/ns16550.c
drivers/serial/serial_pl01x.c
drivers/spi/atmel_spi.c
drivers/spi/atmel_spi.h
drivers/spi/mxc_spi.c
drivers/spi/mxs_spi.c
drivers/spi/omap3_spi.c
drivers/spi/omap3_spi.h
drivers/spi/tegra_spi.c
drivers/usb/host/Makefile
drivers/usb/host/ehci-mxs.c
drivers/usb/host/ohci-da8xx.c [new file with mode: 0644]
drivers/usb/musb/da8xx.c
drivers/video/Makefile
drivers/video/exynos_dp.c [new file with mode: 0644]
drivers/video/exynos_dp_lowlevel.c [new file with mode: 0644]
drivers/video/exynos_dp_lowlevel.h [new file with mode: 0644]
drivers/video/exynos_fb.c
drivers/video/exynos_fimd.c
drivers/video/exynos_pwm_bl.c [new file with mode: 0644]
dts/Makefile
include/bootcount.h [new file with mode: 0644]
include/configs/SX1.h
include/configs/VCMA9.h
include/configs/a320evb.h
include/configs/actux1.h
include/configs/actux2.h
include/configs/actux3.h
include/configs/actux4.h
include/configs/adp-ag101.h
include/configs/adp-ag101p.h
include/configs/adp-ag102.h
include/configs/afeb9260.h
include/configs/am335x_evm.h
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/apollon.h
include/configs/apx4devkit.h [new file with mode: 0644]
include/configs/at91rm9200ek.h
include/configs/at91sam9260ek.h
include/configs/at91sam9261ek.h
include/configs/at91sam9263ek.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9rlek.h
include/configs/at91sam9x5ek.h [new file with mode: 0644]
include/configs/balloon3.h
include/configs/ca9x4_ct_vxp.h
include/configs/calimain.h
include/configs/cam_enc_4xx.h
include/configs/cm4008.h
include/configs/cm41xx.h
include/configs/cm_t35.h
include/configs/colibri_pxa270.h
include/configs/cpu9260.h
include/configs/cpuat91.h
include/configs/da830evm.h
include/configs/da850evm.h
include/configs/davinci_dm355evm.h
include/configs/davinci_dm355leopard.h
include/configs/davinci_dm365evm.h
include/configs/davinci_dm6467evm.h
include/configs/davinci_dvevm.h
include/configs/davinci_schmoogie.h
include/configs/davinci_sffsdr.h
include/configs/davinci_sonata.h
include/configs/devkit3250.h
include/configs/devkit8000.h
include/configs/dig297.h
include/configs/dvlhost.h
include/configs/ea20.h
include/configs/eb_cpux9k2.h
include/configs/edminiv2.h
include/configs/enbw_cmc.h
include/configs/ethernut5.h
include/configs/flea3.h
include/configs/harmony.h
include/configs/hawkboard.h
include/configs/highbank.h
include/configs/igep00x0.h
include/configs/ima3-mx53.h
include/configs/imx27lite-common.h
include/configs/imx31_litekit.h
include/configs/imx31_phycore.h
include/configs/integratorap.h
include/configs/integratorcp.h
include/configs/jadecpu.h
include/configs/jornada.h
include/configs/km/km_arm.h
include/configs/lubbock.h
include/configs/m28evk.h
include/configs/mcx.h
include/configs/medcom.h
include/configs/meesc.h
include/configs/mv-common.h
include/configs/mx1ads.h
include/configs/mx25pdk.h
include/configs/mx28evk.h
include/configs/mx31ads.h
include/configs/mx31pdk.h
include/configs/mx35pdk.h
include/configs/mx51_efikamx.h [moved from include/configs/efikamx.h with 96% similarity]
include/configs/mx51evk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/mx6qarm2.h
include/configs/mx6qsabrelite.h
include/configs/nhk8815.h
include/configs/ns9750dev.h
include/configs/o2d.h [new file with mode: 0644]
include/configs/o2d300.h [new file with mode: 0644]
include/configs/o2dnt-common.h [new file with mode: 0644]
include/configs/o2dnt.h [deleted file]
include/configs/o2dnt2.h [new file with mode: 0644]
include/configs/o2i.h [new file with mode: 0644]
include/configs/o2mnt.h [new file with mode: 0644]
include/configs/o3dnt.h [new file with mode: 0644]
include/configs/omap1510inn.h
include/configs/omap2420h4.h
include/configs/omap3_beagle.h
include/configs/omap3_evm_common.h
include/configs/omap3_logic.h
include/configs/omap3_mvblx.h
include/configs/omap3_overo.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h
include/configs/omap3_zoom1.h
include/configs/omap3_zoom2.h
include/configs/omap4_common.h
include/configs/omap5912osk.h
include/configs/omap5_evm.h
include/configs/omap730p2.h
include/configs/origen.h
include/configs/otc570.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/paz00.h
include/configs/pdnb3.h
include/configs/plutux.h
include/configs/pm9261.h
include/configs/pm9263.h
include/configs/pm9g45.h
include/configs/pxa255_idp.h
include/configs/qong.h
include/configs/rpi_b.h [new file with mode: 0644]
include/configs/s5p_goni.h
include/configs/s5pc210_universal.h
include/configs/sbc35_a9g20.h
include/configs/sc_sps_1.h [new file with mode: 0644]
include/configs/scb9328.h
include/configs/seaboard.h
include/configs/smdk2410.h
include/configs/smdk5250.h
include/configs/smdk6400.h
include/configs/smdkc100.h
include/configs/smdkv310.h
include/configs/snapper9260.h
include/configs/snowball.h [new file with mode: 0644]
include/configs/spear-common.h
include/configs/stamp9g20.h [new file with mode: 0644]
include/configs/tam3517-common.h
include/configs/tec.h
include/configs/tegra20-common-post.h [moved from include/configs/tegra2-common-post.h with 74% similarity]
include/configs/tegra20-common.h [moved from include/configs/tegra2-common.h with 83% similarity]
include/configs/tnetv107x_evm.h
include/configs/tny_a9260.h
include/configs/top9000.h
include/configs/trats.h
include/configs/tricorder.h
include/configs/trimslice.h
include/configs/trizepsiv.h
include/configs/tt01.h
include/configs/tx25.h
include/configs/u8500_href.h
include/configs/vct.h
include/configs/ventana.h
include/configs/versatile.h
include/configs/vision2.h
include/configs/vl_ma2sc.h
include/configs/vpac270.h
include/configs/whistler.h
include/configs/xaeniax.h
include/configs/zipitz2.h
include/configs/zmx25.h
include/cpsw.h [new file with mode: 0644]
include/fdtdec.h
include/flash.h
include/fsl_esdhc.h
include/lcd.h
include/mmc.h
include/mpc5xxx.h
include/mtd/cfi_flash.h
include/nand.h
include/ns16550.h
include/serial.h
include/sh_tmu.h [new file with mode: 0644]
mkconfig
spl/Makefile

index b78e2ac..2e6fde8 100644 (file)
@@ -79,3 +79,6 @@ cscope.*
 /onenand_ipl/onenand-ipl*
 /onenand_ipl/board/*/onenand*
 /onenand_ipl/board/*/*.S
+
+# spl ais files
+/spl/*.ais
diff --git a/CREDITS b/CREDITS
index 933104c..fa9a14e 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -428,6 +428,11 @@ E: art@videon-central.com
 D: Support for NetSilicon NS7520
 D: Support for ColdFire MCF5275
 
+N: Jeremy C. Andrus
+E: jeremy@jeremya.com
+D: ColdFire MCF5249 initialization code
+W: jeremya.com
+
 N: Michal Simek
 E: monstr@monstr.eu
 D: Support for Microblaze, ML401, XUPV2P board
index c5a6f2f..4aabcff 100644 (file)
@@ -237,6 +237,15 @@ Wolfgang Grandegger <wg@denx.de>
        IPHASE4539      MPC8260
        SCM             MPC8260
 
+Anatolij Gustschin <agust@denx.de>
+
+       O2D             MPC5200
+       O2D300          MPC5200
+       O2DNT2          MPC5200
+       O2I             MPC5200
+       O2MNT           MPC5200
+       O3DNT           MPC5200
+
 Rob Herring <rob.herring@calxeda.com>
 
        highbank        highbank
@@ -246,12 +255,6 @@ Klaus Heydeck <heydeck@kieback-peter.de>
        KUP4K           MPC855
        KUP4X           MPC859
 
-Ilko Iliev <iliev@ronetix.at>
-
-       PM9261          AT91SAM9261
-       PM9263          AT91SAM9263
-       PM9G45          ARM926EJS (AT91SAM9G45 SoC)
-
 Gary Jennejohn <garyj@denx.de>
 
        quad100hd       PPC405EP
@@ -615,7 +618,6 @@ Rishi Bhattacharya <rishi@ti.com>
 Andreas Bießmann <andreas.devel@gmail.com>
 
        at91rm9200ek    at91rm9200
-       grasshopper     avr32
 
 Cliff Brake <cliff.brake@gmail.com>
 
@@ -658,7 +660,7 @@ Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
        meesc           ARM926EJS (AT91SAM9263 SoC)
        otc570          ARM926EJS (AT91SAM9263 SoC)
 
-Sedji Gaouaou<sedji.gaouaou@atmel.com>
+Bo Shen<voice.shen@atmel.com>
        at91sam9g10ek           ARM926EJS (AT91SAM9G10 SoC)
        at91sam9m10g45ek        ARM926EJS (AT91SAM9G45 SoC)
 
@@ -681,10 +683,20 @@ Vaibhav Hiremath <hvaibhav@ti.com>
 
        am3517_evm      ARM ARMV7 (AM35x SoC)
 
+Markus Hubig <mhubig@imko.de>
+
+       STAMP9G20       ARM926EJS
+
 Grazvydas Ignotas <notasas@gmail.com>
 
        omap3_pandora   ARM ARMV7 (OMAP3xx SoC)
 
+Ilko Iliev <iliev@ronetix.at>
+
+       PM9261          AT91SAM9261
+       PM9263          AT91SAM9263
+       PM9G45          ARM926EJS (AT91SAM9G45 SoC)
+
 Michael Jones <michael.jones@matrix-vision.de>
 
        omap3_mvblx     ARM ARMV7 (OMAP3xx SoC)
@@ -784,6 +796,10 @@ Linus Walleij <linus.walleij@linaro.org>
        integratorap    various
        integratorcp    various
 
+Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
+
+       apx4devkit      i.MX28
+
 Luka Perkov <uboot@lukaperkov.net>
 
        ib62x0          ARM926EJS
@@ -792,6 +808,10 @@ Dave Peverley <dpeverley@mpc-data.co.uk>
 
        omap730p2       ARM926EJS
 
+Mathieu Poirier <mathieu.poirier@linaro.org>
+
+       snowball        ARM ARMV7 (u8500 SoC)
+
 Stelian Pop <stelian@popies.net>
 
        at91sam9260ek   ARM926EJS (AT91SAM9260 SoC)
@@ -811,9 +831,9 @@ Sricharan R <r.sricharan@ti.com>
 
 Thierry Reding <thierry.reding@avionic-design.de>
 
-       plutux          Tegra2 (ARM7 & A9 Dual Core)
-       medcom          Tegra2 (ARM7 & A9 Dual Core)
-       tec             Tegra2 (ARM7 & A9 Dual Core)
+       plutux          Tegra20 (ARM7 & A9 Dual Core)
+       medcom          Tegra20 (ARM7 & A9 Dual Core)
+       tec             Tegra20 (ARM7 & A9 Dual Core)
 
 Christian Riesch <christian.riesch@omicron.at>
 Manfred Rudigier <manfred.rudigier@omicron.at>
@@ -866,6 +886,14 @@ Michael Schwingen <michael@schwingen.org>
        actux4          xscale/ixp
        dvlhost         xscale/ixp
 
+Matt Sealey <matt@genesi-usa.com>
+
+       efikamx         i.MX51
+       efikasb         i.MX51
+
+Bo Shen <voice.shen@atmel.com>
+       at91sam9x5ek            ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC)
+
 Nick Thompson <nick.thompson@gefanuc.com>
 
        da830evm        ARM926EJS (DA830/OMAP-L137)
@@ -891,8 +919,7 @@ Marek Vasut <marek.vasut@gmail.com>
        vpac270         xscale/pxa
        zipitz2         xscale/pxa
        m28evk          i.MX28
-       efikamx         i.MX51
-       efikasb         i.MX51
+       sc_sps_1        i.MX28
 
 Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
 
@@ -917,16 +944,20 @@ Michael Walle <michael@walle.cc>
 
 Tom Warren <twarren@nvidia.com>
 
-       harmony         Tegra2 (ARM7 & A9 Dual Core)
-       seaboard        Tegra2 (ARM7 & A9 Dual Core)
+       harmony         Tegra20 (ARM7 & A9 Dual Core)
+       seaboard        Tegra20 (ARM7 & A9 Dual Core)
 
 Tom Warren <twarren@nvidia.com>
 Stephen Warren <swarren@nvidia.com>
 
-       ventana         Tegra2 (ARM7 & A9 Dual Core)
-       paz00           Tegra2 (ARM7 & A9 Dual Core)
-       trimslice       Tegra2 (ARM7 & A9 Dual Core)
-       whistler        Tegra2 (ARM7 & A9 Dual Core)
+       ventana         Tegra20 (ARM7 & A9 Dual Core)
+       paz00           Tegra20 (ARM7 & A9 Dual Core)
+       trimslice       Tegra20 (ARM7 & A9 Dual Core)
+       whistler        Tegra20 (ARM7 & A9 Dual Core)
+
+Stephen Warren <swarren@wwwdotorg.org>
+
+       rpi_b           BCM2835 (ARM1176)
 
 Thomas Weber <weber@corscience.de>
 
@@ -1079,6 +1110,9 @@ Wolfgang Wegner <w.wegner@astro-kom.de>
 #      Board           CPU                                             #
 #########################################################################
 
+Andreas Bießmann <andreas.devel@googlemail.com>
+       grasshopper             AT32AP7000
+
 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
 
        FAVR-32-EZKIT           AT32AP7000
diff --git a/MAKEALL b/MAKEALL
index 6b9ff30..eb7dd02 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -87,9 +87,9 @@ while true ; do
        -c|--cpu)
                # echo "Option CPU: argument \`$2'"
                if [ "$opt_c" ] ; then
-                       opt_c="${opt_c%)} || \$3 == \"$2\")"
+                       opt_c="${opt_c%)} || \$3 == \"$2\" || \$3 ~ /$2:/)"
                else
-                       opt_c="(\$3 == \"$2\")"
+                       opt_c="(\$3 == \"$2\" || \$3 ~ /$2:/)"
                fi
                SELECTED='y'
                shift 2 ;;
@@ -211,14 +211,17 @@ RC=0
 # Helper funcs for parsing boards.cfg
 boards_by_field()
 {
+       FS="[ \t]+"
+       [ -n "$3" ] && FS="$3"
        awk \
                -v field="$1" \
                -v select="$2" \
+               -F "$FS" \
                '($1 !~ /^#/ && $field == select) { print $1 }' \
                boards.cfg
 }
 boards_by_arch() { boards_by_field 2 "$@" ; }
-boards_by_cpu()  { boards_by_field 3 "$@" ; }
+boards_by_cpu()  { boards_by_field 3 "$@" "[: \t]+" ; }
 boards_by_soc()  { boards_by_field 6 "$@" ; }
 
 #########################################################################
index 73c8e39..d6d8ab2 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -225,106 +225,105 @@ endif
 
 OBJS := $(addprefix $(obj),$(OBJS))
 
-LIBS  = lib/libgeneric.o
-LIBS += lib/lzma/liblzma.o
-LIBS += lib/lzo/liblzo.o
-LIBS += lib/zlib/libz.o
-ifeq ($(CONFIG_TIZEN),y)
-LIBS += lib/tizen/libtizen.o
-endif
-LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
-       "board/$(VENDOR)/common/lib$(VENDOR).o"; fi)
-LIBS += $(CPUDIR)/lib$(CPU).o
+HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
+
+LIBS-y += lib/libgeneric.o
+LIBS-y += lib/lzma/liblzma.o
+LIBS-y += lib/lzo/liblzo.o
+LIBS-y += lib/zlib/libz.o
+LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o
+LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
+LIBS-y += $(CPUDIR)/lib$(CPU).o
 ifdef SOC
-LIBS += $(CPUDIR)/$(SOC)/lib$(SOC).o
+LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
 endif
 ifeq ($(CPU),ixp)
-LIBS += arch/arm/cpu/ixp/npe/libnpe.o
+LIBS-y += arch/arm/cpu/ixp/npe/libnpe.o
 endif
-ifeq ($(CONFIG_OF_EMBED),y)
-LIBS += dts/libdts.o
-endif
-LIBS += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS += fs/cramfs/libcramfs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o \
+LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
+LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
+LIBS-y += fs/cramfs/libcramfs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o \
        fs/reiserfs/libreiserfs.o fs/ext2/libext2fs.o fs/yaffs2/libyaffs2.o \
        fs/ubifs/libubifs.o fs/zfs/libzfs.o
-LIBS += net/libnet.o
-LIBS += disk/libdisk.o
-LIBS += drivers/bios_emulator/libatibiosemu.o
-LIBS += drivers/block/libblock.o
-LIBS += drivers/dma/libdma.o
-LIBS += drivers/fpga/libfpga.o
-LIBS += drivers/gpio/libgpio.o
-LIBS += drivers/hwmon/libhwmon.o
-LIBS += drivers/i2c/libi2c.o
-LIBS += drivers/input/libinput.o
-LIBS += drivers/misc/libmisc.o
-LIBS += drivers/mmc/libmmc.o
-LIBS += drivers/mtd/libmtd.o
-LIBS += drivers/mtd/nand/libnand.o
-LIBS += drivers/mtd/onenand/libonenand.o
-LIBS += drivers/mtd/ubi/libubi.o
-LIBS += drivers/mtd/spi/libspi_flash.o
-LIBS += drivers/net/libnet.o
-LIBS += drivers/net/phy/libphy.o
-LIBS += drivers/pci/libpci.o
-LIBS += drivers/pcmcia/libpcmcia.o
-LIBS += drivers/power/libpower.o
-LIBS += drivers/spi/libspi.o
+LIBS-y += net/libnet.o
+LIBS-y += disk/libdisk.o
+LIBS-y += drivers/bios_emulator/libatibiosemu.o
+LIBS-y += drivers/block/libblock.o
+LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
+LIBS-y += drivers/dma/libdma.o
+LIBS-y += drivers/fpga/libfpga.o
+LIBS-y += drivers/gpio/libgpio.o
+LIBS-y += drivers/hwmon/libhwmon.o
+LIBS-y += drivers/i2c/libi2c.o
+LIBS-y += drivers/input/libinput.o
+LIBS-y += drivers/misc/libmisc.o
+LIBS-y += drivers/mmc/libmmc.o
+LIBS-y += drivers/mtd/libmtd.o
+LIBS-y += drivers/mtd/nand/libnand.o
+LIBS-y += drivers/mtd/onenand/libonenand.o
+LIBS-y += drivers/mtd/ubi/libubi.o
+LIBS-y += drivers/mtd/spi/libspi_flash.o
+LIBS-y += drivers/net/libnet.o
+LIBS-y += drivers/net/phy/libphy.o
+LIBS-y += drivers/pci/libpci.o
+LIBS-y += drivers/pcmcia/libpcmcia.o
+LIBS-y += drivers/power/libpower.o
+LIBS-y += drivers/spi/libspi.o
 ifeq ($(CPU),mpc83xx)
-LIBS += drivers/qe/libqe.o
-LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+LIBS-y += drivers/qe/libqe.o
+LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
 endif
 ifeq ($(CPU),mpc85xx)
-LIBS += drivers/qe/libqe.o
-LIBS += drivers/net/fm/libfm.o
-LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+LIBS-y += drivers/qe/libqe.o
+LIBS-y += drivers/net/fm/libfm.o
+LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
 endif
 ifeq ($(CPU),mpc86xx)
-LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-LIBS += drivers/rtc/librtc.o
-LIBS += drivers/serial/libserial.o
-ifeq ($(CONFIG_GENERIC_LPC_TPM),y)
-LIBS += drivers/tpm/libtpm.o
-endif
-LIBS += drivers/twserial/libtws.o
-LIBS += drivers/usb/eth/libusb_eth.o
-LIBS += drivers/usb/gadget/libusb_gadget.o
-LIBS += drivers/usb/host/libusb_host.o
-LIBS += drivers/usb/musb/libusb_musb.o
-LIBS += drivers/usb/phy/libusb_phy.o
-LIBS += drivers/usb/ulpi/libusb_ulpi.o
-LIBS += drivers/video/libvideo.o
-LIBS += drivers/watchdog/libwatchdog.o
-LIBS += common/libcommon.o
-LIBS += lib/libfdt/libfdt.o
-LIBS += api/libapi.o
-LIBS += post/libpost.o
-LIBS += test/libtest.o
+LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
+endif
+LIBS-y += drivers/rtc/librtc.o
+LIBS-y += drivers/serial/libserial.o
+LIBS-$(CONFIG_GENERIC_LPC_TPM) += drivers/tpm/libtpm.o
+LIBS-y += drivers/twserial/libtws.o
+LIBS-y += drivers/usb/eth/libusb_eth.o
+LIBS-y += drivers/usb/gadget/libusb_gadget.o
+LIBS-y += drivers/usb/host/libusb_host.o
+LIBS-y += drivers/usb/musb/libusb_musb.o
+LIBS-y += drivers/usb/phy/libusb_phy.o
+LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
+LIBS-y += drivers/video/libvideo.o
+LIBS-y += drivers/watchdog/libwatchdog.o
+LIBS-y += common/libcommon.o
+LIBS-y += lib/libfdt/libfdt.o
+LIBS-y += api/libapi.o
+LIBS-y += post/libpost.o
+LIBS-y += test/libtest.o
 
 ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
-LIBS += $(CPUDIR)/omap-common/libomap-common.o
+LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
 ifeq ($(SOC),mx5)
-LIBS += $(CPUDIR)/imx-common/libimx-common.o
+LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
 endif
 ifeq ($(SOC),mx6)
-LIBS += $(CPUDIR)/imx-common/libimx-common.o
+LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
 endif
 
 ifeq ($(SOC),s5pc1xx)
-LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
+LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
 endif
 ifeq ($(SOC),exynos)
-LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
+LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
+endif
+ifeq ($(SOC),tegra20)
+LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
 endif
 
-LIBS := $(addprefix $(obj),$(sort $(LIBS)))
+LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
 .PHONY : $(LIBS)
 
 LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
@@ -382,6 +381,15 @@ ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
+# enable combined SPL/u-boot/dtb rules for tegra
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+ALL-y += $(obj)u-boot-dtb-tegra.bin
+else
+ALL-y += $(obj)u-boot-nodtb-tegra.bin
+endif
+endif
+
 all:           $(ALL-y) $(SUBDIR_EXAMPLES)
 
 $(obj)u-boot.dtb:      $(obj)u-boot
@@ -442,7 +450,8 @@ $(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
                rm $(obj)spl/u-boot-spl-pad.bin
 
 $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
-               $(obj)tools/mkimage -s -n /dev/null -T aisimage \
+               $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \
+                       -T aisimage \
                        -e $(CONFIG_SPL_TEXT_BASE) \
                        -d $(obj)spl/u-boot-spl.bin \
                        $(obj)spl/u-boot-spl.ais
@@ -451,10 +460,12 @@ $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
                        $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
                cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
                        $(obj)u-boot.ais
-               rm $(obj)spl/u-boot-spl{,-pad}.ais
+
+# Specify the target for use in elftosb call
+ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
 
 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
-               elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
+               elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
                        -o $(obj)u-boot.sb
 
 # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
@@ -473,6 +484,20 @@ $(obj)u-boot.spr:  $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
                        conv=notrunc 2>/dev/null
                cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
 
+ifeq ($(SOC),tegra20)
+ifeq ($(CONFIG_OF_SEPARATE),y)
+$(obj)u-boot-dtb-tegra.bin:    $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin $(obj)u-boot.dtb
+               $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $(obj)u-boot.dtb > $@
+               rm $(obj)spl/u-boot-spl-pad.bin
+else
+$(obj)u-boot-nodtb-tegra.bin:  $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+               $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin
+               cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
+               rm $(obj)spl/u-boot-spl-pad.bin
+endif
+endif
+
 ifeq ($(CONFIG_SANDBOX),y)
 GEN_UBOOT = \
                cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@@ -801,6 +826,7 @@ clobber:    tidy
        @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
        @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
        @rm -f $(obj)dts/*.tmp
+       @rm -f $(obj)spl/u-boot-spl{,-pad}.ais
 
 mrproper \
 distclean:     clobber unconfig
diff --git a/README b/README
index fb9d904..da4341f 100644 (file)
--- a/README
+++ b/README
@@ -744,8 +744,8 @@ The following options need to be configured:
 - Monitor Functions:
                Monitor commands can be included or excluded
                from the build by using the #include files
-               "config_cmd_all.h" and #undef'ing unwanted
-               commands, or using "config_cmd_default.h"
+               <config_cmd_all.h> and #undef'ing unwanted
+               commands, or using <config_cmd_default.h>
                and augmenting with additional #define's
                for wanted commands.
 
index 986b1f9..d435e8a 100644 (file)
@@ -30,6 +30,9 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include <netdev.h>
 
 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
@@ -205,7 +208,7 @@ u32 imx_get_uartclk(void)
        return freq;
 }
 
-unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
+unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 {
        u32 nfc_pdf, hsp_podf;
        u32 pll, ret_val = 0, usb_prdf, usb_podf;
@@ -270,7 +273,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clocks clk)
 
        return ret_val;
 }
-unsigned int mxc_get_peri_clock(enum mxc_peri_clocks clk)
+unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
 {
        u32 ret_val = 0, pdf, pre_pdf, clk_sel;
        struct ccm_regs *ccm =
@@ -463,7 +466,6 @@ int print_cpuinfo(void)
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
  */
-
 int cpu_eth_init(bd_t *bis)
 {
        int rc = -ENODEV;
@@ -475,6 +477,17 @@ int cpu_eth_init(bd_t *bis)
        return rc;
 }
 
+#ifdef CONFIG_FSL_ESDHC
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+       return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
 int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
index f93191d..a302575 100644 (file)
@@ -44,8 +44,6 @@ enum iomux_reg_addr {
 #define MUX_INPUT_NUM_MUX      \
                (((IOMUXSW_INPUT_END - IOMUXSW_INPUT_CTL) >> 2) + 1)
 
-#define PIN_TO_IOMUX_INDEX(pin) ((PIN_TO_IOMUX_PAD(pin) - 0x328) >> 2)
-
 /*
  * Request ownership for an IO pin. This function has to be the first one
  * being called before that pin is used.
diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile
new file mode 100644 (file)
index 0000000..4ea6d6b
--- /dev/null
@@ -0,0 +1,37 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(SOC).o
+
+SOBJS  := lowlevel_init.o
+COBJS  := reset.o timer.o
+
+SRCS   := $(SOBJS:.o=.c) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk
new file mode 100644 (file)
index 0000000..b87ce24
--- /dev/null
@@ -0,0 +1,19 @@
+#
+# (C) Copyright 2012 Stephen Warren
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License
+# version 2 as published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# Don't attempt to override the target CPU/ABI options;
+# the Raspberry Pi toolchain does the right thing by default.
+PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
+PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))
diff --git a/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S b/arch/arm/cpu/arm1176/bcm2835/lowlevel_init.S
new file mode 100644 (file)
index 0000000..c7b0843
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+       mov     pc, lr
diff --git a/arch/arm/cpu/arm1176/bcm2835/reset.c b/arch/arm/cpu/arm1176/bcm2835/reset.c
new file mode 100644 (file)
index 0000000..8c37ad9
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/wdog.h>
+
+#define RESET_TIMEOUT 10
+
+void reset_cpu(ulong addr)
+{
+       struct bcm2835_wdog_regs *regs =
+               (struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
+       uint32_t rstc;
+
+       rstc = readl(&regs->rstc);
+       rstc &= ~BCM2835_WDOG_RSTC_WRCFG_MASK;
+       rstc |= BCM2835_WDOG_RSTC_WRCFG_FULL_RESET;
+
+       writel(BCM2835_WDOG_PASSWORD | RESET_TIMEOUT, &regs->wdog);
+       writel(BCM2835_WDOG_PASSWORD | rstc, &regs->rstc);
+}
diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c
new file mode 100644 (file)
index 0000000..d232d7e
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+int timer_init(void)
+{
+       return 0;
+}
+
+ulong get_timer(ulong base)
+{
+       struct bcm2835_timer_regs *regs =
+               (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR;
+
+       return readl(&regs->clo) - base;
+}
+
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+ulong get_tbclk(void)
+{
+       return CONFIG_SYS_HZ;
+}
+
+void __udelay(unsigned long usec)
+{
+       ulong endtime;
+       signed long diff;
+
+       endtime = get_timer(0) + usec;
+
+       do {
+               ulong now = get_timer(0);
+               diff = endtime - now;
+       } while (diff >= 0);
+}
index c0fd114..532a90b 100644 (file)
@@ -65,3 +65,10 @@ static void cache_flush (void)
        /* mem barrier to sync things */
        asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
 }
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+
+       return 0;
+}
index 974f288..ce7b3c9 100644 (file)
@@ -51,6 +51,8 @@ int cleanup_before_linux (void)
        /* Nothing more needed */
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
        /* No cleanup before linux for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_TEGRA)
+       /* No cleanup before linux for tegra as yet */
 #else
 #error No cleanup_before_linux() defined for this CPU type
 #endif
index 464dd30..c2f898f 100644 (file)
@@ -180,6 +180,9 @@ int timer_init (void)
        PUT32(T0TC, 0);
        PUT32(T0TCR, 1);        /* enable timer0 */
 
+#elif defined(CONFIG_TEGRA)
+       /* No timer routines for tegra as yet */
+       lastdec = 0;
 #else
 #error No timer_init() defined for this CPU type
 #endif
@@ -282,6 +285,8 @@ void __udelay (unsigned long usec)
 
 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
        /* No timer routines for IntegratorAP/CM720T as yet */
+#elif defined(CONFIG_TEGRA)
+       /* No timer routines for tegra as yet */
 #else
 #error Timer routines not defined for this CPU type
 #endif
index 3b97e80..2f914e9 100644 (file)
@@ -51,6 +51,16 @@ _start: b    reset
        ldr     pc, _irq
        ldr     pc, _fiq
 
+#ifdef CONFIG_SPL_BUILD
+_undefined_instruction: .word _undefined_instruction
+_software_interrupt:   .word _software_interrupt
+_prefetch_abort:       .word _prefetch_abort
+_data_abort:           .word _data_abort
+_not_used:             .word _not_used
+_irq:                  .word _irq
+_fiq:                  .word _fiq
+_pad:                  .word 0x12345678 /* now 16*4=64 */
+#else
 _undefined_instruction: .word undefined_instruction
 _software_interrupt:   .word software_interrupt
 _prefetch_abort:       .word prefetch_abort
@@ -58,6 +68,8 @@ _data_abort:          .word data_abort
 _not_used:             .word not_used
 _irq:                  .word irq
 _fiq:                  .word fiq
+_pad:                  .word 0x12345678 /* now 16*4=64 */
+#endif /* CONFIG_SPL_BUILD */
 
        .balignl 16,0xdeadbeef
 
@@ -77,7 +89,11 @@ _fiq:                        .word fiq
 
 .globl _TEXT_BASE
 _TEXT_BASE:
+#ifdef CONFIG_SPL_BUILD
+       .word   CONFIG_SPL_TEXT_BASE
+#else
        .word   CONFIG_SYS_TEXT_BASE
+#endif
 
 /*
  * These are defined in the board-specific linker script.
@@ -167,6 +183,7 @@ stack_setup:
 
        adr     r0, _start
        cmp     r0, r6
+       moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
        beq     clear_bss               /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
        ldr     r3, _bss_start_ofs
@@ -398,6 +415,8 @@ lock_loop:
        ldr     r0, VPBDIV_ADR
        mov     r1, #0x01       /* VPB clock is same as process clock */
        str     r1, [r0]
+#elif defined(CONFIG_TEGRA)
+       /* No cpu_init_crit for tegra as yet */
 #else
 #error No cpu_init_crit() defined for current CPU type
 #endif
@@ -413,7 +432,7 @@ lock_loop:
        str     r1, [r0]
 #endif
 
-#ifndef CONFIG_LPC2292
+#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
        mov     ip, lr
        /*
         * before relocating, we have to setup RAM timing
@@ -427,6 +446,7 @@ lock_loop:
        mov     pc, lr
 
 
+#ifndef CONFIG_SPL_BUILD
 /*
  *************************************************************************
  *
@@ -589,6 +609,7 @@ fiq:
        bl      do_fiq
 
 #endif
+#endif /* CONFIG_SPL_BUILD */
 
 #if defined(CONFIG_NETARM)
        .align  5
@@ -620,6 +641,8 @@ reset_cpu:
 .globl reset_cpu
 reset_cpu:
        mov     pc, r0
+#elif defined(CONFIG_TEGRA)
+       /* No specific reset actions for tegra as yet */
 #else
 #error No reset_cpu() defined for current CPU type
 #endif
diff --git a/arch/arm/cpu/arm720t/tegra20/Makefile b/arch/arm/cpu/arm720t/tegra20/Makefile
new file mode 100644 (file)
index 0000000..6e48475
--- /dev/null
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(SOC).o
+
+COBJS-y        += cpu.o
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
+
+SRCS   := $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm720t/tegra20/board.h b/arch/arm/cpu/arm720t/tegra20/board.h
new file mode 100644 (file)
index 0000000..61b91c0
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2010-2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+void board_init_uart_f(void);
+void gpio_config_uart(void);
similarity index 66%
rename from board/isee/igep0030/config.mk
rename to arch/arm/cpu/arm720t/tegra20/config.mk
index 059a878..62a31d8 100644 (file)
@@ -1,9 +1,9 @@
 #
-# (C) Copyright 2009
-# ISEE 2007 SL, <www.iseebcn.com>
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
 #
-# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
+USE_PRIVATE_LIBGCC = yes
similarity index 63%
rename from arch/arm/cpu/armv7/tegra2/ap20.c
rename to arch/arm/cpu/arm720t/tegra20/cpu.c
index 1aad387..6d4d66b 100644 (file)
 */
 
 #include <asm/io.h>
-#include <asm/arch/tegra2.h>
-#include <asm/arch/ap20.h>
+#include <asm/arch/tegra20.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/fuse.h>
-#include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/scu.h>
-#include <asm/arch/warmboot.h>
 #include <common.h>
-
-int tegra_get_chip_type(void)
-{
-       struct apb_misc_gp_ctlr *gp;
-       struct fuse_regs *fuse = (struct fuse_regs *)TEGRA2_FUSE_BASE;
-       uint tegra_sku_id, rev;
-
-       /*
-        * This is undocumented, Chip ID is bits 15:8 of the register
-        * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-        * Tegra30
-        */
-       gp = (struct apb_misc_gp_ctlr *)TEGRA2_APB_MISC_GP_BASE;
-       rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
-
-       tegra_sku_id = readl(&fuse->sku_info) & 0xff;
-
-       switch (rev) {
-       case CHIPID_TEGRA2:
-               switch (tegra_sku_id) {
-               case SKU_ID_T20:
-                       return TEGRA_SOC_T20;
-               case SKU_ID_T25SE:
-               case SKU_ID_AP25:
-               case SKU_ID_T25:
-               case SKU_ID_AP25E:
-               case SKU_ID_T25E:
-                       return TEGRA_SOC_T25;
-               }
-               break;
-       }
-       /* unknown sku id */
-       return TEGRA_SOC_UNKNOWN;
-}
+#include "cpu.h"
 
 /* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
-static int ap20_cpu_is_cortexa9(void)
+int ap20_cpu_is_cortexa9(void)
 {
        u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
        return id == (PG_UP_TAG_0_PID_CPU & 0xff);
@@ -77,10 +40,8 @@ static int ap20_cpu_is_cortexa9(void)
 
 void init_pllx(void)
 {
-       struct clk_rst_ctlr *clkrst =
-                       (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-       struct clk_pll_simple *pll =
-               &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
+       struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
        u32 reg;
 
        /* If PLLX is already enabled, just return */
@@ -144,14 +105,14 @@ static void enable_cpu_clock(int enable)
 
 static int is_cpu_powered(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
 
        return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 }
 
 static void remove_cpu_io_clamps(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
        u32 reg;
 
        /* Remove the clamps on the CPU I/O signals */
@@ -165,7 +126,7 @@ static void remove_cpu_io_clamps(void)
 
 static void powerup_cpu(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
        u32 reg;
        int timeout = IO_STABILIZATION_DELAY;
 
@@ -196,7 +157,7 @@ static void powerup_cpu(void)
 
 static void enable_cpu_power_rail(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
        u32 reg;
 
        reg = readl(&pmc->pmc_cntrl);
@@ -295,94 +256,3 @@ void halt_avp(void)
                        FLOW_CTLR_HALT_COP_EVENTS);
        }
 }
-
-void enable_scu(void)
-{
-       struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
-       u32 reg;
-
-       /* If SCU already setup/enabled, return */
-       if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
-               return;
-
-       /* Invalidate all ways for all processors */
-       writel(0xFFFF, &scu->scu_inv_all);
-
-       /* Enable SCU - bit 0 */
-       reg = readl(&scu->scu_ctrl);
-       reg |= SCU_CTRL_ENABLE;
-       writel(reg, &scu->scu_ctrl);
-}
-
-static u32 get_odmdata(void)
-{
-       /*
-        * ODMDATA is stored in the BCT in IRAM by the BootROM.
-        * The BCT start and size are stored in the BIT in IRAM.
-        * Read the data @ bct_start + (bct_size - 12). This works
-        * on T20 and T30 BCTs, which are locked down. If this changes
-        * in new chips (T114, etc.), we can revisit this algorithm.
-        */
-
-       u32 bct_start, odmdata;
-
-       bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
-       odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
-
-       return odmdata;
-}
-
-void init_pmc_scratch(void)
-{
-       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
-       u32 odmdata;
-       int i;
-
-       /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
-       for (i = 0; i < 23; i++)
-               writel(0, &pmc->pmc_scratch1+i);
-
-       /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
-       odmdata = get_odmdata();
-       writel(odmdata, &pmc->pmc_scratch20);
-
-#ifdef CONFIG_TEGRA2_LP0
-       /* save Sdram params to PMC 2, 4, and 24 for WB0 */
-       warmboot_save_sdram_params();
-#endif
-}
-
-void tegra2_start(void)
-{
-       struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
-       /* If we are the AVP, start up the first Cortex-A9 */
-       if (!ap20_cpu_is_cortexa9()) {
-               /* enable JTAG */
-               writel(0xC0, &pmt->pmt_cfg_ctl);
-
-               /*
-                * If we are ARM7 - give it a different stack. We are about to
-                * start up the A9 which will want to use this one.
-                */
-               asm volatile("mov       sp, %0\n"
-                       : : "r"(AVP_EARLY_BOOT_STACK_LIMIT));
-
-               start_cpu((u32)_start);
-               halt_avp();
-               /* not reached */
-       }
-
-       /* Init PMC scratch memory */
-       init_pmc_scratch();
-
-       enable_scu();
-
-       /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
-       asm volatile(
-               "mrc    p15, 0, r0, c1, c0, 1\n"
-               "orr    r0, r0, #0x41\n"
-               "mcr    p15, 0, r0, c1, c0, 1\n");
-
-       /* FIXME: should have ap20's L2 disabled too? */
-}
diff --git a/arch/arm/cpu/arm720t/tegra20/cpu.h b/arch/arm/cpu/arm720t/tegra20/cpu.h
new file mode 100644 (file)
index 0000000..6804cd7
--- /dev/null
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2010-2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/types.h>
+
+/* Stabilization delays, in usec */
+#define PLL_STABILIZATION_DELAY (300)
+#define IO_STABILIZATION_DELAY (1000)
+
+#define NVBL_PLLP_KHZ  (216000)
+
+#define PLLX_ENABLED           (1 << 30)
+#define CCLK_BURST_POLICY      0x20008888
+#define SUPER_CCLK_DIVIDER     0x80000000
+
+/* Calculate clock fractional divider value from ref and target frequencies */
+#define CLK_DIVIDER(REF, FREQ)  ((((REF) * 2) / FREQ) - 2)
+
+/* Calculate clock frequency value from reference and clock divider value */
+#define CLK_FREQUENCY(REF, REG)  (((REF) * 2) / (REG + 2))
+
+/* AVP/CPU ID */
+#define PG_UP_TAG_0_PID_CPU    0x55555555      /* CPU aka "a9" aka "mpcore" */
+#define PG_UP_TAG_0             0x0
+
+#define CORESIGHT_UNLOCK       0xC5ACCE55;
+
+/* AP20-Specific Base Addresses */
+
+/* AP20 Base physical address of SDRAM. */
+#define AP20_BASE_PA_SDRAM      0x00000000
+/* AP20 Base physical address of internal SRAM. */
+#define AP20_BASE_PA_SRAM       0x40000000
+/* AP20 Size of internal SRAM (256KB). */
+#define AP20_BASE_PA_SRAM_SIZE  0x00040000
+/* AP20 Base physical address of flash. */
+#define AP20_BASE_PA_NOR_FLASH  0xD0000000
+/* AP20 Base physical address of boot information table. */
+#define AP20_BASE_PA_BOOT_INFO  AP20_BASE_PA_SRAM
+
+/*
+ * Super-temporary stacks for EXTREMELY early startup. The values chosen for
+ * these addresses must be valid on ALL SOCs because this value is used before
+ * we are able to differentiate between the SOC types.
+ *
+ * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its
+ *       stack is placed below the AVP stack. Once the CPU stack has been moved,
+ *       the AVP is free to use the IRAM the CPU stack previously occupied if
+ *       it should need to do so.
+ *
+ * NOTE: In multi-processor CPU complex configurations, each processor will have
+ *       its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a
+ *       limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a
+ *       stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous
+ *       CPU.
+ */
+
+/* Common AVP early boot stack limit */
+#define AVP_EARLY_BOOT_STACK_LIMIT     \
+       (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2))
+/* Common AVP early boot stack size */
+#define AVP_EARLY_BOOT_STACK_SIZE      0x1000
+/* Common CPU early boot stack limit */
+#define CPU_EARLY_BOOT_STACK_LIMIT     \
+       (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE)
+/* Common CPU early boot stack size */
+#define CPU_EARLY_BOOT_STACK_SIZE      0x1000
+
+#define EXCEP_VECTOR_CPU_RESET_VECTOR  (NV_PA_EVP_BASE + 0x100)
+#define CSITE_CPU_DBG0_LAR             (NV_PA_CSITE_BASE + 0x10FB0)
+#define CSITE_CPU_DBG1_LAR             (NV_PA_CSITE_BASE + 0x12FB0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS      (NV_PA_FLOW_BASE + 4)
+#define FLOW_MODE_STOP                 2
+#define HALT_COP_EVENT_JTAG            (1 << 28)
+#define HALT_COP_EVENT_IRQ_1           (1 << 11)
+#define HALT_COP_EVENT_FIQ_1           (1 << 9)
+
+void start_cpu(u32 reset_vector);
+int ap20_cpu_is_cortexa9(void);
+void halt_avp(void)  __attribute__ ((noreturn));
diff --git a/arch/arm/cpu/arm720t/tegra20/spl.c b/arch/arm/cpu/arm720t/tegra20/spl.c
new file mode 100644 (file)
index 0000000..6c16dce
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ * (C) Copyright 2012
+ * NVIDIA Inc, <www.nvidia.com>
+ *
+ * Allen Martin <amartin@nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/utils.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fat.h>
+#include <version.h>
+#include <i2c.h>
+#include <image.h>
+#include <malloc.h>
+#include <linux/compiler.h>
+#include "board.h"
+#include "cpu.h"
+
+#include <asm/io.h>
+#include <asm/arch/tegra20.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/scu.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+inline void hang(void)
+{
+       puts("### ERROR ### Please RESET the board ###\n");
+       for (;;)
+               ;
+}
+
+void board_init_f(ulong dummy)
+{
+       board_init_uart_f();
+
+       /* Initialize periph GPIOs */
+#ifdef CONFIG_SPI_UART_SWITCH
+       gpio_early_init_uart();
+#else
+       gpio_config_uart();
+#endif
+
+       /*
+        * We call relocate_code() with relocation target same as the
+        * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
+        * skipped. Instead, only .bss initialization will happen. That's
+        * all we need
+        */
+       debug(">>board_init_f()\n");
+       relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+}
+
+/* This requires UART clocks to be enabled */
+static void preloader_console_init(void)
+{
+       const char *u_boot_rev = U_BOOT_VERSION;
+
+       gd = &gdata;
+       gd->bd = &bdata;
+       gd->flags |= GD_FLG_RELOC;
+       gd->baudrate = CONFIG_BAUDRATE;
+
+       serial_init();          /* serial communications setup */
+
+       gd->have_console = 1;
+
+       /* Avoid a second "U-Boot" coming from this string */
+       u_boot_rev = &u_boot_rev[7];
+
+       printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
+               U_BOOT_TIME);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+       struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+
+       /* enable JTAG */
+       writel(0xC0, &pmt->pmt_cfg_ctl);
+
+       debug(">>spl:board_init_r()\n");
+
+       mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+                       CONFIG_SYS_SPL_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_BOARD_INIT
+       spl_board_init();
+#endif
+
+       clock_early_init();
+       serial_init();
+       preloader_console_init();
+
+       start_cpu((u32)CONFIG_SYS_TEXT_BASE);
+       halt_avp();
+       /* not reached */
+}
+
+int board_usb_init(const void *blob)
+{
+       return 0;
+}
index f333753..346e58f 100644 (file)
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_AT91SAM9263)   += at91sam9263_devices.o
 COBJS-$(CONFIG_AT91SAM9RL)     += at91sam9rl_devices.o
 COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
 COBJS-$(CONFIG_AT91SAM9G45)    += at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9X5)     += at91sam9x5_devices.o
 COBJS-$(CONFIG_AT91_EFLASH)    += eflash.o
 COBJS-$(CONFIG_AT91_LED)       += led.o
 COBJS-y += clock.o
index 62f76fa..19ec615 100644 (file)
@@ -158,6 +158,10 @@ void at91_spi1_hw_init(unsigned long cs_mask)
 #ifdef CONFIG_MACB
 void at91_macb_hw_init(void)
 {
+       /* Enable EMAC clock */
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
        at91_set_a_periph(AT91_PIO_PORTA, 19, 0);       /* ETXCK_EREFCK */
        at91_set_a_periph(AT91_PIO_PORTA, 17, 0);       /* ERXDV */
        at91_set_a_periph(AT91_PIO_PORTA, 14, 0);       /* ERX0 */
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
new file mode 100644 (file)
index 0000000..6d77219
--- /dev/null
@@ -0,0 +1,232 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+
+unsigned int get_chip_id(void)
+{
+       /* The 0x40 is the offset of cidr in DBGU */
+       return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+       /* The 0x44 is the offset of exid in DBGU */
+       return readl(ATMEL_BASE_DBGU + 0x44);
+}
+
+unsigned int has_emac1()
+{
+       return cpu_is_at91sam9x25();
+}
+
+unsigned int has_emac0()
+{
+       return !(cpu_is_at91sam9g15());
+}
+
+unsigned int has_lcdc()
+{
+       return cpu_is_at91sam9g15() || cpu_is_at91sam9g35()
+               || cpu_is_at91sam9x35();
+}
+
+char *get_cpu_name()
+{
+       unsigned int extension_id = get_extension_chip_id();
+
+       if (cpu_is_at91sam9x5()) {
+               switch (extension_id) {
+               case ARCH_EXID_AT91SAM9G15:
+                       return CONFIG_SYS_AT91_G15_CPU_NAME;
+               case ARCH_EXID_AT91SAM9G25:
+                       return CONFIG_SYS_AT91_G25_CPU_NAME;
+               case ARCH_EXID_AT91SAM9G35:
+                       return CONFIG_SYS_AT91_G35_CPU_NAME;
+               case ARCH_EXID_AT91SAM9X25:
+                       return CONFIG_SYS_AT91_X25_CPU_NAME;
+               case ARCH_EXID_AT91SAM9X35:
+                       return CONFIG_SYS_AT91_X35_CPU_NAME;
+               default:
+                       return CONFIG_SYS_AT91_UNKNOWN_CPU;
+               }
+       } else {
+               return CONFIG_SYS_AT91_UNKNOWN_CPU;
+       }
+}
+
+void at91_seriald_hw_init(void)
+{
+       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 9, 0);        /* DRXD */
+       at91_set_a_periph(AT91_PIO_PORTA, 10, 1);       /* DTXD */
+
+       writel(1 << ATMEL_ID_SYS, &pmc->pcer);
+}
+
+void at91_serial0_hw_init(void)
+{
+       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 0, 1);        /* TXD */
+       at91_set_a_periph(AT91_PIO_PORTA, 1, 0);        /* RXD */
+
+       writel(1 << ATMEL_ID_USART0, &pmc->pcer);
+}
+
+void at91_serial1_hw_init(void)
+{
+       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 5, 1);        /* TXD */
+       at91_set_a_periph(AT91_PIO_PORTA, 6, 0);        /* RXD */
+
+       writel(1 << ATMEL_ID_USART1, &pmc->pcer);
+}
+
+void at91_serial2_hw_init(void)
+{
+       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 7, 1);        /* TXD */
+       at91_set_a_periph(AT91_PIO_PORTA, 8, 0);        /* RXD */
+
+       writel(1 << ATMEL_ID_USART2, &pmc->pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 11, 0);       /* SPI0_MISO */
+       at91_set_a_periph(AT91_PIO_PORTA, 12, 0);       /* SPI0_MOSI */
+       at91_set_a_periph(AT91_PIO_PORTA, 13, 0);       /* SPI0_SPCK */
+
+       /* Enable clock */
+       writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
+
+       if (cs_mask & (1 << 0))
+               at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
+       if (cs_mask & (1 << 1))
+               at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
+       if (cs_mask & (1 << 2))
+               at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
+       if (cs_mask & (1 << 3))
+               at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
+       if (cs_mask & (1 << 4))
+               at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
+       if (cs_mask & (1 << 5))
+               at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
+       if (cs_mask & (1 << 6))
+               at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
+       if (cs_mask & (1 << 7))
+               at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+       at91_set_b_periph(AT91_PIO_PORTA, 21, 0);       /* SPI1_MISO */
+       at91_set_b_periph(AT91_PIO_PORTA, 22, 0);       /* SPI1_MOSI */
+       at91_set_b_periph(AT91_PIO_PORTA, 23, 0);       /* SPI1_SPCK */
+
+       /* Enable clock */
+       writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
+
+       if (cs_mask & (1 << 0))
+               at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
+       if (cs_mask & (1 << 1))
+               at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
+       if (cs_mask & (1 << 2))
+               at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
+       if (cs_mask & (1 << 3))
+               at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
+       if (cs_mask & (1 << 4))
+               at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
+       if (cs_mask & (1 << 5))
+               at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
+       if (cs_mask & (1 << 6))
+               at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
+       if (cs_mask & (1 << 7))
+               at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+       at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
+
+       if (has_emac0()) {
+               /* Enable EMAC0 clock */
+               writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+               /* EMAC0 pins setup */
+               at91_set_a_periph(AT91_PIO_PORTB, 4, 0);        /* ETXCK */
+               at91_set_a_periph(AT91_PIO_PORTB, 3, 0);        /* ERXDV */
+               at91_set_a_periph(AT91_PIO_PORTB, 0, 0);        /* ERX0 */
+               at91_set_a_periph(AT91_PIO_PORTB, 1, 0);        /* ERX1 */
+               at91_set_a_periph(AT91_PIO_PORTB, 2, 0);        /* ERXER */
+               at91_set_a_periph(AT91_PIO_PORTB, 7, 0);        /* ETXEN */
+               at91_set_a_periph(AT91_PIO_PORTB, 9, 0);        /* ETX0 */
+               at91_set_a_periph(AT91_PIO_PORTB, 10, 0);       /* ETX1 */
+               at91_set_a_periph(AT91_PIO_PORTB, 5, 0);        /* EMDIO */
+               at91_set_a_periph(AT91_PIO_PORTB, 6, 0);        /* EMDC */
+       }
+
+       if (has_emac1()) {
+               /* Enable EMAC1 clock */
+               writel(1 << ATMEL_ID_EMAC1, &pmc->pcer);
+               /* EMAC1 pins setup */
+               at91_set_b_periph(AT91_PIO_PORTC, 29, 0);       /* ETXCK */
+               at91_set_b_periph(AT91_PIO_PORTC, 28, 0);       /* ECRSDV */
+               at91_set_b_periph(AT91_PIO_PORTC, 20, 0);       /* ERXO */
+               at91_set_b_periph(AT91_PIO_PORTC, 21, 0);       /* ERX1 */
+               at91_set_b_periph(AT91_PIO_PORTC, 16, 0);       /* ERXER */
+               at91_set_b_periph(AT91_PIO_PORTC, 27, 0);       /* ETXEN */
+               at91_set_b_periph(AT91_PIO_PORTC, 18, 0);       /* ETX0 */
+               at91_set_b_periph(AT91_PIO_PORTC, 19, 0);       /* ETX1 */
+               at91_set_b_periph(AT91_PIO_PORTC, 31, 0);       /* EMDIO */
+               at91_set_b_periph(AT91_PIO_PORTC, 30, 0);       /* EMDC */
+       }
+
+#ifndef CONFIG_RMII
+       /* Only emac0 support MII */
+       if (has_emac0()) {
+               at91_set_b_periph(AT91_PIO_PORTB, 16, 0);       /* ECRS */
+               at91_set_b_periph(AT91_PIO_PORTB, 17, 0);       /* ECOL */
+               at91_set_b_periph(AT91_PIO_PORTB, 13, 0);       /* ERX2 */
+               at91_set_b_periph(AT91_PIO_PORTB, 14, 0);       /* ERX3 */
+               at91_set_b_periph(AT91_PIO_PORTB, 15, 0);       /* ERXCK */
+               at91_set_b_periph(AT91_PIO_PORTB, 11, 0);       /* ETX2 */
+               at91_set_b_periph(AT91_PIO_PORTB, 12, 0);       /* ETX3 */
+               at91_set_b_periph(AT91_PIO_PORTB, 8, 0);        /* ETXER */
+       }
+#endif
+}
+#endif
index a7085de..dc5c6c4 100644 (file)
@@ -154,7 +154,8 @@ int at91_clock_init(unsigned long main_clock)
         * For now, assume this parentage won't change.
         */
        mckr = readl(&pmc->mckr);
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+               || defined(CONFIG_AT91SAM9X5)
        /* plla divisor by 2 */
        gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
 #endif
@@ -168,7 +169,14 @@ int at91_clock_init(unsigned long main_clock)
                freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
        if (mckr & AT91_PMC_MCKR_MDIV_MASK)
                freq /= 2;                      /* processor clock division */
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+               || defined(CONFIG_AT91SAM9X5)
+       /* mdiv <==> divisor
+        *  0   <==>   1
+        *  1   <==>   2
+        *  2   <==>   4
+        *  3   <==>   3
+        */
        gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
                (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
                ? freq / 3
index c47fb31..5cf4fad 100644 (file)
@@ -71,29 +71,3 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
-/*
- * We combine the BOOTCOUNT_MAGIC and bootcount in one 32-bit register.
- * This is done so we need to use only one of the four GPBR registers.
- */
-void bootcount_store (ulong a)
-{
-       at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
-
-       writel((BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff),
-               &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
-}
-
-ulong bootcount_load (void)
-{
-       at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
-
-       ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]);
-       if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
-               return 0;
-       else
-               return val & 0x0000ffff;
-}
-
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
index da7efac..c91928e 100644 (file)
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS-y                                += cpu.o misc.o timer.o psc.o pinmux.o
+COBJS-y                                += cpu.o misc.o timer.o psc.o pinmux.o reset.o
 COBJS-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
 COBJS-$(CONFIG_SOC_DM355)      += dm355.o
 COBJS-$(CONFIG_SOC_DM365)      += dm365.o
@@ -42,8 +42,6 @@ COBJS-$(CONFIG_SOC_DM365)     += dm365_lowlevel.o
 COBJS-$(CONFIG_SOC_DA8XX)      += da850_lowlevel.o
 endif
 
-SOBJS  = reset.o
-
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 SOBJS  += lowlevel_init.o
 endif
index 6cb857a..b31add8 100644 (file)
@@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id)
 out:
        return pll_out;
 }
+
+int set_cpu_clk_info(void)
+{
+       gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
+       /* DDR PHY uses an x2 input clock */
+       gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
+                               (clk_get(DAVINCI_DDR_CLKID) / 1000000);
+       gd->bd->bi_dsp_freq = 0;
+       return 0;
+}
+
 #else /* CONFIG_SOC_DA8XX */
 
 static unsigned pll_div(volatile void *pllbase, unsigned offset)
@@ -187,16 +198,9 @@ unsigned int davinci_clk_get(unsigned int div)
        return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000;
 }
 #endif
-#endif /* !CONFIG_SOC_DA8XX */
 
 int set_cpu_clk_info(void)
 {
-#ifdef CONFIG_SOC_DA8XX
-       gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
-       /* DDR PHY uses an x2 input clock */
-       gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000;
-#else
-
        unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE;
 #if defined(CONFIG_SOC_DM365)
        pllbase = DAVINCI_PLL_CNTRL1_BASE;
@@ -215,10 +219,12 @@ int set_cpu_clk_info(void)
        pllbase = DAVINCI_PLL_CNTRL0_BASE;
 #endif
        gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2;
-#endif
+
        return 0;
 }
 
+#endif /* !CONFIG_SOC_DA8XX */
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
index df7d6a2..ff2e2e3 100644 (file)
@@ -190,13 +190,21 @@ int da850_ddr_setup(void)
 
                setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
                setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
-
-               setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
        }
-
+       setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
        writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
-       clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
-               (1 << DDR_SLEW_CMOSEN_BIT));
+
+       if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
+               /* DDR2 */
+               clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
+                       (1 << DDR_SLEW_DDR_PDENA_BIT) |
+                       (1 << DDR_SLEW_CMOSEN_BIT));
+       } else {
+               /* MOBILE DDR */
+               setbits_le32(&davinci_syscfg1_regs->ddr_slew,
+                       (1 << DDR_SLEW_DDR_PDENA_BIT) |
+                       (1 << DDR_SLEW_CMOSEN_BIT));
+       }
 
        /*
         * SDRAM Configuration Register (SDCR):
@@ -216,7 +224,11 @@ int da850_ddr_setup(void)
        writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
 
        /* write memory configuration and timing */
-       writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
+       if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
+               /* MOBILE DDR only*/
+               writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+                       &dv_ddr2_regs_ctrl->sdbcr2);
+       }
        writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
        writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
 
@@ -240,7 +252,7 @@ int da850_ddr_setup(void)
 
        /* disable self refresh */
        clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
-               DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+               DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
        writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
 
        return 0;
index fa07fb5..133265e 100644 (file)
@@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = {
 };
 
 /* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+       { pinmux(3), 2, 4 }, /* UART0_RXD */
+       { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
 const struct pinmux_config uart1_pins_txrx[] = {
        { pinmux(4), 2, 6 }, /* UART1_RXD */
        { pinmux(4), 2, 7 }, /* UART1_TXD */
@@ -169,3 +174,14 @@ const struct pinmux_config emifa_pins_nor[] = {
        { pinmux(12), 1, 6 }, /* EMA_A[1] */
        { pinmux(12), 1, 7 }, /* EMA_A[0] */
 };
+
+/* MMC0 pin muxer settings */
+const struct pinmux_config mmc0_pins[] = {
+       { pinmux(10), 2, 0 },   /* MMCSD0_CLK */
+       { pinmux(10), 2, 1 },   /* MMCSD0_CMD */
+       { pinmux(10), 2, 2 },   /* MMCSD0_DAT_0 */
+       { pinmux(10), 2, 3 },   /* MMCSD0_DAT_1 */
+       { pinmux(10), 2, 4 },   /* MMCSD0_DAT_2 */
+       { pinmux(10), 2, 5 },   /* MMCSD0_DAT_3 */
+       /* DA850 supports only 4-bit mode, remaining pins are not configured */
+};
index 3e92518..2ffb42a 100644 (file)
@@ -128,6 +128,11 @@ void lpsc_syncreset(unsigned int id)
        lpsc_transition(id, 0x01);
 }
 
+void lpsc_disable(unsigned int id)
+{
+       lpsc_transition(id, 0x0);
+}
+
 /* Not all DaVinci chips have a DSP power domain. */
 #ifdef CONFIG_SOC_DM644X
 
diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.S b/arch/arm/cpu/arm926ejs/davinci/reset.S
deleted file mode 100644 (file)
index ba0a7c3..0000000
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Processor reset using WDT for TI TMS320DM644x SoC.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * -----------------------------------------------------
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-.globl reset_cpu
-reset_cpu:
-       ldr     r0, WDT_TGCR
-       mov     r1, $0x08
-       str     r1, [r0]
-       ldr     r1, [r0]
-       orr     r1, r1, $0x03
-       str     r1, [r0]
-       mov     r1, $0
-       ldr     r0, WDT_TIM12
-       str     r1, [r0]
-       ldr     r0, WDT_TIM34
-       str     r1, [r0]
-       ldr     r0, WDT_PRD12
-       str     r1, [r0]
-       ldr     r0, WDT_PRD34
-       str     r1, [r0]
-       ldr     r0, WDT_TCR
-       ldr     r1, [r0]
-       orr     r1, r1, $0x40
-       str     r1, [r0]
-       ldr     r0, WDT_WDTCR
-       ldr     r1, [r0]
-       orr     r1, r1, $0x4000
-       str     r1, [r0]
-       ldr     r1, WDTCR_VAL1
-       str     r1, [r0]
-       ldr     r1, WDTCR_VAL2
-       str     r1, [r0]
-       /* Write an invalid value to the WDKEY field to trigger
-        * an immediate watchdog reset */
-       mov     r1, $0x4000
-       str     r1, [r0]
-       nop
-       nop
-       nop
-       nop
-reset_cpu_loop:
-       b       reset_cpu_loop
-
-WDT_TGCR:
-       .word   0x01c21c24
-WDT_TIM12:
-       .word   0x01c21c10
-WDT_TIM34:
-       .word   0x01c21c14
-WDT_PRD12:
-       .word   0x01c21c18
-WDT_PRD34:
-       .word   0x01c21c1c
-WDT_TCR:
-       .word   0x01c21c20
-WDT_WDTCR:
-       .word   0x01c21c28
-WDTCR_VAL1:
-       .word   0xa5c64000
-WDTCR_VAL2:
-       .word   0xda7e4000
diff --git a/arch/arm/cpu/arm926ejs/davinci/reset.c b/arch/arm/cpu/arm926ejs/davinci/reset.c
new file mode 100644 (file)
index 0000000..968fb03
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ *  Processor reset using WDT.
+ *
+ * Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * This file is released under the terms of GPL v2 and any later version.
+ * See the file COPYING in the root directory of the source tree for details.
+*/
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer_defs.h>
+#include <asm/arch/hardware.h>
+
+void reset_cpu(unsigned long a)
+{
+       struct davinci_timer *const wdttimer =
+               (struct davinci_timer *)DAVINCI_TIMER1_BASE;
+       writel(0x08, &wdttimer->tgcr);
+       writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
+       writel(0, &wdttimer->tim12);
+       writel(0, &wdttimer->tim34);
+       writel(0, &wdttimer->prd12);
+       writel(0, &wdttimer->prd34);
+       writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
+       writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
+       writel(0xa5c64000, &wdttimer->wdtcr);
+       writel(0xda7e4000, &wdttimer->wdtcr);
+       writel(0x4000, &wdttimer->wdtcr);
+       while (1)
+               /*nothing*/;
+}
index 74632e5..03c85c8 100644 (file)
@@ -28,6 +28,7 @@
 #include <ns16550.h>
 #include <malloc.h>
 #include <spi_flash.h>
+#include <mmc.h>
 
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 
@@ -74,12 +75,7 @@ void board_init_f(ulong dummy)
 
 void board_init_r(gd_t *id, ulong dummy)
 {
-#ifdef CONFIG_SPL_NAND_LOAD
-       nand_init();
-       puts("Nand boot...\n");
-       nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
        mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
                        CONFIG_SYS_MALLOC_LEN);
 
@@ -90,7 +86,19 @@ void board_init_r(gd_t *id, ulong dummy)
        serial_init();          /* serial communications setup */
        gd->have_console = 1;
 
+#endif
+
+#ifdef CONFIG_SPL_NAND_LOAD
+       nand_init();
+       puts("Nand boot...\n");
+       nand_boot();
+#endif
+#ifdef CONFIG_SPL_SPI_LOAD
        puts("SPI boot...\n");
        spi_boot();
 #endif
+#ifdef CONFIG_SPL_MMC_LOAD
+       puts("MMC boot...\n");
+       spl_mmc_load();
+#endif
 }
index 8b07dae..a412a8f 100644 (file)
@@ -186,6 +186,14 @@ int print_cpuinfo(void)
 }
 #endif
 
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+#endif
+}
+
 int cpu_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FEC_MXC)
index 65c4813..41bb84b 100644 (file)
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
 #ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif
@@ -209,7 +210,7 @@ int cpu_mmc_init(bd_t *bis)
 
 void imx_gpio_mode(int gpio_mode)
 {
-       struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
+       struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
        unsigned int pin = gpio_mode & GPIO_PIN_MASK;
        unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
        unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
@@ -228,11 +229,11 @@ void imx_gpio_mode(int gpio_mode)
 
        /* Data direction */
        if (gpio_mode & GPIO_OUT) {
-               writel(readl(&regs->port[port].ddir) | 1 << pin,
-                               &regs->port[port].ddir);
+               writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
+                               &regs->port[port].gpio_dir);
        } else {
-               writel(readl(&regs->port[port].ddir) & ~(1 << pin),
-                               &regs->port[port].ddir);
+               writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
+                               &regs->port[port].gpio_dir);
        }
 
        /* Primary / alternate function */
similarity index 97%
rename from arch/arm/cpu/arm926ejs/mx28/Makefile
rename to arch/arm/cpu/arm926ejs/mxs/Makefile
index 674a3af..eeecf89 100644 (file)
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS  = clock.o mx28.o iomux.o timer.o
+COBJS  = clock.o mxs.o iomux.o timer.o
 
 ifdef  CONFIG_SPL_BUILD
 COBJS  += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
similarity index 89%
rename from arch/arm/cpu/arm926ejs/mx28/clock.c
rename to arch/arm/cpu/arm926ejs/mxs/clock.c
index 0439f9c..bfea6ab 100644 (file)
@@ -43,8 +43,8 @@
 
 static uint32_t mx28_get_pclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -75,8 +75,8 @@ static uint32_t mx28_get_pclk(void)
 
 static uint32_t mx28_get_hclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t div;
        uint32_t clkctrl;
@@ -93,8 +93,8 @@ static uint32_t mx28_get_hclk(void)
 
 static uint32_t mx28_get_emiclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -118,8 +118,8 @@ static uint32_t mx28_get_emiclk(void)
 
 static uint32_t mx28_get_gpmiclk(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        uint32_t clkctrl, clkseq, div;
        uint8_t clkfrac, frac;
@@ -145,8 +145,8 @@ static uint32_t mx28_get_gpmiclk(void)
  */
 void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t div;
        int io_reg;
 
@@ -178,8 +178,8 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
  */
 static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint8_t ret;
        int io_reg;
 
@@ -199,15 +199,15 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
  */
 void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t clk, clkreg;
 
        if (ssp > MXC_SSPCLK3)
                return;
 
        clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-                       (ssp * sizeof(struct mx28_register_32));
+                       (ssp * sizeof(struct mxs_register_32));
 
        clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
        while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
@@ -243,8 +243,8 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
  */
 static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        uint32_t clkreg;
        uint32_t clk, tmp;
 
@@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
                return XTAL_FREQ_KHZ;
 
        clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
-                       (ssp * sizeof(struct mx28_register_32));
+                       (ssp * sizeof(struct mxs_register_32));
 
        tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
 
@@ -273,12 +273,12 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
  */
 void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
 {
-       struct mx28_ssp_regs *ssp_regs;
+       struct mxs_ssp_regs *ssp_regs;
        const uint32_t sspclk = mx28_get_sspclk(bus);
        uint32_t reg;
        uint32_t divide, rate, tgtclk;
 
-       ssp_regs = (struct mx28_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
+       ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
 
        /*
         * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
similarity index 94%
rename from arch/arm/cpu/arm926ejs/mx28/iomux.c
rename to arch/arm/cpu/arm926ejs/mxs/iomux.c
index 12916b6..73f1446 100644 (file)
@@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
 {
        u32 reg, ofs, bp, bm;
        void *iomux_base = (void *)MXS_PINCTRL_BASE;
-       struct mx28_register_32 *mxs_reg;
+       struct mxs_register_32 *mxs_reg;
 
        /* muxsel */
        ofs = 0x100;
@@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
        /* vol */
        if (PAD_VOL_VALID(pad)) {
                bp = PAD_PIN(pad) % 8 * 4 + 2;
-               mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+               mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
                if (PAD_VOL(pad))
                        writel(1 << bp, &mxs_reg->reg_set);
                else
@@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
                ofs = PULL_OFFSET;
                ofs += PAD_BANK(pad) * 0x10;
                bp = PAD_PIN(pad);
-               mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
+               mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
                if (PAD_PULL(pad))
                        writel(1 << bp, &mxs_reg->reg_set);
                else
similarity index 69%
rename from arch/arm/cpu/arm926ejs/mx28/mx28.c
rename to arch/arm/cpu/arm926ejs/mxs/mxs.c
index ff25772..6ce8019 100644 (file)
@@ -41,8 +41,8 @@ DECLARE_GLOBAL_DATA_PTR;
 /* 1 second delay should be plenty of time for block reset. */
 #define        RESET_MAX_TIMEOUT       1000000
 
-#define        MX28_BLOCK_SFTRST       (1 << 31)
-#define        MX28_BLOCK_CLKGATE      (1 << 30)
+#define        MXS_BLOCK_SFTRST        (1 << 31)
+#define        MXS_BLOCK_CLKGATE       (1 << 30)
 
 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
 inline void lowlevel_init(void) {}
@@ -51,10 +51,10 @@ void reset_cpu(ulong ignored) __attribute__((noreturn));
 
 void reset_cpu(ulong ignored)
 {
-       struct mx28_rtc_regs *rtc_regs =
-               (struct mx28_rtc_regs *)MXS_RTC_BASE;
-       struct mx28_lcdif_regs *lcdif_regs =
-               (struct mx28_lcdif_regs *)MXS_LCDIF_BASE;
+       struct mxs_rtc_regs *rtc_regs =
+               (struct mxs_rtc_regs *)MXS_RTC_BASE;
+       struct mxs_lcdif_regs *lcdif_regs =
+               (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 
        /*
         * Shut down the LCD controller as it interferes with BootROM boot mode
@@ -81,7 +81,8 @@ void enable_caches(void)
 #endif
 }
 
-int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
+                                                               int timeout)
 {
        while (--timeout) {
                if ((readl(&reg->reg) & mask) == mask)
@@ -92,7 +93,8 @@ int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
        return !timeout;
 }
 
-int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
+int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
+                                                               int timeout)
 {
        while (--timeout) {
                if ((readl(&reg->reg) & mask) == 0)
@@ -103,34 +105,34 @@ int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
        return !timeout;
 }
 
-int mx28_reset_block(struct mx28_register_32 *reg)
+int mxs_reset_block(struct mxs_register_32 *reg)
 {
        /* Clear SFTRST */
-       writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+       writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
 
-       if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
                return 1;
 
        /* Clear CLKGATE */
-       writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+       writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
 
        /* Set SFTRST */
-       writel(MX28_BLOCK_SFTRST, &reg->reg_set);
+       writel(MXS_BLOCK_SFTRST, &reg->reg_set);
 
        /* Wait for CLKGATE being set */
-       if (mx28_wait_mask_set(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
                return 1;
 
        /* Clear SFTRST */
-       writel(MX28_BLOCK_SFTRST, &reg->reg_clr);
+       writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
 
-       if (mx28_wait_mask_clr(reg, MX28_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
                return 1;
 
        /* Clear CLKGATE */
-       writel(MX28_BLOCK_CLKGATE, &reg->reg_clr);
+       writel(MXS_BLOCK_CLKGATE, &reg->reg_clr);
 
-       if (mx28_wait_mask_clr(reg, MX28_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
+       if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
                return 1;
 
        return 0;
@@ -155,8 +157,8 @@ int arch_misc_init(void)
 
 int arch_cpu_init(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
        extern uint32_t _start;
 
        mx28_fixup_vt((uint32_t)&_start);
@@ -188,14 +190,48 @@ int arch_cpu_init(void)
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
+static const char *get_cpu_type(void)
 {
-       struct mx28_spl_data *data = (struct mx28_spl_data *)
-               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+       struct mxs_digctl_regs *digctl_regs =
+               (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+       switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+       case HW_DIGCTL_CHIPID_MX28:
+               return "28";
+       default:
+               return "??";
+       }
+}
 
-       printf("Freescale i.MX28 family at %d MHz\n",
-                       mxc_get_clock(MXC_ARM_CLK) / 1000000);
-       printf("BOOT:  %s\n", mx28_boot_modes[data->boot_mode_idx].mode);
+static const char *get_cpu_rev(void)
+{
+       struct mxs_digctl_regs *digctl_regs =
+               (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+       uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
+
+       switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
+       case HW_DIGCTL_CHIPID_MX28:
+               switch (rev) {
+               case 0x1:
+                       return "1.2";
+               default:
+                       return "??";
+               }
+       default:
+               return "??";
+       }
+}
+
+int print_cpuinfo(void)
+{
+       struct mxs_spl_data *data = (struct mxs_spl_data *)
+               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+
+       printf("CPU:   Freescale i.MX%s rev%s at %d MHz\n",
+               get_cpu_type(),
+               get_cpu_rev(),
+               mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("BOOT:  %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
        return 0;
 }
 #endif
@@ -212,11 +248,11 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 /*
  * Initializes on-chip ethernet controllers.
  */
-#ifdef CONFIG_CMD_NET
+#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
 int cpu_eth_init(bd_t *bis)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        /* Turn on ENET clocks */
        clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
@@ -257,15 +293,15 @@ void mx28_adjust_mac(int dev_id, unsigned char *mac)
 #define        MXS_OCOTP_MAX_TIMEOUT   1000000
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {
-       struct mx28_ocotp_regs *ocotp_regs =
-               (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+       struct mxs_ocotp_regs *ocotp_regs =
+               (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
        uint32_t data;
 
        memset(mac, 0, 6);
 
        writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
 
-       if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+       if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
                                MXS_OCOTP_MAX_TIMEOUT)) {
                printf("MXS FEC: Can't get MAC from OCOTP\n");
                return;
@@ -286,13 +322,13 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif
 
-int mx28_dram_init(void)
+int mxs_dram_init(void)
 {
-       struct mx28_spl_data *data = (struct mx28_spl_data *)
-               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
+       struct mxs_spl_data *data = (struct mxs_spl_data *)
+               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
 
        if (data->mem_dram_size == 0) {
-               printf("MX28:\n"
+               printf("MXS:\n"
                        "Error, the RAM size passed up from SPL is 0!\n");
                hang();
        }
similarity index 81%
rename from arch/arm/cpu/arm926ejs/mx28/mx28_init.h
rename to arch/arm/cpu/arm926ejs/mxs/mxs_init.h
index e3a4493..2ddc5bc 100644 (file)
 
 void early_delay(int delay);
 
-void mx28_power_init(void);
+void mxs_power_init(void);
 
 #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void);
+void mxs_power_wait_pswitch(void);
 #else
-static inline void mx28_power_wait_pswitch(void) { }
+static inline void mxs_power_wait_pswitch(void) { }
 #endif
 
-void mx28_mem_init(void);
-uint32_t mx28_mem_get_size(void);
+void mxs_mem_init(void);
+uint32_t mxs_mem_get_size(void);
 
-void mx28_lradc_init(void);
-void mx28_lradc_enable_batt_measurement(void);
+void mxs_lradc_init(void);
+void mxs_lradc_enable_batt_measurement(void);
 
 #endif /* __M28_INIT_H__ */
similarity index 85%
rename from arch/arm/cpu/arm926ejs/mx28/spl_boot.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index a6dfca3..ddafddb 100644 (file)
 #include <common.h>
 #include <config.h>
 #include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
 /*
  * This delay function is intended to be used only in early stage of boot, where
@@ -58,7 +57,7 @@ const iomux_cfg_t iomux_boot[] = {
        MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
 };
 
-uint8_t mx28_get_bootmode_index(void)
+uint8_t mxs_get_bootmode_index(void)
 {
        uint8_t bootmode = 0;
        int i;
@@ -83,31 +82,31 @@ uint8_t mx28_get_bootmode_index(void)
        bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
        bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
 
-       for (i = 0; i < ARRAY_SIZE(mx28_boot_modes); i++) {
-               masked = bootmode & mx28_boot_modes[i].boot_mask;
-               if (masked == mx28_boot_modes[i].boot_pads)
+       for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
+               masked = bootmode & mxs_boot_modes[i].boot_mask;
+               if (masked == mxs_boot_modes[i].boot_pads)
                        break;
        }
 
        return i;
 }
 
-void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
+void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
                        const unsigned int iomux_size)
 {
-       struct mx28_spl_data *data = (struct mx28_spl_data *)
-               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mx28_spl_data)) & ~0xf);
-       uint8_t bootmode = mx28_get_bootmode_index();
+       struct mxs_spl_data *data = (struct mxs_spl_data *)
+               ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+       uint8_t bootmode = mxs_get_bootmode_index();
 
        mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
-       mx28_power_init();
+       mxs_power_init();
 
-       mx28_mem_init();
-       data->mem_dram_size = mx28_mem_get_size();
+       mxs_mem_init();
+       data->mem_dram_size = mxs_mem_get_size();
 
        data->boot_mode_idx = bootmode;
 
-       mx28_power_wait_pswitch();
+       mxs_power_wait_pswitch();
 }
 
 /* Support aparatus */
similarity index 91%
rename from arch/arm/cpu/arm926ejs/mx28/spl_lradc_init.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
index 88a603c..d90f0a1 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
-void mx28_lradc_init(void)
+void mxs_lradc_init(void)
 {
-       struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+       struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
        writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
        writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
@@ -49,9 +49,9 @@ void mx28_lradc_init(void)
                        LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
 }
 
-void mx28_lradc_enable_batt_measurement(void)
+void mxs_lradc_enable_batt_measurement(void)
 {
-       struct mx28_lradc_regs *regs = (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+       struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
        /* Check if the channel is present at all. */
        if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
similarity index 83%
rename from arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index e17a4d7..e693145 100644 (file)
 #include <common.h>
 #include <config.h>
 #include <asm/io.h>
-#include <asm/arch/iomux-mx28.h>
 #include <asm/arch/imx-regs.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
-uint32_t dram_vals[] = {
+static uint32_t mx28_dram_vals[] = {
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -82,26 +81,26 @@ uint32_t dram_vals[] = {
        0x00000000, 0x00010001
 };
 
-void __mx28_adjust_memory_params(uint32_t *dram_vals)
+void __mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
-void mx28_adjust_memory_params(uint32_t *dram_vals)
-       __attribute__((weak, alias("__mx28_adjust_memory_params")));
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+       __attribute__((weak, alias("__mxs_adjust_memory_params")));
 
-void init_m28_200mhz_ddr2(void)
+void init_mx28_200mhz_ddr2(void)
 {
        int i;
 
-       mx28_adjust_memory_params(dram_vals);
+       mxs_adjust_memory_params(mx28_dram_vals);
 
-       for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
-               writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+       for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
+               writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
 
-void mx28_mem_init_clock(void)
+void mxs_mem_init_clock(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        /* Gate EMI clock */
        writeb(CLKCTRL_FRAC_CLKGATE,
@@ -129,10 +128,10 @@ void mx28_mem_init_clock(void)
        early_delay(10000);
 }
 
-void mx28_mem_setup_cpu_and_hbus(void)
+void mxs_mem_setup_cpu_and_hbus(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        /* Set fractional divider for ref_cpu to 480 * 18 / 19 = 454MHz
         * and ungate CPU clock */
@@ -161,10 +160,10 @@ void mx28_mem_setup_cpu_and_hbus(void)
        early_delay(15000);
 }
 
-void mx28_mem_setup_vdda(void)
+void mxs_mem_setup_vdda(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
                (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
@@ -172,10 +171,10 @@ void mx28_mem_setup_vdda(void)
                &power_regs->hw_power_vddactrl);
 }
 
-void mx28_mem_setup_vddd(void)
+void mxs_mem_setup_vddd(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
                (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
@@ -183,7 +182,7 @@ void mx28_mem_setup_vddd(void)
                &power_regs->hw_power_vdddctrl);
 }
 
-uint32_t mx28_mem_get_size(void)
+uint32_t mxs_mem_get_size(void)
 {
        uint32_t sz, da;
        uint32_t *vt = (uint32_t *)0x20;
@@ -202,12 +201,12 @@ uint32_t mx28_mem_get_size(void)
        return sz;
 }
 
-void mx28_mem_init(void)
+void mxs_mem_init(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
-       struct mx28_pinctrl_regs *pinctrl_regs =
-               (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_pinctrl_regs *pinctrl_regs =
+               (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
 
        /* Set DDR2 mode */
        writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
@@ -219,9 +218,9 @@ void mx28_mem_init(void)
 
        early_delay(11000);
 
-       mx28_mem_init_clock();
+       mxs_mem_init_clock();
 
-       mx28_mem_setup_vdda();
+       mxs_mem_setup_vdda();
 
        /*
         * Configure the DRAM registers
@@ -230,7 +229,7 @@ void mx28_mem_init(void)
        /* Clear START bit from DRAM_CTL16 */
        clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
 
-       init_m28_200mhz_ddr2();
+       init_mx28_200mhz_ddr2();
 
        /* Clear SREFRESH bit from DRAM_CTL17 */
        clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
@@ -242,9 +241,9 @@ void mx28_mem_init(void)
        while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
                ;
 
-       mx28_mem_setup_vddd();
+       mxs_mem_setup_vddd();
 
        early_delay(10000);
 
-       mx28_mem_setup_cpu_and_hbus();
+       mxs_mem_setup_cpu_and_hbus();
 }
similarity index 81%
rename from arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
rename to arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 4b09b0c..4b917bd 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 
-#include "mx28_init.h"
+#include "mxs_init.h"
 
-void mx28_power_clock2xtal(void)
+void mxs_power_clock2xtal(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        /* Set XTAL as CPU reference clock */
        writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
                &clkctrl_regs->hw_clkctrl_clkseq_set);
 }
 
-void mx28_power_clock2pll(void)
+void mxs_power_clock2pll(void)
 {
-       struct mx28_clkctrl_regs *clkctrl_regs =
-               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct mxs_clkctrl_regs *clkctrl_regs =
+               (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 
        setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
                        CLKCTRL_PLL0CTRL0_POWER);
@@ -52,10 +52,10 @@ void mx28_power_clock2pll(void)
                        CLKCTRL_CLKSEQ_BYPASS_CPU);
 }
 
-void mx28_power_clear_auto_restart(void)
+void mxs_power_clear_auto_restart(void)
 {
-       struct mx28_rtc_regs *rtc_regs =
-               (struct mx28_rtc_regs *)MXS_RTC_BASE;
+       struct mxs_rtc_regs *rtc_regs =
+               (struct mxs_rtc_regs *)MXS_RTC_BASE;
 
        writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
        while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
@@ -85,10 +85,10 @@ void mx28_power_clear_auto_restart(void)
                ;
 }
 
-void mx28_power_set_linreg(void)
+void mxs_power_set_linreg(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        /* Set linear regulator 25mV below switching converter */
        clrsetbits_le32(&power_regs->hw_power_vdddctrl,
@@ -104,10 +104,10 @@ void mx28_power_set_linreg(void)
                        POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 }
 
-int mx28_get_batt_volt(void)
+int mxs_get_batt_volt(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t volt = readl(&power_regs->hw_power_battmonitor);
        volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
        volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
@@ -115,16 +115,16 @@ int mx28_get_batt_volt(void)
        return volt;
 }
 
-int mx28_is_batt_ready(void)
+int mxs_is_batt_ready(void)
 {
-       return (mx28_get_batt_volt() >= 3600);
+       return (mxs_get_batt_volt() >= 3600);
 }
 
-int mx28_is_batt_good(void)
+int mxs_is_batt_good(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
-       uint32_t volt = mx28_get_batt_volt();
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
+       uint32_t volt = mxs_get_batt_volt();
 
        if ((volt >= 2400) && (volt <= 4300))
                return 1;
@@ -145,7 +145,7 @@ int mx28_is_batt_good(void)
 
        early_delay(500000);
 
-       volt = mx28_get_batt_volt();
+       volt = mxs_get_batt_volt();
 
        if (volt >= 3500)
                return 0;
@@ -160,10 +160,10 @@ int mx28_is_batt_good(void)
        return 0;
 }
 
-void mx28_power_setup_5v_detect(void)
+void mxs_power_setup_5v_detect(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        /* Start 5V detection */
        clrsetbits_le32(&power_regs->hw_power_5vctrl,
@@ -172,10 +172,10 @@ void mx28_power_setup_5v_detect(void)
                        POWER_5VCTRL_PWRUP_VBUS_CMPS);
 }
 
-void mx28_src_power_init(void)
+void mxs_src_power_init(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        /* Improve efficieny and reduce transient ripple */
        writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
@@ -203,10 +203,10 @@ void mx28_src_power_init(void)
        clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 }
 
-void mx28_power_init_4p2_params(void)
+void mxs_power_init_4p2_params(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        /* Setup 4P2 parameters */
        clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
@@ -227,10 +227,10 @@ void mx28_power_init_4p2_params(void)
                0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
-void mx28_enable_4p2_dcdc_input(int xfer)
+void mxs_enable_4p2_dcdc_input(int xfer)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
        uint32_t prev_5v_brnout, prev_5v_droop;
 
@@ -323,10 +323,10 @@ void mx28_enable_4p2_dcdc_input(int xfer)
                                POWER_CTRL_ENIRQ_VDD5V_DROOP);
 }
 
-void mx28_power_init_4p2_regulator(void)
+void mxs_power_init_4p2_regulator(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp, tmp2;
 
        setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
@@ -346,7 +346,7 @@ void mx28_power_init_4p2_regulator(void)
         * gradually to avoid large inrush current from the 5V cable which can
         * cause transients/problems
         */
-       mx28_enable_4p2_dcdc_input(0);
+       mxs_enable_4p2_dcdc_input(0);
 
        if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
                /*
@@ -407,17 +407,17 @@ void mx28_power_init_4p2_regulator(void)
        writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 }
 
-void mx28_power_init_dcdc_4p2_source(void)
+void mxs_power_init_dcdc_4p2_source(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        if (!(readl(&power_regs->hw_power_dcdc4p2) &
                POWER_DCDC4P2_ENABLE_DCDC)) {
                hang();
        }
 
-       mx28_enable_4p2_dcdc_input(1);
+       mxs_enable_4p2_dcdc_input(1);
 
        if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
                clrbits_le32(&power_regs->hw_power_dcdc4p2,
@@ -429,10 +429,10 @@ void mx28_power_init_dcdc_4p2_source(void)
        }
 }
 
-void mx28_power_enable_4p2(void)
+void mxs_power_enable_4p2(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t vdddctrl, vddactrl, vddioctrl;
        uint32_t tmp;
 
@@ -451,11 +451,11 @@ void mx28_power_enable_4p2(void)
        setbits_le32(&power_regs->hw_power_vddioctrl,
                POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
 
-       mx28_power_init_4p2_params();
-       mx28_power_init_4p2_regulator();
+       mxs_power_init_4p2_params();
+       mxs_power_init_4p2_regulator();
 
        /* Shutdown battery (none present) */
-       if (!mx28_is_batt_ready()) {
+       if (!mxs_is_batt_ready()) {
                clrbits_le32(&power_regs->hw_power_dcdc4p2,
                                POWER_DCDC4P2_BO_MASK);
                writel(POWER_CTRL_DCDC4P2_BO_IRQ,
@@ -464,7 +464,7 @@ void mx28_power_enable_4p2(void)
                                &power_regs->hw_power_ctrl_clr);
        }
 
-       mx28_power_init_dcdc_4p2_source();
+       mxs_power_init_dcdc_4p2_source();
 
        writel(vdddctrl, &power_regs->hw_power_vdddctrl);
        early_delay(20);
@@ -488,10 +488,10 @@ void mx28_power_enable_4p2(void)
                        &power_regs->hw_power_charge_clr);
 }
 
-void mx28_boot_valid_5v(void)
+void mxs_boot_valid_5v(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        /*
         * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
@@ -508,22 +508,22 @@ void mx28_boot_valid_5v(void)
        writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
                &power_regs->hw_power_ctrl_clr);
 
-       mx28_power_enable_4p2();
+       mxs_power_enable_4p2();
 }
 
-void mx28_powerdown(void)
+void mxs_powerdown(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
        writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
                &power_regs->hw_power_reset);
 }
 
-void mx28_batt_boot(void)
+void mxs_batt_boot(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
        clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
@@ -542,7 +542,7 @@ void mx28_batt_boot(void)
        clrsetbits_le32(&power_regs->hw_power_minpwr,
                        POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 
-       mx28_power_set_linreg();
+       mxs_power_set_linreg();
 
        clrbits_le32(&power_regs->hw_power_vdddctrl,
                POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
@@ -564,10 +564,10 @@ void mx28_batt_boot(void)
                0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
-void mx28_handle_5v_conflict(void)
+void mxs_handle_5v_conflict(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp;
 
        setbits_le32(&power_regs->hw_power_vddioctrl,
@@ -577,52 +577,56 @@ void mx28_handle_5v_conflict(void)
                tmp = readl(&power_regs->hw_power_sts);
 
                if (tmp & POWER_STS_VDDIO_BO) {
-                       mx28_powerdown();
+                       /*
+                        * VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes
+                        * unreliable
+                        */
+                       mxs_powerdown();
                        break;
                }
 
                if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
-                       mx28_boot_valid_5v();
+                       mxs_boot_valid_5v();
                        break;
                } else {
-                       mx28_powerdown();
+                       mxs_powerdown();
                        break;
                }
 
                if (tmp & POWER_STS_PSWITCH_MASK) {
-                       mx28_batt_boot();
+                       mxs_batt_boot();
                        break;
                }
        }
 }
 
-void mx28_5v_boot(void)
+void mxs_5v_boot(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        /*
         * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
         * but their implementation always returns 1 so we omit it here.
         */
        if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
-               mx28_boot_valid_5v();
+               mxs_boot_valid_5v();
                return;
        }
 
        early_delay(1000);
        if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
-               mx28_boot_valid_5v();
+               mxs_boot_valid_5v();
                return;
        }
 
-       mx28_handle_5v_conflict();
+       mxs_handle_5v_conflict();
 }
 
-void mx28_init_batt_bo(void)
+void mxs_init_batt_bo(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        /* Brownout at 3V */
        clrsetbits_le32(&power_regs->hw_power_battmonitor,
@@ -633,10 +637,10 @@ void mx28_init_batt_bo(void)
        writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 }
 
-void mx28_switch_vddd_to_dcdc_source(void)
+void mxs_switch_vddd_to_dcdc_source(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        clrsetbits_le32(&power_regs->hw_power_vdddctrl,
                POWER_VDDDCTRL_LINREG_OFFSET_MASK,
@@ -647,51 +651,48 @@ void mx28_switch_vddd_to_dcdc_source(void)
                POWER_VDDDCTRL_DISABLE_STEPPING);
 }
 
-void mx28_power_configure_power_source(void)
+void mxs_power_configure_power_source(void)
 {
        int batt_ready, batt_good;
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
-       struct mx28_lradc_regs *lradc_regs =
-               (struct mx28_lradc_regs *)MXS_LRADC_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
+       struct mxs_lradc_regs *lradc_regs =
+               (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
-       mx28_src_power_init();
-
-       batt_ready = mx28_is_batt_ready();
+       mxs_src_power_init();
 
        if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
-               batt_good = mx28_is_batt_good();
+               batt_ready = mxs_is_batt_ready();
                if (batt_ready) {
                        /* 5V source detected, good battery detected. */
-                       mx28_batt_boot();
+                       mxs_batt_boot();
                } else {
-                       if (batt_good) {
-                               /* 5V source detected, low battery detceted. */
-                       } else {
+                       batt_good = mxs_is_batt_good();
+                       if (!batt_good) {
                                /* 5V source detected, bad battery detected. */
                                writel(LRADC_CONVERSION_AUTOMATIC,
                                        &lradc_regs->hw_lradc_conversion_clr);
                                clrbits_le32(&power_regs->hw_power_battmonitor,
                                        POWER_BATTMONITOR_BATT_VAL_MASK);
                        }
-                       mx28_5v_boot();
+                       mxs_5v_boot();
                }
        } else {
                /* 5V not detected, booting from battery. */
-               mx28_batt_boot();
+               mxs_batt_boot();
        }
 
-       mx28_power_clock2pll();
+       mxs_power_clock2pll();
 
-       mx28_init_batt_bo();
+       mxs_init_batt_bo();
 
-       mx28_switch_vddd_to_dcdc_source();
+       mxs_switch_vddd_to_dcdc_source();
 }
 
-void mx28_enable_output_rail_protection(void)
+void mxs_enable_output_rail_protection(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
                POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
@@ -706,17 +707,17 @@ void mx28_enable_output_rail_protection(void)
                        POWER_VDDIOCTRL_PWDN_BRNOUT);
 }
 
-int mx28_get_vddio_power_source_off(void)
+int mxs_get_vddio_power_source_off(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp;
 
        if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
                tmp = readl(&power_regs->hw_power_vddioctrl);
                if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
                        if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
-                               POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+                               POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
                                return 1;
                        }
                }
@@ -724,7 +725,7 @@ int mx28_get_vddio_power_source_off(void)
                if (!(readl(&power_regs->hw_power_5vctrl) &
                        POWER_5VCTRL_ENABLE_DCDC)) {
                        if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
-                               POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
+                               POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
                                return 1;
                        }
                }
@@ -734,10 +735,10 @@ int mx28_get_vddio_power_source_off(void)
 
 }
 
-int mx28_get_vddd_power_source_off(void)
+int mxs_get_vddd_power_source_off(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t tmp;
 
        tmp = readl(&power_regs->hw_power_vdddctrl);
@@ -765,21 +766,21 @@ int mx28_get_vddd_power_source_off(void)
        return 0;
 }
 
-void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t cur_target, diff, bo_int = 0;
        uint32_t powered_by_linreg = 0;
 
-       new_brownout = new_target - new_brownout;
+       new_brownout = (new_target - new_brownout + 25) / 50;
 
        cur_target = readl(&power_regs->hw_power_vddioctrl);
        cur_target &= POWER_VDDIOCTRL_TRG_MASK;
        cur_target *= 50;       /* 50 mV step*/
        cur_target += 2800;     /* 2800 mV lowest */
 
-       powered_by_linreg = mx28_get_vddio_power_source_off();
+       powered_by_linreg = mxs_get_vddio_power_source_off();
        if (new_target > cur_target) {
 
                if (powered_by_linreg) {
@@ -858,25 +859,25 @@ void mx28_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
        }
 
        clrsetbits_le32(&power_regs->hw_power_vddioctrl,
-                       POWER_VDDDCTRL_BO_OFFSET_MASK,
-                       new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+                       POWER_VDDIOCTRL_BO_OFFSET_MASK,
+                       new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
 }
 
-void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
+void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t cur_target, diff, bo_int = 0;
        uint32_t powered_by_linreg = 0;
 
-       new_brownout = new_target - new_brownout;
+       new_brownout = (new_target - new_brownout + 12) / 25;
 
        cur_target = readl(&power_regs->hw_power_vdddctrl);
        cur_target &= POWER_VDDDCTRL_TRG_MASK;
        cur_target *= 25;       /* 25 mV step*/
        cur_target += 800;      /* 800 mV lowest */
 
-       powered_by_linreg = mx28_get_vddd_power_source_off();
+       powered_by_linreg = mxs_get_vddd_power_source_off();
        if (new_target > cur_target) {
                if (powered_by_linreg) {
                        bo_int = readl(&power_regs->hw_power_vdddctrl);
@@ -959,31 +960,31 @@ void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
                        new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
 }
 
-void mx28_setup_batt_detect(void)
+void mxs_setup_batt_detect(void)
 {
-       mx28_lradc_init();
-       mx28_lradc_enable_batt_measurement();
+       mxs_lradc_init();
+       mxs_lradc_enable_batt_measurement();
        early_delay(10);
 }
 
-void mx28_power_init(void)
+void mxs_power_init(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
-       mx28_power_clock2xtal();
-       mx28_power_clear_auto_restart();
-       mx28_power_set_linreg();
-       mx28_power_setup_5v_detect();
+       mxs_power_clock2xtal();
+       mxs_power_clear_auto_restart();
+       mxs_power_set_linreg();
+       mxs_power_setup_5v_detect();
 
-       mx28_setup_batt_detect();
+       mxs_setup_batt_detect();
 
-       mx28_power_configure_power_source();
-       mx28_enable_output_rail_protection();
+       mxs_power_configure_power_source();
+       mxs_enable_output_rail_protection();
 
-       mx28_power_set_vddio(3300, 3150);
+       mxs_power_set_vddio(3300, 3150);
 
-       mx28_power_set_vddd(1350, 1200);
+       mxs_power_set_vddd(1350, 1200);
 
        writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
                POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
@@ -996,10 +997,10 @@ void mx28_power_init(void)
 }
 
 #ifdef CONFIG_SPL_MX28_PSWITCH_WAIT
-void mx28_power_wait_pswitch(void)
+void mxs_power_wait_pswitch(void)
 {
-       struct mx28_power_regs *power_regs =
-               (struct mx28_power_regs *)MXS_POWER_BASE;
+       struct mxs_power_regs *power_regs =
+               (struct mxs_power_regs *)MXS_POWER_BASE;
 
        while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
                ;
similarity index 82%
rename from arch/arm/cpu/arm926ejs/mx28/start.S
rename to arch/arm/cpu/arm926ejs/mxs/start.S
index e572b78..7ccd337 100644 (file)
@@ -180,14 +180,6 @@ _reset:
        orr     r0,r0,#0xd3
        msr     cpsr,r0
 
-       /*
-        * we do sys-critical inits only at reboot,
-        * not when booting from ram!
-        */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-       bl      cpu_init_crit
-#endif
-
        bl      board_init_ll
 
        /*
@@ -207,40 +199,6 @@ _reset:
        pop     {r0-r12,r14}
        bx      lr
 
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
-       /*
-        * flush v4 I/D caches
-        */
-       mov     r0, #0
-       mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
-       mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
-
-       /*
-        * disable MMU stuff and caches
-        */
-       mrc     p15, 0, r0, c1, c0, 0
-       bic     r0, r0, #0x00002300     /* clear bits 13, 9:8 (--V- --RS) */
-       bic     r0, r0, #0x00000087     /* clear bits 7, 2:0 (B--- -CAM) */
-       orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
-       orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
-       mcr     p15, 0, r0, c1, c0, 0
-
-       mov     pc, lr          /* back to my caller */
-
-       .align  5
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-
 _hang:
        ldr     sp, _TEXT_BASE                  /* switch to abort stack */
 1:
similarity index 93%
rename from arch/arm/cpu/arm926ejs/mx28/timer.c
rename to arch/arm/cpu/arm926ejs/mxs/timer.c
index 5b73f4a..4ed75e6 100644 (file)
@@ -62,11 +62,11 @@ static inline unsigned long us_to_tick(unsigned long us)
 
 int timer_init(void)
 {
-       struct mx28_timrot_regs *timrot_regs =
-               (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+       struct mxs_timrot_regs *timrot_regs =
+               (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
 
        /* Reset Timers and Rotary Encoder module */
-       mx28_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
+       mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
 
        /* Set fixed_count to 0 */
        writel(0, &timrot_regs->hw_timrot_fixed_count0);
@@ -84,8 +84,8 @@ int timer_init(void)
 
 unsigned long long get_ticks(void)
 {
-       struct mx28_timrot_regs *timrot_regs =
-               (struct mx28_timrot_regs *)MXS_TIMROT_BASE;
+       struct mxs_timrot_regs *timrot_regs =
+               (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
 
        /* Current tick value */
        uint32_t now = readl(&timrot_regs->hw_timrot_running_count0);
similarity index 97%
rename from arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds
rename to arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 0fccd52..f8ea38c 100644 (file)
@@ -37,7 +37,7 @@ SECTIONS
        . = ALIGN(4);
        .text   :
        {
-               arch/arm/cpu/arm926ejs/mx28/start.o     (.text)
+               arch/arm/cpu/arm926ejs/mxs/start.o      (.text)
                *(.text)
        }
 
index 6b2addc..4fdbee4 100644 (file)
@@ -32,8 +32,12 @@ COBJS        += cache_v7.o
 COBJS  += cpu.o
 COBJS  += syslib.o
 
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+SOBJS  += lowlevel_init.o
+endif
+
 SRCS   := $(START:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
+OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
 START  := $(addprefix $(obj),$(START))
 
 all:   $(obj).depend $(START) $(LIB)
index 71309a7..b387ac2 100644 (file)
  */
 
 #include <common.h>
+#include <errno.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
-#include <asm/arch/common_def.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -33,6 +40,78 @@ struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
+static const struct gpio_bank gpio_bank_am33xx[4] = {
+       { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+       { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+       { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+       { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+
+/* MII mode defines */
+#define MII_MODE_ENABLE                0x0
+#define RGMII_MODE_ENABLE      0xA
+
+/* GPIO that controls power to DDR on EVM-SK */
+#define GPIO_DDR_VTT_EN                7
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+static struct am335x_baseboard_id __attribute__((section (".data"))) header;
+
+static inline int board_is_bone(void)
+{
+       return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
+}
+
+static inline int board_is_evm_sk(void)
+{
+       return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
+}
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+       /* Check if baseboard eeprom is available */
+       if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+               puts("Could not probe the EEPROM; something fundamentally "
+                       "wrong on the I2C bus.\n");
+               return -ENODEV;
+       }
+
+       /* read the eeprom using i2c */
+       if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+                                                       sizeof(header))) {
+               puts("Could not read the EEPROM; something fundamentally"
+                       " wrong on the I2C bus.\n");
+               return -EIO;
+       }
+
+       if (header.magic != 0xEE3355AA) {
+               /*
+                * read the eeprom using i2c again,
+                * but use only a 1 byte address
+                */
+               if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
+                                       (uchar *)&header, sizeof(header))) {
+                       puts("Could not read the EEPROM; something "
+                               "fundamentally wrong on the I2C bus.\n");
+                       return -EIO;
+               }
+
+               if (header.magic != 0xEE3355AA) {
+                       printf("Incorrect magic number (0x%x) in EEPROM\n",
+                                       header.magic);
+                       return -EINVAL;
+               }
+       }
+
+       return 0;
+}
+
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
 #define UART_RESET             (0x1 << 1)
@@ -56,6 +135,18 @@ static void init_timer(void)
 }
 #endif
 
+/*
+ * Determine what type of DDR we have.
+ */
+static short inline board_memory_type(void)
+{
+       /* The following boards are known to use DDR3. */
+       if (board_is_evm_sk())
+               return EMIF_REG_SDRAM_TYPE_DDR3;
+
+       return EMIF_REG_SDRAM_TYPE_DDR2;
+}
+
 /*
  * early system init of muxing and clocks.
  */
@@ -97,17 +188,36 @@ void s_init(void)
 
        preloader_console_init();
 
-       config_ddr();
-#endif
+       /* Initalize the board header */
+       enable_i2c0_pin_mux();
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       if (read_eeprom() < 0)
+               puts("Could not get board ID.\n");
+
+       enable_board_pin_mux(&header);
+       if (board_is_evm_sk()) {
+               /*
+                * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
+                * This is safe enough to do on older revs.
+                */
+               gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
+               gpio_direction_output(GPIO_DDR_VTT_EN, 1);
+       }
 
-       /* Enable MMC0 */
-       enable_mmc0_pin_mux();
+       config_ddr(board_memory_type());
+#endif
 }
 
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
-       return omap_mmc_init(0, 0, 0);
+       int ret;
+       
+       ret = omap_mmc_init(0, 0, 0);
+       if (ret)
+               return ret;
+
+       return omap_mmc_init(1, 0, 0);
 }
 #endif
 
@@ -116,3 +226,93 @@ void setup_clocks_for_console(void)
        /* Not yet implemented */
        return;
 }
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       if (read_eeprom() < 0)
+               puts("Could not get board ID.\n");
+
+       gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+
+       return 0;
+}
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+static void cpsw_control(int enabled)
+{
+       /* VTP can be added here */
+
+       return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+       {
+               .slave_reg_ofs  = 0x208,
+               .sliver_reg_ofs = 0xd80,
+               .phy_id         = 0,
+       },
+       {
+               .slave_reg_ofs  = 0x308,
+               .sliver_reg_ofs = 0xdc0,
+               .phy_id         = 1,
+       },
+};
+
+static struct cpsw_platform_data cpsw_data = {
+       .mdio_base              = AM335X_CPSW_MDIO_BASE,
+       .cpsw_base              = AM335X_CPSW_BASE,
+       .mdio_div               = 0xff,
+       .channels               = 8,
+       .cpdma_reg_ofs          = 0x800,
+       .slaves                 = 1,
+       .slave_data             = cpsw_slaves,
+       .ale_reg_ofs            = 0xd00,
+       .ale_entries            = 1024,
+       .host_port_reg_ofs      = 0x108,
+       .hw_stats_reg_ofs       = 0x900,
+       .mac_control            = (1 << 5),
+       .control                = cpsw_control,
+       .host_port_num          = 0,
+       .version                = CPSW_CTRL_VERSION_2,
+};
+
+int board_eth_init(bd_t *bis)
+{
+       uint8_t mac_addr[6];
+       uint32_t mac_hi, mac_lo;
+
+       if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+               debug("<ethaddr> not set. Reading from E-fuse\n");
+               /* try reading mac address from efuse */
+               mac_lo = readl(&cdev->macid0l);
+               mac_hi = readl(&cdev->macid0h);
+               mac_addr[0] = mac_hi & 0xFF;
+               mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+               mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+               mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+               mac_addr[4] = mac_lo & 0xFF;
+               mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+               if (is_valid_ether_addr(mac_addr))
+                       eth_setenv_enetaddr("ethaddr", mac_addr);
+               else
+                       return -1;
+       }
+
+       if (board_is_bone()) {
+               writel(MII_MODE_ENABLE, &cdev->miisel);
+               cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+                               PHY_INTERFACE_MODE_MII;
+       } else {
+               writel(RGMII_MODE_ENABLE, &cdev->miisel);
+               cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
+                               PHY_INTERFACE_MODE_RGMII;
+       }
+
+       return cpsw_register(&cpsw_data);
+}
+#endif
index bbb9c13..2b19506 100644 (file)
@@ -24,6 +24,7 @@
 
 #define PRCM_MOD_EN            0x2
 #define PRCM_FORCE_WAKEUP      0x2
+#define PRCM_FUNCTL            0x0
 
 #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
 #define PRCM_L3_GCLK_ACTIVITY  BIT(4)
@@ -38,7 +39,7 @@
 #define CLK_MODE_SEL           0x7
 #define CLK_MODE_MASK          0xfffffff8
 #define CLK_DIV_SEL            0xFFFFFFE0
-
+#define CPGMAC0_IDLE           0x30000
 
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@@ -70,6 +71,10 @@ static void enable_interface_clocks(void)
        writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
        while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
                ;
+
+       writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
+       while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 /*
@@ -118,6 +123,36 @@ static void enable_per_clocks(void)
        writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
        while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
                ;
+
+       /* gpio1 module */
+       writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
+       while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* gpio2 module */
+       writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
+       while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* gpio3 module */
+       writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
+       while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* i2c1 */
+       writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
+       while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
+               ;
+
+       /* Ethernet */
+       writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
+       while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
+               ;
+
+       /* spi0 */
+       writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+       while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+               ;
 }
 
 static void mpu_pll_config(void)
@@ -216,7 +251,7 @@ static void per_pll_config(void)
                ;
 }
 
-static void ddr_pll_config(void)
+void ddr_pll_config(unsigned int ddrpll_m)
 {
        u32 clkmode, clksel, div_m2;
 
@@ -234,7 +269,7 @@ static void ddr_pll_config(void)
                ;
 
        clksel = clksel & (~CLK_SEL_MASK);
-       clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
+       clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
        writel(clksel, &cmwkup->clkseldpllddr);
 
        div_m2 = div_m2 & CLK_DIV_SEL;
@@ -255,11 +290,6 @@ void enable_emif_clocks(void)
        writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
        /* Enable EMIF0 Clock */
        writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-       /* Poll for emif_gclk  & L3_G clock  are active */
-       while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
-                       PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
-                       PRCM_L3_GCLK_ACTIVITY))
-               ;
        /* Poll if module is functional */
        while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
                ;
@@ -273,7 +303,6 @@ void pll_init()
        mpu_pll_config();
        core_pll_config();
        per_pll_config();
-       ddr_pll_config();
 
        /* Enable the required interconnect clocks */
        enable_interface_clocks();
index ed982c1..fd9fc4a 100644 (file)
@@ -17,13 +17,15 @@ http://www.ti.com/
 
 #include <asm/arch/cpu.h>
 #include <asm/arch/ddr_defs.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <asm/emif.h>
 
 /**
  * Base address for EMIF instances
  */
-static struct emif_regs *emif_reg = {
-                               (struct emif_regs *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg = {
+                               (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
 
 /**
  * Base address for DDR instance
@@ -38,110 +40,80 @@ static struct ddr_regs *ddr_reg[2] = {
 static struct ddr_cmdtctrl *ioctrl_reg = {
                        (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
 
-/**
- * As a convention, all functions here return 0 on success
- * -1 on failure.
- */
-
 /**
  * Configure SDRAM
  */
-int config_sdram(struct sdram_config *cfg)
+void config_sdram(const struct emif_regs *regs)
 {
-       writel(cfg->sdrcr, &emif_reg->sdrcr);
-       writel(cfg->sdrcr2, &emif_reg->sdrcr2);
-       writel(cfg->refresh, &emif_reg->sdrrcr);
-       writel(cfg->refresh_sh, &emif_reg->sdrrcsr);
-
-       return 0;
+       writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
+       writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+       if (regs->zq_config){
+               writel(regs->zq_config, &emif_reg->emif_zq_config);
+               writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
+       }
+       writel(regs->sdram_config, &emif_reg->emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-int set_sdram_timings(struct sdram_timing *t)
+void set_sdram_timings(const struct emif_regs *regs)
 {
-       writel(t->time1, &emif_reg->sdrtim1);
-       writel(t->time1_sh, &emif_reg->sdrtim1sr);
-       writel(t->time2, &emif_reg->sdrtim2);
-       writel(t->time2_sh, &emif_reg->sdrtim2sr);
-       writel(t->time3, &emif_reg->sdrtim3);
-       writel(t->time3_sh, &emif_reg->sdrtim3sr);
-
-       return 0;
+       writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
+       writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
+       writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
+       writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
+       writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
+       writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-int config_ddr_phy(struct ddr_phy_control *p)
+void config_ddr_phy(const struct emif_regs *regs)
 {
-       writel(p->reg, &emif_reg->ddrphycr);
-       writel(p->reg_sh, &emif_reg->ddrphycsr);
-
-       return 0;
+       writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
+       writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
  * Configure DDR CMD control registers
  */
-int config_cmd_ctrl(struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd)
 {
        writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
-       writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
-       writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
        writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
        writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
 
        writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
-       writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
-       writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
        writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
        writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
 
        writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
-       writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
-       writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
        writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
        writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
-
-       return 0;
 }
 
 /**
  * Configure DDR DATA registers
  */
-int config_ddr_data(int macrono, struct ddr_data *data)
+void config_ddr_data(int macrono, const struct ddr_data *data)
 {
        writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
-       writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
-
        writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
-       writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
-
        writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
-       writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
        writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
-       writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
-
        writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
-       writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
-
        writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
-       writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
-
+       writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
        writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
-
-       return 0;
 }
 
-int config_io_ctrl(struct ddr_ioctrl *ioctrl)
+void config_io_ctrl(unsigned long val)
 {
-       writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
-       writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
-       writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
-       writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
-       writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
-
-       return 0;
+       writel(val, &ioctrl_reg->cm0ioctl);
+       writel(val, &ioctrl_reg->cm1ioctl);
+       writel(val, &ioctrl_reg->cm2ioctl);
+       writel(val, &ioctrl_reg->dt0ioctl);
+       writel(val, &ioctrl_reg->dt1ioctl);
 }
index 2f4164d..b2d7c0d 100644 (file)
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include <asm/emif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
-struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
-struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
-
-
 int dram_init(void)
 {
        /* dram_init must store complete ramsize in gd->ram_size */
@@ -47,58 +44,80 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
-static void data_macro_config(int dataMacroNum)
-{
-       struct ddr_data data;
-
-       data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-                               |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
-       data.datardsratio1 = DDR2_RD_DQS>>2;
-       data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-                               |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
-       data.datawdsratio1 = DDR2_WR_DQS>>2;
-       data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-                               |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
-       data.datawiratio1 = DDR2_PHY_WRLVL>>2;
-       data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-                               |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
-       data.datagiratio1 = DDR2_PHY_GATELVL>>2;
-       data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-                               |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
-       data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
-       data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-                               |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
-       data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
-       data.datadldiff0 = PHY_DLL_LOCK_DIFF;
-
-       config_ddr_data(dataMacroNum, &data);
-}
-
-static void cmd_macro_config(void)
-{
-       struct cmd_control cmd;
-
-       cmd.cmd0csratio = DDR2_RATIO;
-       cmd.cmd0csforce = CMD_FORCE;
-       cmd.cmd0csdelay = CMD_DELAY;
-       cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
-       cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
-
-       cmd.cmd1csratio = DDR2_RATIO;
-       cmd.cmd1csforce = CMD_FORCE;
-       cmd.cmd1csdelay = CMD_DELAY;
-       cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
-       cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
-
-       cmd.cmd2csratio = DDR2_RATIO;
-       cmd.cmd2csforce = CMD_FORCE;
-       cmd.cmd2csdelay = CMD_DELAY;
-       cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
-       cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
-
-       config_cmd_ctrl(&cmd);
-
-}
+static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+
+static const struct ddr_data ddr2_data = {
+       .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
+                               |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
+       .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
+                               |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
+       .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
+                               |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
+       .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
+                               |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
+       .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
+                               |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
+       .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
+       &nbs