ARM: OMAP5: dmm: Create a tiler trap section.

The unmapped entries in tiler space are set with
values 0xFF. So creating a DMM section of
size 16MB at 0xFF000000 with ADDRSPACE set to 0x2.

This way all the unmapped entry accesses to tiler
will be trapped by the EMIF and a error response
is sent to the L3 interconnect. L3 errors are
inturn reported to MPU.

Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.

Signed-off-by: R Sricharan <r.sricharan@ti.com>

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index b2b5753e894e73db5245423c5b934ab842232f73..368b78bf498c06529de158a4786973ae949b69e5 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -88,9 +88,9 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
 
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
        .dmm_lisa_map_0 = 0x0,
-       .dmm_lisa_map_1 = 0,
-       .dmm_lisa_map_2 = 0,
-       .dmm_lisa_map_3 = 0x80740300
+       .dmm_lisa_map_1 = 0x0,
+       .dmm_lisa_map_2 = 0x80740300,
+       .dmm_lisa_map_3 = 0xFF020100
 };
 
 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {