usb: dwc3: dwc3-omap: Use the clear register inorder to clear the interrupts
authorKishon Vijay Abraham I <kishon@ti.com>
Mon, 10 Aug 2015 11:22:54 +0000 (16:52 +0530)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 09:29:51 +0000 (11:29 +0200)
Writing "0x00" to the USBOTGSS_IRQENABLE_SET_MISC and
USBOTGSS_IRQENABLE_SET_0 doesn't disable the interrupts. Used
USBOTGSS_IRQENABLE_CLR_MISC and USBOTGSS_IRQENABLE_CLR_0 instead.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
drivers/usb/dwc3/dwc3-omap.c

index 46af109..ac9a856 100644 (file)
 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL              (1 << 3)
 #define USBOTGSS_IRQMISC_IDPULLUP_FALL         (1 << 0)
 
+#define USBOTGSS_INTERRUPTS (USBOTGSS_IRQMISC_OEVT | \
+                            USBOTGSS_IRQMISC_DRVVBUS_RISE | \
+                            USBOTGSS_IRQMISC_CHRGVBUS_RISE | \
+                            USBOTGSS_IRQMISC_DISCHRGVBUS_RISE | \
+                            USBOTGSS_IRQMISC_IDPULLUP_RISE | \
+                            USBOTGSS_IRQMISC_DRVVBUS_FALL | \
+                            USBOTGSS_IRQMISC_CHRGVBUS_FALL | \
+                            USBOTGSS_IRQMISC_DISCHRGVBUS_FALL | \
+                            USBOTGSS_IRQMISC_IDPULLUP_FALL)
+
 /* UTMI_OTG_CTRL REGISTER */
 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS         (1 << 5)
 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS                (1 << 4)
@@ -187,6 +197,18 @@ static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
                                                omap->irq0_offset, value);
 }
 
+static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)
+{
+       dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +
+                                               omap->irqmisc_offset, value);
+}
+
+static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)
+{
+       dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -
+                                               omap->irq0_offset, value);
+}
+
 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
        enum omap_dwc3_vbus_id_status status)
 {
@@ -285,30 +307,18 @@ static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
 
 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
 {
-       u32                     reg;
-
        /* enable all IRQs */
-       reg = USBOTGSS_IRQO_COREIRQ_ST;
-       dwc3_omap_write_irq0_set(omap, reg);
-
-       reg = (USBOTGSS_IRQMISC_OEVT |
-                       USBOTGSS_IRQMISC_DRVVBUS_RISE |
-                       USBOTGSS_IRQMISC_CHRGVBUS_RISE |
-                       USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
-                       USBOTGSS_IRQMISC_IDPULLUP_RISE |
-                       USBOTGSS_IRQMISC_DRVVBUS_FALL |
-                       USBOTGSS_IRQMISC_CHRGVBUS_FALL |
-                       USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
-                       USBOTGSS_IRQMISC_IDPULLUP_FALL);
-
-       dwc3_omap_write_irqmisc_set(omap, reg);
+       dwc3_omap_write_irq0_set(omap, USBOTGSS_IRQO_COREIRQ_ST);
+
+       dwc3_omap_write_irqmisc_set(omap, USBOTGSS_INTERRUPTS);
 }
 
 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
 {
        /* disable all IRQs */
-       dwc3_omap_write_irqmisc_set(omap, 0x00);
-       dwc3_omap_write_irq0_set(omap, 0x00);
+       dwc3_omap_write_irq0_clr(omap, USBOTGSS_IRQO_COREIRQ_ST);
+
+       dwc3_omap_write_irqmisc_clr(omap, USBOTGSS_INTERRUPTS);
 }
 
 static void dwc3_omap_map_offset(struct dwc3_omap *omap)