Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

diff --combined drivers/spi/mxc_spi.c
index cb48019a42b409acb8195ea3bd3cfa97f005de5d,20419e6bc6779fcad35b2abb562e1114a7e184ba..5bed858787f610a9c9a46bb2214665a51d60a9e9
--- 1/drivers/spi/mxc_spi.c
--- 2/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@@ -137,11 -137,15 +137,15 @@@ static s32 spi_cfg_mxc(struct mxc_spi_s
                return -1;
        }
  
-       /* Reset spi */
-       reg_write(&regs->ctrl, 0);
-       reg_write(&regs->ctrl, MXC_CSPICTRL_EN);
- 
-       reg_ctrl = reg_read(&regs->ctrl);
+       /*
+        * Reset SPI and set all CSs to master mode, if toggling
+        * between slave and master mode we might see a glitch
+        * on the clock line
+        */
+       reg_ctrl = MXC_CSPICTRL_MODE_MASK;
+       reg_write(&regs->ctrl, reg_ctrl);
+       reg_ctrl |=  MXC_CSPICTRL_EN;
+       reg_write(&regs->ctrl, reg_ctrl);
  
        /*
         * The following computation is taken directly from Freescale's code.
@@@ -174,9 -178,6 +178,6 @@@
        reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
                MXC_CSPICTRL_POSTDIV(post_div);
  
-       /* always set to master mode */
-       reg_ctrl |= 1 << (cs + 4);
- 
        /* We need to disable SPI before changing registers */
        reg_ctrl &= ~MXC_CSPICTRL_EN;
  
@@@ -408,7 -409,7 +409,7 @@@ struct spi_slave *spi_setup_slave(unsig
        if (bus >= ARRAY_SIZE(spi_bases))
                return NULL;
  
 -      mxcs = calloc(sizeof(struct mxc_spi_slave), 1);
 +      mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
        if (!mxcs) {
                puts("mxc_spi: SPI Slave not allocated !\n");
                return NULL;
@@@ -424,6 -425,8 +425,6 @@@
  
        cs = ret;
  
 -      mxcs->slave.bus = bus;
 -      mxcs->slave.cs = cs;
        mxcs->base = spi_bases[bus];
  
        ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);