Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 249d15a5053ad0cbd7b48033c2c5c7c5b4c0c44c..a71cc13e2ab498d0ea615d4dad98641786a33165 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -230,6 +230,7 @@
 #define MXC_CSPICTRL_EN                (1 << 0)
 #define MXC_CSPICTRL_MODE      (1 << 1)
 #define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
 #define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index eaa7439486a1f46ae78e7444f3df0985f9f79440..d79ab2f13fee81b02348565f9b5498482156d12b 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -346,6 +346,7 @@ struct cspi_regs {
 #define MXC_CSPICTRL_EN                (1 << 0)
 #define MXC_CSPICTRL_MODE      (1 << 1)
 #define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
 #define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
 #define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index cb48019a42b409acb8195ea3bd3cfa97f005de5d..5bed858787f610a9c9a46bb2214665a51d60a9e9 100644 (file)
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -137,11 +137,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
                return -1;
        }
 
-       /* Reset spi */
-       reg_write(&regs->ctrl, 0);
-       reg_write(&regs->ctrl, MXC_CSPICTRL_EN);
-
-       reg_ctrl = reg_read(&regs->ctrl);
+       /*
+        * Reset SPI and set all CSs to master mode, if toggling
+        * between slave and master mode we might see a glitch
+        * on the clock line
+        */
+       reg_ctrl = MXC_CSPICTRL_MODE_MASK;
+       reg_write(&regs->ctrl, reg_ctrl);
+       reg_ctrl |=  MXC_CSPICTRL_EN;
+       reg_write(&regs->ctrl, reg_ctrl);
 
        /*
         * The following computation is taken directly from Freescale's code.
@@ -174,9 +178,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
        reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
                MXC_CSPICTRL_POSTDIV(post_div);
 
-       /* always set to master mode */
-       reg_ctrl |= 1 << (cs + 4);
-
        /* We need to disable SPI before changing registers */
        reg_ctrl &= ~MXC_CSPICTRL_EN;
 

diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h
index 0965b8f8d6d97e4967f0b4cb9be10833769402d4..f5f115fa009269a1214cdac20f3053af7729436b 100644 (file)
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -148,7 +148,7 @@
 
 #define CONFIG_BOOTCOMMAND \
        "mmc dev ${mmcdev};" \
-       "if mmc rescan ${mmcdev}; then " \
+       "if mmc rescan; then " \
                "if run loadbootscript; then " \
                "run bootscript; " \
                "else " \