Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 21 Apr 2014 18:13:48 +0000 (20:13 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 21 Apr 2014 18:13:48 +0000 (20:13 +0200)
55 files changed:
arch/arm/cpu/arm720t/tegra-common/spl.c
arch/arm/cpu/arm720t/tegra114/cpu.c
arch/arm/cpu/arm720t/tegra124/cpu.c
arch/arm/cpu/tegra-common/Makefile
arch/arm/cpu/tegra-common/pinmux-common.c [new file with mode: 0644]
arch/arm/cpu/tegra114-common/funcmux.c
arch/arm/cpu/tegra114-common/pinmux.c
arch/arm/cpu/tegra124-common/funcmux.c
arch/arm/cpu/tegra124-common/pinmux.c
arch/arm/cpu/tegra20-common/emc.c
arch/arm/cpu/tegra20-common/funcmux.c
arch/arm/cpu/tegra20-common/pinmux.c
arch/arm/cpu/tegra20-common/warmboot.c
arch/arm/cpu/tegra20-common/warmboot_avp.c
arch/arm/cpu/tegra30-common/funcmux.c
arch/arm/cpu/tegra30-common/pinmux.c
arch/arm/dts/Makefile
arch/arm/dts/tegra124-jetson-tk1.dts [new file with mode: 0644]
arch/arm/include/asm/arch-tegra/apb_misc.h [moved from arch/arm/include/asm/arch-tegra20/apb_misc.h with 87% similarity]
arch/arm/include/asm/arch-tegra/board.h
arch/arm/include/asm/arch-tegra/pinmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra/usb.h
arch/arm/include/asm/arch-tegra114/pinmux.h
arch/arm/include/asm/arch-tegra114/usb.h [deleted file]
arch/arm/include/asm/arch-tegra124/pinmux.h
arch/arm/include/asm/arch-tegra124/usb.h [deleted file]
arch/arm/include/asm/arch-tegra20/pinmux.h
arch/arm/include/asm/arch-tegra20/usb.h [deleted file]
arch/arm/include/asm/arch-tegra30/pinmux.h
arch/arm/include/asm/arch-tegra30/usb.h [deleted file]
board/avionic-design/common/pinmux-config-tamonten-ng.h
board/avionic-design/common/tamonten-ng.c
board/avionic-design/common/tamonten.c
board/compal/paz00/paz00.c
board/compulab/trimslice/trimslice.c
board/nvidia/cardhu/cardhu.c
board/nvidia/cardhu/pinmux-config-cardhu.h
board/nvidia/common/board.c
board/nvidia/dalmore/dalmore.c
board/nvidia/dalmore/pinmux-config-dalmore.h
board/nvidia/harmony/harmony.c
board/nvidia/jetson-tk1/Makefile [new file with mode: 0644]
board/nvidia/jetson-tk1/jetson-tk1.c [new file with mode: 0644]
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h [new file with mode: 0644]
board/nvidia/seaboard/seaboard.c
board/nvidia/venice2/as3722_init.h
board/nvidia/venice2/pinmux-config-venice2.h
board/nvidia/venice2/venice2.c
board/toradex/colibri_t20-common/colibri_t20-common.c
board/toradex/colibri_t20_iris/colibri_t20_iris.c
boards.cfg
drivers/spi/tegra20_sflash.c
drivers/usb/host/ehci-tegra.c
drivers/video/tegra.c
include/configs/jetson-tk1.h [new file with mode: 0644]

index 5171a8f..3479541 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
+#include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch/spl.h>
 #include "cpu.h"
 
 void spl_board_init(void)
 {
-       struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       struct apb_misc_pp_ctlr *apb_misc =
+                               (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
 
        /* enable JTAG */
-       writel(0xC0, &pmt->pmt_cfg_ctl);
+       writel(0xC0, &apb_misc->cfg_ctl);
 
        board_init_uart_f();
 
index d10b96a..5ed3bb9 100644 (file)
@@ -34,8 +34,8 @@ static void enable_cpu_power_rail(void)
        debug("enable_cpu_power_rail entry\n");
 
        /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
-       pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
-       pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+       pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+       pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
 
        /*
         * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
index 97f5928..6ff6aeb 100644 (file)
@@ -26,8 +26,8 @@ static void enable_cpu_power_rail(void)
        debug("enable_cpu_power_rail entry\n");
 
        /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
-       pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
-       pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+       pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
+       pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
 
        pmic_enable_cpu_vdd();
 
index 34d5734..892556e 100644 (file)
@@ -7,6 +7,10 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
+obj-y += ap.o
+obj-y += board.o
+obj-y += cache.o
+obj-y += clock.o
 obj-y += lowlevel_init.o
-obj-y  += ap.o board.o clock.o cache.o
+obj-y += pinmux-common.o
 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
diff --git a/arch/arm/cpu/tegra-common/pinmux-common.c b/arch/arm/cpu/tegra-common/pinmux-common.c
new file mode 100644 (file)
index 0000000..d62618c
--- /dev/null
@@ -0,0 +1,508 @@
+/*
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+
+/* return 1 if a pingrp is in range */
+#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
+
+/* return 1 if a pmux_func is in range */
+#define pmux_func_isvalid(func) \
+       (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
+
+/* return 1 if a pin_pupd_is in range */
+#define pmux_pin_pupd_isvalid(pupd) \
+       (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
+
+/* return 1 if a pin_tristate_is in range */
+#define pmux_pin_tristate_isvalid(tristate) \
+       (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* return 1 if a pin_io_is in range */
+#define pmux_pin_io_isvalid(io) \
+       (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
+
+/* return 1 if a pin_lock is in range */
+#define pmux_pin_lock_isvalid(lock) \
+       (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
+
+/* return 1 if a pin_od is in range */
+#define pmux_pin_od_isvalid(od) \
+       (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
+
+/* return 1 if a pin_ioreset_is in range */
+#define pmux_pin_ioreset_isvalid(ioreset) \
+       (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
+        ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+       (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
+        ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+#define _R(offset)     (u32 *)(NV_PA_APB_MISC_BASE + (offset))
+
+#if defined(CONFIG_TEGRA20)
+
+#define MUX_REG(grp)   _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
+#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
+
+#define PULL_REG(grp)  _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
+#define PULL_SHIFT(grp)        ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
+
+#define TRI_REG(grp)   _R(0x14 + (((grp) / 32) * 4))
+#define TRI_SHIFT(grp) ((grp) % 32)
+
+#else
+
+#define REG(pin)       _R(0x3000 + ((pin) * 4))
+
+#define MUX_REG(pin)   REG(pin)
+#define MUX_SHIFT(pin) 0
+
+#define PULL_REG(pin)  REG(pin)
+#define PULL_SHIFT(pin)        2
+
+#define TRI_REG(pin)   REG(pin)
+#define TRI_SHIFT(pin) 4
+
+#endif /* CONFIG_TEGRA20 */
+
+#define DRV_REG(group) _R(0x868 + ((group) * 4))
+
+#define IO_SHIFT       5
+#define OD_SHIFT       6
+#define LOCK_SHIFT     7
+#define IO_RESET_SHIFT 8
+#define RCV_SEL_SHIFT  9
+
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
+{
+       u32 *reg = MUX_REG(pin);
+       int i, mux = -1;
+       u32 val;
+
+       /* Error check on pin and func */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_func_isvalid(func));
+
+       if (func >= PMUX_FUNC_RSVD1) {
+               mux = (func - PMUX_FUNC_RSVD1) & 3;
+       } else {
+               /* Search for the appropriate function */
+               for (i = 0; i < 4; i++) {
+                       if (tegra_soc_pingroups[pin].funcs[i] == func) {
+                               mux = i;
+                               break;
+                       }
+               }
+       }
+       assert(mux != -1);
+
+       val = readl(reg);
+       val &= ~(3 << MUX_SHIFT(pin));
+       val |= (mux << MUX_SHIFT(pin));
+       writel(val, reg);
+}
+
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
+{
+       u32 *reg = PULL_REG(pin);
+       u32 val;
+
+       /* Error check on pin and pupd */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_pupd_isvalid(pupd));
+
+       val = readl(reg);
+       val &= ~(3 << PULL_SHIFT(pin));
+       val |= (pupd << PULL_SHIFT(pin));
+       writel(val, reg);
+}
+
+static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
+{
+       u32 *reg = TRI_REG(pin);
+       u32 val;
+
+       /* Error check on pin */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_tristate_isvalid(tri));
+
+       val = readl(reg);
+       if (tri == PMUX_TRI_TRISTATE)
+               val |= (1 << TRI_SHIFT(pin));
+       else
+               val &= ~(1 << TRI_SHIFT(pin));
+       writel(val, reg);
+}
+
+void pinmux_tristate_enable(enum pmux_pingrp pin)
+{
+       pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
+}
+
+void pinmux_tristate_disable(enum pmux_pingrp pin)
+{
+       pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
+}
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
+{
+       u32 *reg = REG(pin);
+       u32 val;
+
+       if (io == PMUX_PIN_NONE)
+               return;
+
+       /* Error check on pin and io */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_io_isvalid(io));
+
+       val = readl(reg);
+       if (io == PMUX_PIN_INPUT)
+               val |= (io & 1) << IO_SHIFT;
+       else
+               val &= ~(1 << IO_SHIFT);
+       writel(val, reg);
+}
+
+static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
+{
+       u32 *reg = REG(pin);
+       u32 val;
+
+       if (lock == PMUX_PIN_LOCK_DEFAULT)
+               return;
+
+       /* Error check on pin and lock */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_lock_isvalid(lock));
+
+       val = readl(reg);
+       if (lock == PMUX_PIN_LOCK_ENABLE) {
+               val |= (1 << LOCK_SHIFT);
+       } else {
+               if (val & (1 << LOCK_SHIFT))
+                       printf("%s: Cannot clear LOCK bit!\n", __func__);
+               val &= ~(1 << LOCK_SHIFT);
+       }
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
+{
+       u32 *reg = REG(pin);
+       u32 val;
+
+       if (od == PMUX_PIN_OD_DEFAULT)
+               return;
+
+       /* Error check on pin and od */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_od_isvalid(od));
+
+       val = readl(reg);
+       if (od == PMUX_PIN_OD_ENABLE)
+               val |= (1 << OD_SHIFT);
+       else
+               val &= ~(1 << OD_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_ioreset(enum pmux_pingrp pin,
+                               enum pmux_pin_ioreset ioreset)
+{
+       u32 *reg = REG(pin);
+       u32 val;
+
+       if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
+               return;
+
+       /* Error check on pin and ioreset */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_ioreset_isvalid(ioreset));
+
+       val = readl(reg);
+       if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
+               val |= (1 << IO_RESET_SHIFT);
+       else
+               val &= ~(1 << IO_RESET_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
+                               enum pmux_pin_rcv_sel rcv_sel)
+{
+       u32 *reg = REG(pin);
+       u32 val;
+
+       if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+               return;
+
+       /* Error check on pin and rcv_sel */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+       val = readl(reg);
+       if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+               val |= (1 << RCV_SEL_SHIFT);
+       else
+               val &= ~(1 << RCV_SEL_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
+{
+       enum pmux_pingrp pin = config->pingrp;
+
+       pinmux_set_func(pin, config->func);
+       pinmux_set_pullupdown(pin, config->pull);
+       pinmux_set_tristate(pin, config->tristate);
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+       pinmux_set_io(pin, config->io);
+       pinmux_set_lock(pin, config->lock);
+       pinmux_set_od(pin, config->od);
+       pinmux_set_ioreset(pin, config->ioreset);
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+       pinmux_set_rcv_sel(pin, config->rcv_sel);
+#endif
+#endif
+}
+
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+                               int len)
+{
+       int i;
+
+       for (i = 0; i < len; i++)
+               pinmux_config_pingrp(&config[i]);
+}
+
+#ifdef TEGRA_PMX_HAS_DRVGRPS
+
+#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
+
+#define pmux_slw_isvalid(slw) \
+       (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
+
+#define pmux_drv_isvalid(drv) \
+       (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
+
+#define pmux_lpmd_isvalid(lpm) \
+       (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
+
+#define pmux_schmt_isvalid(schmt) \
+       (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
+
+#define pmux_hsm_isvalid(hsm) \
+       (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
+
+#define HSM_SHIFT      2
+#define SCHMT_SHIFT    3
+#define LPMD_SHIFT     4
+#define LPMD_MASK      (3 << LPMD_SHIFT)
+#define DRVDN_SHIFT    12
+#define DRVDN_MASK     (0x7F << DRVDN_SHIFT)
+#define DRVUP_SHIFT    20
+#define DRVUP_MASK     (0x7F << DRVUP_SHIFT)
+#define SLWR_SHIFT     28
+#define SLWR_MASK      (3 << SLWR_SHIFT)
+#define SLWF_SHIFT     30
+#define SLWF_MASK      (3 << SLWF_SHIFT)
+
+static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
+{
+       u32 *reg = DRV_REG(grp);
+       u32 val;
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwf == PMUX_SLWF_NONE)
+               return;
+
+       /* Error check on pad and slwf */
+       assert(pmux_drvgrp_isvalid(grp));
+       assert(pmux_slw_isvalid(slwf));
+
+       val = readl(reg);
+       val &= ~SLWF_MASK;
+       val |= (slwf << SLWF_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
+{
+       u32 *reg = DRV_REG(grp);
+       u32 val;
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwr == PMUX_SLWR_NONE)
+               return;
+
+       /* Error check on pad and slwr */
+       assert(pmux_drvgrp_isvalid(grp));
+       assert(pmux_slw_isvalid(slwr));
+
+       val = readl(reg);
+       val &= ~SLWR_MASK;
+       val |= (slwr << SLWR_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
+{
+       u32 *reg = DRV_REG(grp);
+       u32 val;
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvup == PMUX_DRVUP_NONE)
+               return;
+
+       /* Error check on pad and drvup */
+       assert(pmux_drvgrp_isvalid(grp));
+       assert(pmux_drv_isvalid(drvup));
+
+       val = readl(reg);
+       val &= ~DRVUP_MASK;
+       val |= (drvup << DRVUP_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
+{
+       u32 *reg = DRV_REG(grp);
+       u32 val;
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvdn == PMUX_DRVDN_NONE)
+               return;
+
+       /* Error check on pad and drvdn */
+       assert(pmux_drvgrp_isvalid(grp));
+       assert(pmux_drv_isvalid(drvdn));
+
+       val = readl(reg);
+       val &= ~DRVDN_MASK;
+       val |= (drvdn << DRVDN_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
+{
+       u32 *reg = DRV_REG(grp);
+       u32 val;
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (lpmd == PMUX_LPMD_NONE)
+               return;
+
+       /* Error check pad and lpmd value */
+       assert(pmux_drvgrp_isvalid(grp));
+       assert(pmux_lpmd_isvalid(lpmd));
+
+       val = readl(reg);
+       val &= ~LPMD_MASK;
+       val |= (lpmd << LPMD_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
+{
+       u32 *reg = DRV_REG(grp);
+       u32 val;
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (schmt == PMUX_SCHMT_NONE)
+               return;
+
+       /* Error check pad */
+       assert(pmux_drvgrp_isvalid(grp));
+       assert(pmux_schmt_isvalid(schmt));
+
+       val = readl(reg);
+       if (schmt == PMUX_SCHMT_ENABLE)
+               val |= (1 << SCHMT_SHIFT);
+       else
+               val &= ~(1 << SCHMT_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
+{
+       u32 *reg = DRV_REG(grp);
+       u32 val;
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (hsm == PMUX_HSM_NONE)
+               return;
+
+       /* Error check pad */
+       assert(pmux_drvgrp_isvalid(grp));
+       assert(pmux_hsm_isvalid(hsm));
+
+       val = readl(reg);
+       if (hsm == PMUX_HSM_ENABLE)
+               val |= (1 << HSM_SHIFT);
+       else
+               val &= ~(1 << HSM_SHIFT);
+       writel(val, reg);
+
+       return;
+}
+
+static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
+{
+       enum pmux_drvgrp grp = config->drvgrp;
+
+       pinmux_set_drvup_slwf(grp, config->slwf);
+       pinmux_set_drvdn_slwr(grp, config->slwr);
+       pinmux_set_drvup(grp, config->drvup);
+       pinmux_set_drvdn(grp, config->drvdn);
+       pinmux_set_lpmd(grp, config->lpmd);
+       pinmux_set_schmt(grp, config->schmt);
+       pinmux_set_hsm(grp, config->hsm);
+}
+
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+                               int len)
+{
+       int i;
+
+       for (i = 0; i < len; i++)
+               pinmux_config_drvgrp(&config[i]);
+}
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
index 5af7550..52441c7 100644 (file)
@@ -29,20 +29,24 @@ int funcmux_select(enum periph_id id, int config)
        case PERIPH_ID_UART4:
                switch (config) {
                case FUNCMUX_UART4_GMI:
-                       pinmux_set_func(PINGRP_GMI_A16, PMUX_FUNC_UARTD);
-                       pinmux_set_func(PINGRP_GMI_A17, PMUX_FUNC_UARTD);
-                       pinmux_set_func(PINGRP_GMI_A18, PMUX_FUNC_UARTD);
-                       pinmux_set_func(PINGRP_GMI_A19, PMUX_FUNC_UARTD);
-
-                       pinmux_set_io(PINGRP_GMI_A16, PMUX_PIN_OUTPUT);
-                       pinmux_set_io(PINGRP_GMI_A17, PMUX_PIN_INPUT);
-                       pinmux_set_io(PINGRP_GMI_A18, PMUX_PIN_INPUT);
-                       pinmux_set_io(PINGRP_GMI_A19, PMUX_PIN_OUTPUT);
-
-                       pinmux_tristate_disable(PINGRP_GMI_A16);
-                       pinmux_tristate_disable(PINGRP_GMI_A17);
-                       pinmux_tristate_disable(PINGRP_GMI_A18);
-                       pinmux_tristate_disable(PINGRP_GMI_A19);
+                       pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7,
+                                       PMUX_FUNC_UARTD);
+                       pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0,
+                                       PMUX_FUNC_UARTD);
+                       pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1,
+                                       PMUX_FUNC_UARTD);
+                       pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7,
+                                       PMUX_FUNC_UARTD);
+
+                       pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT);
+                       pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT);
+                       pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT);
+                       pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT);
+
+                       pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7);
+                       pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0);
+                       pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1);
+                       pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7);
                        break;
                }
                break;
index 4983a05..3e5acb9 100644 (file)
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
  */
 
-/* Tegra114 pin multiplexing functions */
-
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/tegra.h>
 #include <asm/arch/pinmux.h>
 
-struct tegra_pingroup_desc {
-       const char *name;
-       enum pmux_func funcs[4];
-       enum pmux_func func_safe;
-       enum pmux_vddio vddio;
-       enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT      0
-#define PMUX_PULL_SHIFT                2
-#define PMUX_TRISTATE_SHIFT    4
-#define PMUX_TRISTATE_MASK     (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT          5
-#define PMUX_OD_SHIFT          6
-#define PMUX_LOCK_SHIFT                7
-#define PMUX_IO_RESET_SHIFT    8
-#define PMUX_RCV_SEL_SHIFT     9
-
-#define PGRP_HSM_SHIFT         2
-#define PGRP_SCHMT_SHIFT       3
-#define PGRP_LPMD_SHIFT                4
-#define PGRP_LPMD_MASK         (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT       12
-#define PGRP_DRVDN_MASK                (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT       20
-#define PGRP_DRVUP_MASK                (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT                28
-#define PGRP_SLWR_MASK         (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT                30
-#define PGRP_SLWF_MASK         (3 << PGRP_SLWF_SHIFT)
-
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
-       {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
-               .funcs = {                              \
-                       PMUX_FUNC_ ## f0,               \
-                       PMUX_FUNC_ ## f1,               \
-                       PMUX_FUNC_ ## f2,               \
-                       PMUX_FUNC_ ## f3,               \
-               },                                      \
-               .func_safe = PMUX_FUNC_RSVD1,           \
-               .io = PMUX_PIN_ ## iod,                 \
+#define PIN(pin, f0, f1, f2, f3)       \
+       {                               \
+               .funcs = {              \
+                       PMUX_FUNC_##f0, \
+                       PMUX_FUNC_##f1, \
+                       PMUX_FUNC_##f2, \
+                       PMUX_FUNC_##f3, \
+               },                      \
        }
 
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
-       PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
-       PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
-       PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+#define PIN_RESERVED {}
 
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
-       /*      NAME      VDD      f0           f1         f2       f3  */
-       PINI(ULPI_DATA0,  BB,      SPI3,       HSI,        UARTA,   ULPI),
-       PINI(ULPI_DATA1,  BB,      SPI3,       HSI,        UARTA,   ULPI),
-       PINI(ULPI_DATA2,  BB,      SPI3,       HSI,        UARTA,   ULPI),
-       PINI(ULPI_DATA3,  BB,      SPI3,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA4,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA5,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA6,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA7,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_CLK,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(ULPI_DIR,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(ULPI_NXT,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(ULPI_STP,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(DAP3_FS,     BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(DAP3_DIN,    BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(DAP3_DOUT,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(DAP3_SCLK,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(GPIO_PV0,    BB,      USB,        RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_PV1,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,     CLK12,      RSVD3,   RSVD4),
-       PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
-       PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
-       PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,     PWM0,       SPI4,    UARTA),
-       PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,     PWM1,       SPI4,    UARTA),
-       PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,     RSVD2,      SPI4,    UARTA),
-       PIN_RESERVED,   /* Reserved by t114: 0x3060 - 0x3064 */
+static const struct pmux_pingrp_desc tegra114_pingroups[] = {
+       /*  pin,                    f0,         f1,       f2,           f3 */
+       /* Offset 0x3000 */
+       PIN(ULPI_DATA0_PO1,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA1_PO2,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA2_PO3,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA3_PO4,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA4_PO5,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA5_PO6,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA6_PO7,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA7_PO0,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_CLK_PY0,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(ULPI_DIR_PY1,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(ULPI_NXT_PY2,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(ULPI_STP_PY3,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(DAP3_FS_PP0,            I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+       PIN(DAP3_DIN_PP1,           I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+       PIN(DAP3_DOUT_PP2,          I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+       PIN(DAP3_SCLK_PP3,          I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+       PIN(PV0,                    USB,        RSVD2,    RSVD3,        RSVD4),
+       PIN(PV1,                    RSVD1,      RSVD2,    RSVD3,        RSVD4),
+       PIN(SDMMC1_CLK_PZ0,         SDMMC1,     CLK12,    RSVD3,        RSVD4),
+       PIN(SDMMC1_CMD_PZ1,         SDMMC1,     SPDIF,    SPI4,         UARTA),
+       PIN(SDMMC1_DAT3_PY4,        SDMMC1,     SPDIF,    SPI4,         UARTA),
+       PIN(SDMMC1_DAT2_PY5,        SDMMC1,     PWM0,     SPI4,         UARTA),
+       PIN(SDMMC1_DAT1_PY6,        SDMMC1,     PWM1,     SPI4,         UARTA),
+       PIN(SDMMC1_DAT0_PY7,        SDMMC1,     RSVD2,    SPI4,         UARTA),
+       PIN_RESERVED,
        PIN_RESERVED,
-       PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2, RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK2_REQ,    SDMMC1,  DAP,        RSVD2,      RSVD3,   RSVD4),
-       PIN_RESERVED,   /* Reserved by t114: 0x3070 - 0x310c */
+       /* Offset 0x3068 */
+       PIN(CLK2_OUT_PW5,           EXTPERIPH2, RSVD2,    RSVD3,        RSVD4),
+       PIN(CLK2_REQ_PCC5,          DAP,        RSVD2,    RSVD3,        RSVD4),
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
@@ -146,11 +91,11 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
-       PINI(HDMI_INT,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(DDC_SCL,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(DDC_SDA,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
-       PIN_RESERVED,   /* Reserved by t114: 0x311c - 0x3160 */
        PIN_RESERVED,
+       /* Offset 0x3110 */
+       PIN(HDMI_INT_PN7,           RSVD1,      RSVD2,    RSVD3,        RSVD4),
+       PIN(DDC_SCL_PV4,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+       PIN(DDC_SDA_PV5,            I2C4,       RSVD2,    RSVD3,        RSVD4),
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
@@ -167,574 +112,182 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
-       PINI(UART2_RXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
-       PINI(UART2_TXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
-       PINI(UART2_RTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
-       PINI(UART2_CTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
-       PINI(UART3_TXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
-       PINI(UART3_RXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
-       PINI(UART3_CTS_N, UART,    UARTC,      SDMMC1,     DTV,     SPI4),
-       PINI(UART3_RTS_N, UART,    UARTC,      PWM0,       DTV,     DISPA),
-       PINI(GPIO_PU0,    UART,    OWR,        UARTA,      RSVD3,   RSVD4),
-       PINI(GPIO_PU1,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
-       PINI(GPIO_PU2,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
-       PINI(GPIO_PU3,    UART,    PWM0,       UARTA,      DISPA,   DISPB),
-       PINI(GPIO_PU4,    UART,    PWM1,       UARTA,      DISPA,   DISPB),
-       PINI(GPIO_PU5,    UART,    PWM2,       UARTA,      DISPA,   DISPB),
-       PINI(GPIO_PU6,    UART,    PWM3,       UARTA,      USB,     DISPB),
-       PINI(GEN1_I2C_SDA, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GEN1_I2C_SCL, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP4_FS,     UART,    I2S3,       RSVD2,      DTV,     RSVD4),
-       PINI(DAP4_DIN,    UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP4_DOUT,   UART,    I2S3,       RSVD2,      DTV,     RSVD4),
-       PINI(DAP4_SCLK,   UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK3_OUT,    UART,    EXTPERIPH3, RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK3_REQ,    UART,    DEV3,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GMI_WP_N,    GMI,     RSVD1,      NAND,       GMI,     GMI_ALT),
-       PINI(GMI_IORDY,   GMI,     SDMMC2,     RSVD2,      GMI,     TRACE),
-       PINI(GMI_WAIT,    GMI,     SPI4,       NAND,       GMI,     DTV),
-       PINI(GMI_ADV_N,   GMI,     RSVD1,      NAND,       GMI,     TRACE),
-       PINI(GMI_CLK,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
-       PINI(GMI_CS0_N,   GMI,     RSVD1,      NAND,       GMI,     USB),
-       PINI(GMI_CS1_N,   GMI,     RSVD1,      NAND,       GMI,     SOC),
-       PINI(GMI_CS2_N,   GMI,     SDMMC2,     NAND,       GMI,     TRACE),
-       PINI(GMI_CS3_N,   GMI,     SDMMC2,     NAND,       GMI,     GMI_ALT),
-       PINI(GMI_CS4_N,   GMI,     USB,        NAND,       GMI,     TRACE),
-       PINI(GMI_CS6_N,   GMI,     NAND,       NAND_ALT,   GMI,     SPI4),
-       PINI(GMI_CS7_N,   GMI,     NAND,       NAND_ALT,   GMI,     SDMMC2),
-       PINI(GMI_AD0,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD1,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD2,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD3,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD4,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD5,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_AD6,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_AD7,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_AD8,     GMI,     PWM0,       NAND,       GMI,     DTV),
-       PINI(GMI_AD9,     GMI,     PWM1,       NAND,       GMI,     CLDVFS),
-       PINI(GMI_AD10,    GMI,     PWM2,       NAND,       GMI,     CLDVFS),
-       PINI(GMI_AD11,    GMI,     PWM3,       NAND,       GMI,     USB),
-       PINI(GMI_AD12,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
-       PINI(GMI_AD13,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
-       PINI(GMI_AD14,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
-       PINI(GMI_AD15,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
-       PINI(GMI_A16,     GMI,     UARTD,      TRACE,      GMI,     GMI_ALT),
-       PINI(GMI_A17,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
-       PINI(GMI_A18,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
-       PINI(GMI_A19,     GMI,     UARTD,      SPI4,       GMI,     TRACE),
-       PINI(GMI_WR_N,    GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_OE_N,    GMI,     RSVD1,      NAND,       GMI,     SOC),
-       PINI(GMI_DQS,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
-       PINI(GMI_RST_N,   GMI,     NAND,       NAND_ALT,   GMI,     RSVD4),
-       PINI(GEN2_I2C_SCL, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
-       PINI(GEN2_I2C_SDA, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
-       PINI(SDMMC4_CLK,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
-       PINI(SDMMC4_CMD,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
-       PINI(SDMMC4_DAT0, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT1, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT2, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT3, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT4, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT5, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT6, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT7, SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
-       PIN_RESERVED,   /* Reserved by t114: 0x3280 */
-       PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT3, RSVD4),
-       PINI(GPIO_PCC1,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_PBB0,   CAM,     I2S4,       VI,         VI_ALT1, VI_ALT3),
-       PINI(CAM_I2C_SCL, CAM,     VGP1,       I2C3,       RSVD3,   RSVD4),
-       PINI(CAM_I2C_SDA, CAM,     VGP2,       I2C3,       RSVD3,   RSVD4),
-       PINI(GPIO_PBB3,   CAM,     VGP3,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB4,   CAM,     VGP4,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB5,   CAM,     VGP5,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB6,   CAM,     VGP6,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB7,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_PCC2,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(JTAG_RTCK,   SYS,     RTCK,       RSVD2,      RSVD3,   RSVD4),
-       PINI(PWR_I2C_SCL, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
-       PINI(PWR_I2C_SDA, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
-       PINI(KB_ROW0,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
-       PINI(KB_ROW1,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
-       PINI(KB_ROW2,     SYS,     KBC,        RSVD2,      DTV,     SOC),
-       PINI(KB_ROW3,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
-       PINI(KB_ROW4,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
-       PINI(KB_ROW5,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
-       PINI(KB_ROW6,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
-       PINI(KB_ROW7,     SYS,     KBC,        RSVD2,      CLDVFS,  UARTA),
-       PINI(KB_ROW8,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
-       PINI(KB_ROW9,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
-       PINI(KB_ROW10,    SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
-       PIN_RESERVED,   /* Reserved by t114: 0x32e8 - 0x32f8 */
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PINI(KB_COL0,     SYS,     KBC,        USB,        SPI2,    EMC_DLL),
-       PINI(KB_COL1,     SYS,     KBC,        RSVD2,      SPI2,    EMC_DLL),
-       PINI(KB_COL2,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
-       PINI(KB_COL3,     SYS,     KBC,        DISPA,      PWM2,    UARTA),
-       PINI(KB_COL4,     SYS,     KBC,        OWR,        SDMMC3,  UARTA),
-       PINI(KB_COL5,     SYS,     KBC,        RSVD2,      SDMMC1,  RSVD4),
-       PINI(KB_COL6,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
-       PINI(KB_COL7,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
-       PINI(CLK_32K_OUT, SYS,     BLINK,      SOC,        RSVD3,   RSVD4),
-       PINI(SYS_CLK_REQ, SYS,     SYSCLK,     RSVD2,      RSVD3,   RSVD4),
-       PINI(CORE_PWR_REQ, SYS,    PWRON,      RSVD2,      RSVD3,   RSVD4),
-       PINI(CPU_PWR_REQ, SYS,     CPU,        RSVD2,      RSVD3,   RSVD4),
-       PINI(PWR_INT_N,   SYS,     PMI,        RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK_32K_IN,  SYS,     CLK,        RSVD2,      RSVD3,   RSVD4),
-       PINI(OWR,         SYS,     OWR,        RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP1_FS,     AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(DAP1_DIN,    AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(DAP1_DOUT,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(DAP1_SCLK,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(CLK1_REQ,    AUDIO,   DAP,        DAP1,       RSVD3,   RSVD4),
-       PINI(CLK1_OUT,    AUDIO,   EXTPERIPH1, DAP2,       RSVD3,   RSVD4),
-       PINI(SPDIF_IN,    AUDIO,   SPDIF,      USB,        RSVD3,   RSVD4),
-       PINI(SPDIF_OUT,   AUDIO,   SPDIF,      RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP2_FS,     AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DAP2_DIN,    AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DAP2_DOUT,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DAP2_SCLK,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DVFS_PWM,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
-       PINI(GPIO_X1_AUD, AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_X3_AUD, AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
-       PINI(DVFS_CLK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
-       PINI(GPIO_X4_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
-       PINI(GPIO_X5_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
-       PINI(GPIO_X6_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
-       PINI(GPIO_X7_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
-       PIN_RESERVED,   /* Reserved by t114: 0x3388 - 0x338c */
-       PIN_RESERVED,
-       PINI(SDMMC3_CLK,  SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
-       PINI(SDMMC3_CMD,  SDMMC3,  SDMMC3,     PWM3,       UARTA,   SPI3),
-       PINI(SDMMC3_DAT0, SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
-       PINI(SDMMC3_DAT1, SDMMC3,  SDMMC3,     PWM2,       UARTA,   SPI3),
-       PINI(SDMMC3_DAT2, SDMMC3,  SDMMC3,     PWM1,       DISPA,   SPI3),
-       PINI(SDMMC3_DAT3, SDMMC3,  SDMMC3,     PWM0,       DISPB,   SPI3),
-       PIN_RESERVED,   /* Reserved by t114: 0x33a8 - 0x33dc */
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PINI(HDMI_CEC,    SYS,     CEC,        SDMMC3,     RSVD3,   SOC),
-       PINI(SDMMC1_WP_N, SDMMC1,  SDMMC1,     CLK12,      SPI4,    UARTA),
-       PINI(SDMMC3_CD_N, SYS,  SDMMC3,     OWR,        RSVD3,   RSVD4),
-       PINI(GPIO_W2_AUD, AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
-       PINI(GPIO_W3_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
-       PINI(USB_VBUS_EN0, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
-       PINI(USB_VBUS_EN1, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
-       PINI(SDMMC3_CLK_LB_IN,  SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
-       PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
-       PIN_RESERVED,   /* Reserved by t114: 0x3404 */
-       PINO(RESET_OUT_N, SYS,     RSVD1,      RSVD2,      RSVD3, RESET_OUT_N),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x3164 */
+       PIN(UART2_RXD_PC3,          IRDA,       SPDIF,    UARTA,        SPI4),
+       PIN(UART2_TXD_PC2,          IRDA,       SPDIF,    UARTA,        SPI4),
+       PIN(UART2_RTS_N_PJ6,        UARTA,      UARTB,    RSVD3,        SPI4),
+       PIN(UART2_CTS_N_PJ5,        UARTA,      UARTB,    RSVD3,        SPI4),
+       PIN(UART3_TXD_PW6,          UARTC,      RSVD2,    RSVD3,        SPI4),
+       PIN(UART3_RXD_PW7,          UARTC,      RSVD2,    RSVD3,        SPI4),
+       PIN(UART3_CTS_N_PA1,        UARTC,      SDMMC1,   DTV,          SPI4),
+       PIN(UART3_RTS_N_PC0,        UARTC,      PWM0,     DTV,          DISPLAYA),
+       PIN(PU0,                    OWR,        UARTA,    RSVD3,        RSVD4),
+       PIN(PU1,                    RSVD1,      UARTA,    RSVD3,        RSVD4),
+       PIN(PU2,                    RSVD1,      UARTA,    RSVD3,        RSVD4),
+       PIN(PU3,                    PWM0,       UARTA,    DISPLAYA,     DISPLAYB),
+       PIN(PU4,                    PWM1,       UARTA,    DISPLAYA,     DISPLAYB),
+       PIN(PU5,                    PWM2,       UARTA,    DISPLAYA,     DISPLAYB),
+       PIN(PU6,                    PWM3,       UARTA,    USB,          DISPLAYB),
+       PIN(GEN1_I2C_SDA_PC5,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+       PIN(GEN1_I2C_SCL_PC4,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+       PIN(DAP4_FS_PP4,            I2S3,       RSVD2,    DTV,          RSVD4),
+       PIN(DAP4_DIN_PP5,           I2S3,       RSVD2,    RSVD3,        RSVD4),
+       PIN(DAP4_DOUT_PP6,          I2S3,       RSVD2,    DTV,          RSVD4),
+       PIN(DAP4_SCLK_PP7,          I2S3,       RSVD2,    RSVD3,        RSVD4),
+       PIN(CLK3_OUT_PEE0,          EXTPERIPH3, RSVD2,    RSVD3,        RSVD4),
+       PIN(CLK3_REQ_PEE1,          DEV3,       RSVD2,    RSVD3,        RSVD4),
+       PIN(GMI_WP_N_PC7,           RSVD1,      NAND,     GMI,          GMI_ALT),
+       PIN(GMI_IORDY_PI5,          SDMMC2,     RSVD2,    GMI,          TRACE),
+       PIN(GMI_WAIT_PI7,           SPI4,       NAND,     GMI,          DTV),
+       PIN(GMI_ADV_N_PK0,          RSVD1,      NAND,     GMI,          TRACE),
+       PIN(GMI_CLK_PK1,            SDMMC2,     NAND,     GMI,          TRACE),
+       PIN(GMI_CS0_N_PJ0,          RSVD1,      NAND,     GMI,          USB),
+       PIN(GMI_CS1_N_PJ2,          RSVD1,      NAND,     GMI,          SOC),
+       PIN(GMI_CS2_N_PK3,          SDMMC2,     NAND,     GMI,          TRACE),
+       PIN(GMI_CS3_N_PK4,          SDMMC2,     NAND,     GMI,          GMI_ALT),
+       PIN(GMI_CS4_N_PK2,          USB,        NAND,     GMI,          TRACE),
+       PIN(GMI_CS6_N_PI3,          NAND,       NAND_ALT, GMI,          SPI4),
+       PIN(GMI_CS7_N_PI6,          NAND,       NAND_ALT, GMI,          SDMMC2),
+       PIN(GMI_AD0_PG0,            RSVD1,      NAND,     GMI,          RSVD4),
+       PIN(GMI_AD1_PG1,            RSVD1,      NAND,     GMI,          RSVD4),
+       PIN(GMI_AD2_PG2,            RSVD1,      NAND,     GMI,          RSVD4),
+       PIN(GMI_AD3_PG3,            RSVD1,      NAND,     GMI,          RSVD4),
+       PIN(GMI_AD4_PG4,            RSVD1,      NAND,     GMI,          RSVD4),
+       PIN(GMI_AD5_PG5,            RSVD1,      NAND,     GMI,          SPI4),
+       PIN(GMI_AD6_PG6,            RSVD1,      NAND,     GMI,          SPI4),
+       PIN(GMI_AD7_PG7,            RSVD1,      NAND,     GMI,          SPI4),
+       PIN(GMI_AD8_PH0,            PWM0,       NAND,     GMI,          DTV),
+       PIN(GMI_AD9_PH1,            PWM1,       NAND,     GMI,          CLDVFS),
+       PIN(GMI_AD10_PH2,           PWM2,       NAND,     GMI,          CLDVFS),
+       PIN(GMI_AD11_PH3,           PWM3,       NAND,     GMI,          USB),
+       PIN(GMI_AD12_PH4,           SDMMC2,     NAND,     GMI,          RSVD4),
+       PIN(GMI_AD13_PH5,           SDMMC2,     NAND,     GMI,          RSVD4),
+       PIN(GMI_AD14_PH6,           SDMMC2,     NAND,     GMI,          DTV),
+       PIN(GMI_AD15_PH7,           SDMMC2,     NAND,     GMI,          DTV),
+       PIN(GMI_A16_PJ7,            UARTD,      TRACE,    GMI,          GMI_ALT),
+       PIN(GMI_A17_PB0,            UARTD,      RSVD2,    GMI,          TRACE),
+       PIN(GMI_A18_PB1,            UARTD,      RSVD2,    GMI,          TRACE),
+       PIN(GMI_A19_PK7,            UARTD,      SPI4,     GMI,          TRACE),
+       PIN(GMI_WR_N_PI0,           RSVD1,      NAND,     GMI,          SPI4),
+       PIN(GMI_OE_N_PI1,           RSVD1,      NAND,     GMI,          SOC),
+       PIN(GMI_DQS_P_PJ3,          SDMMC2,     NAND,     GMI,          TRACE),
+       PIN(GMI_RST_N_PI4,          NAND,       NAND_ALT, GMI,          RSVD4),
+       PIN(GEN2_I2C_SCL_PT5,       I2C2,       RSVD2,    GMI,          RSVD4),
+       PIN(GEN2_I2C_SDA_PT6,       I2C2,       RSVD2,    GMI,          RSVD4),
+       PIN(SDMMC4_CLK_PCC4,        SDMMC4,     RSVD2,    GMI,          RSVD4),
+       PIN(SDMMC4_CMD_PT7,         SDMMC4,     RSVD2,    GMI,          RSVD4),
+       PIN(SDMMC4_DAT0_PAA0,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT1_PAA1,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT2_PAA2,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT3_PAA3,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT4_PAA4,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT5_PAA5,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT6_PAA6,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT7_PAA7,       SDMMC4,     RSVD2,    GMI,          RSVD4),
+       PIN_RESERVED,
+       /* Offset 0x3284 */
+       PIN(CAM_MCLK_PCC0,          VI,         VI_ALT1,  VI_ALT3,      RSVD4),
+       PIN(PCC1,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+       PIN(PBB0,                   I2S4,       VI,       VI_ALT1,      VI_ALT3),
+       PIN(CAM_I2C_SCL_PBB1,       VGP1,       I2C3,     RSVD3,        RSVD4),
+       PIN(CAM_I2C_SDA_PBB2,       VGP2,       I2C3,     RSVD3,        RSVD4),
+       PIN(PBB3,                   VGP3,       DISPLAYA, DISPLAYB,     RSVD4),
+       PIN(PBB4,                   VGP4,       DISPLAYA, DISPLAYB,     RSVD4),
+       PIN(PBB5,                   VGP5,       DISPLAYA, DISPLAYB,     RSVD4),
+       PIN(PBB6,                   VGP6,       DISPLAYA, DISPLAYB,     RSVD4),
+       PIN(PBB7,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+       PIN(PCC2,                   I2S4,       RSVD2,    RSVD3,        RSVD4),
+       PIN(JTAG_RTCK,              RTCK,       RSVD2,    RSVD3,        RSVD4),
+       PIN(PWR_I2C_SCL_PZ6,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+       PIN(PWR_I2C_SDA_PZ7,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW0_PR0,            KBC,        RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW1_PR1,            KBC,        RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW2_PR2,            KBC,        RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW3_PR3,            KBC,        DISPLAYA, RSVD3,        DISPLAYB),
+       PIN(KB_ROW4_PR4,            KBC,        DISPLAYA, SPI2,         DISPLAYB),
+       PIN(KB_ROW5_PR5,            KBC,        DISPLAYA, SPI2,         DISPLAYB),
+       PIN(KB_ROW6_PR6,            KBC,        DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+       PIN(KB_ROW7_PR7,            KBC,        RSVD2,    CLDVFS,       UARTA),
+       PIN(KB_ROW8_PS0,            KBC,        RSVD2,    CLDVFS,       UARTA),
+       PIN(KB_ROW9_PS1,            KBC,        RSVD2,    RSVD3,        UARTA),
+       PIN(KB_ROW10_PS2,           KBC,        RSVD2,    RSVD3,        UARTA),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x32fc */
+       PIN(KB_COL0_PQ0,            KBC,        USB,      SPI2,         EMC_DLL),
+       PIN(KB_COL1_PQ1,            KBC,        RSVD2,    SPI2,         EMC_DLL),
+       PIN(KB_COL2_PQ2,            KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(KB_COL3_PQ3,            KBC,        DISPLAYA, PWM2,         UARTA),
+       PIN(KB_COL4_PQ4,            KBC,        OWR,      SDMMC3,       UARTA),
+       PIN(KB_COL5_PQ5,            KBC,        RSVD2,    SDMMC1,       RSVD4),
+       PIN(KB_COL6_PQ6,            KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(KB_COL7_PQ7,            KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(CLK_32K_OUT_PA0,        BLINK,      SOC,      RSVD3,        RSVD4),
+       PIN(SYS_CLK_REQ_PZ5,        SYSCLK,     RSVD2,    RSVD3,        RSVD4),
+       PIN(CORE_PWR_REQ,           PWRON,      RSVD2,    RSVD3,        RSVD4),
+       PIN(CPU_PWR_REQ,            CPU,        RSVD2,    RSVD3,        RSVD4),
+       PIN(PWR_INT_N,              PMI,        RSVD2,    RSVD3,        RSVD4),
+       PIN(CLK_32K_IN,             CLK,        RSVD2,    RSVD3,        RSVD4),
+       PIN(OWR,                    OWR,        RSVD2,    RSVD3,        RSVD4),
+       PIN(DAP1_FS_PN0,            I2S0,       HDA,      GMI,          RSVD4),
+       PIN(DAP1_DIN_PN1,           I2S0,       HDA,      GMI,          RSVD4),
+       PIN(DAP1_DOUT_PN2,          I2S0,       HDA,      GMI,          RSVD4),
+       PIN(DAP1_SCLK_PN3,          I2S0,       HDA,      GMI,          RSVD4),
+       PIN(CLK1_REQ_PEE2,          DAP,        DAP1,     RSVD3,        RSVD4),
+       PIN(CLK1_OUT_PW4,           EXTPERIPH1, DAP2,     RSVD3,        RSVD4),
+       PIN(SPDIF_IN_PK6,           SPDIF,      USB,      RSVD3,        RSVD4),
+       PIN(SPDIF_OUT_PK5,          SPDIF,      RSVD2,    RSVD3,        RSVD4),
+       PIN(DAP2_FS_PA2,            I2S1,       HDA,      RSVD3,        RSVD4),
+       PIN(DAP2_DIN_PA4,           I2S1,       HDA,      RSVD3,        RSVD4),
+       PIN(DAP2_DOUT_PA5,          I2S1,       HDA,      RSVD3,        RSVD4),
+       PIN(DAP2_SCLK_PA3,          I2S1,       HDA,      RSVD3,        RSVD4),
+       PIN(DVFS_PWM_PX0,           SPI6,       CLDVFS,   RSVD3,        RSVD4),
+       PIN(GPIO_X1_AUD_PX1,        SPI6,       RSVD2,    RSVD3,        RSVD4),
+       PIN(GPIO_X3_AUD_PX3,        SPI6,       SPI1,     RSVD3,        RSVD4),
+       PIN(DVFS_CLK_PX2,           SPI6,       CLDVFS,   RSVD3,        RSVD4),
+       PIN(GPIO_X4_AUD_PX4,        RSVD1,      SPI1,     SPI2,         DAP2),
+       PIN(GPIO_X5_AUD_PX5,        RSVD1,      SPI1,     SPI2,         RSVD4),
+       PIN(GPIO_X6_AUD_PX6,        SPI6,       SPI1,     SPI2,         RSVD4),
+       PIN(GPIO_X7_AUD_PX7,        RSVD1,      SPI1,     SPI2,         RSVD4),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x3390 */
+       PIN(SDMMC3_CLK_PA6,         SDMMC3,     RSVD2,    RSVD3,        SPI3),
+       PIN(SDMMC3_CMD_PA7,         SDMMC3,     PWM3,     UARTA,        SPI3),
+       PIN(SDMMC3_DAT0_PB7,        SDMMC3,     RSVD2,    RSVD3,        SPI3),
+       PIN(SDMMC3_DAT1_PB6,        SDMMC3,     PWM2,     UARTA,        SPI3),
+       PIN(SDMMC3_DAT2_PB5,        SDMMC3,     PWM1,     DISPLAYA,     SPI3),
+       PIN(SDMMC3_DAT3_PB4,        SDMMC3,     PWM0,     DISPLAYB,     SPI3),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x33e0 */
+       PIN(HDMI_CEC_PEE3,          CEC,        SDMMC3,   RSVD3,        SOC),
+       PIN(SDMMC1_WP_N_PV3,        SDMMC1,     CLK12,    SPI4,         UARTA),
+       PIN(SDMMC3_CD_N_PV2,        SDMMC3,     OWR,      RSVD3,        RSVD4),
+       PIN(GPIO_W2_AUD_PW2,        SPI6,       RSVD2,    SPI2,         I2C1),
+       PIN(GPIO_W3_AUD_PW3,        SPI6,       SPI1,     SPI2,         I2C1),
+       PIN(USB_VBUS_EN0_PN4,       USB,        RSVD2,    RSVD3,        RSVD4),
+       PIN(USB_VBUS_EN1_PN5,       USB,        RSVD2,    RSVD3,        RSVD4),
+       PIN(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+       PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+       PIN(GMI_CLK_LB,             SDMMC2,     NAND,     GMI,          RSVD4),
+       PIN(RESET_OUT_N,            RSVD1,      RSVD2,    RSVD3,        RESET_OUT_N),
 };
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *tri = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin */
-       assert(pmux_pingrp_isvalid(pin));
-
-       reg = readl(tri);
-       if (enable)
-               reg |= PMUX_TRISTATE_MASK;
-       else
-               reg &= ~PMUX_TRISTATE_MASK;
-       writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pull = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and pupd */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_pupd_isvalid(pupd));
-
-       reg = readl(pull);
-       reg &= ~(0x3 << PMUX_PULL_SHIFT);
-       reg |= (pupd << PMUX_PULL_SHIFT);
-       writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *muxctl = &pmt->pmt_ctl[pin];
-       int i, mux = -1;
-       u32 reg;
-
-       /* Error check on pin and func */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_func_isvalid(func));
-
-       /* Handle special values */
-       if (func == PMUX_FUNC_SAFE)
-               func = tegra_soc_pingroups[pin].func_safe;
-
-       if (func & PMUX_FUNC_RSVD1) {
-               mux = func & 0x3;
-       } else {
-               /* Search for the appropriate function */
-               for (i = 0; i < 4; i++) {
-                       if (tegra_soc_pingroups[pin].funcs[i] == func) {
-                               mux = i;
-                               break;
-                       }
-               }
-       }
-       assert(mux != -1);
-
-       reg = readl(muxctl);
-       reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
-       reg |= (mux << PMUX_MUXCTL_SHIFT);
-       writel(reg, muxctl);
-
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_io = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and io */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_io_isvalid(io));
-
-       reg = readl(pin_io);
-       reg &= ~(0x1 << PMUX_IO_SHIFT);
-       reg |= (io & 0x1) << PMUX_IO_SHIFT;
-       writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_lock = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and lock */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_lock_isvalid(lock));
-
-       if (lock == PMUX_PIN_LOCK_DEFAULT)
-               return 0;
-
-       reg = readl(pin_lock);
-       reg &= ~(0x1 << PMUX_LOCK_SHIFT);
-       if (lock == PMUX_PIN_LOCK_ENABLE)
-               reg |= (0x1 << PMUX_LOCK_SHIFT);
-       else {
-               /* lock == DISABLE, which isn't possible */
-               printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
-                       __func__, lock);
-       }
-       writel(reg, pin_lock);
-
-       return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_od = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and od */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_od_isvalid(od));
-
-       if (od == PMUX_PIN_OD_DEFAULT)
-               return 0;
-
-       reg = readl(pin_od);
-       reg &= ~(0x1 << PMUX_OD_SHIFT);
-       if (od == PMUX_PIN_OD_ENABLE)
-               reg |= (0x1 << PMUX_OD_SHIFT);
-       writel(reg, pin_od);
-
-       return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
-                               enum pmux_pin_ioreset ioreset)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_ioreset = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and ioreset */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_ioreset_isvalid(ioreset));
-
-       if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
-               return 0;
-
-       reg = readl(pin_ioreset);
-       reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
-       if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
-               reg |= (0x1 << PMUX_IO_RESET_SHIFT);
-       writel(reg, pin_ioreset);
-
-       return 0;
-}
-
-static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
-                               enum pmux_pin_rcv_sel rcv_sel)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and rcv_sel */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
-       if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
-               return 0;
-
-       reg = readl(pin_rcv_sel);
-       reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
-       if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
-               reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
-       writel(reg, pin_rcv_sel);
-
-       return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
-       enum pmux_pingrp pin = config->pingroup;
-
-       pinmux_set_func(pin, config->func);
-       pinmux_set_pullupdown(pin, config->pull);
-       pinmux_set_tristate(pin, config->tristate);
-       pinmux_set_io(pin, config->io);
-       pinmux_set_lock(pin, config->lock);
-       pinmux_set_od(pin, config->od);
-       pinmux_set_ioreset(pin, config->ioreset);
-       pinmux_set_rcv_sel(pin, config->rcv_sel);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++)
-               pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_slwf = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and slwf */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_slw_isvalid(slwf));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (slwf == PGRP_SLWF_NONE)
-               return 0;
-
-       reg = readl(pad_slwf);
-       reg &= ~PGRP_SLWF_MASK;
-       reg |= (slwf << PGRP_SLWF_SHIFT);
-       writel(reg, pad_slwf);
-
-       return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_slwr = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and slwr */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_slw_isvalid(slwr));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (slwr == PGRP_SLWR_NONE)
-               return 0;
-
-       reg = readl(pad_slwr);
-       reg &= ~PGRP_SLWR_MASK;
-       reg |= (slwr << PGRP_SLWR_SHIFT);
-       writel(reg, pad_slwr);
-
-       return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_drvup = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and drvup */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_drv_isvalid(drvup));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (drvup == PGRP_DRVUP_NONE)
-               return 0;
-
-       reg = readl(pad_drvup);
-       reg &= ~PGRP_DRVUP_MASK;
-       reg |= (drvup << PGRP_DRVUP_SHIFT);
-       writel(reg, pad_drvup);
-
-       return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_drvdn = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and drvdn */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_drv_isvalid(drvdn));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (drvdn == PGRP_DRVDN_NONE)
-               return 0;
-
-       reg = readl(pad_drvdn);
-       reg &= ~PGRP_DRVDN_MASK;
-       reg |= (drvdn << PGRP_DRVDN_SHIFT);
-       writel(reg, pad_drvdn);
-
-       return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_lpmd = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad and lpmd value */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_lpmd_isvalid(lpmd));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (lpmd == PGRP_LPMD_NONE)
-               return 0;
-
-       reg = readl(pad_lpmd);
-       reg &= ~PGRP_LPMD_MASK;
-       reg |= (lpmd << PGRP_LPMD_SHIFT);
-       writel(reg, pad_lpmd);
-
-       return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_schmt = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad */
-       assert(pmux_padgrp_isvalid(pad));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (schmt == PGRP_SCHMT_NONE)
-               return 0;
-
-       reg = readl(pad_schmt);
-       reg &= ~(1 << PGRP_SCHMT_SHIFT);
-       if (schmt == PGRP_SCHMT_ENABLE)
-               reg |= (0x1 << PGRP_SCHMT_SHIFT);
-       writel(reg, pad_schmt);
-
-       return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_hsm = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad */
-       assert(pmux_padgrp_isvalid(pad));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (hsm == PGRP_HSM_NONE)
-               return 0;
-
-       reg = readl(pad_hsm);
-       reg &= ~(1 << PGRP_HSM_SHIFT);
-       if (hsm == PGRP_HSM_ENABLE)
-               reg |= (0x1 << PGRP_HSM_SHIFT);
-       writel(reg, pad_hsm);
-
-       return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
-       enum pdrive_pingrp pad = config->padgrp;
-
-       padgrp_set_drvup_slwf(pad, config->slwf);
-       padgrp_set_drvdn_slwr(pad, config->slwr);
-       padgrp_set_drvup(pad, config->drvup);
-       padgrp_set_drvdn(pad, config->drvdn);
-       padgrp_set_lpmd(pad, config->lpmd);
-       padgrp_set_schmt(pad, config->schmt);
-       padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++)
-               padctrl_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;
index d19fda0..cced787 100644 (file)
@@ -20,20 +20,20 @@ int funcmux_select(enum periph_id id, int config)
        case PERIPH_ID_UART4:
                switch (config) {
                case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
-                       pinmux_set_func(PINGRP_GPIO_PJ7, PMUX_FUNC_UARTD);
-                       pinmux_set_func(PINGRP_GPIO_PB0, PMUX_FUNC_UARTD);
-                       pinmux_set_func(PINGRP_GPIO_PB1, PMUX_FUNC_UARTD);
-                       pinmux_set_func(PINGRP_GPIO_PK7, PMUX_FUNC_UARTD);
+                       pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
+                       pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
+                       pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
+                       pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
 
-                       pinmux_set_io(PINGRP_GPIO_PJ7, PMUX_PIN_OUTPUT);
-                       pinmux_set_io(PINGRP_GPIO_PB0, PMUX_PIN_INPUT);
-                       pinmux_set_io(PINGRP_GPIO_PB1, PMUX_PIN_INPUT);
-                       pinmux_set_io(PINGRP_GPIO_PK7, PMUX_PIN_OUTPUT);
+                       pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
+                       pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
+                       pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
+                       pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
 
-                       pinmux_tristate_disable(PINGRP_GPIO_PJ7);
-                       pinmux_tristate_disable(PINGRP_GPIO_PB0);
-                       pinmux_tristate_disable(PINGRP_GPIO_PB1);
-                       pinmux_tristate_disable(PINGRP_GPIO_PK7);
+                       pinmux_tristate_disable(PMUX_PINGRP_PJ7);
+                       pinmux_tristate_disable(PMUX_PINGRP_PB0);
+                       pinmux_tristate_disable(PMUX_PINGRP_PB1);
+                       pinmux_tristate_disable(PMUX_PINGRP_PK7);
                        break;
                }
                break;
@@ -41,14 +41,16 @@ int funcmux_select(enum periph_id id, int config)
        case PERIPH_ID_UART1:
                switch (config) {
                case FUNCMUX_UART1_KBC:
-                       pinmux_set_func(PINGRP_KB_ROW9, PMUX_FUNC_UARTA);
-                       pinmux_set_func(PINGRP_KB_ROW10, PMUX_FUNC_UARTA);
+                       pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
+                                       PMUX_FUNC_UARTA);
+                       pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
+                                       PMUX_FUNC_UARTA);
 
-                       pinmux_set_io(PINGRP_KB_ROW9, PMUX_PIN_OUTPUT);
-                       pinmux_set_io(PINGRP_KB_ROW10, PMUX_PIN_INPUT);
+                       pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
+                       pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
 
-                       pinmux_tristate_disable(PINGRP_KB_ROW9);
-                       pinmux_tristate_disable(PINGRP_KB_ROW10);
+                       pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
+                       pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
                        break;
                }
                break;
index a4ab4ea..c6685ea 100644 (file)
 /*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
  *
- * SPDX-License-Identifier:     GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
  */
 
-/* Tegra124 pin multiplexing functions */
-
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/tegra.h>
 #include <asm/arch/pinmux.h>
 
-struct tegra_pingroup_desc {
-       const char *name;
-       enum pmux_func funcs[4];
-       enum pmux_func func_safe;
-       enum pmux_vddio vddio;
-       enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT      0
-#define PMUX_PULL_SHIFT                2
-#define PMUX_TRISTATE_SHIFT    4
-#define PMUX_TRISTATE_MASK     (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT          5
-#define PMUX_OD_SHIFT          6
-#define PMUX_LOCK_SHIFT                7
-#define PMUX_IO_RESET_SHIFT    8
-#define PMUX_RCV_SEL_SHIFT     9
-
-#define PGRP_HSM_SHIFT         2
-#define PGRP_SCHMT_SHIFT       3
-#define PGRP_LPMD_SHIFT                4
-#define PGRP_LPMD_MASK         (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT       12
-#define PGRP_DRVDN_MASK                (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT       20
-#define PGRP_DRVUP_MASK                (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT                28
-#define PGRP_SLWR_MASK         (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT                30
-#define PGRP_SLWF_MASK         (3 << PGRP_SLWF_SHIFT)
-
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
-       {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
-               .funcs = {                              \
-                       PMUX_FUNC_ ## f0,               \
-                       PMUX_FUNC_ ## f1,               \
-                       PMUX_FUNC_ ## f2,               \
-                       PMUX_FUNC_ ## f3,               \
-               },                                      \
-               .func_safe = PMUX_FUNC_RSVD1,           \
-               .io = PMUX_PIN_ ## iod,                 \
+#define PIN(pin, f0, f1, f2, f3)       \
+       {                               \
+               .funcs = {              \
+                       PMUX_FUNC_##f0, \
+                       PMUX_FUNC_##f1, \
+                       PMUX_FUNC_##f2, \
+                       PMUX_FUNC_##f3, \
+               },                      \
        }
 
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
-       PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
-       PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-/* A pin group number which is not used */
-#define PIN_RESERVED \
-       PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+#define PIN_RESERVED {}
 
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
-       /*      NAME      VDD      f0           f1         f2       f3  */
-       PINI(ULPI_DATA0,  BB,      SPI3,       HSI,        UARTA,   ULPI),
-       PINI(ULPI_DATA1,  BB,      SPI3,       HSI,        UARTA,   ULPI),
-       PINI(ULPI_DATA2,  BB,      SPI3,       HSI,        UARTA,   ULPI),
-       PINI(ULPI_DATA3,  BB,      SPI3,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA4,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA5,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA6,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA7,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_CLK,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(ULPI_DIR,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(ULPI_NXT,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(ULPI_STP,    BB,      SPI1,       SPI5,       UARTD,   ULPI),
-       PINI(DAP3_FS,     BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(DAP3_DIN,    BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(DAP3_DOUT,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(DAP3_SCLK,   BB,      I2S2,       SPI5,       DISPA,   DISPB),
-       PINI(GPIO_PV0,    BB,      USB,        RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_PV1,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,     CLK12,      RSVD3,   RSVD4),
-       PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
-       PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,     SPDIF,      SPI4,    UARTA),
-       PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,     PWM0,       SPI4,    UARTA),
-       PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,     PWM1,       SPI4,    UARTA),
-       PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,     RSVD2,      SPI4,    UARTA),
-       PIN_RESERVED,   /* Reserved: 0x3060 - 0x3064 */
+static const struct pmux_pingrp_desc tegra124_pingroups[] = {
+       /*  pin,                    f0,         f1,       f2,           f3 */
+       /* Offset 0x3000 */
+       PIN(ULPI_DATA0_PO1,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA1_PO2,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA2_PO3,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA3_PO4,         SPI3,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA4_PO5,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA5_PO6,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA6_PO7,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_DATA7_PO0,         SPI2,       HSI,      UARTA,        ULPI),
+       PIN(ULPI_CLK_PY0,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(ULPI_DIR_PY1,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(ULPI_NXT_PY2,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(ULPI_STP_PY3,           SPI1,       SPI5,     UARTD,        ULPI),
+       PIN(DAP3_FS_PP0,            I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+       PIN(DAP3_DIN_PP1,           I2S2,       SPI5,     DISPLAYA,     DISPLAYB),
+       PIN(DAP3_DOUT_PP2,          I2S2,       SPI5,     DISPLAYA,     RSVD4),
+       PIN(DAP3_SCLK_PP3,          I2S2,       SPI5,     RSVD3,        DISPLAYB),
+       PIN(PV0,                    RSVD1,      RSVD2,    RSVD3,        RSVD4),
+       PIN(PV1,                    RSVD1,      RSVD2,    RSVD3,        RSVD4),
+       PIN(SDMMC1_CLK_PZ0,         SDMMC1,     CLK12,    RSVD3,        RSVD4),
+       PIN(SDMMC1_CMD_PZ1,         SDMMC1,     SPDIF,    SPI4,         UARTA),
+       PIN(SDMMC1_DAT3_PY4,        SDMMC1,     SPDIF,    SPI4,         UARTA),
+       PIN(SDMMC1_DAT2_PY5,        SDMMC1,     PWM0,     SPI4,         UARTA),
+       PIN(SDMMC1_DAT1_PY6,        SDMMC1,     PWM1,     SPI4,         UARTA),
+       PIN(SDMMC1_DAT0_PY7,        SDMMC1,     RSVD2,    SPI4,         UARTA),
        PIN_RESERVED,
-       PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2, RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK2_REQ,    SDMMC1,  DAP,        RSVD2,      RSVD3,   RSVD4),
-       PIN_RESERVED,   /* Reserved: 0x3070 - 0x310c */
        PIN_RESERVED,
+       /* Offset 0x3068 */
+       PIN(CLK2_OUT_PW5,           EXTPERIPH2, RSVD2,    RSVD3,        RSVD4),
+       PIN(CLK2_REQ_PCC5,          DAP,        RSVD2,    RSVD3,        RSVD4),
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
@@ -137,12 +90,12 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
-       PINI(HDMI_INT,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(DDC_SCL,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(DDC_SDA,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
-       PIN_RESERVED,   /* Reserved: 0x311c - 0x3160 */
        PIN_RESERVED,
        PIN_RESERVED,
+       /* Offset 0x3110 */
+       PIN(HDMI_INT_PN7,           RSVD1,      RSVD2,    RSVD3,        RSVD4),
+       PIN(DDC_SCL_PV4,            I2C4,       RSVD2,    RSVD3,        RSVD4),
+       PIN(DDC_SDA_PV5,            I2C4,       RSVD2,    RSVD3,        RSVD4),
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
@@ -158,573 +111,196 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PIN_RESERVED,
        PIN_RESERVED,
        PIN_RESERVED,
-       PINI(UART2_RXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
-       PINI(UART2_TXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
-       PINI(UART2_RTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
-       PINI(UART2_CTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
-       PINI(UART3_TXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
-       PINI(UART3_RXD,   UART,    UARTC,      RSVD2,      RSVD3,   SPI4),
-       PINI(UART3_CTS_N, UART,    UARTC,      SDMMC1,     DTV,     SPI4),
-       PINI(UART3_RTS_N, UART,    UARTC,      PWM0,       DTV,     DISPA),
-       PINI(GPIO_PU0,    UART,    OWR,        UARTA,      RSVD3,   RSVD4),
-       PINI(GPIO_PU1,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
-       PINI(GPIO_PU2,    UART,    RSVD1,      UARTA,      RSVD3,   RSVD4),
-       PINI(GPIO_PU3,    UART,    PWM0,       UARTA,      DISPA,   DISPB),
-       PINI(GPIO_PU4,    UART,    PWM1,       UARTA,      DISPA,   DISPB),
-       PINI(GPIO_PU5,    UART,    PWM2,       UARTA,      DISPA,   DISPB),
-       PINI(GPIO_PU6,    UART,    PWM3,       UARTA,      USB,     DISPB),
-       PINI(GEN1_I2C_SDA, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GEN1_I2C_SCL, UART,   I2C1,       RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP4_FS,     UART,    I2S3,       RSVD2,      DTV,     RSVD4),
-       PINI(DAP4_DIN,    UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP4_DOUT,   UART,    I2S3,       RSVD2,      DTV,     RSVD4),
-       PINI(DAP4_SCLK,   UART,    I2S3,       RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK3_OUT,    UART,    EXTPERIPH3, RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK3_REQ,    UART,    DEV3,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GMI_WP_N,    GMI,     RSVD1,      NAND,       GMI,     GMI_ALT),
-       PINI(GMI_IORDY,   GMI,     SDMMC2,     RSVD2,      GMI,     TRACE),
-       PINI(GMI_WAIT,    GMI,     SPI4,       NAND,       GMI,     DTV),
-       PINI(GMI_ADV_N,   GMI,     RSVD1,      NAND,       GMI,     TRACE),
-       PINI(GMI_CLK,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
-       PINI(GMI_CS0_N,   GMI,     RSVD1,      NAND,       GMI,     USB),
-       PINI(GMI_CS1_N,   GMI,     RSVD1,      NAND,       GMI,     SOC),
-       PINI(GMI_CS2_N,   GMI,     SDMMC2,     NAND,       GMI,     TRACE),
-       PINI(GMI_CS3_N,   GMI,     SDMMC2,     NAND,       GMI,     GMI_ALT),
-       PINI(GMI_CS4_N,   GMI,     USB,        NAND,       GMI,     TRACE),
-       PINI(GMI_CS6_N,   GMI,     NAND,       NAND_ALT,   GMI,     SPI4),
-       PINI(GMI_CS7_N,   GMI,     NAND,       NAND_ALT,   GMI,     SDMMC2),
-       PINI(GMI_AD0,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD1,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD2,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD3,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD4,     GMI,     RSVD1,      NAND,       GMI,     RSVD4),
-       PINI(GMI_AD5,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_AD6,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_AD7,     GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_AD8,     GMI,     PWM0,       NAND,       GMI,     DTV),
-       PINI(GMI_AD9,     GMI,     PWM1,       NAND,       GMI,     CLDVFS),
-       PINI(GMI_AD10,    GMI,     PWM2,       NAND,       GMI,     CLDVFS),
-       PINI(GMI_AD11,    GMI,     PWM3,       NAND,       GMI,     USB),
-       PINI(GMI_AD12,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
-       PINI(GMI_AD13,    GMI,     SDMMC2,     NAND,       GMI,     RSVD4),
-       PINI(GMI_AD14,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
-       PINI(GMI_AD15,    GMI,     SDMMC2,     NAND,       GMI,     DTV),
-       PINI(GMI_A16,     GMI,     UARTD,      TRACE,      GMI,     GMI_ALT),
-       PINI(GMI_A17,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
-       PINI(GMI_A18,     GMI,     UARTD,      RSVD2,      GMI,     TRACE),
-       PINI(GMI_A19,     GMI,     UARTD,      SPI4,       GMI,     TRACE),
-       PINI(GMI_WR_N,    GMI,     RSVD1,      NAND,       GMI,     SPI4),
-       PINI(GMI_OE_N,    GMI,     RSVD1,      NAND,       GMI,     SOC),
-       PINI(GMI_DQS,     GMI,     SDMMC2,     NAND,       GMI,     TRACE),
-       PINI(GMI_RST_N,   GMI,     NAND,       NAND_ALT,   GMI,     RSVD4),
-       PINI(GEN2_I2C_SCL, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
-       PINI(GEN2_I2C_SDA, GMI,    I2C2,       RSVD2,      GMI,     RSVD4),
-       PINI(SDMMC4_CLK,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
-       PINI(SDMMC4_CMD,  SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
-       PINI(SDMMC4_DAT0, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT1, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT2, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT3, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT4, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT5, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT6, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
-       PINI(SDMMC4_DAT7, SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
-       PIN_RESERVED,   /* Reserved: 0x3280 */
-       PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT3, RSVD4),
-       PINI(GPIO_PCC1,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_PBB0,   CAM,     I2S4,       VI,         VI_ALT1, VI_ALT3),
-       PINI(CAM_I2C_SCL, CAM,     VGP1,       I2C3,       RSVD3,   RSVD4),
-       PINI(CAM_I2C_SDA, CAM,     VGP2,       I2C3,       RSVD3,   RSVD4),
-       PINI(GPIO_PBB3,   CAM,     VGP3,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB4,   CAM,     VGP4,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB5,   CAM,     VGP5,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB6,   CAM,     VGP6,       DISPA,      DISPB,   RSVD4),
-       PINI(GPIO_PBB7,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_PCC2,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(JTAG_RTCK,   SYS,     RTCK,       RSVD2,      RSVD3,   RSVD4),
-       PINI(PWR_I2C_SCL, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
-       PINI(PWR_I2C_SDA, SYS,     I2CPWR,     RSVD2,      RSVD3,   RSVD4),
-       PINI(KB_ROW0,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
-       PINI(KB_ROW1,     SYS,     KBC,        RSVD2,      DTV,     RSVD4),
-       PINI(KB_ROW2,     SYS,     KBC,        RSVD2,      DTV,     SOC),
-       PINI(KB_ROW3,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
-       PINI(KB_ROW4,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
-       PINI(KB_ROW5,     SYS,     KBC,        DISPA,      SPI2,    DISPB),
-       PINI(KB_ROW6,     SYS,     KBC,        DISPA,      RSVD3,   DISPB),
-       PINI(KB_ROW7,     SYS,     KBC,        RSVD2,      CLDVFS,  UARTA),
-       PINI(KB_ROW8,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
-       PINI(KB_ROW9,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
-       PINI(KB_ROW10,    SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
-       PIN_RESERVED,   /* Reserved: 0x32e8 - 0x32f8 */
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PINI(KB_COL0,     SYS,     KBC,        USB,        SPI2,    EMC_DLL),
-       PINI(KB_COL1,     SYS,     KBC,        RSVD2,      SPI2,    EMC_DLL),
-       PINI(KB_COL2,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
-       PINI(KB_COL3,     SYS,     KBC,        DISPA,      PWM2,    UARTA),
-       PINI(KB_COL4,     SYS,     KBC,        OWR,        SDMMC3,  UARTA),
-       PINI(KB_COL5,     SYS,     KBC,        RSVD2,      SDMMC1,  RSVD4),
-       PINI(KB_COL6,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
-       PINI(KB_COL7,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
-       PINI(CLK_32K_OUT, SYS,     BLINK,      SOC,        RSVD3,   RSVD4),
-       PINI(SYS_CLK_REQ, SYS,     SYSCLK,     RSVD2,      RSVD3,   RSVD4),
-       PINI(CORE_PWR_REQ, SYS,    PWRON,      RSVD2,      RSVD3,   RSVD4),
-       PINI(CPU_PWR_REQ, SYS,     CPU,        RSVD2,      RSVD3,   RSVD4),
-       PINI(PWR_INT_N,   SYS,     PMI,        RSVD2,      RSVD3,   RSVD4),
-       PINI(CLK_32K_IN,  SYS,     CLK,        RSVD2,      RSVD3,   RSVD4),
-       PINI(OWR,         SYS,     OWR,        RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP1_FS,     AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(DAP1_DIN,    AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(DAP1_DOUT,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(DAP1_SCLK,   AUDIO,   I2S0,       HDA,        GMI,     RSVD4),
-       PINI(CLK1_REQ,    AUDIO,   DAP,        DAP1,       RSVD3,   RSVD4),
-       PINI(CLK1_OUT,    AUDIO,   EXTPERIPH1, DAP2,       RSVD3,   RSVD4),
-       PINI(SPDIF_IN,    AUDIO,   SPDIF,      USB,        RSVD3,   RSVD4),
-       PINI(SPDIF_OUT,   AUDIO,   SPDIF,      RSVD2,      RSVD3,   RSVD4),
-       PINI(DAP2_FS,     AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DAP2_DIN,    AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DAP2_DOUT,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DAP2_SCLK,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(DVFS_PWM,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
-       PINI(GPIO_X1_AUD, AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_X3_AUD, AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
-       PINI(DVFS_CLK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
-       PINI(GPIO_X4_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
-       PINI(GPIO_X5_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
-       PINI(GPIO_X6_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
-       PINI(GPIO_X7_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
-       PIN_RESERVED,   /* Reserved: 0x3388 - 0x338c */
-       PIN_RESERVED,
-       PINI(SDMMC3_CLK,  SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
-       PINI(SDMMC3_CMD,  SDMMC3,  SDMMC3,     PWM3,       UARTA,   SPI3),
-       PINI(SDMMC3_DAT0, SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
-       PINI(SDMMC3_DAT1, SDMMC3,  SDMMC3,     PWM2,       UARTA,   SPI3),
-       PINI(SDMMC3_DAT2, SDMMC3,  SDMMC3,     PWM1,       DISPA,   SPI3),
-       PINI(SDMMC3_DAT3, SDMMC3,  SDMMC3,     PWM0,       DISPB,   SPI3),
-       PIN_RESERVED,   /* Reserved: 0x33a8 - 0x33dc */
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PIN_RESERVED,
-       PINI(HDMI_CEC,    SYS,     CEC,        SDMMC3,     RSVD3,   SOC),
-       PINI(SDMMC1_WP_N, SDMMC1,  SDMMC1,     CLK12,      SPI4,    UARTA),
-       PINI(SDMMC3_CD_N, SYS,  SDMMC3,     OWR,        RSVD3,   RSVD4),
-       PINI(GPIO_W2_AUD, AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
-       PINI(GPIO_W3_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
-       PINI(USB_VBUS_EN0, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
-       PINI(USB_VBUS_EN1, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
-       PINI(SDMMC3_CLK_LB_IN,  SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
-       PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
-       PIN_RESERVED,   /* Reserved: 0x3404 */
-       PINO(RESET_OUT_N, SYS,     RSVD1,      RSVD2,      RSVD3, RESET_OUT_N),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x3164 */
+       PIN(UART2_RXD_PC3,          IRDA,       SPDIF,    UARTA,        SPI4),
+       PIN(UART2_TXD_PC2,          IRDA,       SPDIF,    UARTA,        SPI4),
+       PIN(UART2_RTS_N_PJ6,        UARTA,      UARTB,    GMI,          SPI4),
+       PIN(UART2_CTS_N_PJ5,        UARTA,      UARTB,    GMI,          SPI4),
+       PIN(UART3_TXD_PW6,          UARTC,      RSVD2,    GMI,          SPI4),
+       PIN(UART3_RXD_PW7,          UARTC,      RSVD2,    GMI,          SPI4),
+       PIN(UART3_CTS_N_PA1,        UARTC,      SDMMC1,   DTV,          GMI),
+       PIN(UART3_RTS_N_PC0,        UARTC,      PWM0,     DTV,          GMI),
+       PIN(PU0,                    OWR,        UARTA,    GMI,          RSVD4),
+       PIN(PU1,                    RSVD1,      UARTA,    GMI,          RSVD4),
+       PIN(PU2,                    RSVD1,      UARTA,    GMI,          RSVD4),
+       PIN(PU3,                    PWM0,       UARTA,    GMI,          DISPLAYB),
+       PIN(PU4,                    PWM1,       UARTA,    GMI,          DISPLAYB),
+       PIN(PU5,                    PWM2,       UARTA,    GMI,          DISPLAYB),
+       PIN(PU6,                    PWM3,       UARTA,    RSVD3,        GMI),
+       PIN(GEN1_I2C_SDA_PC5,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+       PIN(GEN1_I2C_SCL_PC4,       I2C1,       RSVD2,    RSVD3,        RSVD4),
+       PIN(DAP4_FS_PP4,            I2S3,       GMI,      DTV,          RSVD4),
+       PIN(DAP4_DIN_PP5,           I2S3,       GMI,      RSVD3,        RSVD4),
+       PIN(DAP4_DOUT_PP6,          I2S3,       GMI,      DTV,          RSVD4),
+       PIN(DAP4_SCLK_PP7,          I2S3,       GMI,      RSVD3,        RSVD4),
+       PIN(CLK3_OUT_PEE0,          EXTPERIPH3, RSVD2,    RSVD3,        RSVD4),
+       PIN(CLK3_REQ_PEE1,          DEV3,       RSVD2,    RSVD3,        RSVD4),
+       PIN(PC7,                    RSVD1,      RSVD2,    GMI,          GMI_ALT),
+       PIN(PI5,                    SDMMC2,     RSVD2,    GMI,          RSVD4),
+       PIN(PI7,                    RSVD1,      TRACE,    GMI,          DTV),
+       PIN(PK0,                    RSVD1,      SDMMC3,   GMI,          SOC),
+       PIN(PK1,                    SDMMC2,     TRACE,    GMI,          RSVD4),
+       PIN(PJ0,                    RSVD1,      RSVD2,    GMI,          USB),
+       PIN(PJ2,                    RSVD1,      RSVD2,    GMI,          SOC),
+       PIN(PK3,                    SDMMC2,     TRACE,    GMI,          CCLA),
+       PIN(PK4,                    SDMMC2,     RSVD2,    GMI,          GMI_ALT),
+       PIN(PK2,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+       PIN(PI3,                    RSVD1,      RSVD2,    GMI,          SPI4),
+       PIN(PI6,                    RSVD1,      RSVD2,    GMI,          SDMMC2),
+       PIN(PG0,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+       PIN(PG1,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+       PIN(PG2,                    RSVD1,      TRACE,    GMI,          RSVD4),
+       PIN(PG3,                    RSVD1,      TRACE,    GMI,          RSVD4),
+       PIN(PG4,                    RSVD1,      TMDS,     GMI,          SPI4),
+       PIN(PG5,                    RSVD1,      RSVD2,    GMI,          SPI4),
+       PIN(PG6,                    RSVD1,      RSVD2,    GMI,          SPI4),
+       PIN(PG7,                    RSVD1,      RSVD2,    GMI,          SPI4),
+       PIN(PH0,                    PWM0,       TRACE,    GMI,          DTV),
+       PIN(PH1,                    PWM1,       TMDS,     GMI,          DISPLAYA),
+       PIN(PH2,                    PWM2,       TMDS,     GMI,          CLDVFS),
+       PIN(PH3,                    PWM3,       SPI4,     GMI,          CLDVFS),
+       PIN(PH4,                    SDMMC2,     RSVD2,    GMI,          RSVD4),
+       PIN(PH5,                    SDMMC2,     RSVD2,    GMI,          RSVD4),
+       PIN(PH6,                    SDMMC2,     TRACE,    GMI,          DTV),
+       PIN(PH7,                    SDMMC2,     TRACE,    GMI,          DTV),
+       PIN(PJ7,                    UARTD,      RSVD2,    GMI,          GMI_ALT),
+       PIN(PB0,                    UARTD,      RSVD2,    GMI,          RSVD4),
+       PIN(PB1,                    UARTD,      RSVD2,    GMI,          RSVD4),
+       PIN(PK7,                    UARTD,      RSVD2,    GMI,          RSVD4),
+       PIN(PI0,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+       PIN(PI1,                    RSVD1,      RSVD2,    GMI,          RSVD4),
+       PIN(PI2,                    SDMMC2,     TRACE,    GMI,          RSVD4),
+       PIN(PI4,                    SPI4,       TRACE,    GMI,          DISPLAYA),
+       PIN(GEN2_I2C_SCL_PT5,       I2C2,       RSVD2,    GMI,          RSVD4),
+       PIN(GEN2_I2C_SDA_PT6,       I2C2,       RSVD2,    GMI,          RSVD4),
+       PIN(SDMMC4_CLK_PCC4,        SDMMC4,     RSVD2,    GMI,          RSVD4),
+       PIN(SDMMC4_CMD_PT7,         SDMMC4,     RSVD2,    GMI,          RSVD4),
+       PIN(SDMMC4_DAT0_PAA0,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT1_PAA1,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT2_PAA2,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT3_PAA3,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT4_PAA4,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT5_PAA5,       SDMMC4,     SPI3,     RSVD3,        RSVD4),
+       PIN(SDMMC4_DAT6_PAA6,       SDMMC4,     SPI3,     GMI,          RSVD4),
+       PIN(SDMMC4_DAT7_PAA7,       SDMMC4,     RSVD2,    GMI,          RSVD4),
+       PIN_RESERVED,
+       /* Offset 0x3284 */
+       PIN(CAM_MCLK_PCC0,          VI,         VI_ALT1,  VI_ALT3,      SDMMC2),
+       PIN(PCC1,                   I2S4,       RSVD2,    RSVD3,        SDMMC2),
+       PIN(PBB0,                   VGP6,       VIMCLK2,  SDMMC2,       VIMCLK2_ALT),
+       PIN(CAM_I2C_SCL_PBB1,       VGP1,       I2C3,     RSVD3,        SDMMC2),
+       PIN(CAM_I2C_SDA_PBB2,       VGP2,       I2C3,     RSVD3,        SDMMC2),
+       PIN(PBB3,                   VGP3,       DISPLAYA, DISPLAYB,     SDMMC2),
+       PIN(PBB4,                   VGP4,       DISPLAYA, DISPLAYB,     SDMMC2),
+       PIN(PBB5,                   VGP5,       DISPLAYA, RSVD3,        SDMMC2),
+       PIN(PBB6,                   I2S4,       RSVD2,    DISPLAYB,     SDMMC2),
+       PIN(PBB7,                   I2S4,       RSVD2,    RSVD3,        SDMMC2),
+       PIN(PCC2,                   I2S4,       RSVD2,    SDMMC3,       SDMMC2),
+       PIN(JTAG_RTCK,              RTCK,       RSVD2,    RSVD3,        RSVD4),
+       PIN(PWR_I2C_SCL_PZ6,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+       PIN(PWR_I2C_SDA_PZ7,        I2CPWR,     RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW0_PR0,            KBC,        RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW1_PR1,            KBC,        RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW2_PR2,            KBC,        RSVD2,    RSVD3,        RSVD4),
+       PIN(KB_ROW3_PR3,            KBC,        DISPLAYA, SYS,          DISPLAYB),
+       PIN(KB_ROW4_PR4,            KBC,        DISPLAYA, RSVD3,        DISPLAYB),
+       PIN(KB_ROW5_PR5,            KBC,        DISPLAYA, RSVD3,        DISPLAYB),
+       PIN(KB_ROW6_PR6,            KBC,        DISPLAYA, DISPLAYA_ALT, DISPLAYB),
+       PIN(KB_ROW7_PR7,            KBC,        RSVD2,    CLDVFS,       UARTA),
+       PIN(KB_ROW8_PS0,            KBC,        RSVD2,    CLDVFS,       UARTA),
+       PIN(KB_ROW9_PS1,            KBC,        RSVD2,    RSVD3,        UARTA),
+       PIN(KB_ROW10_PS2,           KBC,        RSVD2,    RSVD3,        UARTA),
+       PIN(KB_ROW11_PS3,           KBC,        RSVD2,    RSVD3,        IRDA),
+       PIN(KB_ROW12_PS4,           KBC,        RSVD2,    RSVD3,        IRDA),
+       PIN(KB_ROW13_PS5,           KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(KB_ROW14_PS6,           KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(KB_ROW15_PS7,           KBC,        SOC,      RSVD3,        RSVD4),
+       PIN(KB_COL0_PQ0,            KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(KB_COL1_PQ1,            KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(KB_COL2_PQ2,            KBC,        RSVD2,    SPI2,         RSVD4),
+       PIN(KB_COL3_PQ3,            KBC,        DISPLAYA, PWM2,         UARTA),
+       PIN(KB_COL4_PQ4,            KBC,        OWR,      SDMMC3,       UARTA),
+       PIN(KB_COL5_PQ5,            KBC,        RSVD2,    SDMMC3,       RSVD4),
+       PIN(KB_COL6_PQ6,            KBC,        RSVD2,    SPI2,         UARTD),
+       PIN(KB_COL7_PQ7,            KBC,        RSVD2,    SPI2,         UARTD),
+       PIN(CLK_32K_OUT_PA0,        BLINK,      SOC,      RSVD3,        RSVD4),
+       PIN_RESERVED,
+       /* Offset 0x3324 */
+       PIN(CORE_PWR_REQ,           PWRON,      RSVD2,    RSVD3,        RSVD4),
+       PIN(CPU_PWR_REQ,            CPU,        RSVD2,    RSVD3,        RSVD4),
+       PIN(PWR_INT_N,              PMI,        RSVD2,    RSVD3,        RSVD4),
+       PIN(CLK_32K_IN,             CLK,        RSVD2,    RSVD3,        RSVD4),
+       PIN(OWR,                    OWR,        RSVD2,    RSVD3,        RSVD4),
+       PIN(DAP1_FS_PN0,            I2S0,       HDA,      GMI,          RSVD4),
+       PIN(DAP1_DIN_PN1,           I2S0,       HDA,      GMI,          RSVD4),
+       PIN(DAP1_DOUT_PN2,          I2S0,       HDA,      GMI,          SATA),
+       PIN(DAP1_SCLK_PN3,          I2S0,       HDA,      GMI,          RSVD4),
+       PIN(DAP_MCLK1_REQ_PEE2,     DAP,        DAP1,     SATA,         RSVD4),
+       PIN(DAP_MCLK1_PW4,          EXTPERIPH1, DAP2,     RSVD3,        RSVD4),
+       PIN(SPDIF_IN_PK6,           SPDIF,      RSVD2,    RSVD3,        I2C3),
+       PIN(SPDIF_OUT_PK5,          SPDIF,      RSVD2,    RSVD3,        I2C3),
+       PIN(DAP2_FS_PA2,            I2S1,       HDA,      GMI,          RSVD4),
+       PIN(DAP2_DIN_PA4,           I2S1,       HDA,      GMI,          RSVD4),
+       PIN(DAP2_DOUT_PA5,          I2S1,       HDA,      GMI,          RSVD4),
+       PIN(DAP2_SCLK_PA3,          I2S1,       HDA,      GMI,          RSVD4),
+       PIN(DVFS_PWM_PX0,           SPI6,       CLDVFS,   GMI,          RSVD4),
+       PIN(GPIO_X1_AUD_PX1,        SPI6,       RSVD2,    GMI,          RSVD4),
+       PIN(GPIO_X3_AUD_PX3,        SPI6,       SPI1,     GMI,          RSVD4),
+       PIN(DVFS_CLK_PX2,           SPI6,       CLDVFS,   GMI,          RSVD4),
+       PIN(GPIO_X4_AUD_PX4,        GMI,        SPI1,     SPI2,         DAP2),
+       PIN(GPIO_X5_AUD_PX5,        GMI,        SPI1,     SPI2,         RSVD4),
+       PIN(GPIO_X6_AUD_PX6,        SPI6,       SPI1,     SPI2,         GMI),
+       PIN(GPIO_X7_AUD_PX7,        RSVD1,      SPI1,     SPI2,         RSVD4),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x3390 */
+       PIN(SDMMC3_CLK_PA6,         SDMMC3,     RSVD2,    RSVD3,        SPI3),
+       PIN(SDMMC3_CMD_PA7,         SDMMC3,     PWM3,     UARTA,        SPI3),
+       PIN(SDMMC3_DAT0_PB7,        SDMMC3,     RSVD2,    RSVD3,        SPI3),
+       PIN(SDMMC3_DAT1_PB6,        SDMMC3,     PWM2,     UARTA,        SPI3),
+       PIN(SDMMC3_DAT2_PB5,        SDMMC3,     PWM1,     DISPLAYA,     SPI3),
+       PIN(SDMMC3_DAT3_PB4,        SDMMC3,     PWM0,     DISPLAYB,     SPI3),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x33bc */
+       PIN(PEX_L0_RST_N_PDD1,      PE0,        RSVD2,    RSVD3,        RSVD4),
+       PIN(PEX_L0_CLKREQ_N_PDD2,   PE0,        RSVD2,    RSVD3,        RSVD4),
+       PIN(PEX_WAKE_N_PDD3,        PE,         RSVD2,    RSVD3,        RSVD4),
+       PIN_RESERVED,
+       /* Offset 0x33cc */
+       PIN(PEX_L1_RST_N_PDD5,      PE1,        RSVD2,    RSVD3,        RSVD4),
+       PIN(PEX_L1_CLKREQ_N_PDD6,   PE1,        RSVD2,    RSVD3,        RSVD4),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x33e0 */
+       PIN(HDMI_CEC_PEE3,          CEC,        RSVD2,    RSVD3,        RSVD4),
+       PIN(SDMMC1_WP_N_PV3,        SDMMC1,     CLK12,    SPI4,         UARTA),
+       PIN(SDMMC3_CD_N_PV2,        SDMMC3,     OWR,      RSVD3,        RSVD4),
+       PIN(GPIO_W2_AUD_PW2,        SPI6,       RSVD2,    SPI2,         I2C1),
+       PIN(GPIO_W3_AUD_PW3,        SPI6,       SPI1,     SPI2,         I2C1),
+       PIN(USB_VBUS_EN0_PN4,       USB,        RSVD2,    RSVD3,        RSVD4),
+       PIN(USB_VBUS_EN1_PN5,       USB,        RSVD2,    RSVD3,        RSVD4),
+       PIN(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+       PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,     RSVD2,    RSVD3,        RSVD4),
+       PIN(GMI_CLK_LB,             SDMMC2,     RSVD2,    GMI,          RSVD4),
+       PIN(RESET_OUT_N,            RSVD1,      RSVD2,    RSVD3,        RESET_OUT_N),
+       PIN(KB_ROW16_PT0,           KBC,        RSVD2,    RSVD3,        UARTC),
+       PIN(KB_ROW17_PT1,           KBC,        RSVD2,    RSVD3,        UARTC),
+       PIN(USB_VBUS_EN2_PFF1,      USB,        RSVD2,    RSVD3,        RSVD4),
+       PIN(PFF2,                   SATA,       RSVD2,    RSVD3,        RSVD4),
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       /* Offset 0x3430 */
+       PIN(DP_HPD_PFF0,            DP,         RSVD2,    RSVD3,        RSVD4),
 };
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *tri = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin */
-       assert(pmux_pingrp_isvalid(pin));
-
-       reg = readl(tri);
-       if (enable)
-               reg |= PMUX_TRISTATE_MASK;
-       else
-               reg &= ~PMUX_TRISTATE_MASK;
-       writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pull = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and pupd */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_pupd_isvalid(pupd));
-
-       reg = readl(pull);
-       reg &= ~(0x3 << PMUX_PULL_SHIFT);
-       reg |= (pupd << PMUX_PULL_SHIFT);
-       writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *muxctl = &pmt->pmt_ctl[pin];
-       int i, mux = -1;
-       u32 reg;
-
-       /* Error check on pin and func */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_func_isvalid(func));
-
-       /* Handle special values */
-       if (func == PMUX_FUNC_SAFE)
-               func = tegra_soc_pingroups[pin].func_safe;
-
-       if (func & PMUX_FUNC_RSVD1) {
-               mux = func & 0x3;
-       } else {
-               /* Search for the appropriate function */
-               for (i = 0; i < 4; i++) {
-                       if (tegra_soc_pingroups[pin].funcs[i] == func) {
-                               mux = i;
-                               break;
-                       }
-               }
-       }
-       assert(mux != -1);
-
-       reg = readl(muxctl);
-       reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
-       reg |= (mux << PMUX_MUXCTL_SHIFT);
-       writel(reg, muxctl);
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_io = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and io */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_io_isvalid(io));
-
-       reg = readl(pin_io);
-       reg &= ~(0x1 << PMUX_IO_SHIFT);
-       reg |= (io & 0x1) << PMUX_IO_SHIFT;
-       writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_lock = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and lock */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_lock_isvalid(lock));
-
-       if (lock == PMUX_PIN_LOCK_DEFAULT)
-               return 0;
-
-       reg = readl(pin_lock);
-       reg &= ~(0x1 << PMUX_LOCK_SHIFT);
-       if (lock == PMUX_PIN_LOCK_ENABLE) {
-               reg |= (0x1 << PMUX_LOCK_SHIFT);
-       } else {
-               /* lock == DISABLE, which isn't possible */
-               printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
-                      __func__, lock);
-       }
-       writel(reg, pin_lock);
-
-       return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_od = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and od */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_od_isvalid(od));
-
-       if (od == PMUX_PIN_OD_DEFAULT)
-               return 0;
-
-       reg = readl(pin_od);
-       reg &= ~(0x1 << PMUX_OD_SHIFT);
-       if (od == PMUX_PIN_OD_ENABLE)
-               reg |= (0x1 << PMUX_OD_SHIFT);
-       writel(reg, pin_od);
-
-       return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
-                               enum pmux_pin_ioreset ioreset)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_ioreset = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and ioreset */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_ioreset_isvalid(ioreset));
-
-       if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
-               return 0;
-
-       reg = readl(pin_ioreset);
-       reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
-       if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
-               reg |= (0x1 << PMUX_IO_RESET_SHIFT);
-       writel(reg, pin_ioreset);
-
-       return 0;
-}
-
-static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
-                               enum pmux_pin_rcv_sel rcv_sel)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and rcv_sel */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
-
-       if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
-               return 0;
-
-       reg = readl(pin_rcv_sel);
-       reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
-       if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
-               reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
-       writel(reg, pin_rcv_sel);
-
-       return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
-       enum pmux_pingrp pin = config->pingroup;
-
-       pinmux_set_func(pin, config->func);
-       pinmux_set_pullupdown(pin, config->pull);
-       pinmux_set_tristate(pin, config->tristate);
-       pinmux_set_io(pin, config->io);
-       pinmux_set_lock(pin, config->lock);
-       pinmux_set_od(pin, config->od);
-       pinmux_set_ioreset(pin, config->ioreset);
-       pinmux_set_rcv_sel(pin, config->rcv_sel);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++)
-               pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_slwf = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and slwf */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_slw_isvalid(slwf));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (slwf == PGRP_SLWF_NONE)
-               return 0;
-
-       reg = readl(pad_slwf);
-       reg &= ~PGRP_SLWF_MASK;
-       reg |= (slwf << PGRP_SLWF_SHIFT);
-       writel(reg, pad_slwf);
-
-       return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_slwr = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and slwr */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_slw_isvalid(slwr));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (slwr == PGRP_SLWR_NONE)
-               return 0;
-
-       reg = readl(pad_slwr);
-       reg &= ~PGRP_SLWR_MASK;
-       reg |= (slwr << PGRP_SLWR_SHIFT);
-       writel(reg, pad_slwr);
-
-       return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_drvup = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and drvup */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_drv_isvalid(drvup));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (drvup == PGRP_DRVUP_NONE)
-               return 0;
-
-       reg = readl(pad_drvup);
-       reg &= ~PGRP_DRVUP_MASK;
-       reg |= (drvup << PGRP_DRVUP_SHIFT);
-       writel(reg, pad_drvup);
-
-       return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_drvdn = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and drvdn */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_drv_isvalid(drvdn));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (drvdn == PGRP_DRVDN_NONE)
-               return 0;
-
-       reg = readl(pad_drvdn);
-       reg &= ~PGRP_DRVDN_MASK;
-       reg |= (drvdn << PGRP_DRVDN_SHIFT);
-       writel(reg, pad_drvdn);
-
-       return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_lpmd = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad and lpmd value */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_lpmd_isvalid(lpmd));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (lpmd == PGRP_LPMD_NONE)
-               return 0;
-
-       reg = readl(pad_lpmd);
-       reg &= ~PGRP_LPMD_MASK;
-       reg |= (lpmd << PGRP_LPMD_SHIFT);
-       writel(reg, pad_lpmd);
-
-       return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_schmt = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad */
-       assert(pmux_padgrp_isvalid(pad));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (schmt == PGRP_SCHMT_NONE)
-               return 0;
-
-       reg = readl(pad_schmt);
-       reg &= ~(1 << PGRP_SCHMT_SHIFT);
-       if (schmt == PGRP_SCHMT_ENABLE)
-               reg |= (0x1 << PGRP_SCHMT_SHIFT);
-       writel(reg, pad_schmt);
-
-       return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_hsm = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad */
-       assert(pmux_padgrp_isvalid(pad));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (hsm == PGRP_HSM_NONE)
-               return 0;
-
-       reg = readl(pad_hsm);
-       reg &= ~(1 << PGRP_HSM_SHIFT);
-       if (hsm == PGRP_HSM_ENABLE)
-               reg |= (0x1 << PGRP_HSM_SHIFT);
-       writel(reg, pad_hsm);
-
-       return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
-       enum pdrive_pingrp pad = config->padgrp;
-
-       padgrp_set_drvup_slwf(pad, config->slwf);
-       padgrp_set_drvdn_slwr(pad, config->slwr);
-       padgrp_set_drvup(pad, config->drvup);
-       padgrp_set_drvdn(pad, config->drvdn);
-       padgrp_set_lpmd(pad, config->lpmd);
-       padgrp_set_schmt(pad, config->schmt);
-       padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++)
-               padctrl_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;
index 934e395..ed2462a 100644 (file)
@@ -8,7 +8,7 @@
 #include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/arch-tegra/ap.h>
-#include <asm/arch/apb_misc.h>
+#include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/emc.h>
 #include <asm/arch/tegra.h>
index 1931908..0df4a07 100644 (file)
@@ -14,9 +14,9 @@
  * The PINMUX macro is used to set up pinmux tables.
  */
 #define PINMUX(grp, mux, pupd, tri)                   \
-       {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+       {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
 
-static const struct pingroup_config disp1_default[] = {
+static const struct pmux_pingrp_config disp1_default[] = {
        PINMUX(LDI,   DISPA,      NORMAL,    NORMAL),
        PINMUX(LHP0,  DISPA,      NORMAL,    NORMAL),
        PINMUX(LHP1,  DISPA,      NORMAL,    NORMAL),
@@ -42,26 +42,26 @@ int funcmux_select(enum periph_id id, int config)
        case PERIPH_ID_UART1:
                switch (config) {
                case FUNCMUX_UART1_IRRX_IRTX:
-                       pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
-                       pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
-                       pinmux_tristate_disable(PINGRP_IRRX);
-                       pinmux_tristate_disable(PINGRP_IRTX);
+                       pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
+                       pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PMUX_PINGRP_IRRX);
+                       pinmux_tristate_disable(PMUX_PINGRP_IRTX);
                        break;
                case FUNCMUX_UART1_UAA_UAB:
-                       pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
-                       pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
-                       pinmux_tristate_disable(PINGRP_UAA);
-                       pinmux_tristate_disable(PINGRP_UAB);
+                       pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
+                       pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PMUX_PINGRP_UAA);
+                       pinmux_tristate_disable(PMUX_PINGRP_UAB);
                        bad_config = 0;
                        break;
                case FUNCMUX_UART1_GPU:
-                       pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
-                       pinmux_tristate_disable(PINGRP_GPU);
+                       pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PMUX_PINGRP_GPU);
                        bad_config = 0;
                        break;
                case FUNCMUX_UART1_SDIO1:
-                       pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
-                       pinmux_tristate_disable(PINGRP_SDIO1);
+                       pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
                        bad_config = 0;
                        break;
                }
@@ -77,53 +77,53 @@ int funcmux_select(enum periph_id id, int config)
                         * state the group to avoid driving any signal onto it
                         * until we know what's connected.
                         */
-                       pinmux_tristate_enable(PINGRP_SDB);
-                       pinmux_set_func(PINGRP_SDB,  PMUX_FUNC_SDIO3);
+                       pinmux_tristate_enable(PMUX_PINGRP_SDB);
+                       pinmux_set_func(PMUX_PINGRP_SDB,  PMUX_FUNC_SDIO3);
                }
                break;
 
        case PERIPH_ID_UART2:
                if (config == FUNCMUX_UART2_UAD) {
-                       pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
-                       pinmux_tristate_disable(PINGRP_UAD);
+                       pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
+                       pinmux_tristate_disable(PMUX_PINGRP_UAD);
                }
                break;
 
        case PERIPH_ID_UART4:
                if (config == FUNCMUX_UART4_GMC) {
-                       pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
-                       pinmux_tristate_disable(PINGRP_GMC);
+                       pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
+                       pinmux_tristate_disable(PMUX_PINGRP_GMC);
                }
                break;
 
        case PERIPH_ID_DVC_I2C:
                /* there is only one selection, pinmux_config is ignored */
                if (config == FUNCMUX_DVC_I2CP) {
-                       pinmux_set_func(PINGRP_I2CP, PMUX_FUNC_I2C);
-                       pinmux_tristate_disable(PINGRP_I2CP);
+                       pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
+                       pinmux_tristate_disable(PMUX_PINGRP_I2CP);
                }
                break;
 
        case PERIPH_ID_I2C1:
                /* support pinmux_config of 0 for now, */
                if (config == FUNCMUX_I2C1_RM) {
-                       pinmux_set_func(PINGRP_RM, PMUX_FUNC_I2C);
-                       pinmux_tristate_disable(PINGRP_RM);
+                       pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
+                       pinmux_tristate_disable(PMUX_PINGRP_RM);
                }
                break;
        case PERIPH_ID_I2C2: /* I2C2 */
                switch (config) {
                case FUNCMUX_I2C2_DDC:  /* DDC pin group, select I2C2 */
-                       pinmux_set_func(PINGRP_DDC, PMUX_FUNC_I2C2);
+                       pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
                        /* PTA to HDMI */
-                       pinmux_set_func(PINGRP_PTA, PMUX_FUNC_HDMI);
-                       pinmux_tristate_disable(PINGRP_DDC);
+                       pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
+                       pinmux_tristate_disable(PMUX_PINGRP_DDC);
                        break;
                case FUNCMUX_I2C2_PTA:  /* PTA pin group, select I2C2 */
-                       pinmux_set_func(PINGRP_PTA, PMUX_FUNC_I2C2);
+                       pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
                        /* set DDC_SEL to RSVDx (RSVD2 works for now) */
-                       pinmux_set_func(PINGRP_DDC, PMUX_FUNC_RSVD2);
-                       pinmux_tristate_disable(PINGRP_PTA);
+                       pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
+                       pinmux_tristate_disable(PMUX_PINGRP_PTA);
                        bad_config = 0;
                        break;
                }
@@ -131,50 +131,50 @@ int funcmux_select(enum periph_id id, int config)
        case PERIPH_ID_I2C3: /* I2C3 */
                /* support pinmux_config of 0 for now */
                if (config == FUNCMUX_I2C3_DTF) {
-                       pinmux_set_func(PINGRP_DTF, PMUX_FUNC_I2C3);
-                       pinmux_tristate_disable(PINGRP_DTF);
+                       pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
+                       pinmux_tristate_disable(PMUX_PINGRP_DTF);
                }
                break;
 
        case PERIPH_ID_SDMMC1:
                if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
-                       pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
-                       pinmux_tristate_disable(PINGRP_SDIO1);
+                       pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+                       pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
                }
                break;
 
        case PERIPH_ID_SDMMC2:
                if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
-                       pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
-                       pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
+                       pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
+                       pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
 
-                       pinmux_tristate_disable(PINGRP_DTA);
-                       pinmux_tristate_disable(PINGRP_DTD);
+                       pinmux_tristate_disable(PMUX_PINGRP_DTA);
+                       pinmux_tristate_disable(PMUX_PINGRP_DTD);
                }
                break;
 
        case PERIPH_ID_SDMMC3:
                switch (config) {
                case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
-                       pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3);
-                       pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3);
-                       pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3);
-                       pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3);
-
-                       pinmux_tristate_disable(PINGRP_SLXA);
-                       pinmux_tristate_disable(PINGRP_SLXC);
-                       pinmux_tristate_disable(PINGRP_SLXD);
-                       pinmux_tristate_disable(PINGRP_SLXK);
+                       pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
+
+                       pinmux_tristate_disable(PMUX_PINGRP_SLXA);
+                       pinmux_tristate_disable(PMUX_PINGRP_SLXC);
+                       pinmux_tristate_disable(PMUX_PINGRP_SLXD);
+                       pinmux_tristate_disable(PMUX_PINGRP_SLXK);
                        /* fall through */
 
                case FUNCMUX_SDMMC3_SDB_4BIT:
-                       pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
-                       pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
-                       pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
+                       pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
 
-                       pinmux_tristate_disable(PINGRP_SDB);
-                       pinmux_tristate_disable(PINGRP_SDC);
-                       pinmux_tristate_disable(PINGRP_SDD);
+                       pinmux_tristate_disable(PMUX_PINGRP_SDB);
+                       pinmux_tristate_disable(PMUX_PINGRP_SDC);
+                       pinmux_tristate_disable(PMUX_PINGRP_SDD);
                        bad_config = 0;
                        break;
                }
@@ -183,24 +183,24 @@ int funcmux_select(enum periph_id id, int config)
        case PERIPH_ID_SDMMC4:
                switch (config) {
                case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
-                       pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4);
-                       pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4);
+                       pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
+                       pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
 
-                       pinmux_tristate_disable(PINGRP_ATC);
-                       pinmux_tristate_disable(PINGRP_ATD);
+                       pinmux_tristate_disable(PMUX_PINGRP_ATC);
+                       pinmux_tristate_disable(PMUX_PINGRP_ATD);
                        break;
 
                case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
-                       pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
-                       pinmux_tristate_disable(PINGRP_GME);
+                       pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
+                       pinmux_tristate_disable(PMUX_PINGRP_GME);
                        /* fall through */
 
                case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
-                       pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
-                       pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+                       pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
+                       pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
 
-                       pinmux_tristate_disable(PINGRP_ATB);
-                       pinmux_tristate_disable(PINGRP_GMA);
+                       pinmux_tristate_disable(PMUX_PINGRP_ATB);
+                       pinmux_tristate_disable(PMUX_PINGRP_GMA);
                        bad_config = 0;
                        break;
                }
@@ -208,9 +208,10 @@ int funcmux_select(enum periph_id id, int config)
 
        case PERIPH_ID_KBC:
                if (config == FUNCMUX_DEFAULT) {
-                       enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB,
-                               PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE,
-                               PINGRP_KBCF};
+                       enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
+                               PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
+                               PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
+                               PMUX_PINGRP_KBCF};
                        int i;
 
                        for (i = 0; i < ARRAY_SIZE(grp); i++) {
@@ -223,44 +224,44 @@ int funcmux_select(enum periph_id id, int config)
 
        case PERIPH_ID_USB2:
                if (config == FUNCMUX_USB2_ULPI) {
-                       pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI);
-                       pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI);
-                       pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI);
+                       pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
+                       pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
+                       pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
 
-                       pinmux_tristate_disable(PINGRP_UAA);
-                       pinmux_tristate_disable(PINGRP_UAB);
-                       pinmux_tristate_disable(PINGRP_UDA);
+                       pinmux_tristate_disable(PMUX_PINGRP_UAA);
+                       pinmux_tristate_disable(PMUX_PINGRP_UAB);
+                       pinmux_tristate_disable(PMUX_PINGRP_UDA);
                }
                break;
 
        case PERIPH_ID_SPI1:
                if (config == FUNCMUX_SPI1_GMC_GMD) {
-                       pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
-                       pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+                       pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
+                       pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
 
-                       pinmux_tristate_disable(PINGRP_GMC);
-                       pinmux_tristate_disable(PINGRP_GMD);
+                       pinmux_tristate_disable(PMUX_PINGRP_GMC);
+                       pinmux_tristate_disable(PMUX_PINGRP_GMD);
                }
                break;
 
        case PERIPH_ID_NDFLASH:
                switch (config) {
                case FUNCMUX_NDFLASH_ATC:
-                       pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
-                       pinmux_tristate_disable(PINGRP_ATC);
+                       pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
+                       pinmux_tristate_disable(PMUX_PINGRP_ATC);
                        break;
                case FUNCMUX_NDFLASH_KBC_8_BIT:
-                       pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND);
-                       pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND);
-                       pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND);
-                       pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND);
-                       pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
-
-                       pinmux_tristate_disable(PINGRP_KBCA);
-                       pinmux_tristate_disable(PINGRP_KBCC);
-                       pinmux_tristate_disable(PINGRP_KBCD);
-                       pinmux_tristate_disable(PINGRP_KBCE);
-                       pinmux_tristate_disable(PINGRP_KBCF);
+                       pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
+                       pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
+                       pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
+                       pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
+                       pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
+
+                       pinmux_tristate_disable(PMUX_PINGRP_KBCA);
+                       pinmux_tristate_disable(PMUX_PINGRP_KBCC);
+                       pinmux_tristate_disable(PMUX_PINGRP_KBCD);
+                       pinmux_tristate_disable(PMUX_PINGRP_KBCE);
+                       pinmux_tristate_disable(PMUX_PINGRP_KBCF);
 
                        bad_config = 0;
                        break;
@@ -270,13 +271,13 @@ int funcmux_select(enum periph_id id, int config)
                if (config == FUNCMUX_DEFAULT) {
                        int i;
 
-                       for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
+                       for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
                                pinmux_set_func(i, PMUX_FUNC_DISPA);
                                pinmux_tristate_disable(i);
                                pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
                        }
-                       pinmux_config_table(disp1_default,
-                                           ARRAY_SIZE(disp1_default));
+                       pinmux_config_pingrp_table(disp1_default,
+                                                  ARRAY_SIZE(disp1_default));
                }
                break;
 
index a65e991..e484f99 100644 (file)
@@ -8,10 +8,8 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/tegra.h>
 #include <asm/arch/pinmux.h>
 
-
 /*
  * This defines the order of the pin mux control bits in the registers. For
  * some reason there is no correspendence between the tristate, pin mux and
@@ -256,302 +254,172 @@ enum pmux_pullid {
        PUCTL_NONE = -1
 };
 
-struct tegra_pingroup_desc {
-       const char *name;
-       enum pmux_func funcs[4];
-       enum pmux_func func_safe;
-       enum pmux_vddio vddio;
-       enum pmux_ctlid ctl_id;
-       enum pmux_pullid pull_id;
-};
-
-
-/* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
-#define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
-
-/* Mask value for a tristate (within TRISTATE_REG(id)) */
-#define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
-
-/* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
-#define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
-
-/* Converts a PUCTL id to a shift position */
-#define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
-
-/* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
-#define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
-
-/* Converts a MUXCTL id to a shift position */
-#define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
-
 /* Convenient macro for defining pin group properties */
-#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd)                \
+#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd)      \
        {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
                .funcs = {                              \
-                       PMUX_FUNC_ ## f0,                       \
-                       PMUX_FUNC_ ## f1,                       \
-                       PMUX_FUNC_ ## f2,                       \
-                       PMUX_FUNC_ ## f3,                       \
+                       PMUX_FUNC_ ## f0,               \
+                       PMUX_FUNC_ ## f1,               \
+                       PMUX_FUNC_ ## f2,               \
+                       PMUX_FUNC_ ## f3,               \
                },                                      \
-               .func_safe = PMUX_FUNC_ ## f_safe,              \
                .ctl_id = mux,                          \
                .pull_id = pupd                         \
        }
 
 /* A normal pin group where the mux name and pull-up name match */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe)              \
-               PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe,    \
-                       MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
+#define PIN(pingrp, f0, f1, f2, f3) \
+       PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
 
 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
-#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd)               \
-               PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe,    \
-                       MUXCTL_ ## pg_name, PUCTL_ ## pupd)
+#define PINP(pingrp, f0, f1, f2, f3, pupd) \
+       PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
 
 /* A pin group number which is not used */
 #define PIN_RESERVED \
-       PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
-
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
-       PIN(ATA,  NAND,  IDE,    NAND,   GMI,       RSVD,        IDE),
-       PIN(ATB,  NAND,  IDE,    NAND,   GMI,       SDIO4,       IDE),
-       PIN(ATC,  NAND,  IDE,    NAND,   GMI,       SDIO4,       IDE),
-       PIN(ATD,  NAND,  IDE,    NAND,   GMI,       SDIO4,       IDE),
-       PIN(CDEV1, AUDIO, OSC,   PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
-       PIN(CDEV2, AUDIO, OSC,   AHB_CLK, APB_CLK, PLLP_OUT4,    OSC),
-       PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
-               PLLC_OUT1),
-       PIN(DAP1, AUDIO, DAP1,   RSVD,   GMI,       SDIO2,       DAP1),
-
-       PIN(DAP2, AUDIO, DAP2,   TWC,    RSVD,      GMI,         DAP2),
-       PIN(DAP3, BB,    DAP3,   RSVD,   RSVD,      RSVD,        DAP3),
-       PIN(DAP4, UART,  DAP4,   RSVD,   GMI,       RSVD,        DAP4),
-       PIN(DTA,  VI,    RSVD,   SDIO2,  VI,        RSVD,        RSVD4),
-       PIN(DTB,  VI,    RSVD,   RSVD,   VI,        SPI1,        RSVD1),
-       PIN(DTC,  VI,    RSVD,   RSVD,   VI,        RSVD,        RSVD1),
-       PIN(DTD,  VI,    RSVD,   SDIO2,  VI,        RSVD,        RSVD1),
-       PIN(DTE,  VI,    RSVD,   RSVD,   VI,        SPI1,        RSVD1),
-
-       PINP(GPU, UART,  PWM,    UARTA,  GMI,       RSVD,        RSVD4,
-               GPSLXAU),
-       PIN(GPV,  SD,    PCIE,   RSVD,   RSVD,      RSVD,        PCIE),
-       PIN(I2CP, SYS,   I2C,    RSVD,   RSVD,      RSVD,        RSVD4),
-       PIN(IRTX, UART,  UARTA,  UARTB,  GMI,       SPI4,        UARTB),
-       PIN(IRRX, UART,  UARTA,  UARTB,  GMI,       SPI4,        UARTB),
-       PIN(KBCB, SYS,   KBC,    NAND,   SDIO2,     MIO,         KBC),
-       PIN(KBCA, SYS,   KBC,    NAND,   SDIO2,     EMC_TEST0_DLL, KBC),
-       PINP(PMC, SYS,   PWR_ON, PWR_INTR, RSVD,    RSVD,        PWR_ON, NONE),
-
-       PIN(PTA,  NAND,  I2C2,   HDMI,   GMI,       RSVD,        RSVD4),
-       PIN(RM,   UART,  I2C,    RSVD,   RSVD,      RSVD,        RSVD4),
-       PIN(KBCE, SYS,   KBC,    NAND,   OWR,       RSVD,        KBC),
-       PIN(KBCF, SYS,   KBC,    NAND,   TRACE,     MIO,         KBC),
-       PIN(GMA,  NAND,  UARTE,  SPI3,   GMI,       SDIO4,       SPI3),
-       PIN(GMC,  NAND,  UARTD,  SPI4,   GMI,       SFLASH,      SPI4),
-       PIN(SDMMC1, BB,  SDIO1,  RSVD,   UARTE,     UARTA,       RSVD2),
-       PIN(OWC,  SYS,   OWR,    RSVD,   RSVD,      RSVD,        OWR),
-
-       PIN(GME,  NAND,  RSVD,   DAP5,   GMI,       SDIO4,       GMI),
-       PIN(SDC,  SD,    PWM,    TWC,    SDIO3,     SPI3,        TWC),
-       PIN(SDD,  SD,    UARTA,  PWM,    SDIO3,     SPI3,        PWM),
+       PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
+
+#define DRVGRP(drvgrp) \
+       PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
+
+static const struct pmux_pingrp_desc tegra20_pingroups[] = {
+       PIN(ATA,    IDE,       NAND,      GMI,       RSVD4),
+       PIN(ATB,    IDE,       NAND,      GMI,       SDIO4),
+       PIN(ATC,    IDE,       NAND,      GMI,       SDIO4),
+       PIN(ATD,    IDE,       NAND,      GMI,       SDIO4),
+       PIN(CDEV1,  OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC),
+       PIN(CDEV2,  OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4),
+       PIN(CSUS,   PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
+       PIN(DAP1,   DAP1,      RSVD2,     GMI,       SDIO2),
+
+       PIN(DAP2,   DAP2,      TWC,       RSVD3,     GMI),
+       PIN(DAP3,   DAP3,      RSVD2,     RSVD3,     RSVD4),
+       PIN(DAP4,   DAP4,      RSVD2,     GMI,       RSVD4),
+       PIN(DTA,    RSVD1,     SDIO2,     VI,        RSVD4),
+       PIN(DTB,    RSVD1,     RSVD2,     VI,        SPI1),
+       PIN(DTC,    RSVD1,     RSVD2,     VI,        RSVD4),
+       PIN(DTD,    RSVD1,     SDIO2,     VI,        RSVD4),
+       PIN(DTE,    RSVD1,     RSVD2,     VI,        SPI1),
+
+       PINP(GPU,   PWM,       UARTA,     GMI,       RSVD4,         GPSLXAU),
+       PIN(GPV,    PCIE,      RSVD2,     RSVD3,     RSVD4),
+       PIN(I2CP,   I2C,       RSVD2,     RSVD3,     RSVD4),
+       PIN(IRTX,   UARTA,     UARTB,     GMI,       SPI4),
+       PIN(IRRX,   UARTA,     UARTB,     GMI,       SPI4),
+       PIN(KBCB,   KBC,       NAND,      SDIO2,     MIO),
+       PIN(KBCA,   KBC,       NAND,      SDIO2,     EMC_TEST0_DLL),
+       PINP(PMC,   PWR_ON,    PWR_INTR,  RSVD3,     RSVD4,         NONE),
+
+       PIN(PTA,    I2C2,      HDMI,      GMI,       RSVD4),
+       PIN(RM,     I2C,       RSVD2,     RSVD3,     RSVD4),
+       PIN(KBCE,   KBC,       NAND,      OWR,       RSVD4),
+       PIN(KBCF,   KBC,       NAND,      TRACE,     MIO),
+       PIN(GMA,    UARTE,     SPI3,      GMI,       SDIO4),
+       PIN(GMC,    UARTD,     SPI4,      GMI,       SFLASH),
+       PIN(SDMMC1, SDIO1,     RSVD2,     UARTE,     UARTA),
+       PIN(OWC,    OWR,       RSVD2,     RSVD3,     RSVD4),
+
+       PIN(GME,    RSVD1,     DAP5,      GMI,       SDIO4),
+       PIN(SDC,    PWM,       TWC,       SDIO3,     SPI3),
+       PIN(SDD,    UARTA,     PWM,       SDIO3,     SPI3),
        PIN_RESERVED,
-       PINP(SLXA, SD,   PCIE,   SPI4,   SDIO3,     SPI2,        PCIE, CRTP),
-       PIN(SLXC, SD,    SPDIF,  SPI4,   SDIO3,     SPI2,        SPI4),
-       PIN(SLXD, SD,    SPDIF,  SPI4,   SDIO3,     SPI2,        SPI4),
-       PIN(SLXK, SD,    PCIE,   SPI4,   SDIO3,     SPI2,        PCIE),
-
-       PIN(SPDI, AUDIO, SPDIF,  RSVD,   I2C,       SDIO2,       RSVD2),
-       PIN(SPDO, AUDIO, SPDIF,  RSVD,   I2C,       SDIO2,       RSVD2),
-       PIN(SPIA, AUDIO, SPI1,   SPI2,   SPI3,      GMI,         GMI),
-       PIN(SPIB, AUDIO, SPI1,   SPI2,   SPI3,      GMI,         GMI),
-       PIN(SPIC, AUDIO, SPI1,   SPI2,   SPI3,      GMI,         GMI),
-       PIN(SPID, AUDIO, SPI2,   SPI1,   SPI2_ALT,  GMI,         GMI),
-       PIN(SPIE, AUDIO, SPI2,   SPI1,   SPI2_ALT,  GMI,         GMI),
-       PIN(SPIF, AUDIO, SPI3,   SPI1,   SPI2,      RSVD,        RSVD4),
-
-       PIN(SPIG, AUDIO, SPI3,   SPI2,   SPI2_ALT,  I2C,         SPI2_ALT),
-       PIN(SPIH, AUDIO, SPI3,   SPI2,   SPI2_ALT,  I2C,         SPI2_ALT),
-       PIN(UAA,  BB,    SPI3,   MIPI_HS, UARTA,    ULPI,        MIPI_HS),
-       PIN(UAB,  BB,    SPI2,   MIPI_HS, UARTA,    ULPI,        MIPI_HS),
-       PIN(UAC,  BB,    OWR,    RSVD,   RSVD,      RSVD,        RSVD4),
-       PIN(UAD,  UART,  UARTB,  SPDIF,  UARTA,     SPI4,        SPDIF),
-       PIN(UCA,  UART,  UARTC,  RSVD,   GMI,       RSVD,        RSVD4),
-       PIN(UCB,  UART,  UARTC,  PWM,    GMI,       RSVD,        RSVD4),
+       PINP(SLXA,  PCIE,      SPI4,      SDIO3,     SPI2,          CRTP),
+       PIN(SLXC,   SPDIF,     SPI4,      SDIO3,     SPI2),
+       PIN(SLXD,   SPDIF,     SPI4,      SDIO3,     SPI2),
+       PIN(SLXK,   PCIE,      SPI4,      SDIO3,     SPI2),
+
+       PIN(SPDI,   SPDIF,     RSVD2,     I2C,       SDIO2),
+       PIN(SPDO,   SPDIF,     RSVD2,     I2C,       SDIO2),
+       PIN(SPIA,   SPI1,      SPI2,      SPI3,      GMI),
+       PIN(SPIB,   SPI1,      SPI2,      SPI3,      GMI),
+       PIN(SPIC,   SPI1,      SPI2,      SPI3,      GMI),
+       PIN(SPID,   SPI2,      SPI1,      SPI2_ALT,  GMI),
+       PIN(SPIE,   SPI2,      SPI1,      SPI2_ALT,  GMI),
+       PIN(SPIF,   SPI3,      SPI1,      SPI2,      RSVD4),
+
+       PIN(SPIG,   SPI3,      SPI2,      SPI2_ALT,  I2C),
+       PIN(SPIH,   SPI3,      SPI2,      SPI2_ALT,  I2C),
+       PIN(UAA,    SPI3,      MIPI_HS,   UARTA,     ULPI),
+       PIN(UAB,    SPI2,      MIPI_HS,   UARTA,     ULPI),
+       PIN(UAC,    OWR,       RSVD2,     RSVD3,     RSVD4),
+       PIN(UAD,    UARTB,     SPDIF,     UARTA,     SPI4),
+       PIN(UCA,    UARTC,     RSVD2,     GMI,       RSVD4),
+       PIN(UCB,    UARTC,     PWM,       GMI,       RSVD4),
 
        PIN_RESERVED,
-       PIN(ATE,  NAND,  IDE,    NAND,   GMI,       RSVD,        IDE),
-       PIN(KBCC, SYS,   KBC,    NAND,   TRACE,     EMC_TEST1_DLL, KBC),
+       PIN(ATE,    IDE,       NAND,      GMI,       RSVD4),
+       PIN(KBCC,   KBC,       NAND,      TRACE,     EMC_TEST1_DLL),
        PIN_RESERVED,
        PIN_RESERVED,
-       PIN(GMB,  NAND,  IDE,    NAND,   GMI,       GMI_INT,     GMI),
-       PIN(GMD,  NAND,  RSVD,   NAND,   GMI,       SFLASH,      GMI),
-       PIN(DDC,  LCD,   I2C2,   RSVD,   RSVD,      RSVD,        RSVD4),
+       PIN(GMB,    IDE,       NAND,      GMI,       GMI_INT),
+       PIN(GMD,    RSVD1,     NAND,      GMI,       SFLASH),
+       PIN(DDC,    I2C2,      RSVD2,     RSVD3,     RSVD4),
 
        /* 64 */
-       PINP(LD0,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD1,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD2,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD3,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD4,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD5,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD6,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD7,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-
-       PINP(LD8,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD9,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD10, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD11, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD12, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD13, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD14, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD15, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-
-       PINP(LD16, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LD17),
-       PINP(LD17, LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LD17),
-       PINP(LHP0, LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LD21_20),
-       PINP(LHP1, LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LD19_18),
-       PINP(LHP2, LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LD19_18),
-       PINP(LVP0, LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LC),
-       PINP(LVP1, LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LD21_20),
-       PINP(HDINT, LCD, HDMI,   RSVD,   RSVD,      RSVD,     HDMI , LC),
-
-       PINP(LM0,  LCD,  DISPA,  DISPB,  SPI3,      RSVD,     RSVD4, LC),
-       PINP(LM1,  LCD,  DISPA,  DISPB,  RSVD,      CRT,      RSVD3, LC),
-       PINP(LVS,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LC),
-       PINP(LSC0, LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LC),
-       PINP(LSC1, LCD,  DISPA,  DISPB,  SPI3,      HDMI,     DISPA, LS),
-       PINP(LSCK, LCD,  DISPA,  DISPB,  SPI3,      HDMI,     DISPA, LS),
-       PINP(LDC,  LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LS),
-       PINP(LCSN, LCD,  DISPA,  DISPB,  SPI3,      RSVD,     RSVD4, LS),
+       PINP(LD0,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD1,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD2,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD3,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD4,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD5,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD6,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD7,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+
+       PINP(LD8,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD9,   DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD10,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD11,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD12,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD13,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD14,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD15,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+
+       PINP(LD16,  DISPA,     DISPB,     XIO,       RSVD4,         LD17),
+       PINP(LD17,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD17),
+       PINP(LHP0,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD21_20),
+       PINP(LHP1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD19_18),
+       PINP(LHP2,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD19_18),
+       PINP(LVP0,  DISPA,     DISPB,     RSVD3,     RSVD4,         LC),
+       PINP(LVP1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LD21_20),
+       PINP(HDINT, HDMI,      RSVD2,     RSVD3,     RSVD4,         LC),
+
+       PINP(LM0,   DISPA,     DISPB,     SPI3,      RSVD4,         LC),
+       PINP(LM1,   DISPA,     DISPB,     RSVD3,     CRT,           LC),
+       PINP(LVS,   DISPA,     DISPB,     XIO,       RSVD4,         LC),
+       PINP(LSC0,  DISPA,     DISPB,     XIO,       RSVD4,         LC),
+       PINP(LSC1,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+       PINP(LSCK,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+       PINP(LDC,   DISPA,     DISPB,     RSVD3,     RSVD4,         LS),
+       PINP(LCSN,  DISPA,     DISPB,     SPI3,      RSVD4,         LS),
 
        /* 96 */
-       PINP(LSPI, LCD,  DISPA,  DISPB,  XIO,       HDMI,     DISPA, LC),
-       PINP(LSDA, LCD,  DISPA,  DISPB,  SPI3,      HDMI,     DISPA, LS),
-       PINP(LSDI, LCD,  DISPA,  DISPB,  SPI3,      RSVD,     DISPA, LS),
-       PINP(LPW0, LCD,  DISPA,  DISPB,  SPI3,      HDMI,     DISPA, LS),
-       PINP(LPW1, LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LS),
-       PINP(LPW2, LCD,  DISPA,  DISPB,  SPI3,      HDMI,     DISPA, LS),
-       PINP(LDI,  LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LD23_22),
-       PINP(LHS,  LCD,  DISPA,  DISPB,  XIO,       RSVD,     RSVD4, LC),
-
-       PINP(LPP,  LCD,  DISPA,  DISPB,  RSVD,      RSVD,     RSVD4, LD23_22),
+       PINP(LSPI,  DISPA,     DISPB,     XIO,       HDMI,          LC),
+       PINP(LSDA,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+       PINP(LSDI,  DISPA,     DISPB,     SPI3,      RSVD4,         LS),
+       PINP(LPW0,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+       PINP(LPW1,  DISPA,     DISPB,     RSVD3,     RSVD4,         LS),
+       PINP(LPW2,  DISPA,     DISPB,     SPI3,      HDMI,          LS),
+       PINP(LDI,   DISPA,     DISPB,     RSVD3,     RSVD4,         LD23_22),
+       PINP(LHS,   DISPA,     DISPB,     XIO,       RSVD4,         LC),
+
+       PINP(LPP,   DISPA,     DISPB,     RSVD3,     RSVD4,         LD23_22),
        PIN_RESERVED,
-       PIN(KBCD,  SYS,  KBC,    NAND,   SDIO2,     MIO,      KBC),
-       PIN(GPU7,  SYS,  RTCK,   RSVD,   RSVD,      RSVD,     RTCK),
-       PIN(DTF,   VI,   I2C3,   RSVD,   VI,        RSVD,     RSVD4),
-       PIN(UDA,   BB,   SPI1,   RSVD,   UARTD,     ULPI,     RSVD2),
-       PIN(CRTP,  LCD,  CRT,    RSVD,   RSVD,      RSVD,     RSVD),
-       PINP(SDB,  SD,   UARTA,  PWM,    SDIO3,     SPI2,     PWM,   NONE),
+       PIN(KBCD,   KBC,       NAND,      SDIO2,     MIO),
+       PIN(GPU7,   RTCK,      RSVD2,     RSVD3,     RSVD4),
+       PIN(DTF,    I2C3,      RSVD2,     VI,        RSVD4),
+       PIN(UDA,    SPI1,      RSVD2,     UARTD,     ULPI),
+       PIN(CRTP,   CRT,       RSVD2,     RSVD3,     RSVD4),
+       PINP(SDB,   UARTA,     PWM,       SDIO3,     SPI2,          NONE),
 
        /* these pin groups only have pullup and pull down control */
-       PINALL(CK32,  SYS,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(DDRC,  DDR,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(PMCA,  SYS,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(PMCB,  SYS,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(PMCC,  SYS,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(PMCD,  SYS,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(PMCE,  SYS,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(XM2C,  DDR,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
-       PINALL(XM2D,  DDR,   RSVD, RSVD, RSVD, RSVD,  RSVD, MUXCTL_NONE,
-               PUCTL_NONE),
+       DRVGRP(CK32),
+       DRVGRP(DDRC),
+       DRVGRP(PMCA),
+       DRVGRP(PMCB),
+       DRVGRP(PMCC),
+       DRVGRP(PMCD),
+       DRVGRP(PMCE),
+       DRVGRP(XM2C),
+       DRVGRP(XM2D),
 };
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
-       u32 reg;
-
-       reg = readl(tri);
-       if (enable)
-               reg |= TRISTATE_MASK(pin);
-       else
-               reg &= ~TRISTATE_MASK(pin);
-       writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
-       u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
-       u32 mask_bit;
-       u32 reg;
-       mask_bit = PULL_SHIFT(pull_id);
-
-       reg = readl(pull);
-       reg &= ~(0x3 << mask_bit);
-       reg |= pupd << mask_bit;
-       writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
-       u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
-       u32 mask_bit;
-       int i, mux = -1;
-       u32 reg;
-
-       assert(pmux_func_isvalid(func));
-
-       /* Handle special values */
-       if (func >= PMUX_FUNC_RSVD1) {
-               mux = (func - PMUX_FUNC_RSVD1) & 0x3;
-       } else {
-               /* Search for the appropriate function */
-               for (i = 0; i < 4; i++) {
-                       if (tegra_soc_pingroups[pin].funcs[i] == func) {
-                               mux = i;
-                               break;
-                       }
-               }
-       }
-       assert(mux != -1);
-
-       mask_bit = MUXCTL_SHIFT(mux_id);
-       reg = readl(muxctl);
-       reg &= ~(0x3 << mask_bit);
-       reg |= mux << mask_bit;
-       writel(reg, muxctl);
-}
-
-void pinmux_config_pingroup(const struct pingroup_config *config)
-{
-       enum pmux_pingrp pin = config->pingroup;
-
-       pinmux_set_func(pin, config->func);
-       pinmux_set_pullupdown(pin, config->pull);
-       pinmux_set_tristate(pin, config->tristate);
-}
-
-void pinmux_config_table(const struct pingroup_config *config, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++)
-               pinmux_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
index 8beba53..5fdc4bb 100644 (file)
@@ -15,6 +15,7 @@
 #include <asm/arch/sdram_param.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/fuse.h>
@@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void)
 {
        u32 ram_code;
        struct sdram_params sdram;
-       struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       struct apb_misc_pp_ctlr *apb_misc =
+                               (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
        struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        struct apb_misc_gp_ctlr *gp =
                        (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
@@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void)
        union fbio_spare_reg fbio_spare;
 
        /* get ram code that is used as index to array sdram_params in BCT */
-       ram_code = (readl(&pmt->pmt_strap_opt_a) >>
-                       STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
+       ram_code = (readl(&apb_misc->strapping_opt_a) >>
+                         STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
        memcpy(&sdram,
               (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
               sizeof(sdram));
index b910f78..27ce5f4 100644 (file)
@@ -12,6 +12,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/apb_misc.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/pmc.h>
 #include <asm/arch-tegra/warmboot.h>
@@ -21,7 +22,8 @@
 
 void wb_start(void)
 {
-       struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       struct apb_misc_pp_ctlr *apb_misc =
+                               (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
        struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
        struct clk_rst_ctlr *clkrst =
@@ -33,7 +35,7 @@ void wb_start(void)
        u32 reg;
 
        /* enable JTAG & TBE */
-       writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl);
+       writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
 
        /* Are we running where we're supposed to be? */
        asm volatile (
index e24c57e..409335c 100644 (file)
@@ -29,14 +29,18 @@ int funcmux_select(enum periph_id id, int config)
        case PERIPH_ID_UART1:
                switch (config) {
                case FUNCMUX_UART1_ULPI:
-                       pinmux_set_func(PINGRP_ULPI_DATA0, PMUX_FUNC_UARTA);
-                       pinmux_set_func(PINGRP_ULPI_DATA1, PMUX_FUNC_UARTA);
-                       pinmux_set_func(PINGRP_ULPI_DATA2, PMUX_FUNC_UARTA);
-                       pinmux_set_func(PINGRP_ULPI_DATA3, PMUX_FUNC_UARTA);
-                       pinmux_tristate_disable(PINGRP_ULPI_DATA0);
-                       pinmux_tristate_disable(PINGRP_ULPI_DATA1);
-                       pinmux_tristate_disable(PINGRP_ULPI_DATA2);
-                       pinmux_tristate_disable(PINGRP_ULPI_DATA3);
+                       pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1,
+                                       PMUX_FUNC_UARTA);
+                       pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2,
+                                       PMUX_FUNC_UARTA);
+                       pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3,
+                                       PMUX_FUNC_UARTA);
+                       pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4,
+                                       PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1);
+                       pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2);
+                       pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3);
+                       pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4);
                        break;
                }
                break;
index eecf058..7eb0574 100644 (file)
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
  */
 
-/* Tegra30 pin multiplexing functions */
-
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/tegra.h>
 #include <asm/arch/pinmux.h>
 
-struct tegra_pingroup_desc {
-       const char *name;
-       enum pmux_func funcs[4];
-       enum pmux_func func_safe;
-       enum pmux_vddio vddio;
-       enum pmux_pin_io io;
-};
-
-#define PMUX_MUXCTL_SHIFT      0
-#define PMUX_PULL_SHIFT                2
-#define PMUX_TRISTATE_SHIFT    4
-#define PMUX_TRISTATE_MASK     (1 << PMUX_TRISTATE_SHIFT)
-#define PMUX_IO_SHIFT          5
-#define PMUX_OD_SHIFT          6
-#define PMUX_LOCK_SHIFT                7
-#define PMUX_IO_RESET_SHIFT    8
-
-#define PGRP_HSM_SHIFT         2
-#define PGRP_SCHMT_SHIFT       3
-#define PGRP_LPMD_SHIFT                4
-#define PGRP_LPMD_MASK         (3 << PGRP_LPMD_SHIFT)
-#define PGRP_DRVDN_SHIFT       12
-#define PGRP_DRVDN_MASK                (0x7F << PGRP_DRVDN_SHIFT)
-#define PGRP_DRVUP_SHIFT       20
-#define PGRP_DRVUP_MASK                (0x7F << PGRP_DRVUP_SHIFT)
-#define PGRP_SLWR_SHIFT                28
-#define PGRP_SLWR_MASK         (3 << PGRP_SLWR_SHIFT)
-#define PGRP_SLWF_SHIFT                30
-#define PGRP_SLWF_MASK         (3 << PGRP_SLWF_SHIFT)
-
-/* Convenient macro for defining pin group properties */
-#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
-       {                                               \
-               .vddio = PMUX_VDDIO_ ## vdd,            \
-               .funcs = {                              \
-                       PMUX_FUNC_ ## f0,               \
-                       PMUX_FUNC_ ## f1,               \
-                       PMUX_FUNC_ ## f2,               \
-                       PMUX_FUNC_ ## f3,               \
-               },                                      \
-               .func_safe = PMUX_FUNC_RSVD1,           \
-               .io = PMUX_PIN_ ## iod,                 \
+#define PIN(pin, f0, f1, f2, f3)       \
+       {                               \
+               .funcs = {              \
+                       PMUX_FUNC_##f0, \
+                       PMUX_FUNC_##f1, \
+                       PMUX_FUNC_##f2, \
+                       PMUX_FUNC_##f3, \
+               },                      \
        }
 
-/* Input and output pins */
-#define PINI(pg_name, vdd, f0, f1, f2, f3) \
-       PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
-#define PINO(pg_name, vdd, f0, f1, f2, f3) \
-       PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
-
-const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
-       /*      NAME      VDD      f0           f1         f2       f3  */
-       PINI(ULPI_DATA0,  BB,      SPI3,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA1,  BB,      SPI3,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA2,  BB,      SPI3,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA3,  BB,      SPI3,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA4,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA5,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA6,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_DATA7,  BB,      SPI2,        HSI,       UARTA,   ULPI),
-       PINI(ULPI_CLK,    BB,      SPI1,        RSVD2,     UARTD,   ULPI),
-       PINI(ULPI_DIR,    BB,      SPI1,        RSVD2,     UARTD,   ULPI),
-       PINI(ULPI_NXT,    BB,      SPI1,        RSVD2,     UARTD,   ULPI),
-       PINI(ULPI_STP,    BB,      SPI1,        RSVD2,     UARTD,   ULPI),
-       PINI(DAP3_FS,     BB,      I2S2,        RSVD2,     DISPA,   DISPB),
-       PINI(DAP3_DIN,    BB,      I2S2,        RSVD2,     DISPA,   DISPB),
-       PINI(DAP3_DOUT,   BB,      I2S2,        RSVD2,     DISPA,   DISPB),
-       PINI(DAP3_SCLK,   BB,      I2S2,        RSVD2,     DISPA,   DISPB),
-       PINI(GPIO_PV0,    BB,      RSVD1,       RSVD2,     RSVD3,   RSVD4),
-       PINI(GPIO_PV1,    BB,      RSVD1,       RSVD2,     RSVD3,   RSVD4),
-       PINI(SDMMC1_CLK,  SDMMC1,  SDMMC1,      RSVD2,     RSVD3,   UARTA),
-       PINI(SDMMC1_CMD,  SDMMC1,  SDMMC1,      RSVD2,     RSVD3,   UARTA),
-       PINI(SDMMC1_DAT3, SDMMC1,  SDMMC1,      RSVD2,     UARTE,   UARTA),
-       PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,      RSVD2,     UARTE,   UARTA),
-       PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,      RSVD2,     UARTE,   UARTA),
-       PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,      RSVD2,     UARTE,   UARTA),
-       PINI(GPIO_PV2,    SDMMC1,  OWR,         RSVD2,     RSVD3,   RSVD4),
-       PINI(GPIO_PV3,    SDMMC1,  CLK_12M_OUT, RSVD2,     RSVD3,   RSVD4),
-       PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2,  RSVD2,     RSVD3,   RSVD4),
-       PINI(CLK2_REQ,    SDMMC1,  DAP,         RSVD2,     RSVD3,   RSVD4),
-       PINO(LCD_PWR1,    LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_PWR2,    LCD,     DISPA,       DISPB,     SPI5,    HDCP),
-       PINO(LCD_SDIN,    LCD,     DISPA,       DISPB,     SPI5,    RSVD4),
-       PINO(LCD_SDOUT,   LCD,     DISPA,       DISPB,     SPI5,    HDCP),
-       PINO(LCD_WR_N,    LCD,     DISPA,       DISPB,     SPI5,    HDCP),
-       PINO(LCD_CS0_N,   LCD,     DISPA,       DISPB,     SPI5,    RSVD4),
-       PINO(LCD_DC0,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_SCK,     LCD,     DISPA,       DISPB,     SPI5,    HDCP),
-       PINO(LCD_PWR0,    LCD,     DISPA,       DISPB,     SPI5,    HDCP),
-       PINO(LCD_PCLK,    LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_DE,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_HSYNC,   LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_VSYNC,   LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D0,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D1,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D2,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D3,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D4,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D5,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D6,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D7,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D8,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D9,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D10,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D11,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D12,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D13,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D14,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D15,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D16,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D17,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D18,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D19,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D20,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D21,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D22,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_D23,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_CS1_N,   LCD,     DISPA,       DISPB,     SPI5,    RSVD4),
-       PINO(LCD_M1,      LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINO(LCD_DC1,     LCD,     DISPA,       DISPB,     RSVD3,   RSVD4),
-       PINI(HDMI_INT,    LCD,     HDMI,        RSVD2,     RSVD3,   RSVD4),
-       PINI(DDC_SCL,     LCD,     I2C4,        RSVD2,     RSVD3,   RSVD4),
-       PINI(DDC_SDA,     LCD,     I2C4,        RSVD2,     RSVD3,   RSVD4),
-       PINI(CRT_HSYNC,   LCD,     CRT,         RSVD2,     RSVD3,   RSVD4),
-       PINI(CRT_VSYNC,   LCD,     CRT,         RSVD2,     RSVD3,   RSVD4),
-       PINI(VI_D0,       VI,      DDR,         RSVD2,     VI,      RSVD4),
-       PINI(VI_D1,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D2,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D3,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D4,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D5,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D6,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D7,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D8,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D9,       VI,      DDR,         SDMMC2,    VI,      RSVD4),
-       PINI(VI_D10,      VI,      DDR,         RSVD2,     VI,      RSVD4),
-       PINI(VI_D11,      VI,      DDR,         RSVD2,     VI,      RSVD4),
-       PINI(VI_PCLK,     VI,      RSVD1,       SDMMC2,    VI,      RSVD4),
-       PINI(VI_MCLK,     VI,      VI,          VI,        VI,      VI),
-       PINI(VI_VSYNC,    VI,      DDR,         RSVD2,     VI,      RSVD4),
-       PINI(VI_HSYNC,    VI,      DDR,         RSVD2,     VI,      RSVD4),
-       PINI(UART2_RXD,   UART,    UARTB,       SPDIF,     UARTA,   SPI4),
-       PINI(UART2_TXD,   UART,    UARTB,       SPDIF,     UARTA,   SPI4),
-       PINI(UART2_RTS_N, UART,    UARTA,       UARTB,     GMI,     SPI4),
-       PINI(UART2_CTS_N, UART,    UARTA,       UARTB,     GMI,     SPI4),
-       PINI(UART3_TXD,   UART,    UARTC,       RSVD2,     GMI,     RSVD4),
-       PINI(UART3_RXD,   UART,    UARTC,       RSVD2,     GMI,     RSVD4),
-       PINI(UART3_CTS_N, UART,    UARTC,       RSVD2,     GMI,     RSVD4),
-       PINI(UART3_RTS_N, UART,    UARTC,       PWM0,      GMI,     RSVD4),
-       PINI(GPIO_PU0,    UART,    OWR,         UARTA,     GMI,     RSVD4),
-       PINI(GPIO_PU1,    UART,    RSVD1,       UARTA,     GMI,     RSVD4),
-       PINI(GPIO_PU2,    UART,    RSVD1,       UARTA,     GMI,     RSVD4),
-       PINI(GPIO_PU3,    UART,    PWM0,        UARTA,     GMI,     RSVD4),
-       PINI(GPIO_PU4,    UART,    PWM1,        UARTA,     GMI,     RSVD4),
-       PINI(GPIO_PU5,    UART,    PWM2,        UARTA,     GMI,     RSVD4),
-       PINI(GPIO_PU6,    UART,    PWM3,        UARTA,     GMI,     RSVD4),
-       PINI(GEN1_I2C_SDA, UART,   I2C1,        RSVD2,     RSVD3,   RSVD4),
-       PINI(GEN1_I2C_SCL, UART,   I2C1,        RSVD2,     RSVD3,   RSVD4),
-       PINI(DAP4_FS,     UART,    I2S3,        RSVD2,     GMI,     RSVD4),
-       PINI(DAP4_DIN,    UART,    I2S3,        RSVD2,     GMI,     RSVD4),
-       PINI(DAP4_DOUT,   UART,    I2S3,        RSVD2,     GMI,     RSVD4),
-       PINI(DAP4_SCLK,   UART,    I2S3,        RSVD2,     GMI,     RSVD4),
-       PINI(CLK3_OUT,    UART,    EXTPERIPH3,  RSVD2,     RSVD3,   RSVD4),
-       PINI(CLK3_REQ,    UART,    DEV3,        RSVD2,     RSVD3,   RSVD4),
-       PINI(GMI_WP_N,    GMI,     RSVD1,       NAND,      GMI,     GMI_ALT),
-       PINI(GMI_IORDY,   GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_WAIT,    GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_ADV_N,   GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_CLK,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_CS0_N,   GMI,     RSVD1,       NAND,      GMI,     DTV),
-       PINI(GMI_CS1_N,   GMI,     RSVD1,       NAND,      GMI,     DTV),
-       PINI(GMI_CS2_N,   GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_CS3_N,   GMI,     RSVD1,       NAND,      GMI,     GMI_ALT),
-       PINI(GMI_CS4_N,   GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_CS6_N,   GMI,     NAND,        NAND_ALT,  GMI,     SATA),
-       PINI(GMI_CS7_N,   GMI,     NAND,        NAND_ALT,  GMI,     GMI_ALT),
-       PINI(GMI_AD0,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD1,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD2,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD3,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD4,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD5,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD6,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD7,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD8,     GMI,     PWM0,        NAND,      GMI,     RSVD4),
-       PINI(GMI_AD9,     GMI,     PWM1,        NAND,      GMI,     RSVD4),
-       PINI(GMI_AD10,    GMI,     PWM2,        NAND,      GMI,     RSVD4),
-       PINI(GMI_AD11,    GMI,     PWM3,        NAND,      GMI,     RSVD4),
-       PINI(GMI_AD12,    GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD13,    GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD14,    GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_AD15,    GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_A16,     GMI,     UARTD,       SPI4,      GMI,     GMI_ALT),
-       PINI(GMI_A17,     GMI,     UARTD,       SPI4,      GMI,     DTV),
-       PINI(GMI_A18,     GMI,     UARTD,       SPI4,      GMI,     DTV),
-       PINI(GMI_A19,     GMI,     UARTD,       SPI4,      GMI,     RSVD4),
-       PINI(GMI_WR_N,    GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_OE_N,    GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_DQS,     GMI,     RSVD1,       NAND,      GMI,     RSVD4),
-       PINI(GMI_RST_N,   GMI,     NAND,        NAND_ALT,  GMI,     RSVD4),
-       PINI(GEN2_I2C_SCL, GMI,    I2C2,        HDCP,      GMI,     RSVD4),
-       PINI(GEN2_I2C_SDA, GMI,    I2C2,        HDCP,      GMI,     RSVD4),
-       PINI(SDMMC4_CLK,  SDMMC4,   RSVD1,      NAND,      GMI,     SDMMC4),
-       PINI(SDMMC4_CMD,  SDMMC4,   I2C3,       NAND,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT0, SDMMC4,   UARTE,      SPI3,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT1, SDMMC4,   UARTE,      SPI3,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT2, SDMMC4,   UARTE,      SPI3,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT3, SDMMC4,   UARTE,      SPI3,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT4, SDMMC4,   I2C3,       I2S4,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT5, SDMMC4,   VGP3,       I2S4,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT6, SDMMC4,   VGP4,       I2S4,      GMI,     SDMMC4),
-       PINI(SDMMC4_DAT7, SDMMC4,   VGP5,       I2S4,      GMI,     SDMMC4),
-       PINI(SDMMC4_RST_N, SDMMC4,  VGP6,       RSVD2,     RSVD3,   SDMMC4),
-       PINI(CAM_MCLK,    CAM,     VI,          RSVD2,     VI_ALT2, SDMMC4),
-       PINI(GPIO_PCC1,   CAM,     I2S4,        RSVD2,     RSVD3,   SDMMC4),
-       PINI(GPIO_PBB0,   CAM,     I2S4,        RSVD2,     RSVD3,   SDMMC4),
-       PINI(CAM_I2C_SCL, CAM,     VGP1,        I2C3,      RSVD3,   SDMMC4),
-       PINI(CAM_I2C_SDA, CAM,     VGP2,        I2C3,      RSVD3,   SDMMC4),
-       PINI(GPIO_PBB3,   CAM,     VGP3,        DISPA,     DISPB,   SDMMC4),
-       PINI(GPIO_PBB4,   CAM,     VGP4,        DISPA,     DISPB,   SDMMC4),
-       PINI(GPIO_PBB5,   CAM,     VGP5,        DISPA,     DISPB,   SDMMC4),
-       PINI(GPIO_PBB6,   CAM,     VGP6,        DISPA,     DISPB,   SDMMC4),
-       PINI(GPIO_PBB7,   CAM,     I2S4,        RSVD2,     RSVD3,   SDMMC4),
-       PINI(GPIO_PCC2,   CAM,     I2S4,        RSVD2,     RSVD3,   RSVD4),
-       PINI(JTAG_RTCK,   SYS,     RTCK,        RSVD2,     RSVD3,   RSVD4),
-       PINI(PWR_I2C_SCL, SYS,     I2CPWR,      RSVD2,     RSVD3,   RSVD4),
-       PINI(PWR_I2C_SDA, SYS,     I2CPWR,      RSVD2,     RSVD3,   RSVD4),
-       PINI(KB_ROW0,     SYS,     KBC,         NAND,      RSVD3,   RSVD4),
-       PINI(KB_ROW1,     SYS,     KBC,         NAND,      RSVD3,   RSVD4),
-       PINI(KB_ROW2,     SYS,     KBC,         NAND,      RSVD3,   RSVD4),
-       PINI(KB_ROW3,     SYS,     KBC,         NAND,      RSVD3,   RSVD4),
-       PINI(KB_ROW4,     SYS,     KBC,         NAND,      TRACE,   RSVD4),
-       PINI(KB_ROW5,     SYS,     KBC,         NAND,      TRACE,   OWR),
-       PINI(KB_ROW6,     SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW7,     SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW8,     SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW9,     SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW10,    SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW11,    SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW12,    SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW13,    SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW14,    SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_ROW15,    SYS,     KBC,         NAND,      SDMMC2,  MIO),
-       PINI(KB_COL0,     SYS,     KBC,         NAND,      TRACE,   TEST),
-       PINI(KB_COL1,     SYS,     KBC,         NAND,      TRACE,   TEST),
-       PINI(KB_COL2,     SYS,     KBC,         NAND,      TRACE,   RSVD4),
-       PINI(KB_COL3,     SYS,     KBC,         NAND,      TRACE,   RSVD4),
-       PINI(KB_COL4,     SYS,     KBC,         NAND,      TRACE,   RSVD4),
-       PINI(KB_COL5,     SYS,     KBC,         NAND,      TRACE,   RSVD4),
-       PINI(KB_COL6,     SYS,     KBC,         NAND,      TRACE,   MIO),
-       PINI(KB_COL7,     SYS,     KBC,         NAND,      TRACE,   MIO),
-       PINI(CLK_32K_OUT, SYS,     BLINK,       RSVD2,     RSVD3,   RSVD4),
-       PINI(SYS_CLK_REQ, SYS,     SYSCLK,      RSVD2,     RSVD3,   RSVD4),
-       PINI(CORE_PWR_REQ, SYS,    CORE_PWR_REQ, RSVD2,    RSVD3,   RSVD4),
-       PINI(CPU_PWR_REQ, SYS,     CPU_PWR_REQ, RSVD2,     RSVD3,   RSVD4),
-       PINI(PWR_INT_N,   SYS,     PWR_INT_N,   RSVD2,     RSVD3,   RSVD4),
-       PINI(CLK_32K_IN,  SYS,     CLK_32K_IN,  RSVD2,     RSVD3,   RSVD4),
-       PINI(OWR,         SYS,     OWR,         CEC,       RSVD3,   RSVD4),
-       PINI(DAP1_FS,     AUDIO,   I2S0,        HDA,       GMI,     SDMMC2),
-       PINI(DAP1_DIN,    AUDIO,   I2S0,        HDA,       GMI,     SDMMC2),
-       PINI(DAP1_DOUT,   AUDIO,   I2S0,        HDA,       GMI,     SDMMC2),
-       PINI(DAP1_SCLK,   AUDIO,   I2S0,        HDA,       GMI,     SDMMC2),
-       PINI(CLK1_REQ,    AUDIO,   DAP,         HDA,       RSVD3,   RSVD4),
-       PINI(CLK1_OUT,    AUDIO,   EXTPERIPH1,  RSVD2,     RSVD3,   RSVD4),
-       PINI(SPDIF_IN,    AUDIO,   SPDIF,       HDA,       I2C1,    SDMMC2),
-       PINI(SPDIF_OUT,   AUDIO,   SPDIF,       RSVD2,     I2C1,    SDMMC2),
-       PINI(DAP2_FS,     AUDIO,   I2S1,        HDA,       RSVD3,   GMI),
-       PINI(DAP2_DIN,    AUDIO,   I2S1,        HDA,       RSVD3,   GMI),
-       PINI(DAP2_DOUT,   AUDIO,   I2S1,        HDA,       RSVD3,   GMI),
-       PINI(DAP2_SCLK,   AUDIO,   I2S1,        HDA,       RSVD3,   GMI),
-       PINI(SPI2_MOSI,   AUDIO,   SPI6,        SPI2,      GMI,     GMI),
-       PINI(SPI2_MISO,   AUDIO,   SPI6,        SPI2,      GMI,     GMI),
-       PINI(SPI2_CS0_N,  AUDIO,   SPI6,        SPI2,      GMI,     GMI),
-       PINI(SPI2_SCK,    AUDIO,   SPI6,        SPI2,      GMI,     GMI),
-       PINI(SPI1_MOSI,   AUDIO,   SPI2,        SPI1,      SPI2_ALT, GMI),
-       PINI(SPI1_SCK,    AUDIO,   SPI2,        SPI1,      SPI2_ALT, GMI),
-       PINI(SPI1_CS0_N,  AUDIO,   SPI2,        SPI1,      SPI2_ALT, GMI),
-       PINI(SPI1_MISO,   AUDIO,   SPI3,        SPI1,      SPI2_ALT, RSVD4),
-       PINI(SPI2_CS1_N,  AUDIO,   SPI3,        SPI2,      SPI2_ALT, I2C1),
-       PINI(SPI2_CS2_N,  AUDIO,   SPI3,        SPI2,      SPI2_ALT, I2C1),
-       PINI(SDMMC3_CLK,  SDMMC3,  UARTA,       PWM2,      SDMMC3,  SPI3),
-       PINI(SDMMC3_CMD,  SDMMC3,  UARTA,       PWM3,      SDMMC3,  SPI2),
-       PINI(SDMMC3_DAT0, SDMMC3,  RSVD1,       RSVD2,     SDMMC3,  SPI3),
-       PINI(SDMMC3_DAT1, SDMMC3,  RSVD1,       RSVD2,     SDMMC3,  SPI3),
-       PINI(SDMMC3_DAT2, SDMMC3,  RSVD1,       PWM1,      SDMMC3,  SPI3),
-       PINI(SDMMC3_DAT3, SDMMC3,  RSVD1,       PWM0,      SDMMC3,  SPI3),
-       PINI(SDMMC3_DAT4, SDMMC3,  PWM1,        SPI4,      SDMMC3,  SPI2),
-       PINI(SDMMC3_DAT5, SDMMC3,  PWM0,        SPI4,      SDMMC3,  SPI2),
-       PINI(SDMMC3_DAT6, SDMMC3,  SPDIF,       SPI4,      SDMMC3,  SPI2),
-       PINI(SDMMC3_DAT7, SDMMC3,  SPDIF,       SPI4,      SDMMC3,  SPI2),
-       PINI(PEX_L0_PRSNT_N,    PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L0_RST_N,      PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L0_CLKREQ_N,   PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_WAKE_N,        PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L1_PRSNT_N,    PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L1_RST_N,      PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L1_CLKREQ_N,   PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L2_PRSNT_N,    PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L2_RST_N,      PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(PEX_L2_CLKREQ_N,   PEXCTL,   PCIE, HDA,       RSVD3,   RSVD4),
-       PINI(HDMI_CEC,          SYS,      CEC,  RSVD2,     RSVD3,   RSVD4),
+#define PIN_RESERVED {}
+
+static const struct pmux_pingrp_desc tegra30_pingroups[] = {
+       /*  pin,                  f0,           f1,       f2,       f3 */
+       /* Offset 0x3000 */
+       PIN(ULPI_DATA0_PO1,       SPI3,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_DATA1_PO2,       SPI3,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_DATA2_PO3,       SPI3,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_DATA3_PO4,       SPI3,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_DATA4_PO5,       SPI2,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_DATA5_PO6,       SPI2,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_DATA6_PO7,       SPI2,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_DATA7_PO0,       SPI2,         HSI,      UARTA,    ULPI),
+       PIN(ULPI_CLK_PY0,         SPI1,         RSVD2,    UARTD,    ULPI),
+       PIN(ULPI_DIR_PY1,         SPI1,         RSVD2,    UARTD,    ULPI),
+       PIN(ULPI_NXT_PY2,         SPI1,         RSVD2,    UARTD,    ULPI),
+       PIN(ULPI_STP_PY3,         SPI1,         RSVD2,    UARTD,    ULPI),
+       PIN(DAP3_FS_PP0,          I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+       PIN(DAP3_DIN_PP1,         I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+       PIN(DAP3_DOUT_PP2,        I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+       PIN(DAP3_SCLK_PP3,        I2S2,         RSVD2,    DISPLAYA, DISPLAYB),
+       PIN(PV0,                  RSVD1,        RSVD2,    RSVD3,    RSVD4),
+       PIN(PV1,                  RSVD1,        RSVD2,    RSVD3,    RSVD4),
+       PIN(SDMMC1_CLK_PZ0,       SDMMC1,       RSVD2,    RSVD3,    UARTA),
+       PIN(SDMMC1_CMD_PZ1,       SDMMC1,       RSVD2,    RSVD3,    UARTA),
+       PIN(SDMMC1_DAT3_PY4,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+       PIN(SDMMC1_DAT2_PY5,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+       PIN(SDMMC1_DAT1_PY6,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+       PIN(SDMMC1_DAT0_PY7,      SDMMC1,       RSVD2,    UARTE,    UARTA),
+       PIN(PV2,                  OWR,          RSVD2,    RSVD3,    RSVD4),
+       PIN(PV3,                  CLK_12M_OUT,  RSVD2,    RSVD3,    RSVD4),
+       PIN(CLK2_OUT_PW5,         EXTPERIPH2,   RSVD2,    RSVD3,    RSVD4),
+       PIN(CLK2_REQ_PCC5,        DAP,          RSVD2,    RSVD3,    RSVD4),
+       PIN(LCD_PWR1_PC1,         DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_PWR2_PC6,         DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+       PIN(LCD_SDIN_PZ2,         DISPLAYA,     DISPLAYB, SPI5,     RSVD4),
+       PIN(LCD_SDOUT_PN5,        DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+       PIN(LCD_WR_N_PZ3,         DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+       PIN(LCD_CS0_N_PN4,        DISPLAYA,     DISPLAYB, SPI5,     RSVD4),
+       PIN(LCD_DC0_PN6,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_SCK_PZ4,          DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+       PIN(LCD_PWR0_PB2,         DISPLAYA,     DISPLAYB, SPI5,     HDCP),
+       PIN(LCD_PCLK_PB3,         DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_DE_PJ1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_HSYNC_PJ3,        DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_VSYNC_PJ4,        DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D0_PE0,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D1_PE1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D2_PE2,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D3_PE3,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D4_PE4,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D5_PE5,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D6_PE6,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D7_PE7,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D8_PF0,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D9_PF1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D10_PF2,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D11_PF3,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D12_PF4,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D13_PF5,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D14_PF6,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D15_PF7,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D16_PM0,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D17_PM1,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D18_PM2,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D19_PM3,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D20_PM4,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D21_PM5,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D22_PM6,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_D23_PM7,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_CS1_N_PW0,        DISPLAYA,     DISPLAYB, SPI5,     RSVD4),
+       PIN(LCD_M1_PW1,           DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(LCD_DC1_PD2,          DISPLAYA,     DISPLAYB, RSVD3,    RSVD4),
+       PIN(HDMI_INT_PN7,         HDMI,         RSVD2,    RSVD3,    RSVD4),
+       PIN(DDC_SCL_PV4,          I2C4,         RSVD2,    RSVD3,    RSVD4),
+       PIN(DDC_SDA_PV5,          I2C4,         RSVD2,    RSVD3,    RSVD4),
+       PIN(CRT_HSYNC_PV6,        CRT,          RSVD2,    RSVD3,    RSVD4),
+       PIN(CRT_VSYNC_PV7,        CRT,          RSVD2,    RSVD3,    RSVD4),
+       PIN(VI_D0_PT4,            DDR,          RSVD2,    VI,       RSVD4),
+       PIN(VI_D1_PD5,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D2_PL0,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D3_PL1,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D4_PL2,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D5_PL3,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D6_PL4,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D7_PL5,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D8_PL6,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D9_PL7,            DDR,          SDMMC2,   VI,       RSVD4),
+       PIN(VI_D10_PT2,           DDR,          RSVD2,    VI,       RSVD4),
+       PIN(VI_D11_PT3,           DDR,          RSVD2,    VI,       RSVD4),
+       PIN(VI_PCLK_PT0,          RSVD1,        SDMMC2,   VI,       RSVD4),
+       PIN(VI_MCLK_PT1,          VI,           VI_ALT1,  VI_ALT2,  VI_ALT3),
+       PIN(VI_VSYNC_PD6,         DDR,          RSVD2,    VI,       RSVD4),
+       PIN(VI_HSYNC_PD7,         DDR,          RSVD2,    VI,       RSVD4),
+       PIN(UART2_RXD_PC3,        UARTB,        SPDIF,    UARTA,    SPI4),
+       PIN(UART2_TXD_PC2,        UARTB,        SPDIF,    UARTA,    SPI4),
+       PIN(UART2_RTS_N_PJ6,      UARTA,        UARTB,    GMI,      SPI4),
+       PIN(UART2_CTS_N_PJ5,      UARTA,        UARTB,    GMI,      SPI4),
+       PIN(UART3_TXD_PW6,        UARTC,        RSVD2,    GMI,      RSVD4),
+       PIN(UART3_RXD_PW7,        UARTC,        RSVD2,    GMI,      RSVD4),
+       PIN(UART3_CTS_N_PA1,      UARTC,        RSVD2,    GMI,      RSVD4),
+       PIN(UART3_RTS_N_PC0,      UARTC,        PWM0,     GMI,      RSVD4),
+       PIN(PU0,                  OWR,          UARTA,    GMI,      RSVD4),
+       PIN(PU1,                  RSVD1,        UARTA,    GMI,      RSVD4),
+       PIN(PU2,                  RSVD1,        UARTA,    GMI,      RSVD4),
+       PIN(PU3,                  PWM0,         UARTA,    GMI,      RSVD4),
+       PIN(PU4,                  PWM1,         UARTA,    GMI,      RSVD4),
+       PIN(PU5,                  PWM2,         UARTA,    GMI,      RSVD4),
+       PIN(PU6,                  PWM3,         UARTA,    GMI,      RSVD4),
+       PIN(GEN1_I2C_SDA_PC5,     I2C1,         RSVD2,    RSVD3,    RSVD4),
+       PIN(GEN1_I2C_SCL_PC4,     I2C1,         RSVD2,    RSVD3,    RSVD4),
+       PIN(DAP4_FS_PP4,          I2S3,         RSVD2,    GMI,      RSVD4),
+       PIN(DAP4_DIN_PP5,         I2S3,         RSVD2,    GMI,      RSVD4),
+       PIN(DAP4_DOUT_PP6,        I2S3,         RSVD2,    GMI,      RSVD4),
+       PIN(DAP4_SCLK_PP7,        I2S3,         RSVD2,    GMI,      RSVD4),
+       PIN(CLK3_OUT_PEE0,        EXTPERIPH3,   RSVD2,    RSVD3,    RSVD4),
+       PIN(CLK3_REQ_PEE1,        DEV3,         RSVD2,    RSVD3,    RSVD4),
+       PIN(GMI_WP_N_PC7,         RSVD1,        NAND,     GMI,      GMI_ALT),
+       PIN(GMI_IORDY_PI5,        RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_WAIT_PI7,         RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_ADV_N_PK0,        RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_CLK_PK1,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_CS0_N_PJ0,        RSVD1,        NAND,     GMI,      DTV),
+       PIN(GMI_CS1_N_PJ2,        RSVD1,        NAND,     GMI,      DTV),
+       PIN(GMI_CS2_N_PK3,        RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_CS3_N_PK4,        RSVD1,        NAND,     GMI,      GMI_ALT),
+       PIN(GMI_CS4_N_PK2,        RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_CS6_N_PI3,        NAND,         NAND_ALT, GMI,      SATA),
+       PIN(GMI_CS7_N_PI6,        NAND,         NAND_ALT, GMI,      GMI_ALT),
+       PIN(GMI_AD0_PG0,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD1_PG1,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD2_PG2,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD3_PG3,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD4_PG4,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD5_PG5,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD6_PG6,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD7_PG7,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD8_PH0,          PWM0,         NAND,     GMI,      RSVD4),
+       PIN(GMI_AD9_PH1,          PWM1,         NAND,     GMI,      RSVD4),
+       PIN(GMI_AD10_PH2,         PWM2,         NAND,     GMI,      RSVD4),
+       PIN(GMI_AD11_PH3,         PWM3,         NAND,     GMI,      RSVD4),
+       PIN(GMI_AD12_PH4,         RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD13_PH5,         RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD14_PH6,         RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_AD15_PH7,         RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_A16_PJ7,          UARTD,        SPI4,     GMI,      GMI_ALT),
+       PIN(GMI_A17_PB0,          UARTD,        SPI4,     GMI,      DTV),
+       PIN(GMI_A18_PB1,          UARTD,        SPI4,     GMI,      DTV),
+       PIN(GMI_A19_PK7,          UARTD,        SPI4,     GMI,      RSVD4),
+       PIN(GMI_WR_N_PI0,         RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_OE_N_PI1,         RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_DQS_PI2,          RSVD1,        NAND,     GMI,      RSVD4),
+       PIN(GMI_RST_N_PI4,        NAND,         NAND_ALT, GMI,      RSVD4),
+       PIN(GEN2_I2C_SCL_PT5,     I2C2,         HDCP,     GMI,      RSVD4),
+       PIN(GEN2_I2C_SDA_PT6,     I2C2,         HDCP,     GMI,      RSVD4),
+       PIN(SDMMC4_CLK_PCC4,      INVALID,      NAND,     GMI,      SDMMC4),
+       PIN(SDMMC4_CMD_PT7,       I2C3,         NAND,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT0_PAA0,     UARTE,        SPI3,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT1_PAA1,     UARTE,        SPI3,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT2_PAA2,     UARTE,        SPI3,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT3_PAA3,     UARTE,        SPI3,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT4_PAA4,     I2C3,         I2S4,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT5_PAA5,     VGP3,         I2S4,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT6_PAA6,     VGP4,         I2S4,     GMI,      SDMMC4),
+       PIN(SDMMC4_DAT7_PAA7,     VGP5,         I2S4,     GMI,      SDMMC4),
+       PIN(SDMMC4_RST_N_PCC3,    VGP6,         RSVD2,    RSVD3,    SDMMC4),
+       PIN(CAM_MCLK_PCC0,        VI,           VI_ALT1,  VI_ALT3,  SDMMC4),
+       PIN(PCC1,                 I2S4,         RSVD2,    RSVD3,    SDMMC4),
+       PIN(PBB0,                 I2S4,         RSVD2,    RSVD3,    SDMMC4),
+       PIN(CAM_I2C_SCL_PBB1,     VGP1,         I2C3,     RSVD3,    SDMMC4),
+       PIN(CAM_I2C_SDA_PBB2,     VGP2,         I2C3,     RSVD3,    SDMMC4),
+       PIN(PBB3,                 VGP3,         DISPLAYA, DISPLAYB, SDMMC4),
+       PIN(PBB4,                 VGP4,         DISPLAYA, DISPLAYB, SDMMC4),
+       PIN(PBB5,                 VGP5,         DISPLAYA, DISPLAYB, SDMMC4),
+       PIN(PBB6,                 VGP6,         DISPLAYA, DISPLAYB, SDMMC4),
+       PIN(PBB7,                 I2S4,         RSVD2,    RSVD3,    SDMMC4),
+       PIN(PCC2,                 I2S4,         RSVD2,    RSVD3,    RSVD4),
+       PIN(JTAG_RTCK_PU7,        RTCK,         RSVD2,    RSVD3,    RSVD4),
+       PIN(PWR_I2C_SCL_PZ6,      I2CPWR,       RSVD2,    RSVD3,    RSVD4),
+       PIN(PWR_I2C_SDA_PZ7,      I2CPWR,       RSVD2,    RSVD3,    RSVD4),
+       PIN(KB_ROW0_PR0,          KBC,          NAND,     RSVD3,    RSVD4),
+       PIN(KB_ROW1_PR1,          KBC,          NAND,     RSVD3,    RSVD4),
+       PIN(KB_ROW2_PR2,          KBC,          NAND,     RSVD3,    RSVD4),
+       PIN(KB_ROW3_PR3,          KBC,          NAND,     RSVD3,    INVALID),
+       PIN(KB_ROW4_PR4,          KBC,          NAND,     TRACE,    RSVD4),
+       PIN(KB_ROW5_PR5,          KBC,          NAND,     TRACE,    OWR),
+       PIN(KB_ROW6_PR6,          KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW7_PR7,          KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW8_PS0,          KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW9_PS1,          KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW10_PS2,         KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW11_PS3,         KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW12_PS4,         KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW13_PS5,         KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW14_PS6,         KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_ROW15_PS7,         KBC,          NAND,     SDMMC2,   MIO),
+       PIN(KB_COL0_PQ0,          KBC,          NAND,     TRACE,    TEST),
+       PIN(KB_COL1_PQ1,          KBC,          NAND,     TRACE,    TEST),
+       PIN(KB_COL2_PQ2,          KBC,          NAND,     TRACE,    RSVD4),
+       PIN(KB_COL3_PQ3,          KBC,          NAND,     TRACE,    RSVD4),
+       PIN(KB_COL4_PQ4,          KBC,          NAND,     TRACE,    RSVD4),
+       PIN(KB_COL5_PQ5,          KBC,          NAND,     TRACE,    RSVD4),
+       PIN(KB_COL6_PQ6,          KBC,          NAND,     TRACE,    MIO),
+       PIN(KB_COL7_PQ7,          KBC,          NAND,     TRACE,    MIO),
+       PIN(CLK_32K_OUT_PA0,      BLINK,        RSVD2,    RSVD3,    RSVD4),
+       PIN(SYS_CLK_REQ_PZ5,      SYSCLK,       RSVD2,    RSVD3,    RSVD4),
+       PIN(CORE_PWR_REQ,         CORE_PWR_REQ, RSVD2,    RSVD3,    RSVD4),
+       PIN(CPU_PWR_REQ,          CPU_PWR_REQ,  RSVD2,    RSVD3,    RSVD4),
+       PIN(PWR_INT_N,            PWR_INT_N,    RSVD2,    RSVD3,    RSVD4),
+       PIN(CLK_32K_IN,           CLK_32K_IN,   RSVD2,    RSVD3,    RSVD4),
+       PIN(OWR,                  OWR,          CEC,      RSVD3,    RSVD4),
+       PIN(DAP1_FS_PN0,          I2S0,         HDA,      GMI,      SDMMC2),
+       PIN(DAP1_DIN_PN1,         I2S0,         HDA,      GMI,      SDMMC2),
+       PIN(DAP1_DOUT_PN2,        I2S0,         HDA,      GMI,      SDMMC2),
+       PIN(DAP1_SCLK_PN3,        I2S0,         HDA,      GMI,      SDMMC2),
+       PIN(CLK1_REQ_PEE2,        DAP,          HDA,      RSVD3,    RSVD4),
+       PIN(CLK1_OUT_PW4,         EXTPERIPH1,   RSVD2,    RSVD3,    RSVD4),
+       PIN(SPDIF_IN_PK6,         SPDIF,        HDA,      I2C1,     SDMMC2),
+       PIN(SPDIF_OUT_PK5,        SPDIF,        RSVD2,    I2C1,     SDMMC2),
+       PIN(DAP2_FS_PA2,          I2S1,         HDA,      RSVD3,    GMI),
+       PIN(DAP2_DIN_PA4,         I2S1,         HDA,      RSVD3,    GMI),
+       PIN(DAP2_DOUT_PA5,        I2S1,         HDA,      RSVD3,    GMI),
+       PIN(DAP2_SCLK_PA3,        I2S1,         HDA,      RSVD3,    GMI),
+       PIN(SPI2_MOSI_PX0,        SPI6,         SPI2,     SPI3,     GMI),
+       PIN(SPI2_MISO_PX1,        SPI6,         SPI2,     SPI3,     GMI),
+       PIN(SPI2_CS0_N_PX3,       SPI6,         SPI2,     SPI3,     GMI),
+       PIN(SPI2_SCK_PX2,         SPI6,         SPI2,     SPI3,     GMI),
+       PIN(SPI1_MOSI_PX4,        SPI2,         SPI1,     SPI2_ALT, GMI),
+       PIN(SPI1_SCK_PX5,         SPI2,         SPI1,     SPI2_ALT, GMI),
+       PIN(SPI1_CS0_N_PX6,       SPI2,         SPI1,     SPI2_ALT, GMI),
+       PIN(SPI1_MISO_PX7,        SPI3,         SPI1,     SPI2_ALT, RSVD4),
+       PIN(SPI2_CS1_N_PW2,       SPI3,         SPI2,     SPI2_ALT, I2C1),
+       PIN(SPI2_CS2_N_PW3,       SPI3,         SPI2,     SPI2_ALT, I2C1),
+       PIN(SDMMC3_CLK_PA6,       UARTA,        PWM2,     SDMMC3,   SPI3),
+       PIN(SDMMC3_CMD_PA7,       UARTA,        PWM3,     SDMMC3,   SPI2),
+       PIN(SDMMC3_DAT0_PB7,      RSVD1,        RSVD2,    SDMMC3,   SPI3),
+       PIN(SDMMC3_DAT1_PB6,      RSVD1,        RSVD2,    SDMMC3,   SPI3),
+       PIN(SDMMC3_DAT2_PB5,      RSVD1,        PWM1,     SDMMC3,   SPI3),
+       PIN(SDMMC3_DAT3_PB4,      RSVD1,        PWM0,     SDMMC3,   SPI3),
+       PIN(SDMMC3_DAT4_PD1,      PWM1,         SPI4,     SDMMC3,   SPI2),
+       PIN(SDMMC3_DAT5_PD0,      PWM0,         SPI4,     SDMMC3,   SPI2),
+       PIN(SDMMC3_DAT6_PD3,      SPDIF,        SPI4,     SDMMC3,   SPI2),
+       PIN(SDMMC3_DAT7_PD4,      SPDIF,        SPI4,     SDMMC3,   SPI2),
+       PIN(PEX_L0_PRSNT_N_PDD0,  PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L0_RST_N_PDD1,    PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L0_CLKREQ_N_PDD2, PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_WAKE_N_PDD3,      PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L1_PRSNT_N_PDD4,  PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L1_RST_N_PDD5,    PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L1_CLKREQ_N_PDD6, PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L2_PRSNT_N_PDD7,  PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L2_RST_N_PCC6,    PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(PEX_L2_CLKREQ_N_PCC7, PCIE,         HDA,      RSVD3,    RSVD4),
+       PIN(HDMI_CEC_PEE3,        CEC,          RSVD2,    RSVD3,    RSVD4),
 };
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *tri = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin */
-       assert(pmux_pingrp_isvalid(pin));
-
-       reg = readl(tri);
-       if (enable)
-               reg |= PMUX_TRISTATE_MASK;
-       else
-               reg &= ~PMUX_TRISTATE_MASK;
-       writel(reg, tri);
-}
-
-void pinmux_tristate_enable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 1);
-}
-
-void pinmux_tristate_disable(enum pmux_pingrp pin)
-{
-       pinmux_set_tristate(pin, 0);
-}
-
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pull = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and pupd */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_pupd_isvalid(pupd));
-
-       reg = readl(pull);
-       reg &= ~(0x3 << PMUX_PULL_SHIFT);
-       reg |= (pupd << PMUX_PULL_SHIFT);
-       writel(reg, pull);
-}
-
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *muxctl = &pmt->pmt_ctl[pin];
-       int i, mux = -1;
-       u32 reg;
-
-       /* Error check on pin and func */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_func_isvalid(func));
-
-       /* Handle special values */
-       if (func == PMUX_FUNC_SAFE)
-               func = tegra_soc_pingroups[pin].func_safe;
-
-       if (func & PMUX_FUNC_RSVD1) {
-               mux = func & 0x3;
-       } else {
-               /* Search for the appropriate function */
-               for (i = 0; i < 4; i++) {
-                       if (tegra_soc_pingroups[pin].funcs[i] == func) {
-                               mux = i;
-                               break;
-                       }
-               }
-       }
-       assert(mux != -1);
-
-       reg = readl(muxctl);
-       reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
-       reg |= (mux << PMUX_MUXCTL_SHIFT);
-       writel(reg, muxctl);
-
-}
-
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_io = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and io */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_io_isvalid(io));
-
-       reg = readl(pin_io);
-       reg &= ~(0x1 << PMUX_IO_SHIFT);
-       reg |= (io & 0x1) << PMUX_IO_SHIFT;
-       writel(reg, pin_io);
-}
-
-static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_lock = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and lock */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_lock_isvalid(lock));
-
-       if (lock == PMUX_PIN_LOCK_DEFAULT)
-               return 0;
-
-       reg = readl(pin_lock);
-       reg &= ~(0x1 << PMUX_LOCK_SHIFT);
-       if (lock == PMUX_PIN_LOCK_ENABLE)
-               reg |= (0x1 << PMUX_LOCK_SHIFT);
-       else {
-               /* lock == DISABLE, which isn't possible */
-               printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
-                       __func__, lock);
-       }
-       writel(reg, pin_lock);
-
-       return 0;
-}
-
-static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_od = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and od */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_od_isvalid(od));
-
-       if (od == PMUX_PIN_OD_DEFAULT)
-               return 0;
-
-       reg = readl(pin_od);
-       reg &= ~(0x1 << PMUX_OD_SHIFT);
-       if (od == PMUX_PIN_OD_ENABLE)
-               reg |= (0x1 << PMUX_OD_SHIFT);
-       writel(reg, pin_od);
-
-       return 0;
-}
-
-static int pinmux_set_ioreset(enum pmux_pingrp pin,
-                               enum pmux_pin_ioreset ioreset)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pin_ioreset = &pmt->pmt_ctl[pin];
-       u32 reg;
-
-       /* Error check on pin and ioreset */
-       assert(pmux_pingrp_isvalid(pin));
-       assert(pmux_pin_ioreset_isvalid(ioreset));
-
-       if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
-               return 0;
-
-       reg = readl(pin_ioreset);
-       reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
-       if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
-               reg |= (0x1 << PMUX_IO_RESET_SHIFT);
-       writel(reg, pin_ioreset);
-
-       return 0;
-}
-
-void pinmux_config_pingroup(struct pingroup_config *config)
-{
-       enum pmux_pingrp pin = config->pingroup;
-
-       pinmux_set_func(pin, config->func);
-       pinmux_set_pullupdown(pin, config->pull);
-       pinmux_set_tristate(pin, config->tristate);
-       pinmux_set_io(pin, config->io);
-       pinmux_set_lock(pin, config->lock);
-       pinmux_set_od(pin, config->od);
-       pinmux_set_ioreset(pin, config->ioreset);
-}
-
-void pinmux_config_table(struct pingroup_config *config, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++)
-               pinmux_config_pingroup(&config[i]);
-}
-
-static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
-                               int slwf)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_slwf = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and slwf */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_slw_isvalid(slwf));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (slwf == PGRP_SLWF_NONE)
-               return 0;
-
-       reg = readl(pad_slwf);
-       reg &= ~PGRP_SLWF_MASK;
-       reg |= (slwf << PGRP_SLWF_SHIFT);
-       writel(reg, pad_slwf);
-
-       return 0;
-}
-
-static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_slwr = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and slwr */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_slw_isvalid(slwr));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (slwr == PGRP_SLWR_NONE)
-               return 0;
-
-       reg = readl(pad_slwr);
-       reg &= ~PGRP_SLWR_MASK;
-       reg |= (slwr << PGRP_SLWR_SHIFT);
-       writel(reg, pad_slwr);
-
-       return 0;
-}
-
-static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_drvup = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and drvup */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_drv_isvalid(drvup));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (drvup == PGRP_DRVUP_NONE)
-               return 0;
-
-       reg = readl(pad_drvup);
-       reg &= ~PGRP_DRVUP_MASK;
-       reg |= (drvup << PGRP_DRVUP_SHIFT);
-       writel(reg, pad_drvup);
-
-       return 0;
-}
-
-static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_drvdn = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check on pad and drvdn */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_drv_isvalid(drvdn));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (drvdn == PGRP_DRVDN_NONE)
-               return 0;
-
-       reg = readl(pad_drvdn);
-       reg &= ~PGRP_DRVDN_MASK;
-       reg |= (drvdn << PGRP_DRVDN_SHIFT);
-       writel(reg, pad_drvdn);
-
-       return 0;
-}
-
-static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_lpmd = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad and lpmd value */
-       assert(pmux_padgrp_isvalid(pad));
-       assert(pmux_pad_lpmd_isvalid(lpmd));
-
-       /* NONE means unspecified/do not change/use POR value */
-       if (lpmd == PGRP_LPMD_NONE)
-               return 0;
-
-       reg = readl(pad_lpmd);
-       reg &= ~PGRP_LPMD_MASK;
-       reg |= (lpmd << PGRP_LPMD_SHIFT);
-       writel(reg, pad_lpmd);
-
-       return 0;
-}
-
-static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_schmt = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad */
-       assert(pmux_padgrp_isvalid(pad));
-
-       reg = readl(pad_schmt);
-       reg &= ~(1 << PGRP_SCHMT_SHIFT);
-       if (schmt == PGRP_SCHMT_ENABLE)
-               reg |= (0x1 << PGRP_SCHMT_SHIFT);
-       writel(reg, pad_schmt);
-
-       return 0;
-}
-static int padgrp_set_hsm(enum pdrive_pingrp pad,
-                       enum pgrp_hsm hsm)
-{
-       struct pmux_tri_ctlr *pmt =
-                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       u32 *pad_hsm = &pmt->pmt_drive[pad];
-       u32 reg;
-
-       /* Error check pad */
-       assert(pmux_padgrp_isvalid(pad));
-
-       reg = readl(pad_hsm);
-       reg &= ~(1 << PGRP_HSM_SHIFT);
-       if (hsm == PGRP_HSM_ENABLE)
-               reg |= (0x1 << PGRP_HSM_SHIFT);
-       writel(reg, pad_hsm);
-
-       return 0;
-}
-
-void padctrl_config_pingroup(struct padctrl_config *config)
-{
-       enum pdrive_pingrp pad = config->padgrp;
-
-       padgrp_set_drvup_slwf(pad, config->slwf);
-       padgrp_set_drvdn_slwr(pad, config->slwr);
-       padgrp_set_drvup(pad, config->drvup);
-       padgrp_set_drvdn(pad, config->drvdn);
-       padgrp_set_lpmd(pad, config->lpmd);
-       padgrp_set_schmt(pad, config->schmt);
-       padgrp_set_hsm(pad, config->hsm);
-}
-
-void padgrp_config_table(struct padctrl_config *config, int len)
-{
-       int i;
-
-       for (i = 0; i < len; i++)
-               padctrl_config_pingroup(&config[i]);
-}
+const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;
index 2c3c773..5554615 100644 (file)
@@ -22,6 +22,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
        tegra30-cardhu.dtb \
        tegra30-tec-ng.dtb \
        tegra114-dalmore.dtb \
+       tegra124-jetson-tk1.dtb \
        tegra124-venice2.dtb
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
        zynq-zc706.dtb \
diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
new file mode 100644 (file)
index 0000000..52e8c0e
--- /dev/null
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+       model = "NVIDIA Jetson TK1";
+       compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
+
+       aliases {
+               i2c0 = "/i2c@7000d000";
+               i2c1 = "/i2c@7000c000";
+               i2c2 = "/i2c@7000c400";
+               i2c3 = "/i2c@7000c500";
+               i2c4 = "/i2c@7000c700";
+               i2c5 = "/i2c@7000d100";
+               sdhci0 = "/sdhci@700b0600";
+               sdhci1 = "/sdhci@700b0400";
+               spi0 = "/spi@7000d400";
+               spi1 = "/spi@7000da00";
+               usb0 = "/usb@7d008000";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x80000000>;
+       };
+
+       i2c@7000c000 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c400 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c500 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c700 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000d000 {
+               status = "okay";
+               clock-frequency = <400000>;
+       };
+
+       i2c@7000d100 {
+               status = "okay";
+               clock-frequency = <400000>;
+       };
+
+       spi@7000d400 {
+               status = "okay";
+               spi-max-frequency = <25000000>;
+       };
+
+       spi@7000da00 {
+               status = "okay";
+               spi-max-frequency = <25000000>;
+       };
+
+       sdhci@700b0400 {
+               status = "okay";
+               cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+               power-gpios = <&gpio 136 0>; /* gpio PR0 */
+               bus-width = <4>;
+       };
+
+       sdhci@700b0600 {
+               status = "okay";
+               bus-width = <8>;
+       };
+
+       usb@7d008000 {
+               status = "okay";
+               nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+       };
+};
similarity index 87%
rename from arch/arm/include/asm/arch-tegra20/apb_misc.h
rename to arch/arm/include/asm/arch-tegra/apb_misc.h
index f314f5a..a5bc092 100644 (file)
@@ -11,6 +11,8 @@
 struct apb_misc_pp_ctlr {
        u32     reserved0[2];
        u32     strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+       u32     reserved1[6];   /* 0x0c .. 0x20 */
+       u32     cfg_ctl;        /* 0x24 */
 };
 
 /* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
index 0e69864..ff77364 100644 (file)
@@ -24,6 +24,7 @@ void gpio_early_init(void);  /* overrideable GPIO config        */
  * an empty stub function will be called.
  */
 
+void pinmux_init(void);      /* overrideable general pinmux setup */
 void pin_mux_usb(void);      /* overrideable USB pinmux setup     */
 void pin_mux_spi(void);      /* overrideable SPI pinmux setup     */
 void pin_mux_nand(void);     /* overrideable NAND pinmux setup    */
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
new file mode 100644 (file)
index 0000000..035159d
--- /dev/null
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2010-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TEGRA_PINMUX_H_
+#define _TEGRA_PINMUX_H_
+
+#include <asm/arch/tegra.h>
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+       PMUX_PULL_NORMAL = 0,
+       PMUX_PULL_DOWN,
+       PMUX_PULL_UP,
+};
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+       PMUX_TRI_NORMAL = 0,
+       PMUX_TRI_TRISTATE = 1,
+};
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+enum pmux_pin_io {
+       PMUX_PIN_OUTPUT = 0,
+       PMUX_PIN_INPUT = 1,
+       PMUX_PIN_NONE,
+};
+
+enum pmux_pin_lock {
+       PMUX_PIN_LOCK_DEFAULT = 0,
+       PMUX_PIN_LOCK_DISABLE,
+       PMUX_PIN_LOCK_ENABLE,
+};
+
+enum pmux_pin_od {
+       PMUX_PIN_OD_DEFAULT = 0,
+       PMUX_PIN_OD_DISABLE,
+       PMUX_PIN_OD_ENABLE,
+};
+
+enum pmux_pin_ioreset {
+       PMUX_PIN_IO_RESET_DEFAULT = 0,
+       PMUX_PIN_IO_RESET_DISABLE,
+       PMUX_PIN_IO_RESET_ENABLE,
+};
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+enum pmux_pin_rcv_sel {
+       PMUX_PIN_RCV_SEL_DEFAULT = 0,
+       PMUX_PIN_RCV_SEL_NORMAL,
+       PMUX_PIN_RCV_SEL_HIGH,
+};
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pmux_pingrp_config {
+       u32 pingrp:16;          /* pin group PMUX_PINGRP_...        */
+       u32 func:8;             /* function to assign PMUX_FUNC_... */
+       u32 pull:2;             /* pull up/down/normal PMUX_PULL_...*/
+       u32 tristate:2;         /* tristate or normal PMUX_TRI_...  */
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+       u32 io:2;               /* input or output PMUX_PIN_...     */
+       u32 lock:2;             /* lock enable/disable PMUX_PIN...  */
+       u32 od:2;               /* open-drain or push-pull driver   */
+       u32 ioreset:2;          /* input/output reset PMUX_PIN...   */
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+       u32 rcv_sel:2;          /* select between High and Normal  */
+                               /* VIL/VIH receivers */
+#endif
+#endif
+};
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+#endif
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config       List of config items
+ * @param len          Number of config items in list
+ */
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+                               int len);
+
+#ifdef TEGRA_PMX_HAS_DRVGRPS
+
+#define PMUX_SLWF_MIN  0
+#define PMUX_SLWF_MAX  3
+#define PMUX_SLWF_NONE -1
+
+#define PMUX_SLWR_MIN  0
+#define PMUX_SLWR_MAX  3
+#define PMUX_SLWR_NONE -1
+
+#define PMUX_DRVUP_MIN 0
+#define PMUX_DRVUP_MAX 127
+#define PMUX_DRVUP_NONE        -1
+
+#define PMUX_DRVDN_MIN 0
+#define PMUX_DRVDN_MAX 127
+#define PMUX_DRVDN_NONE        -1
+
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+       PMUX_LPMD_X8 = 0,
+       PMUX_LPMD_X4,
+       PMUX_LPMD_X2,
+       PMUX_LPMD_X,
+       PMUX_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+       PMUX_SCHMT_DISABLE = 0,
+       PMUX_SCHMT_ENABLE = 1,
+       PMUX_SCHMT_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+       PMUX_HSM_DISABLE = 0,
+       PMUX_HSM_ENABLE = 1,
+       PMUX_HSM_NONE = -1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct pmux_drvgrp_config {
+       u32 drvgrp:16;  /* pin group PMUX_DRVGRP_x   */
+       u32 slwf:3;             /* falling edge slew         */
+       u32 slwr:3;             /* rising edge slew          */
+       u32 drvup:8;            /* pull-up drive strength    */
+       u32 drvdn:8;            /* pull-down drive strength  */
+       u32 lpmd:3;             /* low-power mode selection  */
+       u32 schmt:2;            /* schmidt enable            */
+       u32 hsm:2;              /* high-speed mode enable    */
+};
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config       List of config items
+ * @param len          Number of config items in list
+ */
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+                               int len);
+
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
+
+struct pmux_pingrp_desc {
+       u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+       u8 ctl_id;
+       u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
+#endif /* _TEGRA_PINMUX_H_ */
index a1efd07..ceb7bcd 100644 (file)
@@ -8,6 +8,189 @@
 #ifndef _TEGRA_USB_H_
 #define _TEGRA_USB_H_
 
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+       /* 0x000 */
+       uint id;
+       uint reserved0;
+       uint host;
+       uint device;
+
+       /* 0x010 */
+       uint txbuf;
+       uint rxbuf;
+       uint reserved1[2];
+
+       /* 0x020 */
+       uint reserved2[56];
+
+       /* 0x100 */
+       u16 cap_length;
+       u16 hci_version;
+       uint hcs_params;
+       uint hcc_params;
+       uint reserved3[5];
+
+       /* 0x120 */
+       uint dci_version;
+       uint dcc_params;
+       uint reserved4[2];
+
+#ifdef CONFIG_TEGRA20
+       /* 0x130 */
+       uint reserved4_2[4];
+
+       /* 0x140 */
+       uint usb_cmd;
+       uint usb_sts;
+       uint usb_intr;
+       uint frindex;
+
+       /* 0x150 */
+       uint reserved5;
+       uint periodic_list_base;
+       uint async_list_addr;
+       uint async_tt_sts;
+
+       /* 0x160 */
+       uint burst_size;
+       uint tx_fill_tuning;
+       uint reserved6;   /* is this port_sc1 on some controllers? */
+       uint icusb_ctrl;
+
+       /* 0x170 */
+       uint ulpi_viewport;
+       uint reserved7;
+       uint endpt_nak;
+       uint endpt_nak_enable;
+
+       /* 0x180 */
+       uint reserved;
+       uint port_sc1;
+       uint reserved8[6];
+
+       /* 0x1a0 */
+       uint reserved9;
+       uint otgsc;
+       uint usb_mode;
+       uint endpt_setup_stat;
+
+       /* 0x1b0 */
+       uint reserved10[20];
+
+       /* 0x200 */
+       uint reserved11[0x80];
+#else
+       /* 0x130 */
+       uint usb_cmd;
+       uint usb_sts;
+       uint usb_intr;
+       uint frindex;
+
+       /* 0x140 */
+       uint reserved5;
+       uint periodic_list_base;
+       uint async_list_addr;
+       uint reserved5_1;
+
+       /* 0x150 */
+       uint burst_size;
+       uint tx_fill_tuning;
+       uint reserved6;
+       uint icusb_ctrl;
+
+       /* 0x160 */
+       uint ulpi_viewport;
+       uint reserved7[3];
+
+       /* 0x170 */
+       uint reserved;
+       uint port_sc1;
+       uint reserved8[6];
+
+       /* 0x190 */
+       uint reserved9[8];
+
+       /* 0x1b0 */
+       uint reserved10;
+       uint hostpc1_devlc;
+       uint reserved10_1[2];
+
+       /* 0x1c0 */
+       uint reserved10_2[4];
+
+       /* 0x1d0 */
+       uint reserved10_3[4];
+
+       /* 0x1e0 */
+       uint reserved10_4[4];
+
+       /* 0x1f0 */
+       uint reserved10_5;
+       uint otgsc;
+       uint usb_mode;
+       uint reserved10_6;
+
+       /* 0x200 */
+       uint endpt_nak;
+       uint endpt_nak_enable;
+       uint endpt_setup_stat;
+       uint reserved11_1[0x7D];
+#endif
+
+       /* 0x400 */
+       uint susp_ctrl;
+       uint phy_vbus_sensors;
+       uint phy_vbus_wakeup_id;
+       uint phy_alt_vbus_sys;
+
+#ifdef CONFIG_TEGRA20
+       /* 0x410 */
+       uint usb1_legacy_ctrl;
+       uint reserved12[4];
+
+       /* 0x424 */
+       uint ulpi_timing_ctrl_0;
+       uint ulpi_timing_ctrl_1;
+       uint reserved13[53];
+#else
+
+       /* 0x410 */
+       uint usb1_legacy_ctrl;
+       uint reserved12[3];
+
+       /* 0x420 */
+       uint reserved13[56];
+#endif
+
+       /* 0x500 */
+       uint reserved14[64 * 3];
+
+       /* 0x800 */
+       uint utmip_pll_cfg0;
+       uint utmip_pll_cfg1;
+       uint utmip_xcvr_cfg0;
+       uint utmip_bias_cfg0;
+
+       /* 0x810 */
+       uint utmip_hsrx_cfg0;
+       uint utmip_hsrx_cfg1;
+       uint utmip_fslsrx_cfg0;
+       uint utmip_fslsrx_cfg1;
+
+       /* 0x820 */
+       uint utmip_tx_cfg0;
+       uint utmip_misc_cfg0;
+       uint utmip_misc_cfg1;
+       uint utmip_debounce_cfg0;
+
+       /* 0x830 */
+       uint utmip_bat_chrg_cfg0;
+       uint utmip_spare_cfg0;
+       uint utmip_xcvr_cfg1;
+       uint utmip_bias_cfg1;
+};
+
 /* USB1_LEGACY_CTRL */
 #define USB1_NO_LEGACY_MODE            1
 
 #define USB_PHY_CLK_VALID                      (1 << 7)
 #define USB_SUSP_CLR                           (1 << 5)
 
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
 /* USB2_IF_USB_SUSP_CTRL_0 */
 #define ULPI_PHY_ENB                           (1 << 13)
 
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP                 (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP                 (1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD                 (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)               (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD            (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)  (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD                  (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)                        (((x) & 0x7) << 25)
+#endif
+
 /* USBx_UTMIP_MISC_CFG0 */
 #define UTMIP_SUSPEND_EXIT_ON_EDGE             (1 << 22)
 
 /* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN                 (1 << 30)
+
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
 #define UTMIP_PLLU_STABLE_COUNT_SHIFT          6
 #define UTMIP_PLLU_STABLE_COUNT_MASK           \
                                (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT       18
 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK                \
                                (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
-#define UTMIP_PHY_XTAL_CLOCKEN                 (1 << 30)
 
 /* USBx_UTMIP_PLL_CFG1_0 */
+/* Tegra 3 and later: Moved to Clock and Reset register space */
 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT      27
 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK       \
                                (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
 #define IC_ENB1                                        (1 << 3)
 
-/* PORTSC1, USB1, defined for Tegra20 */
+#ifdef CONFIG_TEGRA20
+/* PORTSC1, USB1 */
 #define PTS1_SHIFT                             31
 #define PTS1_MASK                              (1 << PTS1_SHIFT)
 #define STS1                                   (1 << 30)
 
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT              30
+#define PTS_MASK               (3U << PTS_SHIFT)
+#define STS                    (1 << 29)
+#else
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT                              29
+#define PTS_MASK                               (0x7U << PTS_SHIFT)
+#define STS                                            (1 << 28)
+#endif
+
 #define PTS_UTMI       0
 #define PTS_RESERVED   1
 #define PTS_ULPI       2
index 9c22c08..c1cb3ef 100644 (file)
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
  */
 
 #ifndef _TEGRA114_PINMUX_H_
 #define _TEGRA114_PINMUX_H_
 
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- *     - function
- *     - pullup / pulldown
- *     - tristate or normal
- */
 enum pmux_pingrp {
-       PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
-       PINGRP_ULPI_DATA1,
-       PINGRP_ULPI_DATA2,
-       PINGRP_ULPI_DATA3,
-       PINGRP_ULPI_DATA4,
-       PINGRP_ULPI_DATA5,
-       PINGRP_ULPI_DATA6,
-       PINGRP_ULPI_DATA7,
-       PINGRP_ULPI_CLK,
-       PINGRP_ULPI_DIR,
-       PINGRP_ULPI_NXT,
-       PINGRP_ULPI_STP,
-       PINGRP_DAP3_FS,
-       PINGRP_DAP3_DIN,
-       PINGRP_DAP3_DOUT,
-       PINGRP_DAP3_SCLK,
-       PINGRP_GPIO_PV0,
-       PINGRP_GPIO_PV1,
-       PINGRP_SDMMC1_CLK,
-       PINGRP_SDMMC1_CMD,
-       PINGRP_SDMMC1_DAT3,
-       PINGRP_SDMMC1_DAT2,
-       PINGRP_SDMMC1_DAT1,
-       PINGRP_SDMMC1_DAT0,
-       PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
-       PINGRP_CLK2_REQ,
-       PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
-       PINGRP_DDC_SCL,
-       PINGRP_DDC_SDA,
-       PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
-       PINGRP_UART2_TXD,
-       PINGRP_UART2_RTS_N,
-       PINGRP_UART2_CTS_N,
-       PINGRP_UART3_TXD,
-       PINGRP_UART3_RXD,
-       PINGRP_UART3_CTS_N,
-       PINGRP_UART3_RTS_N,
-       PINGRP_GPIO_PU0,
-       PINGRP_GPIO_PU1,
-       PINGRP_GPIO_PU2,
-       PINGRP_GPIO_PU3,
-       PINGRP_GPIO_PU4,
-       PINGRP_GPIO_PU5,
-       PINGRP_GPIO_PU6,
-       PINGRP_GEN1_I2C_SDA,
-       PINGRP_GEN1_I2C_SCL,
-       PINGRP_DAP4_FS,
-       PINGRP_DAP4_DIN,
-       PINGRP_DAP4_DOUT,
-       PINGRP_DAP4_SCLK,
-       PINGRP_CLK3_OUT,
-       PINGRP_CLK3_REQ,
-       PINGRP_GMI_WP_N,
-       PINGRP_GMI_IORDY,
-       PINGRP_GMI_WAIT,
-       PINGRP_GMI_ADV_N,
-       PINGRP_GMI_CLK,
-       PINGRP_GMI_CS0_N,
-       PINGRP_GMI_CS1_N,
-       PINGRP_GMI_CS2_N,
-       PINGRP_GMI_CS3_N,
-       PINGRP_GMI_CS4_N,
-       PINGRP_GMI_CS6_N,
-       PINGRP_GMI_CS7_N,
-       PINGRP_GMI_AD0,
-       PINGRP_GMI_AD1,
-       PINGRP_GMI_AD2,
-       PINGRP_GMI_AD3,
-       PINGRP_GMI_AD4,
-       PINGRP_GMI_AD5,
-       PINGRP_GMI_AD6,
-       PINGRP_GMI_AD7,
-       PINGRP_GMI_AD8,
-       PINGRP_GMI_AD9,
-       PINGRP_GMI_AD10,
-       PINGRP_GMI_AD11,
-       PINGRP_GMI_AD12,
-       PINGRP_GMI_AD13,
-       PINGRP_GMI_AD14,
-       PINGRP_GMI_AD15,
-       PINGRP_GMI_A16,
-       PINGRP_GMI_A17,
-       PINGRP_GMI_A18,
-       PINGRP_GMI_A19,
-       PINGRP_GMI_WR_N,
-       PINGRP_GMI_OE_N,
-       PINGRP_GMI_DQS,
-       PINGRP_GMI_RST_N,
-       PINGRP_GEN2_I2C_SCL,
-       PINGRP_GEN2_I2C_SDA,
-       PINGRP_SDMMC4_CLK,
-       PINGRP_SDMMC4_CMD,
-       PINGRP_SDMMC4_DAT0,
-       PINGRP_SDMMC4_DAT1,
-       PINGRP_SDMMC4_DAT2,
-       PINGRP_SDMMC4_DAT3,
-       PINGRP_SDMMC4_DAT4,
-       PINGRP_SDMMC4_DAT5,
-       PINGRP_SDMMC4_DAT6,
-       PINGRP_SDMMC4_DAT7,
-       PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
-       PINGRP_GPIO_PCC1,
-       PINGRP_GPIO_PBB0,
-       PINGRP_CAM_I2C_SCL,
-       PINGRP_CAM_I2C_SDA,
-       PINGRP_GPIO_PBB3,
-       PINGRP_GPIO_PBB4,
-       PINGRP_GPIO_PBB5,
-       PINGRP_GPIO_PBB6,
-       PINGRP_GPIO_PBB7,
-       PINGRP_GPIO_PCC2,
-       PINGRP_JTAG_RTCK,
-       PINGRP_PWR_I2C_SCL,
-       PINGRP_PWR_I2C_SDA,
-       PINGRP_KB_ROW0,
-       PINGRP_KB_ROW1,
-       PINGRP_KB_ROW2,
-       PINGRP_KB_ROW3,
-       PINGRP_KB_ROW4,
-       PINGRP_KB_ROW5,
-       PINGRP_KB_ROW6,
-       PINGRP_KB_ROW7,
-       PINGRP_KB_ROW8,
-       PINGRP_KB_ROW9,
-       PINGRP_KB_ROW10,
-       PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
-       PINGRP_KB_COL1,
-       PINGRP_KB_COL2,
-       PINGRP_KB_COL3,
-       PINGRP_KB_COL4,
-       PINGRP_KB_COL5,
-       PINGRP_KB_COL6,
-       PINGRP_KB_COL7,
-       PINGRP_CLK_32K_OUT,
-       PINGRP_SYS_CLK_REQ,
-       PINGRP_CORE_PWR_REQ,
-       PINGRP_CPU_PWR_REQ,
-       PINGRP_PWR_INT_N,
-       PINGRP_CLK_32K_IN,
-       PINGRP_OWR,
-       PINGRP_DAP1_FS,
-       PINGRP_DAP1_DIN,
-       PINGRP_DAP1_DOUT,
-       PINGRP_DAP1_SCLK,
-       PINGRP_CLK1_REQ,
-       PINGRP_CLK1_OUT,
-       PINGRP_SPDIF_IN,
-       PINGRP_SPDIF_OUT,
-       PINGRP_DAP2_FS,
-       PINGRP_DAP2_DIN,
-       PINGRP_DAP2_DOUT,
-       PINGRP_DAP2_SCLK,
-       PINGRP_DVFS_PWM,
-       PINGRP_GPIO_X1_AUD,
-       PINGRP_GPIO_X3_AUD,
-       PINGRP_DVFS_CLK,
-       PINGRP_GPIO_X4_AUD,
-       PINGRP_GPIO_X5_AUD,
-       PINGRP_GPIO_X6_AUD,
-       PINGRP_GPIO_X7_AUD,
-       PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
-       PINGRP_SDMMC3_CMD,
-       PINGRP_SDMMC3_DAT0,
-       PINGRP_SDMMC3_DAT1,
-       PINGRP_SDMMC3_DAT2,
-       PINGRP_SDMMC3_DAT3,
-       PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
-       PINGRP_SDMMC1_WP_N,
-       PINGRP_SDMMC3_CD_N,
-       PINGRP_GPIO_W2_AUD,
-       PINGRP_GPIO_W3_AUD,
-       PINGRP_USB_VBUS_EN0,    /* offset 0x33f4 */
-       PINGRP_USB_VBUS_EN1,
-       PINGRP_SDMMC3_CLK_LB_IN,
-       PINGRP_SDMMC3_CLK_LB_OUT,
-       PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
-       PINGRP_COUNT,
+       PMUX_PINGRP_ULPI_DATA0_PO1,
+       PMUX_PINGRP_ULPI_DATA1_PO2,
+       PMUX_PINGRP_ULPI_DATA2_PO3,
+       PMUX_PINGRP_ULPI_DATA3_PO4,
+       PMUX_PINGRP_ULPI_DATA4_PO5,
+       PMUX_PINGRP_ULPI_DATA5_PO6,
+       PMUX_PINGRP_ULPI_DATA6_PO7,
+       PMUX_PINGRP_ULPI_DATA7_PO0,
+       PMUX_PINGRP_ULPI_CLK_PY0,
+       PMUX_PINGRP_ULPI_DIR_PY1,
+       PMUX_PINGRP_ULPI_NXT_PY2,
+       PMUX_PINGRP_ULPI_STP_PY3,
+       PMUX_PINGRP_DAP3_FS_PP0,
+       PMUX_PINGRP_DAP3_DIN_PP1,
+       PMUX_PINGRP_DAP3_DOUT_PP2,
+       PMUX_PINGRP_DAP3_SCLK_PP3,
+       PMUX_PINGRP_PV0,
+       PMUX_PINGRP_PV1,
+       PMUX_PINGRP_SDMMC1_CLK_PZ0,
+       PMUX_PINGRP_SDMMC1_CMD_PZ1,
+       PMUX_PINGRP_SDMMC1_DAT3_PY4,
+       PMUX_PINGRP_SDMMC1_DAT2_PY5,
+       PMUX_PINGRP_SDMMC1_DAT1_PY6,
+       PMUX_PINGRP_SDMMC1_DAT0_PY7,
+       PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+       PMUX_PINGRP_CLK2_REQ_PCC5,
+       PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+       PMUX_PINGRP_DDC_SCL_PV4,
+       PMUX_PINGRP_DDC_SDA_PV5,
+       PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+       PMUX_PINGRP_UART2_TXD_PC2,
+       PMUX_PINGRP_UART2_RTS_N_PJ6,
+       PMUX_PINGRP_UART2_CTS_N_PJ5,
+       PMUX_PINGRP_UART3_TXD_PW6,
+       PMUX_PINGRP_UART3_RXD_PW7,
+       PMUX_PINGRP_UART3_CTS_N_PA1,
+       PMUX_PINGRP_UART3_RTS_N_PC0,
+       PMUX_PINGRP_PU0,
+       PMUX_PINGRP_PU1,
+       PMUX_PINGRP_PU2,
+       PMUX_PINGRP_PU3,
+       PMUX_PINGRP_PU4,
+       PMUX_PINGRP_PU5,
+       PMUX_PINGRP_PU6,
+       PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+       PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+       PMUX_PINGRP_DAP4_FS_PP4,
+       PMUX_PINGRP_DAP4_DIN_PP5,
+       PMUX_PINGRP_DAP4_DOUT_PP6,
+       PMUX_PINGRP_DAP4_SCLK_PP7,
+       PMUX_PINGRP_CLK3_OUT_PEE0,
+       PMUX_PINGRP_CLK3_REQ_PEE1,
+       PMUX_PINGRP_GMI_WP_N_PC7,
+       PMUX_PINGRP_GMI_IORDY_PI5,
+       PMUX_PINGRP_GMI_WAIT_PI7,
+       PMUX_PINGRP_GMI_ADV_N_PK0,
+       PMUX_PINGRP_GMI_CLK_PK1,
+       PMUX_PINGRP_GMI_CS0_N_PJ0,
+       PMUX_PINGRP_GMI_CS1_N_PJ2,
+       PMUX_PINGRP_GMI_CS2_N_PK3,
+       PMUX_PINGRP_GMI_CS3_N_PK4,
+       PMUX_PINGRP_GMI_CS4_N_PK2,
+       PMUX_PINGRP_GMI_CS6_N_PI3,
+       PMUX_PINGRP_GMI_CS7_N_PI6,
+       PMUX_PINGRP_GMI_AD0_PG0,
+       PMUX_PINGRP_GMI_AD1_PG1,
+       PMUX_PINGRP_GMI_AD2_PG2,
+       PMUX_PINGRP_GMI_AD3_PG3,
+       PMUX_PINGRP_GMI_AD4_PG4,
+       PMUX_PINGRP_GMI_AD5_PG5,
+       PMUX_PINGRP_GMI_AD6_PG6,
+       PMUX_PINGRP_GMI_AD7_PG7,
+       PMUX_PINGRP_GMI_AD8_PH0,
+       PMUX_PINGRP_GMI_AD9_PH1,
+       PMUX_PINGRP_GMI_AD10_PH2,
+       PMUX_PINGRP_GMI_AD11_PH3,
+       PMUX_PINGRP_GMI_AD12_PH4,
+       PMUX_PINGRP_GMI_AD13_PH5,
+       PMUX_PINGRP_GMI_AD14_PH6,
+       PMUX_PINGRP_GMI_AD15_PH7,
+       PMUX_PINGRP_GMI_A16_PJ7,
+       PMUX_PINGRP_GMI_A17_PB0,
+       PMUX_PINGRP_GMI_A18_PB1,
+       PMUX_PINGRP_GMI_A19_PK7,
+       PMUX_PINGRP_GMI_WR_N_PI0,
+       PMUX_PINGRP_GMI_OE_N_PI1,
+       PMUX_PINGRP_GMI_DQS_P_PJ3,
+       PMUX_PINGRP_GMI_RST_N_PI4,
+       PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+       PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+       PMUX_PINGRP_SDMMC4_CLK_PCC4,
+       PMUX_PINGRP_SDMMC4_CMD_PT7,
+       PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+       PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+       PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+       PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+       PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+       PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+       PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+       PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+       PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+       PMUX_PINGRP_PCC1,
+       PMUX_PINGRP_PBB0,
+       PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+       PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+       PMUX_PINGRP_PBB3,
+       PMUX_PINGRP_PBB4,
+       PMUX_PINGRP_PBB5,
+       PMUX_PINGRP_PBB6,
+       PMUX_PINGRP_PBB7,
+       PMUX_PINGRP_PCC2,
+       PMUX_PINGRP_JTAG_RTCK,
+       PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+       PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+       PMUX_PINGRP_KB_ROW0_PR0,
+       PMUX_PINGRP_KB_ROW1_PR1,
+       PMUX_PINGRP_KB_ROW2_PR2,
+       PMUX_PINGRP_KB_ROW3_PR3,
+       PMUX_PINGRP_KB_ROW4_PR4,
+       PMUX_PINGRP_KB_ROW5_PR5,
+       PMUX_PINGRP_KB_ROW6_PR6,
+       PMUX_PINGRP_KB_ROW7_PR7,
+       PMUX_PINGRP_KB_ROW8_PS0,
+       PMUX_PINGRP_KB_ROW9_PS1,
+       PMUX_PINGRP_KB_ROW10_PS2,
+       PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
+       PMUX_PINGRP_KB_COL1_PQ1,
+       PMUX_PINGRP_KB_COL2_PQ2,
+       PMUX_PINGRP_KB_COL3_PQ3,
+       PMUX_PINGRP_KB_COL4_PQ4,
+       PMUX_PINGRP_KB_COL5_PQ5,
+       PMUX_PINGRP_KB_COL6_PQ6,
+       PMUX_PINGRP_KB_COL7_PQ7,
+       PMUX_PINGRP_CLK_32K_OUT_PA0,
+       PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+       PMUX_PINGRP_CORE_PWR_REQ,
+       PMUX_PINGRP_CPU_PWR_REQ,
+       PMUX_PINGRP_PWR_INT_N,
+       PMUX_PINGRP_CLK_32K_IN,
+       PMUX_PINGRP_OWR,
+       PMUX_PINGRP_DAP1_FS_PN0,
+       PMUX_PINGRP_DAP1_DIN_PN1,
+       PMUX_PINGRP_DAP1_DOUT_PN2,
+       PMUX_PINGRP_DAP1_SCLK_PN3,
+       PMUX_PINGRP_CLK1_REQ_PEE2,
+       PMUX_PINGRP_CLK1_OUT_PW4,
+       PMUX_PINGRP_SPDIF_IN_PK6,
+       PMUX_PINGRP_SPDIF_OUT_PK5,
+       PMUX_PINGRP_DAP2_FS_PA2,
+       PMUX_PINGRP_DAP2_DIN_PA4,
+       PMUX_PINGRP_DAP2_DOUT_PA5,
+       PMUX_PINGRP_DAP2_SCLK_PA3,
+       PMUX_PINGRP_DVFS_PWM_PX0,
+       PMUX_PINGRP_GPIO_X1_AUD_PX1,
+       PMUX_PINGRP_GPIO_X3_AUD_PX3,
+       PMUX_PINGRP_DVFS_CLK_PX2,
+       PMUX_PINGRP_GPIO_X4_AUD_PX4,
+       PMUX_PINGRP_GPIO_X5_AUD_PX5,
+       PMUX_PINGRP_GPIO_X6_AUD_PX6,
+       PMUX_PINGRP_GPIO_X7_AUD_PX7,
+       PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+       PMUX_PINGRP_SDMMC3_CMD_PA7,
+       PMUX_PINGRP_SDMMC3_DAT0_PB7,
+       PMUX_PINGRP_SDMMC3_DAT1_PB6,
+       PMUX_PINGRP_SDMMC3_DAT2_PB5,
+       PMUX_PINGRP_SDMMC3_DAT3_PB4,
+       PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+       PMUX_PINGRP_SDMMC1_WP_N_PV3,
+       PMUX_PINGRP_SDMMC3_CD_N_PV2,
+       PMUX_PINGRP_GPIO_W2_AUD_PW2,
+       PMUX_PINGRP_GPIO_W3_AUD_PW3,
+       PMUX_PINGRP_USB_VBUS_EN0_PN4,
+       PMUX_PINGRP_USB_VBUS_EN1_PN5,
+       PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+       PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+       PMUX_PINGRP_GMI_CLK_LB,
+       PMUX_PINGRP_RESET_OUT_N,
+       PMUX_PINGRP_COUNT,
 };
 
-enum pdrive_pingrp {
-       PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
-       PDRIVE_PINGROUP_AO2,
-       PDRIVE_PINGROUP_AT1,
-       PDRIVE_PINGROUP_AT2,
-       PDRIVE_PINGROUP_AT3,
-       PDRIVE_PINGROUP_AT4,
-       PDRIVE_PINGROUP_AT5,
-       PDRIVE_PINGROUP_CDEV1,
-       PDRIVE_PINGROUP_CDEV2,
-       PDRIVE_PINGROUP_DAP1 = 10,      /* offset 0x890 */
-       PDRIVE_PINGROUP_DAP2,
-       PDRIVE_PINGROUP_DAP3,
-       PDRIVE_PINGROUP_DAP4,
-       PDRIVE_PINGROUP_DBG,
-       PDRIVE_PINGROUP_SDIO3 = 18,     /* offset 0x8B0 */
-       PDRIVE_PINGROUP_SPI,
-       PDRIVE_PINGROUP_UAA,
-       PDRIVE_PINGROUP_UAB,
-       PDRIVE_PINGROUP_UART2,
-       PDRIVE_PINGROUP_UART3,
-       PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
-       PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
-       PDRIVE_PINGROUP_GMA,
-       PDRIVE_PINGROUP_GME = 42,       /* offset 0x910 */
-       PDRIVE_PINGROUP_GMF,
-       PDRIVE_PINGROUP_GMG,
-       PDRIVE_PINGROUP_GMH,
-       PDRIVE_PINGROUP_OWR,
-       PDRIVE_PINGROUP_UAD,
-       PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
-       PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
-       PDRIVE_PINGROUP_AT6 = 75,       /* offset 0x994 */
-       PDRIVE_PINGROUP_DAP5,
-       PDRIVE_PINGROUP_VBUS,
-       PDRIVE_PINGROUP_AO3,
-       PDRIVE_PINGROUP_HVC,
-       PDRIVE_PINGROUP_SDIO4,
-       PDRIVE_PINGROUP_AO0,
-       PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+       PMUX_DRVGRP_AO1,
+       PMUX_DRVGRP_AO2,
+       PMUX_DRVGRP_AT1,
+       PMUX_DRVGRP_AT2,
+       PMUX_DRVGRP_AT3,
+       PMUX_DRVGRP_AT4,
+       PMUX_DRVGRP_AT5,
+       PMUX_DRVGRP_CDEV1,
+       PMUX_DRVGRP_CDEV2,
+       PMUX_DRVGRP_DAP1 = (0x28 / 4),
+       PMUX_DRVGRP_DAP2,
+       PMUX_DRVGRP_DAP3,
+       PMUX_DRVGRP_DAP4,
+       PMUX_DRVGRP_DBG,
+       PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+       PMUX_DRVGRP_SPI,
+       PMUX_DRVGRP_UAA,
+       PMUX_DRVGRP_UAB,
+       PMUX_DRVGRP_UART2,
+       PMUX_DRVGRP_UART3,
+       PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+       PMUX_DRVGRP_DDC = (0x94 / 4),
+       PMUX_DRVGRP_GMA,
+       PMUX_DRVGRP_GME = (0xa8 / 4),
+       PMUX_DRVGRP_GMF,
+       PMUX_DRVGRP_GMG,
+       PMUX_DRVGRP_GMH,
+       PMUX_DRVGRP_OWR,
+       PMUX_DRVGRP_UDA,
+       PMUX_DRVGRP_DEV3 = (0xc4 / 4),
+       PMUX_DRVGRP_CEC = (0xd0 / 4),
+       PMUX_DRVGRP_AT6 = (0x12c / 4),
+       PMUX_DRVGRP_DAP5,
+       PMUX_DRVGRP_USB_VBUS_EN,
+       PMUX_DRVGRP_AO3,
+       PMUX_DRVGRP_HV0,
+       PMUX_DRVGRP_SDIO4,
+       PMUX_DRVGRP_AO0,
+       PMUX_DRVGRP_COUNT,
 };
 
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
 enum pmux_func {
-       PMUX_FUNC_AHB_CLK,
-       PMUX_FUNC_APB_CLK,
-       PMUX_FUNC_AUDIO_SYNC,
-       PMUX_FUNC_CRT,
-       PMUX_FUNC_DAP1,
-       PMUX_FUNC_DAP2,
-       PMUX_FUNC_DAP3,
-       PMUX_FUNC_DAP4,
-       PMUX_FUNC_DAP5,
-       PMUX_FUNC_DISPA,
-       PMUX_FUNC_DISPB,
-       PMUX_FUNC_EMC_TEST0_DLL,
-       PMUX_FUNC_EMC_TEST1_DLL,
-       PMUX_FUNC_GMI,
-       PMUX_FUNC_GMI_INT,
-       PMUX_FUNC_HDMI,
-       PMUX_FUNC_I2C1,
-       PMUX_FUNC_I2C2,
-       PMUX_FUNC_I2C3,
-       PMUX_FUNC_IDE,
-       PMUX_FUNC_KBC,
-       PMUX_FUNC_MIO,
-       PMUX_FUNC_MIPI_HS,
-       PMUX_FUNC_NAND,
-       PMUX_FUNC_OSC,
-       PMUX_FUNC_OWR,
-       PMUX_FUNC_PCIE,
-       PMUX_FUNC_PLLA_OUT,
-       PMUX_FUNC_PLLC_OUT1,
-       PMUX_FUNC_PLLM_OUT1,
-       PMUX_FUNC_PLLP_OUT2,
-       PMUX_FUNC_PLLP_OUT3,
-       PMUX_FUNC_PLLP_OUT4,
-       PMUX_FUNC_PWM,
-       PMUX_FUNC_PWR_INTR,
-       PMUX_FUNC_PWR_ON,
-       PMUX_FUNC_RTCK,
-       PMUX_FUNC_SDMMC1,
-       PMUX_FUNC_SDMMC2,
-       PMUX_FUNC_SDMMC3,
-       PMUX_FUNC_SDMMC4,
-       PMUX_FUNC_SFLASH,
-       PMUX_FUNC_SPDIF,
-       PMUX_FUNC_SPI1,
-       PMUX_FUNC_SPI2,
-       PMUX_FUNC_SPI2_ALT,
-       PMUX_FUNC_SPI3,
-       PMUX_FUNC_SPI4,
-       PMUX_FUNC_TRACE,
-       PMUX_FUNC_TWC,
-       PMUX_FUNC_UARTA,
-       PMUX_FUNC_UARTB,
-       PMUX_FUNC_UARTC,
-       PMUX_FUNC_UARTD,
-       PMUX_FUNC_UARTE,
-       PMUX_FUNC_ULPI,
-       PMUX_FUNC_VI,
-       PMUX_FUNC_VI_SENSOR_CLK,
-       PMUX_FUNC_XIO,
-       /* End of Tegra2 MUX selectors */
        PMUX_FUNC_BLINK,
        PMUX_FUNC_CEC,
+       PMUX_FUNC_CLDVFS,
+       PMUX_FUNC_CLK,
        PMUX_FUNC_CLK12,
+       PMUX_FUNC_CPU,
        PMUX_FUNC_DAP,
-       PMUX_FUNC_DAPSDMMC2,
-       PMUX_FUNC_DDR,
+       PMUX_FUNC_DAP1,
+       PMUX_FUNC_DAP2,
        PMUX_FUNC_DEV3,
+       PMUX_FUNC_DISPLAYA,
+       PMUX_FUNC_DISPLAYA_ALT,
+       PMUX_FUNC_DISPLAYB,
        PMUX_FUNC_DTV,
-       PMUX_FUNC_VI_ALT1,
-       PMUX_FUNC_VI_ALT2,
-       PMUX_FUNC_VI_ALT3,
        PMUX_FUNC_EMC_DLL,
        PMUX_FUNC_EXTPERIPH1,
        PMUX_FUNC_EXTPERIPH2,
        PMUX_FUNC_EXTPERIPH3,
+       PMUX_FUNC_GMI,
        PMUX_FUNC_GMI_ALT,
        PMUX_FUNC_HDA,
        PMUX_FUNC_HSI,
+       PMUX_FUNC_I2C1,
+       PMUX_FUNC_I2C2,
+       PMUX_FUNC_I2C3,
        PMUX_FUNC_I2C4,
-       PMUX_FUNC_I2C5,
        PMUX_FUNC_I2CPWR,
        PMUX_FUNC_I2S0,
        PMUX_FUNC_I2S1,
        PMUX_FUNC_I2S2,
        PMUX_FUNC_I2S3,
        PMUX_FUNC_I2S4,
+       PMUX_FUNC_IRDA,
+       PMUX_FUNC_KBC,
+       PMUX_FUNC_NAND,
        PMUX_FUNC_NAND_ALT,
-       PMUX_FUNC_POPSDIO4,
-       PMUX_FUNC_POPSDMMC4,
+       PMUX_FUNC_OWR,
+       PMUX_FUNC_PMI,
        PMUX_FUNC_PWM0,
        PMUX_FUNC_PWM1,
        PMUX_FUNC_PWM2,
        PMUX_FUNC_PWM3,
-       PMUX_FUNC_SATA,
+       PMUX_FUNC_PWRON,
+       PMUX_FUNC_RESET_OUT_N,
+       PMUX_FUNC_RTCK,
+       PMUX_FUNC_SDMMC1,
+       PMUX_FUNC_SDMMC2,
+       PMUX_FUNC_SDMMC3,
+       PMUX_FUNC_SDMMC4,
+       PMUX_FUNC_SOC,
+       PMUX_FUNC_SPDIF,
+       PMUX_FUNC_SPI1,
+       PMUX_FUNC_SPI2,
+       PMUX_FUNC_SPI3,
+       PMUX_FUNC_SPI4,
        PMUX_FUNC_SPI5,
        PMUX_FUNC_SPI6,
        PMUX_FUNC_SYSCLK,
+       PMUX_FUNC_TRACE,
+       PMUX_FUNC_UARTA,
+       PMUX_FUNC_UARTB,
+       PMUX_FUNC_UARTC,
+       PMUX_FUNC_UARTD,
+       PMUX_FUNC_ULPI,
+       PMUX_FUNC_USB,
        PMUX_FUNC_VGP1,
        PMUX_FUNC_VGP2,
        PMUX_FUNC_VGP3,
        PMUX_FUNC_VGP4,
        PMUX_FUNC_VGP5,
        PMUX_FUNC_VGP6,
-       /* End of Tegra3 MUX selectors */
-       PMUX_FUNC_USB,
-       PMUX_FUNC_SOC,
-       PMUX_FUNC_CPU,
-       PMUX_FUNC_CLK,
-       PMUX_FUNC_PWRON,
-       PMUX_FUNC_PMI,
-       PMUX_FUNC_CLDVFS,
-       PMUX_FUNC_RESET_OUT_N,
-       /* End of Tegra114 MUX selectors */
-
-       PMUX_FUNC_SAFE,
-       PMUX_FUNC_MAX,
-
-       PMUX_FUNC_INVALID = 0x4000,
-       PMUX_FUNC_RSVD1 = 0x8000,
-       PMUX_FUNC_RSVD2 = 0x8001,
-       PMUX_FUNC_RSVD3 = 0x8002,
-       PMUX_FUNC_RSVD4 = 0x8003,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
-       || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
-       PMUX_PULL_NORMAL = 0,
-       PMUX_PULL_DOWN,
-       PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
-                               ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
-       PMUX_TRI_NORMAL = 0,
-       PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
-                               && ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
-       PMUX_PIN_OUTPUT = 0,
-       PMUX_PIN_INPUT = 1,
-       PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
-                               ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
-       PMUX_PIN_LOCK_DEFAULT = 0,
-       PMUX_PIN_LOCK_DISABLE,
-       PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
-                               ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
-       PMUX_PIN_OD_DEFAULT = 0,
-       PMUX_PIN_OD_DISABLE,
-       PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
-                               ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
-       PMUX_PIN_IO_RESET_DEFAULT = 0,
-       PMUX_PIN_IO_RESET_DISABLE,
-       PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
-                               (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
-                               ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
-       PMUX_PIN_RCV_SEL_DEFAULT = 0,
-       PMUX_PIN_RCV_SEL_NORMAL,
-       PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
-                               (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
-                               ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
-       PMUX_VDDIO_BB = 0,
-       PMUX_VDDIO_LCD,
-       PMUX_VDDIO_VI,
-       PMUX_VDDIO_UART,
-       PMUX_VDDIO_DDR,
-       PMUX_VDDIO_NAND,
-       PMUX_VDDIO_SYS,
-       PMUX_VDDIO_AUDIO,
-       PMUX_VDDIO_SD,
-       PMUX_VDDIO_CAM,
-       PMUX_VDDIO_GMI,
-       PMUX_VDDIO_PEXCTL,
-       PMUX_VDDIO_SDMMC1,
-       PMUX_VDDIO_SDMMC3,
-       PMUX_VDDIO_SDMMC4,
-
-       PMUX_VDDIO_NONE
-};
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX  3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX  PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE        -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE        PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE        -1
-#define PGRP_HSM_NONE  PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
-                               (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
-                               (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
-                               (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
-       PGRP_LPMD_X8 = 0,
-       PGRP_LPMD_X4,
-       PGRP_LPMD_X2,
-       PGRP_LPMD_X,
-       PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
-       PGRP_SCHMT_DISABLE = 0,
-       PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
-       PGRP_HSM_DISABLE = 0,
-       PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
-       enum pdrive_pingrp padgrp;      /* pin group PDRIVE_PINGRP_x */
-       int slwf;                       /* falling edge slew         */
-       int slwr;                       /* rising edge slew          */
-       int drvup;                      /* pull-up drive strength    */
-       int drvdn;                      /* pull-down drive strength  */
-       enum pgrp_lpmd lpmd;            /* low-power mode selection  */
-       enum pgrp_schmt schmt;          /* schmidt enable            */
-       enum pgrp_hsm hsm;              /* high-speed mode enable    */
-};
-
-/* t114 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET    ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
-                               PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
-       uint pmt_reserved0;             /* ABP_MISC_PP_ reserved offset 00 */
-       uint pmt_reserved1;             /* ABP_MISC_PP_ reserved offset 04 */
-       uint pmt_strap_opt_a;           /* _STRAPPING_OPT_A_0, offset 08   */
-       uint pmt_reserved2;             /* ABP_MISC_PP_ reserved offset 0C */
-       uint pmt_reserved3;             /* ABP_MISC_PP_ reserved offset 10 */
-       uint pmt_reserved4[4];          /* _TRI_STATE_REG_A/B/C/D in t20 */
-       uint pmt_cfg_ctl;               /* _CONFIG_CTL_0, offset 24        */
-
-       uint pmt_reserved[528];         /* ABP_MISC_PP_ reserved offs 28-864 */
-
-       uint pmt_drive[PDRIVE_PINGROUP_COUNT];  /* pin drive grps offs 868 */
-       uint pmt_reserved5[PMUX_OFFSET];
-       uint pmt_ctl[PINGRP_COUNT];     /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
-       enum pmux_pingrp pingroup;      /* pin group PINGRP_...             */
-       enum pmux_func func;            /* function to assign FUNC_...      */
-       enum pmux_pull pull;            /* pull up/down/normal PMUX_PULL_...*/
-       enum pmux_tristate tristate;    /* tristate or normal PMUX_TRI_...  */
-       enum pmux_pin_io io;            /* input or output PMUX_PIN_...  */
-       enum pmux_pin_lock lock;        /* lock enable/disable PMUX_PIN...  */
-       enum pmux_pin_od od;            /* open-drain or push-pull driver  */
-       enum pmux_pin_ioreset ioreset;  /* input/output reset PMUX_PIN...  */
-       enum pmux_pin_rcv_sel rcv_sel;  /* select between High and Normal  */
-                                       /* VIL/VIH receivers */
+       PMUX_FUNC_VI,
+       PMUX_FUNC_VI_ALT1,
+       PMUX_FUNC_VI_ALT3,
+       PMUX_FUNC_RSVD1,
+       PMUX_FUNC_RSVD2,
+       PMUX_FUNC_RSVD3,
+       PMUX_FUNC_RSVD4,
+       PMUX_FUNC_COUNT,
 };
 
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config       List of config items
- * @param len          Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
-/**
- * Set the GP pad configs
- *
- * @param config       List of config items
- * @param len          Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
 
-#endif /* _TEGRA114_PINMUX_H_ */
+#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/usb.h b/arch/arm/include/asm/arch-tegra114/usb.h
deleted file mode 100644 (file)
index d46048c..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA114_USB_H_
-#define _TEGRA114_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
-       /* 0x000 */
-       uint id;
-       uint reserved0;
-       uint host;
-       uint device;
-
-       /* 0x010 */
-       uint txbuf;
-       uint rxbuf;
-       uint reserved1[2];
-
-       /* 0x020 */
-       uint reserved2[56];
-
-       /* 0x100 */
-       u16 cap_length;
-       u16 hci_version;
-       uint hcs_params;
-       uint hcc_params;
-       uint reserved3[5];
-
-       /* 0x120 */
-       uint dci_version;
-       uint dcc_params;
-       uint reserved4[2];
-
-       /* 0x130 */
-       uint usb_cmd;
-       uint usb_sts;
-       uint usb_intr;
-       uint frindex;
-
-       /* 0x140 */
-       uint reserved5;
-       uint periodic_list_base;
-       uint async_list_addr;
-       uint reserved5_1;
-
-       /* 0x150 */
-       uint burst_size;
-       uint tx_fill_tuning;
-       uint reserved6;
-       uint icusb_ctrl;
-
-       /* 0x160 */
-       uint ulpi_viewport;
-       uint reserved7[3];
-
-       /* 0x170 */
-       uint reserved;
-       uint port_sc1;
-       uint reserved8[6];
-
-       /* 0x190 */
-       uint reserved9[8];
-
-       /* 0x1b0 */
-       uint reserved10;
-       uint hostpc1_devlc;
-       uint reserved10_1[2];
-
-       /* 0x1c0 */
-       uint reserved10_2[4];
-
-       /* 0x1d0 */
-       uint reserved10_3[4];
-
-       /* 0x1e0 */
-       uint reserved10_4[4];
-
-       /* 0x1f0 */
-       uint reserved10_5;
-       uint otgsc;
-       uint usb_mode;
-       uint reserved10_6;
-
-       /* 0x200 */
-       uint endpt_nak;
-       uint endpt_nak_enable;
-       uint endpt_setup_stat;
-       uint reserved11_1[0x7D];
-
-       /* 0x400 */
-       uint susp_ctrl;
-       uint phy_vbus_sensors;
-       uint phy_vbus_wakeup_id;
-       uint phy_alt_vbus_sys;
-
-       /* 0x410 */
-       uint usb1_legacy_ctrl;
-       uint reserved12[3];
-
-       /* 0x420 */
-       uint reserved13[56];
-
-       /* 0x500 */
-       uint reserved14[64 * 3];
-
-       /* 0x800 */
-       uint utmip_pll_cfg0;
-       uint utmip_pll_cfg1;
-       uint utmip_xcvr_cfg0;
-       uint utmip_bias_cfg0;
-
-       /* 0x810 */
-       uint utmip_hsrx_cfg0;
-       uint utmip_hsrx_cfg1;
-       uint utmip_fslsrx_cfg0;
-       uint utmip_fslsrx_cfg1;
-
-       /* 0x820 */
-       uint utmip_tx_cfg0;
-       uint utmip_misc_cfg0;
-       uint utmip_misc_cfg1;
-       uint utmip_debounce_cfg0;
-
-       /* 0x830 */
-       uint utmip_bat_chrg_cfg0;
-       uint utmip_spare_cfg0;
-       uint utmip_xcvr_cfg1;
-       uint utmip_bias_cfg1;
-};
-
-/* USB2D_HOSTPC1_DEVLC_0 */
-#define PTS_SHIFT                              29
-#define PTS_MASK                               (0x7U << PTS_SHIFT)
-
-#define STS                                    (1 << 28)
-#endif /* _TEGRA114_USB_H_ */
index 9662e2b..c49801c 100644 (file)
 /*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
  *
- * SPDX-License-Identifier:     GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
  */
 
 #ifndef _TEGRA124_PINMUX_H_
 #define _TEGRA124_PINMUX_H_
 
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- *     - function
- *     - pullup / pulldown
- *     - tristate or normal
- */
 enum pmux_pingrp {
-       PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
-       PINGRP_ULPI_DATA1,
-       PINGRP_ULPI_DATA2,
-       PINGRP_ULPI_DATA3,
-       PINGRP_ULPI_DATA4,
-       PINGRP_ULPI_DATA5,
-       PINGRP_ULPI_DATA6,
-       PINGRP_ULPI_DATA7,
-       PINGRP_ULPI_CLK,
-       PINGRP_ULPI_DIR,
-       PINGRP_ULPI_NXT,
-       PINGRP_ULPI_STP,
-       PINGRP_DAP3_FS,
-       PINGRP_DAP3_DIN,
-       PINGRP_DAP3_DOUT,
-       PINGRP_DAP3_SCLK,
-       PINGRP_GPIO_PV0,
-       PINGRP_GPIO_PV1,
-       PINGRP_SDMMC1_CLK,
-       PINGRP_SDMMC1_CMD,
-       PINGRP_SDMMC1_DAT3,
-       PINGRP_SDMMC1_DAT2,
-       PINGRP_SDMMC1_DAT1,
-       PINGRP_SDMMC1_DAT0,
-       PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
-       PINGRP_CLK2_REQ,
-       PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
-       PINGRP_DDC_SCL,
-       PINGRP_DDC_SDA,
-       PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
-       PINGRP_UART2_TXD,
-       PINGRP_UART2_RTS_N,
-       PINGRP_UART2_CTS_N,
-       PINGRP_UART3_TXD,
-       PINGRP_UART3_RXD,
-       PINGRP_UART3_CTS_N,
-       PINGRP_UART3_RTS_N,
-       PINGRP_GPIO_PU0,
-       PINGRP_GPIO_PU1,
-       PINGRP_GPIO_PU2,
-       PINGRP_GPIO_PU3,
-       PINGRP_GPIO_PU4,
-       PINGRP_GPIO_PU5,
-       PINGRP_GPIO_PU6,
-       PINGRP_GEN1_I2C_SDA,
-       PINGRP_GEN1_I2C_SCL,
-       PINGRP_DAP4_FS,
-       PINGRP_DAP4_DIN,
-       PINGRP_DAP4_DOUT,
-       PINGRP_DAP4_SCLK,
-       PINGRP_CLK3_OUT,
-       PINGRP_CLK3_REQ,
-       /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
-       PINGRP_GPIO_PC7,                        /* offset 0x31c0 */
-       PINGRP_GPIO_PI5,
-       PINGRP_GPIO_PI7,
-       PINGRP_GPIO_PK0,
-       PINGRP_GPIO_PK1,
-       PINGRP_GPIO_PJ0,
-       PINGRP_GPIO_PJ2,
-       PINGRP_GPIO_PK3,
-       PINGRP_GPIO_PK4,
-       PINGRP_GPIO_PK2,
-       PINGRP_GPIO_PI3,
-       PINGRP_GPIO_PI6,
-       PINGRP_GPIO_PG0,
-       PINGRP_GPIO_PG1,
-       PINGRP_GPIO_PG2,
-       PINGRP_GPIO_PG3,
-       PINGRP_GPIO_PG4,
-       PINGRP_GPIO_PG5,
-       PINGRP_GPIO_PG6,
-       PINGRP_GPIO_PG7,
-       PINGRP_GPIO_PH0,
-       PINGRP_GPIO_PH1,
-       PINGRP_GPIO_PH2,
-       PINGRP_GPIO_PH3,
-       PINGRP_GPIO_PH4,
-       PINGRP_GPIO_PH5,
-       PINGRP_GPIO_PH6,
-       PINGRP_GPIO_PH7,
-       PINGRP_GPIO_PJ7,
-       PINGRP_GPIO_PB0,
-       PINGRP_GPIO_PB1,
-       PINGRP_GPIO_PK7,
-       PINGRP_GPIO_PI0,
-       PINGRP_GPIO_PI1,
-       PINGRP_GPIO_PI2,
-       PINGRP_GPIO_PI4,                        /* offset 0x324c */
-       PINGRP_GEN2_I2C_SCL,
-       PINGRP_GEN2_I2C_SDA,
-       PINGRP_SDMMC4_CLK,
-       PINGRP_SDMMC4_CMD,
-       PINGRP_SDMMC4_DAT0,
-       PINGRP_SDMMC4_DAT1,
-       PINGRP_SDMMC4_DAT2,
-       PINGRP_SDMMC4_DAT3,
-       PINGRP_SDMMC4_DAT4,
-       PINGRP_SDMMC4_DAT5,
-       PINGRP_SDMMC4_DAT6,
-       PINGRP_SDMMC4_DAT7,
-       PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
-       PINGRP_GPIO_PCC1,
-       PINGRP_GPIO_PBB0,
-       PINGRP_CAM_I2C_SCL,
-       PINGRP_CAM_I2C_SDA,
-       PINGRP_GPIO_PBB3,
-       PINGRP_GPIO_PBB4,
-       PINGRP_GPIO_PBB5,
-       PINGRP_GPIO_PBB6,
-       PINGRP_GPIO_PBB7,
-       PINGRP_GPIO_PCC2,
-       PINGRP_JTAG_RTCK,
-       PINGRP_PWR_I2C_SCL,
-       PINGRP_PWR_I2C_SDA,
-       PINGRP_KB_ROW0,
-       PINGRP_KB_ROW1,
-       PINGRP_KB_ROW2,
-       PINGRP_KB_ROW3,
-       PINGRP_KB_ROW4,
-       PINGRP_KB_ROW5,
-       PINGRP_KB_ROW6,
-       PINGRP_KB_ROW7,
-       PINGRP_KB_ROW8,
-       PINGRP_KB_ROW9,
-       PINGRP_KB_ROW10,
-       PINGRP_KB_ROW11,
-       PINGRP_KB_ROW12,
-       PINGRP_KB_ROW13,
-       PINGRP_KB_ROW14,
-       PINGRP_KB_ROW15,
-       PINGRP_KB_COL0,                         /* offset 0x32fc */
-       PINGRP_KB_COL1,
-       PINGRP_KB_COL2,
-       PINGRP_KB_COL3,
-       PINGRP_KB_COL4,
-       PINGRP_KB_COL5,
-       PINGRP_KB_COL6,
-       PINGRP_KB_COL7,
-       PINGRP_CLK_32K_OUT,
-       PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2,   /* offset 0x3324 */
-       PINGRP_CPU_PWR_REQ,
-       PINGRP_PWR_INT_N,
-       PINGRP_CLK_32K_IN,
-       PINGRP_OWR,
-       PINGRP_DAP1_FS,
-       PINGRP_DAP1_DIN,
-       PINGRP_DAP1_DOUT,
-       PINGRP_DAP1_SCLK,
-       PINGRP_CLK1_REQ,
-       PINGRP_CLK1_OUT,
-       PINGRP_SPDIF_IN,
-       PINGRP_SPDIF_OUT,
-       PINGRP_DAP2_FS,
-       PINGRP_DAP2_DIN,
-       PINGRP_DAP2_DOUT,
-       PINGRP_DAP2_SCLK,
-       PINGRP_DVFS_PWM,
-       PINGRP_GPIO_X1_AUD,
-       PINGRP_GPIO_X3_AUD,
-       PINGRP_DVFS_CLK,
-       PINGRP_GPIO_X4_AUD,
-       PINGRP_GPIO_X5_AUD,
-       PINGRP_GPIO_X6_AUD,
-       PINGRP_GPIO_X7_AUD,
-       PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
-       PINGRP_SDMMC3_CMD,
-       PINGRP_SDMMC3_DAT0,
-       PINGRP_SDMMC3_DAT1,
-       PINGRP_SDMMC3_DAT2,
-       PINGRP_SDMMC3_DAT3,
-       PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
-       PINGRP_PEX_L0_CLKREQ,
-       PINGRP_PEX_WAKE,
-       PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
-       PINGRP_PEX_L1_CLKREQ,
-       PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
-       PINGRP_SDMMC1_WP_N,
-       PINGRP_SDMMC3_CD_N,
-       PINGRP_GPIO_W2_AUD,
-       PINGRP_GPIO_W3_AUD,
-       PINGRP_USB_VBUS_EN0,
-       PINGRP_USB_VBUS_EN1,
-       PINGRP_SDMMC3_CLK_LB_IN,
-       PINGRP_SDMMC3_CLK_LB_OUT,
-       PINGRP_GMI_CLK_LB,
-       PINGRP_RESET_OUT_N,
-       PINGRP_KB_ROW16,                        /* offset 0x340c */
-       PINGRP_KB_ROW17,
-       PINGRP_USB_VBUS_EN2,
-       PINGRP_GPIO_PFF2,
-       PINGRP_DP_HPD,                          /* last reg offset = 0x3430 */
-       PINGRP_COUNT,
+       PMUX_PINGRP_ULPI_DATA0_PO1,
+       PMUX_PINGRP_ULPI_DATA1_PO2,
+       PMUX_PINGRP_ULPI_DATA2_PO3,
+       PMUX_PINGRP_ULPI_DATA3_PO4,
+       PMUX_PINGRP_ULPI_DATA4_PO5,
+       PMUX_PINGRP_ULPI_DATA5_PO6,
+       PMUX_PINGRP_ULPI_DATA6_PO7,
+       PMUX_PINGRP_ULPI_DATA7_PO0,
+       PMUX_PINGRP_ULPI_CLK_PY0,
+       PMUX_PINGRP_ULPI_DIR_PY1,
+       PMUX_PINGRP_ULPI_NXT_PY2,
+       PMUX_PINGRP_ULPI_STP_PY3,
+       PMUX_PINGRP_DAP3_FS_PP0,
+       PMUX_PINGRP_DAP3_DIN_PP1,
+       PMUX_PINGRP_DAP3_DOUT_PP2,
+       PMUX_PINGRP_DAP3_SCLK_PP3,
+       PMUX_PINGRP_PV0,
+       PMUX_PINGRP_PV1,
+       PMUX_PINGRP_SDMMC1_CLK_PZ0,
+       PMUX_PINGRP_SDMMC1_CMD_PZ1,
+       PMUX_PINGRP_SDMMC1_DAT3_PY4,
+       PMUX_PINGRP_SDMMC1_DAT2_PY5,
+       PMUX_PINGRP_SDMMC1_DAT1_PY6,
+       PMUX_PINGRP_SDMMC1_DAT0_PY7,
+       PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+       PMUX_PINGRP_CLK2_REQ_PCC5,
+       PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+       PMUX_PINGRP_DDC_SCL_PV4,
+       PMUX_PINGRP_DDC_SDA_PV5,
+       PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+       PMUX_PINGRP_UART2_TXD_PC2,
+       PMUX_PINGRP_UART2_RTS_N_PJ6,
+       PMUX_PINGRP_UART2_CTS_N_PJ5,
+       PMUX_PINGRP_UART3_TXD_PW6,
+       PMUX_PINGRP_UART3_RXD_PW7,
+       PMUX_PINGRP_UART3_CTS_N_PA1,
+       PMUX_PINGRP_UART3_RTS_N_PC0,
+       PMUX_PINGRP_PU0,
+       PMUX_PINGRP_PU1,
+       PMUX_PINGRP_PU2,
+       PMUX_PINGRP_PU3,
+       PMUX_PINGRP_PU4,
+       PMUX_PINGRP_PU5,
+       PMUX_PINGRP_PU6,
+       PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+       PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+       PMUX_PINGRP_DAP4_FS_PP4,
+       PMUX_PINGRP_DAP4_DIN_PP5,
+       PMUX_PINGRP_DAP4_DOUT_PP6,
+       PMUX_PINGRP_DAP4_SCLK_PP7,
+       PMUX_PINGRP_CLK3_OUT_PEE0,
+       PMUX_PINGRP_CLK3_REQ_PEE1,
+       PMUX_PINGRP_PC7,
+       PMUX_PINGRP_PI5,
+       PMUX_PINGRP_PI7,
+       PMUX_PINGRP_PK0,
+       PMUX_PINGRP_PK1,
+       PMUX_PINGRP_PJ0,
+       PMUX_PINGRP_PJ2,
+       PMUX_PINGRP_PK3,
+       PMUX_PINGRP_PK4,
+       PMUX_PINGRP_PK2,
+       PMUX_PINGRP_PI3,
+       PMUX_PINGRP_PI6,
+       PMUX_PINGRP_PG0,
+       PMUX_PINGRP_PG1,
+       PMUX_PINGRP_PG2,
+       PMUX_PINGRP_PG3,
+       PMUX_PINGRP_PG4,
+       PMUX_PINGRP_PG5,
+       PMUX_PINGRP_PG6,
+       PMUX_PINGRP_PG7,
+       PMUX_PINGRP_PH0,
+       PMUX_PINGRP_PH1,
+       PMUX_PINGRP_PH2,
+       PMUX_PINGRP_PH3,
+       PMUX_PINGRP_PH4,
+       PMUX_PINGRP_PH5,
+       PMUX_PINGRP_PH6,
+       PMUX_PINGRP_PH7,
+       PMUX_PINGRP_PJ7,
+       PMUX_PINGRP_PB0,
+       PMUX_PINGRP_PB1,
+       PMUX_PINGRP_PK7,
+       PMUX_PINGRP_PI0,
+       PMUX_PINGRP_PI1,
+       PMUX_PINGRP_PI2,
+       PMUX_PINGRP_PI4,
+       PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+       PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+       PMUX_PINGRP_SDMMC4_CLK_PCC4,
+       PMUX_PINGRP_SDMMC4_CMD_PT7,
+       PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+       PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+       PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+       PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+       PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+       PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+       PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+       PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+       PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+       PMUX_PINGRP_PCC1,
+       PMUX_PINGRP_PBB0,
+       PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+       PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+       PMUX_PINGRP_PBB3,
+       PMUX_PINGRP_PBB4,
+       PMUX_PINGRP_PBB5,
+       PMUX_PINGRP_PBB6,
+       PMUX_PINGRP_PBB7,
+       PMUX_PINGRP_PCC2,
+       PMUX_PINGRP_JTAG_RTCK,
+       PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+       PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+       PMUX_PINGRP_KB_ROW0_PR0,
+       PMUX_PINGRP_KB_ROW1_PR1,
+       PMUX_PINGRP_KB_ROW2_PR2,
+       PMUX_PINGRP_KB_ROW3_PR3,
+       PMUX_PINGRP_KB_ROW4_PR4,
+       PMUX_PINGRP_KB_ROW5_PR5,
+       PMUX_PINGRP_KB_ROW6_PR6,
+       PMUX_PINGRP_KB_ROW7_PR7,
+       PMUX_PINGRP_KB_ROW8_PS0,
+       PMUX_PINGRP_KB_ROW9_PS1,
+       PMUX_PINGRP_KB_ROW10_PS2,
+       PMUX_PINGRP_KB_ROW11_PS3,
+       PMUX_PINGRP_KB_ROW12_PS4,
+       PMUX_PINGRP_KB_ROW13_PS5,
+       PMUX_PINGRP_KB_ROW14_PS6,
+       PMUX_PINGRP_KB_ROW15_PS7,
+       PMUX_PINGRP_KB_COL0_PQ0,
+       PMUX_PINGRP_KB_COL1_PQ1,
+       PMUX_PINGRP_KB_COL2_PQ2,
+       PMUX_PINGRP_KB_COL3_PQ3,
+       PMUX_PINGRP_KB_COL4_PQ4,
+       PMUX_PINGRP_KB_COL5_PQ5,
+       PMUX_PINGRP_KB_COL6_PQ6,
+       PMUX_PINGRP_KB_COL7_PQ7,
+       PMUX_PINGRP_CLK_32K_OUT_PA0,
+       PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
+       PMUX_PINGRP_CPU_PWR_REQ,
+       PMUX_PINGRP_PWR_INT_N,
+       PMUX_PINGRP_CLK_32K_IN,
+       PMUX_PINGRP_OWR,
+       PMUX_PINGRP_DAP1_FS_PN0,
+       PMUX_PINGRP_DAP1_DIN_PN1,
+       PMUX_PINGRP_DAP1_DOUT_PN2,
+       PMUX_PINGRP_DAP1_SCLK_PN3,
+       PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
+       PMUX_PINGRP_DAP_MCLK1_PW4,
+       PMUX_PINGRP_SPDIF_IN_PK6,
+       PMUX_PINGRP_SPDIF_OUT_PK5,
+       PMUX_PINGRP_DAP2_FS_PA2,
+       PMUX_PINGRP_DAP2_DIN_PA4,
+       PMUX_PINGRP_DAP2_DOUT_PA5,
+       PMUX_PINGRP_DAP2_SCLK_PA3,
+       PMUX_PINGRP_DVFS_PWM_PX0,
+       PMUX_PINGRP_GPIO_X1_AUD_PX1,
+       PMUX_PINGRP_GPIO_X3_AUD_PX3,
+       PMUX_PINGRP_DVFS_CLK_PX2,
+       PMUX_PINGRP_GPIO_X4_AUD_PX4,
+       PMUX_PINGRP_GPIO_X5_AUD_PX5,
+       PMUX_PINGRP_GPIO_X6_AUD_PX6,
+       PMUX_PINGRP_GPIO_X7_AUD_PX7,
+       PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+       PMUX_PINGRP_SDMMC3_CMD_PA7,
+       PMUX_PINGRP_SDMMC3_DAT0_PB7,
+       PMUX_PINGRP_SDMMC3_DAT1_PB6,
+       PMUX_PINGRP_SDMMC3_DAT2_PB5,
+       PMUX_PINGRP_SDMMC3_DAT3_PB4,
+       PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
+       PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+       PMUX_PINGRP_PEX_WAKE_N_PDD3,
+       PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
+       PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+       PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+       PMUX_PINGRP_SDMMC1_WP_N_PV3,
+       PMUX_PINGRP_SDMMC3_CD_N_PV2,
+       PMUX_PINGRP_GPIO_W2_AUD_PW2,
+       PMUX_PINGRP_GPIO_W3_AUD_PW3,
+       PMUX_PINGRP_USB_VBUS_EN0_PN4,
+       PMUX_PINGRP_USB_VBUS_EN1_PN5,
+       PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+       PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+       PMUX_PINGRP_GMI_CLK_LB,
+       PMUX_PINGRP_RESET_OUT_N,
+       PMUX_PINGRP_KB_ROW16_PT0,
+       PMUX_PINGRP_KB_ROW17_PT1,
+       PMUX_PINGRP_USB_VBUS_EN2_PFF1,
+       PMUX_PINGRP_PFF2,
+       PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
+       PMUX_PINGRP_COUNT,
 };
 
-enum pdrive_pingrp {
-       PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
-       PDRIVE_PINGROUP_AO2,
-       PDRIVE_PINGROUP_AT1,
-       PDRIVE_PINGROUP_AT2,
-       PDRIVE_PINGROUP_AT3,
-       PDRIVE_PINGROUP_AT4,
-       PDRIVE_PINGROUP_AT5,
-       PDRIVE_PINGROUP_CDEV1,
-       PDRIVE_PINGROUP_CDEV2,
-       PDRIVE_PINGROUP_DAP1 = 10,      /* offset 0x890 */
-       PDRIVE_PINGROUP_DAP2,
-       PDRIVE_PINGROUP_DAP3,
-       PDRIVE_PINGROUP_DAP4,
-       PDRIVE_PINGROUP_DBG,
-       PDRIVE_PINGROUP_SDIO3 = 18,     /* offset 0x8B0 */
-       PDRIVE_PINGROUP_SPI,
-       PDRIVE_PINGROUP_UAA,
-       PDRIVE_PINGROUP_UAB,
-       PDRIVE_PINGROUP_UART2,
-       PDRIVE_PINGROUP_UART3,
-       PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
-       PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
-       PDRIVE_PINGROUP_GMA,
-       PDRIVE_PINGROUP_GME = 42,       /* offset 0x910 */
-       PDRIVE_PINGROUP_GMF,
-       PDRIVE_PINGROUP_GMG,
-       PDRIVE_PINGROUP_GMH,
-       PDRIVE_PINGROUP_OWR,
-       PDRIVE_PINGROUP_UAD,
-       PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
-       PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
-       PDRIVE_PINGROUP_AT6 = 75,       /* offset 0x994 */
-       PDRIVE_PINGROUP_DAP5,
-       PDRIVE_PINGROUP_VBUS,
-       PDRIVE_PINGROUP_AO3,
-       PDRIVE_PINGROUP_HVC,
-       PDRIVE_PINGROUP_SDIO4,
-       PDRIVE_PINGROUP_AO0,
-       PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+       PMUX_DRVGRP_AO1,
+       PMUX_DRVGRP_AO2,
+       PMUX_DRVGRP_AT1,
+       PMUX_DRVGRP_AT2,
+       PMUX_DRVGRP_AT3,
+       PMUX_DRVGRP_AT4,
+       PMUX_DRVGRP_AT5,
+       PMUX_DRVGRP_CDEV1,
+       PMUX_DRVGRP_CDEV2,
+       PMUX_DRVGRP_DAP1 = (0x28 / 4),
+       PMUX_DRVGRP_DAP2,
+       PMUX_DRVGRP_DAP3,
+       PMUX_DRVGRP_DAP4,
+       PMUX_DRVGRP_DBG,
+       PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+       PMUX_DRVGRP_SPI,
+       PMUX_DRVGRP_UAA,
+       PMUX_DRVGRP_UAB,
+       PMUX_DRVGRP_UART2,
+       PMUX_DRVGRP_UART3,
+       PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+       PMUX_DRVGRP_DDC = (0x94 / 4),
+       PMUX_DRVGRP_GMA,
+       PMUX_DRVGRP_GME = (0xa8 / 4),
+       PMUX_DRVGRP_GMF,
+       PMUX_DRVGRP_GMG,
+       PMUX_DRVGRP_GMH,
+       PMUX_DRVGRP_OWR,
+       PMUX_DRVGRP_UDA,
+       PMUX_DRVGRP_GPV,
+       PMUX_DRVGRP_DEV3,
+       PMUX_DRVGRP_CEC = (0xd0 / 4),
+       PMUX_DRVGRP_AT6 = (0x12c / 4),
+       PMUX_DRVGRP_DAP5,
+       PMUX_DRVGRP_USB_VBUS_EN,
+       PMUX_DRVGRP_AO3 = (0x140 / 4),
+       PMUX_DRVGRP_AO0 = (0x148 / 4),
+       PMUX_DRVGRP_HV0,
+       PMUX_DRVGRP_SDIO4 = (0x15c / 4),
+       PMUX_DRVGRP_AO4,
+       PMUX_DRVGRP_COUNT,
 };
 
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
 enum pmux_func {
-       PMUX_FUNC_AHB_CLK,
-       PMUX_FUNC_APB_CLK,
-       PMUX_FUNC_AUDIO_SYNC,
-       PMUX_FUNC_CRT,
-       PMUX_FUNC_DAP1,
-       PMUX_FUNC_DAP2,
-       PMUX_FUNC_DAP3,
-       PMUX_FUNC_DAP4,
-       PMUX_FUNC_DAP5,
-       PMUX_FUNC_DISPA,
-       PMUX_FUNC_DISPB,
-       PMUX_FUNC_EMC_TEST0_DLL,
-       PMUX_FUNC_EMC_TEST1_DLL,
-       PMUX_FUNC_GMI,
-       PMUX_FUNC_GMI_INT,
-       PMUX_FUNC_HDMI,
-       PMUX_FUNC_I2C1,
-       PMUX_FUNC_I2C2,
-       PMUX_FUNC_I2C3,
-       PMUX_FUNC_IDE,
-       PMUX_FUNC_KBC,
-       PMUX_FUNC_MIO,
-       PMUX_FUNC_MIPI_HS,
-       PMUX_FUNC_NAND,
-       PMUX_FUNC_OSC,
-       PMUX_FUNC_OWR,
-       PMUX_FUNC_PCIE,
-       PMUX_FUNC_PLLA_OUT,
-       PMUX_FUNC_PLLC_OUT1,
-       PMUX_FUNC_PLLM_OUT1,
-       PMUX_FUNC_PLLP_OUT2,
-       PMUX_FUNC_PLLP_OUT3,
-       PMUX_FUNC_PLLP_OUT4,
-       PMUX_FUNC_PWM,
-       PMUX_FUNC_PWR_INTR,
-       PMUX_FUNC_PWR_ON,
-       PMUX_FUNC_RTCK,
-       PMUX_FUNC_SDMMC1,
-       PMUX_FUNC_SDMMC2,
-       PMUX_FUNC_SDMMC3,
-       PMUX_FUNC_SDMMC4,
-       PMUX_FUNC_SFLASH,
-       PMUX_FUNC_SPDIF,
-       PMUX_FUNC_SPI1,
-       PMUX_FUNC_SPI2,
-       PMUX_FUNC_SPI2_ALT,
-       PMUX_FUNC_SPI3,
-       PMUX_FUNC_SPI4,
-       PMUX_FUNC_TRACE,
-       PMUX_FUNC_TWC,
-       PMUX_FUNC_UARTA,
-       PMUX_FUNC_UARTB,
-       PMUX_FUNC_UARTC,
-       PMUX_FUNC_UARTD,
-       PMUX_FUNC_UARTE,
-       PMUX_FUNC_ULPI,
-       PMUX_FUNC_VI,
-       PMUX_FUNC_VI_SENSOR_CLK,
-       PMUX_FUNC_XIO,
-       /* End of Tegra2 MUX selectors */
        PMUX_FUNC_BLINK,
+       PMUX_FUNC_CCLA,
        PMUX_FUNC_CEC,
+       PMUX_FUNC_CLDVFS,
+       PMUX_FUNC_CLK,
        PMUX_FUNC_CLK12,
+       PMUX_FUNC_CPU,
        PMUX_FUNC_DAP,
-       PMUX_FUNC_DAPSDMMC2,
-       PMUX_FUNC_DDR,
+       PMUX_FUNC_DAP1,
+       PMUX_FUNC_DAP2,
        PMUX_FUNC_DEV3,
+       PMUX_FUNC_DISPLAYA,
+       PMUX_FUNC_DISPLAYA_ALT,
+       PMUX_FUNC_DISPLAYB,
+       PMUX_FUNC_DP,
        PMUX_FUNC_DTV,
-       PMUX_FUNC_VI_ALT1,
-       PMUX_FUNC_VI_ALT2,
-       PMUX_FUNC_VI_ALT3,
-       PMUX_FUNC_EMC_DLL,
        PMUX_FUNC_EXTPERIPH1,
        PMUX_FUNC_EXTPERIPH2,
        PMUX_FUNC_EXTPERIPH3,
+       PMUX_FUNC_GMI,
        PMUX_FUNC_GMI_ALT,
        PMUX_FUNC_HDA,
        PMUX_FUNC_HSI,
+       PMUX_FUNC_I2C1,
+       PMUX_FUNC_I2C2,
+       PMUX_FUNC_I2C3,
        PMUX_FUNC_I2C4,
-       PMUX_FUNC_I2C5,
        PMUX_FUNC_I2CPWR,
        PMUX_FUNC_I2S0,
        PMUX_FUNC_I2S1,
        PMUX_FUNC_I2S2,
        PMUX_FUNC_I2S3,
        PMUX_FUNC_I2S4,
-       PMUX_FUNC_NAND_ALT,
-       PMUX_FUNC_POPSDIO4,
-       PMUX_FUNC_POPSDMMC4,
+       PMUX_FUNC_IRDA,
+       PMUX_FUNC_KBC,
+       PMUX_FUNC_OWR,
+       PMUX_FUNC_PE,
+       PMUX_FUNC_PE0,
+       PMUX_FUNC_PE1,
+       PMUX_FUNC_PMI,
        PMUX_FUNC_PWM0,
        PMUX_FUNC_PWM1,
        PMUX_FUNC_PWM2,
        PMUX_FUNC_PWM3,
+       PMUX_FUNC_PWRON,
+       PMUX_FUNC_RESET_OUT_N,
+       PMUX_FUNC_RTCK,
        PMUX_FUNC_SATA,
+       PMUX_FUNC_SDMMC1,
+       PMUX_FUNC_SDMMC2,
+       PMUX_FUNC_SDMMC3,
+       PMUX_FUNC_SDMMC4,
+       PMUX_FUNC_SOC,
+       PMUX_FUNC_SPDIF,
+       PMUX_FUNC_SPI1,
+       PMUX_FUNC_SPI2,
+       PMUX_FUNC_SPI3,
+       PMUX_FUNC_SPI4,
        PMUX_FUNC_SPI5,
        PMUX_FUNC_SPI6,
-       PMUX_FUNC_SYSCLK,
+       PMUX_FUNC_SYS,
+       PMUX_FUNC_TMDS,
+       PMUX_FUNC_TRACE,
+       PMUX_FUNC_UARTA,
+       PMUX_FUNC_UARTB,
+       PMUX_FUNC_UARTC,
+       PMUX_FUNC_UARTD,
+       PMUX_FUNC_ULPI,
+       PMUX_FUNC_USB,
        PMUX_FUNC_VGP1,
        PMUX_FUNC_VGP2,
        PMUX_FUNC_VGP3,
        PMUX_FUNC_VGP4,
        PMUX_FUNC_VGP5,
        PMUX_FUNC_VGP6,
-       /* End of Tegra3 MUX selectors */