CPC45 MPC8245
PM520 MPC5200
+Michael Weiss <michael.weiss@ifm.com>
+
+ PDM360NG MPC5121e
+
Stephen Williams <steve@icarus.com>
JSE PPC405GPr
EP1C20 Nios-II
EP1S10 Nios-II
EP1S40 Nios-II
+ nios2-generic Nios-II
#########################################################################
# MicroBlaze Systems: #
aria \
mecp5123 \
mpc5121ads \
+ pdm360ng \
"
#########################################################################
${LIST_86xx} \
"
-LIST_ppc=" \
+LIST_powerpc=" \
${LIST_5xx} \
${LIST_512x} \
${LIST_5xxx} \
${LIST_7xx} \
"
+# Alias "ppc" -> "powerpc" to not break compatibility with older scripts
+# still using "ppc" instead of "powerpc"
+LIST_ppc=" \
+ ${LIST_powerpc} \
+"
+
#########################################################################
## StrongARM Systems
#########################################################################
EP1S40 \
PCI5441 \
PK1C20 \
+ nios2-generic \
"
#########################################################################
#-----------------------------------------------------------------------
-#----- for now, just run PPC by default -----
-[ $# = 0 ] && set $LIST_ppc
+#----- for now, just run PowerPC by default -----
+[ $# = 0 ] && set $LIST_powerpc
#-----------------------------------------------------------------------
|microblaze \
|mips|mips_el \
|nios|nios2 \
- |ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
+ |ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \
|sh|sh2|sh3|sh4 \
|sparc \
|x86|I486 \
#########################################################################
-ifeq ($(ARCH),powerpc)
-ARCH = ppc
-endif
-
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
SUBDIRS = tools \
endif
ifeq ($(CPU),mpc85xx)
LIBS += drivers/qe/qe.a
-LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a
-LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a
+LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.a
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
endif
ifeq ($(CPU),mpc86xx)
-LIBS += arch/ppc/cpu/mpc8xxx/ddr/libddr.a
-LIBS += arch/ppc/cpu/mpc8xxx/lib8xxx.a
+LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.a
+LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.a
endif
LIBS += drivers/rtc/librtc.a
LIBS += drivers/serial/libserial.a
#########################################################################
canmb_config: unconfig
- @$(MKCONFIG) -a canmb ppc mpc5xxx canmb
+ @$(MKCONFIG) -a canmb powerpc mpc5xxx canmb
cmi_mpc5xx_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc5xx cmi
+ @$(MKCONFIG) $(@:_config=) powerpc mpc5xx cmi
PATI_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc5xx pati mpl
+ @$(MKCONFIG) $(@:_config=) powerpc mpc5xx pati mpl
#########################################################################
## MPC5xxx Systems
#########################################################################
aev_config: unconfig
- @$(MKCONFIG) -a aev ppc mpc5xxx tqm5200 tqc
+ @$(MKCONFIG) -a aev powerpc mpc5xxx tqm5200 tqc
BC3450_config: unconfig
- @$(MKCONFIG) -a BC3450 ppc mpc5xxx bc3450
+ @$(MKCONFIG) -a BC3450 powerpc mpc5xxx bc3450
cm5200_config: unconfig
- @$(MKCONFIG) -a cm5200 ppc mpc5xxx cm5200
+ @$(MKCONFIG) -a cm5200 powerpc mpc5xxx cm5200
cpci5200_config: unconfig
- @$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd
+ @$(MKCONFIG) -a cpci5200 powerpc mpc5xxx cpci5200 esd
digsy_mtc_config \
digsy_mtc_LOWBOOT_config \
{ echo "TEXT_BASE = 0x00100000" >$(obj)board/digsy_mtc/config.tmp ; \
echo "... with RAMBOOT configuration" ; \
}
- @$(MKCONFIG) -a digsy_mtc ppc mpc5xxx digsy_mtc
+ @$(MKCONFIG) -a digsy_mtc powerpc mpc5xxx digsy_mtc
galaxy5200_LOWBOOT_config \
galaxy5200_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
- @$(MKCONFIG) -a galaxy5200 ppc mpc5xxx galaxy5200
+ @$(MKCONFIG) -a galaxy5200 powerpc mpc5xxx galaxy5200
hmi1001_config: unconfig
- @$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001
+ @$(MKCONFIG) hmi1001 powerpc mpc5xxx hmi1001
Lite5200_config \
Lite5200_LOWBOOT_config \
{ echo "#define CONFIG_MPC5200_DDR" >>$(obj)include/config.h ; \
$(XECHO) "... DDR memory revision" ; \
}
- @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
+ @$(MKCONFIG) -a IceCube powerpc mpc5xxx icecube
jupiter_config: unconfig
- @$(MKCONFIG) jupiter ppc mpc5xxx jupiter
+ @$(MKCONFIG) jupiter powerpc mpc5xxx jupiter
inka4x0_config: unconfig
- @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
+ @$(MKCONFIG) inka4x0 powerpc mpc5xxx inka4x0
ipek01_config: unconfig
- @$(MKCONFIG) -a ipek01 ppc mpc5xxx ipek01
+ @$(MKCONFIG) -a ipek01 powerpc mpc5xxx ipek01
lite5200b_config \
lite5200b_PM_config \
{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/icecube/config.tmp ; \
$(XECHO) "... with LOWBOOT configuration" ; \
}
- @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
+ @$(MKCONFIG) -a IceCube powerpc mpc5xxx icecube
mcc200_config \
mcc200_SDRAM_config \
@[ -z "$(findstring prs200,$@)" ] || \
{ echo "#define CONFIG_PRS200" >>$(obj)include/config.h ;\
}
- @$(MKCONFIG) -n $@ -a mcc200 ppc mpc5xxx mcc200
+ @$(MKCONFIG) -n $@ -a mcc200 powerpc mpc5xxx mcc200
mecp5200_config: unconfig
- @$(MKCONFIG) mecp5200 ppc mpc5xxx mecp5200 esd
+ @$(MKCONFIG) mecp5200 powerpc mpc5xxx mecp5200 esd
motionpro_config: unconfig
- @$(MKCONFIG) motionpro ppc mpc5xxx motionpro
+ @$(MKCONFIG) motionpro powerpc mpc5xxx motionpro
mucmc52_config: unconfig
- @$(MKCONFIG) mucmc52 ppc mpc5xxx mucmc52
+ @$(MKCONFIG) mucmc52 powerpc mpc5xxx mucmc52
munices_config: unconfig
- @$(MKCONFIG) munices ppc mpc5xxx munices
+ @$(MKCONFIG) munices powerpc mpc5xxx munices
MVBC_P_config: unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@[ -z "$(findstring MVBC_P,$@)" ] || \
{ echo "#define CONFIG_MVBC_P" >>$(obj)include/config.h; }
- @$(MKCONFIG) -n $@ -a MVBC_P ppc mpc5xxx mvbc_p matrix_vision
+ @$(MKCONFIG) -n $@ -a MVBC_P powerpc mpc5xxx mvbc_p matrix_vision
MVSMR_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/matrix_vision/mvsmr
- @$(MKCONFIG) $(@:_config=) ppc mpc5xxx mvsmr matrix_vision
+ @$(MKCONFIG) $(@:_config=) powerpc mpc5xxx mvsmr matrix_vision
o2dnt_config: unconfig
- @$(MKCONFIG) o2dnt ppc mpc5xxx o2dnt
+ @$(MKCONFIG) o2dnt powerpc mpc5xxx o2dnt
pcm030_config \
pcm030_LOWBOOT_config: unconfig
{ echo "TEXT_BASE = 0xFF000000" >$(obj)board/phytec/pcm030/config.tmp ; \
echo "... with LOWBOOT configuration" ; \
}
- @$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
+ @$(MKCONFIG) -a pcm030 powerpc mpc5xxx pcm030 phytec
pf5200_config: unconfig
- @$(MKCONFIG) pf5200 ppc mpc5xxx pf5200 esd
+ @$(MKCONFIG) pf5200 powerpc mpc5xxx pf5200 esd
PM520_config \
PM520_DDR_config \
{ echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \
$(XECHO) "... booting from 8-bit flash" ; \
}
- @$(MKCONFIG) -a PM520 ppc mpc5xxx pm520
+ @$(MKCONFIG) -a PM520 powerpc mpc5xxx pm520
smmaco4_config: unconfig
- @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 tqc
+ @$(MKCONFIG) -a smmaco4 powerpc mpc5xxx tqm5200 tqc
spieval_config: unconfig
- @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 tqc
+ @$(MKCONFIG) -a spieval powerpc mpc5xxx tqm5200 tqc
TB5200_B_config \
TB5200_config: unconfig
{ echo "#define CONFIG_TQM5200_B" >>$(obj)include/config.h ; \
$(XECHO) "... with MPC5200B processor" ; \
}
- @$(MKCONFIG) -n $@ -a TB5200 ppc mpc5xxx tqm5200 tqc
+ @$(MKCONFIG) -n $@ -a TB5200 powerpc mpc5xxx tqm5200 tqc
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
@mkdir -p $(obj)include
@ echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a TOP5200 ppc mpc5xxx top5200 emk
+ @$(MKCONFIG) -n $@ -a TOP5200 powerpc mpc5xxx top5200 emk
Total5200_config \
Total5200_lowboot_config \
{ echo "TEXT_BASE = 0xFE000000" >$(obj)board/total5200/config.tmp ; \
$(XECHO) "... with lowboot configuration" ; \
}
- @$(MKCONFIG) -a Total5200 ppc mpc5xxx total5200
+ @$(MKCONFIG) -a Total5200 powerpc mpc5xxx total5200
cam5200_config \
cam5200_niosflash_config \
@[ -z "$(findstring HIGHBOOT,$@)" ] || \
{ echo "TEXT_BASE = 0xFFF00000" >$(obj)board/tqm5200/config.tmp ; \
}
- @$(MKCONFIG) -n $@ -a TQM5200 ppc mpc5xxx tqm5200 tqc
+ @$(MKCONFIG) -n $@ -a TQM5200 powerpc mpc5xxx tqm5200 tqc
uc101_config: unconfig
- @$(MKCONFIG) uc101 ppc mpc5xxx uc101
+ @$(MKCONFIG) uc101 powerpc mpc5xxx uc101
v38b_config: unconfig
- @$(MKCONFIG) -a v38b ppc mpc5xxx v38b
+ @$(MKCONFIG) -a v38b powerpc mpc5xxx v38b
#########################################################################
## MPC512x Systems
#########################################################################
aria_config: unconfig
- @$(MKCONFIG) -a aria ppc mpc512x aria davedenx
+ @$(MKCONFIG) -a aria powerpc mpc512x aria davedenx
mecp5123_config: unconfig
- @$(MKCONFIG) -a mecp5123 ppc mpc512x mecp5123 esd
+ @$(MKCONFIG) -a mecp5123 powerpc mpc512x mecp5123 esd
mpc5121ads_config \
mpc5121ads_rev2_config \
@if [ "$(findstring rev2,$@)" ] ; then \
echo "#define CONFIG_ADS5121_REV2 1" > $(obj)include/config.h; \
fi
- @$(MKCONFIG) -a mpc5121ads ppc mpc512x mpc5121ads freescale
+ @$(MKCONFIG) -a mpc5121ads powerpc mpc512x mpc5121ads freescale
+
+pdm360ng_config: unconfig
+ @$(MKCONFIG) -a pdm360ng powerpc mpc512x pdm360ng
#########################################################################
## MPC8xx Systems
@mkdir -p $(obj)include
$(if $(findstring AdderII,$@), \
@echo "#define CONFIG_MPC852T" > $(obj)include/config.h)
- @$(MKCONFIG) -a Adder ppc mpc8xx adder
+ @$(MKCONFIG) -a Adder powerpc mpc8xx adder
AdderUSB_config: unconfig
- @$(MKCONFIG) -a AdderUSB ppc mpc8xx adder
+ @$(MKCONFIG) -a AdderUSB powerpc mpc8xx adder
ADS860_config \
FADS823_config \
MPC86xADS_config \
MPC885ADS_config \
FADS860T_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx fads
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx fads
AMX860_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx amx860 westel
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx amx860 westel
c2mon_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx c2mon
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx c2mon
CCM_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx CCM siemens
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx CCM siemens
cogent_mpc8xx_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx cogent
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx cogent
ELPT860_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx elpt860 LEOX
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx elpt860 LEOX
EP88x_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx ep88x
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx ep88x
ESTEEM192E_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx esteem192e
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx esteem192e
ETX094_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx etx094
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx etx094
FLAGADM_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx flagadm
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx flagadm
xtract_GEN860T = $(subst _SC,,$(subst _config,,$1))
{ echo "#define CONFIG_SC" >>$(obj)include/config.h ; \
$(XECHO) "With reduced H/W feature set (SC)..." ; \
}
- @$(MKCONFIG) -a $(call xtract_GEN860T,$@) ppc mpc8xx gen860t
+ @$(MKCONFIG) -a $(call xtract_GEN860T,$@) powerpc mpc8xx gen860t
GENIETV_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx genietv
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx genietv
GTH_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx gth
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx gth
hermes_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx hermes
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx hermes
HMI10_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx tqm8xx tqc
IAD210_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx IAD210 siemens
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx IAD210 siemens
xtract_ICU862 = $(subst _100MHz,,$(subst _config,,$1))
{ echo "#define CONFIG_100MHz" >>$(obj)include/config.h ; \
$(XECHO) "... with 100MHz system clock" ; \
}
- @$(MKCONFIG) -a $(call xtract_ICU862,$@) ppc mpc8xx icu862
+ @$(MKCONFIG) -a $(call xtract_ICU862,$@) powerpc mpc8xx icu862
IP860_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx ip860
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx ip860
IVML24_256_config \
IVML24_128_config \
@[ -z "$(findstring IVML24_256_config,$@)" ] || \
{ echo "#define CONFIG_IVML24_64M" >>$(obj)include/config.h ; \
}
- @$(MKCONFIG) -a IVML24 ppc mpc8xx ivm
+ @$(MKCONFIG) -a IVML24 powerpc mpc8xx ivm
IVMS8_256_config \
IVMS8_128_config \
@[ -z "$(findstring IVMS8_256_config,$@)" ] || \
{ echo "#define CONFIG_IVMS8_64M" >>$(obj)include/config.h ; \
}
- @$(MKCONFIG) -a IVMS8 ppc mpc8xx ivm
+ @$(MKCONFIG) -a IVMS8 powerpc mpc8xx ivm
kmsupx4_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx km8xx keymile
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx km8xx keymile
KUP4K_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4k kup
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx kup4k kup
KUP4X_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx kup4x kup
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx kup4x kup
LANTEC_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx lantec
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx lantec
lwmon_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx lwmon
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx lwmon
MBX_config \
MBX860T_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx mbx8xx
mgsuvd_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx km8xx keymile
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx km8xx keymile
MHPC_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx mhpc eltec
xtract_NETVIA = $(subst _V2,,$(subst _config,,$1))
{ echo "#define CONFIG_NETVIA_VERSION 2" >>$(obj)include/config.h ; \
$(XECHO) "... Version 2" ; \
}
- @$(MKCONFIG) -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia
+ @$(MKCONFIG) -a $(call xtract_NETVIA,$@) powerpc mpc8xx netvia
xtract_NETPHONE = $(subst _V2,,$(subst _config,,$1))
@[ -z "$(findstring NETPHONE_V2_config,$@)" ] || \
{ echo "#define CONFIG_NETPHONE_VERSION 2" >>$(obj)include/config.h ; \
}
- @$(MKCONFIG) -a $(call xtract_NETPHONE,$@) ppc mpc8xx netphone
+ @$(MKCONFIG) -a $(call xtract_NETPHONE,$@) powerpc mpc8xx netphone
xtract_NETTA = $(subst _SWAPHOOK,,$(subst _6412,,$(subst _ISDN,,$(subst _config,,$1))))
@[ -n "$(findstring SWAPHOOK_,$@)" ] || \
{ echo "#undef CONFIG_NETTA_SWAPHOOK" >>$(obj)include/config.h ; \
}
- @$(MKCONFIG) -a $(call xtract_NETTA,$@) ppc mpc8xx netta
+ @$(MKCONFIG) -a $(call xtract_NETTA,$@) powerpc mpc8xx netta
xtract_NETTA2 = $(subst _V2,,$(subst _config,,$1))
@[ -z "$(findstring NETTA2_V2_config,$@)" ] || \
{ echo "#define CONFIG_NETTA2_VERSION 2" >>$(obj)include/config.h ; \
}
- @$(MKCONFIG) -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2
+ @$(MKCONFIG) -a $(call xtract_NETTA2,$@) powerpc mpc8xx netta2
NC650_Rev1_config \
NC650_Rev2_config \
@[ -z "$(findstring Rev2,$@)" ] || \
{ echo "#define CONFIG_IDS852_REV2 1" >>$(obj)include/config.h ; \
}
- @$(MKCONFIG) -a NC650 ppc mpc8xx nc650
+ @$(MKCONFIG) -a NC650 powerpc mpc8xx nc650
NX823_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx nx823
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx nx823
pcu_e_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx pcu_e siemens
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx pcu_e siemens
QS850_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs850 snmc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx qs850 snmc
QS823_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs850 snmc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx qs850 snmc
QS860T_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx qs860t snmc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx qs860t snmc
quantum_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx quantum
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx quantum
R360MPI_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx r360mpi
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx r360mpi
RBC823_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx rbc823
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx rbc823
RPXClassic_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXClassic
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx RPXClassic
RPXlite_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXlite
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx RPXlite
RPXlite_DW_64_config \
RPXlite_DW_LCD_config \
{ echo "#define CONFIG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \
$(XECHO) "... with ENV in NVRAM ..."; \
}
- @$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw
+ @$(MKCONFIG) -a RPXlite_DW powerpc mpc8xx RPXlite_dw
rmu_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx rmu
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx rmu
RRvision_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx RRvision
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx RRvision
RRvision_LCD_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
- @$(MKCONFIG) -a RRvision ppc mpc8xx RRvision
+ @$(MKCONFIG) -a RRvision powerpc mpc8xx RRvision
SM850_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx tqm8xx tqc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx tqm8xx tqc
spc1920_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx spc1920
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx spc1920
SPD823TS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx spd8xx
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx spd8xx
stxxtc_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc stx
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx stxxtc stx
svm_sc8xx_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx svm_sc8xx
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx svm_sc8xx
SXNI855T_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx sixnet
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx sixnet
# EMK MPC8xx based modules
TOP860_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx top860 emk
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx top860 emk
# Play some tricks for configuration selection
# Only 855 and 860 boards may come with FEC
echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
$(XECHO) "... with LCD display" ; \
}
- @$(MKCONFIG) -a $(call xtract_8xx,$@) ppc mpc8xx tqm8xx tqc
+ @$(MKCONFIG) -a $(call xtract_8xx,$@) powerpc mpc8xx tqm8xx tqc
TTTech_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ104V7DS01" >>$(obj)include/config.h
- @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc
+ @$(MKCONFIG) -a TQM823L powerpc mpc8xx tqm8xx tqc
uc100_config : unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx uc100
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx uc100
v37_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ084V1DG21" >>$(obj)include/config.h
- @$(MKCONFIG) $(@:_config=) ppc mpc8xx v37
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8xx v37
wtk_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_LCD" >$(obj)include/config.h
@echo "#define CONFIG_SHARP_LQ065T9DR51U" >>$(obj)include/config.h
- @$(MKCONFIG) -a TQM823L ppc mpc8xx tqm8xx tqc
+ @$(MKCONFIG) -a TQM823L powerpc mpc8xx tqm8xx tqc
#########################################################################
## PPC4xx Systems
xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1))))))
acadia_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx acadia amcc
acadia_nand_config: unconfig
@mkdir -p $(obj)include $(obj)board/amcc/acadia
@mkdir -p $(obj)nand_spl/board/amcc/acadia
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a acadia ppc ppc4xx acadia amcc
+ @$(MKCONFIG) -n $@ -a acadia powerpc ppc4xx acadia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/acadia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
ADCIOP_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx adciop esd
alpr_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx alpr prodrive
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx alpr prodrive
AP1000_config:unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ap1000 amirix
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx ap1000 amirix
APC405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx apc405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx apc405 esd
AR405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ar405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx ar405 esd
ASH405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ash405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx ash405 esd
bamboo_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx bamboo amcc
bamboo_nand_config: unconfig
@mkdir -p $(obj)include $(obj)board/amcc/bamboo
@mkdir -p $(obj)nand_spl/board/amcc/bamboo
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a bamboo ppc ppc4xx bamboo amcc
+ @$(MKCONFIG) -n $@ -a bamboo powerpc ppc4xx bamboo amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
bubinga_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx bubinga amcc
CANBT_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx canbt esd
# Arches, Canyonlands & Glacier use different U-Boot images
arches_config \
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
+ @$(MKCONFIG) -n $@ -a canyonlands powerpc ppc4xx canyonlands amcc
canyonlands_nand_config \
glacier_nand_config: unconfig
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_nand_config=)) | \
tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
+ @$(MKCONFIG) -n $@ -a canyonlands powerpc ppc4xx canyonlands amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/canyonlands/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >> $(obj)include/config.h ; \
$(XECHO) "SysClk = 33MHz" ; \
}
- @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+ @$(MKCONFIG) -a $(call xtract_4xx,$@) powerpc ppc4xx PPChameleonEVB dave
CMS700_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx cms700 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx cms700 esd
CPCI2DP_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci2dp esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx cpci2dp esd
CPCI405_config \
CPCI4052_config \
CPCI405DT_config \
CPCI405AB_config: unconfig
@mkdir -p $(obj)board/esd/cpci405
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx cpci405 esd
CPCIISER4_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx cpciiser4 esd
CRAYL1_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx L1 cray
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx L1 cray
csb272_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx csb272
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx csb272
csb472_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx csb472
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx csb472
DASA_SIM_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx dasa_sim esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx dasa_sim esd
dlvision_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx dlvision gdsys
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx dlvision gdsys
DP405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx dp405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx dp405 esd
DU405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx du405 esd
DU440_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx du440 esd
ebony_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx ebony amcc
ERIC_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx eric
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx eric
fx12mm_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
> $(obj)board/avnet/fx12mm/config.tmp
@echo "TEXT_BASE := 0xFFCB0000" \
>> $(obj)board/avnet/fx12mm/config.tmp
- @$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+ @$(MKCONFIG) fx12mm powerpc ppc4xx fx12mm avnet
fx12mm_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
> $(obj)board/avnet/fx12mm/config.tmp
@echo "TEXT_BASE := 0x03000000" \
>> $(obj)board/avnet/fx12mm/config.tmp
- @$(MKCONFIG) fx12mm ppc ppc4xx fx12mm avnet
+ @$(MKCONFIG) fx12mm powerpc ppc4xx fx12mm avnet
G2000_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx g2000
gdppc440etx_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx gdppc440etx gdsys
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx gdppc440etx gdsys
hcu4_config: unconfig
@mkdir -p $(obj)board/netstal/common
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx hcu4 netstal
hcu5_config: unconfig
@mkdir -p $(obj)board/netstal/common
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx hcu5 netstal
HH405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx hh405 esd
HUB405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx hub405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx hub405 esd
# Compact-Center(codename intip) & DevCon-Center use different U-Boot images
intip_config \
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a intip ppc ppc4xx intip gdsys
+ @$(MKCONFIG) -n $@ -a intip powerpc ppc4xx intip gdsys
JSE_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx jse
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx jse
KAREF_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx karef sandburst
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx karef sandburst
katmai_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx katmai amcc
# Kilauea & Haleakala images are identical (recognized via PVR)
kilauea_config \
haleakala_config: unconfig
- @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc
+ @$(MKCONFIG) -n $@ -a kilauea powerpc ppc4xx kilauea amcc
kilauea_nand_config \
haleakala_nand_config: unconfig
@mkdir -p $(obj)include $(obj)board/amcc/kilauea
@mkdir -p $(obj)nand_spl/board/amcc/kilauea
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc
+ @$(MKCONFIG) -n $@ -a kilauea powerpc ppc4xx kilauea amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
korat_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx korat
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx korat
luan_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx luan amcc
lwmon5_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx lwmon5
makalu_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx makalu amcc
mcu25_config: unconfig
@mkdir -p $(obj)board/netstal/common
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx mcu25 netstal
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx mcu25 netstal
METROBOX_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx metrobox sandburst
MIP405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx mip405 mpl
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx mip405 mpl
MIP405T_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MIP405T" >$(obj)include/config.h
@$(XECHO) "Enable subset config for MIP405T"
- @$(MKCONFIG) -a MIP405 ppc ppc4xx mip405 mpl
+ @$(MKCONFIG) -a MIP405 powerpc ppc4xx mip405 mpl
ML2_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ml2
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx ml2
ml507_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
> $(obj)board/xilinx/ml507/config.tmp
@echo "TEXT_BASE := 0xFE360000" \
>> $(obj)board/xilinx/ml507/config.tmp
- @$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
+ @$(MKCONFIG) ml507 powerpc ppc4xx ml507 xilinx
ml507_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
> $(obj)board/xilinx/ml507/config.tmp
@echo "TEXT_BASE := 0x04000000" \
>> $(obj)board/xilinx/ml507/config.tmp
- @$(MKCONFIG) ml507 ppc ppc4xx ml507 xilinx
+ @$(MKCONFIG) ml507 powerpc ppc4xx ml507 xilinx
neo_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx neo gdsys
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx neo gdsys
ocotea_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocotea amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx ocotea amcc
OCRTC_config \
ORSG_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx ocrtc esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx ocrtc esd
p3p440_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx p3p440 prodrive
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx p3p440 prodrive
PCI405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx pci405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx pci405 esd
pcs440ep_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx pcs440ep
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx pcs440ep
PIP405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx pip405 mpl
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx pip405 mpl
PLU405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx plu405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx plu405 esd
PMC405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx pmc405 esd
PMC405DE_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405de esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx pmc405de esd
PMC440_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx pmc440 esd
PPChameleonEVB_config \
PPChameleonEVB_BA_25_config \
{ echo "#define CONFIG_PPCHAMELEON_CLK_33" >>$(obj)include/config.h ; \
$(XECHO) "SysClk = 33MHz" ; \
}
- @$(MKCONFIG) -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+ @$(MKCONFIG) -a $(call xtract_4xx,$@) powerpc ppc4xx PPChameleonEVB dave
quad100hd_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx quad100hd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx quad100hd
redwood_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx redwood amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx redwood amcc
sbc405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx sbc405
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx sbc405
sc3_config:unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx sc3
sequoia_config \
rainier_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
+ @$(MKCONFIG) -n $@ -a sequoia powerpc ppc4xx sequoia amcc
sequoia_nand_config \
rainier_nand_config: unconfig
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
+ @$(MKCONFIG) -n $@ -a sequoia powerpc ppc4xx sequoia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
@echo "#define CONFIG_SYS_RAMBOOT" > $(obj)include/config.h
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
- @$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
+ @$(MKCONFIG) -n $@ -a sequoia powerpc ppc4xx sequoia amcc
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
@echo "LDSCRIPT = board/amcc/sequoia/u-boot-ram.lds" >> \
$(obj)board/amcc/sequoia/config.tmp
taihu_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx taihu amcc
taishan_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx taishan amcc
v5fx30teval_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
> $(obj)board/avnet/v5fx30teval/config.tmp
@echo "TEXT_BASE := 0x03000000" \
>> $(obj)board/avnet/v5fx30teval/config.tmp
- @$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+ @$(MKCONFIG) v5fx30teval powerpc ppc4xx v5fx30teval avnet
v5fx30teval_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
> $(obj)board/avnet/v5fx30teval/config.tmp
@echo "TEXT_BASE := 0xFF1C0000" \
>> $(obj)board/avnet/v5fx30teval/config.tmp
- @$(MKCONFIG) v5fx30teval ppc ppc4xx v5fx30teval avnet
+ @$(MKCONFIG) v5fx30teval powerpc ppc4xx v5fx30teval avnet
VOH405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx voh405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx voh405 esd
VOM405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx vom405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx vom405 esd
W7OLMC_config \
W7OLMG_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx w7o
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx w7o
# Walnut & Sycamore images are identical (recognized via PVR)
walnut_config \
sycamore_config: unconfig
- @$(MKCONFIG) -n $@ -a walnut ppc ppc4xx walnut amcc
+ @$(MKCONFIG) -n $@ -a walnut powerpc ppc4xx walnut amcc
WUH405_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx wuh405 esd
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx wuh405 esd
xilinx-ppc405-generic_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
> $(obj)board/xilinx/ppc405-generic/config.tmp
@echo "TEXT_BASE := 0xFE360000" \
>> $(obj)board/xilinx/ppc405-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+ @$(MKCONFIG) xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx
xilinx-ppc405-generic_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc405-generic
> $(obj)board/xilinx/ppc405-generic/config.tmp
@echo "TEXT_BASE := 0x04000000" \
>> $(obj)board/xilinx/ppc405-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc405-generic ppc ppc4xx ppc405-generic xilinx
+ @$(MKCONFIG) xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx
xilinx-ppc440-generic_flash_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
> $(obj)board/xilinx/ppc440-generic/config.tmp
@echo "TEXT_BASE := 0xFE360000" \
>> $(obj)board/xilinx/ppc440-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+ @$(MKCONFIG) xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx
xilinx-ppc440-generic_config: unconfig
@mkdir -p $(obj)include $(obj)board/xilinx/ppc440-generic
> $(obj)board/xilinx/ppc440-generic/config.tmp
@echo "TEXT_BASE := 0x04000000" \
>> $(obj)board/xilinx/ppc440-generic/config.tmp
- @$(MKCONFIG) xilinx-ppc440-generic ppc ppc4xx ppc440-generic xilinx
+ @$(MKCONFIG) xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx
XPEDITE1000_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx xpedite1000 xes
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx xpedite1000 xes
yosemite_config \
yellowstone_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
- @$(MKCONFIG) -n $@ -a yosemite ppc ppc4xx yosemite amcc
+ @$(MKCONFIG) -n $@ -a yosemite powerpc ppc4xx yosemite amcc
yucca_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx yucca amcc
zeus_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
+ @$(MKCONFIG) $(@:_config=) powerpc ppc4xx zeus
#########################################################################
## MPC8220 Systems
Alaska8220_config \
Yukon8220_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8220 alaska
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8220 alaska
sorcery_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8220 sorcery
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8220 sorcery
#########################################################################
## MPC824x Systems
xtract_82xx = $(subst _BIGFLASH,,$(subst _ROMBOOT,,$(subst _L2,,$(subst _266MHz,,$(subst _300MHz,,$(subst _config,,$1))))))
A3000_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x a3000
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x a3000
barco_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x barco
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x barco
BMW_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x bmw
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x bmw
CPC45_config \
CPC45_ROMBOOT_config: unconfig
- @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc824x cpc45
+ @$(MKCONFIG) $(call xtract_82xx,$@) powerpc mpc824x cpc45
@cd $(obj)include ; \
if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
echo "export CONFIG_BOOT_ROM" >> config.mk;
CU824_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x cu824
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x cu824
debris_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x debris etin
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x debris etin
eXalion_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x eXalion
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x eXalion
HIDDEN_DRAGON_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x hidden_dragon
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x hidden_dragon
kvme080_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x kvme080 etin
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x kvme080 etin
# HDLAN is broken ATM. Should be fixed as soon as hardware is available and as
# time permits.
*HGLAN*) echo "#define CONFIG_HGLAN 1" >$(obj)include/config.h; ;; \
*HDLAN*) echo "#define CONFIG_HLAN 1" >$(obj)include/config.h; ;; \
esac
- @$(MKCONFIG) -n $@ -a linkstation ppc mpc824x linkstation
+ @$(MKCONFIG) -n $@ -a linkstation powerpc mpc824x linkstation
MOUSSE_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x mousse
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x mousse
MUSENKI_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x musenki
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x musenki
MVBLUE_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x mvblue
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x mvblue
OXC_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x oxc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x oxc
PN62_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x pn62
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x pn62
Sandpoint8240_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x sandpoint
Sandpoint8245_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x sandpoint
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x sandpoint
sbc8240_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x sbc8240
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x sbc8240
utx8245_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc824x utx8245
+ @$(MKCONFIG) $(@:_config=) powerpc mpc824x utx8245
#########################################################################
## MPC8260 Systems
#########################################################################
atc_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 atc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 atc
cogent_mpc8260_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 cogent
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 cogent
CPU86_config \
CPU86_ROMBOOT_config: unconfig
- @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc8260 cpu86
+ @$(MKCONFIG) $(call xtract_82xx,$@) powerpc mpc8260 cpu86
@cd $(obj)include ; \
if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
CPU87_config \
CPU87_ROMBOOT_config: unconfig
- @$(MKCONFIG) $(call xtract_82xx,$@) ppc mpc8260 cpu87
+ @$(MKCONFIG) $(call xtract_82xx,$@) powerpc mpc8260 cpu87
@cd $(obj)include ; \
if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
ep8248_config \
ep8248E_config : unconfig
- @$(MKCONFIG) ep8248 ppc mpc8260 ep8248
+ @$(MKCONFIG) ep8248 powerpc mpc8260 ep8248
ep8260_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 ep8260
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 ep8260
ep82xxm_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 ep82xxm
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 ep82xxm
gw8260_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 gw8260
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 gw8260
hymod_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 hymod
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 hymod
IDS8247_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 ids8247
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 ids8247
IPHASE4539_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 iphase4539
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 iphase4539
ISPAN_config \
ISPAN_REVB_config: unconfig
@if [ "$(findstring _REVB_,$@)" ] ; then \
echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \
fi
- @$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
+ @$(MKCONFIG) -a ISPAN powerpc mpc8260 ispan
mgcoge_config : unconfig
- @$(MKCONFIG) mgcoge ppc mpc8260 mgcoge keymile
+ @$(MKCONFIG) mgcoge powerpc mpc8260 mgcoge keymile
MPC8260ADS_config \
MPC8260ADS_lowboot_config \
{ echo "TEXT_BASE = 0xFF800000" >$(obj)board/freescale/mpc8260ads/config.tmp ; \
$(XECHO) "... with lowboot configuration" ; \
}
- @$(MKCONFIG) -a MPC8260ADS ppc mpc8260 mpc8260ads freescale
+ @$(MKCONFIG) -a MPC8260ADS powerpc mpc8260 mpc8260ads freescale
MPC8266ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 mpc8266ads freescale
muas3001_dev_config \
muas3001_config : unconfig
@if [ "$(findstring dev,$@)" ] ; then \
echo "#define CONFIG_MUAS_DEV_BOARD" > $(obj)include/config.h ; \
fi
- @$(MKCONFIG) -a muas3001 ppc mpc8260 muas3001
+ @$(MKCONFIG) -a muas3001 powerpc mpc8260 muas3001
# PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash
PM825_config \
echo "TEXT_BASE = 0xFF000000" >$(obj)board/pm826/config.tmp ; \
fi; \
fi
- @$(MKCONFIG) -a PM826 ppc mpc8260 pm826
+ @$(MKCONFIG) -a PM826 powerpc mpc8260 pm826
PM828_config \
PM828_PCI_config \
echo "#define CONFIG_BOOT_ROM" >>$(obj)include/config.h ; \
echo "TEXT_BASE = 0xFF800000" >$(obj)board/pm826/config.tmp ; \
fi
- @$(MKCONFIG) -a PM828 ppc mpc8260 pm828
+ @$(MKCONFIG) -a PM828 powerpc mpc8260 pm828
ppmc8260_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 ppmc8260
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 ppmc8260
Rattler8248_config \
Rattler_config: unconfig
@mkdir -p $(obj)include
$(if $(findstring 8248,$@), \
@echo "#define CONFIG_MPC8248" > $(obj)include/config.h)
- @$(MKCONFIG) -a Rattler ppc mpc8260 rattler
+ @$(MKCONFIG) -a Rattler powerpc mpc8260 rattler
RPXsuper_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 rpxsuper
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 rpxsuper
rsdproto_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 rsdproto
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 rsdproto
sacsng_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 sacsng
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 sacsng
sbc8260_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 sbc8260
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 sbc8260
SCM_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 SCM siemens
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 SCM siemens
TQM8255_AA_config \
TQM8260_AA_config \
echo "#undef CONFIG_BUSMODE_60x" >>$(obj)include/config.h ; \
$(XECHO) "... without 60x Bus Mode" ; \
fi
- @$(MKCONFIG) -a TQM8260 ppc mpc8260 tqm8260 tqc
+ @$(MKCONFIG) -a TQM8260 powerpc mpc8260 tqm8260 tqc
TQM8272_config: unconfig
- @$(MKCONFIG) TQM8272 ppc mpc8260 tqm8272 tqc
+ @$(MKCONFIG) TQM8272 powerpc mpc8260 tqm8272 tqc
VoVPN-GW_66MHz_config \
VoVPN-GW_100MHz_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > $(obj)include/config.h
- @$(MKCONFIG) -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk
+ @$(MKCONFIG) -a VoVPN-GW powerpc mpc8260 vovpn-gw funkwerk
ZPC1900_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc8260 zpc1900
+ @$(MKCONFIG) $(@:_config=) powerpc mpc8260 zpc1900
#########################################################################
## Coldfire
#########################################################################
kmeter1_config: unconfig
- @$(MKCONFIG) kmeter1 ppc mpc83xx kmeter1 keymile
+ @$(MKCONFIG) kmeter1 powerpc mpc83xx kmeter1 keymile
MPC8313ERDB_33_config \
MPC8313ERDB_66_config \
echo "TEXT_BASE = 0x00100000" > $(obj)board/freescale/mpc8313erdb/config.tmp ; \
echo "#define CONFIG_NAND_U_BOOT" >>$(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
+ @$(MKCONFIG) -a MPC8313ERDB powerpc mpc83xx mpc8313erdb freescale
@if [ "$(findstring _NAND_,$@)" ] ; then \
echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
fi ;
MPC8315ERDB_NAND_config \
MPC8315ERDB_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
+ @$(MKCONFIG) -t $(@:_config=) MPC8315ERDB powerpc mpc83xx mpc8315erdb freescale
MPC8323ERDB_config: unconfig
- @$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
+ @$(MKCONFIG) -a MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale
MPC832XEMDS_config \
MPC832XEMDS_HOST_33_config \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
+ @$(MKCONFIG) -a MPC832XEMDS powerpc mpc83xx mpc832xemds freescale
MPC8349EMDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale
+ @$(MKCONFIG) $(@:_config=) powerpc mpc83xx mpc8349emds freescale
MPC8349ITX_config \
MPC8349ITX_LOWBOOT_config \
@if [ "$(findstring LOWBOOT,$@)" ] ; then \
echo "TEXT_BASE = 0xFE000000" >$(obj)board/freescale/mpc8349itx/config.tmp ; \
fi
- @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
+ @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX powerpc mpc83xx mpc8349itx freescale
MPC8360EMDS_config \
MPC8360EMDS_HOST_33_config \
echo "#define CONFIG_PQ_MDS_PIB 1" >>$(obj)include/config.h ; \
echo "#define CONFIG_PQ_MDS_PIB_ATM 1" >>$(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
+ @$(MKCONFIG) -a MPC8360EMDS powerpc mpc83xx mpc8360emds freescale
MPC8360ERDK_33_config \
MPC8360ERDK_66_config \
$(XECHO) -n "... CLKIN 33MHz " ; \
echo "#define CONFIG_CLKIN_33MHZ" >>$(obj)include/config.h ;\
fi ;
- @$(MKCONFIG) -a MPC8360ERDK ppc mpc83xx mpc8360erdk freescale
+ @$(MKCONFIG) -a MPC8360ERDK powerpc mpc83xx mpc8360erdk freescale
MPC837XEMDS_config \
MPC837XEMDS_HOST_config: unconfig
$(XECHO) -n "... PCI HOST " ; \
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a MPC837XEMDS ppc mpc83xx mpc837xemds freescale
+ @$(MKCONFIG) -a MPC837XEMDS powerpc mpc83xx mpc837xemds freescale
MPC837XERDB_config: unconfig
- @$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale
+ @$(MKCONFIG) -a MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
MVBLM7_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 matrix_vision
+ @$(MKCONFIG) $(@:_config=) powerpc mpc83xx mvblm7 matrix_vision
sbc8349_config \
sbc8349_PCI_33_config \
sbc8349_PCI_66_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) sbc8349 ppc mpc83xx sbc8349
+ @$(MKCONFIG) -t $(@:_config=) sbc8349 powerpc mpc83xx sbc8349
SIMPC8313_LP_config \
SIMPC8313_SP_config: unconfig
$(XECHO) -n "...Small Page NAND..." ; \
echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \
fi ;
- @$(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon
+ @$(MKCONFIG) -a SIMPC8313 powerpc mpc83xx simpc8313 sheldon
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
TQM834x_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
+ @$(MKCONFIG) $(@:_config=) powerpc mpc83xx tqm834x tqc
caddy2_config \
vme8349_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
+ @$(MKCONFIG) -t $(@:_config=) vme8349 powerpc mpc83xx vme8349 esd
edb9301_config \
edb9302_config \
#########################################################################
ATUM8548_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx atum8548
MPC8536DS_NAND_config \
MPC8536DS_SDCARD_config \
MPC8536DS_SPIFLASH_config \
MPC8536DS_36BIT_config \
MPC8536DS_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
+ @$(MKCONFIG) -t $(@:_config=) MPC8536DS powerpc mpc85xx mpc8536ds freescale
MPC8540ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx mpc8540ads freescale
MPC8540EVAL_config \
MPC8540EVAL_33_config \
else \
$(XECHO) " host" ; \
fi
- @$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
+ @$(MKCONFIG) -a MPC8540EVAL powerpc mpc85xx mpc8540eval
MPC8560ADS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx mpc8560ads freescale
MPC8541CDS_legacy_config \
MPC8541CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
$(XECHO) "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale
+ @$(MKCONFIG) -a MPC8541CDS powerpc mpc85xx mpc8541cds freescale
MPC8544DS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx mpc8544ds freescale
MPC8548CDS_legacy_config \
MPC8548CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
$(XECHO) "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale
+ @$(MKCONFIG) -a MPC8548CDS powerpc mpc85xx mpc8548cds freescale
MPC8555CDS_legacy_config \
MPC8555CDS_config: unconfig
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
$(XECHO) "... legacy" ; \
fi
- @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale
+ @$(MKCONFIG) -a MPC8555CDS powerpc mpc85xx mpc8555cds freescale
MPC8568MDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx mpc8568mds freescale
MPC8569MDS_ATM_config \
MPC8569MDS_NAND_config \
MPC8569MDS_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) MPC8569MDS ppc mpc85xx mpc8569mds freescale
+ @$(MKCONFIG) -t $(@:_config=) MPC8569MDS powerpc mpc85xx mpc8569mds freescale
MPC8572DS_36BIT_config \
MPC8572DS_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) MPC8572DS ppc mpc85xx mpc8572ds freescale
+ @$(MKCONFIG) -t $(@:_config=) MPC8572DS powerpc mpc85xx mpc8572ds freescale
P2020DS_36BIT_config \
P2020DS_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale
+ @$(MKCONFIG) -t $(@:_config=) P2020DS powerpc mpc85xx p2020ds freescale
P1011RDB_config \
P1011RDB_NAND_config \
P2020RDB_NAND_config \
P2020RDB_SDCARD_config \
P2020RDB_SPIFLASH_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
+ @$(MKCONFIG) -t $(@:_config=) P1_P2_RDB powerpc mpc85xx p1_p2_rdb freescale
PM854_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx pm854
PM856_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm856
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx pm856
sbc8540_config \
sbc8540_33_config \
sbc8540_66_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) SBC8540 ppc mpc85xx sbc8560
+ @$(MKCONFIG) -t $(@:_config=) SBC8540 powerpc mpc85xx sbc8560
sbc8548_config \
sbc8548_PCI_33_config \
sbc8548_PCI_66_config \
sbc8548_PCI_33_PCIE_config \
sbc8548_PCI_66_PCIE_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) sbc8548 ppc mpc85xx sbc8548
+ @$(MKCONFIG) -t $(@:_config=) sbc8548 powerpc mpc85xx sbc8548
sbc8560_config \
sbc8560_33_config \
sbc8560_66_config: unconfig
- @$(MKCONFIG) -t $(@:_config=) sbc8560 ppc mpc85xx sbc8560
+ @$(MKCONFIG) -t $(@:_config=) sbc8560 powerpc mpc85xx sbc8560
socrates_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx socrates
stxgp3_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 stx
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx stxgp3 stx
stxssa_config \
stxssa_4M_config: unconfig
echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
$(XECHO) "... with 4 MiB flash memory" ; \
fi
- @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa stx
+ @$(MKCONFIG) -a stxssa powerpc mpc85xx stxssa stx
TQM8540_config \
TQM8541_config \
echo "#define CONFIG_$${BTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \
echo "#define CONFIG_BOARDNAME \"$${BTYPE}\"">>$(obj)include/config.h;
- @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc
+ @$(MKCONFIG) -a TQM85xx powerpc mpc85xx tqm85xx tqc
@echo "CONFIG_$(@:_config=) = y">>$(obj)include/config.mk;
XPEDITE5200_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5200 xes
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx xpedite5200 xes
XPEDITE5370_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx xpedite5370 xes
+ @$(MKCONFIG) $(@:_config=) powerpc mpc85xx xpedite5370 xes
#########################################################################
## MPC86xx Systems
#########################################################################
MPC8610HPCD_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8610hpcd freescale
+ @$(MKCONFIG) $(@:_config=) powerpc mpc86xx mpc8610hpcd freescale
MPC8641HPCN_36BIT_config \
MPC8641HPCN_config: unconfig
echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
$(XECHO) "... enabling 36-bit physical addressing." ; \
fi
- @$(MKCONFIG) -a MPC8641HPCN ppc mpc86xx mpc8641hpcn freescale
+ @$(MKCONFIG) -a MPC8641HPCN powerpc mpc86xx mpc8641hpcn freescale
sbc8641d_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc86xx sbc8641d
+ @$(MKCONFIG) $(@:_config=) powerpc mpc86xx sbc8641d
XPEDITE5170_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc86xx xpedite5170 xes
+ @$(MKCONFIG) $(@:_config=) powerpc mpc86xx xpedite5170 xes
#########################################################################
## 74xx/7xx Systems
#########################################################################
AmigaOneG3SE_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx AmigaOneG3SE MAI
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx AmigaOneG3SE MAI
BAB7xx_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx bab7xx eltec
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx bab7xx eltec
CPCI750_config: unconfig
- @$(MKCONFIG) CPCI750 ppc 74xx_7xx cpci750 esd
+ @$(MKCONFIG) CPCI750 powerpc 74xx_7xx cpci750 esd
DB64360_config: unconfig
- @$(MKCONFIG) DB64360 ppc 74xx_7xx db64360 Marvell
+ @$(MKCONFIG) DB64360 powerpc 74xx_7xx db64360 Marvell
DB64460_config: unconfig
- @$(MKCONFIG) DB64460 ppc 74xx_7xx db64460 Marvell
+ @$(MKCONFIG) DB64460 powerpc 74xx_7xx db64460 Marvell
ELPPC_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx elppc eltec
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx elppc eltec
EVB64260_config \
EVB64260_750CX_config: unconfig
- @$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
+ @$(MKCONFIG) EVB64260 powerpc 74xx_7xx evb64260
mpc7448hpc2_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2 freescale
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx mpc7448hpc2 freescale
P3G4_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx evb64260
p3m750_config \
p3m7448_config: unconfig
else \
echo "#define CONFIG_P3M7448" >>$(obj)include/config.h ; \
fi
- @$(MKCONFIG) -a p3mx ppc 74xx_7xx p3mx prodrive
+ @$(MKCONFIG) -a p3mx powerpc 74xx_7xx p3mx prodrive
PCIPPC2_config \
PCIPPC6_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx pcippc2
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx pcippc2
ppmc7xx_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx ppmc7xx
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx ppmc7xx
ZUMA_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
+ @$(MKCONFIG) $(@:_config=) powerpc 74xx_7xx evb64260
#========================================================================
# ARM
PCI5441_config : unconfig
@$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent
+# nios2 generic boards
+NIOS2_GENERIC = nios2-generic
+
+$(NIOS2_GENERIC:%=%_config) : unconfig
+ @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
+
#========================================================================
## Microblaze
#========================================================================
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.imx
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
- @rm -f $(obj)arch/ppc/cpu/mpc824x/bedbug_603e.c
+ @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
/nios2 Files generic to Altera NIOS2 architecture
/cpu CPU specific files
/lib Architecture specific library files
- /ppc Files generic to PowerPC architecture
+ /powerpc Files generic to PowerPC architecture
/cpu CPU specific files
/74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs
/mpc5xx Files specific to Freescale MPC5xx CPUs
the CPU's i2c node address).
Now, the u-boot i2c code for the mpc8xx
- (arch/ppc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
+ (arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node
and so its address should therefore be cleared to 0 (See,
eg, MPC823e User's Manual p.16-473). So, set
CONFIG_SYS_I2C_SLAVE to 0.
custom i2c_init_board() routine in boards/xxx/board.c
is run early in the boot sequence.
+ CONFIG_SYS_I2C_BOARD_LATE_INIT
+
+ An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is
+ defined a custom i2c_board_late_init() routine in
+ boards/xxx/board.c is run AFTER the operations in i2c_init()
+ is completed. This callpoint can be used to unreset i2c bus
+ using CPU i2c controller register accesses for CPUs whose i2c
+ controller provide such a method. It is called at the end of
+ i2c_init() to allow i2c_init operations to setup the i2c bus
+ controller on the CPU (e.g. setting bus speed & slave address).
+
CONFIG_I2CFAST (PPC405GP|PPC405EP only)
This option enables configuration of bi_iic_fast[] flags
15 arch/<arch>/lib/bootm.c All preparation done, transferring control to OS
- -30 arch/ppc/lib/board.c Fatal error, hang the system
+ -30 arch/powerpc/lib/board.c Fatal error, hang the system
-31 post/post.c POST test failed, detected by post_output_backlog()
-32 post/post.c POST test failed, detected by post_run_single()
CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL,
CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE,
CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
- Overrides the default PCI memory map in arch/ppc/cpu/mpc8260/pci.c if set.
+ Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set.
- CONFIG_PCI_DISABLE_PCIE:
Disable PCI-Express on systems where it is supported but not
(no, we don't intend to provide a full virtual machine interface to
Linux :-).
-But now you can ignore ALL boot loader code (in arch/ppc/mbxboot).
+But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot).
Just make sure your machine specific header file (for instance
include/asm-ppc/tqm8xx.h) includes the same definition of the Board
-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
> -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \
- > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \
+ > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \
> examples/uImage.TQM850L
Image Name: 2.4.4 kernel for TQM850L
Created: Wed Jul 19 02:34:59 2000
needs more space in Flash, but boots much faster since it does not
need to be uncompressed:
- -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz
+ -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz
-> tools/mkimage -n '2.4.4 kernel for TQM850L' \
> -A ppc -O linux -T kernel -C none -a 0 -e 0 \
- > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \
+ > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \
> examples/uImage.TQM850L-uncompressed
Image Name: 2.4.4 kernel for TQM850L
Created: Wed Jul 19 02:34:59 2000
#define MACH_TYPE_SKAT91_S3E 2790
#define MACH_TYPE_OMAP4_PANDA 2791
#define MACH_TYPE_DF7220 2792
+#define MACH_TYPE_NEMINI 2793
+#define MACH_TYPE_T8200 2794
+#define MACH_TYPE_APF51 2795
+#define MACH_TYPE_DR_RC_UNIT 2796
+#define MACH_TYPE_BORDEAUX 2797
+#define MACH_TYPE_CATANIA_B 2798
+#define MACH_TYPE_MX51_OCEAN 2799
+#define MACH_TYPE_TI8168EVM 2800
+#define MACH_TYPE_NEOCOREOMAP 2801
+#define MACH_TYPE_WITHINGS_WBP 2802
+#define MACH_TYPE_DBPS 2803
+#define MACH_TYPE_SBC9261 2804
+#define MACH_TYPE_PCBFP0001 2805
+#define MACH_TYPE_SPEEDY 2806
+#define MACH_TYPE_CHRYSAOR 2807
+#define MACH_TYPE_TANGO 2808
+#define MACH_TYPE_SYNOLOGY_DSX11 2809
+#define MACH_TYPE_HANLIN_V3EXT 2810
+#define MACH_TYPE_HANLIN_V5 2811
+#define MACH_TYPE_HANLIN_V3PLUS 2812
+#define MACH_TYPE_IRIVER_STORY 2813
+#define MACH_TYPE_IREX_ILIAD 2814
+#define MACH_TYPE_IREX_DR1000 2815
+#define MACH_TYPE_TETON_BGA 2816
+#define MACH_TYPE_SNAPPER9G45 2817
+#define MACH_TYPE_TAM3517 2818
+#define MACH_TYPE_PDC100 2819
+#define MACH_TYPE_EUKREA_CPUIMX25 2820
+#define MACH_TYPE_EUKREA_CPUIMX35 2821
+#define MACH_TYPE_EUKREA_CPUIMX51SD 2822
+#define MACH_TYPE_EUKREA_CPUIMX51 2823
+#define MACH_TYPE_P565 2824
+#define MACH_TYPE_ACER_A4 2825
+#define MACH_TYPE_DAVINCI_DM368_BIP 2826
+#define MACH_TYPE_ESHARE 2827
+#define MACH_TYPE_HW_OMAPL138_EUROPA 2828
+#define MACH_TYPE_WLBARGN 2829
+#define MACH_TYPE_BM170 2830
+#define MACH_TYPE_NETSPACE_MINI_V2 2831
+#define MACH_TYPE_NETSPACE_PLUG_V2 2832
+#define MACH_TYPE_SIEMENS_L1 2833
+#define MACH_TYPE_ELV_LCU1 2834
+#define MACH_TYPE_MCU1 2835
+#define MACH_TYPE_OMAP3_TAO3530 2836
+#define MACH_TYPE_OMAP3_PCUTOUCH 2837
+#define MACH_TYPE_SMDKC210 2838
+#define MACH_TYPE_OMAP3_BRAILLO 2839
+#define MACH_TYPE_SPYPLUG 2840
+#define MACH_TYPE_GINGER 2841
+#define MACH_TYPE_TNY_T3530 2842
+#define MACH_TYPE_PCA102 2843
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# else
# define machine_arch_type MACH_TYPE_DAVINCI_CIO
# endif
-# define machine_is_davinci_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO)
+# define machine_is_davinci_dm6467_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO)
#else
-# define machine_is_davinci_cio() (0)
+# define machine_is_davinci_dm6467_cio() (0)
#endif
#ifdef CONFIG_MACH_SMARTMETER_DL
# define machine_is_df7220() (0)
#endif
+#ifdef CONFIG_MACH_NEMINI
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NEMINI
+# endif
+# define machine_is_nemini() (machine_arch_type == MACH_TYPE_NEMINI)
+#else
+# define machine_is_nemini() (0)
+#endif
+
+#ifdef CONFIG_MACH_T8200
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_T8200
+# endif
+# define machine_is_t8200() (machine_arch_type == MACH_TYPE_T8200)
+#else
+# define machine_is_t8200() (0)
+#endif
+
+#ifdef CONFIG_MACH_APF51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_APF51
+# endif
+# define machine_is_apf51() (machine_arch_type == MACH_TYPE_APF51)
+#else
+# define machine_is_apf51() (0)
+#endif
+
+#ifdef CONFIG_MACH_DR_RC_UNIT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DR_RC_UNIT
+# endif
+# define machine_is_dr_rc_unit() (machine_arch_type == MACH_TYPE_DR_RC_UNIT)
+#else
+# define machine_is_dr_rc_unit() (0)
+#endif
+
+#ifdef CONFIG_MACH_BORDEAUX
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BORDEAUX
+# endif
+# define machine_is_bordeaux() (machine_arch_type == MACH_TYPE_BORDEAUX)
+#else
+# define machine_is_bordeaux() (0)
+#endif
+
+#ifdef CONFIG_MACH_CATANIA_B
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CATANIA_B
+# endif
+# define machine_is_catania_b() (machine_arch_type == MACH_TYPE_CATANIA_B)
+#else
+# define machine_is_catania_b() (0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_OCEAN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MX51_OCEAN
+# endif
+# define machine_is_mx51_ocean() (machine_arch_type == MACH_TYPE_MX51_OCEAN)
+#else
+# define machine_is_mx51_ocean() (0)
+#endif
+
+#ifdef CONFIG_MACH_TI8168EVM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TI8168EVM
+# endif
+# define machine_is_ti8168evm() (machine_arch_type == MACH_TYPE_TI8168EVM)
+#else
+# define machine_is_ti8168evm() (0)
+#endif
+
+#ifdef CONFIG_MACH_NEOCOREOMAP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NEOCOREOMAP
+# endif
+# define machine_is_neocoreomap() (machine_arch_type == MACH_TYPE_NEOCOREOMAP)
+#else
+# define machine_is_neocoreomap() (0)
+#endif
+
+#ifdef CONFIG_MACH_WITHINGS_WBP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WITHINGS_WBP
+# endif
+# define machine_is_withings_wbp() (machine_arch_type == MACH_TYPE_WITHINGS_WBP)
+#else
+# define machine_is_withings_wbp() (0)
+#endif
+
+#ifdef CONFIG_MACH_DBPS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DBPS
+# endif
+# define machine_is_dbps() (machine_arch_type == MACH_TYPE_DBPS)
+#else
+# define machine_is_dbps() (0)
+#endif
+
+#ifdef CONFIG_MACH_SBC9261
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SBC9261
+# endif
+# define machine_is_at91sam9261() (machine_arch_type == MACH_TYPE_SBC9261)
+#else
+# define machine_is_at91sam9261() (0)
+#endif
+
+#ifdef CONFIG_MACH_PCBFP0001
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PCBFP0001
+# endif
+# define machine_is_pcbfp0001() (machine_arch_type == MACH_TYPE_PCBFP0001)
+#else
+# define machine_is_pcbfp0001() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPEEDY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPEEDY
+# endif
+# define machine_is_speedy() (machine_arch_type == MACH_TYPE_SPEEDY)
+#else
+# define machine_is_speedy() (0)
+#endif
+
+#ifdef CONFIG_MACH_CHRYSAOR
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_CHRYSAOR
+# endif
+# define machine_is_chrysaor() (machine_arch_type == MACH_TYPE_CHRYSAOR)
+#else
+# define machine_is_chrysaor() (0)
+#endif
+
+#ifdef CONFIG_MACH_TANGO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TANGO
+# endif
+# define machine_is_tango() (machine_arch_type == MACH_TYPE_TANGO)
+#else
+# define machine_is_tango() (0)
+#endif
+
+#ifdef CONFIG_MACH_SYNOLOGY_DSX11
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SYNOLOGY_DSX11
+# endif
+# define machine_is_synology_dsx11() (machine_arch_type == MACH_TYPE_SYNOLOGY_DSX11)
+#else
+# define machine_is_synology_dsx11() (0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V3EXT
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HANLIN_V3EXT
+# endif
+# define machine_is_hanlin_v3ext() (machine_arch_type == MACH_TYPE_HANLIN_V3EXT)
+#else
+# define machine_is_hanlin_v3ext() (0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V5
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HANLIN_V5
+# endif
+# define machine_is_hanlin_v5() (machine_arch_type == MACH_TYPE_HANLIN_V5)
+#else
+# define machine_is_hanlin_v5() (0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V3PLUS
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HANLIN_V3PLUS
+# endif
+# define machine_is_hanlin_v3plus() (machine_arch_type == MACH_TYPE_HANLIN_V3PLUS)
+#else
+# define machine_is_hanlin_v3plus() (0)
+#endif
+
+#ifdef CONFIG_MACH_IRIVER_STORY
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IRIVER_STORY
+# endif
+# define machine_is_iriver_story() (machine_arch_type == MACH_TYPE_IRIVER_STORY)
+#else
+# define machine_is_iriver_story() (0)
+#endif
+
+#ifdef CONFIG_MACH_IREX_ILIAD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IREX_ILIAD
+# endif
+# define machine_is_irex_iliad() (machine_arch_type == MACH_TYPE_IREX_ILIAD)
+#else
+# define machine_is_irex_iliad() (0)
+#endif
+
+#ifdef CONFIG_MACH_IREX_DR1000
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_IREX_DR1000
+# endif
+# define machine_is_irex_dr1000() (machine_arch_type == MACH_TYPE_IREX_DR1000)
+#else
+# define machine_is_irex_dr1000() (0)
+#endif
+
+#ifdef CONFIG_MACH_TETON_BGA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TETON_BGA
+# endif
+# define machine_is_teton_bga() (machine_arch_type == MACH_TYPE_TETON_BGA)
+#else
+# define machine_is_teton_bga() (0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPER9G45
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SNAPPER9G45
+# endif
+# define machine_is_snapper9g45() (machine_arch_type == MACH_TYPE_SNAPPER9G45)
+#else
+# define machine_is_snapper9g45() (0)
+#endif
+
+#ifdef CONFIG_MACH_TAM3517
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TAM3517
+# endif
+# define machine_is_tam3517() (machine_arch_type == MACH_TYPE_TAM3517)
+#else
+# define machine_is_tam3517() (0)
+#endif
+
+#ifdef CONFIG_MACH_PDC100
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PDC100
+# endif
+# define machine_is_pdc100() (machine_arch_type == MACH_TYPE_PDC100)
+#else
+# define machine_is_pdc100() (0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX25
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX25
+# endif
+# define machine_is_eukrea_cpuimx25sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX25)
+#else
+# define machine_is_eukrea_cpuimx25sd() (0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX35
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX35
+# endif
+# define machine_is_eukrea_cpuimx35sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX35)
+#else
+# define machine_is_eukrea_cpuimx35sd() (0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX51SD
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51SD
+# endif
+# define machine_is_eukrea_cpuimx51sd() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51SD)
+#else
+# define machine_is_eukrea_cpuimx51sd() (0)
+#endif
+
+#ifdef CONFIG_MACH_EUKREA_CPUIMX51
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX51
+# endif
+# define machine_is_eukrea_cpuimx51() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX51)
+#else
+# define machine_is_eukrea_cpuimx51() (0)
+#endif
+
+#ifdef CONFIG_MACH_P565
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_P565
+# endif
+# define machine_is_p565() (machine_arch_type == MACH_TYPE_P565)
+#else
+# define machine_is_p565() (0)
+#endif
+
+#ifdef CONFIG_MACH_ACER_A4
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ACER_A4
+# endif
+# define machine_is_acer_a4() (machine_arch_type == MACH_TYPE_ACER_A4)
+#else
+# define machine_is_acer_a4() (0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM368_BIP
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_DAVINCI_DM368_BIP
+# endif
+# define machine_is_davinci_dm368_bip() (machine_arch_type == MACH_TYPE_DAVINCI_DM368_BIP)
+#else
+# define machine_is_davinci_dm368_bip() (0)
+#endif
+
+#ifdef CONFIG_MACH_ESHARE
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ESHARE
+# endif
+# define machine_is_eshare() (machine_arch_type == MACH_TYPE_ESHARE)
+#else
+# define machine_is_eshare() (0)
+#endif
+
+#ifdef CONFIG_MACH_HW_OMAPL138_EUROPA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_HW_OMAPL138_EUROPA
+# endif
+# define machine_is_hw_omapl138_europa() (machine_arch_type == MACH_TYPE_HW_OMAPL138_EUROPA)
+#else
+# define machine_is_hw_omapl138_europa() (0)
+#endif
+
+#ifdef CONFIG_MACH_WLBARGN
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_WLBARGN
+# endif
+# define machine_is_wlbargn() (machine_arch_type == MACH_TYPE_WLBARGN)
+#else
+# define machine_is_wlbargn() (0)
+#endif
+
+#ifdef CONFIG_MACH_BM170
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_BM170
+# endif
+# define machine_is_bm170() (machine_arch_type == MACH_TYPE_BM170)
+#else
+# define machine_is_bm170() (0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_MINI_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NETSPACE_MINI_V2
+# endif
+# define machine_is_netspace_mini_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MINI_V2)
+#else
+# define machine_is_netspace_mini_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_NETSPACE_PLUG_V2
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_NETSPACE_PLUG_V2
+# endif
+# define machine_is_netspace_plug_v2() (machine_arch_type == MACH_TYPE_NETSPACE_PLUG_V2)
+#else
+# define machine_is_netspace_plug_v2() (0)
+#endif
+
+#ifdef CONFIG_MACH_SIEMENS_L1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SIEMENS_L1
+# endif
+# define machine_is_siemens_l1() (machine_arch_type == MACH_TYPE_SIEMENS_L1)
+#else
+# define machine_is_siemens_l1() (0)
+#endif
+
+#ifdef CONFIG_MACH_ELV_LCU1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ELV_LCU1
+# endif
+# define machine_is_elv_lcu1() (machine_arch_type == MACH_TYPE_ELV_LCU1)
+#else
+# define machine_is_elv_lcu1() (0)
+#endif
+
+#ifdef CONFIG_MACH_MCU1
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MCU1
+# endif
+# define machine_is_mcu1() (machine_arch_type == MACH_TYPE_MCU1)
+#else
+# define machine_is_mcu1() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_TAO3530
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_TAO3530
+# endif
+# define machine_is_omap3_tao3530() (machine_arch_type == MACH_TYPE_OMAP3_TAO3530)
+#else
+# define machine_is_omap3_tao3530() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_PCUTOUCH
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_PCUTOUCH
+# endif
+# define machine_is_omap3_pcutouch() (machine_arch_type == MACH_TYPE_OMAP3_PCUTOUCH)
+#else
+# define machine_is_omap3_pcutouch() (0)
+#endif
+
+#ifdef CONFIG_MACH_SMDKC210
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SMDKC210
+# endif
+# define machine_is_smdkc210() (machine_arch_type == MACH_TYPE_SMDKC210)
+#else
+# define machine_is_smdkc210() (0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_BRAILLO
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP3_BRAILLO
+# endif
+# define machine_is_omap3_braillo() (machine_arch_type == MACH_TYPE_OMAP3_BRAILLO)
+#else
+# define machine_is_omap3_braillo() (0)
+#endif
+
+#ifdef CONFIG_MACH_SPYPLUG
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_SPYPLUG
+# endif
+# define machine_is_spyplug() (machine_arch_type == MACH_TYPE_SPYPLUG)
+#else
+# define machine_is_spyplug() (0)
+#endif
+
+#ifdef CONFIG_MACH_GINGER
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_GINGER
+# endif
+# define machine_is_ginger() (machine_arch_type == MACH_TYPE_GINGER)
+#else
+# define machine_is_ginger() (0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_T3530
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_TNY_T3530
+# endif
+# define machine_is_tny_t3530() (machine_arch_type == MACH_TYPE_TNY_T3530)
+#else
+# define machine_is_tny_t3530() (0)
+#endif
+
+#ifdef CONFIG_MACH_PCA102
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_PCA102
+# endif
+# define machine_is_pca102() (machine_arch_type == MACH_TYPE_PCA102)
+#else
+# define machine_is_pca102() (0)
+#endif
+
/*
* These have not yet been registered
*/
}
void icache_disable(void) {
+ /* we are not generate ICACHE size -> flush whole cache */
+ flush_cache(0, 32768);
MSRCLR(0x20);
}
}
void dcache_disable(void) {
+#ifdef XILINX_USE_DCACHE
+#ifdef XILINX_DCACHE_BYTE_SIZE
+ flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+#else
+#warning please rebuild BSPs and update configuration
+ flush_cache(0, 32768);
+#endif
+#endif
MSRCLR(0x80);
}
+
+void flush_cache (ulong addr, ulong size)
+{
+ int i;
+ for (i = 0; i < size; i += 4)
+ asm volatile (
+#ifdef CONFIG_ICACHE
+ "wic %0, r0;"
+#endif
+ "nop;"
+#ifdef CONFIG_DCACHE
+ "wdc.flush %0, r0;"
+#endif
+ "nop;"
+ :
+ : "r" (addr + i)
+ : "memory");
+}
}
#ifdef CONFIG_SYS_INTC_0
-#ifdef CONFIG_SYS_TIMER_0
-extern void timer_init (void);
-#endif
-#ifdef CONFIG_SYS_FSL_2
-extern void fsl_init2 (void);
-#endif
-
static struct irq_action vecs[CONFIG_SYS_INTC_0_NUM];
}
/* initialize intc controller */
intc_init ();
-#ifdef CONFIG_SYS_TIMER_0
- timer_init ();
-#endif
-#ifdef CONFIG_SYS_FSL_2
- fsl_init2 ();
-#endif
enable_interrupts ();
return 0;
}
void interrupt_handler (void)
{
- int irqs = (intc->isr & intc->ier); /* find active interrupt */
- int i = 1;
+ int irqs = intc->ivr; /* find active interrupt */
+ int mask = 1;
#ifdef DEBUG_INT
int value;
printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
R14(value);
printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
#endif
- struct irq_action *act = vecs;
- while (irqs) {
- if (irqs & 1) {
+ struct irq_action *act = vecs + irqs;
+
+ intc->iar = mask << irqs;
+
#ifdef DEBUG_INT
- printf
- ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
- act->handler, act->count, act->arg);
+ printf
+ ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
+ act->handler, act->count, act->arg);
#endif
- act->handler (act->arg);
- act->count++;
- intc->iar = i;
- return;
- }
- irqs >>= 1;
- act++;
- i <<= 1;
- }
+ act->handler (act->arg);
+ act->count++;
#ifdef DEBUG_INT
printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
.text
.global _interrupt_handler
_interrupt_handler:
- addi r1, r1, -4
- swi r2, r1, 0
- addi r1, r1, -4
- swi r3, r1, 0
- addi r1, r1, -4
- swi r4, r1, 0
- addi r1, r1, -4
- swi r5, r1, 0
- addi r1, r1, -4
- swi r6, r1, 0
- addi r1, r1, -4
- swi r7, r1, 0
- addi r1, r1, -4
- swi r8, r1, 0
- addi r1, r1, -4
- swi r9, r1, 0
- addi r1, r1, -4
- swi r10, r1, 0
- addi r1, r1, -4
- swi r11, r1, 0
- addi r1, r1, -4
- swi r12, r1, 0
- addi r1, r1, -4
- swi r13, r1, 0
- addi r1, r1, -4
- swi r14, r1, 0
- addi r1, r1, -4
- swi r15, r1, 0
- addi r1, r1, -4
- swi r16, r1, 0
- addi r1, r1, -4
- swi r17, r1, 0
- addi r1, r1, -4
- swi r18, r1, 0
- addi r1, r1, -4
- swi r19, r1, 0
- addi r1, r1, -4
- swi r20, r1, 0
- addi r1, r1, -4
- swi r21, r1, 0
- addi r1, r1, -4
- swi r22, r1, 0
- addi r1, r1, -4
- swi r23, r1, 0
- addi r1, r1, -4
- swi r24, r1, 0
- addi r1, r1, -4
- swi r25, r1, 0
- addi r1, r1, -4
- swi r26, r1, 0
- addi r1, r1, -4
- swi r27, r1, 0
- addi r1, r1, -4
- swi r28, r1, 0
- addi r1, r1, -4
- swi r29, r1, 0
- addi r1, r1, -4
- swi r30, r1, 0
- addi r1, r1, -4
- swi r31, r1, 0
+ swi r2, r1, -4
+ swi r3, r1, -8
+ swi r4, r1, -12
+ swi r5, r1, -16
+ swi r6, r1, -20
+ swi r7, r1, -24
+ swi r8, r1, -28
+ swi r9, r1, -32
+ swi r10, r1, -36
+ swi r11, r1, -40
+ swi r12, r1, -44
+ swi r13, r1, -48
+ swi r14, r1, -52
+ swi r15, r1, -56
+ swi r16, r1, -60
+ swi r17, r1, -64
+ swi r18, r1, -68
+ swi r19, r1, -72
+ swi r20, r1, -76
+ swi r21, r1, -80
+ swi r22, r1, -84
+ swi r23, r1, -88
+ swi r24, r1, -92
+ swi r25, r1, -96
+ swi r26, r1, -100
+ swi r27, r1, -104
+ swi r28, r1, -108
+ swi r29, r1, -112
+ swi r30, r1, -116
+ swi r31, r1, -120
+ addik r1, r1, -124
brlid r15, interrupt_handler
nop
nop
- lwi r31, r1, 0
- addi r1, r1, 4
- lwi r30, r1, 0
- addi r1, r1, 4
- lwi r29, r1, 0
- addi r1, r1, 4
- lwi r28, r1, 0
- addi r1, r1, 4
- lwi r27, r1, 0
- addi r1, r1, 4
- lwi r26, r1, 0
- addi r1, r1, 4
- lwi r25, r1, 0
- addi r1, r1, 4
- lwi r24, r1, 0
- addi r1, r1, 4
- lwi r23, r1, 0
- addi r1, r1, 4
- lwi r22, r1, 0
- addi r1, r1, 4
- lwi r21, r1, 0
- addi r1, r1, 4
- lwi r20, r1, 0
- addi r1, r1, 4
- lwi r19, r1, 0
- addi r1, r1, 4
- lwi r18, r1, 0
- addi r1, r1, 4
- lwi r17, r1, 0
- addi r1, r1, 4
- lwi r16, r1, 0
- addi r1, r1, 4
- lwi r15, r1, 0
- addi r1, r1, 4
- lwi r14, r1, 0
- addi r1, r1, 4
- lwi r13, r1, 0
- addi r1, r1, 4
- lwi r12, r1, 0
- addi r1, r1, 4
- lwi r11, r1, 0
- addi r1, r1, 4
- lwi r10, r1, 0
- addi r1, r1, 4
- lwi r9, r1, 0
- addi r1, r1, 4
- lwi r8, r1, 0
- addi r1, r1, 4
- lwi r7, r1, 0
- addi r1, r1, 4
- lwi r6, r1, 0
- addi r1, r1, 4
- lwi r5, r1, 0
- addi r1, r1, 4
- lwi r4, r1, 0
- addi r1, r1, 4
- lwi r3, r1, 0
- addi r1, r1, 4
- lwi r2, r1, 0
- addi r1, r1, 4
+ addik r1, r1, 124
+ lwi r31, r1, -120
+ lwi r30, r1, -116
+ lwi r29, r1, -112
+ lwi r28, r1, -108
+ lwi r27, r1, -104
+ lwi r26, r1, -100
+ lwi r25, r1, -96
+ lwi r24, r1, -92
+ lwi r23, r1, -88
+ lwi r22, r1, -84
+ lwi r21, r1, -80
+ lwi r20, r1, -76
+ lwi r19, r1, -72
+ lwi r18, r1, -68
+ lwi r17, r1, -64
+ lwi r16, r1, -60
+ lwi r15, r1, -56
+ lwi r14, r1, -52
+ lwi r13, r1, -48
+ lwi r12, r1, -44
+ lwi r11, r1, -40
+ lwi r10, r1, -36
+ lwi r9, r1, -32
+ lwi r8, r1, -28
+ lwi r7, r1, -24
+ lwi r6, r1, -20
+ lwi r5, r1, -16
+ lwi r4, r1, -12
+ lwi r3, r1, -8
+ lwi r2, r1, -4
/* enable_interrupt */
#ifdef XILINX_USE_MSR_INSTR
tmr->control = tmr->control | TIMER_INTERRUPT;
}
-void timer_init (void)
+int timer_init (void)
{
tmr->loadreg = CONFIG_SYS_TIMER_0_PRELOAD;
tmr->control = TIMER_INTERRUPT | TIMER_RESET;
TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
reset_timer ();
install_interrupt_handler (CONFIG_SYS_TIMER_0_IRQ, timer_isr, (void *)tmr);
+ return 0;
}
#endif
#endif
COBJS-y += board.o
COBJS-y += bootm.o
-COBJS-y += cache.o
COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
#include <timestamp.h>
#include <version.h>
#include <watchdog.h>
+#include <stdio_dev.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET)
extern int eth_init (bd_t * bis);
#endif
+#ifdef CONFIG_SYS_TIMER_0
+extern int timer_init (void);
+#endif
+#ifdef CONFIG_SYS_FSL_2
+extern void fsl_init2 (void);
+#endif
/*
* All attempts to come up with a "common" initialization sequence
#endif
#ifdef CONFIG_SYS_INTC_0
interrupts_init,
+#endif
+#ifdef CONFIG_SYS_TIMER_0
+ timer_init,
+#endif
+#ifdef CONFIG_SYS_FSL_2
+ fsl_init2,
#endif
NULL,
};
bd_t *bd;
init_fnc_t **init_fnc_ptr;
gd = (gd_t *) CONFIG_SYS_GBL_DATA_OFFSET;
+ char *s;
#if defined(CONFIG_CMD_FLASH)
ulong flash_size = 0;
#endif
}
puts ("SDRAM :\n");
- printf ("\t\tIcache:%s\n", icache_status() ? "OK" : "FAIL");
- printf ("\t\tDcache:%s\n", dcache_status() ? "OK" : "FAIL");
+ printf ("\t\tIcache:%s\n", icache_status() ? "ON" : "OFF");
+ printf ("\t\tDcache:%s\n", dcache_status() ? "ON" : "OFF");
printf ("\tU-Boot Start:0x%08x\n", TEXT_BASE);
#if defined(CONFIG_CMD_FLASH)
}
#endif
+ /* relocate environment function pointers etc. */
+ env_relocate ();
+
+ /* Initialize stdio devices */
+ stdio_init ();
+
+ if ((s = getenv ("loadaddr")) != NULL) {
+ load_addr = simple_strtoul (s, NULL, 16);
+ }
+
#if defined(CONFIG_CMD_NET)
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
eth_init (bd);
#endif
- /* relocate environment function pointers etc. */
- env_relocate ();
-
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
/* First parameter is mapped to $r5 for kernel boot args */
- void (*theKernel) (char *);
+ void (*theKernel) (char *, ulong, ulong);
char *commandline = getenv ("bootargs");
+ ulong rd_data_start, rd_data_end;
if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
return 1;
- theKernel = (void (*)(char *))images->ep;
+ int ret;
+
+ char *of_flat_tree = NULL;
+#if defined(CONFIG_OF_LIBFDT)
+ ulong of_size = 0;
+
+ /* find flattened device tree */
+ ret = boot_get_fdt (flag, argc, argv, images, &of_flat_tree, &of_size);
+ if (ret)
+ return 1;
+#endif
+
+ theKernel = (void (*)(char *, ulong, ulong))images->ep;
+
+ /* find ramdisk */
+ ret = boot_get_ramdisk (argc, argv, images, IH_ARCH_MICROBLAZE,
+ &rd_data_start, &rd_data_end);
+ if (ret)
+ return 1;
show_boot_progress (15);
+ if (!(ulong) of_flat_tree)
+ of_flat_tree = (char *)simple_strtoul (argv[3], NULL, 16);
+
#ifdef DEBUG
- printf ("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong) theKernel);
+ printf ("## Transferring control to Linux (at address 0x%08lx) " \
+ "ramdisk 0x%08lx, FDT 0x%08lx...\n",
+ (ulong) theKernel, rd_data_start, (ulong) of_flat_tree);
#endif
- theKernel (commandline);
+#ifdef XILINX_USE_DCACHE
+#ifdef XILINX_DCACHE_BYTE_SIZE
+ flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
+#else
+#warning please rebuild BSPs and update configuration
+ flush_cache(0, 32768);
+#endif
+#endif
+ /*
+ * Linux Kernel Parameters (passing device tree):
+ * r5: pointer to command line
+ * r6: pointer to ramdisk
+ * r7: pointer to the fdt, followed by the board info data
+ */
+ theKernel (commandline, rd_data_start, (ulong) of_flat_tree);
/* does not return */
return 1;
PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
PLATFORM_CPPFLAGS += -ffixed-r15 -G0
+
+LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
.global _start
_start:
+ wrctl status, r0 /* Disable interrupts */
/* ICACHE INIT -- only the icache line at the reset address
* is invalidated at reset. So the init must stay within
* the cache line size (8 words). If GERMS is used, we'll
ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE)
ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
- mov r6, r0
-0: initi r6
- add r6, r6, r4
- bltu r6, r5, 0b
+0: initi r5
+ sub r5, r5, r4
+ bgt r5, r0, 0b
br _except_end /* Skip the tramp */
/* EXCEPTION TRAMPOLINE -- the following gets copied
/* INTERRUPTS -- for now, all interrupts masked and globally
* disabled.
*/
- wrctl status, r0 /* Disable interrupts */
wrctl ienable, r0 /* All disabled */
/* DCACHE INIT -- if dcache not implemented, initd behaves as
{
.text :
{
- arch/nios/cpu2/start.o (.text)
+ arch/nios2/cpu/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
#define __ASM_NIOS2_BYTEORDER_H_
#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
#include <linux/byteorder/little_endian.h>
#endif /* __ASM_NIOS2_BYTEORDER_H_ */
--- /dev/null
+#ifndef __ASM_NIOS2_DMA_MAPPING_H
+#define __ASM_NIOS2_DMA_MAPPING_H
+
+/* dma_alloc_coherent() return cache-line aligned allocation which is mapped
+ * to uncached io region.
+ *
+ * IO_REGION_BASE should be defined in board config header file
+ * 0x80000000 for nommu, 0xe0000000 for mmu
+ */
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE);
+ if (!addr)
+ return 0;
+ flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE);
+ *handle = ((unsigned long)addr +
+ (CONFIG_SYS_DCACHELINE_SIZE - 1)) &
+ ~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE);
+ return (void *)(*handle | IO_REGION_BASE);
+}
+
+#endif /* __ASM_NIOS2_DMA_MAPPING_H */
#include <stdio_dev.h>
#include <watchdog.h>
#include <malloc.h>
+#include <mmc.h>
#include <net.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#if defined(CONFIG_SYS_NIOS_EPCSBASE)
#include <nios2-epcs.h>
#endif
+#ifdef CONFIG_CMD_NAND
+#include <nand.h> /* cannot even include nand.h if it isnt configured */
+#endif
DECLARE_GLOBAL_DATA_PTR;
bd = gd->bd;
bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_SYS_NO_FLASH
bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#endif
#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
/* The Malloc area is immediately below the monitor copy in RAM */
mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
+#ifndef CONFIG_SYS_NO_FLASH
WATCHDOG_RESET ();
bd->bi_flashsize = flash_init();
+#endif
+
+#ifdef CONFIG_CMD_NAND
+ puts("NAND: ");
+ nand_init();
+#endif
+
+#ifdef CONFIG_GENERIC_MMC
+ puts("MMC: ");
+ mmc_initialize(bd);
+#endif
WATCHDOG_RESET ();
env_relocate();
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
START = start.o
COBJS-y := cpu.o
COBJS-y += traps.o
+COBJS-y += common.o
COBJS-y += cpu_init.o
COBJS-y += fixed_sdram.o
COBJS-y += i2c.o
/*
- * needed for arch/ppc/cpu/mpc512x/start.S
+ * needed for arch/powerpc/cpu/mpc512x/start.S
*
* These should be auto-generated
*/
--- /dev/null
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
+
+#if defined(CONFIG_SYS_POST_WORD_ADDR)
+# define _POST_ADDR (CONFIG_SYS_POST_WORD_ADDR)
+#else
+#error echo "No POST word address defined"
+#endif
+
+void post_word_store(ulong a)
+{
+ volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+ out_be32(save_addr, a);
+}
+
+ulong post_word_load(void)
+{
+ volatile void *save_addr = (volatile void *)(_POST_ADDR);
+
+ return in_be32(save_addr);
+}
+#endif /* CONFIG_POST || CONFIG_LOGBUFFER */
# Use default linker script.
# A board port can override this setting in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc512x/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc512x/u-boot.lds
#include <video_fb.h>
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
#ifdef CONFIG_FSL_DIU_LOGO_BMP
extern unsigned int FSL_Logo_BMP[];
#else
char *valid_bmp(char *addr)
{
unsigned long h_addr;
+ bd_t *bd = gd->bd;
h_addr = simple_strtoul(addr, NULL, 16);
- if (h_addr < CONFIG_SYS_FLASH_BASE ||
- h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+ if (h_addr < bd->bi_flashstart ||
+ h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) {
printf("bmp addr %lx is not a valid flash address\n", h_addr);
return 0;
} else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
char *bmp = NULL;
char *bmp_env;
+#if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES)
+ xres = CONFIG_VIDEO_XRES;
+ yres = CONFIG_VIDEO_YRES;
+#else
xres = 1024;
yres = 768;
+#endif
pixel_format = 0x88883316;
debug("mpc5121_diu_init\n");
u32 *dram_init_seq, int seq_sz)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
u32 msize_log2 = __ilog2(msize);
u32 i;
}
/* Initialize IO Control */
- out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+ out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
/* Initialize DDR Local Window */
out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
+ msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+ /* Fix DDR Local Window for new size */
+ out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
+ sync_law(&im->sysconf.ddrlaw.ar);
+
return msize;
}
--- /dev/null
+/*
+ * (C) Copyright 2000 - 2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Based ont the MPC5200 PSC driver.
+ * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
+ */
+
+/*
+ * Minimal serial functions needed to use one of the PSC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PSC_CONSOLE) || defined(CONFIG_SERIAL_MULTI)
+
+static void fifo_init (volatile psc512x_t *psc)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ u32 tfsize, rfsize;
+
+ /* reset Rx & Tx fifo slice */
+ out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
+ out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
+
+ /* disable Tx & Rx FIFO interrupts */
+ out_be32(&psc->rfintmask, 0);
+ out_be32(&psc->tfintmask, 0);
+
+#if defined(CONFIG_SERIAL_MULTI)
+ switch (((u32)psc & 0xf00) >> 8) {
+ case 0:
+ tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
+ rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
+ break;
+ case 1:
+ tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
+ rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
+ break;
+ case 2:
+ tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
+ rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
+ break;
+ case 3:
+ tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
+ rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
+ break;
+ case 4:
+ tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
+ rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
+ break;
+ case 5:
+ tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
+ rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
+ break;
+ case 6:
+ tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
+ rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
+ break;
+ case 7:
+ tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
+ rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
+ break;
+ case 8:
+ tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
+ rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
+ break;
+ case 9:
+ tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
+ rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
+ break;
+ case 10:
+ tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
+ rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
+ break;
+ case 11:
+ tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
+ rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
+ break;
+ default:
+ return;
+ }
+#else
+ tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
+ rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
+#endif
+ out_be32(&psc->tfsize, tfsize);
+ out_be32(&psc->rfsize, rfsize);
+
+ /* enable Tx & Rx FIFO slice */
+ out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
+ out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
+
+ out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
+ __asm__ volatile ("sync");
+}
+
+void serial_setbrg_dev(unsigned int idx)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+ unsigned long baseclk, div;
+ unsigned long baudrate;
+ char buf[16];
+ char *br_env;
+
+ baudrate = gd->baudrate;
+ if (idx != CONFIG_PSC_CONSOLE) {
+ /* Allows setting baudrate for other serial devices
+ * on PSCx using environment. If not specified, use
+ * the same baudrate as for console.
+ */
+ sprintf(buf, "psc%d_baudrate", idx);
+ br_env = getenv(buf);
+ if (br_env)
+ baudrate = simple_strtoul(br_env, NULL, 10);
+
+ debug("%s: idx %d, baudrate %d\n", __func__, idx, baudrate);
+ }
+
+ /* calculate divisor for setting PSC CTUR and CTLR registers */
+ baseclk = (gd->ips_clk + 8) / 16;
+ div = (baseclk + (baudrate / 2)) / baudrate;
+
+ out_8(&psc->ctur, (div >> 8) & 0xff);
+ out_8(&psc->ctlr, div & 0xff); /* set baudrate */
+}
+
+int serial_init_dev(unsigned int idx)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+#if defined(CONFIG_SERIAL_MULTI)
+ u32 reg;
+
+ reg = in_be32(&im->clk.sccr[0]);
+ out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
+#endif
+
+ fifo_init (psc);
+
+ /* set MR register to point to MR1 */
+ out_8(&psc->command, PSC_SEL_MODE_REG_1);
+
+ /* disable Tx/Rx */
+ out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
+
+ /* choose the prescaler by 16 for the Tx/Rx clock generation */
+ out_be16(&psc->psc_clock_select, 0xdd00);
+
+ /* switch to UART mode */
+ out_be32(&psc->sicr, 0);
+
+ /* mode register points to mr1 */
+ /* configure parity, bit length and so on in mode register 1*/
+ out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+ /* now, mode register points to mr2 */
+ out_8(&psc->mode, PSC_MODE_1_STOPBIT);
+
+ /* set baudrate */
+ serial_setbrg_dev(idx);
+
+ /* disable all interrupts */
+ out_be16(&psc->psc_imr, 0);
+
+ /* reset and enable Rx/Tx */
+ out_8(&psc->command, PSC_RST_RX);
+ out_8(&psc->command, PSC_RST_TX);
+ out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ return 0;
+}
+
+int serial_uninit_dev(unsigned int idx)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+ u32 reg;
+
+ out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
+ reg = in_be32(&im->clk.sccr[0]);
+ reg &= ~CLOCK_SCCR1_PSC_EN(idx);
+ out_be32(&im->clk.sccr[0], reg);
+
+ return 0;
+}
+
+void serial_putc_dev(unsigned int idx, const char c)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+ if (c == '\n')
+ serial_putc_dev(idx, '\r');
+
+ /* Wait for last character to go. */
+ while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
+ ;
+
+ out_8(&psc->tfdata_8, c);
+}
+
+void serial_putc_raw_dev(unsigned int idx, const char c)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+ /* Wait for last character to go. */
+ while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
+ ;
+
+ out_8(&psc->tfdata_8, c);
+}
+
+void serial_puts_dev(unsigned int idx, const char *s)
+{
+ while (*s)
+ serial_putc_dev(idx, *s++);
+}
+
+int serial_getc_dev(unsigned int idx)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+ /* Wait for a character to arrive. */
+ while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
+ ;
+
+ return in_8(&psc->rfdata_8);
+}
+
+int serial_tstc_dev(unsigned int idx)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+ return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
+}
+
+void serial_setrts_dev(unsigned int idx, int s)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+ if (s) {
+ /* Assert RTS (become LOW) */
+ out_8(&psc->op1, 0x1);
+ }
+ else {
+ /* Negate RTS (become HIGH) */
+ out_8(&psc->op0, 0x1);
+ }
+}
+
+int serial_getcts_dev(unsigned int idx)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+ return (in_8(&psc->ip) & 0x1) ? 0 : 1;
+}
+#endif /* CONFIG_PSC_CONSOLE || CONFIG_SERIAL_MULTI */
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
+ int serial##port##_init(void) \
+ { \
+ return serial_init_dev(port); \
+ } \
+ int serial##port##_uninit(void) \
+ { \
+ return serial_uninit_dev(port); \
+ } \
+ void serial##port##_setbrg(void) \
+ { \
+ serial_setbrg_dev(port); \
+ } \
+ int serial##port##_getc(void) \
+ { \
+ return serial_getc_dev(port); \
+ } \
+ int serial##port##_tstc(void) \
+ { \
+ return serial_tstc_dev(port); \
+ } \
+ void serial##port##_putc(const char c) \
+ { \
+ serial_putc_dev(port, c); \
+ } \
+ void serial##port##_puts(const char *s) \
+ { \
+ serial_puts_dev(port, s); \
+ }
+
+#define INIT_PSC_SERIAL_STRUCTURE(port, name, bus) { \
+ name, \
+ bus, \
+ serial##port##_init, \
+ serial##port##_uninit, \
+ serial##port##_setbrg, \
+ serial##port##_getc, \
+ serial##port##_tstc, \
+ serial##port##_putc, \
+ serial##port##_puts, \
+}
+
+#if defined(CONFIG_SYS_PSC1)
+DECLARE_PSC_SERIAL_FUNCTIONS(1);
+struct serial_device serial1_device =
+INIT_PSC_SERIAL_STRUCTURE(1, "psc1", "UART1");
+#endif
+
+#if defined(CONFIG_SYS_PSC3)
+DECLARE_PSC_SERIAL_FUNCTIONS(3);
+struct serial_device serial3_device =
+INIT_PSC_SERIAL_STRUCTURE(3, "psc3", "UART3");
+#endif
+
+#if defined(CONFIG_SYS_PSC4)
+DECLARE_PSC_SERIAL_FUNCTIONS(4);
+struct serial_device serial4_device =
+INIT_PSC_SERIAL_STRUCTURE(4, "psc4", "UART4");
+#endif
+
+#if defined(CONFIG_SYS_PSC6)
+DECLARE_PSC_SERIAL_FUNCTIONS(6);
+struct serial_device serial6_device =
+INIT_PSC_SERIAL_STRUCTURE(6, "psc6", "UART6");
+#endif
+
+#else
+
+void serial_setbrg(void)
+{
+ serial_setbrg_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_init(void)
+{
+ return serial_init_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_putc(const char c)
+{
+ serial_putc_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_putc_raw(const char c)
+{
+ serial_putc_raw_dev(CONFIG_PSC_CONSOLE, c);
+}
+
+void serial_puts(const char *s)
+{
+ serial_puts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getc(void)
+{
+ return serial_getc_dev(CONFIG_PSC_CONSOLE);
+}
+
+int serial_tstc(void)
+{
+ return serial_tstc_dev(CONFIG_PSC_CONSOLE);
+}
+
+void serial_setrts(int s)
+{
+ return serial_setrts_dev(CONFIG_PSC_CONSOLE, s);
+}
+
+int serial_getcts(void)
+{
+ return serial_getcts_dev(CONFIG_PSC_CONSOLE);
+}
+#endif /* CONFIG_PSC_CONSOLE */
+
+#if defined(CONFIG_SERIAL_MULTI)
+#include <stdio_dev.h>
+/*
+ * Routines for communication with serial devices over PSC
+ */
+/* Bitfield for initialized PSCs */
+static unsigned int initialized;
+
+struct stdio_dev *open_port(int num, int baudrate)
+{
+ struct stdio_dev *port;
+ char env_var[16];
+ char env_val[10];
+ char name[7];
+
+ if (num < 0 || num > 11)
+ return NULL;
+
+ sprintf(name, "psc%d", num);
+ port = stdio_get_by_name(name);
+ if (!port)
+ return NULL;
+
+ if (!test_bit(num, &initialized)) {
+ sprintf(env_var, "psc%d_baudrate", num);
+ sprintf(env_val, "%d", baudrate);
+ setenv(env_var, env_val);
+
+ if (port->start())
+ return NULL;
+
+ set_bit(num, &initialized);
+ }
+
+ return port;
+}
+
+int close_port(int num)
+{
+ struct stdio_dev *port;
+ int ret;
+ char name[7];
+
+ if (num < 0 || num > 11)
+ return -1;
+
+ sprintf(name, "psc%d", num);
+ port = stdio_get_by_name(name);
+ if (!port)
+ return -1;
+
+ ret = port->stop();
+ clear_bit(num, &initialized);
+
+ return ret;
+}
+
+int write_port(struct stdio_dev *port, char *buf)
+{
+ if (!port || !buf)
+ return -1;
+
+ port->puts(buf);
+
+ return 0;
+}
+
+int read_port(struct stdio_dev *port, char *buf, int size)
+{
+ int cnt = 0;
+
+ if (!port || !buf)
+ return -1;
+
+ if (!size)
+ return 0;
+
+ while (port->tstc()) {
+ buf[cnt++] = port->getc();
+ if (cnt > size)
+ break;
+ }
+
+ return cnt;
+}
+#endif /* CONFIG_SERIAL_MULTI */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc512x/start.o (.text)
+ arch/powerpc/cpu/mpc512x/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
#
#
-# File: arch/ppc/cpu/mpc5xx/Makefile
+# File: arch/powerpc/cpu/mpc5xx/Makefile
#
# Discription: Makefile to build mpc5xx cpu configuration.
# Will include top config.mk which itselfs
-# uses the definitions made in arch/ppc/cpu/mpc5xx/config.mk
+# uses the definitions made in arch/powerpc/cpu/mpc5xx/config.mk
#
PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xx/u-boot.lds
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc5xx/start.o (.text)
+ arch/powerpc/cpu/mpc5xx/start.o (.text)
*(.text)
*(.got1)
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot.lds
* MA 02111-1307 USA
*/
-/* this section was ripped out of arch/ppc/syslib/mpc52xx_pic.c in the
+/* this section was ripped out of arch/powerpc/syslib/mpc52xx_pic.c in the
* Linux 2.6 source with the following copyright.
*
* Based on (well, mostly copied from) the code from the 2.4 kernel by
* MA 02111-1307 USA
*
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
- * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the
+ * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
* Linux/PPC sources (m8260_tty.c had no copyright info in it).
*
* Martin Krause, 8 Jun 2006
"serial0",
"UART0",
serial0_init,
+ NULL,
serial0_setbrg,
serial0_getc,
serial0_tstc,
"serial1",
"UART1",
serial1_init,
+ NULL,
serial1_setbrg,
serial1_getc,
serial1_tstc,
/* */
/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
/* incrementing by 0x1000 each time. The code below is sort of */
- /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
+ /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
/* */
/*--------------------------------------------------------------*/
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc5xxx/start.o (.text)
- arch/ppc/cpu/mpc5xxx/traps.o (.text)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text)
+ arch/powerpc/cpu/mpc5xxx/traps.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc5xxx/start.o (.text)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8220/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc8220/u-boot.lds
/* */
/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
/* incrementing by 0x1000 each time. The code below is sort of */
- /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
+ /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
/* */
/*--------------------------------------------------------------*/
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8220/start.o (.text)
+ arch/powerpc/cpu/mpc8220/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc824x/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc824x/u-boot.lds
/*
- * arch/ppc/kernel/mpc10x_common.c
+ * arch/powerpc/kernel/mpc10x_common.c
*
* Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
* Mem ctlr, EPIC, etc.
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc824x/start.o (.text)
+ arch/powerpc/cpu/mpc824x/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
/*
- * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
+ * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
* copyright notice:
*
* General Purpose functions for the global management of the
-mstring -mcpu=603e -mmultiple
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc8260/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc8260/u-boot.lds
static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
/****************************************************************************/
-/* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the */
+/* this section was ripped out of arch/powerpc/kernel/ppc8260_pic.c in the */
/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
/* The 8260 internal interrupt controller. It is usually
return irq;
}
-/* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c */
+/* end of code ripped out of arch/powerpc/kernel/ppc8260_pic.c */
/****************************************************************************/
int interrupt_init_cpu (unsigned *decrementer_count)
* MA 02111-1307 USA
*
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
- * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the
+ * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
* Linux/PPC sources (m8260_tty.c had no copyright info in it).
*/
/* */
/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
/* incrementing by 0x1000 each time. The code below is sort of */
- /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
+ /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
/* */
/*--------------------------------------------------------------*/
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8260/start.o (.text)
+ arch/powerpc/cpu/mpc8260/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
-ffixed-r2 -msoft-float
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc83xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc83xx/u-boot.lds
puts(cpu_type_list[i].name);
if (IS_E_PROCESSOR(spridr))
puts("E");
- if (REVID_MAJOR(spridr) >= 2)
+ if ((SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
+ SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
+ REVID_MAJOR(spridr) >= 2)
puts("A");
printf(", Rev: %d.%d", REVID_MAJOR(spridr),
REVID_MINOR(spridr));
#include <config.h>
#include <common.h>
#include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
/* SerDes registers */
#define FSL_SRDSCR0_OFFS 0x0
#if defined(CONFIG_MPC8315)
u32 tdm_clk;
#endif
-#if defined(CONFIG_MPC837x)
+#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
u32 enc_clk;
return -7;
}
-#if defined(CONFIG_MPC837x)
+#if defined(CONFIG_FSL_ESDHC)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
case 0:
sdhc_clk = 0;
i2c1_clk = enc_clk;
#elif defined(CONFIG_MPC831x)
i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC837x)
+#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
#endif
#if !defined(CONFIG_MPC832x)
#if defined(CONFIG_MPC8315)
gd->tdm_clk = tdm_clk;
#endif
-#if defined(CONFIG_MPC837x)
+#if defined(CONFIG_FSL_ESDHC)
gd->sdhc_clk = sdhc_clk;
#endif
gd->core_clk = core_clk;
#if defined(CONFIG_MPC8315)
printf(" TDM: %-4s MHz\n", strmhz(buf, gd->tdm_clk));
#endif
-#if defined(CONFIG_MPC837x)
+#if defined(CONFIG_FSL_ESDHC)
printf(" SDHC: %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
#endif
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
*
* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
* incrementing by 0x1000 each time. The code below is sort of
- * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
+ * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
*
*/
lis r3, 0
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc83xx/start.o (.text)
+ arch/powerpc/cpu/mpc83xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
* Adapted for Motorola MPC8560 chips
* Xianghua Xiao <x.xiao@motorola.com>
*
- * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
+ * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
* copyright notice:
*
* General Purpose functions for the global management of the
PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe)
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc85xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc85xx/u-boot.lds
/*
- * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#ifdef CONFIG_DDR_CLK_FREQ
+#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_CORENET
- u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
- >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
-#else
+#endif /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#endif
#else
#ifdef CONFIG_FSL_CORENET
- u32 ddr_sync = 0;
+ u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+ >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#else
u32 ddr_ratio = 0;
-#endif
+#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
int i;
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
- memctl->or0 = CONFIG_SYS_OR0_REMAP;
+ out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
- memctl->or1 = CONFIG_SYS_OR1_REMAP;
+ out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (! memctl->br1 & 1) {
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
- memctl->br0 = CONFIG_SYS_BR0_PRELIM;
- memctl->or0 = CONFIG_SYS_OR0_PRELIM;
+ out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
+ out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- memctl->or1 = CONFIG_SYS_OR1_PRELIM;
- memctl->br1 = CONFIG_SYS_BR1_PRELIM;
+ out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
+ out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- memctl->or2 = CONFIG_SYS_OR2_PRELIM;
- memctl->br2 = CONFIG_SYS_BR2_PRELIM;
+ out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
+ out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- memctl->or3 = CONFIG_SYS_OR3_PRELIM;
- memctl->br3 = CONFIG_SYS_BR3_PRELIM;
+ out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
+ out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- memctl->or4 = CONFIG_SYS_OR4_PRELIM;
- memctl->br4 = CONFIG_SYS_BR4_PRELIM;
+ out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
+ out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- memctl->or5 = CONFIG_SYS_OR5_PRELIM;
- memctl->br5 = CONFIG_SYS_BR5_PRELIM;
+ out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
+ out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- memctl->or6 = CONFIG_SYS_OR6_PRELIM;
- memctl->br6 = CONFIG_SYS_BR6_PRELIM;
+ out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
+ out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- memctl->or7 = CONFIG_SYS_OR7_PRELIM;
- memctl->br7 = CONFIG_SYS_BR7_PRELIM;
+ out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
+ out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
#endif
#if defined(CONFIG_CPM2)
int cpu_init_r(void)
{
+#ifdef CONFIG_SYS_LBC_LCRR
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+#endif
+
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
#if defined(CONFIG_MP)
setup_mp();
#endif
+
+#ifdef CONFIG_SYS_LBC_LCRR
+ /*
+ * Modify the CLKDIV field of LCRR register to improve the writing
+ * speed for NOR flash.
+ */
+ clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
+ __raw_readl(&lbc->lcrr);
+ isync();
+#endif
+
return 0;
}
/*
- * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
[14] = 4, /* CC4 PPL / 4 */
};
uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+ uint ratio[4];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+ uint mem_pll_rat;
sysInfo->freqSystemBus = sysclk;
sysInfo->freqDDRBus = sysclk;
- freqCC_PLL[0] = sysclk;
- freqCC_PLL[1] = sysclk;
- freqCC_PLL[2] = sysclk;
- freqCC_PLL[3] = sysclk;
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
- freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
- freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
- freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
- freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+ mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+ if (mem_pll_rat > 2)
+ sysInfo->freqDDRBus *= mem_pll_rat;
+ else
+ sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
+ ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
+ ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
+ ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
+ ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
+ for (i = 0; i < 4; i++) {
+ if (ratio[i] > 4)
+ freqCC_PLL[i] = sysclk * ratio[i];
+ else
+ freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
+ }
rcw_tmp = in_be32(&gur->rcwsr[3]);
for (i = 0; i < cpu_numcores(); i++) {
u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright 2007 Freescale Semiconductor.
* Copyright (C) 2003 Motorola
.bootpg ADDR(.text) - 0x1000 :
{
- arch/ppc/cpu/mpc85xx/start.o (.bootpg)
+ arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
. = ADDR(.text) + 0x80000;
. = 0xfff00000;
.text : {
*(.text)
- }
+ }
_etext = .;
.reloc : {
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
- arch/ppc/cpu/mpc85xx/start.o (.bootpg)
+ arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
} :text = 0xffff
.resetvec RESET_VECTOR_ADDRESS :
"serial_smc",
"SMC",
smc_init,
+ NULL,
smc_setbrg,
smc_getc,
smc_tstc,
"serial_scc",
"SCC",
scc_init,
+ NULL,
scc_setbrg,
scc_getc,
scc_tstc,
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
- * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and
- * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains
+ * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
+ * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
* cpu specific common code for 85xx/86xx processors.
* See file CREDITS for list of people who contributed to this
* project.
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
+ /* set the turnaround time */
+ trwt_mclk = 1;
#else /* CONFIG_FSL_DDR2 */
/*
* (tXARD and tXARDS). Empirical?
/*
* Copyright 2009 Freescale Semiconductor, Inc.
*
- * This file is derived from arch/ppc/cpu/mpc85xx/cpu.c and
- * arch/ppc/cpu/mpc86xx/cpu.c. Basically this file contains
+ * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
+ * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
* cpu specific common code for 85xx/86xx processors.
* See file CREDITS for list of people who contributed to this
* project.
(1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
},
[LAW_TRGT_IF_PCIE_2] = {
- .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
- (1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
- (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
- (1 << 0x18) | (1 << 0x1c),
+ .cfg = (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+ (1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
+ (1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
},
[LAW_TRGT_IF_PCIE_3] = {
- .cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
- (1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
- (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
+ .cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
+ (1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) |
+ (1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c),
},
};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)
/*
- * arch/ppc/cpu/ppc4xx/40x_spd_sdram.c
+ * arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
* This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
* SDRAM controller. Those are all current 405 PPC's.
*
/*
- * arch/ppc/cpu/ppc4xx/44x_spd_ddr.c
+ * arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
* This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
* DDR controller. Those are 440GP/GX/EP/GR.
*
/*
- * arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c
+ * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those currently are:
*
/*
- * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+ * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
* DDR2 controller (non Denali Core). Those currently are:
*
"serial0",
"UART0",
serial0_init,
+ NULL,
serial0_setbrg,
serial0_getc,
serial0_tstc,
"serial1",
"UART1",
serial1_init,
+ NULL,
serial1_setbrg,
serial1_getc,
serial1_tstc,
endif
# Use default linker script. Board port can override in board/*/config.mk
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/ppc4xx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/ppc4xx/u-boot.lds
/*
- * arch/ppc/cpu/ppc4xx/denali_data_eye.c
+ * arch/powerpc/cpu/ppc4xx/denali_data_eye.c
* Extracted from board/amcc/sequoia/sdram.c by Larry Johnson <lrj@acm.org>.
*
* (C) Copyright 2006
/*
- * arch/ppc/cpu/ppc4xx/denali_spd_ddr2.c
+ * arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
* DDR2 controller, specifically the 440EPx/GRx.
*
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org.
*
- * Based primarily on arch/ppc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
+ * Based primarily on arch/powerpc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
/*
- * linux/arch/ppc/kernel/traps.c
+ * linux/arch/powerpc/kernel/traps.c
*
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
#ifdef CONFIG_440
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
- arch/ppc/cpu/ppc4xx/start.o (.bootpg)
+ arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
/*
* PPC440 board need a board specific object with the
/*
- * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
#define DDR_BL8 8 /* burst length 8 */
+#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
+#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
+#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
+#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
+#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
+
#if defined(CONFIG_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
/*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#define OR_GPCM_SETA_SHIFT 3
#define OR_GPCM_TRLX 0x00000004
#define OR_GPCM_TRLX_SHIFT 2
+#define OR_GPCM_TRLX_CLEAR 0x00000000
+#define OR_GPCM_TRLX_SET 0x00000004
#define OR_GPCM_EHTR 0x00000002
#define OR_GPCM_EHTR_SHIFT 1
+#define OR_GPCM_EHTR_CLEAR 0x00000000
+#define OR_GPCM_EHTR_SET 0x00000002
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0
/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <yashi@atmark-techno.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* MA 02111-1307 USA
*/
-#include <common.h>
+#ifndef __FSL_MPC83XX_SERDES_H
+#define __FSL_MPC83XX_SERDES_H
+
+#include <config.h>
+
+#define FSL_SERDES_CLK_100 (0 << 28)
+#define FSL_SERDES_CLK_125 (1 << 28)
+#define FSL_SERDES_CLK_150 (3 << 28)
+#define FSL_SERDES_PROTO_SATA 0
+#define FSL_SERDES_PROTO_PEX 1
+#define FSL_SERDES_PROTO_PEX_X2 2
+#define FSL_SERDES_PROTO_SGMII 3
+#define FSL_SERDES_VDD_1V 1
+
+extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
-void flush_cache (ulong addr, ulong size)
-{
- int i;
- for (i = 0; i < size; i += 4)
- asm volatile (
-#ifdef CONFIG_ICACHE
- "wic %0, r0;"
-#endif
- "nop;"
-#ifdef CONFIG_DCACHE
- "wdc %0, r0;"
-#endif
- "nop;"
- :
- : "r" (addr + i)
- : "memory");
-}
+#endif /* __FSL_MPC83XX_SERDES_H */
u32 ddr_time_config2; /* Timing Configuration Register */
} ddr512x_config_t;
+typedef struct sdram_conf_s {
+ unsigned long size;
+ ddr512x_config_t cfg;
+} sdram_conf_t;
+
/*
* DMA/Messaging Unit
*/
u8 reserved[0x0cfc]; /* fill to 4096 bytes size */
} ioctrl512x_t;
-/* Indexes in regs array */
-/* Set for DDR */
-#define IOCTRL_MUX_DDR 0x00000036
-
/* IO pin fields */
#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
*
* Overall size of FIFOC memory is not documented in the MPC5121e RM, but
* tests indicate that it is 1024 words total.
+ *
+ * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice.
*/
-#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */
+#define FIFOC_PSC0_TX_SIZE 0x04
#define FIFOC_PSC0_TX_ADDR 0x0
-#define FIFOC_PSC0_RX_SIZE 0x0
-#define FIFOC_PSC0_RX_ADDR 0x0
+#define FIFOC_PSC0_RX_SIZE 0x04
+#define FIFOC_PSC0_RX_ADDR 0x10
-#define FIFOC_PSC1_TX_SIZE 0x0
-#define FIFOC_PSC1_TX_ADDR 0x0
-#define FIFOC_PSC1_RX_SIZE 0x0
-#define FIFOC_PSC1_RX_ADDR 0x0
+#define FIFOC_PSC1_TX_SIZE 0x04
+#define FIFOC_PSC1_TX_ADDR 0x20
+#define FIFOC_PSC1_RX_SIZE 0x04
+#define FIFOC_PSC1_RX_ADDR 0x30
-#define FIFOC_PSC2_TX_SIZE 0x0
-#define FIFOC_PSC2_TX_ADDR 0x0
-#define FIFOC_PSC2_RX_SIZE 0x0
-#define FIFOC_PSC2_RX_ADDR 0x0
+#define FIFOC_PSC2_TX_SIZE 0x04
+#define FIFOC_PSC2_TX_ADDR 0x40
+#define FIFOC_PSC2_RX_SIZE 0x04
+#define FIFOC_PSC2_RX_ADDR 0x50
#define FIFOC_PSC3_TX_SIZE 0x04
-#define FIFOC_PSC3_TX_ADDR 0x0
+#define FIFOC_PSC3_TX_ADDR 0x60
#define FIFOC_PSC3_RX_SIZE 0x04
-#define FIFOC_PSC3_RX_ADDR 0x10
-
-#define FIFOC_PSC4_TX_SIZE 0x0
-#define FIFOC_PSC4_TX_ADDR 0x0
-#define FIFOC_PSC4_RX_SIZE 0x0
-#define FIFOC_PSC4_RX_ADDR 0x0
-
-#define FIFOC_PSC5_TX_SIZE 0x0
-#define FIFOC_PSC5_TX_ADDR 0x0
-#define FIFOC_PSC5_RX_SIZE 0x0
-#define FIFOC_PSC5_RX_ADDR 0x0
-
-#define FIFOC_PSC6_TX_SIZE 0x0
-#define FIFOC_PSC6_TX_ADDR 0x0
-#define FIFOC_PSC6_RX_SIZE 0x0
-#define FIFOC_PSC6_RX_ADDR 0x0
-
-#define FIFOC_PSC7_TX_SIZE 0x0
-#define FIFOC_PSC7_TX_ADDR 0x0
-#define FIFOC_PSC7_RX_SIZE 0x0
-#define FIFOC_PSC7_RX_ADDR 0x0
-
-#define FIFOC_PSC8_TX_SIZE 0x0
-#define FIFOC_PSC8_TX_ADDR 0x0
-#define FIFOC_PSC8_RX_SIZE 0x0
-#define FIFOC_PSC8_RX_ADDR 0x0
-
-#define FIFOC_PSC9_TX_SIZE 0x0
-#define FIFOC_PSC9_TX_ADDR 0x0
-#define FIFOC_PSC9_RX_SIZE 0x0
-#define FIFOC_PSC9_RX_ADDR 0x0
-
-#define FIFOC_PSC10_TX_SIZE 0x0
-#define FIFOC_PSC10_TX_ADDR 0x0
-#define FIFOC_PSC10_RX_SIZE 0x0
-#define FIFOC_PSC10_RX_ADDR 0x0
-
-#define FIFOC_PSC11_TX_SIZE 0x0
-#define FIFOC_PSC11_TX_ADDR 0x0
-#define FIFOC_PSC11_RX_SIZE 0x0
-#define FIFOC_PSC11_RX_ADDR 0x0
+#define FIFOC_PSC3_RX_ADDR 0x70
+
+#define FIFOC_PSC4_TX_SIZE 0x04
+#define FIFOC_PSC4_TX_ADDR 0x80
+#define FIFOC_PSC4_RX_SIZE 0x04
+#define FIFOC_PSC4_RX_ADDR 0x90
+
+#define FIFOC_PSC5_TX_SIZE 0x04
+#define FIFOC_PSC5_TX_ADDR 0xa0
+#define FIFOC_PSC5_RX_SIZE 0x04
+#define FIFOC_PSC5_RX_ADDR 0xb0
+
+#define FIFOC_PSC6_TX_SIZE 0x04
+#define FIFOC_PSC6_TX_ADDR 0xc0
+#define FIFOC_PSC6_RX_SIZE 0x04
+#define FIFOC_PSC6_RX_ADDR 0xd0
+
+#define FIFOC_PSC7_TX_SIZE 0x04
+#define FIFOC_PSC7_TX_ADDR 0xe0
+#define FIFOC_PSC7_RX_SIZE 0x04
+#define FIFOC_PSC7_RX_ADDR 0xf0
+
+#define FIFOC_PSC8_TX_SIZE 0x04
+#define FIFOC_PSC8_TX_ADDR 0x100
+#define FIFOC_PSC8_RX_SIZE 0x04
+#define FIFOC_PSC8_RX_ADDR 0x110
+
+#define FIFOC_PSC9_TX_SIZE 0x04
+#define FIFOC_PSC9_TX_ADDR 0x120
+#define FIFOC_PSC9_RX_SIZE 0x04
+#define FIFOC_PSC9_RX_ADDR 0x130
+
+#define FIFOC_PSC10_TX_SIZE 0x04
+#define FIFOC_PSC10_TX_ADDR 0x140
+#define FIFOC_PSC10_RX_SIZE 0x04
+#define FIFOC_PSC10_RX_ADDR 0x150
+
+#define FIFOC_PSC11_TX_SIZE 0x04
+#define FIFOC_PSC11_TX_ADDR 0x160
+#define FIFOC_PSC11_RX_SIZE 0x04
+#define FIFOC_PSC11_RX_ADDR 0x170
/*
* SATA
/*
* MPC85xx Internal Memory Map
*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
u8 res4[12];
u32 gpindr; /* General-purpose input data */
u8 res5[12];
- u32 pmuxcr; /* Alt function signal multiplex control */
+ u32 alt_pmuxcr; /* Alt function signal multiplex control */
u8 res6[12];
u32 devdisr; /* Device disable control */
#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
#define FSL_CORENET_DEVDISR_I2C2 0x00000010
#define FSL_CORENET_DEVDISR_DUART1 0x00000002
#define FSL_CORENET_DEVDISR_DUART2 0x00000001
- u8 res7[12];
+ u32 devdisr2; /* Device disable control 2 */
+#define FSL_CORENET_DEVDISR2_PME 0x80000000
+#define FSL_CORENET_DEVDISR2_SEC 0x40000000
+#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
+#define FSL_CORENET_DEVDISR2_FM1 0x02000000
+#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
+#define FSL_CORENET_DEVDISR2_FM2 0x00020000
+#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
+ u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
u8 res8[12];
u32 coredisru; /* uppper portion for support of 64 cores */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
-#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
-#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
+#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
+#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
+#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
u32 cgencrl; /* Core general control */
u8 res31[184];
u32 sriopstecr; /* SRIO prescaler timer enable control */
- u8 res32[2300];
+ u8 res32[1788];
+ u32 pmuxcr; /* Pin multiplexing control */
+ u8 res33[60];
+ u32 iovselsr; /* I/O voltage selection status */
+ u8 res34[28];
+ u32 ddrclkdr; /* DDR clock disable */
+ u8 res35;
+ u32 elbcclkdr; /* eLBC clock disable */
+ u8 res36[20];
+ u32 sdhcpcr; /* eSDHC polarity configuration */
+ u8 res37[380];
} ccsr_gur_t;
typedef struct ccsr_clk {
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
+#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
+#endif
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
#define SRDS_RSTCTL_RST 0x80000000
#define SRDS_RSTCTL_RSTDONE 0x40000000
#define SRDS_RSTCTL_RSTERR 0x20000000
+#define SRDS_RSTCTL_SDPD 0x00000020
u32 pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
+#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
u32 pllcr1; /* PLL Control Register 1 */
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
u32 res[5];
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
+#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
+/* Some additional macros for combinations often used */
+#define SA_IG (SA_I | SA_G)
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
+/* Some additional macros for combinations often used */
+#define AC_RW (AC_R | AC_W)
+#define AC_RWX (AC_R | AC_W | AC_X)
/* Some handy macros */
* that the overall structure is a multiple of 16 bytes in length.
*
* Note that the offsets of the fields in this struct correspond with
- * the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
+ * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
*/
#include <linux/config.h>
WATCHDOG_RESET();
-#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx)
+#if defined(CONFIG_SYS_DELAYED_ICACHE)
icache_enable (); /* it's time to enable the instruction cache */
#endif
+++ /dev/null
-/*
- * (C) Copyright 2000 - 2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Based ont the MPC5200 PSC driver.
- * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_PSC_CONSOLE)
-
-static void fifo_init (volatile psc512x_t *psc)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-
- /* reset Rx & Tx fifo slice */
- out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
- out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
-
- /* disable Tx & Rx FIFO interrupts */
- out_be32(&psc->rfintmask, 0);
- out_be32(&psc->tfintmask, 0);
-
- out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
- out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
-
- /* enable Tx & Rx FIFO slice */
- out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
- out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
-
- out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
- __asm__ volatile ("sync");
-}
-
-void serial_setbrg(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
- unsigned long baseclk, div;
-
- /* calculate dividor for setting PSC CTUR and CTLR registers */
- baseclk = (gd->ips_clk + 8) / 16;
- div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
-
- out_8(&psc->ctur, (div >> 8) & 0xff);
- out_8(&psc->ctlr, div & 0xff); /* set baudrate */
-}
-
-int serial_init(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-
- fifo_init (psc);
-
- /* set MR register to point to MR1 */
- out_8(&psc->command, PSC_SEL_MODE_REG_1);
-
- /* disable Tx/Rx */
- out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
-
- /* choose the prescaler by 16 for the Tx/Rx clock generation */
- out_be16(&psc->psc_clock_select, 0xdd00);
-
- /* switch to UART mode */
- out_be32(&psc->sicr, 0);
-
- /* mode register points to mr1 */
- /* configure parity, bit length and so on in mode register 1*/
- out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
- /* now, mode register points to mr2 */
- out_8(&psc->mode, PSC_MODE_1_STOPBIT);
-
- /* set baudrate */
- serial_setbrg();
-
- /* disable all interrupts */
- out_be16(&psc->psc_imr, 0);
-
- /* reset and enable Rx/Tx */
- out_8(&psc->command, PSC_RST_RX);
- out_8(&psc->command, PSC_RST_TX);
- out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
-
- return 0;
-}
-
-void serial_putc (const char c)
-{
- volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-
- if (c == '\n')
- serial_putc ('\r');
-
- /* Wait for last character to go. */
- while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
- ;
-
- out_8(&psc->tfdata_8, c);
-}
-
-void serial_putc_raw (const char c)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-
- /* Wait for last character to go. */
- while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
- ;
-
- out_8(&psc->tfdata_8, c);
-}
-
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int serial_getc (void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-
- /* Wait for a character to arrive. */
- while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
- ;
-
- return in_8(&psc->rfdata_8);
-}
-
-int serial_tstc (void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-
- return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
-}
-
-void serial_setrts(int s)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-
- if (s) {
- /* Assert RTS (become LOW) */
- out_8(&psc->op1, 0x1);
- }
- else {
- /* Negate RTS (become HIGH) */
- out_8(&psc->op0, 0x1);
- }
-}
-
-int serial_getcts(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
-
- return (in_8(&psc->ip) & 0x1) ? 0 : 1;
-}
-#endif /* CONFIG_PSC_CONSOLE */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
lib/string.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/extable.o (.text)
- arch/ppc/lib/time.o (.text)
- arch/ppc/lib/ticks.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/extable.o (.text)
+ arch/powerpc/lib/time.o (.text)
+ arch/powerpc/lib/ticks.o (.text)
. = env_offset;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
common/env_embedded.o(.text)
/*
* COM1 NS16550 support
- * originally from linux source (arch/ppc/boot/ns16550.c)
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
* modified to use CONFIG_SYS_ISA_MEM and new defines
*
* further modified by Josh Huber <huber@mclx.com> to support
/*
* NS16550 Serial Port
- * originally from linux source (arch/ppc/boot/ns16550.h)
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
* modified slightly to
* have addresses as offsets from CONFIG_SYS_ISA_BASE
* added a few more definitions
*************************************************************************/
/*
* based on Linux code
- * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
+ * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
* This program is free software; you can redistribute it and/or
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
*************************************************************************/
/*
* based on Linux code
- * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
+ * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
* This program is free software; you can redistribute it and/or
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
--- /dev/null
+/*
+ * Altera CF drvier
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_IDE_RESET) && defined(CONFIG_SYS_CF_CTL_BASE)
+/* ide_set_reset for Altera CF interface */
+#define ALTERA_CF_CTL_STATUS 0
+#define ALTERA_CF_IDE_CTL 4
+#define ALTERA_CF_CTL_STATUS_PRESENT_MSK (0x1)
+#define ALTERA_CF_CTL_STATUS_POWER_MSK (0x2)
+#define ALTERA_CF_CTL_STATUS_RESET_MSK (0x4)
+#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK (0x8)
+#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK (0x1)
+
+void ide_set_reset(int idereset)
+{
+ int i;
+ writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK :
+ ALTERA_CF_CTL_STATUS_POWER_MSK,
+ CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS);
+ /* wait 500 ms for power to stabilize */
+ for (i = 0; i < 500; i++)
+ udelay(1000);
+}
+#endif
+++ /dev/null
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-OUTPUT_FORMAT("elf32-littlenios2")
-OUTPUT_ARCH(nios2)
-ENTRY(_start)
-
-SECTIONS
-{
- .text :
- {
- arch/nios/cpu2/start.o (.text)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t*)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.gnu.linkonce.r*)
- }
- . = ALIGN (4);
- _etext = .;
- PROVIDE (etext = .);
-
- /* CMD TABLE - sandwich this in between text and data so
- * the initialization code relocates the command table as
- * well -- admittedly, this is just pure laziness ;-)
- */
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
- . = ALIGN(4);
- __u_boot_cmd_end = .;
-
- /* INIT DATA sections - "Small" data (see the gcc -G option)
- * is always gp-relative. Here we make all init data sections
- * adjacent to simplify the startup code -- and provide
- * the global pointer for gp-relative access.
- */
- _data = .;
- .data :
- {
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d*)
- }
-
- . = ALIGN(16);
- _gp = .; /* Global pointer addr */
- PROVIDE (gp = .);
-
- .sdata :
- {
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- }
- . = ALIGN(4);
-
- _edata = .;
- PROVIDE (edata = .);
-
- /* UNINIT DATA - Small uninitialized data is first so it's
- * adjacent to sdata and can be referenced via gp. The normal
- * bss follows. We keep it adjacent to simplify init code.
- */
- __bss_start = .;
- .sbss (NOLOAD) :
- {
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- }
- . = ALIGN(4);
- .bss (NOLOAD) :
- {
- *(.bss)
- *(.bss.*)
- *(.dynbss)
- *(COMMON)
- *(.scommon)
- }
- . = ALIGN(4);
- _end = .;
- PROVIDE (end = .);
-
- /* DEBUG -- symbol table, string table, etc. etc.
- */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_info 0 : { *(.debug_info) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
--- /dev/null
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o
+COBJS-$(CONFIG_EPLED) += ../common/epled.o
+COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
+
+SOBJS-y := text_base.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+# Scott McNutt <smcnutt@psyent.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# we get text_base from board config header, so do not use this
+#TEXT_BASE = do-not-use-me
+
+PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
+
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
--- /dev/null
+/*
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file is generated by sopc-create-config-files.
+ */
+#ifndef _CUSTOM_FPGA_H_
+#define _CUSTOM_FPGA_H_
+
+/* generated from std_1c20.sopc */
+
+/* cpu.data_master is a altera_nios2 */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define CONFIG_SYS_RESET_ADDR 0x00000000
+#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
+#define CONFIG_SYS_ICACHE_SIZE 4096
+#define CONFIG_SYS_ICACHELINE_SIZE 32
+#define CONFIG_SYS_DCACHE_SIZE 2048
+#define CONFIG_SYS_DCACHELINE_SIZE 4
+
+/* sdram.s1 is a altera_avalon_new_sdram_controller */
+#define CONFIG_SYS_SDRAM_BASE 0x01000000
+#define CONFIG_SYS_SDRAM_SIZE 0x01000000
+
+/* uart1.s1 is a altera_avalon_uart */
+#define CONFIG_SYS_UART_BASE 0x82120840
+#define CONFIG_SYS_UART_FREQ 50000000
+#define CONFIG_SYS_UART_BAUD 115200
+
+/* lan91c111.s1 is a altera_avalon_lan91c111 */
+#define CONFIG_SMC91111_BASE 0x82110300
+#define CONFIG_SMC91111
+#define CONFIG_SMC_USE_32_BIT
+
+/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
+#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
+
+/* led_pio.s1 is a altera_avalon_pio */
+#define LED_PIO_BASE 0x82120870
+
+/* high_res_timer.s1 is a altera_avalon_timer */
+#define CONFIG_SYS_TIMER_BASE 0x82120820
+#define CONFIG_SYS_TIMER_IRQ 3
+#define CONFIG_SYS_TIMER_FREQ 50000000
+
+/* ext_flash.s1 is a altera_avalon_cfi_flash */
+#define CONFIG_SYS_FLASH_BASE 0x80000000
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 1024
+
+/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
+#define CONFIG_SYS_SRAM_BASE 0x02000000
+#define CONFIG_SYS_SRAM_SIZE 0x00100000
+
+/* sysid.control_slave is a altera_avalon_sysid */
+#define CONFIG_SYS_SYSID_BASE 0x821208b8
+
+#endif /* _CUSTOM_FPGA_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+void text_base_hook(void); /* nop hook for text_base.S */
+
+int board_early_init_f(void)
+{
+ text_base_hook();
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("BOARD : %s\n", CONFIG_BOARD_NAME);
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC91111
+ rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+ rc += dm9000_initialize(bis);
+#endif
+#ifdef CONFIG_ALTERA_TSE
+ rc += altera_tse_initialize(0,
+ CONFIG_SYS_ALTERA_TSE_MAC_BASE,
+ CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
+ CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE);
+#endif
+#ifdef CONFIG_ETHOC
+ rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
+#endif
+ return rc;
+}
+#endif
--- /dev/null
+/*
+ * text_base
+ *
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <config.h>
+
+#ifdef CONFIG_SYS_MONITOR_BASE
+ .text
+ /* text base used in link script u-boot.lds */
+ .global text_base
+ .equ text_base,CONFIG_SYS_MONITOR_BASE
+ /* dummy func to let linker include this file */
+ .global text_base_hook
+text_base_hook:
+ ret
+#endif
SECTIONS
{
+ . = text_base;
.text :
{
- arch/nios/cpu2/start.o (.text)
+ arch/nios2/cpu/start.o (.text)
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
+ tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
#endif
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
/* PCI base & peripherals */
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
- tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+ tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
+ tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
/* PCI */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
/* USB 2.0 Device */
- tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
tlbtab_end
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
-#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
#define BOARD_ARCHES 4
/*
- * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
#if defined(CONFIG_ARCHES)
* enable SA_I
*/
#ifndef CONFIG_NAND_SPL
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
#else
- tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
+ tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
+ tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
#endif
/*
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
#endif
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
/* PCIe UTL register */
- tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
#if !defined(CONFIG_ARCHES)
/* TLB-entry for NAND */
- tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
/* TLB-entry for CPLD */
- tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
#else
/* TLB-entry for FPGA */
- tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
#endif
/* TLB-entry for OCM */
- tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
/* TLB-entry for Local Configuration registers => peripherals */
- tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
/* AHB: Internal USB Peripherals (USB, SATA) */
- tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
#if defined(CONFIG_RAPIDIO)
/* TLB-entries for RapidIO (SRIO) */
tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
- 0xD, AC_R|AC_W|SA_G|SA_I)
+ 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
- 0xD, AC_R|AC_W|SA_G|SA_I)
+ 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
- 0xD, AC_R|AC_W|SA_G|SA_I)
+ 0xD, AC_RW | SA_IG)
tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
- 0x4, AC_R|AC_W|SA_G|SA_I)
+ 0x4, AC_RW | SA_IG)
#endif
tlbtab_end
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x20000);
tlbtab:
tlbtab_start
- tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
/*
* TLB entries for SDRAM are not needed on this platform.
* routine.
*/
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
- tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
tlbtab_end
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
* routine.
*/
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
tlbtab_end
/**************************************************************************
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
* routine.
*/
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
tlbtab_end
}
/*
- * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_wrdtr(u32 default_val) {
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
- tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
+ tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
+ tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
+ tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
+ tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
/*
* TLB entries for SDRAM are not needed on this platform.
*/
/* internal ram (l2 cache) */
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
/* peripherals at f0000000 */
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
/* PCI */
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
tlbtab_end
}
/*
- * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_clktr(u32 default_val) {
tlbtab:
tlbtab_start
- tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
/*
* TLB entries for SDRAM are not needed on this platform.
* routine.
*/
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
- tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
tlbtab_end
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
*/
/* Although 512 KB, map 256k at a time */
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
- tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
- tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
/*
* Peripheral base
*/
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
tlbtab_end
tlbtab_start
/* vxWorks needs this as first entry for the Machine Check interrupt */
- tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
/*
* The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
#ifndef CONFIG_SYS_RAMBOOT
/* TLB-entry for DDR SDRAM (Up to 2GB) */
#ifdef CONFIG_4xx_DCACHE
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
#else
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
#endif
#endif /* CONFIG_SYS_RAMBOOT */
/* TLB-entry for EBC */
- tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
#endif
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
#endif
/* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
/* TLB-entry for NAND */
- tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
/* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
/*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
/* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
/* TLB-entry PCI IO Space - from sr@denx.de */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
tlbtab_end
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
extern void denali_core_search_data_eye(void);
#if defined(CONFIG_NAND_SPL)
-/* Using arch/ppc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
*(.text)
*(.got1)
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-#define _256M 0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_8M 0x00000060
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
/**************************************************************************
* TLB TABLE
*
tlbtab:
tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
tlbtab_end
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_8M 0x00000060
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/**************************************************************************
* TLB TABLE
*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
/* PCI */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
/* USB 2.0 Device */
- tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
tlbtab_end
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
* routine.
*/
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
- tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
- tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
tlbtab_end
/**************************************************************************
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
* routine.
*/
- tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
- tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
+ tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
- tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
- tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
tlbtab_end
}
/*
- * Override the default functions in arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
static int ppc440spe_rev_a(void)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
board/amirix/ap1000/init.o (.text)
- arch/ppc/cpu/ppc4xx/kgdb.o (.text)
- arch/ppc/cpu/ppc4xx/traps.o (.text)
- arch/ppc/cpu/ppc4xx/interrupts.o (.text)
- arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
- arch/ppc/cpu/ppc4xx/speed.o (.text)
+ arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
+ arch/powerpc/cpu/ppc4xx/traps.o (.text)
+ arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
+ arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/powerpc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
/* . = env_offset;*/
/*
* COM1 NS16550 support
- * originally from linux source (arch/ppc/boot/ns16550.c)
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
* modified to use CONFIG_SYS_ISA_MEM and new defines
*/
/*
* NS16550 Serial Port
- * originally from linux source (arch/ppc/boot/ns16550.h)
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
* modified slightly to
* have addresses as offsets from CONFIG_SYS_ISA_BASE
* added a few more definitions
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc5xxx/start.o (.text)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
common/env_embedded.o(.text)
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in arch/ppc/cpu/ppc4xx
+ * in arch/powerpc/cpu/ppc4xx
*/
sdram_init();
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in arch/ppc/cpu/ppc4xx
+ * in arch/powerpc/cpu/ppc4xx
*/
sdram_init();
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in arch/ppc/cpu/ppc4xx
+ * in arch/powerpc/cpu/ppc4xx
*/
sdram_init();
*************************************************************************/
/*
* based on Linux code
- * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
+ * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
* This program is free software; you can redistribute it and/or
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
. = env_offset;
common/env_embedded.o(.text)
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
#endif
/* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
/* TLB-entry for PCI IO */
- tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
/* TLB-entries for EBC: CPLD, DUMEM, DUIO */
- tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
/* TLB-entry for NAND */
- tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
/* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
/* TLB-entry PCI registers */
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
/* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
tlbtab_end
* speed up boot process. It is patched after relocation to enable SA_I
*/
#ifndef CONFIG_NAND_SPL
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
#else
- tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
#endif
/* TLB entries for DDR2 SDRAM are generated dynamically */
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
#endif
/* TLB-entry for PCI Memory */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
/* TLB-entries for EBC */
/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
* This dummy entry is only for convinience in order not to modify the
* amount of entries. Currently OS/9 relies on this :-)
*/
- tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
/* TLB-entry for NAND */
- tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
/* TLB-entry for Internal Registers & OCM */
- tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
+ tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
/*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
/* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
/* TLB-entry PCI IO space */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
/* TODO: what about high IO space */
tlbtab_end
*/
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
+#define TLB02 TLB2(AC_RWX | SA_IG)
.globl reconfig_tlb0
reconfig_tlb0:
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
/* Align to next NAND block */
. = ALIGN(0x4000);
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/cpu/mpc8xx/serial.o (.text)
- arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
- arch/ppc/cpu/mpc8xx/speed.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/cpu/mpc8xx/serial.o (.text)
+ arch/powerpc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/powerpc/cpu/mpc8xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/cpu/mpc8xx/cpu.o (.text)
- arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
- arch/ppc/cpu/mpc8xx/speed.o (.text)
- arch/ppc/cpu/mpc8xx/serial.o (.text)
- arch/ppc/lib/extable.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/cpu/mpc8xx/cpu.o (.text)
+ arch/powerpc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/powerpc/cpu/mpc8xx/speed.o (.text)
+ arch/powerpc/cpu/mpc8xx/serial.o (.text)
+ arch/powerpc/lib/extable.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/string.o (.text)
lib/crc32.o (.text)
common/dlmalloc.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
/*. = DEFINED(env_offset) ? env_offset : .;*/
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
+/* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */
+static struct fb_videomode fsl_diu_mode_800 = {
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 31250,
+ .left_margin = 86,
+ .right_margin = 42,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .hsync_len = 128,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
/*
* These parameters give default parameters
* for video output 1024x768,
disable_lcdc();
- if (xres == 1280) {
+ switch (xres) {
+ case 800:
+ fsl_diu_mode_db = &fsl_diu_mode_800;
+ break;
+ case 1280:
fsl_diu_mode_db = &fsl_diu_mode_1280;
- } else {
+ break;
+ default:
fsl_diu_mode_db = &fsl_diu_mode_1024;
}
b = *bitmap++;
for (k = 0; k < 8; k++) {
if (b & 0x80)
- *fb_t = palette[1];
+ *fb_t++ = palette[1];
else
- *fb_t = palette[0];
+ *fb_t++ = palette[0];
b = b << 1;
}
}
* We will over-ride the env_init called in board_init_f
* This is really a work-around because, the HLP bank 1
* where NVRAM resides is not visible during board_init_f
- * (arch/ppc/lib/board.c)
+ * (arch/powerpc/lib/board.c)
* Alternatively, we could use the I2C EEPROM at start-up to configure
* and enable all HLP banks and not just HLP 0 as is being done for
* Taiga Rev. 2.
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
#include <spd_sdram.h>
#include <tsec.h>
#include <libfdt.h>
#include <i2c.h>
#include <fdt_support.h>
#include <asm/fsl_i2c.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
static struct pci_region pci_regions[] = {
{
#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <vsc7385.h>
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc86xx/start.o (.text)
- arch/ppc/cpu/mpc86xx/traps.o (.text)
- arch/ppc/cpu/mpc86xx/interrupts.o (.text)
- arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
- arch/ppc/cpu/mpc86xx/cpu.o (.text)
- arch/ppc/cpu/mpc86xx/speed.o (.text)
+ arch/powerpc/cpu/mpc86xx/start.o (.text)
+ arch/powerpc/cpu/mpc86xx/traps.o (.text)
+ arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu.o (.text)
+ arch/powerpc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
*(.text)
*(.got1)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc86xx/start.o (.text)
- arch/ppc/cpu/mpc86xx/traps.o (.text)
- arch/ppc/cpu/mpc86xx/interrupts.o (.text)
- arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
- arch/ppc/cpu/mpc86xx/cpu.o (.text)
- arch/ppc/cpu/mpc86xx/speed.o (.text)
+ arch/powerpc/cpu/mpc86xx/start.o (.text)
+ arch/powerpc/cpu/mpc86xx/traps.o (.text)
+ arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu.o (.text)
+ arch/powerpc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
drivers/bios_emulator/atibios.o (.text)
*(.text)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_pci_board_setup(void *blob);
+
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
base = getenv_bootm_low();
size = getenv_bootm_size();
+ ft_pci_board_setup(blob);
+
fdt_fixup_memory(blob, (u64)base, (u64)size);
}
#endif
* the speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
- 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+ 0, AC_RWX | SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
- 0, AC_R|AC_W|AC_X|SA_G )
+ 0, AC_RWX | SA_G )
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
- 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ 0, AC_RWX | SA_IG )
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
- 0, AC_R|AC_W|SA_G|SA_I )
+ 0, AC_RW | SA_IG )
/* PCI */
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
- 0, AC_R|AC_W|SA_G|SA_I )
+ 0, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
- 0, AC_R|AC_W|SA_G|SA_I )
+ 0, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
- 0, AC_R|AC_W|SA_G|SA_I )
+ 0, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
- 0, AC_R|AC_W|SA_G|SA_I )
+ 0, AC_RW | SA_IG )
tlbtab_end
* enable SA_I
*/
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
- 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+ 4, AC_RWX | SA_G) /* TLB 0 */
/*
* TLB entries for SDRAM are not needed on this platform.
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
- 0, AC_R|AC_W|AC_X|SA_G)
+ 0, AC_RWX | SA_G)
#endif
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
- AC_R|AC_W|SA_G|SA_I)
+ AC_RW | SA_IG)
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
- AC_R|AC_W|SA_G|SA_I)
+ AC_RW | SA_IG)
/* TLB-entry for NVRAM */
tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
- AC_R|AC_W|SA_G|SA_I)
+ AC_RW | SA_IG)
/* TLB-entry for UART */
tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
- AC_R|AC_W|SA_G|SA_I)
+ AC_RW | SA_IG)
/* TLB-entry for IO */
tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
- AC_R|AC_W|SA_G|SA_I)
+ AC_RW | SA_IG)
/* TLB-entry for OCM */
tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
- AC_R|AC_W|AC_X|SA_I)
+ AC_RWX | SA_I)
/* TLB-entry for Local Configuration registers => peripherals */
tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
- 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+ 4, AC_RWX | SA_IG)
/* AHB: Internal USB Peripherals (USB, SATA) */
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
- AC_R|AC_W|AC_X|SA_G|SA_I)
+ AC_RWX | SA_IG)
tlbtab_end
/*
* Configure the MPC8XX I/O ports per the ioport configuration table
- * (taken from ./arch/ppc/cpu/mpc8260/cpu_init.c)
+ * (taken from ./arch/powerpc/cpu/mpc8260/cpu_init.c)
*/
void config_mpc8xx_ioports (volatile immap_t * immr)
{
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o(.text)
+ arch/powerpc/cpu/mpc8xx/start.o(.text)
*(.text)
common/env_embedded.o(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/lib/time.o (.text)
- arch/ppc/lib/ticks.o (.text)
- arch/ppc/lib/cache.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/lib/time.o (.text)
+ arch/powerpc/lib/ticks.o (.text)
+ arch/powerpc/lib/cache.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/lib/time.o (.text)
- arch/ppc/lib/ticks.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/lib/time.o (.text)
+ arch/powerpc/lib/ticks.o (.text)
. = env_offset;
common/env_embedded.o(.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8260/start.o (.text)
+ arch/powerpc/cpu/mpc8260/start.o (.text)
/*
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
/*
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/lib/time.o (.text)
- arch/ppc/lib/ticks.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/lib/time.o (.text)
+ arch/powerpc/lib/ticks.o (.text)
/**
. = env_offset;
common/env_embedded.o(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/lib/time.o (.text)
- arch/ppc/lib/ticks.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/lib/time.o (.text)
+ arch/powerpc/lib/ticks.o (.text)
/**
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
#endif
/*
- * This function is also called by arch/ppc/lib/board.c:board_init_f (it is
+ * This function is also called by arch/powerpc/lib/board.c:board_init_f (it is
* also in the init_sequence array) but later. Many more things are
* configured, but we are still running from flash.
*/
/* **** No more functions called by board_init_f. **** */
/*
- * This function is called by arch/ppc/lib/board.c:board_init_r. At this
+ * This function is called by arch/powerpc/lib/board.c:board_init_r. At this
* point, basic setup is done, U-Boot has been moved into SDRAM and
* PCI has been set up. From here we done late setup.
*/
/*
* this is even after checkboard. It returns the size of the SDRAM
* that we have installed. This function is called by board_init_f
- * in arch/ppc/lib/board.c to initialize the memory and return what I
+ * in arch/powerpc/lib/board.c to initialize the memory and return what I
* found.
*/
phys_size_t initdram (int board_type)
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c.
+ * Based in part on arch/powerpc/cpu/mpc8260/ether_scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on arch/ppc/cpu/mpc8xx/scc.c.
+ * Based in part on arch/powerpc/cpu/mpc8xx/scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
- * Based in part on arch/ppc/cpu/mpc8260/ether_scc.c.
+ * Based in part on arch/powerpc/cpu/mpc8260/ether_scc.c.
*
* See file CREDITS for list of people who contributed to this
* project.
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
/*
* TLB entries for SDRAM are not needed on this platform. They are
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
- AC_R|AC_W|AC_X|SA_G )
+ AC_RWX | SA_G )
#endif
/* TLB-entry for PCI Memory */
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
+ CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
+ CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
+ CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
- CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
+ CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
/* TLB-entry for EBC */
- tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
/* TLB-entry for Internal Registers & OCM */
/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
- tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
+ tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
/*TLB-entry PCI registers*/
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
/* TLB-entry for peripherals */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
/* TLB-entry PCI IO Space - from sr@denx.de */
- tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
tlbtab_end
.bootpg 0xF7FBF000 :
{
- arch/ppc/cpu/ppc4xx/start.o (.bootpg)
+ arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
/*
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
/*
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
- * This file was adapted from arch/ppc/cpu/mpc5xxx/serial.c
+ * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c
*
*/
N(n), \
U(n), \
quad_init_##n, \
+ NULL, \
quad_setbrg_##n, \
quad_getc_##n, \
quad_tstc_##n, \
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
#endif
/* TLB-entry for PCI Memory */
- tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
/* TLB-entry for the FPGA Chip select 2 */
- tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+ tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
/* TLB-entry for the FPGA Chip select 3 */
- tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
+ tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
/* TLB-entry for the LIME Controller */
- tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
- tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
+ tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
/* TLB-entry for Internal Registers & OCM */
- tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I)
+ tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
/*TLB-entry PCI registers*/
- tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
/* TLB-entry for peripherals */
- tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
tlbtab_end
{
/* WARNING - the following is hand-optimized to fit within */
/* the first two sectors (=8KB) of our S29GL flash chip */
- cpu/mpc5xxx/start.o (.text)
- cpu/mpc5xxx/traps.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/cache.o (.text)
- lib_ppc/time.o (.text)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text)
+ arch/powerpc/cpu/mpc5xxx/traps.o (.text)
+ lib/crc32.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
/* This is only needed to force failure if size of above code will ever */
/* increase and grow into reserved space. */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
- * Code in faintly related to linux/arch/ppc/8xx_io:
+ * Code in faintly related to linux/arch/powerpc/8xx_io:
* MPC8xx CPM I2C interface. Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
*
* This file implements functions to read the MBX's Vital Product Data
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
board/ml2/init.o (.text)
- arch/ppc/cpu/ppc4xx/kgdb.o (.text)
- arch/ppc/cpu/ppc4xx/traps.o (.text)
- arch/ppc/cpu/ppc4xx/interrupts.o (.text)
- arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
- arch/ppc/cpu/ppc4xx/speed.o (.text)
+ arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
+ arch/powerpc/cpu/ppc4xx/traps.o (.text)
+ arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
+ arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/powerpc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
/* . = env_offset;*/
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc824x/start.o (.text)
- arch/ppc/lib/board.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/cpu/mpc824x/start.o (.text)
+ arch/powerpc/lib/board.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
PROVIDE(_f_init_rom = .);
.init : {
- arch/ppc/cpu/mpc824x/start.o (.text)
+ arch/powerpc/cpu/mpc824x/start.o (.text)
*(.init)
} > ram
_init_size = SIZEOF(.init);
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc824x/start.o (.text)
+ arch/powerpc/cpu/mpc824x/start.o (.text)
common/board.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
common/env_embedded.o(.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot.lds
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc5xxx/start.o (.text)
+ arch/powerpc/cpu/mpc5xxx/start.o (.text)
*(.text)
*(.got1)
. = ALIGN(16);
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
*(.text)
*(.got1)
}
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
Startup sequence
----------------
-(arch/ppc/cpu/ppc4xx/resetvec.S)
+(arch/powerpc/cpu/ppc4xx/resetvec.S)
depending on configs option
call _start_440 _start_pci oder _start
-(arch/ppc/cpu/ppc4xx/start.S)
+(arch/powerpc/cpu/ppc4xx/start.S)
_start_440:
initialize register like
call cpu_init_f /* run low-level CPU init code (from Flash) */
call cpu_init_f
- board_init_f: (arch/ppc/lib\board.c)
+ board_init_f: (arch/powerpc/lib\board.c)
init_sequence defines a list of function to be called
board_early_init_f: (board/netstal/hcu5/hcu5.c)
We are using Bootstrap-Option A
* - board info struct
Save local variables to board info struct
call relocate_code() does not return
- relocate_code: (arch/ppc/cpu/ppc4xx/start.S)
+ relocate_code: (arch/powerpc/cpu/ppc4xx/start.S)
-------------------------------------------------------
From now on our copy is in RAM and we will run from there,
starting with board_init_r
-------------------------------------------------------
- board_init_r: (arch/ppc/lib\board.c)
+ board_init_r: (arch/powerpc/lib\board.c)
setup bd function pointers
trap_init
flash_init: (board/netstal/hcu5/flash.c)
/* setup for u-boot erase, update */
setup bd flash info
- cpu_init_r: (arch/ppc/cpu/ppc4xx/cpu_init.c)
+ cpu_init_r: (arch/powerpc/cpu/ppc4xx/cpu_init.c)
peripheral chip select in using defines like
CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
mem_malloc_init
Most of the HW specific code for the HCU5 may be found in
include/configs/hcu5.h
board/netstal/hcu5/*
-arch/ppc/cpu/ppc4xx/*
-arch/ppc/lib/*
+arch/powerpc/cpu/ppc4xx/*
+arch/powerpc/lib/*
include/ppc440.h
Drivers for serial etc are found under drivers/
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
tlbtab_start
/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
- tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
- AC_R|AC_W|AC_X|SA_G|SA_I )
+ AC_RWX | SA_IG )
/* TLB#2: TLB-entry for EBC */
- tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
/*
* TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
* to enable SA_I
*/
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
- AC_R|AC_W|AC_X|SA_G)
+ AC_RWX | SA_G)
/*
* TLB entries for SDRAM are not needed on this platform.
/* TLB#4: */
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
- AC_R|AC_W|SA_G|SA_I )
+ AC_RW | SA_IG )
/* TLB#5: */
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
- AC_R|AC_W|SA_G|SA_I )
+ AC_RW | SA_IG )
/* TLB#6: */
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
- AC_R|AC_W|SA_G|SA_I )
+ AC_RW | SA_IG )
/* TLB-entry for Internal Registers & OCM */
/* TLB#7: */
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
- AC_R|AC_W|AC_X|SA_G|SA_I )
+ AC_RWX | SA_IG )
/*TLB-entry PCI registers*/
/* TLB#8: */
- tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
/* TLB-entry for peripherals */
/* TLB#9: */
- tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
/* CAN */
/* TLB#10: */
- tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
/* TLB#11: CPLD and IMC-Standard 32 MB */
- tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
/* TLB#12: */
tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
- AC_R|AC_W|AC_X|SA_G|SA_I )
+ AC_RWX | SA_IG )
/* IMC-Fast 32 MB */
/* TLB#13: */
- tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
/* TLB#14: */
tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
- AC_R|AC_W|AC_X|SA_G|SA_I )
+ AC_RWX | SA_IG )
tlbtab_end
/*
* This function is run very early, out of flash, and before devices are
- * initialized. It is called by arch/ppc/lib/board.c:board_init_f by virtue
+ * initialized. It is called by arch/powerpc/lib/board.c:board_init_f by virtue
* of being in the init_sequence array.
*
* The SDRAM has been initialized already -- start.S:start called
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_8M 0x00000060
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/**************************************************************************
* TLB TABLE
*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
- tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+ tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
/*
* TLB entries for SDRAM are not needed on this platform.
* routine.
*/
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
/* PCI */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
/* USB 2.0 Device */
- tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
tlbtab_end
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
/*--------------------------------------------------------------------
- * GPIO's are alreay setup in arch/ppc/cpu/ppc4xx/cpu_init.c
+ * GPIO's are alreay setup in arch/powerpc/cpu/ppc4xx/cpu_init.c
* via define from board config file.
*-------------------------------------------------------------------*/
--- /dev/null
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2009
+# Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xF0000000
--- /dev/null
+/*
+ * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
+ *
+ * (C) Copyright 2009-2010
+ * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#include <flash.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <serial.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];
+ulong flash_get_size (phys_addr_t base, int banknum);
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_SPDIF_EN | \
+ CLOCK_SCCR2_DIU_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
+int board_early_init_f(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * Initialize Local Window for FLASH-Bank1 access (CS1)
+ */
+ out_be32(&im->sysconf.lpcs1aw,
+ CSAW_START(CONFIG_SYS_FLASH1_BASE) |
+ CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE)
+ );
+ out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+
+ /*
+ * Local Window for MRAM access (CS2)
+ */
+ out_be32(&im->sysconf.lpcs2aw,
+ CSAW_START(CONFIG_SYS_MRAM_BASE) |
+ CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE)
+ );
+ out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+
+ sync_law(&im->sysconf.lpcs2aw);
+
+ /*
+ * Configure Flash Speed
+ */
+ out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+ out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+ /*
+ * Enable clocks
+ */
+ out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+ out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+ setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+ return 0;
+}
+
+sdram_conf_t mddrc_config[] = {
+ {
+ (512 << 20), /* 512 MB RAM configuration */
+ {
+ CONFIG_SYS_MDDRC_SYS_CFG,
+ CONFIG_SYS_MDDRC_TIME_CFG0,
+ CONFIG_SYS_MDDRC_TIME_CFG1,
+ CONFIG_SYS_MDDRC_TIME_CFG2
+ }
+ },
+ {
+ (128 << 20), /* 128 MB RAM configuration */
+ {
+ CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
+ CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
+ CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
+ CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
+ }
+ },
+};
+
+phys_size_t initdram (int board_type)
+{
+ int i;
+ u32 msize = 0;
+ u32 pdm360ng_init_seq[] = {
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_MICRON_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_NOP,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_EM2,
+ CONFIG_SYS_DDRCMD_EM3,
+ CONFIG_SYS_DDRCMD_EN_DLL,
+ CONFIG_SYS_DDRCMD_RES_DLL,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_DDRCMD_RFSH,
+ CONFIG_SYS_MICRON_INIT_DEV_OP,
+ CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+ CONFIG_SYS_DDRCMD_OCD_EXIT,
+ CONFIG_SYS_DDRCMD_PCHG_ALL,
+ CONFIG_SYS_DDRCMD_NOP
+ };
+
+ for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
+ msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
+ ARRAY_SIZE(pdm360ng_init_seq));
+ if (msize == mddrc_config[i].size)
+ break;
+ }
+
+ return msize;
+}
+
+#if defined(CONFIG_SERIAL_MULTI)
+static int set_lcd_brightness(char *);
+#endif
+
+int misc_init_r(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ /*
+ * Re-configure flash setup using auto-detected info
+ */
+ if (flash_info[1].size > 0) {
+ out_be32(&im->sysconf.lpcs1aw,
+ CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
+ CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
+ flash_info[1].size));
+ sync_law(&im->sysconf.lpcs1aw);
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
+ } else {
+ /* Disable Bank 1 */
+ out_be32(&im->sysconf.lpcs1aw, 0x01000100);
+ sync_law(&im->sysconf.lpcs1aw);
+ }
+
+ out_be32(&im->sysconf.lpcs0aw,
+ CSAW_START(gd->bd->bi_flashstart) |
+ CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
+ sync_law(&im->sysconf.lpcs0aw);
+
+ /*
+ * Re-check to get correct base address
+ */
+ flash_get_size (gd->bd->bi_flashstart, 0);
+
+ /*
+ * Re-do flash protection upon new addresses
+ */
+ flash_protect (FLAG_PROTECT_CLEAR,
+ gd->bd->bi_flashstart, 0xffffffff,
+ &flash_info[0]);
+
+ /* Monitor protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_SYS_MONITOR_BASE,
+ CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+ &flash_info[0]);
+
+ /* Environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+ /* Redundant environment protection ON by default */
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR_REDUND,
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[0]);
+#endif
+
+#ifdef CONFIG_FSL_DIU_FB
+# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+ mpc5121_diu_init();
+#endif
+#if defined(CONFIG_SERIAL_MULTI)
+ set_lcd_brightness(0);
+#endif
+ /* Switch LCD-Backlight and LVDS-Interface on */
+ setbits_be32(&im->gpio.gpdir, 0x01040000);
+ clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
+#endif
+
+#if defined(CONFIG_HARD_I2C)
+ if (!getenv("ethaddr")) {
+ uchar buf[6];
+ uchar ifm_oui[3] = { 0, 2, 1, };
+ int ret;
+
+ /* I2C-0 for on-board eeprom */
+ i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
+
+ /* Read ethaddr from EEPROM */
+ ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
+ if (ret != 0) {
+ printf("Error: Unable to read MAC from I2C"
+ " EEPROM at address %02X:%02X\n",
+ CONFIG_SYS_I2C_EEPROM_ADDR,
+ CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
+ return 1;
+ }
+
+ /* Owned by IFM ? */
+ if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
+ printf("Illegal MAC address in EEPROM: %pM\n", buf);
+ return 1;
+ }
+
+ eth_setenv_enetaddr("ethaddr", buf);
+ }
+#endif /* defined(CONFIG_HARD_I2C) */
+
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /* FUNC1=LPC_CS4 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+ IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO10 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=CAN3_TX */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO14 */
+ {
+ offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
+ /* DIU_LD22-DIU_LD23 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
+ /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
+ /* VIU_DATA0-VIU_DATA2 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=FEC_TXD_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
+ /* VIU_DATA3, VIU_DATA4 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
+ /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
+ /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
+ /* DIU_LD00-DIU_LD21 */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+ },
+ /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
+ /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC2=CAN3_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* Sets lowest slew on 2 CAN_TX Pins*/
+ {
+ offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
+ /* CAN4_TX, CAN4_RX */
+ {
+ offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
+ /* GPIO8, GPIO9 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
+ /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
+ /* FEC_RXD_3, FEC_RXD_2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO17 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
+ /* GPIO2, GPIO20, GPIO21 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=VIU_PIX_CLK */
+ {
+ offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
+ /* GPIO24, GPIO25 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC1=NFC_CE2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+ IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
+ /* VIU_DATA5-VIU_DATA9 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
+ /* LPC_TSIZ1-LPC_TSIZ2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=LPC_TS */
+ {
+ offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=GPIO16 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
+ /* GPIO18-GPIO19, GPT7/GPIO7 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO0/GPT0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
+ /* GPIO11, GPIO2, GPIO12, GPIO13 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+ },
+ /* FUNC2=DIU_DE */
+ {
+ offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
+
+int checkboard (void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ puts("Board: PDM360NG\n");
+
+ /* initialize function mux & slew rate IO inter alia on IO Pins */
+
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
+ setbits_be32(&im->io_ctrl.io_control_gp,
+ (1 << 0) | /* GP_MUX7->GPIO7 */
+ (1 << 5)); /* GP_MUX2->GPIO2 */
+
+ /* configure GPIO24 (VIU_CE), output/high */
+ setbits_be32(&im->gpio.gpdir, 0x80);
+ setbits_be32(&im->gpio.gpdat, 0x80);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+ { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
+ { "cfi-flash", MTD_DEV_TYPE_NOR, },
+};
+#endif
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ u32 val[8];
+ int rc, i = 0;
+
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+ fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+ /* Fixup NOR FLASH mapping */
+ val[i++] = 0; /* chip select number */
+ val[i++] = 0; /* always 0 */
+ val[i++] = gd->bd->bi_flashstart;
+ val[i++] = gd->bd->bi_flashsize;
+
+ /* Fixup MRAM mapping */
+ val[i++] = 2; /* chip select number */
+ val[i++] = 0; /* always 0 */
+ val[i++] = CONFIG_SYS_MRAM_BASE;
+ val[i++] = CONFIG_SYS_MRAM_SIZE;
+
+ rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+ val, i * sizeof(u32), 1);
+ if (rc)
+ printf("Unable to update localbus ranges, err=%s\n",
+ fdt_strerror(rc));
+
+ /* Fixup reg property in NOR Flash node */
+ i = 0;
+ val[i++] = 0; /* always 0 */
+ val[i++] = 0; /* start at offset 0 */
+ val[i++] = flash_info[0].size; /* size of Bank 0 */
+
+ /* Second Bank available? */
+ if (flash_info[1].size > 0) {
+ val[i++] = 0; /* always 0 */
+ val[i++] = flash_info[0].size; /* offset of Bank 1 */
+ val[i++] = flash_info[1].size; /* size of Bank 1 */
+ }
+
+ rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
+ val, i * sizeof(u32), 1);
+ if (rc)
+ printf("Unable to update flash reg property, err=%s\n",
+ fdt_strerror(rc));
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#if defined(CONFIG_SERIAL_MULTI)
+/*
+ * If argument is NULL, set the LCD brightness to the
+ * value from "brightness" environment variable. Set
+ * the LCD brightness to the value specified by the
+ * argument otherwise. Default brightness is zero.
+ */
+#define MAX_BRIGHTNESS 99
+static int set_lcd_brightness(char *brightness)
+{
+ struct stdio_dev *cop_port;
+ char *env;
+ char cmd_buf[20];
+ int val = 0;
+ int cs = 0;
+ int len, i;
+
+ if (brightness) {
+ val = simple_strtol(brightness, NULL, 10);
+ } else {
+ env = getenv("brightness");
+ if (env)
+ val = simple_strtol(env, NULL, 10);
+ }
+
+ if (val < 0)
+ val = 0;
+
+ if (val > MAX_BRIGHTNESS)
+ val = MAX_BRIGHTNESS;
+
+ sprintf(cmd_buf, "$SB;%04d;", val);
+
+ len = strlen(cmd_buf);
+ for (i = 1; i <= len; i++)
+ cs += cmd_buf[i];
+
+ cs = (~cs + 1) & 0xff;
+ sprintf(cmd_buf + len, "%02X\n", cs);
+
+ /* IO Coprocessor communication */
+ cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+ if (!cop_port) {
+ printf("Error: Can't open IO Coprocessor port.\n");
+ return -1;
+ }
+
+ debug("%s: cmd: %s", __func__, cmd_buf);
+ write_port(cop_port, cmd_buf);
+ /*
+ * Wait for transmission and maybe response data
+ * before closing the port.
+ */
+ udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+ memset(cmd_buf, 0, sizeof(cmd_buf));
+ len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
+ if (len)
+ printf("Error: %s\n", cmd_buf);
+
+ close_port(4);
+
+ return 0;
+}
+
+static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[])
+{
+ if (argc < 2) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ return set_lcd_brightness(argv[1]);
+}
+
+U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
+ "set LCD brightness",
+ "<brightness> - set LCD backlight level to <brightness>.\n"
+);
+#endif /* CONFIG_SERIAL_MULTI */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/**************************************************************************
* TLB TABLE
*
tlbtab:
tlbtab_start
- tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
+ tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
+ tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
#ifdef CONFIG_4xx_DCACHE
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
+ tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
#else
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
#endif
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
#endif
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+ tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
/* PCI */
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
+ tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
/* NAND */
- tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+ tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
tlbtab_end
*************************************************************************/
/*
* based on Linux code
- * arch/ppc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
+ * arch/powerpc/galileo/EVB64460/mv64460_eth.c - Driver for MV64460X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
* This program is free software; you can redistribute it and/or
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/74xx_7xx/start.o (.text)
+ arch/powerpc/cpu/74xx_7xx/start.o (.text)
/* store the environment in a seperate sector in the boot flash */
/* . = env_offset; */
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/**************************************************************************
* TLB TABLE
*
tlbtab:
tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX )
+ tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX )
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
tlbtab_end
+++ /dev/null
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-OUTPUT_FORMAT("elf32-littlenios2")
-OUTPUT_ARCH(nios2)
-ENTRY(_start)
-
-SECTIONS
-{
- .text :
- {
- arch/nios/cpu2/start.o (.text)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t*)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.gnu.linkonce.r*)
- }
- . = ALIGN (4);
- _etext = .;
- PROVIDE (etext = .);
-
- /* CMD TABLE - sandwich this in between text and data so
- * the initialization code relocates the command table as
- * well -- admittedly, this is just pure laziness ;-)
- */
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
- . = ALIGN(4);
- __u_boot_cmd_end = .;
-
- /* INIT DATA sections - "Small" data (see the gcc -G option)
- * is always gp-relative. Here we make all init data sections
- * adjacent to simplify the startup code -- and provide
- * the global pointer for gp-relative access.
- */
- _data = .;
- .data :
- {
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d*)
- }
-
- . = ALIGN(16);
- _gp = .; /* Global pointer addr */
- PROVIDE (gp = .);
-
- .sdata :
- {
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- }
- . = ALIGN(4);
-
- _edata = .;
- PROVIDE (edata = .);
-
- /* UNINIT DATA - Small uninitialized data is first so it's
- * adjacent to sdata and can be referenced via gp. The normal
- * bss follows. We keep it adjacent to simplify init code.
- */
- __bss_start = .;
- .sbss (NOLOAD) :
- {
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- }
- . = ALIGN(4);
- .bss (NOLOAD) :
- {
- *(.bss)
- *(.bss.*)
- *(.dynbss)
- *(COMMON)
- *(.scommon)
- }
- . = ALIGN(4);
- _end = .;
- PROVIDE (end = .);
-
- /* DEBUG -- symbol table, string table, etc. etc.
- */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_info 0 : { *(.debug_info) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
+++ /dev/null
-/*
- * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-OUTPUT_FORMAT("elf32-littlenios2")
-OUTPUT_ARCH(nios2)
-ENTRY(_start)
-
-SECTIONS
-{
- .text :
- {
- arch/nios/cpu2/start.o (.text)
- *(.text)
- *(.text.*)
- *(.gnu.linkonce.t*)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- *(.gnu.linkonce.r*)
- }
- . = ALIGN (4);
- _etext = .;
- PROVIDE (etext = .);
-
- /* CMD TABLE - sandwich this in between text and data so
- * the initialization code relocates the command table as
- * well -- admittedly, this is just pure laziness ;-)
- */
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
- . = ALIGN(4);
- __u_boot_cmd_end = .;
-
- /* INIT DATA sections - "Small" data (see the gcc -G option)
- * is always gp-relative. Here we make all init data sections
- * adjacent to simplify the startup code -- and provide
- * the global pointer for gp-relative access.
- */
- _data = .;
- .data :
- {
- *(.data)
- *(.data.*)
- *(.gnu.linkonce.d*)
- }
-
- . = ALIGN(16);
- _gp = .; /* Global pointer addr */
- PROVIDE (gp = .);
-
- .sdata :
- {
- *(.sdata)
- *(.sdata.*)
- *(.gnu.linkonce.s.*)
- }
- . = ALIGN(4);
-
- _edata = .;
- PROVIDE (edata = .);
-
- /* UNINIT DATA - Small uninitialized data is first so it's
- * adjacent to sdata and can be referenced via gp. The normal
- * bss follows. We keep it adjacent to simplify init code.
- */
- __bss_start = .;
- .sbss (NOLOAD) :
- {
- *(.sbss)
- *(.sbss.*)
- *(.gnu.linkonce.sb.*)
- *(.scommon)
- }
- . = ALIGN(4);
- .bss (NOLOAD) :
- {
- *(.bss)
- *(.bss.*)
- *(.dynbss)
- *(COMMON)
- *(.scommon)
- }
- . = ALIGN(4);
- _end = .;
- PROVIDE (end = .);
-
- /* DEBUG -- symbol table, string table, etc. etc.
- */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- .debug_info 0 : { *(.debug_info) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
-}
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/cpu_init.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/cpu_init.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
/***
. = env_offset;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8260/start.o (.text)
+ arch/powerpc/cpu/mpc8260/start.o (.text)
*(.text)
*(.got1)
/*. = env_offset; */
*/
/*
- * Ported from arch/ppc/cpu/ppc4xx/i2c.c by AS HARNOIS by
+ * Ported from arch/powerpc/cpu/ppc4xx/i2c.c by AS HARNOIS by
* Travis B. Sawyer
* Sandburst Corporation.
*/
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/**************************************************************************
* TLB TABLE
*
tlbtab:
tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
tlbtab_end
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
board/sandburst/karef/init.o (.text)
- arch/ppc/cpu/ppc4xx/kgdb.o (.text)
- arch/ppc/cpu/ppc4xx/traps.o (.text)
- arch/ppc/cpu/ppc4xx/interrupts.o (.text)
- arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
- arch/ppc/cpu/ppc4xx/speed.o (.text)
+ arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
+ arch/powerpc/cpu/ppc4xx/traps.o (.text)
+ arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
+ arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/powerpc/cpu/ppc4xx/speed.o (.text)
drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
/* common/env_embedded.o(.text) */
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/**************************************************************************
* TLB TABLE
*
tlbtab:
tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
tlbtab_end
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
board/sandburst/metrobox/init.o (.text)
- arch/ppc/cpu/ppc4xx/kgdb.o (.text)
- arch/ppc/cpu/ppc4xx/traps.o (.text)
- arch/ppc/cpu/ppc4xx/interrupts.o (.text)
- arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
- arch/ppc/cpu/ppc4xx/speed.o (.text)
+ arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
+ arch/powerpc/cpu/ppc4xx/traps.o (.text)
+ arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
+ arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/powerpc/cpu/ppc4xx/speed.o (.text)
drivers/net/4xx_enet.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
/* common/env_embedded.o(.text) */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc86xx/start.o (.text)
- arch/ppc/cpu/mpc86xx/traps.o (.text)
- arch/ppc/cpu/mpc86xx/interrupts.o (.text)
- arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
- arch/ppc/cpu/mpc86xx/cpu.o (.text)
- arch/ppc/cpu/mpc86xx/speed.o (.text)
+ arch/powerpc/cpu/mpc86xx/start.o (.text)
+ arch/powerpc/cpu/mpc86xx/traps.o (.text)
+ arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu.o (.text)
+ arch/powerpc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
board/sc3/init.o (.text)
- arch/ppc/cpu/ppc4xx/kgdb.o (.text)
- arch/ppc/cpu/ppc4xx/traps.o (.text)
- arch/ppc/cpu/ppc4xx/interrupts.o (.text)
- arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
- arch/ppc/cpu/ppc4xx/speed.o (.text)
+ arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
+ arch/powerpc/cpu/ppc4xx/traps.o (.text)
+ arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
+ arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/powerpc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
/* . = env_offset;*/
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
- arch/ppc/cpu/mpc8xx/interrupts.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
+ arch/powerpc/cpu/mpc8xx/interrupts.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/env_embedded.o(.text)
*(.text)
*(.got1)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
#endif
/* Why is the phy reset done _after_ the ethernet
- * initialization in arch/ppc/lib/board.c?
+ * initialization in arch/powerpc/lib/board.c?
* Do it here so it's done before the TSECs are used.
*/
reset_phy();
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
. = env_offset;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
+ arch/powerpc/lib/cache.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
common/env_embedded.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
endif
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
-LDSCRIPT := $(SRCTREE)/arch/ppc/cpu/mpc5xxx/u-boot-customlayout.lds
+LDSCRIPT := $(SRCTREE)/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
- arch/ppc/cpu/mpc8xx/traps.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/traps.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
- arch/ppc/lib/cache.o (.text)
- arch/ppc/lib/time.o (.text)
+ arch/powerpc/lib/cache.o (.text)
+ arch/powerpc/lib/time.o (.text)
/*
. = env_offset;
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
common/env_embedded.o(.text)
/*
* ToDo: Move the asm init routine sdram_init() to this C file,
* or even better use some common ppc4xx code available
- * in arch/ppc/cpu/ppc4xx
+ * in arch/powerpc/cpu/ppc4xx
*/
sdram_init();
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
- arch/ppc/lib/ppcstring.o (.text)
+ arch/powerpc/lib/ppcstring.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
lib/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/mpc8xx/start.o (.text)
+ arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*/
#include <ppc_asm.tmpl>
+#include <asm/mmu.h>
#include <config.h>
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
-#define TLB1(rpn,erpn) (((rpn)&0xfffffc00) | (erpn))
-#define TLB2(a) ((a)&0x00000fbf)
-
-#define tlbtab_start \
- mflr r1; \
- bl 0f;
-
-#define tlbtab_end \
- .long 0, 0, 0; \
-0: mflr r0; \
- mtlr r1; \
- blr;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
/*
* TLB TABLE
*
tlbtab:
tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
+ tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
+ tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
+ tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
tlbtab_end
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/ppc/cpu/ppc4xx/start.o (.text)
+ arch/powerpc/cpu/ppc4xx/start.o (.text)
board/xes/xpedite1000/init.o (.text)
- arch/ppc/cpu/ppc4xx/kgdb.o (.text)
- arch/ppc/cpu/ppc4xx/traps.o (.text)
- arch/ppc/cpu/ppc4xx/interrupts.o (.text)
- arch/ppc/cpu/ppc4xx/4xx_uart.o (.text)
- arch/ppc/cpu/ppc4xx/cpu_init.o (.text)
- arch/ppc/cpu/ppc4xx/speed.o (.text)
+ arch/powerpc/cpu/ppc4xx/kgdb.o (.text)
+ arch/powerpc/cpu/ppc4xx/traps.o (.text)
+ arch/powerpc/cpu/ppc4xx/interrupts.o (.text)
+ arch/powerpc/cpu/ppc4xx/4xx_uart.o (.text)
+ arch/powerpc/cpu/ppc4xx/cpu_init.o (.text)
+ arch/powerpc/cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
/* common/env_embedded.o(.text) */
.plt : { *(.plt) }
.text :
{
- arch/ppc/cpu/mpc86xx/start.o (.text)
- arch/ppc/cpu/mpc86xx/traps.o (.text)
- arch/ppc/cpu/mpc86xx/interrupts.o (.text)
- arch/ppc/cpu/mpc86xx/cpu_init.o (.text)
- arch/ppc/cpu/mpc86xx/cpu.o (.text)
- arch/ppc/cpu/mpc86xx/speed.o (.text)
+ arch/powerpc/cpu/mpc86xx/start.o (.text)
+ arch/powerpc/cpu/mpc86xx/traps.o (.text)
+ arch/powerpc/cpu/mpc86xx/interrupts.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu_init.o (.text)
+ arch/powerpc/cpu/mpc86xx/cpu.o (.text)
+ arch/powerpc/cpu/mpc86xx/speed.o (.text)
common/dlmalloc.o (.text)
lib/crc32.o (.text)
- arch/ppc/lib/extable.o (.text)
+ arch/powerpc/lib/extable.o (.text)
lib/zlib.o (.text)
*(.text)
*(.got1)
puts("*");
}
-void fsl_init2 (void) {
+int fsl_init2 (void) {
puts("fsl_init2\n");
- install_interrupt_handler (FSL_INTR_2,\
- fsl_isr2,\
- NULL);
+ install_interrupt_handler (FSL_INTR_2, fsl_isr2, NULL);
+ return 0;
}
#endif
.bootpg 0xFFFFF000 :
{
- arch/ppc/cpu/ppc4xx/start.o (.bootpg)
+ arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
.bootpg 0xFFFFF000 :
{
- arch/ppc/cpu/ppc4xx/start.o (.bootpg)
+ arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
-/* taken from arch/ppc/kernel/ppc-stub.c */
+/* taken from arch/powerpc/kernel/ppc-stub.c */
/****************************************************************************
#else
return &serial0_device;
#endif
+#elif defined(CONFIG_MPC512X)
+#if (CONFIG_PSC_CONSOLE == 3)
+ return &serial3_device;
+#elif (CONFIG_PSC_CONSOLE == 6)
+ return &serial6_device;
+#else
+#error "Bad CONFIG_PSC_CONSOLE."
+#endif
#elif defined(CONFIG_S3C2410)
#if defined(CONFIG_SERIAL1)
return &s3c24xx_serial0_device;
serial_register(&s5p_serial1_device);
serial_register(&s5p_serial2_device);
serial_register(&s5p_serial3_device);
+#endif
+#if defined(CONFIG_MPC512X)
+#if defined(CONFIG_SYS_PSC1)
+ serial_register(&serial1_device);
+#endif
+#if defined(CONFIG_SYS_PSC3)
+ serial_register(&serial3_device);
+#endif
+#if defined(CONFIG_SYS_PSC4)
+ serial_register(&serial4_device);
+#endif
+#if defined(CONFIG_SYS_PSC6)
+ serial_register(&serial6_device);
+#endif
#endif
serial_assign (default_serial_console ()->name);
}
dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
dev.start = s->init;
+ dev.stop = s->uninit;
dev.putc = s->putc;
dev.puts = s->puts;
dev.getc = s->getc;
$ make oldconfig
$ make dep
$ make uImage
- $ cp -p arch/ppc/mbxboot/uImage /tftpboot
+ $ cp -p arch/powerpc/mbxboot/uImage /tftpboot
Load uImage via tftp and boot it.
added console settings from environment
- common/devices.c added ISA keyboard init
- common/main.c corrected the read of bootdelay
-- arch/ppc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405
-- arch/ppc/cpu/ppc4xx/i2c.c added 16bit read write I2C support
+- arch/powerpc/cpu/ppc4xx/405gp_pci.c excluded file from PIP405
+- arch/powerpc/cpu/ppc4xx/i2c.c added 16bit read write I2C support
added page write
-- arch/ppc/cpu/ppc4xx/speed.c added get_PCI_freq
-- arch/ppc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
+- arch/powerpc/cpu/ppc4xx/speed.c added get_PCI_freq
+- arch/powerpc/cpu/ppc4xx/start.S added CONFIG_IDENT_STRING
- disk/Makefile added part_iso for CD support
- disk/part.c changed to work with block device description
added ISO CD support
"U_BOOT_VERSION __TIME__ DATE___ " String, to allows to identify intermidiate
and custom versions.
Changed files:
-- arch/ppc/cpu/ppc4xx/start.s
+- arch/powerpc/cpu/ppc4xx/start.s
Firmware Image:
---------------
Correct PCI Frequency for PPC405:
---------------------------------
-Added function (in arch/ppc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
+Added function (in arch/powerpc/cpu/ppc4xx/speed.c) to get the PCI frequency for PPC405 CPU.
The PCI Frequency will now be set correct in the board description in common/board.c.
(was set to the busfreq before).
Changed files:
-- arch/ppc/cpu/ppc4xx/speed.c
+- arch/powerpc/cpu/ppc4xx/speed.c
- common/board.c
I2C Stuff:
Added 16bit read/write support for I2C (PPC405), and page write to
I2C EEPROM if defined CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE.
Changed files:
-- arch/ppc/cpu/ppc4xx/i2c.c
+- arch/powerpc/cpu/ppc4xx/i2c.c
- common/cmd_i2c.c
Environment / Console:
reconfiguration of the physical interface chip.
The test routines for the SCC ethernet tests will be located in
-arch/ppc/cpu/mpc8xx/scc.c.
+arch/powerpc/cpu/mpc8xx/scc.c.
2.2.3.2. UART tests (SMC/SCC)
test will be executed manually.
The test routine for the SMC/SCC UART tests will be located in
-arch/ppc/cpu/mpc8xx/serial.c.
+arch/powerpc/cpu/mpc8xx/serial.c.
2.2.3.3. USB test
board/RPXLITE/RPXLITE.c /* DRAM-related routines */
board/RPXLITE/flash.c /* flash-related routines */
board/RPXLITE/config.mk /* set text base address */
- arch/ppc/cpu/mpc8xx/serial.c /* board specific register setting */
+ arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */
include/config_RPXLITE.h /* board specific registers */
See 'reg_config.txt' for register values in detail.
MAKEALL - TQM8260 entry added
Makefile - TQM8260_config entry added
-arch/ppc/cpu/mpc8260/Makefile - soft_i2c.o module added
-arch/ppc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
+arch/powerpc/cpu/mpc8260/Makefile - soft_i2c.o module added
+arch/powerpc/cpu/mpc8260/ether_scc.c - TQM8260-specific definitions added, an obvious
bug fixed (fcr -> scr)
-arch/ppc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
+arch/powerpc/cpu/mpc8260/ether_fcc.c - TQM8260-specific definitions added
include/flash.h - added definitions for the AM29LV640D Flash chip
board/tqm8260/flash.c - flash driver (for AM29LV640D)
board/tqm8260/ppcboot.lds - linker script
board/tqm8260/tqm8260.c - ioport and memory initialization
-arch/ppc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
+arch/powerpc/cpu/mpc8260/soft_i2c.c - software i2c EEPROM driver
include/config_TQM8260.h - main configuration file
- include/asm-ppc/global_data.h added global variables - inp_clk, pci_clk,
vco_clk, pev_clk, flb_clk, and bExtUart
-- arch/ppc/lib/board.c added CONFIG_MPC8220 support
+- arch/powerpc/lib/board.c added CONFIG_MPC8220 support
- net/eth.c added FEC support for MPC8220
- board/alaska/config.mk config make
- board/alaska/u-boot.lds Linker description
-- arch/ppc/cpu/mpc8220/dma.h multi-channel dma header file
-- arch/ppc/cpu/mpc8220/dramSetup.h dram setup header file
-- arch/ppc/cpu/mpc8220/fec.h MPC8220 FEC header file
-- arch/ppc/cpu/mpc8220/cpu.c cpu specific code
-- arch/ppc/cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup
-- arch/ppc/cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup
-- arch/ppc/cpu/mpc8220/fec.c MPC8220 FEC driver
-- arch/ppc/cpu/mpc8220/i2c.c MPC8220 I2C driver
-- arch/ppc/cpu/mpc8220/interrupts.c interrupt support (not enable)
-- arch/ppc/cpu/mpc8220/loadtask.c load dma
-- arch/ppc/cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock
-- arch/ppc/cpu/mpc8220/traps.c exception
-- arch/ppc/cpu/mpc8220/uart.c MPC8220 UART driver
-- arch/ppc/cpu/mpc8220/Makefile Makefile
-- arch/ppc/cpu/mpc8220/config.mk config make
-- arch/ppc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
-- arch/ppc/cpu/mpc8220/io.S io functions
-- arch/ppc/cpu/mpc8220/start.S start up
+- arch/powerpc/cpu/mpc8220/dma.h multi-channel dma header file
+- arch/powerpc/cpu/mpc8220/dramSetup.h dram setup header file
+- arch/powerpc/cpu/mpc8220/fec.h MPC8220 FEC header file
+- arch/powerpc/cpu/mpc8220/cpu.c cpu specific code
+- arch/powerpc/cpu/mpc8220/cpu_init.c Flexbus ChipSelect and Mux pins setup
+- arch/powerpc/cpu/mpc8220/dramSetup.c MPC8220 DDR SDRAM setup
+- arch/powerpc/cpu/mpc8220/fec.c MPC8220 FEC driver
+- arch/powerpc/cpu/mpc8220/i2c.c MPC8220 I2C driver
+- arch/powerpc/cpu/mpc8220/interrupts.c interrupt support (not enable)
+- arch/powerpc/cpu/mpc8220/loadtask.c load dma
+- arch/powerpc/cpu/mpc8220/speed.c system, pci, flexbus, pev, and cpu clock
+- arch/powerpc/cpu/mpc8220/traps.c exception
+- arch/powerpc/cpu/mpc8220/uart.c MPC8220 UART driver
+- arch/powerpc/cpu/mpc8220/Makefile Makefile
+- arch/powerpc/cpu/mpc8220/config.mk config make
+- arch/powerpc/cpu/mpc8220/fec_dma_task.S MPC8220 FEC multi-channel dma program
+- arch/powerpc/cpu/mpc8220/io.S io functions
+- arch/powerpc/cpu/mpc8220/start.S start up
- include/mpc8220.h
./common/board.c
Added call to initialize debugger on startup.
-./arch/ppc/cpu/ppc4xx/Makefile
+./arch/powerpc/cpu/ppc4xx/Makefile
Added bedbug_405.c to the Makefile.
-./arch/ppc/cpu/ppc4xx/start.S
+./arch/powerpc/cpu/ppc4xx/start.S
Added code to handle the debug exception (0x2000) on the 405.
Also added code to handle critical exceptions since the debug
is treated as critical on the 405.
-./arch/ppc/cpu/ppc4xx/traps.c
+./arch/powerpc/cpu/ppc4xx/traps.c
Added more detailed output for the program exception to tell
if it is an illegal instruction, privileged instruction or
a trap. Also added debug trap handler.
hardware breakpoints and stepping through code. These
routines are common to all PowerPC processors.
-./arch/ppc/cpu/ppc4xx/bedbug_405.c
+./arch/powerpc/cpu/ppc4xx/bedbug_405.c
AMCC PPC405 specific debugger routines.
common/cmd_bedbug.c
Added call to initialize 860 debugger.
- arch/ppc/cpu/mpc8xx/Makefile
+ arch/powerpc/cpu/mpc8xx/Makefile
Added new file "bedbug_860.c" to the makefile
- arch/ppc/cpu/mpc8xx/start.S
+ arch/powerpc/cpu/mpc8xx/start.S
Added handler for InstructionBreakpoint (0xfd00)
- arch/ppc/cpu/mpc8xx/traps.c
+ arch/powerpc/cpu/mpc8xx/traps.c
Added new routine DebugException()
New Files:
- arch/ppc/cpu/mpc8xx/bedbug_860.c
+ arch/powerpc/cpu/mpc8xx/bedbug_860.c
CPU-specific routines for 860 debug registers.
u-boot-0.2.0/common/cmd_boot.c
u-boot-0.2.0/common/cmd_reginfo.c
u-boot-0.2.0/common/environment.c
-u-boot-0.2.0/arch/ppc/cpu/mpc5xx/*
+u-boot-0.2.0/arch/powerpc/cpu/mpc5xx/*
u-boot-0.2.0/include/cmd_reginfo.h
u-boot-0.2.0/include/common.h
u-boot-0.2.0/include/ppc_asm.tmpl
u-boot-0.2.0/include/status_led.h
u-boot-0.2.0/include/asm-ppc/u-boot.h
u-boot-0.2.0/include/asm-ppc/5xx_immap.h
-u-boot-0.2.0/arch/ppc/lib/board.c
-u-boot-0.2.0/arch/ppc/lib/cache.c
-u-boot-0.2.0/arch/ppc/lib/time.c
+u-boot-0.2.0/arch/powerpc/lib/board.c
+u-boot-0.2.0/arch/powerpc/lib/cache.c
+u-boot-0.2.0/arch/powerpc/lib/time.c
u-boot-0.2.0/Makefile
u-boot-0.2.0/CREDITS
u-boot-0.2.0/doc/README.mpc5xx
kernel's ppcboot.h is consistent with U-Boot's u-boot.h. You can use two
default configuration files as your starting points to configure the
kernel:
- arch/ppc/configs/mpc8540_ads_defconfig
- arch/ppc/configs/mpc8560_ads_defconfig
+ arch/powerpc/configs/mpc8540_ads_defconfig
+ arch/powerpc/configs/mpc8560_ads_defconfig
3. DEFINITIONS AND COMPILATION
#include <common.h>
#include <command.h>
#include <asm/io.h>
+#include <asm/processor.h>
#include <malloc.h>
#include <libata.h>
#include <fis.h>
/* Wait the controller offline */
ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+ /*
+ * For P1022/1013 Rev1.0 silicon, after power on SATA host
+ * controller is configured in legacy mode instead of the
+ * expected enterprise mode. software needs to clear bit[28]
+ * of HControl register to change to enterprise mode from
+ * legacy mode.
+ */
+ {
+ u32 svr = get_svr();
+ if (IS_SVR_REV(svr, 1, 0) &&
+ ((SVR_SOC_VER(svr) == SVR_P1022) ||
+ (SVR_SOC_VER(svr) == SVR_P1022_E) ||
+ (SVR_SOC_VER(svr) == SVR_P1013) ||
+ (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+ out_le32(®->hstatus, 0x20000000);
+ out_le32(®->hcontrol, 0x00000100);
+ }
+ }
+#endif
+
/* Set the command header base address to CHBA register to tell DMA */
out_le32(®->chba, (u32)cmd_hdr & ~0x3);
/* ext_c_ddc
*/
-#define PRD_ENTRY_EXT 0x80000000 /* extension flag or called indirect descriptor flag */
-#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Snoop enable for all data associated with the PRD entry */
+#define PRD_ENTRY_EXT 0x80000000 /* extension flag */
+#ifdef CONFIG_FSL_SATA_V2
+#define PRD_ENTRY_DATA_SNOOP 0x10000000 /* Data snoop enable */
+#else
+#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Data snoop enable */
+#endif
#define PRD_ENTRY_LEN_MASK 0x003fffff /* Data word count */
#define PRD_ENTRY_MAX_XFER_SZ (PRD_ENTRY_LEN_MASK + 1)
unsigned int temp;
#ifdef CONFIG_SYS_I2C_INIT_BOARD
- /* call board specific i2c bus reset routine before accessing the */
- /* environment, which might be in a chip on that bus. For details */
- /* about this problem see doc/I2C_Edge_Conditions. */
+ /* Call board specific i2c bus reset routine before accessing the
+ * environment, which might be in a chip on that bus. For details
+ * about this problem see doc/I2C_Edge_Conditions.
+ */
i2c_init_board();
#endif
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
writeb(0x0, &dev->sr); /* clear status register */
writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
#endif
+
+#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
+ /* Call board specific i2c bus reset routine AFTER the bus has been
+ * initialized. Use either this callpoint or i2c_init_board;
+ * which is called before i2c_init operations.
+ * For details about this problem see doc/I2C_Edge_Conditions.
+ */
+ i2c_board_late_init();
+#endif
}
static int
uint xfertyp = 0;
if (data) {
- xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
-
+ xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ xfertyp |= XFERTYP_DMAEN;
+#endif
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static int
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+ struct fsl_esdhc *regs = mmc->priv;
+ uint blocks;
+ char *buffer;
+ uint databuf;
+ uint size;
+ uint irqstat;
+ uint timeout;
+
+ if (data->flags & MMC_DATA_READ) {
+ blocks = data->blocks;
+ buffer = data->dest;
+ while (blocks) {
+ timeout = PIO_TIMEOUT;
+ size = data->blocksize;
+ irqstat = esdhc_read32(®s->irqstat);
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
+ && --timeout);
+ if (timeout <= 0) {
+ printf("\nData Read Failed in PIO Mode.");
+ return timeout;
+ }
+ while (size && (!(irqstat & IRQSTAT_TC))) {
+ udelay(100); /* Wait before last byte transfer complete */
+ irqstat = esdhc_read32(®s->irqstat);
+ databuf = in_le32(®s->datport);
+ *((uint *)buffer) = databuf;
+ buffer += 4;
+ size -= 4;
+ }
+ blocks--;
+ }
+ } else {
+ blocks = data->blocks;
+ buffer = data->src;
+ while (blocks) {
+ timeout = PIO_TIMEOUT;
+ size = data->blocksize;
+ irqstat = esdhc_read32(®s->irqstat);
+ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
+ && --timeout);
+ if (timeout <= 0) {
+ printf("\nData Write Failed in PIO Mode.");
+ return timeout;
+ }
+ while (size && (!(irqstat & IRQSTAT_TC))) {
+ udelay(100); /* Wait before last byte transfer complete */
+ databuf = *((uint *)buffer);
+ buffer += 4;
+ size -= 4;
+ irqstat = esdhc_read32(®s->irqstat);
+ out_le32(®s->datport, databuf);
+ }
+ blocks--;
+ }
+ }
+}
+#endif
+
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
uint wml_value;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ if (!(data->flags & MMC_DATA_READ)) {
+ if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+ printf("\nThe SD card is locked. "
+ "Can not write to a locked card.\n\n");
+ return TIMEOUT;
+ }
+ esdhc_write32(®s->dsaddr, (u32)data->src);
+ } else
+ esdhc_write32(®s->dsaddr, (u32)data->dest);
+#else
wml_value = data->blocksize/4;
if (data->flags & MMC_DATA_READ) {
wml_value << 16);
esdhc_write32(®s->dsaddr, (u32)data->src);
}
+#endif
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
/* Wait until all of the blocks are transferred */
if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+ esdhc_pio_read_write(mmc, data);
+#else
do {
irqstat = esdhc_read32(®s->irqstat);
return TIMEOUT;
} while (!(irqstat & IRQSTAT_TC) &&
(esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
+#endif
}
esdhc_write32(®s->irqstat, -1);
/*
- * arch/ppc/kernel/pci_auto.c
+ * arch/powerpc/kernel/pci_auto.c
*
* PCI autoconfiguration library
*
/*--------------------------------------------------------------------+
* Fixed PHY (PHY-less) support for Ethernet Ports.
*
- * Copied from arch/ppc/cpu/ppc4xx/4xx_enet.c
+ * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
*--------------------------------------------------------------------*/
/*
void serial_putc (char c)
{
- while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
- WATCHDOG_RESET ();
+ while (1) {
+ unsigned st = readl(&jtag->control);
+ if (NIOS_JTAG_WSPACE(st))
+ break;
+#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
+ if (!(st & NIOS_JTAG_AC)) /* no connection */
+ return;
+#endif
+ WATCHDOG_RESET();
+ }
writel ((unsigned char)c, &jtag->data);
}
/*
* COM1 NS16550 support
- * originally from linux source (arch/ppc/boot/ns16550.c)
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
* modified to use CONFIG_SYS_ISA_MEM and new defines
*/
name,\
bus,\
eserial##port##_init,\
+ NULL,\
eserial##port##_setbrg,\
eserial##port##_getc,\
eserial##port##_tstc,\
"serial_ffuart",
"PXA",
ffuart_init,
+ NULL,
ffuart_setbrg,
ffuart_getc,
ffuart_tstc,
"serial_btuart",
"PXA",
btuart_init,
+ NULL,
btuart_setbrg,
btuart_getc,
btuart_tstc,
"serial_stuart",
"PXA",
stuart_init,
+ NULL,
stuart_setbrg,
stuart_getc,
stuart_tstc,
name, \
bus, \
s3serial##port##_init, \
+ NULL,\
s3serial##port##_setbrg, \
s3serial##port##_getc, \
s3serial##port##_tstc, \
name, \
bus, \
s5p_serial##port##_init, \
+ NULL, \
s5p_serial##port##_setbrg, \
s5p_serial##port##_getc, \
s5p_serial##port##_tstc, \
/*
* Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
- * With help from the common/soft_spi and arch/ppc/cpu/mpc8260 drivers
+ * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
*
* See file CREDITS for list of people who contributed to this
* project.
#define msleep(a) udelay(a * 1000)
+#ifndef CONFIG_DISPLAY_VBEST_VGG322403
#define XRES 240
#define YRES 320
#define PANEL_TYPE IPU_PANEL_TFT
#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
#define IF_CONF 0
#define IF_CLK_DIV 0x175
+#else /* Display Vbest VGG322403 */
+#define XRES 320
+#define YRES 240
+#define PANEL_TYPE IPU_PANEL_TFT
+#define PIXEL_CLK 156000
+#define PIXEL_FMT IPU_PIX_FMT_RGB666
+#define H_START_WIDTH 20 /* left_margin */
+#define H_SYNC_WIDTH 30 /* hsync_len */
+#define H_END_WIDTH (38 + 30) /* right_margin + hsync_len */
+#define V_START_WIDTH 7 /* upper_margin */
+#define V_SYNC_WIDTH 3 /* vsync_len */
+#define V_END_WIDTH (26 + 3) /* lower_margin + vsync_len */
+#define SIG_POL (DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+#define IF_CONF 0
+#define IF_CLK_DIV 0x175
+#endif
#define LCD_COLOR_IPU LCD_COLOR16
# MA 02111-1307 USA
#
-ifeq ($(ARCH),ppc)
+ifeq ($(ARCH),powerpc)
LOAD_ADDR = 0x40000
endif
ifeq ($(ARCH),arm)
EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o
EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o
EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o
-ifeq ($(ARCH),ppc)
-EXT_SOBJ_FILES-$(CONFIG_API) += arch/ppc/lib/ppcstring.o
+ifeq ($(ARCH),powerpc)
+EXT_SOBJ_FILES-$(CONFIG_API) += arch/powerpc/lib/ppcstring.o
endif
# Create a list of source files so their dependencies can be auto-generated
/* The dpalloc function used and implemented in this file was derieved
- * from PPCBoot/U-Boot file "arch/ppc/cpu/mpc8260/commproc.c".
+ * from PPCBoot/U-Boot file "arch/powerpc/cpu/mpc8260/commproc.c".
*/
/* Author: Arun Dharankar <ADharankar@ATTBI.Com>
*/
/*
- * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
+ * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
* copyright notice:
*
* General Purpose functions for the global management of the
#endif
#define CONFIG_CMDLINE_EDITING 1
-
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/*
* Miscellaneous configurable options
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+ HID0_ENABLE_INSTRUCTION_CACHE | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE | \
HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\
HID0_ENABLE_INSTRUCTION_CACHE |\
/*
* High Level Configuration Options
*/
+#define CONFIG_MPC83xx 1
#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
#define CONFIG_MPC8349 /* MPC8349 specific */
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_INIT 0x00000000
+#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1
#endif
#define CONFIG_CMDLINE_EDITING 1
-
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/*
* Miscellaneous configurable options
| SICRL_ETSEC2_A )
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE | \
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+
#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* i-cache and d-cache disabled */
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT
+#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
/* DDR Controller Configuration
*
/*
* Backward compatible definitions,
- * so we do not have to change arch/ppc/cpu/mpc512x/fixed_sdram.c
+ * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
*/
#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
#define CONFIG_SYS_FLASH_BASE 0xfe000000
/*
- * The flash size is autoconfigured, but arch/ppc/cpu/mpc5xxx/cpu_init.c needs this
+ * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
* variable defined
*/
#define CONFIG_SYS_FLASH_SIZE 0x02000000
* SDRAM Controller DDR autocalibration values and takes a lot longer
* to run than Method_B.
* (See the Method_A and Method_B algorithm discription in the file:
- * arch/ppc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
+ * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
* Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
*
* DDR Autocalibration Method_B is the default.
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
* taken from the orignal Linkstation boot code
*
* Most of the low level configuration setttings are normally used
- * in arch/ppc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
+ * in arch/powerpc/cpu/mpc824x/cpu_init.c which is NOT used by this implementation.
* Low level initialisation is done in board/linkstation/early_init.S
* The values below are included for reference purpose only
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
/* DDR Controller Configuration
*
--- /dev/null
+/*
+ * (C) Copyright 2010 DENX Software Engineering
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * Common configuration options for MPC5121 based boards
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MPC5121_COMMON_H
+#define __MPC5121_COMMON_H
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM base */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes of initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+
+/*
+ * Serial console
+ */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_CMDLINE_EDITING 1 /* command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __MPC5121_COMMON_H */
#endif
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
+
+#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
/* DDR Controller Configuration
*
--- /dev/null
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcnutt@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
+#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
+#define CONFIG_BOARD_EARLY_INIT_F /* enable early board-spec. init */
+#define CONFIG_SYS_NIOS_SYSID_BASE CONFIG_SYS_SYSID_BASE
+
+/*
+ * SERIAL
+ */
+#define CONFIG_ALTERA_UART
+#if defined(CONFIG_ALTERA_JTAG_UART)
+# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_JTAG_UART_BASE
+#else
+# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_UART_BASE
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_NIOS_FIXEDBAUD
+#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD
+#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_TIMER_BASE
+#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_TIMER_IRQ
+#define CONFIG_SYS_HZ 1000 /* Always 1000 */
+#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
+#define CONFIG_SYS_NIOS_TMRCNT \
+ (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED /* Enable status driver */
+#define CONFIG_EPLED /* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR LED_PIO_BASE
+
+#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
+#define STATUS_LED_STATE 1 /* Blinking */
+#define STATUS_LED_PERIOD (500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+
+#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
+#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
+#define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \
+ CONFIG_SYS_MONITOR_LEN) | \
+ CONFIG_SYS_FLASH_BASE)
+
+/*
+ * MEMORY ORGANIZATION
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE - \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Global data size rsvd */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000)
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \
+ CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP /* Provide extended help */
+#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS 16 /* Max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - 0x20000)
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2009-2010
+ * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * pdm360ng board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_PDM360NG 1
+
+/*
+ * Memory map for the PDM360NG board:
+ *
+ * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
+ * 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB)
+ * 0x5000_0000 - 0x5001_FFFF SRAM (128 KB)
+ * 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
+ * 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB)
+ * 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC512X 1 /* MPC512X family */
+#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
+
+/* Used for silent command in environment */
+#define CONFIG_SYS_DEVICE_NULLDEV
+#define CONFIG_SILENT_CONSOLE
+
+/* Video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_XRES 800
+#define CONFIG_VIDEO_YRES 480
+#endif
+
+#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR 0x80000000
+#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
+
+/*
+ * DDR Setup
+ */
+
+/* DDR is system memory */
+#define CONFIG_SYS_DDR_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
+
+/* DDR pin mux and slew rate */
+#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012
+
+/* Manually set all parameters as there's no SPD etc. */
+/*
+ * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Read Delay: 3
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Enabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
+
+/*
+ * Alternative 1: small RAM (128 MB) configuration
+ */
+#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40
+#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
+
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
+
+#define CONFIG_SYS_DDRCMD_NOP 0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
+#define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */
+#define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */
+/* EMR with 150 ohm ODT todo: verify */
+#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040
+#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100
+#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
+/* EMR with 150 ohm ODT todo: verify */
+#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0
+/* EMR new command with 150 ohm ODT todo: verify */
+#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */
+#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */
+/* start of FLASH-Bank1 */
+#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_FLASH_SIZE)
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
+
+#define CONFIG_SYS_SRAM_BASE 0x50000000
+#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
+
+/* ALE active low, data size 4 bytes */
+#define CONFIG_SYS_CS0_CFG 0x05059350
+/* ALE active low, data size 4 bytes */
+#define CONFIG_SYS_CS1_CFG 0x05059350
+
+#define CONFIG_SYS_MRAM_BASE 0x50040000
+#define CONFIG_SYS_MRAM_SIZE 0x00020000
+/* ALE active low, data size 4 bytes */
+#define CONFIG_SYS_CS2_CFG 0x05059110
+
+/* alt. CS timing for CS0, CS1, CS2 */
+#define CONFIG_SYS_CS_ALETIMING 0x00000007
+
+/*
+ * NAND FLASH
+ */
+#define CONFIG_CMD_NAND /* enable NAND support */
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH 1
+#define CONFIG_FSL_NFC_WRITE_SIZE 2048
+#define CONFIG_FSL_NFC_SPARE_SIZE 64
+#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+
+/*
+ * Dynamic MTD partition support
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
+#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \
+ "nand0=MPC5121 NAND"
+
+/*
+ * Flash layout
+ */
+#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \
+ "256k(environment1)," \
+ "256k(environment2)," \
+ "256k(splash-factory)," \
+ "2m(FIT: recovery)," \
+ "4608k(fs-recovery)," \
+ "256k(splash-customer),"\
+ "5m(FIT: kernel+dtb)," \
+ "64m(rootfs squash)ro," \
+ "51m(userfs ubi);" \
+ "f8000000.flash:-(unused);" \
+ "MPC5121 NAND:1024m(extended-userfs)"
+
+/*
+ * Override partitions in device tree using info
+ * in "mtdparts" environment variable
+ */
+#ifdef CONFIG_CMD_MTDPARTS
+#define CONFIG_FDT_FIXUP_PARTITIONS
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */
+#ifdef CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */
+#else
+#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
+#if CONFIG_PSC_CONSOLE != 6
+#error CONFIG_PSC_CONSOLE must be 6
+#endif
+
+#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
+
+/*
+ * Used PSC UART devices
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_PSC1
+#define CONFIG_SYS_PSC4
+#define CONFIG_SYS_PSC6
+
+/*
+ * Co-processor communication parameters
+ */
+#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000
+#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400
+
+/*
+ * I2C
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM addr */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Write Mode */
+
+/*
+ * MAC addr in EEPROM
+ */
+#define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10
+/*
+ * Enabled only to delete "ethaddr" before testing
+ * "ethaddr" setting from EEPROM
+ */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC 1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 0x1F
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_FEC_AN_TIMEOUT 1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* Decrementer freq: 1ms ticks */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 32768
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#ifdef CONFIG_CMD_KGDB
+/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT 5
+#endif
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+#ifdef CONFIG_SERIAL_MULTI
+/* POST support */
+#define CONFIG_POST (CONFIG_SYS_POST_COPROC)
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME pdm360ng
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 400000
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo PDM360NG SAMPLE;" \
+ "echo"
+
+#define CONFIG_BOOTCOMMAND "run env_cont"
+
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE
+
+#define OF_CPU "PowerPC,5121@0"
+#define OF_SOC_COMPAT "fsl,mpc5121-immr"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc@80000000/serial@11600"
+
+/*
+ * Include common options for all mpc5121 boards
+ */
+#include "mpc5121-common.h"
+
+#endif /* __CONFIG_H */
#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
#define CONFIG_NET_MULTI 1
+/* Framebuffer and LCD */
+#define CONFIG_LCD
+#define CONFIG_VIDEO_MX3
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define LCD_BPP LCD_COLOR16
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_DISPLAY_VBEST_VGG322403
+
/*
* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
* initial TFTP transfer, should the user wish one, significantly.
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./arch/ppc/cpu/ppc4xx/start.S */
+/* see ./arch/powerpc/cpu/ppc4xx/start.S */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
* Taken from PPCBoot board/icecube/icecube.h
*/
-/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
+/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
#define CONFIG_SYS_EBC_PB0AP 0x04002480
/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
*
* Taken in part from PPCBoot board/icecube/icecube.h
*/
-/* see ./arch/ppc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
+/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
#define CONFIG_SYS_GPIO0_OSRH 0x55555550
#define CONFIG_SYS_GPIO0_OSRL 0x00000110
#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\
HID0_ENABLE_INSTRUCTION_CACHE |\
* - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR
* - Stackpointer will be located to
* (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF)
- * in arch/ppc/cpu/ppc4xx/start.S
+ * in arch/powerpc/cpu/ppc4xx/start.S
*/
#undef CONFIG_SYS_INIT_DCACHE_CS
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* ################################################################################### */
-/* These defines will be used in arch/ppc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
+/* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */
/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
/* This chip select accesses the boot device */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
/* FPGA and NAND */
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
+#undef CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_BMP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
#define PRSSTAT_CDPL (0x00040000)
#define PRSSTAT_CINS (0x00010000)
#define PRSSTAT_BREN (0x00000800)
+#define PRSSTAT_BWEN (0x00000400)
#define PRSSTAT_DLA (0x00000004)
#define PRSSTAT_CICHB (0x00000002)
#define PRSSTAT_CIDHB (0x00000001)
#define XFERTYP_DMAEN 0x00000001
#define CINS_TIMEOUT 1000
+#define PIO_TIMEOUT 100000
#define DSADDR 0x2e004
#ifdef CONFIG_SYS_I2C_INIT_BOARD
void i2c_init_board(void);
#endif
+#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
+void i2c_board_late_init(void);
+#endif
#if defined(CONFIG_I2C_MUX)
/*
* NS16550 Serial Port
- * originally from linux source (arch/ppc/boot/ns16550.h)
+ * originally from linux source (arch/powerpc/boot/ns16550.h)
*
* Cleanup and unification
* (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
#define CONFIG_SYS_POST_BSPEC4 0x00080000
#define CONFIG_SYS_POST_BSPEC5 0x00100000
#define CONFIG_SYS_POST_CODEC 0x00200000
+#define CONFIG_SYS_POST_COPROC 0x00400000
#endif /* CONFIG_POST */
char ctlr[CTLRSIZE];
int (*init) (void);
+ int (*uninit) (void);
void (*setbrg) (void);
int (*getc) (void);
int (*tstc) (void);
#endif
+#if defined(CONFIG_MPC512X)
+extern struct serial_device serial1_device;
+extern struct serial_device serial3_device;
+extern struct serial_device serial4_device;
+extern struct serial_device serial6_device;
+#endif
+
#if defined(CONFIG_S3C2410)
extern struct serial_device s3c24xx_serial0_device;
extern struct serial_device s3c24xx_serial1_device;
#endif /* CONFIG_USB_TTY */
+#if defined(CONFIG_MPC512X) && defined(CONFIG_SERIAL_MULTI)
+extern struct stdio_dev *open_port(int num, int baudrate);
+extern int close_port(int num);
+extern int write_port(struct stdio_dev *port, char *buf);
+extern int read_port(struct stdio_dev *port, char *buf, int size);
+#endif
+
#endif
*
* Code generated for this function might be very inefficient
* for some CPUs. __div64_32() can be overridden by linking arch-specific
- * assembly versions such as arch/ppc/lib/div64.S and arch/sh/lib/div64.S.
+ * assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S.
*/
#include <linux/types.h>
# from cpu directory
$(obj)cache.S:
@rm -f $(obj)cache.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)gpio.c:
@rm -f $(obj)gpio.c
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/gpio.c $(obj)gpio.c
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $(obj)gpio.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)memory.c:
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
# from cpu directory
$(obj)44x_spd_ddr2.c: $(obj)ecc.h
@rm -f $(obj)44x_spd_ddr2.c
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
$(obj)cache.S:
@rm -f $(obj)cache.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/cache.S $(obj)cache.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)ecc.h:
@rm -f $(obj)ecc.h
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/ecc.h $(obj)ecc.h
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $(obj)ecc.h
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from nand_spl directory
$(obj)nand_boot.c:
# from cpu directory
$(obj)denali_data_eye.c:
@rm -f $(obj)denali_data_eye.c
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
- ln -s $(SRCTREE)/arch/ppc/cpu/ppc4xx/start.S $(obj)start.S
+ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
# create symbolic links for common files
$(obj)start.S:
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $(obj)start.S
$(obj)nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
$(obj)nand_init.c:
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
$(obj)cache.c:
- ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
$(obj)time.c:
- ln -sf $(SRCTREE)/arch/ppc/lib/time.c $(obj)time.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
$(obj)ticks.S:
- ln -sf $(SRCTREE)/arch/ppc/lib/ticks.S $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
#########################################################################
# create symbolic links for common files
$(obj)start.S:
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $(obj)start.S
$(obj)nand_boot_fsl_elbc.c:
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
$(obj)nand_init.c:
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $(obj)nand_init.c
$(obj)cache.c:
- ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
$(obj)time.c:
- ln -sf $(SRCTREE)/arch/ppc/lib/time.c $(obj)time.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
$(obj)ticks.S:
- ln -sf $(SRCTREE)/arch/ppc/lib/ticks.S $(obj)ticks.S
+ ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
#########################################################################
$(obj)cache.c:
@rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
$(obj)cache.c:
@rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
$(obj)cache.c:
@rm -f $(obj)cache.c
- ln -sf $(SRCTREE)/arch/ppc/lib/cache.c $(obj)cache.c
+ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
$(obj)cpu_init_early.c:
@rm -f $(obj)cpu_init_early.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
$(obj)cpu_init_nand.c:
@rm -f $(obj)cpu_init_nand.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
$(obj)fsl_law.c:
@rm -f $(obj)fsl_law.c
$(obj)fixed_ivor.S:
@rm -f $(obj)fixed_ivor.S
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
$(obj)start.S: $(obj)fixed_ivor.S
@rm -f $(obj)start.S
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/start.S $(obj)start.S
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
$(obj)tlb.c:
@rm -f $(obj)tlb.c
- ln -sf $(SRCTREE)/arch/ppc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
$(obj)tlb_table.c:
@rm -f $(obj)tlb_table.c
$(obj)start.S:
@rm -f $@
- ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/start.S $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
$(obj)nand_boot_fsl_elbc.c:
@rm -f $@
$(obj)nand_init.c:
@rm -f $@
- ln -s $(SRCTREE)/arch/ppc/cpu/mpc83xx/nand_init.c $@
+ ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $@
$(obj)cache.c:
@rm -f $@
- ln -s $(SRCTREE)/arch/ppc/lib/cache.c $@
+ ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)time.c:
@rm -f $@
- ln -s $(SRCTREE)/arch/ppc/lib/time.c $@
+ ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@
$(obj)ticks.S:
@rm -f $@
- ln -s $(SRCTREE)/arch/ppc/lib/ticks.S $@
+ ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2010 DENX Software Engineering
+# Anatolij Gustschin, agust@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(OBJTREE)/include/autoconf.mk
+
+LIB = libpostpdm360ng.a
+
+COBJS-$(CONFIG_HAS_POST) += coproc_com.o
+
+include $(TOPDIR)/post/rules.mk
--- /dev/null
+/*
+ * (C) Copyright 2010 DENX Software Engineering,
+ * Anatolij Gustschin, agust@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Co-Processor communication POST
+ */
+#include <common.h>
+#include <post.h>
+#include <serial.h>
+
+#if defined(CONFIG_SERIAL_MULTI)
+
+/*
+ * Actually the termination sequence of the coprocessor
+ * commands is "\r\n" (CR LF), but here we use a side effect of
+ * the putc() routine of the serial driver which checks for LF
+ * and sends CR before sending LF. Therefore the termination
+ * sequence in the command below is only "\n".
+ * "alive" string is the coprocessor response for ping command
+ * and not a command, therefore it is terminated with "\r\n".
+ */
+char alive[] = "$AL;38\r\n";
+char ping[] = "$PI;2C\n";
+
+int coprocessor_post_test(int flags)
+{
+ struct stdio_dev *cop_port;
+ int ret;
+ char buf[10];
+
+ /* Test IO Coprocessor communication */
+ cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+ if (!cop_port)
+ return -1;
+
+ write_port(cop_port, ping);
+ udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+
+ memset(buf, 0, sizeof(buf));
+ ret = read_port(cop_port, buf, sizeof(buf));
+ close_port(4);
+ if (ret <= 0) {
+ post_log("Error: Can't read IO Coprocessor port.\n");
+ return -1;
+ }
+
+ if (strcmp(buf, alive)) {
+ post_log("Error: IO-Cop. resp.: %s\n", buf);
+ return -1;
+ }
+
+ /* Test WD Coprocessor communication */
+ cop_port = open_port(1, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+ if (!cop_port) {
+ post_log("Error: Can't open WD Coprocessor port.\n");
+ return -1;
+ }
+
+ write_port(cop_port, ping);
+ udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+
+ memset(buf, 0, sizeof(buf));
+ ret = read_port(cop_port, buf, sizeof(buf));
+ close_port(1);
+ if (ret <= 0) {
+ post_log("Error: Can't read WD Coprocessor port.\n");
+ return -1;
+ }
+
+ if (strcmp(buf, alive)) {
+ post_log("Error: WD-Cop. resp.: %s\n", buf);
+ return -1;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_SERIAL_MULTI */
/* Additional Special-Purpose Registers.
* The values must match the initialization
- * values from arch/ppc/cpu/ppc4xx/start.S
+ * values from arch/powerpc/cpu/ppc4xx/start.S
*/
{0x30, "PID", 0x00000000, 0x00000000},
{0x3a, "CSRR0", 0x00000000, 0x00000000},
#
include $(TOPDIR)/config.mk
-LIB = libpostppc.a
+LIB = libpost$(ARCH).a
AOBJS-$(CONFIG_HAS_POST) += asm.o
COBJS-$(CONFIG_HAS_POST) += cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o
#
include $(TOPDIR)/config.mk
-LIB = libpostppcfpu.a
+LIB = libpost$(ARCH)fpu.a
COBJS-$(CONFIG_HAS_POST) += fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o
COBJS-$(CONFIG_HAS_POST) += acc1.o compare-fp-1.o mul-subnormal-single-1.o
extern int fpga_post_test (int flags);
extern int lwmon5_watchdog_post_test(int flags);
extern int sysmon1_post_test(int flags);
+extern int coprocessor_post_test(int flags);
extern int sysmon_init_f (void);
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5
CONFIG_POST_BSPEC5,
#endif
+#if CONFIG_POST & CONFIG_SYS_POST_COPROC
+ {
+ "Coprocessors communication test",
+ "coproc_com",
+ "This test checks communication with coprocessors.",
+ POST_RAM | POST_ALWAYS | POST_CRITICAL,
+ &coprocessor_post_test,
+ NULL,
+ NULL,
+ CONFIG_SYS_POST_COPROC
+ }
+#endif
};
unsigned int post_list_size = sizeof (post_list) / sizeof (struct post_test);
projects / karo-tx-uboot.git / commitdiff