Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 6 Jan 2014 07:49:58 +0000 (08:49 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 6 Jan 2014 07:49:58 +0000 (08:49 +0100)
Conflicts:
include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.

855 files changed:
CREDITS
MAKEALL
Makefile
README
api/Makefile
arch/arm/config.mk
arch/arm/cpu/Makefile
arch/arm/cpu/arm720t/tegra-common/cpu.c
arch/arm/cpu/arm926ejs/at91/led.c
arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/am33xx/Makefile
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
arch/arm/cpu/armv7/am33xx/ddr.c
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/cpu/armv7/am33xx/mem.c
arch/arm/cpu/armv7/at91/sama5d3_devices.c
arch/arm/cpu/armv7/at91/timer.c
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/exynos/spl_boot.c
arch/arm/cpu/armv7/nonsec_virt.S
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/abb.c
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap-common/pipe3-phy.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/pipe3-phy.h [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/sata.c [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/omap3/clock.c
arch/arm/cpu/armv7/omap4/hw_data.c
arch/arm/cpu/armv7/omap4/sdram_elpida.c
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/cpu/armv7/rmobile/Makefile
arch/arm/cpu/armv7/rmobile/config.mk [deleted file]
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c [new file with mode: 0644]
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c [new file with mode: 0644]
arch/arm/cpu/armv7/rmobile/cpu_info.c
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S [new file with mode: 0644]
arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c [new file with mode: 0644]
arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h [new file with mode: 0644]
arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c [new file with mode: 0644]
arch/arm/cpu/armv7/rmobile/timer.c
arch/arm/cpu/armv7/socfpga/Makefile
arch/arm/cpu/armv7/socfpga/freeze_controller.c [new file with mode: 0644]
arch/arm/cpu/armv7/socfpga/spl.c
arch/arm/cpu/armv7/zynq/cpu.c
arch/arm/cpu/at91-common/Makefile [new file with mode: 0644]
arch/arm/cpu/at91-common/mpddrc.c [new file with mode: 0644]
arch/arm/cpu/at91-common/phy.c [new file with mode: 0644]
arch/arm/cpu/at91-common/spl.c [new file with mode: 0644]
arch/arm/cpu/at91-common/u-boot-spl.lds [new file with mode: 0644]
arch/arm/cpu/ixp/u-boot.lds
arch/arm/cpu/pxa/pxa2xx.c
arch/arm/cpu/tegra-common/ap.c
arch/arm/cpu/u-boot-spl.lds
arch/arm/cpu/u-boot.lds
arch/arm/include/asm/arch-am33xx/clock.h
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/ddr_defs.h
arch/arm/include/asm/arch-am33xx/gpio.h
arch/arm/include/asm/arch-am33xx/hardware.h
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
arch/arm/include/asm/arch-am33xx/i2c.h
arch/arm/include/asm/arch-am33xx/mem.h
arch/arm/include/asm/arch-am33xx/mux_am43xx.h
arch/arm/include/asm/arch-am33xx/omap.h
arch/arm/include/asm/arch-am33xx/spl.h
arch/arm/include/asm/arch-at91/at91_common.h
arch/arm/include/asm/arch-at91/at91_pio.h
arch/arm/include/asm/arch-at91/at91_pit.h
arch/arm/include/asm/arch-at91/at91_pmc.h
arch/arm/include/asm/arch-at91/at91_spi.h
arch/arm/include/asm/arch-at91/at91_wdt.h
arch/arm/include/asm/arch-at91/at91cap9.h
arch/arm/include/asm/arch-at91/at91sam9_smc.h
arch/arm/include/asm/arch-at91/atmel_mpddrc.h [new file with mode: 0644]
arch/arm/include/asm/arch-at91/gpio.h
arch/arm/include/asm/arch-at91/sama5d3.h
arch/arm/include/asm/arch-at91/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-bcm2835/mbox.h
arch/arm/include/asm/arch-davinci/hardware.h
arch/arm/include/asm/arch-exynos/dwmmc.h
arch/arm/include/asm/arch-exynos/mmc.h
arch/arm/include/asm/arch-exynos/power.h
arch/arm/include/asm/arch-exynos/spi.h
arch/arm/include/asm/arch-omap3/clock.h
arch/arm/include/asm/arch-omap3/dss.h
arch/arm/include/asm/arch-omap3/omap3.h
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/clock.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/arch-omap5/sata.h [new file with mode: 0644]
arch/arm/include/asm/arch-rmobile/gpio.h
arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-rmobile/r8a7790.h [new file with mode: 0644]
arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-rmobile/r8a7791.h [new file with mode: 0644]
arch/arm/include/asm/arch-rmobile/rmobile.h
arch/arm/include/asm/arch-s5pc1xx/mmc.h
arch/arm/include/asm/arch-socfpga/freeze_controller.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra/clock.h
arch/arm/include/asm/arch-tegra/tegra.h
arch/arm/include/asm/emif.h
arch/arm/include/asm/omap_common.h
arch/arm/include/asm/omap_elm.h [moved from arch/arm/include/asm/arch-am33xx/elm.h with 100% similarity]
arch/arm/include/asm/omap_gpmc.h
arch/arm/lib/board.c
arch/blackfin/cpu/.gitignore
arch/blackfin/cpu/Makefile
arch/blackfin/cpu/bootrom-asm-offsets.awk [deleted file]
arch/blackfin/cpu/bootrom-asm-offsets.c.in [deleted file]
arch/blackfin/cpu/gpio.c
arch/blackfin/cpu/os_log.c
arch/blackfin/include/asm/blackfin_local.h
arch/blackfin/include/asm/gpio.h
arch/microblaze/cpu/u-boot.lds
arch/mips/cpu/mips32/cache.S
arch/mips/cpu/mips32/cpu.c
arch/mips/cpu/mips32/start.S
arch/mips/include/asm/malta.h
arch/mips/include/asm/mipsregs.h
arch/mips/lib/bootm.c
arch/powerpc/cpu/Makefile [new file with mode: 0644]
arch/powerpc/cpu/mpc512x/Makefile
arch/powerpc/cpu/mpc824x/.gitignore [deleted file]
arch/powerpc/cpu/mpc824x/Makefile
arch/powerpc/cpu/mpc824x/cpu_init.c
arch/powerpc/cpu/mpc83xx/Makefile
arch/powerpc/cpu/mpc83xx/ecc.c
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/liodn.c
arch/powerpc/cpu/mpc85xx/mp.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/spl_minimal.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t2080_ids.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t2080_serdes.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/t4240_ids.c
arch/powerpc/cpu/mpc86xx/Makefile
arch/powerpc/cpu/mpc8xxx/Makefile
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/Makefile [deleted file]
arch/powerpc/include/asm/config.h
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/config_mpc86xx.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/immap_83xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/immap_86xx.h
arch/powerpc/include/asm/mpc85xx_gpio.h
arch/powerpc/include/asm/processor.h
arch/sandbox/cpu/Makefile
arch/sandbox/cpu/os.c
arch/sandbox/cpu/start.c
arch/sandbox/include/asm/config.h
arch/sandbox/include/asm/getopt.h
arch/sandbox/include/asm/io.h
arch/sandbox/include/asm/sections.h
arch/sandbox/include/asm/spi.h [new file with mode: 0644]
arch/sandbox/include/asm/state.h
arch/sandbox/include/asm/types.h
arch/sparc/cpu/leon3/start.S
board/BuS/vl_ma2sc/vl_ma2sc.c
board/LEOX/elpt860/u-boot.lds
board/LaCie/edminiv2/Makefile
board/LaCie/net2big_v2/Makefile
board/LaCie/netspace_v2/Makefile
board/LaCie/wireless_space/Makefile
board/Marvell/db64360/Makefile
board/Marvell/db64460/Makefile
board/actux1/u-boot.lds
board/actux2/u-boot.lds
board/actux3/u-boot.lds
board/afeb9260/afeb9260.c
board/altera/nios2-generic/Makefile
board/altera/nios2-generic/config.mk
board/atmel/at91sam9260ek/at91sam9260ek.c
board/atmel/at91sam9263ek/at91sam9263ek.c
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/atmel/at91sam9x5ek/at91sam9x5ek.c
board/atmel/sama5d3xek/sama5d3xek.c
board/avionic-design/common/pinmux-config-tamonten-ng.h [new file with mode: 0644]
board/avionic-design/common/tamonten-ng.c [new file with mode: 0644]
board/avionic-design/dts/tegra30-tamonten.dtsi [new file with mode: 0644]
board/avionic-design/dts/tegra30-tec-ng.dts [new file with mode: 0644]
board/avionic-design/medcom-wide/Makefile
board/avionic-design/plutux/Makefile
board/avionic-design/tec-ng/Makefile [new file with mode: 0644]
board/avionic-design/tec/Makefile
board/bluewater/snapper9260/snapper9260.c
board/calao/sbc35_a9g20/sbc35_a9g20.c
board/calao/usb_a9263/Makefile [new file with mode: 0644]
board/calao/usb_a9263/usb_a9263.c [new file with mode: 0644]
board/cogent/config.mk [deleted file]
board/cogent/dipsw.c
board/cogent/flash.c
board/cogent/lcd.c
board/cogent/mb.c
board/cogent/serial.c
board/compal/paz00/Makefile
board/compulab/cm_t335/Makefile [new file with mode: 0644]
board/compulab/cm_t335/cm_t335.c [new file with mode: 0644]
board/compulab/cm_t335/mux.c [new file with mode: 0644]
board/compulab/cm_t335/spl.c [new file with mode: 0644]
board/compulab/cm_t335/u-boot.lds [new file with mode: 0644]
board/compulab/cm_t35/cm_t35.c
board/compulab/common/Makefile
board/compulab/common/eeprom.h
board/compulab/common/omap3_display.c
board/compulab/trimslice/Makefile
board/davinci/da8xxevm/u-boot-spl-hawk.lds
board/dvlhost/u-boot.lds
board/egnite/ethernut5/ethernut5.c
board/emk/top5200/Makefile
board/emk/top860/Makefile
board/esd/adciop/Makefile
board/esd/apc405/Makefile
board/esd/ar405/Makefile
board/esd/ash405/Makefile
board/esd/cms700/Makefile
board/esd/cpci2dp/Makefile
board/esd/cpci405/Makefile
board/esd/cpci5200/Makefile
board/esd/cpci750/Makefile
board/esd/cpciiser4/Makefile
board/esd/dasa_sim/Makefile
board/esd/dp405/Makefile
board/esd/du405/Makefile
board/esd/hh405/Makefile
board/esd/hub405/Makefile
board/esd/meesc/meesc.c
board/esd/ocrtc/Makefile
board/esd/otc570/otc570.c
board/esd/pci405/Makefile
board/esd/pf5200/Makefile
board/esd/plu405/Makefile
board/esd/pmc405/Makefile
board/esd/pmc405de/Makefile
board/esd/pmc440/Makefile
board/esd/voh405/Makefile
board/esd/vom405/Makefile
board/esd/wuh405/Makefile
board/esteem192e/u-boot.lds
board/eukrea/cpu9260/cpu9260.c
board/exmeritus/hww1u1a/ddr.c
board/exmeritus/hww1u1a/hww1u1a.c
board/freescale/b4860qds/ddr.c
board/freescale/bsc9131rdb/ddr.c
board/freescale/bsc9131rdb/spl_minimal.c
board/freescale/bsc9132qds/bsc9132qds.c
board/freescale/bsc9132qds/ddr.c
board/freescale/bsc9132qds/spl_minimal.c
board/freescale/c29xpcie/c29xpcie.c
board/freescale/c29xpcie/ddr.c
board/freescale/corenet_ds/ddr.c
board/freescale/corenet_ds/eth_p4080.c
board/freescale/corenet_ds/p3041ds_ddr.c
board/freescale/corenet_ds/p4080ds_ddr.c
board/freescale/corenet_ds/p5020ds_ddr.c
board/freescale/corenet_ds/p5040ds_ddr.c
board/freescale/m52277evb/config.mk [deleted file]
board/freescale/m52277evb/u-boot.lds
board/freescale/m5235evb/config.mk [deleted file]
board/freescale/m53017evb/u-boot.lds
board/freescale/m54451evb/config.mk [deleted file]
board/freescale/m54455evb/config.mk [deleted file]
board/freescale/mpc8349emds/Makefile
board/freescale/mpc8349emds/ddr.c
board/freescale/mpc8349emds/mpc8349emds.c
board/freescale/mpc8536ds/ddr.c
board/freescale/mpc8536ds/mpc8536ds.c
board/freescale/mpc8540ads/ddr.c
board/freescale/mpc8540ads/mpc8540ads.c
board/freescale/mpc8541cds/ddr.c
board/freescale/mpc8541cds/mpc8541cds.c
board/freescale/mpc8544ds/ddr.c
board/freescale/mpc8544ds/mpc8544ds.c
board/freescale/mpc8548cds/ddr.c
board/freescale/mpc8548cds/mpc8548cds.c
board/freescale/mpc8555cds/ddr.c
board/freescale/mpc8555cds/mpc8555cds.c
board/freescale/mpc8560ads/ddr.c
board/freescale/mpc8560ads/mpc8560ads.c
board/freescale/mpc8568mds/ddr.c
board/freescale/mpc8568mds/mpc8568mds.c
board/freescale/mpc8569mds/ddr.c
board/freescale/mpc8569mds/mpc8569mds.c
board/freescale/mpc8572ds/ddr.c
board/freescale/mpc8572ds/mpc8572ds.c
board/freescale/mpc8610hpcd/Makefile
board/freescale/mpc8610hpcd/ddr.c
board/freescale/mpc8610hpcd/mpc8610hpcd.c
board/freescale/mpc8641hpcn/Makefile
board/freescale/mpc8641hpcn/ddr.c
board/freescale/mpc8641hpcn/mpc8641hpcn.c
board/freescale/mx31ads/u-boot.lds
board/freescale/p1010rdb/README.P1010RDB-PA [moved from board/freescale/p1010rdb/README with 97% similarity]
board/freescale/p1010rdb/README.P1010RDB-PB [new file with mode: 0644]
board/freescale/p1010rdb/ddr.c
board/freescale/p1010rdb/p1010rdb.c
board/freescale/p1010rdb/spl_minimal.c
board/freescale/p1022ds/ddr.c
board/freescale/p1022ds/p1022ds.c
board/freescale/p1022ds/spl_minimal.c
board/freescale/p1023rdb/ddr.c
board/freescale/p1023rdb/p1023rdb.c
board/freescale/p1023rds/p1023rds.c
board/freescale/p1_p2_rdb/ddr.c
board/freescale/p1_p2_rdb_pc/ddr.c
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
board/freescale/p1_p2_rdb_pc/spl_minimal.c
board/freescale/p1_twr/ddr.c
board/freescale/p1_twr/p1_twr.c
board/freescale/p2020come/ddr.c
board/freescale/p2020ds/ddr.c
board/freescale/p2020ds/p2020ds.c
board/freescale/p2041rdb/ddr.c
board/freescale/t1040qds/Makefile
board/freescale/t1040qds/ddr.c
board/freescale/t1040qds/t1040_pbi.cfg [new file with mode: 0644]
board/freescale/t1040qds/t1040_rcw.cfg [new file with mode: 0644]
board/freescale/t104xrdb/Makefile [new file with mode: 0644]
board/freescale/t104xrdb/README [new file with mode: 0644]
board/freescale/t104xrdb/ddr.c [new file with mode: 0644]
board/freescale/t104xrdb/ddr.h [new file with mode: 0644]
board/freescale/t104xrdb/law.c [new file with mode: 0644]
board/freescale/t104xrdb/pci.c [new file with mode: 0644]
board/freescale/t104xrdb/t104xrdb.c [new file with mode: 0644]
board/freescale/t104xrdb/t104xrdb.h [new file with mode: 0644]
board/freescale/t104xrdb/tlb.c [new file with mode: 0644]
board/freescale/t2080qds/Makefile [new file with mode: 0644]
board/freescale/t2080qds/ddr.c [new file with mode: 0644]
board/freescale/t2080qds/ddr.h [new file with mode: 0644]
board/freescale/t2080qds/eth_t2080qds.c [new file with mode: 0644]
board/freescale/t2080qds/law.c [new file with mode: 0644]
board/freescale/t2080qds/pci.c [new file with mode: 0644]
board/freescale/t2080qds/t2080_pbi.cfg [new file with mode: 0644]
board/freescale/t2080qds/t2080_rcw.cfg [new file with mode: 0644]
board/freescale/t2080qds/t2080qds.c [new file with mode: 0644]
board/freescale/t2080qds/t2080qds.h [new file with mode: 0644]
board/freescale/t2080qds/t2080qds_qixis.h [new file with mode: 0644]
board/freescale/t2080qds/tlb.c [new file with mode: 0644]
board/freescale/t4qds/ddr.c
board/freescale/t4qds/eth.c
board/gaisler/gr_cpci_ax2000/config.mk
board/gaisler/gr_ep2s60/config.mk
board/gaisler/gr_xc3s_1500/config.mk
board/gaisler/grsim/config.mk
board/gaisler/grsim_leon2/config.mk
board/gdsys/p1022/controlcenterd.c
board/gdsys/p1022/ddr.c
board/genietv/u-boot.lds
board/h2200/Makefile
board/hermes/u-boot.lds
board/icpdas/lp8x4x/lp8x4x.c
board/imgtec/malta/Makefile [moved from board/qemu-malta/Makefile with 81% similarity]
board/imgtec/malta/flash-malta-boot.tcl [new file with mode: 0644]
board/imgtec/malta/lowlevel_init.S [new file with mode: 0644]
board/imgtec/malta/malta.c [new file with mode: 0644]
board/imgtec/malta/superio.c [new file with mode: 0644]
board/imgtec/malta/superio.h [new file with mode: 0644]
board/isee/igep0033/board.c
board/keymile/km82xx/Makefile
board/keymile/km83xx/Makefile
board/keymile/km_arm/Makefile
board/keymile/kmp204x/Makefile
board/keymile/kmp204x/ddr.c
board/kmc/kzm9g/kzm9g.c
board/kup/kup4k/Makefile
board/kup/kup4x/Makefile
board/logicpd/am3517evm/am3517evm.c
board/logicpd/am3517evm/am3517evm.h
board/matrix_vision/mvsmr/u-boot.lds
board/mpl/mip405/Makefile
board/mpl/pati/Makefile
board/mpl/pip405/Makefile
board/mpl/vcma9/Makefile
board/mvblue/u-boot.lds
board/nvidia/beaver/Makefile
board/nvidia/ventana/Makefile
board/overo/overo.c
board/phytec/pcm051/board.c
board/pn62/Makefile [deleted file]
board/pn62/cmd_pn62.c [deleted file]
board/pn62/misc.c [deleted file]
board/pn62/pn62.c [deleted file]
board/pn62/pn62.h [deleted file]
board/prodrive/p3mx/Makefile
board/psyent/pci5441/Makefile
board/psyent/pci5441/config.mk
board/psyent/pk1c20/Makefile
board/psyent/pk1c20/config.mk
board/qemu-malta/lowlevel_init.S [deleted file]
board/qemu-malta/qemu-malta.c [deleted file]
board/rbc823/u-boot.lds
board/renesas/ecovec/ecovec.c
board/renesas/koelsch/Makefile [new file with mode: 0644]
board/renesas/koelsch/koelsch.c [new file with mode: 0644]
board/renesas/koelsch/qos.c [new file with mode: 0644]
board/renesas/koelsch/qos.h [new file with mode: 0644]
board/renesas/lager/Makefile [new file with mode: 0644]
board/renesas/lager/lager.c [new file with mode: 0644]
board/renesas/lager/qos.c [new file with mode: 0644]
board/renesas/lager/qos.h [new file with mode: 0644]
board/ronetix/pm9261/led.c
board/ronetix/pm9261/pm9261.c
board/ronetix/pm9263/led.c
board/ronetix/pm9263/pm9263.c
board/ronetix/pm9g45/pm9g45.c
board/samsung/smdk5250/exynos5-dt.c
board/samsung/trats/trats.c
board/samsung/trats2/trats2.c
board/sandbox/sandbox/README.sandbox
board/sandburst/karef/Makefile
board/sandburst/metrobox/Makefile
board/sbc8548/Makefile
board/sbc8548/ddr.c
board/sbc8548/sbc8548.c
board/sbc8641d/Makefile
board/sbc8641d/ddr.c
board/sbc8641d/sbc8641d.c
board/siemens/common/board.c
board/siemens/corvus/Makefile [new file with mode: 0644]
board/siemens/corvus/board.c [new file with mode: 0644]
board/siemens/dxr2/Makefile
board/siemens/dxr2/board.c
board/siemens/pxm2/Makefile
board/siemens/pxm2/board.c
board/siemens/rut/Makefile
board/siemens/rut/board.c
board/siemens/taurus/Makefile [new file with mode: 0644]
board/siemens/taurus/taurus.c [new file with mode: 0644]
board/socrates/Makefile
board/socrates/ddr.c
board/socrates/sdram.c
board/spd8xx/u-boot.lds
board/stx/stxgp3/Makefile
board/stx/stxgp3/ddr.c
board/stx/stxgp3/stxgp3.c
board/stx/stxssa/Makefile
board/stx/stxssa/ddr.c
board/stx/stxssa/stxssa.c
board/svm_sc8xx/u-boot.lds
board/taskit/stamp9g20/stamp9g20.c
board/technexion/tao3530/Makefile [new file with mode: 0644]
board/technexion/tao3530/tao3530.c [new file with mode: 0644]
board/technexion/tao3530/tao3530.h [new file with mode: 0644]
board/ti/am335x/board.c
board/ti/am335x/u-boot.lds
board/ti/am3517crane/am3517crane.c
board/ti/am43xx/board.c
board/ti/am43xx/board.h
board/ti/am43xx/mux.c
board/ti/beagle/Makefile
board/ti/dra7xx/evm.c
board/ti/evm/evm.c
board/ti/omap5_uevm/evm.c
board/ti/panda/panda.c
board/ti/ti814x/evm.c
board/ti/ti816x/evm.c
board/toradex/colibri_t20_iris/Makefile
board/tqc/tqm5200/Makefile
board/tqc/tqm8260/Makefile
board/tqc/tqm8272/Makefile
board/tqc/tqm8xx/u-boot.lds
board/vpac270/u-boot-spl.lds
board/xes/xpedite517x/ddr.c
board/xes/xpedite517x/xpedite517x.c
board/xes/xpedite520x/ddr.c
board/xes/xpedite537x/ddr.c
board/xes/xpedite550x/ddr.c
board/xilinx/ppc405-generic/Makefile
board/xilinx/ppc440-generic/Makefile
boards.cfg
common/Makefile
common/cmd_eeprom.c
common/cmd_mdio.c
common/cmd_mii.c
common/hash.c
common/lcd.c
config.mk
doc/README.at91-soc
doc/README.malta [new file with mode: 0644]
doc/README.nand
doc/README.omap3
doc/README.p1010rdb [deleted file]
doc/README.rmobile
doc/README.scrapyard
doc/SPI/README.sandbox-spi [new file with mode: 0644]
doc/device-tree-bindings/spi/spi-bus.txt [new file with mode: 0644]
drivers/Makefile
drivers/bios_emulator/Makefile
drivers/block/ahci.c
drivers/ddr/fsl/Makefile [new file with mode: 0644]
drivers/ddr/fsl/arm_ddr_gen3.c [new file with mode: 0644]
drivers/ddr/fsl/ctrl_regs.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c with 96% similarity]
drivers/ddr/fsl/ddr1_dimm_params.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c with 99% similarity]
drivers/ddr/fsl/ddr2_dimm_params.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c with 99% similarity]
drivers/ddr/fsl/ddr3_dimm_params.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c with 99% similarity]
drivers/ddr/fsl/interactive.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/interactive.c with 99% similarity]
drivers/ddr/fsl/lc_common_dimm_params.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c with 98% similarity]
drivers/ddr/fsl/main.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/main.c with 98% similarity]
drivers/ddr/fsl/mpc85xx_ddr_gen1.c [moved from arch/powerpc/cpu/mpc85xx/ddr-gen1.c with 91% similarity]
drivers/ddr/fsl/mpc85xx_ddr_gen2.c [moved from arch/powerpc/cpu/mpc85xx/ddr-gen2.c with 96% similarity]
drivers/ddr/fsl/mpc85xx_ddr_gen3.c [moved from arch/powerpc/cpu/mpc85xx/ddr-gen3.c with 96% similarity]
drivers/ddr/fsl/mpc86xx_ddr.c [moved from arch/powerpc/cpu/mpc86xx/ddr-8641.c with 91% similarity]
drivers/ddr/fsl/options.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/options.c with 97% similarity]
drivers/ddr/fsl/util.c [moved from arch/powerpc/cpu/mpc8xxx/ddr/util.c with 95% similarity]
drivers/fpga/Makefile
drivers/gpio/at91_gpio.c
drivers/i2c/Makefile
drivers/i2c/designware_i2c.c
drivers/i2c/fti2c010.c
drivers/i2c/mxs_i2c.c
drivers/i2c/omap1510_i2c.c [deleted file]
drivers/i2c/omap24xx_i2c.c
drivers/i2c/s3c24x0_i2c.c
drivers/i2c/sh_i2c.c
drivers/i2c/soft_i2c.c
drivers/i2c/tegra_i2c.c
drivers/i2c/zynq_i2c.c
drivers/misc/Makefile
drivers/misc/cros_ec_spi.c
drivers/misc/fsl_ifc.c [moved from arch/powerpc/cpu/mpc8xxx/fsl_ifc.c with 86% similarity]
drivers/misc/gpio_led.c
drivers/mmc/Makefile
drivers/mmc/dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
drivers/mmc/fsl_esdhc_spl.c
drivers/mmc/ftsdc021_sdhci.c [new file with mode: 0644]
drivers/mtd/nand/Makefile
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsl_ifc_spl.c
drivers/mtd/nand/omap_elm.c [moved from arch/arm/cpu/armv7/am33xx/elm.c with 97% similarity]
drivers/mtd/nand/omap_gpmc.c
drivers/mtd/onenand/onenand_base.c
drivers/mtd/spi/Makefile
drivers/mtd/spi/fsl_espi_spl.c
drivers/mtd/spi/sandbox.c [new file with mode: 0644]
drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/sf_probe.c
drivers/net/at91_emac.c
drivers/net/cpsw.c
drivers/net/designware.c
drivers/net/designware.h
drivers/net/dm9000x.c
drivers/net/e1000.c
drivers/net/e1000.h
drivers/net/fm/Makefile
drivers/net/fm/eth.c
drivers/net/fm/fm.h
drivers/net/fm/init.c
drivers/net/fm/t2080.c [new file with mode: 0644]
drivers/net/fsl_mdio.c
drivers/net/mvgbe.c
drivers/net/npe/Makefile
drivers/net/pcnet.c
drivers/net/phy/atheros.c
drivers/net/phy/micrel.c
drivers/net/phy/phy.c
drivers/net/phy/realtek.c
drivers/net/phy/smsc.c
drivers/net/phy/vitesse.c
drivers/net/rtl8139.c
drivers/net/rtl8169.c
drivers/net/sh_eth.c
drivers/net/sh_eth.h
drivers/net/tsec.c
drivers/net/zynq_gem.c
drivers/pci/Makefile
drivers/pci/pci_msc01.c [new file with mode: 0644]
drivers/power/twl6030.c
drivers/qe/Makefile
drivers/rtc/mc146818.c
drivers/serial/serial_zynq.c
drivers/spi/Makefile
drivers/spi/bfin_spi.c
drivers/spi/bfin_spi6xx.c
drivers/spi/exynos_spi.c
drivers/spi/omap3_spi.c
drivers/spi/omap3_spi.h
drivers/spi/sandbox_spi.c [new file with mode: 0644]
drivers/spi/spi.c
drivers/tpm/Makefile
drivers/tpm/tis_i2c.c [deleted file]
drivers/usb/gadget/regs-otg.h
drivers/usb/gadget/s3c_udc_otg.c
drivers/usb/host/ehci-omap.c
drivers/video/Makefile
drivers/video/bcm2835.c
drivers/video/bus_vcxk.c
drivers/video/scf0403_lcd.c [new file with mode: 0644]
examples/api/Makefile
examples/standalone/Makefile
examples/standalone/eepro100_eeprom.c [deleted file]
examples/standalone/stubs.c
fs/Makefile
fs/cbfs/Makefile
fs/cramfs/Makefile
fs/ext4/Makefile
fs/fdos/Makefile
fs/jffs2/Makefile
fs/reiserfs/Makefile
fs/sandbox/Makefile
fs/ubifs/Makefile
fs/yaffs2/Makefile
fs/zfs/Makefile
include/common.h
include/common_timing_params.h [moved from arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h with 100% similarity]
include/configs/ASH405.h
include/configs/B4860QDS.h
include/configs/BSC9131RDB.h
include/configs/BSC9132QDS.h
include/configs/C29XPCIE.h
include/configs/HWW1U1A.h
include/configs/MPC8349EMDS.h
include/configs/MPC8536DS.h
include/configs/MPC8540ADS.h
include/configs/MPC8541CDS.h
include/configs/MPC8544DS.h
include/configs/MPC8548CDS.h
include/configs/MPC8555CDS.h
include/configs/MPC8560ADS.h
include/configs/MPC8568MDS.h
include/configs/MPC8569MDS.h
include/configs/MPC8572DS.h
include/configs/MPC8610HPCD.h
include/configs/MPC8641HPCN.h
include/configs/P1010RDB.h
include/configs/P1022DS.h
include/configs/P1023RDB.h
include/configs/P1_P2_RDB.h
include/configs/P2020COME.h
include/configs/P2020DS.h
include/configs/P2041RDB.h
include/configs/P4080DS.h
include/configs/PN62.h [deleted file]
include/configs/T1040QDS.h
include/configs/T1040RDB.h [new file with mode: 0644]
include/configs/T1042RDB_PI.h [new file with mode: 0644]
include/configs/T2080QDS.h [new file with mode: 0644]
include/configs/T4240QDS.h
include/configs/VCMA9.h
include/configs/afeb9260.h
include/configs/alpr.h
include/configs/am335x_evm.h
include/configs/am335x_igep0033.h
include/configs/am3517_crane.h
include/configs/am3517_evm.h
include/configs/am43xx_evm.h
include/configs/arndale.h
include/configs/at91sam9260ek.h
include/configs/at91sam9263ek.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9n12ek.h
include/configs/at91sam9x5ek.h
include/configs/balloon3.h
include/configs/bct-brettl2.h
include/configs/bf506f-ezkit.h
include/configs/bf525-ucr2.h
include/configs/bf533-stamp.h
include/configs/bf537-minotaur.h
include/configs/bf537-pnav.h
include/configs/bf537-srv1.h
include/configs/bf537-stamp.h
include/configs/bf538f-ezkit.h
include/configs/blackstamp.h
include/configs/cm-bf537e.h
include/configs/cm-bf537u.h
include/configs/cm-bf548.h
include/configs/cm_t335.h [new file with mode: 0644]
include/configs/cm_t35.h
include/configs/controlcenterd.h
include/configs/corenet_ds.h
include/configs/corvus.h [new file with mode: 0644]
include/configs/cpu9260.h
include/configs/devkit8000.h
include/configs/dig297.h
include/configs/dnp5370.h
include/configs/dra7xx_evm.h
include/configs/eb_cpux9k2.h
include/configs/ecovec.h
include/configs/ethernut5.h
include/configs/exynos5250-dt.h
include/configs/highbank.h
include/configs/ibf-dsp561.h
include/configs/km/kmp204x-common.h
include/configs/koelsch.h [new file with mode: 0644]
include/configs/kzm9g.h
include/configs/lager.h [new file with mode: 0644]
include/configs/lp8x4x.h
include/configs/malta.h [moved from include/configs/qemu-malta.h with 66% similarity]
include/configs/mcx.h
include/configs/meesc.h
include/configs/mpq101.h
include/configs/mx51_efikamx.h
include/configs/nokia_rx51.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap3_evm_common.h
include/configs/omap3_evm_quick_nand.h
include/configs/omap3_igep00x0.h
include/configs/omap3_logic.h
include/configs/omap3_mvblx.h
include/configs/omap3_overo.h
include/configs/omap3_pandora.h
include/configs/omap3_sdp3430.h
include/configs/omap3_zoom1.h
include/configs/omap3_zoom2.h
include/configs/omap4_common.h
include/configs/omap4_panda.h
include/configs/omap5_uevm.h
include/configs/origen.h
include/configs/otc570.h
include/configs/p1_p2_rdb_pc.h
include/configs/p1_twr.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/pcm051.h
include/configs/pm9261.h
include/configs/pm9263.h
include/configs/pm9g45.h
include/configs/sama5d3xek.h
include/configs/sandbox.h
include/configs/sbc35_a9g20.h
include/configs/sbc8548.h
include/configs/scb9328.h
include/configs/siemens-am33x-common.h
include/configs/smdkv310.h
include/configs/snapper9260.h
include/configs/snowball.h
include/configs/socfpga_cyclone5.h
include/configs/socrates.h
include/configs/spieval.h [deleted file]
include/configs/stamp9g20.h
include/configs/stxgp3.h
include/configs/stxssa.h
include/configs/t4qds.h
include/configs/tam3517-common.h
include/configs/tao3530.h [new file with mode: 0644]
include/configs/taurus.h [new file with mode: 0644]
include/configs/tcm-bf537.h
include/configs/tec-ng.h [new file with mode: 0644]
include/configs/tegra114-common.h
include/configs/tegra30-common.h
include/configs/ti_armv7_common.h
include/configs/trats.h
include/configs/trats2.h
include/configs/tricorder.h
include/configs/u8500_href.h
include/configs/usb_a9263.h [new file with mode: 0644]
include/configs/vexpress_common.h
include/configs/vl_ma2sc.h
include/configs/xpedite517x.h
include/configs/xpedite520x.h
include/configs/xpedite537x.h
include/configs/xpedite550x.h
include/configs/zipitz2.h
include/configs/zynq.h
include/dwmmc.h
include/faraday/ftsdc021.h [new file with mode: 0644]
include/fm_eth.h
include/fsl_ddr.h [moved from arch/powerpc/cpu/mpc8xxx/ddr/ddr.h with 97% similarity]
include/fsl_ddr_dimm_params.h [moved from arch/powerpc/include/asm/fsl_ddr_dimm_params.h with 100% similarity]
include/fsl_ddr_sdram.h [moved from arch/powerpc/include/asm/fsl_ddr_sdram.h with 98% similarity]
include/fsl_ifc.h [moved from arch/powerpc/include/asm/fsl_ifc.h with 99% similarity]
include/fsl_immap.h [new file with mode: 0644]
include/fsl_mdio.h
include/i2c.h
include/linux/mtd/mtd.h
include/micrel.h
include/msc01.h [new file with mode: 0644]
include/mtd/mtd-abi.h
include/net.h
include/os.h
include/pci.h
include/pci_ids.h
include/pci_msc01.h [new file with mode: 0644]
include/phy.h
include/scf0403_lcd.h [new file with mode: 0644]
include/spi.h
include/spi_flash.h
include/tsec.h
include/twl6030.h
lib/Makefile
lib/fdtdec.c
lib/lzma/Makefile
lib/lzo/Makefile
lib/rsa/Makefile
lib/time.c
lib/zlib/Makefile
nand_spl/board/amcc/acadia/Makefile
nand_spl/board/amcc/bamboo/Makefile
nand_spl/board/amcc/canyonlands/Makefile
nand_spl/board/amcc/kilauea/Makefile
nand_spl/board/amcc/sequoia/Makefile
nand_spl/board/freescale/mpc8315erdb/Makefile
nand_spl/board/freescale/mpc8536ds/Makefile
nand_spl/board/freescale/mpc8569mds/Makefile
nand_spl/board/freescale/mpc8569mds/nand_boot.c
nand_spl/board/freescale/mpc8572ds/Makefile
nand_spl/board/freescale/p1023rds/Makefile
nand_spl/board/freescale/p1023rds/nand_boot.c
nand_spl/board/freescale/p1_p2_rdb/Makefile
nand_spl/board/freescale/p1_p2_rdb/nand_boot.c
nand_spl/board/sheldon/simpc8313/Makefile
net/tftp.c
post/board/lwmon/Makefile
post/board/lwmon5/Makefile
post/board/netta/Makefile
post/board/pdm360ng/Makefile
post/cpu/mpc83xx/Makefile
post/cpu/mpc8xx/Makefile
post/cpu/ppc4xx/Makefile
post/drivers/Makefile
post/lib_powerpc/Makefile
post/lib_powerpc/fpu/Makefile
scripts/Makefile.build
spl/Makefile
tools/buildman/README
tools/buildman/board.py
tools/gdb/Makefile
tools/imls/Makefile [deleted file]
tools/imls/README [deleted file]
tools/imls/imls.c [deleted file]
tools/patman/README
tools/patman/commit.py
tools/patman/patchstream.py
tools/updater/Makefile [deleted file]
tools/updater/cmd_flash.c [deleted file]
tools/updater/ctype.c [deleted file]
tools/updater/dummy.c [deleted file]
tools/updater/flash.c [deleted file]
tools/updater/flash_hw.c [deleted file]
tools/updater/junk [deleted file]
tools/updater/ppcstring.S [deleted file]
tools/updater/string.c [deleted file]
tools/updater/update.c [deleted file]
tools/updater/utils.c [deleted file]

diff --git a/CREDITS b/CREDITS
index 3b657e9..52f289e 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -143,7 +143,7 @@ W: www.freescale.com
 
 N: Dr. Wolfgang Grandegger
 E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards
+D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
 W: www.denx.de
 
 N: Peter Figuli
diff --git a/MAKEALL b/MAKEALL
index 80cd4f8..a74f0fc 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -18,6 +18,7 @@ usage()
          -c CPU,    --cpu CPU         Build all boards with cpu CPU
          -v VENDOR, --vendor VENDOR   Build all boards with vendor VENDOR
          -s SOC,    --soc SOC         Build all boards with soc SOC
+         -b BOARD,  --board BOARD     Build all boards with board name BOARD
          -l,        --list            List all targets to be built
          -m,        --maintainers     List all targets and maintainer email
          -M,        --mails           List all targets and all affilated emails
@@ -59,8 +60,8 @@ usage()
        exit ${ret}
 }
 
-SHORT_OPTS="ha:c:v:s:lmMCnr"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors"
+SHORT_OPTS="ha:c:v:s:b:lmMCnr"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors"
 
 # Option processing based on util-linux-2.13/getopt-parse.bash
 
@@ -121,6 +122,17 @@ while true ; do
                fi
                SELECTED='y'
                shift 2 ;;
+       -b|--board)
+               # echo "Option BOARD: argument \`$2'"
+               if [ "$opt_b" ] ; then
+                       opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")"
+               else
+                       # We need to check the 7th field too
+                       # for boards whose 6th field is "-"
+                       opt_b="(\$6 == \"$2\" || \$7 == \"$2\")"
+               fi
+               SELECTED='y'
+               shift 2 ;;
        -C|--check)
                CHECK='C=1'
                shift ;;
@@ -158,6 +170,7 @@ FILTER="\$1 !~ /^#/"
 [ "$opt_c" ] && FILTER="${FILTER} && $opt_c"
 [ "$opt_s" ] && FILTER="${FILTER} && $opt_s"
 [ "$opt_v" ] && FILTER="${FILTER} && $opt_v"
+[ "$opt_b" ] && FILTER="${FILTER} && $opt_b"
 
 if [ "$SELECTED" ] ; then
        SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg)
index 1f499c5..0d86b55 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -5,10 +5,10 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-VERSION = 2013
-PATCHLEVEL = 10
+VERSION = 2014
+PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -65,11 +65,9 @@ endif
 # the object files are placed in the source directory.
 #
 
-ifdef O
 ifeq ("$(origin O)", "command line")
 BUILD_DIR := $(O)
 endif
-endif
 
 # Call a source code checker (by default, "sparse") as part of the
 # C compilation.
@@ -138,7 +136,6 @@ unexport CDPATH
 # The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC
 # is "yes"), so compile examples after U-Boot is compiled.
 SUBDIR_TOOLS = tools
-SUBDIR_EXAMPLES = examples/standalone examples/api
 SUBDIRS = $(SUBDIR_TOOLS)
 
 .PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE)
@@ -152,8 +149,10 @@ all:
 sinclude $(obj)include/autoconf.mk.dep
 sinclude $(obj)include/autoconf.mk
 
+SUBDIR_EXAMPLES-y := examples/standalone
+SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api
 ifndef CONFIG_SANDBOX
-SUBDIRS += $(SUBDIR_EXAMPLES)
+SUBDIRS += $(SUBDIR_EXAMPLES-y)
 endif
 
 # load ARCH, BOARD, and CPU configuration
@@ -231,87 +230,67 @@ OBJS := $(addprefix $(obj),$(OBJS))
 
 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
 
-LIBS-y += lib/libgeneric.o
-LIBS-y += lib/rsa/librsa.o
-LIBS-y += lib/lzma/liblzma.o
-LIBS-y += lib/lzo/liblzo.o
-LIBS-y += lib/zlib/libz.o
-LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o
-LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o
-LIBS-y += $(CPUDIR)/lib$(CPU).o
+LIBS-y += lib/
+LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
+LIBS-y += $(CPUDIR)/
 ifdef SOC
-LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o
-endif
-ifeq ($(CPU),ixp)
-LIBS-y += drivers/net/npe/libnpe.o
-endif
-LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
-LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/libfs.o \
-       fs/fat/libfat.o
-LIBS-y += net/libnet.o
-LIBS-y += disk/libdisk.o
-LIBS-y += drivers/libdrivers.o
-LIBS-y += drivers/dma/libdma.o
-LIBS-y += drivers/gpio/libgpio.o
-LIBS-y += drivers/i2c/libi2c.o
-LIBS-y += drivers/input/libinput.o
-LIBS-y += drivers/mmc/libmmc.o
-LIBS-y += drivers/mtd/libmtd.o
-LIBS-y += drivers/mtd/nand/libnand.o
-LIBS-y += drivers/mtd/onenand/libonenand.o
-LIBS-y += drivers/mtd/ubi/libubi.o
-LIBS-y += drivers/mtd/spi/libspi_flash.o
-LIBS-y += drivers/net/libnet.o
-LIBS-y += drivers/net/phy/libphy.o
-LIBS-y += drivers/pci/libpci.o
-LIBS-y += drivers/power/libpower.o \
-       drivers/power/fuel_gauge/libfuel_gauge.o \
-       drivers/power/mfd/libmfd.o \
-       drivers/power/pmic/libpmic.o \
-       drivers/power/battery/libbattery.o
-LIBS-y += drivers/spi/libspi.o
-ifeq ($(CPU),mpc83xx)
-LIBS-y += drivers/qe/libqe.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc85xx)
-LIBS-y += drivers/qe/libqe.o
-LIBS-y += drivers/net/fm/libfm.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-ifeq ($(CPU),mpc86xx)
-LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
-LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
-endif
-LIBS-y += drivers/serial/libserial.o
-LIBS-y += drivers/usb/eth/libusb_eth.o
-LIBS-y += drivers/usb/gadget/libusb_gadget.o
-LIBS-y += drivers/usb/host/libusb_host.o
-LIBS-y += drivers/usb/musb/libusb_musb.o
-LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
-LIBS-y += drivers/usb/phy/libusb_phy.o
-LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
-LIBS-y += common/libcommon.o
-LIBS-y += lib/libfdt/libfdt.o
-LIBS-y += api/libapi.o
-LIBS-y += post/libpost.o
-LIBS-y += test/libtest.o
+LIBS-y += $(CPUDIR)/$(SOC)/
+endif
+LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/
+LIBS-$(CONFIG_OF_EMBED) += dts/
+LIBS-y += arch/$(ARCH)/lib/
+LIBS-y += fs/
+LIBS-y += net/
+LIBS-y += disk/
+LIBS-y += drivers/
+LIBS-y += drivers/dma/
+LIBS-y += drivers/gpio/
+LIBS-y += drivers/i2c/
+LIBS-y += drivers/input/
+LIBS-y += drivers/mmc/
+LIBS-y += drivers/mtd/
+LIBS-y += drivers/mtd/nand/
+LIBS-y += drivers/mtd/onenand/
+LIBS-y += drivers/mtd/ubi/
+LIBS-y += drivers/mtd/spi/
+LIBS-y += drivers/net/
+LIBS-y += drivers/net/phy/
+LIBS-y += drivers/pci/
+LIBS-y += drivers/power/ \
+       drivers/power/fuel_gauge/ \
+       drivers/power/mfd/ \
+       drivers/power/pmic/ \
+       drivers/power/battery/
+LIBS-y += drivers/spi/
+LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/
+LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+LIBS-y += drivers/serial/
+LIBS-y += drivers/usb/eth/
+LIBS-y += drivers/usb/gadget/
+LIBS-y += drivers/usb/host/
+LIBS-y += drivers/usb/musb/
+LIBS-y += drivers/usb/musb-new/
+LIBS-y += drivers/usb/phy/
+LIBS-y += drivers/usb/ulpi/
+LIBS-y += common/
+LIBS-y += lib/libfdt/
+LIBS-$(CONFIG_API) += api/
+LIBS-y += post/
+LIBS-y += test/
 
 ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
-LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
+LIBS-y += arch/$(ARCH)/imx-common/
 endif
 
-LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o
+LIBS-$(CONFIG_ARM) += arch/arm/cpu/
+LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/
 
+LIBS-y += board/$(BOARDDIR)/
+
+LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y))
 LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
 .PHONY : $(LIBS)
 
-LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o
-LIBBOARD := $(addprefix $(obj),$(LIBBOARD))
-
 # Add GCC lib
 ifdef USE_PRIVATE_LIBGCC
 ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
@@ -335,7 +314,7 @@ LDPPFLAGS += \
          sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
 
 __OBJS := $(subst $(obj),,$(OBJS))
-__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD))
+__LIBS := $(subst $(obj),,$(LIBS))
 
 #########################################################################
 #########################################################################
@@ -371,16 +350,18 @@ endif
 
 # enable combined SPL/u-boot/dtb rules for tegra
 ifneq ($(CONFIG_TEGRA),)
+ifeq ($(CONFIG_SPL),y)
 ifeq ($(CONFIG_OF_SEPARATE),y)
 ALL-y += $(obj)u-boot-dtb-tegra.bin
 else
 ALL-y += $(obj)u-boot-nodtb-tegra.bin
 endif
 endif
+endif
 
 build := -f $(TOPDIR)/scripts/Makefile.build -C
 
-all:           $(ALL-y) $(SUBDIR_EXAMPLES)
+all:           $(ALL-y) $(SUBDIR_EXAMPLES-y)
 
 $(obj)u-boot.dtb:      checkdtc $(obj)u-boot
                $(MAKE) $(build) dts binary
@@ -393,7 +374,7 @@ $(obj)u-boot.hex:   $(obj)u-boot
                $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
 
 $(obj)u-boot.srec:     $(obj)u-boot
-               $(OBJCOPY) -O srec $< $@
+               $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
 
 $(obj)u-boot.bin:      $(obj)u-boot
                $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
@@ -549,7 +530,7 @@ GEN_UBOOT = \
 endif
 
 $(obj)u-boot:  depend \
-               $(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
+               $(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
                $(GEN_UBOOT)
 ifeq ($(CONFIG_KALLSYMS),y)
                smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \
@@ -564,16 +545,11 @@ $(OBJS):
 
 $(LIBS):       depend $(SUBDIR_TOOLS)
                $(MAKE) $(build) $(dir $(subst $(obj),,$@))
-               mv $(dir $@)built-in.o $@
-
-$(LIBBOARD):   depend $(LIBS)
-               $(MAKE) $(build) $(dir $(subst $(obj),,$@))
-               mv $(dir $@)built-in.o $@
 
 $(SUBDIRS):    depend
                $(MAKE) -C $@ all
 
-$(SUBDIR_EXAMPLES): $(obj)u-boot
+$(SUBDIR_EXAMPLES-y): $(obj)u-boot
 
 $(LDSCRIPT):   depend
                $(MAKE) -C $(dir $@) $(notdir $@)
@@ -593,9 +569,6 @@ $(obj)spl/u-boot-spl.bin:   $(SUBDIR_TOOLS) depend
 $(obj)tpl/u-boot-tpl.bin:      $(SUBDIR_TOOLS) depend
                $(MAKE) -C spl all CONFIG_TPL_BUILD=y
 
-updater:
-               $(MAKE) -C tools/updater all
-
 # Explicitly make _depend in subdirs containing multiple targets to prevent
 # parallel sub-makes creating .depend files simultaneously.
 depend dep:    $(TIMESTAMP_FILE) $(VERSION_FILE) \
@@ -634,7 +607,7 @@ SYSTEM_MAP = \
                grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
                LC_ALL=C sort
 $(obj)System.map:      $(obj)u-boot
-               @$(call SYSTEM_MAP,$<) > $(obj)System.map
+               @$(call SYSTEM_MAP,$<) > $@
 
 checkthumb:
        @if test $(call cc-version) -lt 0404; then \
@@ -738,7 +711,7 @@ else        # !config.mk
 all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
 $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \
 $(filter-out tools,$(SUBDIRS)) \
-updater depend dep tags ctags etags cscope $(obj)System.map:
+depend dep tags ctags etags cscope $(obj)System.map:
        @echo "System not configured - see README" >&2
        @ exit 1
 
@@ -806,12 +779,6 @@ sinclude $(obj).boards.depend
 $(obj).boards.depend:  boards.cfg
        @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@
 
-#
-# Functions to generate common board directory names
-#
-lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
-ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
-
 #########################################################################
 #########################################################################
 
@@ -842,7 +809,6 @@ clean:
               $(obj)board/matrix_vision/*/bootscript.img                 \
               $(obj)board/voiceblue/eeprom                               \
               $(obj)u-boot.lds                                           \
-              $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]          \
               $(obj)arch/blackfin/cpu/init.{lds,elf}
        @rm -f $(obj)include/bmp_logo.h
        @rm -f $(obj)include/bmp_logo_data.h
@@ -888,8 +854,6 @@ clobber:    tidy
        @rm -f $(obj)MLO MLO.byteswap
        @rm -f $(obj)SPL
        @rm -f $(obj)tools/xway-swap-bytes
-       @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
-       @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
        @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
        @rm -fr $(obj)include/generated
        @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
diff --git a/README b/README
index f0ffaf4..8f0b38c 100644 (file)
--- a/README
+++ b/README
@@ -423,16 +423,50 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
                This value denotes start offset of DSP CCSR space.
 
-               CONFIG_SYS_FSL_DDR_EMU
-               Specify emulator support for DDR. Some DDR features such as
-               deskew training are not available.
-
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
                Defines the endianess of the CPU. Implementation of those
                values is arch specific.
 
+               CONFIG_SYS_FSL_DDR
+               Freescale DDR driver in use. This type of DDR controller is
+               found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core
+               SoCs.
+
+               CONFIG_SYS_FSL_DDR_ADDR
+               Freescale DDR memory-mapped register base.
+
+               CONFIG_SYS_FSL_DDR_EMU
+               Specify emulator support for DDR. Some DDR features such as
+               deskew training are not available.
+
+               CONFIG_SYS_FSL_DDRC_GEN1
+               Freescale DDR1 controller.
+
+               CONFIG_SYS_FSL_DDRC_GEN2
+               Freescale DDR2 controller.
+
+               CONFIG_SYS_FSL_DDRC_GEN3
+               Freescale DDR3 controller.
+
+               CONFIG_SYS_FSL_DDRC_ARM_GEN3
+               Freescale DDR3 controller for ARM-based SoCs.
+
+               CONFIG_SYS_FSL_DDR1
+               Board config to use DDR1. It can be enabled for SoCs with
+               Freescale DDR1 or DDR2 controllers, depending on the board
+               implemetation.
+
+               CONFIG_SYS_FSL_DDR2
+               Board config to use DDR2. It can be eanbeld for SoCs with
+               Freescale DDR2 or DDR3 controllers, depending on the board
+               implementation.
+
+               CONFIG_SYS_FSL_DDR3
+               Board config to use DDR3. It can be enabled for SoCs with
+               Freescale DDR3 controllers.
+
 - Intel Monahans options:
                CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
 
@@ -1979,6 +2013,21 @@ CBFS (Coreboot Filesystem) support
                kernel). Defining CONFIG_STATUS_LED enables this
                feature in U-Boot.
 
+               Additional options:
+
+               CONFIG_GPIO_LED
+               The status LED can be connected to a GPIO pin.
+               In such cases, the gpio_led driver can be used as a
+               status LED backend implementation. Define CONFIG_GPIO_LED
+               to include the gpio_led driver in the U-Boot binary.
+
+               CONFIG_GPIO_LED_INVERTED_TABLE
+               Some GPIO connected LEDs may have inverted polarity in which
+               case the GPIO high value corresponds to LED off state and
+               GPIO low value corresponds to LED on state.
+               In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
+               with a list of GPIO LEDs that have inverted polarity.
+
 - CAN Support: CONFIG_CAN_DRIVER
 
                Defining CONFIG_CAN_DRIVER enables CAN driver support
@@ -2056,6 +2105,48 @@ CBFS (Coreboot Filesystem) support
                  - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
                  - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
 
+               - drivers/i2c/sh_i2c.c:
+                 - activate this driver with CONFIG_SYS_I2C_SH
+                 - This driver adds from 2 to 5 i2c buses
+
+                 - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
+                 - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
+                 - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
+                 - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
+                 - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
+                 - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
+                 - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
+                 - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
+                 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
+                 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
+                 - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
+                 - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
+                 - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
+
+               - drivers/i2c/omap24xx_i2c.c
+                 - activate this driver with CONFIG_SYS_I2C_OMAP24XX
+                 - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0
+                 - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1
+                 - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2
+                 - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3
+                 - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4
+                 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4
+
+               - drivers/i2c/zynq_i2c.c
+                 - activate this driver with CONFIG_SYS_I2C_ZYNQ
+                 - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting
+                 - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr
+
+               - drivers/i2c/s3c24x0_i2c.c:
+                 - activate this driver with CONFIG_SYS_I2C_S3C24X0
+                 - This driver adds i2c buses (11 for Exynos5250, Exynos5420
+                   9 i2c buses for Exynos4 and 1 for S3C24X0 SoCs from Samsung)
+                   with a fix speed from 100000 and the slave addr 0!
+
                additional defines:
 
                CONFIG_SYS_NUM_I2C_BUSES
@@ -3162,7 +3253,7 @@ FIT uImage format:
 
                CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
                Set for the SPL on PPC mpc8xxx targets, support for
-               arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+               drivers/ddr/fsl/libddr.o in SPL binary.
 
                CONFIG_SPL_COMMON_INIT_DDR
                Set for common ddr init with serial presence detect in
index fb130ff..3c095ee 100644 (file)
@@ -4,5 +4,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \
-                      api_platform-$(ARCH).o
+obj-y += api.o api_display.o api_net.o api_storage.o
+obj-$(CONFIG_ARM) += api_platform-arm.o
+obj-$(CONFIG_PPC) += api_platform-powerpc.o
index bdabcf4..fd3e5fb 100644 (file)
@@ -103,3 +103,6 @@ ALL-y += checkarmreloc
 # such usage by requiring word relocations.
 PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
 endif
+
+# limit ourselves to the sections we want in the .bin.
+OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn
index fd0da53..b2d30b1 100644 (file)
@@ -1,2 +1,3 @@
+obj-$(CONFIG_AT91FAMILY) += at91-common/
 obj-$(CONFIG_TEGRA) += $(SOC)-common/
 obj-$(CONFIG_TEGRA) += tegra-common/
index 9294611..72c69b9 100644 (file)
@@ -49,33 +49,68 @@ int get_num_cpus(void)
  * Timing tables for each SOC for all four oscillator options.
  */
 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
-       /* T20: 1 GHz */
-       /*  n,  m, p, cpcon */
-       {{ 1000, 13, 0, 12},    /* OSC 13M */
-        { 625,  12, 0, 8},     /* OSC 19.2M */
-        { 1000, 12, 0, 12},    /* OSC 12M */
-        { 1000, 26, 0, 12},    /* OSC 26M */
+       /*
+        * T20: 1 GHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      22:20    3
+        * PLLX_BASE  n      17: 8   10
+        * PLLX_BASE  m       4: 0    5
+        * PLLX_MISC  cpcon  11: 8    4
+        */
+       {
+               { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+               { .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+               { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+               { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
        },
-
-       /* T25: 1.2 GHz */
-       {{ 923, 10, 0, 12},
-        { 750, 12, 0, 8},
-        { 600,  6, 0, 12},
-        { 600, 13, 0, 12},
+       /*
+        * T25: 1.2 GHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      22:20    3
+        * PLLX_BASE  n      17: 8   10
+        * PLLX_BASE  m       4: 0    5
+        * PLLX_MISC  cpcon  11: 8    4
+        */
+       {
+               { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+               { .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+               { .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+               { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
        },
-
-       /* T30: 1.4 GHz */
-       {{ 862, 8, 0, 8},
-        { 583, 8, 0, 4},
-        { 700, 6, 0, 8},
-        { 700, 13, 0, 8},
+       /*
+        * T30: 1.4 GHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      22:20    3
+        * PLLX_BASE  n      17: 8   10
+        * PLLX_BASE  m       4: 0    5
+        * PLLX_MISC  cpcon  11: 8    4
+        */
+       {
+               { .n = 862, .m =  8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+               { .n = 583, .m =  8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
+               { .n = 700, .m =  6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+               { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
        },
-
-       /* T114: 1.4 GHz */
-       {{ 862, 8, 0, 8},
-        { 583, 8, 0, 4},
-        { 696, 12, 0, 8},
-        { 700, 13, 0, 8},
+       /*
+        * T114: 700 MHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      23:20    4
+        * PLLX_BASE  n      15: 8    8
+        * PLLX_BASE  m       7: 0    8
+        */
+       {
+               { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+               { .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+               { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+               { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
        },
 };
 
@@ -100,6 +135,7 @@ void adjust_pllp_out_freqs(void)
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
                u32 divp, u32 cpcon)
 {
+       int chip = tegra_get_chip();
        u32 reg;
 
        /* If PLLX is already enabled, just return */
@@ -116,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
        writel(reg, &pll->pll_base);
 
        /* Set cpcon to PLLX_MISC */
-       reg = (cpcon << PLL_CPCON_SHIFT);
+       if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+               reg = (cpcon << PLL_CPCON_SHIFT);
+       else
+               reg = 0;
 
        /* Set dccon to PLLX_MISC if freq > 600MHz */
        if (divn > 600)
index 5dd9048..46ed055 100644 (file)
@@ -7,43 +7,41 @@
  */
 
 #include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/gpio.h>
 #include <asm/arch/gpio.h>
 
 #ifdef CONFIG_RED_LED
 void red_led_on(void)
 {
-       at91_set_gpio_value(CONFIG_RED_LED, 1);
+       gpio_set_value(CONFIG_RED_LED, 1);
 }
 
 void red_led_off(void)
 {
-       at91_set_gpio_value(CONFIG_RED_LED, 0);
+       gpio_set_value(CONFIG_RED_LED, 0);
 }
 #endif
 
 #ifdef CONFIG_GREEN_LED
 void green_led_on(void)
 {
-       at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+       gpio_set_value(CONFIG_GREEN_LED, 0);
 }
 
 void green_led_off(void)
 {
-       at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+       gpio_set_value(CONFIG_GREEN_LED, 1);
 }
 #endif
 
 #ifdef CONFIG_YELLOW_LED
 void yellow_led_on(void)
 {
-       at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+       gpio_set_value(CONFIG_YELLOW_LED, 0);
 }
 
 void yellow_led_off(void)
 {
-       at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+       gpio_set_value(CONFIG_YELLOW_LED, 1);
 }
 #endif
index 40bcc31..80fb9bd 100644 (file)
@@ -51,11 +51,13 @@ SECTIONS
 
        _end = .;
 
-       /DISCARD/ : { *(.dynstr*) }
-       /DISCARD/ : { *(.dynsym*) }
-       /DISCARD/ : { *(.dynamic*) }
-       /DISCARD/ : { *(.hash*) }
-       /DISCARD/ : { *(.plt*) }
-       /DISCARD/ : { *(.interp*) }
-       /DISCARD/ : { *(.gnu*) }
+       .dynsym _end : { *(.dynsym) }
+       .dynbss : { *(.dynbss) }
+       .dynstr : { *(.dynstr*) }
+       .dynamic : { *(.dynamic*) }
+       .hash : { *(.hash*) }
+       .plt : { *(.plt*) }
+       .interp : { *(.interp*) }
+       .gnu : { *(.gnu*) }
+       .ARM.exidx : { *(.ARM.exidx*) }
 }
index 4927736..76b499d 100644 (file)
@@ -51,11 +51,13 @@ SECTIONS
 
        _end = .;
 
-       /DISCARD/ : { *(.dynstr*) }
-       /DISCARD/ : { *(.dynsym*) }
-       /DISCARD/ : { *(.dynamic*) }
-       /DISCARD/ : { *(.hash*) }
-       /DISCARD/ : { *(.plt*) }
-       /DISCARD/ : { *(.interp*) }
-       /DISCARD/ : { *(.gnu*) }
+       .dynsym _end : { *(.dynsym) }
+       .dynbss : { *(.dynbss) }
+       .dynstr : { *(.dynstr*) }
+       .dynamic : { *(.dynamic*) }
+       .hash : { *(.hash*) }
+       .plt : { *(.plt*) }
+       .interp : { *(.interp*) }
+       .gnu : { *(.gnu*) }
+       .ARM.exidx : { *(.ARM.exidx*) }
 }
index d3347b3..0467d00 100644 (file)
@@ -12,7 +12,7 @@ obj-y += cache_v7.o
 obj-y  += cpu.o
 obj-y  += syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y  += lowlevel_init.o
 endif
index 966fcab..5566310 100644 (file)
@@ -19,4 +19,3 @@ obj-y += ddr.o
 obj-y  += emif4.o
 obj-y  += board.o
 obj-y  += mux.o
-obj-$(CONFIG_NAND_OMAP_GPMC)   += elm.o
index 803aa9c..c7dad66 100644 (file)
@@ -241,3 +241,11 @@ void s_init(void)
        sdram_init();
 #endif
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif /* !CONFIG_SYS_DCACHE_OFF */
index 8e5f3c6..0672798 100644 (file)
@@ -101,9 +101,15 @@ void do_setup_dpll(const struct dpll_regs *dpll_regs,
 static void setup_dplls(void)
 {
        const struct dpll_params *params;
-       do_setup_dpll(&dpll_core_regs, &dpll_core);
-       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu);
-       do_setup_dpll(&dpll_per_regs, &dpll_per);
+
+       params = get_dpll_core_params();
+       do_setup_dpll(&dpll_core_regs, params);
+
+       params = get_dpll_mpu_params();
+       do_setup_dpll(&dpll_mpu_regs, params);
+
+       params = get_dpll_per_params();
+       do_setup_dpll(&dpll_per_regs, params);
        writel(0x300, &cmwkup->clkdcoldodpllper);
 
        params = get_dpll_ddr_params();
index fabe259..92142c8 100644 (file)
@@ -62,6 +62,21 @@ const struct dpll_params dpll_core = {
 const struct dpll_params dpll_per = {
                960, OSC-1, 5, -1, -1, -1, -1};
 
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+       return &dpll_mpu;
+}
+
+const struct dpll_params *get_dpll_core_params(void)
+{
+       return &dpll_core;
+}
+
+const struct dpll_params *get_dpll_per_params(void)
+{
+       return &dpll_per;
+}
+
 void setup_clocks_for_console(void)
 {
        clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
index c4890f2..97c00b4 100644 (file)
@@ -18,6 +18,7 @@
 
 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
+struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
 
 const struct dpll_regs dpll_mpu_regs = {
        .cm_clkmode_dpll        = CM_WKUP + 0x560,
@@ -47,15 +48,9 @@ const struct dpll_regs dpll_ddr_regs = {
        .cm_idlest_dpll         = CM_WKUP + 0x5A4,
        .cm_clksel_dpll         = CM_WKUP + 0x5AC,
        .cm_div_m2_dpll         = CM_WKUP + 0x5B0,
+       .cm_div_m4_dpll         = CM_WKUP + 0x5B8,
 };
 
-const struct dpll_params dpll_mpu = {
-               -1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
-               -1, -1, -1, -1, -1, -1, -1};
-const struct dpll_params dpll_per = {
-               -1, -1, -1, -1, -1, -1, -1};
-
 void setup_clocks_for_console(void)
 {
        /* Do not add any spl_debug prints in this function */
@@ -107,4 +102,7 @@ void enable_basic_clocks(void)
        };
 
        do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
+
+       /* Select the Master osc clk as Timer2 clock source */
+       writel(0x1, &cmdpll->clktimer2clk);
 }
index fa697c7..d05e666 100644 (file)
@@ -36,6 +36,73 @@ static struct ddr_data_regs *ddr_data_reg[2] = {
 static struct ddr_cmdtctrl *ioctrl_reg = {
                        (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
 
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
+{
+       u32 mr;
+
+       mr_addr |= cs << EMIF_REG_CS_SHIFT;
+       writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+
+       mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
+       debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
+       if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+           ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+           ((mr & 0xff000000) >> 24) == (mr & 0xff))
+               return mr & 0xff;
+       else
+               return mr;
+}
+
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
+{
+       mr_addr |= cs << EMIF_REG_CS_SHIFT;
+       writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
+       writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
+}
+
+static void configure_mr(int nr, u32 cs)
+{
+       u32 mr_addr;
+
+       while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
+               ;
+       set_mr(nr, cs, LPDDR2_MR10, 0x56);
+
+       set_mr(nr, cs, LPDDR2_MR1, 0x43);
+       set_mr(nr, cs, LPDDR2_MR2, 0x2);
+
+       mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
+       set_mr(nr, cs, mr_addr, 0x2);
+}
+
+/*
+ * Configure EMIF4D5 registers and MR registers
+ */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
+{
+       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
+       writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
+       writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
+       writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
+
+       writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
+       writel(regs->emif_rd_wr_lvl_rmp_win,
+              &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
+       writel(regs->emif_rd_wr_lvl_rmp_ctl,
+              &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
+       writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+       writel(regs->emif_rd_wr_exec_thresh,
+              &emif_reg[nr]->emif_rd_wr_exec_thresh);
+
+       writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+       writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+       if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
+               configure_mr(nr, 0);
+               configure_mr(nr, 1);
+       }
+}
+
 /**
  * Configure SDRAM
  */
@@ -72,15 +139,67 @@ void set_sdram_timings(const struct emif_regs *regs, int nr)
        writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
+void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
+{
+}
+
+/*
+ * Configure EXT PHY registers
+ */
+static void ext_phy_settings(const struct emif_regs *regs, int nr)
+{
+       u32 *ext_phy_ctrl_base = 0;
+       u32 *emif_ext_phy_ctrl_base = 0;
+       const u32 *ext_phy_ctrl_const_regs;
+       u32 i = 0;
+       u32 size;
+
+       ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
+       emif_ext_phy_ctrl_base =
+                       (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
+
+       /* Configure external phy control timing registers */
+       for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+               writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+               /* Update shadow registers */
+               writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+       }
+
+       /*
+        * external phy 6-24 registers do not change with
+        * ddr frequency
+        */
+       emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
+
+       if (!size)
+               return;
+
+       for (i = 0; i < size; i++) {
+               writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+               /* Update shadow registers */
+               writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
+       }
+}
+
 /**
  * Configure DDR PHY
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
+       /*
+        * disable initialization and refreshes for now until we
+        * finish programming EMIF regs.
+        */
+       setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
+                    EMIF_REG_INITREF_DIS_MASK);
+
        writel(regs->emif_ddr_phy_ctlr_1,
                &emif_reg[nr]->emif_ddr_phy_ctrl_1);
        writel(regs->emif_ddr_phy_ctlr_1,
                &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
+
+       if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
+               ext_phy_settings(regs, nr);
 }
 
 /**
@@ -88,16 +207,16 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
  */
 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
+       if (!cmd)
+               return;
+
        writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
-       writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
        writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 
        writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
-       writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
        writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 
        writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
-       writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
        writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 }
 
@@ -108,6 +227,9 @@ void config_ddr_data(const struct ddr_data *data, int nr)
 {
        int i;
 
+       if (!data)
+               return;
+
        for (i = 0; i < DDR_DATA_REGS_NR; i++) {
                writel(data->datardsratio0,
                        &(ddr_data_reg[nr]+i)->dt0rdsratio0);
@@ -121,18 +243,23 @@ void config_ddr_data(const struct ddr_data *data, int nr)
                        &(ddr_data_reg[nr]+i)->dt0fwsratio0);
                writel(data->datawrsratio0,
                        &(ddr_data_reg[nr]+i)->dt0wrsratio0);
-               writel(data->datauserank0delay,
-                       &(ddr_data_reg[nr]+i)->dt0rdelays0);
-               writel(data->datadldiff0,
-                       &(ddr_data_reg[nr]+i)->dt0dldiff0);
        }
 }
 
-void config_io_ctrl(unsigned long val)
+void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 {
-       writel(val, &ioctrl_reg->cm0ioctl);
-       writel(val, &ioctrl_reg->cm1ioctl);
-       writel(val, &ioctrl_reg->cm2ioctl);
-       writel(val, &ioctrl_reg->dt0ioctl);
-       writel(val, &ioctrl_reg->dt1ioctl);
+       if (!ioregs)
+               return;
+
+       writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
+       writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
+       writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
+       writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
+       writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
+#ifdef CONFIG_AM43XX
+       writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
+       writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
+       writel(ioregs->emif_sdram_config_ext,
+              &ioctrl_reg->emif_sdram_config_ext);
+#endif
 }
index 59ad25c..d28fceb 100644 (file)
@@ -48,6 +48,11 @@ static struct vtp_reg *vtpreg[2] = {
 #ifdef CONFIG_AM33XX
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 #endif
+#ifdef CONFIG_AM43XX
+static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
+static struct cm_device_inst *cm_device =
+                               (struct cm_device_inst *)CM_DEVICE_INST;
+#endif
 
 #ifdef CONFIG_TI81XX
 void config_dmm(const struct dmm_lisa_map_regs *regs)
@@ -87,7 +92,7 @@ void __weak ddr_pll_config(unsigned int ddrpll_m)
 {
 }
 
-void config_ddr(unsigned int pll, unsigned int ioctrl,
+void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
                const struct ddr_data *data, const struct cmd_control *ctrl,
                const struct emif_regs *regs, int nr)
 {
@@ -99,7 +104,18 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
 
        config_ddr_data(data, nr);
 #ifdef CONFIG_AM33XX
-       config_io_ctrl(ioctrl);
+       config_io_ctrl(ioregs);
+
+       /* Set CKE to be controlled by EMIF/DDR PHY */
+       writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
+#ifdef CONFIG_AM43XX
+       writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
+       while ((readl(&cm_device->cm_dll_ctrl) && CM_DLL_READYST) == 0)
+               ;
+       writel(0x0, &ddrctrl->ddrioctrl);
+
+       config_io_ctrl(ioregs);
 
        /* Set CKE to be controlled by EMIF/DDR PHY */
        writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
@@ -108,6 +124,9 @@ void config_ddr(unsigned int pll, unsigned int ioctrl,
        /* Program EMIF instance */
        config_ddr_phy(regs, nr);
        set_sdram_timings(regs, nr);
-       config_sdram(regs, nr);
+       if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
+               config_sdram_emif4d5(regs, nr);
+       else
+               config_sdram(regs, nr);
 }
 #endif
index b6eb466..56c9e7d 100644 (file)
 
 struct gpmc *gpmc_cfg;
 
-#if defined(CONFIG_CMD_NAND)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-       M_NAND_GPMC_CONFIG1,
-       M_NAND_GPMC_CONFIG2,
-       M_NAND_GPMC_CONFIG3,
-       M_NAND_GPMC_CONFIG4,
-       M_NAND_GPMC_CONFIG5,
-       M_NAND_GPMC_CONFIG6, 0
-};
-#endif
-
 
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
                        u32 size)
@@ -61,11 +50,34 @@ void gpmc_init(void)
 {
        /* putting a blanket check on GPMC based on ZeBu for now */
        gpmc_cfg = (struct gpmc *)GPMC_BASE;
-
-#ifdef CONFIG_CMD_NAND
-       const u32 *gpmc_config = NULL;
-       u32 base = 0;
+#if defined(CONFIG_NOR)
+/* configure GPMC for NOR */
+       const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
+                                               STNOR_GPMC_CONFIG2,
+                                               STNOR_GPMC_CONFIG3,
+                                               STNOR_GPMC_CONFIG4,
+                                               STNOR_GPMC_CONFIG5,
+                                               STNOR_GPMC_CONFIG6,
+                                               STNOR_GPMC_CONFIG7
+                                               };
+       u32 size = GPMC_SIZE_16M;
+       u32 base = CONFIG_SYS_FLASH_BASE;
+#elif defined(CONFIG_NAND)
+/* configure GPMC for NAND */
+       const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
+                                               M_NAND_GPMC_CONFIG2,
+                                               M_NAND_GPMC_CONFIG3,
+                                               M_NAND_GPMC_CONFIG4,
+                                               M_NAND_GPMC_CONFIG5,
+                                               M_NAND_GPMC_CONFIG6,
+                                               0
+                                               };
+       u32 size = GPMC_SIZE_256M;
+       u32 base = CONFIG_SYS_NAND_BASE;
+#else
+       const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
        u32 size = 0;
+       u32 base = 0;
 #endif
        /* global settings */
        writel(0x00000008, &gpmc_cfg->sysconfig);
@@ -81,12 +93,6 @@ void gpmc_init(void)
         */
        writel(0, &gpmc_cfg->cs[0].config7);
        sdelay(1000);
-
-#ifdef CONFIG_CMD_NAND
-       gpmc_config = gpmc_m_nand;
-
-       base = PISMO1_NAND_BASE;
-       size = PISMO1_NAND_SIZE;
-       enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
-#endif
+       /* enable chip-select specific configurations */
+       enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 }
index 51f0a6d..78ecfc8 100644 (file)
@@ -15,7 +15,7 @@
 
 unsigned int has_emac()
 {
-       return cpu_is_sama5d31() || cpu_is_sama5d35();
+       return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
 }
 
 unsigned int has_gmac()
@@ -42,6 +42,8 @@ char *get_cpu_name()
                        return "SAMA5D34";
                case ARCH_EXID_SAMA5D35:
                        return "SAMA5D35";
+               case ARCH_EXID_SAMA5D36:
+                       return "SAMA5D36";
                default:
                        return "Unknown CPU type";
                }
@@ -82,7 +84,7 @@ void at91_seriald_hw_init(void)
        at91_set_a_periph(AT91_PIO_PORTB, 30, 0);       /* DRXD */
 
        /* Enable clock */
-       at91_periph_clk_enable(ATMEL_ID_SYS);
+       at91_periph_clk_enable(ATMEL_ID_DBGU);
 }
 
 #if defined(CONFIG_ATMEL_SPI)
index 3808aed..e3ebfe0 100644 (file)
@@ -60,7 +60,7 @@ int timer_init(void)
        at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
 
        /* Enable PITC Clock */
-       at91_periph_clk_enable(ATMEL_ID_SYS);
+       at91_periph_clk_enable(ATMEL_ID_PIT);
 
        /* Enable PITC */
        writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
index 36fedd6..84a5047 100644 (file)
@@ -1410,7 +1410,8 @@ void set_mmc_clk(int dev_index, unsigned int div)
        else {
                if (proid_is_exynos4412())
                        exynos4x12_set_mmc_clk(dev_index, div);
-               exynos4_set_mmc_clk(dev_index, div);
+               else
+                       exynos4_set_mmc_clk(dev_index, div);
        }
 }
 
index 8002bce..74cc700 100644 (file)
@@ -462,7 +462,7 @@ static int exynos4_pinmux_config(int peripheral, int flags)
        case PERIPH_ID_SDMMC1:
        case PERIPH_ID_SDMMC3:
        case PERIPH_ID_SDMMC4:
-               printf("SDMMC device %d not implemented\n", peripheral);
+               debug("SDMMC device %d not implemented\n", peripheral);
                return -1;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
index 3651c00..ade45fd 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/dmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
 #include <asm/arch/spl.h>
+#include <asm/arch/spi.h>
 
 #include "common_setup.h"
 #include "clock_init.h"
@@ -59,6 +62,121 @@ static int config_branch_prediction(int set_cr_z)
 }
 #endif
 
+#ifdef CONFIG_SPI_BOOTING
+static void spi_rx_tx(struct exynos_spi *regs, int todo,
+                       void *dinp, void const *doutp, int i)
+{
+       uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
+       int rx_lvl, tx_lvl;
+       uint out_bytes, in_bytes;
+
+       out_bytes = todo;
+       in_bytes = todo;
+       setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+       clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+       writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+
+       while (in_bytes) {
+               uint32_t spi_sts;
+               int temp;
+
+               spi_sts = readl(&regs->spi_sts);
+               rx_lvl = ((spi_sts >> 15) & 0x7f);
+               tx_lvl = ((spi_sts >> 6) & 0x7f);
+               while (tx_lvl < 32 && out_bytes) {
+                       temp = 0xffffffff;
+                       writel(temp, &regs->tx_data);
+                       out_bytes -= 4;
+                       tx_lvl += 4;
+               }
+               while (rx_lvl >= 4 && in_bytes) {
+                       temp = readl(&regs->rx_data);
+                       if (rxp)
+                               *rxp++ = temp;
+                       in_bytes -= 4;
+                       rx_lvl -= 4;
+               }
+       }
+}
+
+/*
+ * Copy uboot from spi flash to RAM
+ *
+ * @parma uboot_size   size of u-boot to copy
+ * @param uboot_addr   address in u-boot to copy
+ */
+static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
+{
+       int upto, todo;
+       int i, timeout = 100;
+       struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
+
+       set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
+       /* set the spi1 GPIO */
+       exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
+
+       /* set pktcnt and enable it */
+       writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+       /* set FB_CLK_SEL */
+       writel(SPI_FB_DELAY_180, &regs->fb_clk);
+       /* set CH_WIDTH and BUS_WIDTH as word */
+       setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+                                       SPI_MODE_BUS_WIDTH_WORD);
+       clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
+
+       /* clear rx and tx channel if set priveously */
+       clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+
+       setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
+                       SPI_RX_BYTE_SWAP |
+                       SPI_RX_HWORD_SWAP);
+
+       /* do a soft reset */
+       setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+       clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+
+       /* now set rx and tx channel ON */
+       setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
+       clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
+
+       /* Send read instruction (0x3h) followed by a 24 bit addr */
+       writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
+
+       /* waiting for TX done */
+       while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
+               if (!timeout) {
+                       debug("SPI TIMEOUT\n");
+                       break;
+               }
+               timeout--;
+       }
+
+       for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
+               todo = min(uboot_size - upto, (1 << 15));
+               spi_rx_tx(regs, todo, (void *)(uboot_addr),
+                         (void *)(SPI_FLASH_UBOOT_POS), i);
+       }
+
+       setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
+
+       /*
+        * Let put controller mode to BYTE as
+        * SPI driver does not support WORD mode yet
+        */
+       clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+                                       SPI_MODE_BUS_WIDTH_WORD);
+       writel(0, &regs->swap_cfg);
+
+       /*
+        * Flush spi tx, rx fifos and reset the SPI controller
+        * and clear rx/tx channel
+        */
+       clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+       clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+       clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+}
+#endif
+
 /*
 * Copy U-boot from mmc to RAM:
 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@@ -70,6 +188,9 @@ void copy_uboot_to_ram(void)
 
        u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
        u32 offset = 0, size = 0;
+#ifdef CONFIG_SPI_BOOTING
+       struct spl_machine_param *param = spl_get_machine_params();
+#endif
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
        u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
        void (*end_bootop_from_emmc)(void);
@@ -91,9 +212,8 @@ void copy_uboot_to_ram(void)
        switch (bootmode) {
 #ifdef CONFIG_SPI_BOOTING
        case BOOT_MODE_SERIAL:
-               offset = SPI_FLASH_UBOOT_POS;
-               size = CONFIG_BL2_SIZE;
-               copy_bl2 = get_irom_func(SPI_INDEX);
+               /* Customised function to copy u-boot from SF */
+               exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
                break;
 #endif
        case BOOT_MODE_MMC:
index 24b4c18..6367e09 100644 (file)
@@ -14,6 +14,7 @@
 .arch_extension sec
 .arch_extension virt
 
+       .align  5
 /* the vector table for secure state and HYP mode */
 _monitor_vectors:
        .word 0 /* reset */
@@ -32,7 +33,6 @@ _monitor_vectors:
  * to non-secure state.
  * We use only r0 and r1 here, due to constraints in the caller.
  */
-       .align  5
 _secure_monitor:
        mrc     p15, 0, r1, c1, c1, 0           @ read SCR
        bic     r1, r1, #0x4e                   @ clear IRQ, FIQ, EA, nET bits
index 4d3a165..59f5352 100644 (file)
@@ -17,6 +17,11 @@ obj-y        += vc.o
 obj-y  += abb.o
 endif
 
+ifneq ($(CONFIG_OMAP54XX),)
+obj-y  += pipe3-phy.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y  += boot-common.o
 obj-y  += lowlevel_init.o
index a46783f..423aeb9 100644 (file)
@@ -11,6 +11,7 @@
 
 #include <common.h>
 #include <asm/omap_common.h>
+#include <asm/arch/clock.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 
index bb77b5c..dfa3760 100644 (file)
@@ -779,7 +779,8 @@ void gpi2c_init(void)
        static int gpi2c = 1;
 
        if (gpi2c) {
-               i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+               i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
+                        CONFIG_SYS_OMAP24_I2C_SLAVE);
                gpi2c = 0;
        }
 }
index b0e1caa..cd6289b 100644 (file)
@@ -50,20 +50,6 @@ inline u32 emif_num(u32 base)
                return 0;
 }
 
-/*
- * Get SDRAM type connected to EMIF.
- * Assuming similar SDRAM parts are connected to both EMIF's
- * which is typically the case. So it is sufficient to get
- * SDRAM type from EMIF1.
- */
-u32 emif_sdram_type()
-{
-       struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
-       return (readl(&emif->emif_sdram_config) &
-               EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
-}
-
 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
 {
        u32 mr;
@@ -206,7 +192,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
        }
 }
 
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
@@ -217,47 +203,86 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 
        /*
         * Set invert_clkout (if activated)--DDR_PHYCTRL_1
-        * Invert clock adds an additional half cycle delay on the command
-        * interface.  The additional half cycle, is usually meant to enable
-        * leveling in the situation that DQS is later than CK on the board.It
-        * also helps provide some additional margin for leveling.
+        * Invert clock adds an additional half cycle delay on the
+        * command interface.  The additional half cycle, is usually
+        * meant to enable leveling in the situation that DQS is later
+        * than CK on the board.It also helps provide some additional
+        * margin for leveling.
         */
-       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+       writel(regs->emif_ddr_phy_ctlr_1,
+              &emif->emif_ddr_phy_ctrl_1);
+
+       writel(regs->emif_ddr_phy_ctlr_1,
+              &emif->emif_ddr_phy_ctrl_1_shdw);
        __udelay(130);
 
        writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
-               & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+              & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 
        /* Launch Full leveling */
        writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 
        /* Wait till full leveling is complete */
        readl(&emif->emif_rd_wr_lvl_ctl);
-       __udelay(130);
+             __udelay(130);
 
        /* Read data eye leveling no of samples */
        config_data_eye_leveling_samples(base);
 
-       /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
-       writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
+       /*
+        * Launch 8 incremental WR_LVL- to compensate for
+        * PHY limitation.
+        */
+       writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
+              &emif->emif_rd_wr_lvl_ctl);
+
        __udelay(130);
 
        /* Launch Incremental leveling */
        writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
-       __udelay(130);
+              __udelay(130);
 }
 
-static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
-       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+       u32 fifo_reg;
+
+       fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
+       writel(fifo_reg | 0x00000100,
+              &emif->emif_ddr_fifo_misaligned_clear_1);
+
+       fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
+       writel(fifo_reg | 0x00000100,
+              &emif->emif_ddr_fifo_misaligned_clear_2);
+
+       /* Launch Full leveling */
+       writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+       /* Wait till full leveling is complete */
+       readl(&emif->emif_rd_wr_lvl_ctl);
+             __udelay(130);
+
+       /* Read data eye leveling no of samples */
        config_data_eye_leveling_samples(base);
 
-       writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
-       writel(regs->sdram_config, &emif->emif_sdram_config);
+       /*
+        * Disable leveling. This is because if leveling is kept
+        * enabled, then PHY triggers a false leveling during
+        * EMIF-idle scenario which results in wrong delay
+        * values getting updated. After this the EMIF becomes
+        * unaccessible. So disable it after the first time
+        */
+       writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
+}
+
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+       if (is_omap54xx())
+               omap5_ddr3_leveling(base, regs);
+       else
+               dra7_ddr3_leveling(base, regs);
 }
 
 static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -270,9 +295,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
         * defined, contents of mode Registers must be fully initialized.
         * H/W takes care of this initialization
         */
-       writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
-       writel(regs->sdram_config_init, &emif->emif_sdram_config);
-
        writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 
        /* Update timing registers */
@@ -283,15 +305,24 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
        writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
        writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
-       do_ext_phy_settings(base, regs);
+       /*
+        * The same sequence should work on OMAP5432 as well. But strange that
+        * it is not working
+        */
+       if (omap_revision() == DRA752_ES1_0) {
+               do_ext_phy_settings(base, regs);
+               writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+               writel(regs->sdram_config_init, &emif->emif_sdram_config);
+       } else {
+               writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+               writel(regs->sdram_config_init, &emif->emif_sdram_config);
+               do_ext_phy_settings(base, regs);
+       }
 
        /* enable leveling */
        writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 
-       if (omap_revision() == DRA752_ES1_0)
-               ddr3_sw_leveling(base, regs);
-       else
-               ddr3_leveling(base, regs);
+       ddr3_leveling(base, regs);
 }
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1079,10 +1110,7 @@ static void do_sdram_init(u32 base)
        if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
                set_lpmode_selfrefresh(base);
                emif_reset_phy(base);
-               if (omap_revision() == DRA752_ES1_0)
-                       ddr3_sw_leveling(base, regs);
-               else
-                       ddr3_leveling(base, regs);
+               ddr3_leveling(base, regs);
        }
 
        /* Write to the shadow registers */
@@ -1244,6 +1272,42 @@ void dmm_init(u32 base)
 
 }
 
+static void do_bug0039_workaround(u32 base)
+{
+       u32 val, i, clkctrl;
+       struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
+       const struct read_write_regs *bug_00339_regs;
+       u32 iterations;
+       u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
+       u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
+
+       if (is_dra7xx())
+               phy_status_base++;
+
+       bug_00339_regs = get_bug_regs(&iterations);
+
+       /* Put EMIF in to idle */
+       clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
+       __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
+
+       /* Copy the phy status registers in to phy ctrl shadow registers */
+       for (i = 0; i < iterations; i++) {
+               val = __raw_readl(phy_status_base +
+                                 bug_00339_regs[i].read_reg - 1);
+
+               __raw_writel(val, phy_ctrl_base +
+                            ((bug_00339_regs[i].write_reg - 1) << 1));
+
+               __raw_writel(val, phy_ctrl_base +
+                            (bug_00339_regs[i].write_reg << 1) - 1);
+       }
+
+       /* Disable leveling */
+       writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
+
+       __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
+}
+
 /*
  * SDRAM initialization:
  * SDRAM initialization has two parts:
@@ -1319,5 +1383,11 @@ void sdram_init(void)
                        debug("get_ram_size() successful");
        }
 
+       if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
+           (!in_sdram && !warm_reset())) {
+               do_bug0039_workaround(EMIF1_BASE);
+               do_bug0039_workaround(EMIF2_BASE);
+       }
+
        debug("<<sdram_init()\n");
 }
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
new file mode 100644 (file)
index 0000000..b71d769
--- /dev/null
@@ -0,0 +1,231 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "pipe3-phy.h"
+
+/* PLLCTRL Registers */
+#define PLL_STATUS              0x00000004
+#define PLL_GO                  0x00000008
+#define PLL_CONFIGURATION1      0x0000000C
+#define PLL_CONFIGURATION2      0x00000010
+#define PLL_CONFIGURATION3      0x00000014
+#define PLL_CONFIGURATION4      0x00000020
+
+#define PLL_REGM_MASK           0x001FFE00
+#define PLL_REGM_SHIFT          9
+#define PLL_REGM_F_MASK         0x0003FFFF
+#define PLL_REGM_F_SHIFT        0
+#define PLL_REGN_MASK           0x000001FE
+#define PLL_REGN_SHIFT          1
+#define PLL_SELFREQDCO_MASK     0x0000000E
+#define PLL_SELFREQDCO_SHIFT    1
+#define PLL_SD_MASK             0x0003FC00
+#define PLL_SD_SHIFT            10
+#define SET_PLL_GO              0x1
+#define PLL_TICOPWDN            BIT(16)
+#define PLL_LDOPWDN             BIT(15)
+#define PLL_LOCK                0x2
+#define PLL_IDLE                0x1
+
+/* PHY POWER CONTROL Register */
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK         0x003FC000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT        0xE
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK        0xFFC00000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT       0x16
+
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON       0x3
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF      0x0
+
+
+#define PLL_IDLE_TIME   100     /* in milliseconds */
+#define PLL_LOCK_TIME   100     /* in milliseconds */
+
+static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+       return __raw_readl(addr + offset);
+}
+
+static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
+               u32 data)
+{
+       __raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
+                                                                       *pipe3)
+{
+       u32 rate;
+       struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
+
+       rate = get_sys_clk_freq();
+
+       for (; dpll_map->rate; dpll_map++) {
+               if (rate == dpll_map->rate)
+                       return &dpll_map->params;
+       }
+
+       printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
+              __func__, rate);
+       return NULL;
+}
+
+
+static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
+{
+       u32 val;
+       int timeout = PLL_LOCK_TIME;
+
+       do {
+               mdelay(1);
+               val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+               if (val & PLL_LOCK)
+                       break;
+       } while (--timeout);
+
+       if (!(val & PLL_LOCK)) {
+               printf("%s: DPLL failed to lock\n", __func__);
+               return -EBUSY;
+       }
+
+       return 0;
+}
+
+static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
+{
+       u32                     val;
+       struct pipe3_dpll_params *dpll_params;
+
+       dpll_params = omap_pipe3_get_dpll_params(phy);
+       if (!dpll_params) {
+               printf("%s: Invalid DPLL parameters\n", __func__);
+               return -EINVAL;
+       }
+
+       val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+       val &= ~PLL_REGN_MASK;
+       val |= dpll_params->n << PLL_REGN_SHIFT;
+       omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+       val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+       val &= ~PLL_SELFREQDCO_MASK;
+       val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
+       omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+       val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+       val &= ~PLL_REGM_MASK;
+       val |= dpll_params->m << PLL_REGM_SHIFT;
+       omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+       val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
+       val &= ~PLL_REGM_F_MASK;
+       val |= dpll_params->mf << PLL_REGM_F_SHIFT;
+       omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
+
+       val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
+       val &= ~PLL_SD_MASK;
+       val |= dpll_params->sd << PLL_SD_SHIFT;
+       omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
+
+       omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
+
+       return omap_pipe3_wait_lock(phy);
+}
+
+static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
+{
+       u32 val, rate;
+
+       val = readl(phy->power_reg);
+
+       rate = get_sys_clk_freq();
+       rate = rate/1000000;
+
+       if (on) {
+               val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+                               OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+               val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
+                       OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+               val |= rate <<
+                       OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+       } else {
+               val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+               val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
+                       OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+       }
+
+       writel(val, phy->power_reg);
+}
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy)
+{
+       int ret;
+       u32 val;
+
+       /* Program the DPLL only if not locked */
+       val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+       if (!(val & PLL_LOCK)) {
+               ret = omap_pipe3_dpll_program(phy);
+               if (ret)
+                       return ret;
+       } else {
+               /* else just bring it out of IDLE mode */
+               val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+               if (val & PLL_IDLE) {
+                       val &= ~PLL_IDLE;
+                       omap_pipe3_writel(phy->pll_ctrl_base,
+                                         PLL_CONFIGURATION2, val);
+                       ret = omap_pipe3_wait_lock(phy);
+                       if (ret)
+                               return ret;
+               }
+       }
+
+       /* Power up the PHY */
+       omap_control_phy_power(phy, 1);
+
+       return 0;
+}
+
+int phy_pipe3_power_off(struct omap_pipe3 *phy)
+{
+       u32 val;
+       int timeout = PLL_IDLE_TIME;
+
+       /* Power down the PHY */
+       omap_control_phy_power(phy, 0);
+
+       /* Put DPLL in IDLE mode */
+       val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+       val |= PLL_IDLE;
+       omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+       /* wait for LDO and Oscillator to power down */
+       do {
+               mdelay(1);
+               val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+               if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
+                       break;
+       } while (--timeout);
+
+       if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+               printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
+                      __func__, val);
+               return -EBUSY;
+       }
+
+       return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
new file mode 100644 (file)
index 0000000..441f49a
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __OMAP_PIPE3_PHY_H
+#define __OMAP_PIPE3_PHY_H
+
+struct pipe3_dpll_params {
+       u16     m;
+       u8      n;
+       u8      freq:3;
+       u8      sd;
+       u32     mf;
+};
+
+struct pipe3_dpll_map {
+       unsigned long rate;
+       struct pipe3_dpll_params params;
+};
+
+struct omap_pipe3 {
+       void __iomem            *pll_ctrl_base;
+       void __iomem            *power_reg;
+       struct pipe3_dpll_map   *dpll_map;
+};
+
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy);
+int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
+
+#endif /* __OMAP_PIPE3_PHY_H */
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
new file mode 100644 (file)
index 0000000..f5468c4
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * TI SATA platform driver
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sata.h>
+#include <asm/io.h>
+#include "pipe3-phy.h"
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+       {12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
+       {16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
+       {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
+       {20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
+       {26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
+       {38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
+       { },                                    /* Terminator */
+};
+
+struct omap_pipe3 sata_phy = {
+       .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
+       /* .power_reg is updated at runtime */
+       .dpll_map = dpll_map_sata,
+};
+
+int omap_sata_init(void)
+{
+       int ret;
+       u32 val;
+
+       u32 const clk_domains_sata[] = {
+               0
+       };
+
+       u32 const clk_modules_hw_auto_sata[] = {
+               (*prcm)->cm_l3init_ocp2scp3_clkctrl,
+               0
+       };
+
+       u32 const clk_modules_explicit_en_sata[] = {
+               (*prcm)->cm_l3init_sata_clkctrl,
+               0
+       };
+
+       do_enable_clocks(clk_domains_sata,
+                        clk_modules_hw_auto_sata,
+                        clk_modules_explicit_en_sata,
+                        0);
+
+       /* Enable optional functional clock for SATA */
+       setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+                    SATA_CLKCTRL_OPTFCLKEN_MASK);
+
+       sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
+
+       /* Power up the PHY */
+       phy_pipe3_power_on(&sata_phy);
+
+       /* Enable SATA module, No Idle, No Standby */
+       val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
+       writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
+
+       ret = ahci_init(DWC_AHSATA_BASE);
+       scsi_scan(1);
+
+       return ret;
+}
index 5e93b34..02aa129 100644 (file)
@@ -32,6 +32,11 @@ SECTIONS
        . = ALIGN(4);
        .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
 
+       . = ALIGN(4);
+       .u_boot_list : {
+               KEEP(*(SORT(.u_boot_list*_i2c_*)));
+       } >.sram
+
        . = ALIGN(4);
        __image_copy_end = .;
        _end = .;
index 7d1f8d9..2922816 100644 (file)
@@ -98,7 +98,7 @@ void spl_board_init(void)
        gpmc_init();
 #endif
 #ifdef CONFIG_SPL_I2C_SUPPORT
-       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+       i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 #endif
 }
 #endif /* CONFIG_SPL_BUILD */
index 9f989ff..1bc27bd 100644 (file)
@@ -708,7 +708,7 @@ void per_clocks_enable(void)
        sr32(&prcm_base->iclken_per, 17, 1, 1);
 #endif
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
        /* Turn on all 3 I2C clocks */
        sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
        sr32(&prcm_base->iclken1_core, 15, 3, 0x7);     /* I2C1,2,3 = on */
@@ -730,8 +730,6 @@ void per_clocks_enable(void)
                sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
                sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
        }
-       sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
-       sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
 
        sdelay(1000);
 }
index 6a225c8..1b2f439 100644 (file)
@@ -288,17 +288,21 @@ struct vcores_data omap4460_volts = {
        .mm.pmic = &twl6030,
 };
 
+/*
+ * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
+ * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
+ */
 struct vcores_data omap4470_volts = {
-       .mpu.value = 1200,
+       .mpu.value = 1202,
        .mpu.addr = SMPS_REG_ADDR_SMPS1,
        .mpu.pmic = &twl6030,
 
        .core.value = 1126,
-       .core.addr = SMPS_REG_ADDR_SMPS1,
+       .core.addr = SMPS_REG_ADDR_SMPS2,
        .core.pmic = &twl6030,
 
-       .mm.value = 1137,
-       .mm.addr = SMPS_REG_ADDR_SMPS1,
+       .mm.value = 1139,
+       .mm.addr = SMPS_REG_ADDR_SMPS5,
        .mm.pmic = &twl6030,
 };
 
index e4c8316..6903696 100644 (file)
@@ -32,7 +32,7 @@
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 
-static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
        .sdram_config_init              = 0x80000eb9,
        .sdram_config                   = 0x80001ab9,
        .ref_ctrl                       = 0x0000030c,
@@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
        .emif_ddr_phy_ctlr_1            = 0x049ff808
 };
 
-static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
        .sdram_config_init              = 0x80000eb1,
        .sdram_config                   = 0x80001ab1,
        .ref_ctrl                       = 0x000005cd,
@@ -321,3 +321,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 {
        *regs = &mr_regs;
 }
+
+__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+       return 0;
+}
index a1b249e..5268a1f 100644 (file)
@@ -39,17 +39,6 @@ static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
        {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
 };
 
-/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
-static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
-       {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
-       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 13 MHz   */
-       {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 16.8 MHz */
-       {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},      /* 19.2 MHz */
-       {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 26 MHz   */
-       {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-       {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}       /* 38.4 MHz */
-};
-
 /* OPP NOM FREQUENCY for ES1.0 */
 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
        {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},        /* 12 MHz   */
@@ -83,6 +72,7 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
        {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}        /* 38.4 MHz */
 };
 
+/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
        {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 12 MHz   */
        {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},         /* 20 MHz   */
@@ -169,13 +159,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
 };
 
 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
-       {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 12 MHz   */
+       {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 12 MHz   */
        {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 20 MHz   */
-       {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},            /* 16.8 MHz */
-       {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 19.2 MHz */
-       {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},           /* 26 MHz   */
+       {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},             /* 16.8 MHz */
+       {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 19.2 MHz */
+       {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},            /* 26 MHz   */
        {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},       /* 27 MHz   */
-       {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},             /* 38.4 MHz */
+       {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},              /* 38.4 MHz */
 };
 
 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
@@ -272,7 +262,7 @@ struct dplls omap5_dplls_es1 = {
 };
 
 struct dplls omap5_dplls_es2 = {
-       .mpu = mpu_dpll_params_1100mhz,
+       .mpu = mpu_dpll_params_1ghz,
        .core = core_dpll_params_2128mhz_ddr532_es2,
        .per = per_dpll_params_768mhz_es2,
        .iva = iva_dpll_params_2330mhz,
@@ -600,6 +590,7 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = {
        .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
        .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
        .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+       .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 };
 
 const struct ctrl_ioregs ioregs_omap5432_es2 = {
@@ -610,16 +601,18 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
        .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
        .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
        .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+       .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 };
 
 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
        .ctrl_ddrch = 0x40404040,
        .ctrl_lpddr2ch = 0x40404040,
        .ctrl_ddr3ch = 0x80808080,
-       .ctrl_ddrio_0 = 0xbae8c631,
-       .ctrl_ddrio_1 = 0xb46318d8,
+       .ctrl_ddrio_0 = 0xA2084210,
+       .ctrl_ddrio_1 = 0x84210840,
        .ctrl_ddrio_2 = 0x84210000,
-       .ctrl_emif_sdram_config_ext = 0xb2c00000,
+       .ctrl_emif_sdram_config_ext = 0x0001C1A7,
+       .ctrl_emif_sdram_config_ext_final = 0x000101A7,
        .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 
index 1065891..5386ae0 100644 (file)
@@ -168,12 +168,6 @@ void do_io_settings(void)
                io_settings_lpddr2();
        else
                io_settings_ddr3();
-
-       /* Efuse settings */
-       writel(EFUSE_1, (*ctrl)->control_efuse_1);
-       writel(EFUSE_2, (*ctrl)->control_efuse_2);
-       writel(EFUSE_3, (*ctrl)->control_efuse_3);
-       writel(EFUSE_4, (*ctrl)->control_efuse_4);
 }
 
 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
@@ -297,13 +291,17 @@ void srcomp_enable(void)
 
 void config_data_eye_leveling_samples(u32 emif_base)
 {
+       const struct ctrl_ioregs *ioregs;
+
+       get_ioregs(&ioregs);
+
        /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
        if (emif_base == EMIF1_BASE)
-               writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-                       (*ctrl)->control_emif1_sdram_config_ext);
+               writel(ioregs->ctrl_emif_sdram_config_ext_final,
+                      (*ctrl)->control_emif1_sdram_config_ext);
        else if (emif_base == EMIF2_BASE)
-               writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-                       (*ctrl)->control_emif2_sdram_config_ext);
+               writel(ioregs->ctrl_emif_sdram_config_ext_final,
+                      (*ctrl)->control_emif2_sdram_config_ext);
 }
 
 void init_omap_revision(void)
index 304ac1c..77c428b 100644 (file)
@@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
        .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
        .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
        .cm_l3init_p1500_clkctrl = 0x4a009378,
+       .cm_l3init_sata_clkctrl = 0x4a009388,
        .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
        .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+       .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
 
        /* cm2.l4per */
        .cm_l4per_clkstctrl = 0x4a009400,
@@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_status                         = 0x4A002134,
        .control_std_fuse_opp_vdd_mpu_2         = 0x4A0021B4,
        .control_phy_power_usb                  = 0x4A002370,
+       .control_phy_power_sata                 = 0x4A002374,
        .control_padconf_core_base              = 0x4A002800,
        .control_paconf_global                  = 0x4A002DA0,
        .control_paconf_mode                    = 0x4A002DA4,
@@ -373,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_status                         = 0x4A002134,
+       .control_phy_power_sata                 = 0x4A002374,
        .control_core_mac_id_0_lo               = 0x4A002514,
        .control_core_mac_id_0_hi               = 0x4A002518,
        .control_core_mac_id_1_lo               = 0x4A00251C,
@@ -698,6 +702,7 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
        .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
        .cm_l3init_p1500_clkctrl = 0x4a009678,
+       .cm_l3init_sata_clkctrl = 0x4a009688,
        .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
        .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
        .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
@@ -891,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_l3init_hsusbhost_clkctrl            = 0x4a009340,
        .cm_l3init_hsusbotg_clkctrl             = 0x4a009348,
        .cm_l3init_hsusbtll_clkctrl             = 0x4a009350,
+       .cm_l3init_sata_clkctrl                 = 0x4a009388,
        .cm_gmac_clkstctrl                      = 0x4a0093c0,
        .cm_gmac_gmac_clkctrl                   = 0x4a0093d0,
        .cm_l3init_ocp2scp1_clkctrl             = 0x4a0093e0,
+       .cm_l3init_ocp2scp3_clkctrl             = 0x4a0093e8,
 
        /* cm2.l4per */
        .cm_l4per_clkstctrl                     = 0x4a009700,
index e65c116..2e18706 100644 (file)
@@ -148,13 +148,13 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .read_idle_ctrl                 = 0x00050000,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0E20400A,
-       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
-       .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x009E009E,
-       .emif_ddr_ext_phy_ctrl_3        = 0x009E009E,
-       .emif_ddr_ext_phy_ctrl_4        = 0x009E009E,
-       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
        .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -172,13 +172,13 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .read_idle_ctrl                 = 0x00050000,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0020400A,
-       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
-       .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x009D009D,
-       .emif_ddr_ext_phy_ctrl_3        = 0x009D009D,
-       .emif_ddr_ext_phy_ctrl_4        = 0x009D009D,
-       .emif_ddr_ext_phy_ctrl_5        = 0x009D009D,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
        .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -306,7 +306,7 @@ void emif_get_device_details(u32 emif_nr,
 
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ext_phy_ctrl_const_base[] = {
        0x01004010,
        0x00001004,
        0x04010040,
@@ -329,7 +329,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
        0x0
 };
 
-const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
        0x01004010,
        0x00001004,
        0x04010040,
@@ -352,7 +352,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
        0x0
 };
 
-const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
        0x50D4350D,
        0x00000D43,
        0x04010040,
@@ -376,51 +376,61 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
 };
 
 const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
-       0x009E009E,
-       0x002E002E,
-       0x002E002E,
-       0x002E002E,
-       0x002E002E,
-       0x002E002E,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x004D004D,
-       0x0,
-       0x600020,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+       0x00B000B0,
+       0x00400040,
+       0x00400040,
+       0x00400040,
+       0x00400040,
+       0x00400040,
+       0x00800080,
+       0x00800080,
+       0x00800080,
+       0x00800080,
+       0x00800080,
+       0x00600060,
+       0x00600060,
+       0x00600060,
+       0x00600060,
+       0x00600060,
+       0x00800080,
+       0x00800080,
        0x40010080,
-       0x8102040
+       0x08102040,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0
 };
 
 const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
-       0x009D009D,
-       0x002D002D,
-       0x002D002D,
-       0x002D002D,
-       0x002D002D,
-       0x002D002D,
-       0x00570057,
-       0x00570057,
-       0x00570057,
-       0x00570057,
-       0x00570057,
-       0x00570057,
-       0x00570057,
-       0x00570057,
-       0x00570057,
-       0x00570057,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+       0x00BB00BB,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x00600060,
+       0x00600060,
+       0x00600060,
+       0x00600060,
+       0x00600060,
        0x0,
-       0x600020,
+       0x00600020,
        0x40010080,
-       0x8102040
+       0x08102040,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0
 };
 
 const struct lpddr2_mr_regs mr_regs = {
@@ -431,27 +441,38 @@ const struct lpddr2_mr_regs mr_regs = {
        .mr16   = MR16_REF_FULL_ARRAY
 };
 
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+                                            const u32 **regs,
+                                            u32 *size)
 {
        switch (omap_revision()) {
        case OMAP5430_ES1_0:
        case OMAP5430_ES2_0:
                *regs = ext_phy_ctrl_const_base;
+               *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
                break;
        case OMAP5432_ES1_0:
                *regs = ddr3_ext_phy_ctrl_const_base_es1;
+               *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
                break;
        case OMAP5432_ES2_0:
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
+               *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
                break;
        case DRA752_ES1_0:
-               if (emif_nr == 1)
+               if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
-               else
+                       *size =
+                       ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
+               } else {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+                       *size =
+                       ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
+               }
                break;
        default:
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
+               *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 
        }
 }
@@ -468,6 +489,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
        u32 emif_nr;
        const u32 *ext_phy_ctrl_const_regs;
        u32 i = 0;
+       u32 size;
 
        emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
@@ -487,8 +509,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
         * external phy 6-24 registers do not change with
         * ddr frequency
         */
-       emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
-       for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+       emif_get_ext_phy_ctrl_const_regs(emif_nr,
+                                        &ext_phy_ctrl_const_regs, &size);
+
+       for (i = 0; i < size; i++) {
                writel(ext_phy_ctrl_const_regs[i],
                       emif_ext_phy_ctrl_base++);
                /* Update shadow registers */
@@ -545,6 +569,74 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = {
        .min_tck        = &min_tck,
 };
 
+/*
+ * List of status registers to be controlled back to control registers
+ * after initial leveling
+ * readreg, writereg
+ */
+const struct read_write_regs omap5_bug_00339_regs[] = {
+       { 8,  5 },
+       { 9,  6 },
+       { 10, 7 },
+       { 14, 8 },
+       { 15, 9 },
+       { 16, 10 },
+       { 11, 2 },
+       { 12, 3 },
+       { 13, 4 },
+       { 17, 11 },
+       { 18, 12 },
+       { 19, 13 },
+};
+
+const struct read_write_regs dra_bug_00339_regs[] = {
+       { 7,  7 },
+       { 8,  8 },
+       { 9,  9 },
+       { 10, 10 },
+       { 11, 11 },
+       { 12, 2 },
+       { 13, 3 },
+       { 14, 4 },
+       { 15, 5 },
+       { 16, 6 },
+       { 17, 12 },
+       { 18, 13 },
+       { 19, 14 },
+       { 20, 15 },
+       { 21, 16 },
+       { 22, 17 },
+       { 23, 18 },
+       { 24, 19 },
+       { 25, 20 },
+       { 26, 21}
+};
+
+const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+       const struct read_write_regs *bug_00339_regs_ptr = NULL;
+
+       switch (omap_revision()) {
+       case OMAP5430_ES1_0:
+       case OMAP5430_ES2_0:
+       case OMAP5432_ES1_0:
+       case OMAP5432_ES2_0:
+               bug_00339_regs_ptr = omap5_bug_00339_regs;
+               *iterations = sizeof(omap5_bug_00339_regs)/
+                            sizeof(omap5_bug_00339_regs[0]);
+               break;
+       case DRA752_ES1_0:
+               bug_00339_regs_ptr = dra_bug_00339_regs;
+               *iterations = sizeof(dra_bug_00339_regs)/
+                            sizeof(dra_bug_00339_regs[0]);
+               break;
+       default:
+               printf("\n Error: UnKnown SOC");
+       }
+
+       return bug_00339_regs_ptr;
+}
+
 void emif_get_device_timings_sdp(u32 emif_nr,
                const struct lpddr2_device_timings **cs0_device_timings,
                const struct lpddr2_device_timings **cs1_device_timings)
index 8f4cf3a..2221999 100644 (file)
@@ -5,20 +5,13 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y = lowlevel_init.o
-obj-y += cpu_info.o
+obj-y = cpu_info.o
 obj-y += emac.o
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_GLOBAL_TIMER) += timer.o
-obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
-obj-$(CONFIG_R8A7740) += pfc-r8a7740.o
-obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
-obj-$(CONFIG_SH73A0) += pfc-sh73a0.o
-obj-$(CONFIG_TMU_TIMER) += sh_timer.o
-
-SRCS += $(obj)sh_timer.c
-# from arch/sh/lib/ directory
-$(obj)sh_timer.c:
-       @rm -f $(obj)sh_timer.c
-       ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c
+obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
+obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk
deleted file mode 100644 (file)
index 3a36ab6..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
new file mode 100644 (file)
index 0000000..7232e23
--- /dev/null
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
+ *     This file is r8a7790 processor support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+       return (readl(PRR) & 0x00007F00) >> 8;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+       return (readl(PRR) & 0x000000F0) >> 4;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
new file mode 100644 (file)
index 0000000..2de58ed
--- /dev/null
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+       u32 product;
+
+       product = readl(PRR);
+
+       return (u32)((product & 0x00007F00) >> 8);
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+       u32 product;
+
+       product = readl(PRR);
+
+       return (u32)((product & 0x000000F0) >> 4);
+}
index 07a33fb..83d5282 100644 (file)
@@ -58,6 +58,16 @@ int print_cpuinfo(void)
                       rmobile_get_cpu_rev_fraction());
                break;
 
+       case 0x45:
+               printf("CPU: Renesas Electronics R8A7790 rev %d\n",
+                      rmobile_get_cpu_rev_integer());
+               break;
+
+       case 0x47:
+               printf("CPU: Renesas Electronics R8A7791 rev %d\n",
+                       rmobile_get_cpu_rev_integer());
+               break;
+
        default:
                printf("CPU: Renesas Electronics CPU rev %d.%d\n",
                       rmobile_get_cpu_rev_integer(),
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
new file mode 100644 (file)
index 0000000..e07cc80
--- /dev/null
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+ *     This file is lager low level initialize.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+       mrc     p15, 0, r4, c0, c0, 5 /* mpidr */
+       orr     r4, r4, r4, lsr #6
+       and     r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
+
+       b do_lowlevel_init
+
+       .pool
+
+/*
+ * CPU ID #1-#3 come here
+ */
+       .align  4
+do_cpu_waiting:
+       ldr     r1, =0xe6180000 /* sysc */
+1:     ldr     r0, [r1, #0x20] /* sbar */
+       tst     r0, r0
+       beq     1b
+       bx      r0
+
+/*
+ * Only CPU ID #0 comes here
+ */
+       .align  4
+do_lowlevel_init:
+       /* surpress wfe if ca15 */
+       tst     r4, #4
+       mrceq p15, 0, r0, c1, c0, 1     /* actlr */
+       orreq r0, r0, #(1<<7)
+       mcreq p15, 0, r0, c1, c0, 1
+       /* and set l2 latency */
+       mrceq p15, 1, r0, c9, c0, 2     /* l2ctlr */
+       orreq r0, r0, #0x00000800
+       orreq r0, r0, #0x00000003
+       mcreq p15, 1, r0, c9, c0, 2
+
+       ldr     r3, =(CONFIG_SYS_INIT_SP_ADDR)
+       sub     sp, r3, #4
+       str     lr, [sp]
+
+       /* initialize system */
+       bl s_init
+
+       ldr     lr, [sp]
+       mov     pc, lr
+       nop
+ENDPROC(lowlevel_init)
+       .ltorg
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
new file mode 100644 (file)
index 0000000..1259062
--- /dev/null
@@ -0,0 +1,829 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
+ *     This file is r8a7790 processor support - PFC hardware block.
+ *
+ * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Magnus Damm
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+       PINMUX_RESERVED = 0,
+
+       PINMUX_DATA_BEGIN,
+       GP_ALL(DATA),
+       PINMUX_DATA_END,
+
+       PINMUX_INPUT_BEGIN,
+       GP_ALL(IN),
+       PINMUX_INPUT_END,
+
+       PINMUX_OUTPUT_BEGIN,
+       GP_ALL(OUT),
+       PINMUX_OUTPUT_END,
+
+       PINMUX_FUNCTION_BEGIN,
+       GP_ALL(FN),
+
+       /* GPSR0 */
+       FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+       FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+       FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+       FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+       FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+       FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+       FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+       FN_IP3_14_12, FN_IP3_17_15,
+
+       /* GPSR1 */
+       FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+       FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+       FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+       FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+       FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+       FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+       FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+       /* GPSR2 */
+       FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+       FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+       FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+       FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+       FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+       FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+       FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+       /* GPSR3 */
+       FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+       FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+       FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+       FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+       FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+       FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+       FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+       /* GPSR4 */
+       FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+       FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+       FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+       FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+       FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+       FN_IP13_18_16, FN_IP13_22_19, FN