Merge branch 'for-1.3.0'

diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index fd99a938c0f87830bb96004a0622e3e6868258e5..45dcf4dab03d425e9d867a6a1a7badef747d7237 100644 (file)
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -207,13 +207,16 @@ void read_from_px_regs_altbank(int set)
        out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
 }
 
+#ifndef CFG_PIXIS_VBOOT_MASK
+#define CFG_PIXIS_VBOOT_MASK   0x40
+#endif
 
 void set_altbank(void)
 {
        u8 tmp;
 
        tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
-       tmp ^= 0x40;
+       tmp ^= CFG_PIXIS_VBOOT_MASK;
 
        out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
 }

diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index bbc0cd600494fb4fe9ca5e9d06c9edd75b873fea..11354d38dabe259027d7e3ad7c21b1023f581c4e 100644 (file)
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -131,7 +131,7 @@ checkcpu(void)
 static inline void
 soft_restart(unsigned long addr)
 {
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
 
        /*
         * SRR0 has system reset vector, SRR1 has default MSR value
@@ -159,7 +159,7 @@ soft_restart(unsigned long addr)
 void
 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
 
 #ifdef CFG_RESET_ADDRESS
        ulong addr = CFG_RESET_ADDRESS;

diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 059097f5142ae595d51b6cd105b1180c43195c85..d57bcdf2c875ff548c5d13422beda21d19f01c4d 100644 (file)
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -1270,10 +1270,12 @@ spd_sdram(void)
                debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
                debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
        }
+
+       debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
+
 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
 
-       debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
-             memsize_ddr1, memsize_ddr2);
+       debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
 
        /*
         * If neither DDR controller is enabled return 0.

diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index f580ccadee5ea515ff5b911c348da1529834eca6..13e2a2c079fca14d44a5347d890e68abd033cb3e 100644 (file)
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -198,6 +198,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1          0x18    /* VELA VSpeed 1 */
 #define PIXIS_VCLKH            0x19    /* VELA VCLKH register */
 #define PIXIS_VCLKL            0x1A    /* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK   0x40    /* Reset altbank mask*/
 
 
 /* define to use L1 as initial stack */

diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index aa6dbc47adfc47cbae13a53829566ffa740e94a5..6f8724026333015a119001749448497e729e1a63 100644 (file)
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -201,6 +201,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define PIXIS_VSPEED1          0x18    /* VELA VSpeed 1 */
 #define PIXIS_VCLKH            0x19    /* VELA VCLKH register */
 #define PIXIS_VCLKL            0x1A    /* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK   0x40    /* Reset altbank mask*/
 
 #define CFG_MAX_FLASH_BANKS    2               /* number of banks */
 #define CFG_MAX_FLASH_SECT     128             /* sectors per device */