odroid: clock: set aclk_cores to 200MHz

This change fixes suspend/resume issue in the kernel caused
by the wrong 'aclk_cores' clock value expected by the kernel.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index ac19527a90ecdc56a0e87f38c4d1922b2ece803f..5edb250f06bbb98b606d02c22e5c4364fd6cda42 100644 (file)
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -158,10 +158,10 @@ static void board_clock_init(void)
         * For MOUThpm = 1000 MHz (MOUTapll)
         * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
         * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
         * For MOUThpm = 1000 MHz (MOUTapll)
         * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
         * sclkhpm = doutcopy / (ratio + 1) = 200 (4)

-        * cores_out = armclk / (ratio + 1) = 1000 (0)
+        * cores_out = armclk / (ratio + 1) = 200 (4)

         */
        clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
         */
        clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);

-       set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0);
+       set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);

 
        clrsetbits_le32(&clk->div_cpu1, clr, set);
 
 
        clrsetbits_le32(&clk->div_cpu1, clr, set);