Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 15 Mar 2013 19:50:43 +0000 (20:50 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 15 Mar 2013 19:50:43 +0000 (20:50 +0100)
73 files changed:
MAINTAINERS
arch/arm/cpu/arm720t/tegra114/cpu.c
arch/arm/cpu/armv7/tegra20/Makefile
arch/arm/cpu/armv7/tegra20/usb.c [deleted file]
arch/arm/cpu/tegra114-common/pinmux.c
arch/arm/cpu/tegra30-common/pinmux.c
arch/arm/dts/tegra114.dtsi
arch/arm/dts/tegra20.dtsi
arch/arm/dts/tegra30.dtsi
arch/arm/include/asm/arch-tegra/mmc.h
arch/arm/include/asm/arch-tegra/tegra_i2c.h
arch/arm/include/asm/arch-tegra/tegra_mmc.h
arch/arm/include/asm/arch-tegra/usb.h [moved from arch/arm/include/asm/arch-tegra20/usb.h with 89% similarity]
arch/arm/include/asm/arch-tegra114/gp_padctrl.h
arch/arm/include/asm/arch-tegra114/pinmux.h
arch/arm/include/asm/arch-tegra20/tegra.h
arch/arm/include/asm/arch-tegra30/gp_padctrl.h
arch/arm/include/asm/arch-tegra30/pinmux.h
arch/arm/include/asm/arch-tegra30/tegra.h
board/avionic-design/common/tamonten.c
board/avionic-design/dts/tegra20-medcom-wide.dts
board/avionic-design/dts/tegra20-plutux.dts
board/avionic-design/dts/tegra20-tamonten.dtsi [new file with mode: 0644]
board/avionic-design/dts/tegra20-tec.dts
board/compal/dts/tegra20-paz00.dts
board/compal/paz00/paz00.c
board/compulab/dts/tegra20-trimslice.dts
board/compulab/trimslice/trimslice.c
board/nvidia/cardhu/cardhu.c
board/nvidia/cardhu/cardhu.c.mmc [deleted file]
board/nvidia/cardhu/pinmux-config-cardhu.h
board/nvidia/common/board.c
board/nvidia/dalmore/dalmore.c
board/nvidia/dalmore/pinmux-config-dalmore.h
board/nvidia/dts/tegra114-dalmore.dts
board/nvidia/dts/tegra20-harmony.dts
board/nvidia/dts/tegra20-seaboard.dts
board/nvidia/dts/tegra20-ventana.dts
board/nvidia/dts/tegra20-whistler.dts
board/nvidia/dts/tegra30-cardhu.dts
board/nvidia/harmony/harmony.c
board/nvidia/seaboard/seaboard.c
board/nvidia/whistler/whistler.c
board/toradex/colibri_t20_iris/colibri_t20_iris.c
board/toradex/dts/tegra20-colibri_t20_iris.dts
disk/part.c
disk/part_amiga.c
disk/part_dos.c
disk/part_efi.c
disk/part_iso.c
disk/part_mac.c
drivers/i2c/tegra_i2c.c
drivers/mmc/tegra_mmc.c
drivers/usb/host/ehci-tegra.c
dts/Makefile
include/config_fallbacks.h
include/configs/cardhu.h
include/configs/colibri_t20_iris.h
include/configs/dalmore.h
include/configs/harmony.h
include/configs/medcom-wide.h
include/configs/paz00.h
include/configs/plutux.h
include/configs/seaboard.h
include/configs/tec.h
include/configs/tegra-common.h
include/configs/tegra114-common.h
include/configs/tegra20-common.h
include/configs/trimslice.h
include/configs/ventana.h
include/configs/whistler.h
include/fdtdec.h
lib/fdtdec.c

index d3f1bea..0951108 100644 (file)
@@ -976,6 +976,8 @@ Tom Warren <twarren@nvidia.com>
 
        harmony         Tegra20 (ARM7 & A9 Dual Core)
        seaboard        Tegra20 (ARM7 & A9 Dual Core)
+       cardhu          Tegra30 (ARM7 & A9 Quad Core)
+       dalmore         Tegra114 (ARM7 & A15 Quad Core)
 
 Tom Warren <twarren@nvidia.com>
 Stephen Warren <swarren@nvidia.com>
index 5962e15..6a94179 100644 (file)
@@ -201,6 +201,7 @@ void t114_init_clocks(void)
        reset_set_enable(PERIPH_ID_MSELECT, 0);
        reset_set_enable(PERIPH_ID_EMC1, 0);
        reset_set_enable(PERIPH_ID_MC1, 0);
+       reset_set_enable(PERIPH_ID_DVFS, 0);
 
        debug("t114_init_clocks exit\n");
 }
@@ -269,6 +270,8 @@ void powerup_cpus(void)
 
 void start_cpu(u32 reset_vector)
 {
+       u32 imme, inst;
+
        debug("start_cpu entry, reset_vector = %x\n", reset_vector);
 
        t114_init_clocks();
@@ -285,12 +288,38 @@ void start_cpu(u32 reset_vector)
        /* Take CPU(s) out of reset */
        remove_cpu_resets();
 
+       /* Set the entry point for CPU execution from reset */
+
        /*
-        * Set the entry point for CPU execution from reset,
-        *  if it's a non-zero value.
+        * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
+        * See nvbug 1193357 for details.
         */
-       if (reset_vector)
-               writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+
+       /* mov r0, #lsb(reset_vector) */
+       imme = reset_vector & 0xffff;
+       inst = imme & 0xfff;
+       inst |= ((imme >> 12) << 16);
+       inst |= 0xe3000000;
+       writel(inst, 0x4003fff0);
+
+       /* movt r0, #msb(reset_vector) */
+       imme = (reset_vector >> 16) & 0xffff;
+       inst = imme & 0xfff;
+       inst |= ((imme >> 12) << 16);
+       inst |= 0xe3400000;
+       writel(inst, 0x4003fff4);
+
+       /* bx r0 */
+       writel(0xe12fff10, 0x4003fff8);
+
+       /* b -12 */
+       imme = (u32)-20;
+       inst = (imme >> 2) & 0xffffff;
+       inst |= 0xea000000;
+       writel(inst, 0x4003fffc);
+
+       /* Write to orignal location for compatibility */
+       writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
 
        /* If the CPU(s) don't already have power, power 'em up */
        powerup_cpus();
index 54ed8c4..c8a8504 100644 (file)
@@ -27,7 +27,6 @@ include $(TOPDIR)/config.mk
 
 LIB    =  $(obj)lib$(SOC).o
 
-COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 COBJS-$(CONFIG_PWM_TEGRA) += pwm.o
 COBJS-$(CONFIG_VIDEO_TEGRA) += display.o
 
diff --git a/arch/arm/cpu/armv7/tegra20/usb.c b/arch/arm/cpu/armv7/tegra20/usb.c
deleted file mode 100644 (file)
index 1bccf2b..0000000
+++ /dev/null
@@ -1,567 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm-generic/gpio.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/usb.h>
-#include <usb/ulpi.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/sys_proto.h>
-#include <asm/arch-tegra/uart.h>
-#include <libfdt.h>
-#include <fdtdec.h>
-
-#ifdef CONFIG_USB_ULPI
-       #ifndef CONFIG_USB_ULPI_VIEWPORT
-       #error  "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
-                       define CONFIG_USB_ULPI_VIEWPORT"
-       #endif
-#endif
-
-enum {
-       USB_PORTS_MAX   = 4,                    /* Maximum ports we allow */
-};
-
-/* Parameters we need for USB */
-enum {
-       PARAM_DIVN,                     /* PLL FEEDBACK DIVIDer */
-       PARAM_DIVM,                     /* PLL INPUT DIVIDER */
-       PARAM_DIVP,                     /* POST DIVIDER (2^N) */
-       PARAM_CPCON,                    /* BASE PLLC CHARGE Pump setup ctrl */
-       PARAM_LFCON,                    /* BASE PLLC LOOP FILter setup ctrl */
-       PARAM_ENABLE_DELAY_COUNT,       /* PLL-U Enable Delay Count */
-       PARAM_STABLE_COUNT,             /* PLL-U STABLE count */
-       PARAM_ACTIVE_DELAY_COUNT,       /* PLL-U Active delay count */
-       PARAM_XTAL_FREQ_COUNT,          /* PLL-U XTAL frequency count */
-       PARAM_DEBOUNCE_A_TIME,          /* 10MS DELAY for BIAS_DEBOUNCE_A */
-       PARAM_BIAS_TIME,                /* 20US DELAY AFter bias cell op */
-
-       PARAM_COUNT
-};
-
-/* Possible port types (dual role mode) */
-enum dr_mode {
-       DR_MODE_NONE = 0,
-       DR_MODE_HOST,           /* supports host operation */
-       DR_MODE_DEVICE,         /* supports device operation */
-       DR_MODE_OTG,            /* supports both */
-};
-
-/* Information about a USB port */
-struct fdt_usb {
-       struct usb_ctlr *reg;   /* address of registers in physical memory */
-       unsigned utmi:1;        /* 1 if port has external tranceiver, else 0 */
-       unsigned ulpi:1;        /* 1 if port has external ULPI transceiver */
-       unsigned enabled:1;     /* 1 to enable, 0 to disable */
-       unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
-       enum dr_mode dr_mode;   /* dual role mode */
-       enum periph_id periph_id;/* peripheral id */
-       struct fdt_gpio_state vbus_gpio;        /* GPIO for vbus enable */
-       struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
-};
-
-static struct fdt_usb port[USB_PORTS_MAX];     /* List of valid USB ports */
-static unsigned port_count;                    /* Number of available ports */
-
-/*
- * This table has USB timing parameters for each Oscillator frequency we
- * support. There are four sets of values:
- *
- * 1. PLLU configuration information (reference clock is osc/clk_m and
- * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
- *
- *  Reference frequency     13.0MHz      19.2MHz      12.0MHz      26.0MHz
- *  ----------------------------------------------------------------------
- *      DIVN                960 (0x3c0)  200 (0c8)    960 (3c0h)   960 (3c0)
- *      DIVM                13 (0d)      4 (04)       12 (0c)      26 (1a)
- * Filter frequency (MHz)   1            4.8          6            2
- * CPCON                    1100b        0011b        1100b        1100b
- * LFCON0                   0            0            0            0
- *
- * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
- *
- * Reference frequency     13.0MHz         19.2MHz         12.0MHz     26.0MHz
- * ---------------------------------------------------------------------------
- * PLLU_ENABLE_DLY_COUNT   02 (0x02)       03 (03)         02 (02)     04 (04)
- * PLLU_STABLE_COUNT       51 (33)         75 (4B)         47 (2F)    102 (66)
- * PLL_ACTIVE_DLY_COUNT    05 (05)         06 (06)         04 (04)     09 (09)
- * XTAL_FREQ_COUNT        127 (7F)        187 (BB)        118 (76)    254 (FE)
- *
- * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
- * SessEnd. Each of these signals have their own debouncer and for each of
- * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
- * BIAS_DEBOUNCE_B).
- *
- * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
- *    0xffff -> No debouncing at all
- *    <n> ms = <n> *1000 / (1/19.2MHz) / 4
- *
- * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
- * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4  = 4800 = 0x12c0
- *
- * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
- * values, so we can keep those to default.
- *
- * 4. The 20 microsecond delay after bias cell operation.
- */
-static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
-       /* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
-       { 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
-       { 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
-       { 0x3C0, 0x0C, 0x00, 0xC,   0,  0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
-       { 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
-};
-
-/* UTMIP Idle Wait Delay */
-static const u8 utmip_idle_wait_delay = 17;
-
-/* UTMIP Elastic limit */
-static const u8 utmip_elastic_limit = 16;
-
-/* UTMIP High Speed Sync Start Delay */
-static const u8 utmip_hs_sync_start_delay = 9;
-
-/* Put the port into host mode */
-static void set_host_mode(struct fdt_usb *config)
-{
-       /*
-        * If we are an OTG port, check if remote host is driving VBus and
-        * bail out in this case.
-        */
-       if (config->dr_mode == DR_MODE_OTG &&
-               (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
-               return;
-
-       /*
-        * If not driving, we set the GPIO to enable VBUS. We assume
-        * that the pinmux is set up correctly for this.
-        */
-       if (fdt_gpio_isvalid(&config->vbus_gpio)) {
-               fdtdec_setup_gpio(&config->vbus_gpio);
-               gpio_direction_output(config->vbus_gpio.gpio,
-                       (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
-                                0 : 1);
-               debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
-                       (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
-                               "low" : "high");
-       }
-}
-
-void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
-{
-       /* Reset the USB controller with 2us delay */
-       reset_periph(config->periph_id, 2);
-
-       /*
-        * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
-        * base address
-        */
-       if (config->has_legacy_mode)
-               setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
-
-       /* Put UTMIP1/3 in reset */
-       setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
-
-       /* Enable the UTMIP PHY */
-       if (config->utmi)
-               setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
-
-       /*
-        * TODO: where do we take the USB1 out of reset? The old code would
-        * take USB3 out of reset, but not USB1. This code doesn't do either.
-        */
-}
-
-/* set up the UTMI USB controller with the parameters provided */
-static int init_utmi_usb_controller(struct fdt_usb *config,
-                               struct usb_ctlr *usbctlr, const u32 timing[])
-{
-       u32 val;
-       int loop_count;
-
-       clock_enable(config->periph_id);
-
-       /* Reset the usb controller */
-       usbf_reset_controller(config, usbctlr);
-
-       /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
-       clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
-
-       /* Follow the crystal clock disable by >100ns delay */
-       udelay(1);
-
-       /*
-        * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
-        * mux must be switched to actually use a_sess_vld threshold.
-        */
-       if (fdt_gpio_isvalid(&config->vbus_gpio)) {
-               clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
-                       VBUS_SENSE_CTL_MASK,
-                       VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
-       }
-
-       /*
-        * PLL Delay CONFIGURATION settings. The following parameters control
-        * the bring up of the plls.
-        */
-       val = readl(&usbctlr->utmip_misc_cfg1);
-       clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
-               timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
-       clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
-               timing[PARAM_ACTIVE_DELAY_COUNT] <<
-                       UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
-       writel(val, &usbctlr->utmip_misc_cfg1);
-
-       /* Set PLL enable delay count and crystal frequency count */
-       val = readl(&usbctlr->utmip_pll_cfg1);
-       clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
-               timing[PARAM_ENABLE_DELAY_COUNT] <<
-                       UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
-       clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
-               timing[PARAM_XTAL_FREQ_COUNT] <<
-                       UTMIP_XTAL_FREQ_COUNT_SHIFT);
-       writel(val, &usbctlr->utmip_pll_cfg1);
-
-       /* Setting the tracking length time */
-       clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
-               UTMIP_BIAS_PDTRK_COUNT_MASK,
-               timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
-
-       /* Program debounce time for VBUS to become valid */
-       clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
-               UTMIP_DEBOUNCE_CFG0_MASK,
-               timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
-
-       setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
-
-       /* Disable battery charge enabling bit */
-       setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
-
-       clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
-       setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
-
-       /*
-        * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
-        * Setting these fields, together with default values of the
-        * other fields, results in programming the registers below as
-        * follows:
-        *         UTMIP_HSRX_CFG0 = 0x9168c000
-        *         UTMIP_HSRX_CFG1 = 0x13
-        */
-
-       /* Set PLL enable delay count and Crystal frequency count */
-       val = readl(&usbctlr->utmip_hsrx_cfg0);
-       clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
-               utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
-       clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
-               utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
-       writel(val, &usbctlr->utmip_hsrx_cfg0);
-
-       /* Configure the UTMIP_HS_SYNC_START_DLY */
-       clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
-               UTMIP_HS_SYNC_START_DLY_MASK,
-               utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
-
-       /* Preceed the crystal clock disable by >100ns delay. */
-       udelay(1);
-
-       /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
-       setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
-
-       /* Finished the per-controller init. */
-
-       /* De-assert UTMIP_RESET to bring out of reset. */
-       clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
-
-       /* Wait for the phy clock to become valid in 100 ms */
-       for (loop_count = 100000; loop_count != 0; loop_count--) {
-               if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
-                       break;
-               udelay(1);
-       }
-       if (!loop_count)
-               return -1;
-
-       /* Disable ICUSB FS/LS transceiver */
-       clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
-
-       /* Select UTMI parallel interface */
-       clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
-                       PTS_UTMI << PTS_SHIFT);
-       clrbits_le32(&usbctlr->port_sc1, STS);
-
-       /* Deassert power down state */
-       clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
-               UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
-       clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
-               UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
-
-       return 0;
-}
-
-#ifdef CONFIG_USB_ULPI
-/* if board file does not set a ULPI reference frequency we default to 24MHz */
-#ifndef CONFIG_ULPI_REF_CLK
-#define CONFIG_ULPI_REF_CLK 24000000
-#endif
-
-/* set up the ULPI USB controller with the parameters provided */
-static int init_ulpi_usb_controller(struct fdt_usb *config,
-                               struct usb_ctlr *usbctlr)
-{
-       u32 val;
-       int loop_count;
-       struct ulpi_viewport ulpi_vp;
-
-       /* set up ULPI reference clock on pllp_out4 */
-       clock_enable(PERIPH_ID_DEV2_OUT);
-       clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
-
-       /* reset ULPI phy */
-       if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
-               fdtdec_setup_gpio(&config->phy_reset_gpio);
-               gpio_direction_output(config->phy_reset_gpio.gpio, 0);
-               mdelay(5);
-               gpio_set_value(config->phy_reset_gpio.gpio, 1);
-       }
-
-       /* Reset the usb controller */
-       clock_enable(config->periph_id);
-       usbf_reset_controller(config, usbctlr);
-
-       /* enable pinmux bypass */
-       setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
-                       ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
-
-       /* Select ULPI parallel interface */
-       clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
-
-       /* enable ULPI transceiver */
-       setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
-
-       /* configure ULPI transceiver timings */
-       val = 0;
-       writel(val, &usbctlr->ulpi_timing_ctrl_1);
-
-       val |= ULPI_DATA_TRIMMER_SEL(4);
-       val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
-       val |= ULPI_DIR_TRIMMER_SEL(4);
-       writel(val, &usbctlr->ulpi_timing_ctrl_1);
-       udelay(10);
-
-       val |= ULPI_DATA_TRIMMER_LOAD;
-       val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
-       val |= ULPI_DIR_TRIMMER_LOAD;
-       writel(val, &usbctlr->ulpi_timing_ctrl_1);
-
-       /* set up phy for host operation with external vbus supply */
-       ulpi_vp.port_num = 0;
-       ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
-
-       if (ulpi_init(&ulpi_vp)) {
-               printf("Tegra ULPI viewport init failed\n");
-               return -1;
-       }
-
-       ulpi_set_vbus(&ulpi_vp, 1, 1);
-       ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
-
-       /* enable wakeup events */
-       setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
-
-       /* Enable and wait for the phy clock to become valid in 100 ms */
-       setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
-       for (loop_count = 100000; loop_count != 0; loop_count--) {
-               if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
-                       break;
-               udelay(1);
-       }
-       if (!loop_count)
-               return -1;
-       clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
-
-       return 0;
-}
-#else
-static int init_ulpi_usb_controller(struct fdt_usb *config,
-                               struct usb_ctlr *usbctlr)
-{
-       printf("No code to set up ULPI controller, please enable"
-                       "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
-       return -1;
-}
-#endif
-
-static void config_clock(const u32 timing[])
-{
-       clock_start_pll(CLOCK_ID_USB,
-               timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
-               timing[PARAM_CPCON], timing[PARAM_LFCON]);
-}
-
-/**
- * Add a new USB port to the list of available ports.
- *
- * @param config       USB port configuration
- * @return 0 if ok, -1 if error (too many ports)
- */
-static int add_port(struct fdt_usb *config, const u32 timing[])
-{
-       struct usb_ctlr *usbctlr = config->reg;
-
-       if (port_count == USB_PORTS_MAX) {
-               printf("tegrausb: Cannot register more than %d ports\n",
-                     USB_PORTS_MAX);
-               return -1;
-       }
-
-       if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
-               printf("tegrausb: Cannot init port\n");
-               return -1;
-       }
-
-       if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
-               printf("tegrausb: Cannot init port\n");
-               return -1;
-       }
-
-       port[port_count++] = *config;
-
-       return 0;
-}
-
-int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
-{
-       struct usb_ctlr *usbctlr;
-
-       if (portnum >= port_count)
-               return -1;
-       set_host_mode(&port[portnum]);
-
-       usbctlr = port[portnum].reg;
-       *hccr = (u32)&usbctlr->cap_length;
-       *hcor = (u32)&usbctlr->usb_cmd;
-       return 0;
-}
-
-int tegrausb_stop_port(int portnum)
-{
-       struct usb_ctlr *usbctlr;
-
-       usbctlr = port[portnum].reg;
-
-       /* Stop controller */
-       writel(0, &usbctlr->usb_cmd);
-       udelay(1000);
-
-       /* Initiate controller reset */
-       writel(2, &usbctlr->usb_cmd);
-       udelay(1000);
-
-       return 0;
-}
-
-int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
-                  struct fdt_usb *config)
-{
-       const char *phy, *mode;
-
-       config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
-       mode = fdt_getprop(blob, node, "dr_mode", NULL);
-       if (mode) {
-               if (0 == strcmp(mode, "host"))
-                       config->dr_mode = DR_MODE_HOST;
-               else if (0 == strcmp(mode, "peripheral"))
-                       config->dr_mode = DR_MODE_DEVICE;
-               else if (0 == strcmp(mode, "otg"))
-                       config->dr_mode = DR_MODE_OTG;
-               else {
-                       debug("%s: Cannot decode dr_mode '%s'\n", __func__,
-                             mode);
-                       return -FDT_ERR_NOTFOUND;
-               }
-       } else {
-               config->dr_mode = DR_MODE_HOST;
-       }
-
-       phy = fdt_getprop(blob, node, "phy_type", NULL);
-       config->utmi = phy && 0 == strcmp("utmi", phy);
-       config->ulpi = phy && 0 == strcmp("ulpi", phy);
-       config->enabled = fdtdec_get_is_enabled(blob, node);
-       config->has_legacy_mode = fdtdec_get_bool(blob, node,
-                                                 "nvidia,has-legacy-mode");
-       config->periph_id = clock_decode_periph_id(blob, node);
-       if (config->periph_id == PERIPH_ID_NONE) {
-               debug("%s: Missing/invalid peripheral ID\n", __func__);
-               return -FDT_ERR_NOTFOUND;
-       }
-       fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
-       fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
-                       &config->phy_reset_gpio);
-       debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
-               "vbus=%d, phy_reset=%d, dr_mode=%d\n",
-               config->enabled, config->has_legacy_mode, config->utmi,
-               config->ulpi, config->periph_id, config->vbus_gpio.gpio,
-               config->phy_reset_gpio.gpio, config->dr_mode);
-
-       return 0;
-}
-
-int board_usb_init(const void *blob)
-{
-       struct fdt_usb config;
-       unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
-       enum clock_osc_freq freq;
-       int node_list[USB_PORTS_MAX];
-       int node, count, i;
-
-       /* Set up the USB clocks correctly based on our oscillator frequency */
-       freq = clock_get_osc_freq();
-       config_clock(usb_pll[freq]);
-
-       /* count may return <0 on error */
-       count = fdtdec_find_aliases_for_id(blob, "usb",
-                       COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
-       for (i = 0; i < count; i++) {
-               debug("USB %d: ", i);
-               node = node_list[i];
-               if (!node)
-                       continue;
-               if (fdt_decode_usb(blob, node, osc_freq, &config)) {
-                       debug("Cannot decode USB node %s\n",
-                             fdt_get_name(blob, node, NULL));
-                       return -1;
-               }
-
-               if (add_port(&config, usb_pll[freq]))
-                       return -1;
-               set_host_mode(&config);
-       }
-
-       return 0;
-}
index 52b3ec4..4983a05 100644 (file)
@@ -37,6 +37,20 @@ struct tegra_pingroup_desc {
 #define PMUX_OD_SHIFT          6
 #define PMUX_LOCK_SHIFT                7
 #define PMUX_IO_RESET_SHIFT    8
+#define PMUX_RCV_SEL_SHIFT     9
+
+#define PGRP_HSM_SHIFT         2
+#define PGRP_SCHMT_SHIFT       3
+#define PGRP_LPMD_SHIFT                4
+#define PGRP_LPMD_MASK         (3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT       12
+#define PGRP_DRVDN_MASK                (0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT       20
+#define PGRP_DRVUP_MASK                (0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT                28
+#define PGRP_SLWR_MASK         (3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT                30
+#define PGRP_SLWF_MASK         (3 << PGRP_SLWF_SHIFT)
 
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
@@ -58,6 +72,10 @@ struct tegra_pingroup_desc {
 #define PINO(pg_name, vdd, f0, f1, f2, f3) \
        PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
 
+/* A pin group number which is not used */
+#define PIN_RESERVED \
+       PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
+
 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        /*      NAME      VDD      f0           f1         f2       f3  */
        PINI(ULPI_DATA0,  BB,      SPI3,       HSI,        UARTA,   ULPI),
@@ -84,71 +102,71 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PINI(SDMMC1_DAT2, SDMMC1,  SDMMC1,     PWM0,       SPI4,    UARTA),
        PINI(SDMMC1_DAT1, SDMMC1,  SDMMC1,     PWM1,       SPI4,    UARTA),
        PINI(SDMMC1_DAT0, SDMMC1,  SDMMC1,     RSVD2,      SPI4,    UARTA),
-       PINI(GPIO_PV2,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(GPIO_PV3,    BB,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x3060 - 0x3064 */
+       PIN_RESERVED,
        PINI(CLK2_OUT,    SDMMC1,  EXTPERIPH2, RSVD2,      RSVD3,   RSVD4),
        PINI(CLK2_REQ,    SDMMC1,  DAP,        RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_PWR1,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_PWR2,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_SDIN,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_SDOUT,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_WR_N,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_CS0_N,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_DC0,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_SCK,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_PWR0,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_PCLK,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_DE,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_HSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_VSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D0,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D1,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D2,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D3,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D4,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D5,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D6,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D7,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D8,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D9,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D10,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D11,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D12,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D13,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D14,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D15,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D16,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D17,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D18,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D19,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D20,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D21,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D22,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_D23,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_CS1_N,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_M1,      LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINO(LCD_DC1,     LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x3070 - 0x310c */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
        PINI(HDMI_INT,    LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
        PINI(DDC_SCL,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
        PINI(DDC_SDA,     LCD,     I2C4,       RSVD2,      RSVD3,   RSVD4),
-       PINI(CRT_HSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(CRT_VSYNC,   LCD,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D0,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D1,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D2,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D3,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D4,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D5,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D6,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D7,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D8,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D9,       VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D10,      VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_D11,      VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_PCLK,     VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_MCLK,     VI,      RSVD1,      RSVD3,      RSVD3,   RSVD4),
-       PINI(VI_VSYNC,    VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(VI_HSYNC,    VI,      RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x311c - 0x3160 */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
        PINI(UART2_RXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
        PINI(UART2_TXD,   UART,    UARTB,      SPDIF,      UARTA,   SPI4),
        PINI(UART2_RTS_N, UART,    UARTA,      UARTB,      RSVD3,   SPI4),
@@ -220,8 +238,8 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PINI(SDMMC4_DAT5, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
        PINI(SDMMC4_DAT6, SDMMC4,  SDMMC4,     SPI3,       GMI,     RSVD4),
        PINI(SDMMC4_DAT7, SDMMC4,  SDMMC4,     RSVD2,      GMI,     RSVD4),
-       PINI(SDMMC4_RST_N, SDMMC4, RSVD1,      RSVD2,      RSVD3,   SDMMC4),
-       PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT2, RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x3280 */
+       PINI(CAM_MCLK,    CAM,     VI,         VI_ALT1,    VI_ALT3, RSVD4),
        PINI(GPIO_PCC1,   CAM,     I2S4,       RSVD2,      RSVD3,   RSVD4),
        PINI(GPIO_PBB0,   CAM,     I2S4,       VI,         VI_ALT1, VI_ALT3),
        PINI(CAM_I2C_SCL, CAM,     VGP1,       I2C3,       RSVD3,   RSVD4),
@@ -246,11 +264,11 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PINI(KB_ROW8,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
        PINI(KB_ROW9,     SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
        PINI(KB_ROW10,    SYS,     KBC,        RSVD2,      RSVD3,   UARTA),
-       PINI(KB_ROW11,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(KB_ROW12,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(KB_ROW13,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(KB_ROW14,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(KB_ROW15,    SYS,     RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x32e8 - 0x32f8 */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
        PINI(KB_COL0,     SYS,     KBC,        USB,        SPI2,    EMC_DLL),
        PINI(KB_COL1,     SYS,     KBC,        RSVD2,      SPI2,    EMC_DLL),
        PINI(KB_COL2,     SYS,     KBC,        RSVD2,      SPI2,    RSVD4),
@@ -278,36 +296,46 @@ const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
        PINI(DAP2_DIN,    AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
        PINI(DAP2_DOUT,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
        PINI(DAP2_SCLK,   AUDIO,   I2S1,       HDA,        RSVD3,   RSVD4),
-       PINI(SPI2_MOSI,   AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
-       PINI(SPI2_MISO,   AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
-       PINI(SPI2_CS0_N,  AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
-       PINI(SPI2_SCK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
-       PINI(SPI1_MOSI,   AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
-       PINI(SPI1_SCK,    AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
-       PINI(SPI1_CS0_N,  AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
-       PINI(SPI1_MISO,   AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
-       PINI(SPI2_CS1_N,  AUDIO,   RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(SPI2_CS2_N,  AUDIO,   RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PINI(DVFS_PWM,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+       PINI(GPIO_X1_AUD, AUDIO,   SPI6,       RSVD2,      RSVD3,   RSVD4),
+       PINI(GPIO_X3_AUD, AUDIO,   SPI6,       SPI1,       RSVD3,   RSVD4),
+       PINI(DVFS_CLK,    AUDIO,   SPI6,       CLDVFS,     RSVD3,   RSVD4),
+       PINI(GPIO_X4_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    DAP2),
+       PINI(GPIO_X5_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+       PINI(GPIO_X6_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    RSVD4),
+       PINI(GPIO_X7_AUD, AUDIO,   RSVD1,      SPI1,       SPI2,    RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x3388 - 0x338c */
+       PIN_RESERVED,
        PINI(SDMMC3_CLK,  SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
        PINI(SDMMC3_CMD,  SDMMC3,  SDMMC3,     PWM3,       UARTA,   SPI3),
        PINI(SDMMC3_DAT0, SDMMC3,  SDMMC3,     RSVD2,      RSVD3,   SPI3),
        PINI(SDMMC3_DAT1, SDMMC3,  SDMMC3,     PWM2,       UARTA,   SPI3),
        PINI(SDMMC3_DAT2, SDMMC3,  SDMMC3,     PWM1,       DISPA,   SPI3),
        PINI(SDMMC3_DAT3, SDMMC3,  SDMMC3,     PWM0,       DISPB,   SPI3),
-       PINI(SDMMC3_DAT4, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(SDMMC3_DAT5, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(SDMMC3_DAT6, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
-       PINI(SDMMC3_DAT7, SDMMC3,  RSVD1,      RSVD2,      RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x33a8 - 0x33dc */
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
+       PIN_RESERVED,
        PINI(HDMI_CEC,    SYS,     CEC,        SDMMC3,     RSVD3,   SOC),
        PINI(SDMMC1_WP_N, SDMMC1,  SDMMC1,     CLK12,      SPI4,    UARTA),
-       PINI(SDMMC3_CD_N, SDMMC3,  SDMMC3,     OWR,        RSVD3,   RSVD4),
-       PINI(SPI1_CS1_N,  AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
-       PINI(SPI1_CS2_N,  AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
-       PINI(USB_VBUS_EN0, SYS,    USB,        RSVD2,      RSVD3,   RSVD4),
-       PINI(USB_VBUS_EN1, SYS,    USB,        RSVD2,      RSVD3,   RSVD4),
+       PINI(SDMMC3_CD_N, SYS,  SDMMC3,     OWR,        RSVD3,   RSVD4),
+       PINI(GPIO_W2_AUD, AUDIO,   SPI6,       RSVD2,      SPI2,    I2C1),
+       PINI(GPIO_W3_AUD, AUDIO,   SPI6,       SPI1,       SPI2,    I2C1),
+       PINI(USB_VBUS_EN0, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
+       PINI(USB_VBUS_EN1, LCD,    USB,        RSVD2,      RSVD3,   RSVD4),
        PINI(SDMMC3_CLK_LB_IN,  SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
-       PINO(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
-       PINO(NAND_GMI_CLK_LB,   GMI,    SDMMC2, NAND,      GMI,     RSVD4),
+       PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2,     RSVD3,   RSVD4),
+       PIN_RESERVED,   /* Reserved by t114: 0x3404 */
        PINO(RESET_OUT_N, SYS,     RSVD1,      RSVD2,      RSVD3, RESET_OUT_N),
 };
 
@@ -484,6 +512,30 @@ static int pinmux_set_ioreset(enum pmux_pingrp pin,
        return 0;
 }
 
+static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
+                               enum pmux_pin_rcv_sel rcv_sel)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
+       u32 reg;
+
+       /* Error check on pin and rcv_sel */
+       assert(pmux_pingrp_isvalid(pin));
+       assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
+
+       if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
+               return 0;
+
+       reg = readl(pin_rcv_sel);
+       reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
+       if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
+               reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
+       writel(reg, pin_rcv_sel);
+
+       return 0;
+}
+
 void pinmux_config_pingroup(struct pingroup_config *config)
 {
        enum pmux_pingrp pin = config->pingroup;
@@ -495,6 +547,7 @@ void pinmux_config_pingroup(struct pingroup_config *config)
        pinmux_set_lock(pin, config->lock);
        pinmux_set_od(pin, config->od);
        pinmux_set_ioreset(pin, config->ioreset);
+       pinmux_set_rcv_sel(pin, config->rcv_sel);
 }
 
 void pinmux_config_table(struct pingroup_config *config, int len)
@@ -504,3 +557,184 @@ void pinmux_config_table(struct pingroup_config *config, int len)
        for (i = 0; i < len; i++)
                pinmux_config_pingroup(&config[i]);
 }
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_slwf = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and slwf */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_slw_isvalid(slwf));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwf == PGRP_SLWF_NONE)
+               return 0;
+
+       reg = readl(pad_slwf);
+       reg &= ~PGRP_SLWF_MASK;
+       reg |= (slwf << PGRP_SLWF_SHIFT);
+       writel(reg, pad_slwf);
+
+       return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_slwr = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and slwr */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_slw_isvalid(slwr));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwr == PGRP_SLWR_NONE)
+               return 0;
+
+       reg = readl(pad_slwr);
+       reg &= ~PGRP_SLWR_MASK;
+       reg |= (slwr << PGRP_SLWR_SHIFT);
+       writel(reg, pad_slwr);
+
+       return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_drvup = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and drvup */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_drv_isvalid(drvup));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvup == PGRP_DRVUP_NONE)
+               return 0;
+
+       reg = readl(pad_drvup);
+       reg &= ~PGRP_DRVUP_MASK;
+       reg |= (drvup << PGRP_DRVUP_SHIFT);
+       writel(reg, pad_drvup);
+
+       return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_drvdn = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and drvdn */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_drv_isvalid(drvdn));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvdn == PGRP_DRVDN_NONE)
+               return 0;
+
+       reg = readl(pad_drvdn);
+       reg &= ~PGRP_DRVDN_MASK;
+       reg |= (drvdn << PGRP_DRVDN_SHIFT);
+       writel(reg, pad_drvdn);
+
+       return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_lpmd = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad and lpmd value */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_lpmd_isvalid(lpmd));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (lpmd == PGRP_LPMD_NONE)
+               return 0;
+
+       reg = readl(pad_lpmd);
+       reg &= ~PGRP_LPMD_MASK;
+       reg |= (lpmd << PGRP_LPMD_SHIFT);
+       writel(reg, pad_lpmd);
+
+       return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_schmt = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad */
+       assert(pmux_padgrp_isvalid(pad));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (schmt == PGRP_SCHMT_NONE)
+               return 0;
+
+       reg = readl(pad_schmt);
+       reg &= ~(1 << PGRP_SCHMT_SHIFT);
+       if (schmt == PGRP_SCHMT_ENABLE)
+               reg |= (0x1 << PGRP_SCHMT_SHIFT);
+       writel(reg, pad_schmt);
+
+       return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_hsm = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad */
+       assert(pmux_padgrp_isvalid(pad));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (hsm == PGRP_HSM_NONE)
+               return 0;
+
+       reg = readl(pad_hsm);
+       reg &= ~(1 << PGRP_HSM_SHIFT);
+       if (hsm == PGRP_HSM_ENABLE)
+               reg |= (0x1 << PGRP_HSM_SHIFT);
+       writel(reg, pad_hsm);
+
+       return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+       enum pdrive_pingrp pad = config->padgrp;
+
+       padgrp_set_drvup_slwf(pad, config->slwf);
+       padgrp_set_drvdn_slwr(pad, config->slwr);
+       padgrp_set_drvup(pad, config->drvup);
+       padgrp_set_drvdn(pad, config->drvdn);
+       padgrp_set_lpmd(pad, config->lpmd);
+       padgrp_set_schmt(pad, config->schmt);
+       padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+       int i;
+
+       for (i = 0; i < len; i++)
+               padctrl_config_pingroup(&config[i]);
+}
index 122665f..eecf058 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -38,6 +38,19 @@ struct tegra_pingroup_desc {
 #define PMUX_LOCK_SHIFT                7
 #define PMUX_IO_RESET_SHIFT    8
 
+#define PGRP_HSM_SHIFT         2
+#define PGRP_SCHMT_SHIFT       3
+#define PGRP_LPMD_SHIFT                4
+#define PGRP_LPMD_MASK         (3 << PGRP_LPMD_SHIFT)
+#define PGRP_DRVDN_SHIFT       12
+#define PGRP_DRVDN_MASK                (0x7F << PGRP_DRVDN_SHIFT)
+#define PGRP_DRVUP_SHIFT       20
+#define PGRP_DRVUP_MASK                (0x7F << PGRP_DRVUP_SHIFT)
+#define PGRP_SLWR_SHIFT                28
+#define PGRP_SLWR_MASK         (3 << PGRP_SLWR_SHIFT)
+#define PGRP_SLWF_SHIFT                30
+#define PGRP_SLWF_MASK         (3 << PGRP_SLWF_SHIFT)
+
 /* Convenient macro for defining pin group properties */
 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
        {                                               \
@@ -504,3 +517,178 @@ void pinmux_config_table(struct pingroup_config *config, int len)
        for (i = 0; i < len; i++)
                pinmux_config_pingroup(&config[i]);
 }
+
+static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
+                               int slwf)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_slwf = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and slwf */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_slw_isvalid(slwf));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwf == PGRP_SLWF_NONE)
+               return 0;
+
+       reg = readl(pad_slwf);
+       reg &= ~PGRP_SLWF_MASK;
+       reg |= (slwf << PGRP_SLWF_SHIFT);
+       writel(reg, pad_slwf);
+
+       return 0;
+}
+
+static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_slwr = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and slwr */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_slw_isvalid(slwr));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (slwr == PGRP_SLWR_NONE)
+               return 0;
+
+       reg = readl(pad_slwr);
+       reg &= ~PGRP_SLWR_MASK;
+       reg |= (slwr << PGRP_SLWR_SHIFT);
+       writel(reg, pad_slwr);
+
+       return 0;
+}
+
+static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_drvup = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and drvup */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_drv_isvalid(drvup));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvup == PGRP_DRVUP_NONE)
+               return 0;
+
+       reg = readl(pad_drvup);
+       reg &= ~PGRP_DRVUP_MASK;
+       reg |= (drvup << PGRP_DRVUP_SHIFT);
+       writel(reg, pad_drvup);
+
+       return 0;
+}
+
+static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_drvdn = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check on pad and drvdn */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_drv_isvalid(drvdn));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (drvdn == PGRP_DRVDN_NONE)
+               return 0;
+
+       reg = readl(pad_drvdn);
+       reg &= ~PGRP_DRVDN_MASK;
+       reg |= (drvdn << PGRP_DRVDN_SHIFT);
+       writel(reg, pad_drvdn);
+
+       return 0;
+}
+
+static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_lpmd = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad and lpmd value */
+       assert(pmux_padgrp_isvalid(pad));
+       assert(pmux_pad_lpmd_isvalid(lpmd));
+
+       /* NONE means unspecified/do not change/use POR value */
+       if (lpmd == PGRP_LPMD_NONE)
+               return 0;
+
+       reg = readl(pad_lpmd);
+       reg &= ~PGRP_LPMD_MASK;
+       reg |= (lpmd << PGRP_LPMD_SHIFT);
+       writel(reg, pad_lpmd);
+
+       return 0;
+}
+
+static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_schmt = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad */
+       assert(pmux_padgrp_isvalid(pad));
+
+       reg = readl(pad_schmt);
+       reg &= ~(1 << PGRP_SCHMT_SHIFT);
+       if (schmt == PGRP_SCHMT_ENABLE)
+               reg |= (0x1 << PGRP_SCHMT_SHIFT);
+       writel(reg, pad_schmt);
+
+       return 0;
+}
+static int padgrp_set_hsm(enum pdrive_pingrp pad,
+                       enum pgrp_hsm hsm)
+{
+       struct pmux_tri_ctlr *pmt =
+                       (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+       u32 *pad_hsm = &pmt->pmt_drive[pad];
+       u32 reg;
+
+       /* Error check pad */
+       assert(pmux_padgrp_isvalid(pad));
+
+       reg = readl(pad_hsm);
+       reg &= ~(1 << PGRP_HSM_SHIFT);
+       if (hsm == PGRP_HSM_ENABLE)
+               reg |= (0x1 << PGRP_HSM_SHIFT);
+       writel(reg, pad_hsm);
+
+       return 0;
+}
+
+void padctrl_config_pingroup(struct padctrl_config *config)
+{
+       enum pdrive_pingrp pad = config->padgrp;
+
+       padgrp_set_drvup_slwf(pad, config->slwf);
+       padgrp_set_drvdn_slwr(pad, config->slwr);
+       padgrp_set_drvup(pad, config->drvup);
+       padgrp_set_drvdn(pad, config->drvdn);
+       padgrp_set_lpmd(pad, config->lpmd);
+       padgrp_set_schmt(pad, config->schmt);
+       padgrp_set_hsm(pad, config->hsm);
+}
+
+void padgrp_config_table(struct padctrl_config *config, int len)
+{
+       int i;
+
+       for (i = 0; i < len; i++)
+               padctrl_config_pingroup(&config[i]);
+}
index d06cd12..701c0f9 100644 (file)
@@ -1,5 +1,78 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
        compatible = "nvidia,tegra114";
+
+       tegra_car: clock {
+               compatible = "nvidia,tegra114-car";
+               reg = <0x60006000 0x1000>;
+               #clock-cells = <1>;
+       };
+
+       gpio: gpio {
+               compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
+               reg = <0x6000d000 0x1000>;
+               interrupts = <0 32 0x04
+                             0 33 0x04
+                             0 34 0x04
+                             0 35 0x04
+                             0 55 0x04
+                             0 87 0x04
+                             0 89 0x04
+                             0 125 0x04>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+       };
+
+       i2c@7000c000 {
+               compatible = "nvidia,tegra114-i2c";
+               reg = <0x7000c000 0x100>;
+               interrupts = <0 38 0x04>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&tegra_car 12>;
+               status = "disabled";
+       };
+
+       i2c@7000c400 {
+               compatible = "nvidia,tegra114-i2c";
+               reg = <0x7000c400 0x100>;
+               interrupts = <0 84 0x04>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&tegra_car 54>;
+               status = "disabled";
+       };
+
+       i2c@7000c500 {
+               compatible = "nvidia,tegra114-i2c";
+               reg = <0x7000c500 0x100>;
+               interrupts = <0 92 0x04>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&tegra_car 67>;
+               status = "disabled";
+       };
+
+       i2c@7000c700 {
+               compatible = "nvidia,tegra114-i2c";
+               reg = <0x7000c700 0x100>;
+               interrupts = <0 120 0x04>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&tegra_car 103>;
+               status = "disabled";
+       };
+
+       i2c@7000d000 {
+               compatible = "nvidia,tegra114-i2c";
+               reg = <0x7000d000 0x100>;
+               interrupts = <0 53 0x04>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clocks = <&tegra_car 47>;
+               status = "disabled";
+       };
 };
index 9a89685..3805750 100644 (file)
@@ -1,4 +1,4 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
        compatible = "nvidia,tegra20";
        sdhci@c8000000 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000000 0x200>;
-               interrupts = < 46 >;
+               interrupts = <0 14 0x04>;
+               clocks = <&tegra_car 14>;
+               status = "disabled";
        };
 
        sdhci@c8000200 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000200 0x200>;
-               interrupts = < 47 >;
+               interrupts = <0 15 0x04>;
+               clocks = <&tegra_car 9>;
+               status = "disabled";
        };
 
        sdhci@c8000400 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000400 0x200>;
-               interrupts = < 51 >;
+               interrupts = <0 19 0x04>;
+               clocks = <&tegra_car 69>;
+               status = "disabled";
        };
 
        sdhci@c8000600 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000600 0x200>;
-               interrupts = < 63 >;
+               interrupts = <0 31 0x04>;
+               clocks = <&tegra_car 15>;
+               status = "disabled";
        };
 };
index 7b8126f..ccf154f 100644 (file)
@@ -1,10 +1,10 @@
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
        compatible = "nvidia,tegra30";
 
-       tegra_car: clock@60006000 {
-               compatible = "nvidia,tegra30-car", "nvidia,tegra20-car";
+       tegra_car: clock {
+               compatible = "nvidia,tegra30-car";
                reg = <0x60006000 0x1000>;
                #clock-cells = <1>;
        };
                              0 141 0x04
                              0 142 0x04
                              0 143 0x04>;
+               clocks = <&tegra_car 34>;
+       };
+
+       gpio: gpio {
+               compatible = "nvidia,tegra30-gpio";
+               reg = <0x6000d000 0x1000>;
+               interrupts = <0 32 0x04
+                             0 33 0x04
+                             0 34 0x04
+                             0 35 0x04
+                             0 55 0x04
+                             0 87 0x04
+                             0 89 0x04
+                             0 125 0x04>;
+               #gpio-cells = <2>;
+               gpio-controller;
+               #interrupt-cells = <2>;
+               interrupt-controller;
        };
 
        i2c@7000c000 {
+               compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+               reg = <0x7000c000 0x100>;
+               interrupts = <0 38 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-               reg = <0x7000C000 0x100>;
-               /* PERIPH_ID_I2C1, CLK_M */
-               clocks = <&tegra_car 12>;
+               clocks = <&tegra_car 12>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
+               status = "disabled";
        };
 
        i2c@7000c400 {
+               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+               reg = <0x7000c400 0x100>;
+               interrupts = <0 84 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-               reg = <0x7000C400 0x100>;
-               /* PERIPH_ID_I2C2, CLK_M */
-               clocks = <&tegra_car 54>;
+               clocks = <&tegra_car 54>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
+               status = "disabled";
        };
 
        i2c@7000c500 {
+               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+               reg = <0x7000c500 0x100>;
+               interrupts = <0 92 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-               reg = <0x7000C500 0x100>;
-               /* PERIPH_ID_I2C3, CLK_M */
-               clocks = <&tegra_car 67>;
+               clocks = <&tegra_car 67>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
+               status = "disabled";
        };
 
        i2c@7000c700 {
+               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+               reg = <0x7000c700 0x100>;
+               interrupts = <0 120 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-               reg = <0x7000C700 0x100>;
-               /* PERIPH_ID_I2C4, CLK_M */
-               clocks = <&tegra_car 103>;
+               clocks = <&tegra_car 103>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
+               status = "disabled";
        };
 
        i2c@7000d000 {
+               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+               reg = <0x7000d000 0x100>;
+               interrupts = <0 53 0x04>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
-               reg = <0x7000D000 0x100>;
-               /* PERIPH_ID_I2C_DVC, CLK_M */
-               clocks = <&tegra_car 47>;
+               clocks = <&tegra_car 47>, <&tegra_car 182>;
+               clock-names = "div-clk", "fast-clk";
+               status = "disabled";
        };
 
        spi@7000d400 {
                nvidia,dma-request-selector = <&apbdma 15>;
                #address-cells = <1>;
                #size-cells = <0>;
-               status = "disabled";
-               /* PERIPH_ID_SBC1, PLLP_OUT0 */
                clocks = <&tegra_car 41>;
+               status = "disabled";
        };
 
        spi@7000d600 {
                nvidia,dma-request-selector = <&apbdma 16>;
                #address-cells = <1>;
                #size-cells = <0>;
-               status = "disabled";
-               /* PERIPH_ID_SBC2, PLLP_OUT0 */
                clocks = <&tegra_car 44>;
+               status = "disabled";
        };
 
        spi@7000d800 {
                nvidia,dma-request-selector = <&apbdma 17>;
                #address-cells = <1>;
                #size-cells = <0>;
-               status = "disabled";
-               /* PERIPH_ID_SBC3, PLLP_OUT0 */
                clocks = <&tegra_car 46>;
+               status = "disabled";
        };
 
        spi@7000da00 {
                nvidia,dma-request-selector = <&apbdma 18>;
                #address-cells = <1>;
                #size-cells = <0>;
-               status = "disabled";
-               /* PERIPH_ID_SBC4, PLLP_OUT0 */
                clocks = <&tegra_car 68>;
+               status = "disabled";
        };
 
        spi@7000dc00 {
                nvidia,dma-request-selector = <&apbdma 27>;
                #address-cells = <1>;
                #size-cells = <0>;
-               status = "disabled";
-               /* PERIPH_ID_SBC5, PLLP_OUT0 */
                clocks = <&tegra_car 104>;
+               status = "disabled";
        };
 
        spi@7000de00 {
                nvidia,dma-request-selector = <&apbdma 28>;
                #address-cells = <1>;
                #size-cells = <0>;
-               status = "disabled";
-               /* PERIPH_ID_SBC6, PLLP_OUT0 */
                clocks = <&tegra_car 105>;
+               status = "disabled";
+       };
+
+       sdhci@78000000 {
+               compatible = "nvidia,tegra30-sdhci";
+               reg = <0x78000000 0x200>;
+               interrupts = <0 14 0x04>;
+               clocks = <&tegra_car 14>;
+               status = "disabled";
+       };
+
+       sdhci@78000200 {
+               compatible = "nvidia,tegra30-sdhci";
+               reg = <0x78000200 0x200>;
+               interrupts = <0 15 0x04>;
+               clocks = <&tegra_car 9>;
+               status = "disabled";
+       };
+
+       sdhci@78000400 {
+               compatible = "nvidia,tegra30-sdhci";
+               reg = <0x78000400 0x200>;
+               interrupts = <0 19 0x04>;
+               clocks = <&tegra_car 69>;
+               status = "disabled";
+       };
+
+       sdhci@78000600 {
+               compatible = "nvidia,tegra30-sdhci";
+               reg = <0x78000600 0x200>;
+               interrupts = <0 31 0x04>;
+               clocks = <&tegra_car 15>;
+               status = "disabled";
        };
 };
index 5c95047..71ad407 100644 (file)
@@ -22,6 +22,6 @@
 #ifndef _TEGRA_MMC_H_
 #define _TEGRA_MMC_H_
 
-int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+void tegra_mmc_init(void);
 
 #endif /* _TEGRA_MMC_H_ */
index 2650744..853e59b 100644 (file)
@@ -105,6 +105,7 @@ struct i2c_ctlr {
        u32 sl_delay_count;             /* 3C: I2C_I2C_SL_DELAY_COUNT */
        u32 reserved_2[4];              /* 40: */
        struct i2c_control control;     /* 50 ~ 68 */
+       u32 clk_div;                    /* 6C: I2C_I2C_CLOCK_DIVISOR */
 };
 
 /* bit fields definitions for IO Packet Header 1 format */
@@ -154,6 +155,11 @@ struct i2c_ctlr {
 #define I2C_INT_ARBITRATION_LOST_SHIFT 2
 #define I2C_INT_ARBITRATION_LOST_MASK  (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
 
+/* I2C_CLK_DIVISOR_REGISTER */
+#define CLK_DIV_STD_FAST_MODE          0x19
+#define CLK_DIV_HS_MODE                        1
+#define CLK_MULT_STD_FAST_MODE         8
+
 /**
  * Returns the bus number of the DVC controller
  *
index dd746ca..2a3f830 100644 (file)
 #ifndef __TEGRA_MMC_H_
 #define __TEGRA_MMC_H_
 
-#define TEGRA_SDMMC1_BASE      0xC8000000
-#define TEGRA_SDMMC2_BASE      0xC8000200
-#define TEGRA_SDMMC3_BASE      0xC8000400
-#define TEGRA_SDMMC4_BASE      0xC8000600
+#include <fdtdec.h>
+
+#define MAX_HOSTS              4       /* Max number of 'hosts'/controllers */
 
 #ifndef __ASSEMBLY__
 struct tegra_mmc {
@@ -62,12 +61,30 @@ struct tegra_mmc {
        unsigned char   admaerr;        /* offset 54h */
        unsigned char   res4[3];        /* RESERVED, offset 55h-57h */
        unsigned long   admaaddr;       /* offset 58h-5Fh */
-       unsigned char   res5[0x9c];     /* RESERVED, offset 60h-FBh */
+       unsigned char   res5[0xa0];     /* RESERVED, offset 60h-FBh */
        unsigned short  slotintstatus;  /* offset FCh */
        unsigned short  hcver;          /* HOST Version */
-       unsigned char   res6[0x100];    /* RESERVED, offset 100h-1FFh */
+       unsigned int    venclkctl;      /* _VENDOR_CLOCK_CNTRL_0,    100h */
+       unsigned int    venspictl;      /* _VENDOR_SPI_CNTRL_0,      104h */
+       unsigned int    venspiintsts;   /* _VENDOR_SPI_INT_STATUS_0, 108h */
+       unsigned int    venceatactl;    /* _VENDOR_CEATA_CNTRL_0,    10Ch */
+       unsigned int    venbootctl;     /* _VENDOR_BOOT_CNTRL_0,     110h */
+       unsigned int    venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
+       unsigned int    venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
+       unsigned int    vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
+       unsigned int    venmiscctl;     /* _VENDOR_MISC_CNTRL_0,     120h */
+       unsigned int    res6[47];       /* 0x124 ~ 0x1DC */
+       unsigned int    sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0,      1E0h */
+       unsigned int    autocalcfg;     /* _AUTO_CAL_CONFIG_0,       1E4h */
+       unsigned int    autocalintval;  /* _AUTO_CAL_INTERVAL_0,     1E8h */
+       unsigned int    autocalsts;     /* _AUTO_CAL_STATUS_0,       1ECh */
 };
 
+#define TEGRA_MMC_PWRCTL_SD_BUS_POWER                          (1 << 0)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8                   (5 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0                   (6 << 1)
+#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3                   (7 << 1)
+
 #define TEGRA_MMC_HOSTCTL_DMASEL_MASK                          (3 << 3)
 #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                          (0 << 3)
 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                   (2 << 3)
@@ -117,15 +134,26 @@ struct tegra_mmc {
 
 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                    (1 << 1)
 
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define MEMCOMP_PADCTRL_VREF   7
+#define AUTO_CAL_ENABLED       (1 << 29)
+#define AUTO_CAL_PD_OFFSET     (0x70 << 8)
+#define AUTO_CAL_PU_OFFSET     (0x62 << 0)
+
 struct mmc_host {
        struct tegra_mmc *reg;
+       int id;                 /* device id/number, 0-3 */
+       int enabled;            /* 1 to enable, 0 to disable */
+       int width;              /* Bus Width, 1, 4 or 8 */
+       enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
+       struct fdt_gpio_state cd_gpio;          /* Change Detect GPIO */
+       struct fdt_gpio_state pwr_gpio;         /* Power GPIO */
+       struct fdt_gpio_state wp_gpio;          /* Write Protect GPIO */
        unsigned int version;   /* SDHCI spec. version */
        unsigned int clock;     /* Current clock (MHz) */
-       unsigned int base;      /* Base address, SDMMC1/2/3/4 */
-       enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
-       int pwr_gpio;           /* Power GPIO */
-       int cd_gpio;            /* Change Detect GPIO */
 };
 
+void pad_init_mmc(struct mmc_host *host);
+
 #endif /* __ASSEMBLY__ */
 #endif /* __TEGRA_MMC_H_ */
similarity index 89%
rename from arch/arm/include/asm/arch-tegra20/usb.h
rename to arch/arm/include/asm/arch-tegra/usb.h
index fdbd127..ef6c089 100644 (file)
@@ -243,29 +243,7 @@ struct usb_ctlr {
 #define VBUS_VLD_STS                   (1 << 26)
 
 
-/* Change the USB host port into host mode */
-void usb_set_host_mode(void);
-
 /* Setup USB on the board */
 int board_usb_init(const void *blob);
 
-/**
- * Start up the given port number (ports are numbered from 0 on each board).
- * This returns values for the appropriate hccr and hcor addresses to use for
- * USB EHCI operations.
- *
- * @param portnum      port number to start
- * @param hccr         returns start address of EHCI HCCR registers
- * @param hcor         returns start address of EHCI HCOR registers
- * @return 0 if ok, -1 on error (generally invalid port number)
- */
-int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor);
-
-/**
- * Stop the current port
- *
- * @return 0 if ok, -1 if no port was active
- */
-int tegrausb_stop_port(int portnum);
-
 #endif /* _TEGRA_USB_H_ */
index c538bdd..1ef1a14 100644 (file)
@@ -27,7 +27,7 @@ struct apb_misc_gp_ctlr {
        u32     emu_revid;      /* 0x60: APB_MISC_GP_EMU_REVID */
        u32     xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
        u32     aocfg1;         /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
-       u32     aocfg2;         /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */
+       u32     aocfg2;         /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
        u32     atcfg1;         /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
        u32     atcfg2;         /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
        u32     atcfg3;         /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
@@ -35,25 +35,43 @@ struct apb_misc_gp_ctlr {
        u32     atcfg5;         /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
        u32     cdev1cfg;       /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
        u32     cdev2cfg;       /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
-       u32     csuscfg;        /* 0x8C: APB_MISC_GP_CSUSCFGPADCTRL */
+       u32     reserved1;      /* 0x8C: */
        u32     dap1cfg;        /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
        u32     dap2cfg;        /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
        u32     dap3cfg;        /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
        u32     dap4cfg;        /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
        u32     dbgcfg;         /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
-       u32     lcdcfg1;        /* 0xA4: APB_MISC_GP_LCDCFG1PADCTRL */
-       u32     lcdcfg2;        /* 0xA8: APB_MISC_GP_LCDCFG2PADCTRL */
-       u32     sdio2cfg;       /* 0xAC: APB_MISC_GP_SDIO2CFGPADCTRL */
+       u32     reserved2[3];   /* 0xA4 - 0xAC: */
        u32     sdio3cfg;       /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
        u32     spicfg;         /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
        u32     uaacfg;         /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
        u32     uabcfg;         /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
        u32     uart2cfg;       /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
        u32     uart3cfg;       /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
-       u32     vicfg1;         /* 0xC8: APB_MISC_GP_VICFG1PADCTRL */
-       u32     vivttgen;       /* 0xCC: APB_MISC_GP_VIVTTGENPADCTRL */
-       u32     reserved1[7];   /* 0xD0-0xE8: */
+       u32     reserved3[9];   /* 0xC8-0xE8: */
        u32     sdio1cfg;       /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
+       u32     reserved4[3];   /* 0xF0-0xF8: */
+       u32     ddccfg;         /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
+       u32     gmacfg;         /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
+       u32     reserved5[3];   /* 0x104-0x10C: */
+       u32     gmecfg;         /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
+       u32     gmfcfg;         /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
+       u32     gmgcfg;         /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
+       u32     gmhcfg;         /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
+       u32     owrcfg;         /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
+       u32     uadcfg;         /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
+       u32     reserved6;      /* 0x128: */
+       u32     dev3cfg;        /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
+       u32     reserved7[2];   /* 0x130 - 0x134: */
+       u32     ceccfg;         /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
+       u32     reserved8[22];  /* 0x13C - 0x190: */
+       u32     atcfg6;         /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
+       u32     dap5cfg;        /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
+       u32     vbuscfg;        /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
+       u32     aocfg3;         /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
+       u32     hvccfg0;        /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
+       u32     sdio4cfg;       /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
+       u32     aocfg0;         /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
 };
 
 #endif /* _TEGRA114_GP_PADCTRL_H_ */
index fd22930..9c22c08 100644 (file)
@@ -50,72 +50,12 @@ enum pmux_pingrp {
        PINGRP_SDMMC1_DAT2,
        PINGRP_SDMMC1_DAT1,
        PINGRP_SDMMC1_DAT0,
-       PINGRP_GPIO_PV2,
-       PINGRP_GPIO_PV3,
-       PINGRP_CLK2_OUT,
+       PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
        PINGRP_CLK2_REQ,
-       PINGRP_LCD_PWR1,
-       PINGRP_LCD_PWR2,
-       PINGRP_LCD_SDIN,
-       PINGRP_LCD_SDOUT,
-       PINGRP_LCD_WR_N,
-       PINGRP_LCD_CS0_N,
-       PINGRP_LCD_DC0,
-       PINGRP_LCD_SCK,
-       PINGRP_LCD_PWR0,
-       PINGRP_LCD_PCLK,
-       PINGRP_LCD_DE,
-       PINGRP_LCD_HSYNC,
-       PINGRP_LCD_VSYNC,
-       PINGRP_LCD_D0,
-       PINGRP_LCD_D1,
-       PINGRP_LCD_D2,
-       PINGRP_LCD_D3,
-       PINGRP_LCD_D4,
-       PINGRP_LCD_D5,
-       PINGRP_LCD_D6,
-       PINGRP_LCD_D7,
-       PINGRP_LCD_D8,
-       PINGRP_LCD_D9,
-       PINGRP_LCD_D10,
-       PINGRP_LCD_D11,
-       PINGRP_LCD_D12,
-       PINGRP_LCD_D13,
-       PINGRP_LCD_D14,
-       PINGRP_LCD_D15,
-       PINGRP_LCD_D16,
-       PINGRP_LCD_D17,
-       PINGRP_LCD_D18,
-       PINGRP_LCD_D19,
-       PINGRP_LCD_D20,
-       PINGRP_LCD_D21,
-       PINGRP_LCD_D22,
-       PINGRP_LCD_D23,
-       PINGRP_LCD_CS1_N,
-       PINGRP_LCD_M1,
-       PINGRP_LCD_DC1,
-       PINGRP_HDMI_INT,
+       PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
        PINGRP_DDC_SCL,
        PINGRP_DDC_SDA,
-       PINGRP_CRT_HSYNC,
-       PINGRP_CRT_VSYNC,
-       PINGRP_VI_D0,
-       PINGRP_VI_D1,
-       PINGRP_VI_D2,
-       PINGRP_VI_D3,
-       PINGRP_VI_D4,
-       PINGRP_VI_D5,
-       PINGRP_VI_D6,
-       PINGRP_VI_D7,
-       PINGRP_VI_D8,
-       PINGRP_VI_D9,
-       PINGRP_VI_D10,
-       PINGRP_VI_D11,
-       PINGRP_VI_PCLK,
-       PINGRP_VI_MCLK,
-       PINGRP_VI_VSYNC,
-       PINGRP_VI_HSYNC,
-       PINGRP_UART2_RXD,
+       PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
        PINGRP_UART2_TXD,
        PINGRP_UART2_RTS_N,
        PINGRP_UART2_CTS_N,
@@ -186,8 +126,7 @@ enum pmux_pingrp {
        PINGRP_SDMMC4_DAT5,
        PINGRP_SDMMC4_DAT6,
        PINGRP_SDMMC4_DAT7,
-       PINGRP_SDMMC4_RST_N,
-       PINGRP_CAM_MCLK,
+       PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
        PINGRP_GPIO_PCC1,
        PINGRP_GPIO_PBB0,
        PINGRP_CAM_I2C_SCL,
@@ -212,12 +151,7 @@ enum pmux_pingrp {
        PINGRP_KB_ROW8,
        PINGRP_KB_ROW9,
        PINGRP_KB_ROW10,
-       PINGRP_KB_ROW11,
-       PINGRP_KB_ROW12,
-       PINGRP_KB_ROW13,
-       PINGRP_KB_ROW14,
-       PINGRP_KB_ROW15,
-       PINGRP_KB_COL0,
+       PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
        PINGRP_KB_COL1,
        PINGRP_KB_COL2,
        PINGRP_KB_COL3,
@@ -244,47 +178,30 @@ enum pmux_pingrp {
        PINGRP_DAP2_DIN,
        PINGRP_DAP2_DOUT,
        PINGRP_DAP2_SCLK,
-       PINGRP_SPI2_MOSI,
-       PINGRP_SPI2_MISO,
-       PINGRP_SPI2_CS0_N,
-       PINGRP_SPI2_SCK,
-       PINGRP_SPI1_MOSI,
-       PINGRP_SPI1_SCK,
-       PINGRP_SPI1_CS0_N,
-       PINGRP_SPI1_MISO,
-       PINGRP_SPI2_CS1_N,
-       PINGRP_SPI2_CS2_N,
-       PINGRP_SDMMC3_CLK,
+       PINGRP_DVFS_PWM,
+       PINGRP_GPIO_X1_AUD,
+       PINGRP_GPIO_X3_AUD,
+       PINGRP_DVFS_CLK,
+       PINGRP_GPIO_X4_AUD,
+       PINGRP_GPIO_X5_AUD,
+       PINGRP_GPIO_X6_AUD,
+       PINGRP_GPIO_X7_AUD,
+       PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
        PINGRP_SDMMC3_CMD,
        PINGRP_SDMMC3_DAT0,
        PINGRP_SDMMC3_DAT1,
        PINGRP_SDMMC3_DAT2,
        PINGRP_SDMMC3_DAT3,
-       PINGRP_SDMMC3_DAT4,
-       PINGRP_SDMMC3_DAT5,
-       PINGRP_SDMMC3_DAT6,
-       PINGRP_SDMMC3_DAT7,
-       PINGRP_PEX_L0_PRSNT_N,
-       PINGRP_PEX_L0_RST_N,
-       PINGRP_PEX_L0_CLKREQ_N,
-       PINGRP_PEX_WAKE_N,
-       PINGRP_PEX_L1_PRSNT_N,
-       PINGRP_PEX_L1_RST_N,
-       PINGRP_PEX_L1_CLKREQ_N,
-       PINGRP_PEX_L2_PRSNT_N,
-       PINGRP_PEX_L2_RST_N,
-       PINGRP_PEX_L2_CLKREQ_N,
-       PINGRP_HDMI_CEC,        /* offset 0x33e0 */
+       PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
        PINGRP_SDMMC1_WP_N,
        PINGRP_SDMMC3_CD_N,
-       PINGRP_SPI1_CS1_N,
-       PINGRP_SPI1_CS2_N,
-       PINGRP_USB_VBUS_EN0,    /* offset 0x33f4 */
+       PINGRP_GPIO_W2_AUD,
+       PINGRP_GPIO_W3_AUD,
+       PINGRP_USB_VBUS_EN0,    /* offset 0x33f4 */
        PINGRP_USB_VBUS_EN1,
        PINGRP_SDMMC3_CLK_LB_IN,
        PINGRP_SDMMC3_CLK_LB_OUT,
-       PINGRP_NAND_GMI_CLK_LB,
-       PINGRP_RESET_OUT_N,
+       PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
        PINGRP_COUNT,
 };
 
@@ -298,41 +215,35 @@ enum pdrive_pingrp {
        PDRIVE_PINGROUP_AT5,
        PDRIVE_PINGROUP_CDEV1,
        PDRIVE_PINGROUP_CDEV2,
-       PDRIVE_PINGROUP_CSUS,
-       PDRIVE_PINGROUP_DAP1,
+       PDRIVE_PINGROUP_DAP1 = 10,      /* offset 0x890 */
        PDRIVE_PINGROUP_DAP2,
        PDRIVE_PINGROUP_DAP3,
        PDRIVE_PINGROUP_DAP4,
        PDRIVE_PINGROUP_DBG,
-       PDRIVE_PINGROUP_LCD1,
-       PDRIVE_PINGROUP_LCD2,
-       PDRIVE_PINGROUP_SDIO2,
-       PDRIVE_PINGROUP_SDIO3,
+       PDRIVE_PINGROUP_SDIO3 = 18,     /* offset 0x8B0 */
        PDRIVE_PINGROUP_SPI,
        PDRIVE_PINGROUP_UAA,
        PDRIVE_PINGROUP_UAB,
        PDRIVE_PINGROUP_UART2,
        PDRIVE_PINGROUP_UART3,
-       PDRIVE_PINGROUP_VI1 = 24,       /* offset 0x8c8 */
-       PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8ec */
-       PDRIVE_PINGROUP_CRT = 36,       /* offset 0x8f8 */
-       PDRIVE_PINGROUP_DDC,
+       PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
+       PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
        PDRIVE_PINGROUP_GMA,
-       PDRIVE_PINGROUP_GMB,
-       PDRIVE_PINGROUP_GMC,
-       PDRIVE_PINGROUP_GMD,
-       PDRIVE_PINGROUP_GME,
+       PDRIVE_PINGROUP_GME = 42,       /* offset 0x910 */
        PDRIVE_PINGROUP_GMF,
        PDRIVE_PINGROUP_GMG,
        PDRIVE_PINGROUP_GMH,
        PDRIVE_PINGROUP_OWR,
        PDRIVE_PINGROUP_UAD,
-       PDRIVE_PINGROUP_GPV,
        PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
        PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
-       PDRIVE_PINGROUP_AT6,
+       PDRIVE_PINGROUP_AT6 = 75,       /* offset 0x994 */
        PDRIVE_PINGROUP_DAP5,
        PDRIVE_PINGROUP_VBUS,
+       PDRIVE_PINGROUP_AO3,
+       PDRIVE_PINGROUP_HVC,
+       PDRIVE_PINGROUP_SDIO4,
+       PDRIVE_PINGROUP_AO0,
        PDRIVE_PINGROUP_COUNT,
 };
 
@@ -401,6 +312,7 @@ enum pmux_func {
        PMUX_FUNC_VI,
        PMUX_FUNC_VI_SENSOR_CLK,
        PMUX_FUNC_XIO,
+       /* End of Tegra2 MUX selectors */
        PMUX_FUNC_BLINK,
        PMUX_FUNC_CEC,
        PMUX_FUNC_CLK12,
@@ -444,7 +356,7 @@ enum pmux_func {
        PMUX_FUNC_VGP4,
        PMUX_FUNC_VGP5,
        PMUX_FUNC_VGP6,
-
+       /* End of Tegra3 MUX selectors */
        PMUX_FUNC_USB,
        PMUX_FUNC_SOC,
        PMUX_FUNC_CPU,
@@ -453,10 +365,12 @@ enum pmux_func {
        PMUX_FUNC_PMI,
        PMUX_FUNC_CLDVFS,
        PMUX_FUNC_RESET_OUT_N,
+       /* End of Tegra114 MUX selectors */
 
        PMUX_FUNC_SAFE,
        PMUX_FUNC_MAX,
 
+       PMUX_FUNC_INVALID = 0x4000,
        PMUX_FUNC_RSVD1 = 0x8000,
        PMUX_FUNC_RSVD2 = 0x8001,
        PMUX_FUNC_RSVD3 = 0x8002,
@@ -492,6 +406,7 @@ enum pmux_tristate {
 enum pmux_pin_io {
        PMUX_PIN_OUTPUT = 0,
        PMUX_PIN_INPUT = 1,
+       PMUX_PIN_NONE,
 };
 /* return 1 if a pin_io_is in range */
 #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
@@ -525,6 +440,16 @@ enum pmux_pin_ioreset {
                                (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
                                ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
 
+enum pmux_pin_rcv_sel {
+       PMUX_PIN_RCV_SEL_DEFAULT = 0,
+       PMUX_PIN_RCV_SEL_NORMAL,
+       PMUX_PIN_RCV_SEL_HIGH,
+};
+/* return 1 if a pin_rcv_sel_is in range */
+#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
+                               (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
+                               ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
+
 /* Available power domains used by pin groups */
 enum pmux_vddio {
        PMUX_VDDIO_BB = 0,
@@ -546,10 +471,73 @@ enum pmux_vddio {
        PMUX_VDDIO_NONE
 };
 
-/* T114 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET  (0x868 >> 2)
-#define PMUX_OFFSET     ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
-                       PDRIVE_PINGROUP_COUNT)
+#define PGRP_SLWF_NONE -1
+#define PGRP_SLWF_MAX  3
+#define PGRP_SLWR_NONE PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX  PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE        -1
+#define PGRP_DRVUP_MAX 127
+#define PGRP_DRVDN_NONE        PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
+
+#define PGRP_SCHMT_NONE        -1
+#define PGRP_HSM_NONE  PGRP_SCHMT_NONE
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
+                               (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
+                               (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
+                               (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+       PGRP_LPMD_X8 = 0,
+       PGRP_LPMD_X4,
+       PGRP_LPMD_X2,
+       PGRP_LPMD_X,
+       PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+       PGRP_SCHMT_DISABLE = 0,
+       PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+       PGRP_HSM_DISABLE = 0,
+       PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+       enum pdrive_pingrp padgrp;      /* pin group PDRIVE_PINGRP_x */
+       int slwf;                       /* falling edge slew         */
+       int slwr;                       /* rising edge slew          */
+       int drvup;                      /* pull-up drive strength    */
+       int drvdn;                      /* pull-down drive strength  */
+       enum pgrp_lpmd lpmd;            /* low-power mode selection  */
+       enum pgrp_schmt schmt;          /* schmidt enable            */
+       enum pgrp_hsm hsm;              /* high-speed mode enable    */
+};
+
+/* t114 pin drive group and pin mux registers */
+#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
+#define PMUX_OFFSET    ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
+                               PDRIVE_PINGROUP_COUNT)
 struct pmux_tri_ctlr {
        uint pmt_reserved0;             /* ABP_MISC_PP_ reserved offset 00 */
        uint pmt_reserved1;             /* ABP_MISC_PP_ reserved offset 04 */
@@ -581,6 +569,8 @@ struct pingroup_config {
        enum pmux_pin_lock lock;        /* lock enable/disable PMUX_PIN...  */
        enum pmux_pin_od od;            /* open-drain or push-pull driver  */
        enum pmux_pin_ioreset ioreset;  /* input/output reset PMUX_PIN...  */
+       enum pmux_pin_rcv_sel rcv_sel;  /* select between High and Normal  */
+                                       /* VIL/VIH receivers */
 };
 
 /* Set a pin group to tristate */
@@ -615,4 +605,12 @@ void pinmux_config_table(struct pingroup_config *config, int len);
 /* Set a group of pins from a table */
 void pinmux_init(void);
 
-#endif  /* _TEGRA114_PINMUX_H_ */
+/**
+ * Set the GP pad configs
+ *
+ * @param config       List of config items
+ * @param len          Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
+#endif /* _TEGRA114_PINMUX_H_ */
index e1de044..ad5c01d 100644 (file)
@@ -29,7 +29,6 @@
 #include <asm/arch-tegra/tegra.h>
 
 #define TEGRA_USB1_BASE                0xC5000000
-#define TEGRA_USB3_BASE                0xC5008000
 
 #define BCT_ODMDATA_OFFSET     4068    /* 12 bytes from end of BCT */
 
index 9b383d0..23d184f 100644 (file)
@@ -56,4 +56,10 @@ struct apb_misc_gp_ctlr {
        u32     sdio1cfg;       /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
 };
 
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define SDIOCFG_DRVUP_SLWF     1
+#define SDIOCFG_DRVDN_SLWR     1
+#define SDIOCFG_DRVUP          0x2E
+#define SDIOCFG_DRVDN          0x2A
+
 #endif /* _TEGRA30_GP_PADCTRL_H_ */
index 341951b..a9e1b46 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -531,6 +531,63 @@ enum pmux_vddio {
        PMUX_VDDIO_NONE
 };
 
+#define PGRP_SLWF_NONE -1
+#define PGRP_SLWF_MAX  3
+#define        PGRP_SLWR_NONE  PGRP_SLWF_NONE
+#define PGRP_SLWR_MAX  PGRP_SLWF_MAX
+
+#define PGRP_DRVUP_NONE        -1
+#define PGRP_DRVUP_MAX 127
+#define        PGRP_DRVDN_NONE PGRP_DRVUP_NONE
+#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
+
+/* return 1 if a padgrp is in range */
+#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
+
+/* return 1 if a slew-rate rising/falling edge value is in range */
+#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))
+
+/* return 1 if a driver output pull-up/down strength code value is in range */
+#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))
+
+/* return 1 if a low-power mode value is in range */
+#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))
+
+/* Defines a pin group cfg's low-power mode select */
+enum pgrp_lpmd {
+       PGRP_LPMD_X8 = 0,
+       PGRP_LPMD_X4,
+       PGRP_LPMD_X2,
+       PGRP_LPMD_X,
+       PGRP_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pgrp_schmt {
+       PGRP_SCHMT_DISABLE = 0,
+       PGRP_SCHMT_ENABLE = 1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pgrp_hsm {
+       PGRP_HSM_DISABLE = 0,
+       PGRP_HSM_ENABLE = 1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct padctrl_config {
+       enum pdrive_pingrp padgrp;      /* pin group PDRIVE_PINGRP_x */
+       int slwf;                       /* falling edge slew         */
+       int slwr;                       /* rising edge slew          */
+       int drvup;                      /* pull-up drive strength    */
+       int drvdn;                      /* pull-down drive strength  */
+       enum pgrp_lpmd lpmd;            /* low-power mode selection  */
+       enum pgrp_schmt schmt;          /* schmidt enable            */
+       enum pgrp_hsm hsm;              /* high-speed mode enable    */
+};
+
 /* t30 pin drive group and pin mux registers */
 #define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
 #define PMUX_OFFSET    ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
@@ -600,4 +657,12 @@ void pinmux_config_table(struct pingroup_config *config, int len);
 /* Set a group of pins from a table */
 void pinmux_init(void);
 
+/**
+ * Set the GP pad configs
+ *
+ * @param config       List of config items
+ * @param len          Number of config items in list
+ */
+void padgrp_config_table(struct padctrl_config *config, int len);
+
 #endif /* _TEGRA30_PINMUX_H_ */
index decf564..c02c5d8 100644 (file)
@@ -21,6 +21,8 @@
 
 #include <asm/arch-tegra/tegra.h>
 
+#define TEGRA_USB1_BASE                0x7D000000
+
 #define BCT_ODMDATA_OFFSET     6116    /* 12 bytes from end of BCT */
 
 #define MAX_NUM_CPU            4
index e6a932e..ea95e43 100644 (file)
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
 #include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/arch-tegra/sys_proto.h>
 #include <asm/arch-tegra/uart.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)
@@ -54,7 +49,7 @@ void gpio_early_init(void)
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
        funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
        /* for write-protect GPIO PI6 */
@@ -62,16 +57,4 @@ static void pin_mux_mmc(void)
        /* for CD GPIO PH2 */
        pinmux_tristate_disable(PINGRP_ATD);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-       /* Enable muxes, etc. for SDMMC controllers */
-       pin_mux_mmc();
-
-       /* init dev 0, SD slot, with 4-bit bus */
-       tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
-
-       return 0;
-}
 #endif
index e46afbe..a9a07f9 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20-tamonten.dtsi"
 
 / {
        model = "Avionic Design Medcom-Wide";
@@ -8,6 +8,7 @@
 
        aliases {
                usb0 = "/usb@c5008000";
+               sdhci0 = "/sdhci@c8000600";
        };
 
        memory {
index 3e6cce0..20016f2 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20-tamonten.dtsi"
 
 / {
        model = "Avionic Design Plutux";
@@ -8,6 +8,7 @@
 
        aliases {
                usb0 = "/usb@c5008000";
+               sdhci0 = "/sdhci@c8000600";
        };
 
        memory {
diff --git a/board/avionic-design/dts/tegra20-tamonten.dtsi b/board/avionic-design/dts/tegra20-tamonten.dtsi
new file mode 100644 (file)
index 0000000..86c7bab
--- /dev/null
@@ -0,0 +1,489 @@
+#include "tegra20.dtsi"
+
+/ {
+       model = "Avionic Design Tamonten SOM";
+       compatible = "ad,tamonten", "nvidia,tegra20";
+
+       memory {
+               reg = <0x00000000 0x20000000>;
+       };
+
+       host1x {
+               hdmi {
+                       vdd-supply = <&hdmi_vdd_reg>;
+                       pll-supply = <&hdmi_pll_reg>;
+
+                       nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                       nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+               };
+       };
+
+       pinmux {
+               pinctrl-names = "default";
+               pinctrl-0 = <&state_default>;
+
+               state_default: pinmux {
+                       ata {
+                               nvidia,pins = "ata";
+                               nvidia,function = "ide";
+                       };
+                       atb {
+                               nvidia,pins = "atb", "gma", "gme";
+                               nvidia,function = "sdio4";
+                       };
+                       atc {
+                               nvidia,pins = "atc";
+                               nvidia,function = "nand";
+                       };
+                       atd {
+                               nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+                                       "spia", "spib", "spic";
+                               nvidia,function = "gmi";
+                       };
+                       cdev1 {
+                               nvidia,pins = "cdev1";
+                               nvidia,function = "plla_out";
+                       };
+                       cdev2 {
+                               nvidia,pins = "cdev2";
+                               nvidia,function = "pllp_out4";
+                       };
+                       crtp {
+                               nvidia,pins = "crtp";
+                               nvidia,function = "crt";
+                       };
+                       csus {
+                               nvidia,pins = "csus";
+                               nvidia,function = "vi_sensor_clk";
+                       };
+                       dap1 {
+                               nvidia,pins = "dap1";
+                               nvidia,function = "dap1";
+                       };
+                       dap2 {
+                               nvidia,pins = "dap2";
+                               nvidia,function = "dap2";
+                       };
+                       dap3 {
+                               nvidia,pins = "dap3";
+                               nvidia,function = "dap3";
+                       };
+                       dap4 {
+                               nvidia,pins = "dap4";
+                               nvidia,function = "dap4";
+                       };
+                       dta {
+                               nvidia,pins = "dta", "dtd";
+                               nvidia,function = "sdio2";
+                       };
+                       dtb {
+                               nvidia,pins = "dtb", "dtc", "dte";
+                               nvidia,function = "rsvd1";
+                       };
+                       dtf {
+                               nvidia,pins = "dtf";
+                               nvidia,function = "i2c3";
+                       };
+                       gmc {
+                               nvidia,pins = "gmc";
+                               nvidia,function = "uartd";
+                       };
+                       gpu7 {
+                               nvidia,pins = "gpu7";
+                               nvidia,function = "rtck";
+                       };
+                       gpv {
+                               nvidia,pins = "gpv", "slxa", "slxk";
+                               nvidia,function = "pcie";
+                       };
+                       hdint {
+                               nvidia,pins = "hdint";
+                               nvidia,function = "hdmi";
+                       };
+                       i2cp {
+                               nvidia,pins = "i2cp";
+                               nvidia,function = "i2cp";
+                       };
+                       irrx {
+                               nvidia,pins = "irrx", "irtx";
+                               nvidia,function = "uarta";
+                       };
+                       kbca {
+                               nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                       "kbce", "kbcf";
+                               nvidia,function = "kbc";
+                       };
+                       lcsn {
+                               nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                       "ld3", "ld4", "ld5", "ld6", "ld7",
+                                       "ld8", "ld9", "ld10", "ld11", "ld12",
+                                       "ld13", "ld14", "ld15", "ld16", "ld17",
+                                       "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                       "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                       "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                       "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                       "lvs";
+                               nvidia,function = "displaya";
+                       };
+                       owc {
+                               nvidia,pins = "owc", "spdi", "spdo", "uac";
+                               nvidia,function = "rsvd2";
+                       };
+                       pmc {
+                               nvidia,pins = "pmc";
+                               nvidia,function = "pwr_on";
+                       };
+                       rm {
+                               nvidia,pins = "rm";
+                               nvidia,function = "i2c1";
+                       };
+                       sdb {
+                               nvidia,pins = "sdb", "sdc", "sdd";
+                               nvidia,function = "pwm";
+                       };
+                       sdio1 {
+                               nvidia,pins = "sdio1";
+                               nvidia,function = "sdio1";
+                       };
+                       slxc {
+                               nvidia,pins = "slxc", "slxd";
+                               nvidia,function = "spdif";
+                       };
+                       spid {
+                               nvidia,pins = "spid", "spie", "spif";
+                               nvidia,function = "spi1";
+                       };
+                       spig {
+                               nvidia,pins = "spig", "spih";
+                               nvidia,function = "spi2_alt";
+                       };
+                       uaa {
+                               nvidia,pins = "uaa", "uab", "uda";
+                               nvidia,function = "ulpi";
+                       };
+                       uad {
+                               nvidia,pins = "uad";
+                               nvidia,function = "irda";
+                       };
+                       uca {
+                               nvidia,pins = "uca", "ucb";
+                               nvidia,function = "uartc";
+                       };
+                       conf_ata {
+                               nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                       "cdev1", "cdev2", "dap1", "dtb", "gma",
+                                       "gmb", "gmc", "gmd", "gme", "gpu7",
+                                       "gpv", "i2cp", "pta", "rm", "slxa",
+                                       "slxk", "spia", "spib", "uac";
+                               nvidia,pull = <0>;
+                               nvidia,tristate = <0>;
+                       };
+                       conf_ck32 {
+                               nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                       "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                               nvidia,pull = <0>;
+                       };
+                       conf_csus {
+                               nvidia,pins = "csus", "spid", "spif";
+                               nvidia,pull = <1>;
+                               nvidia,tristate = <1>;
+                       };
+                       conf_crtp {
+                               nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+                                       "dtc", "dte", "dtf", "gpu", "sdio1",
+                                       "slxc", "slxd", "spdi", "spdo", "spig",
+                                       "uda";
+                               nvidia,pull = <0>;
+                               nvidia,tristate = <1>;
+                       };
+                       conf_ddc {
+                               nvidia,pins = "ddc", "dta", "dtd", "kbca",
+                                       "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                       "sdc";
+                               nvidia,pull = <2>;
+                               nvidia,tristate = <0>;
+                       };
+                       conf_hdint {
+                               nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                       "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                       "lvp0", "owc", "sdb";
+                               nvidia,tristate = <1>;
+                       };
+                       conf_irrx {
+                               nvidia,pins = "irrx", "irtx", "sdd", "spic",
+                                       "spie", "spih", "uaa", "uab", "uad",
+                                       "uca", "ucb";
+                               nvidia,pull = <2>;
+                               nvidia,tristate = <1>;
+                       };
+                       conf_lc {
+                               nvidia,pins = "lc", "ls";
+                               nvidia,pull = <2>;
+                       };
+                       conf_ld0 {
+                               nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                       "ld5", "ld6", "ld7", "ld8", "ld9",
+                                       "ld10", "ld11", "ld12", "ld13", "ld14",
+                                       "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                       "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                       "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                       "lvs", "pmc";
+                               nvidia,tristate = <0>;
+                       };
+                       conf_ld17_0 {
+                               nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                       "ld23_22";
+                               nvidia,pull = <1>;
+                       };
+               };
+
+               state_i2cmux_ddc: pinmux_i2cmux_ddc {
+                       ddc {
+                               nvidia,pins = "ddc";
+                               nvidia,function = "i2c2";
+                       };
+                       pta {
+                               nvidia,pins = "pta";
+                               nvidia,function = "rsvd4";
+                       };
+               };
+
+               state_i2cmux_pta: pinmux_i2cmux_pta {
+                       ddc {
+                               nvidia,pins = "ddc";
+                               nvidia,function = "rsvd4";
+                       };
+                       pta {
+                               nvidia,pins = "pta";
+                               nvidia,function = "i2c2";
+                       };
+               };
+
+               state_i2cmux_idle: pinmux_i2cmux_idle {
+                       ddc {
+                               nvidia,pins = "ddc";
+                               nvidia,function = "rsvd4";
+                       };
+                       pta {
+                               nvidia,pins = "pta";
+                               nvidia,function = "rsvd4";
+                       };
+               };
+       };
+
+       i2s@70002800 {
+               status = "okay";
+       };
+
+       serial@70006300 {
+               status = "okay";
+       };
+
+       i2c@7000c000 {
+               clock-frequency = <400000>;
+               status = "okay";
+       };
+
+       i2c@7000c400 {
+               clock-frequency = <100000>;
+               status = "okay";
+       };
+
+       i2cmux {
+               compatible = "i2c-mux-pinctrl";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               i2c-parent = <&{/i2c@7000c400}>;
+
+               pinctrl-names = "ddc", "pta", "idle";
+               pinctrl-0 = <&state_i2cmux_ddc>;
+               pinctrl-1 = <&state_i2cmux_pta>;
+               pinctrl-2 = <&state_i2cmux_idle>;
+
+               hdmi_ddc: i2c@0 {
+                       reg = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               i2c@1 {
+                       reg = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+
+       i2c@7000d000 {
+               clock-frequency = <400000>;
+               status = "okay";
+
+               pmic: tps6586x@34 {
+                       compatible = "ti,tps6586x";
+                       reg = <0x34>;
+                       interrupts = <0 86 0x4>;
+
+                       ti,system-power-controller;
+
+                       #gpio-cells = <2>;
+                       gpio-controller;
+
+                       sys-supply = <&vdd_5v0_reg>;
+                       vin-sm0-supply = <&sys_reg>;
+                       vin-sm1-supply = <&sys_reg>;
+                       vin-sm2-supply = <&sys_reg>;
+                       vinldo01-supply = <&sm2_reg>;
+                       vinldo23-supply = <&sm2_reg>;
+                       vinldo4-supply = <&sm2_reg>;
+                       vinldo678-supply = <&sm2_reg>;
+                       vinldo9-supply = <&sm2_reg>;
+
+                       regulators {
+                               sys_reg: sys {
+                                       regulator-name = "vdd_sys";
+                                       regulator-always-on;
+                               };
+
+                               sm0 {
+                                       regulator-name = "vdd_sys_sm0,vdd_core";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                                       regulator-always-on;
+                               };
+
+                               sm1 {
+                                       regulator-name = "vdd_sys_sm1,vdd_cpu";
+                                       regulator-min-microvolt = <1000000>;
+                                       regulator-max-microvolt = <1000000>;
+                                       regulator-always-on;
+                               };
+
+                               sm2_reg: sm2 {
+                                       regulator-name = "vdd_sys_sm2,vin_ldo*";
+                                       regulator-min-microvolt = <3700000>;
+                                       regulator-max-microvolt = <3700000>;
+                                       regulator-always-on;
+                               };
+
+                               ldo0 {
+                                       regulator-name = "vdd_ldo0,vddio_pex_clk";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                               };
+
+                               ldo1 {
+                                       regulator-name = "vdd_ldo1,avdd_pll*";
+                                       regulator-min-microvolt = <1100000>;
+                                       regulator-max-microvolt = <1100000>;
+                                       regulator-always-on;
+                               };
+
+                               ldo2 {
+                                       regulator-name = "vdd_ldo2,vdd_rtc";
+                                       regulator-min-microvolt = <1200000>;
+                                       regulator-max-microvolt = <1200000>;
+                               };
+
+                               ldo3 {
+                                       regulator-name = "vdd_ldo3,avdd_usb*";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-always-on;
+                               };
+
+                               ldo4 {
+                                       regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                                       regulator-always-on;
+                               };
+
+                               ldo5 {
+                                       regulator-name = "vdd_ldo5,vcore_mmc";
+                                       regulator-min-microvolt = <2850000>;
+                                       regulator-max-microvolt = <2850000>;
+                               };
+
+                               ldo6 {
+                                       regulator-name = "vdd_ldo6,avdd_vdac";
+                                       /*
+                                        * According to the Tegra 2 Automotive
+                                        * DataSheet, a typical value for this
+                                        * would be 2.8V, but the PMIC only
+                                        * supports 2.85V.
+                                        */
+                                       regulator-min-microvolt = <2850000>;
+                                       regulator-max-microvolt = <2850000>;
+                               };
+
+                               hdmi_vdd_reg: ldo7 {
+                                       regulator-name = "vdd_ldo7,avdd_hdmi";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                               };
+
+                               hdmi_pll_reg: ldo8 {
+                                       regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                       regulator-min-microvolt = <1800000>;
+                                       regulator-max-microvolt = <1800000>;
+                               };
+
+                               ldo9 {
+                                       regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+                                       /*
+                                        * According to the Tegra 2 Automotive
+                                        * DataSheet, a typical value for this
+                                        * would be 2.8V, but the PMIC only
+                                        * supports 2.85V.
+                                        */
+                                       regulator-min-microvolt = <2850000>;
+                                       regulator-max-microvolt = <2850000>;
+                                       regulator-always-on;
+                               };
+
+                               ldo_rtc {
+                                       regulator-name = "vdd_rtc_out";
+                                       regulator-min-microvolt = <3300000>;
+                                       regulator-max-microvolt = <3300000>;
+                                       regulator-always-on;
+                               };
+                       };
+               };
+
+               temperature-sensor@4c {
+                       compatible = "onnn,nct1008";
+                       reg = <0x4c>;
+               };
+       };
+
+       pmc {
+               nvidia,invert-interrupt;
+       };
+
+       usb@c5008000 {
+               status = "okay";
+       };
+
+       sdhci@c8000600 {
+               cd-gpios = <&gpio 58 1>; /* gpio PH2 */
+               wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+               bus-width = <4>;
+               status = "okay";
+       };
+
+       regulators {
+               compatible = "simple-bus";
+
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               vdd_5v0_reg: regulator@0 {
+                       compatible = "regulator-fixed";
+                       reg = <0>;
+                       regulator-name = "vdd_5v0";
+                       regulator-min-microvolt = <5000000>;
+                       regulator-max-microvolt = <5000000>;
+                       regulator-always-on;
+               };
+       };
+};
index bf3ff1d..1d7cf89 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20-tamonten.dtsi"
 
 / {
        model = "Avionic Design Tamonten Evaluation Carrier";
@@ -8,6 +8,7 @@
 
        aliases {
                usb0 = "/usb@c5008000";
+               sdhci0 = "/sdhci@c8000600";
        };
 
        memory {
index 31b064d..780203c 100644 (file)
@@ -1,13 +1,15 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20.dtsi"
 
 / {
-        model = "Toshiba AC100 / Dynabook AZ";
-        compatible = "compal,paz00", "nvidia,tegra20";
+       model = "Toshiba AC100 / Dynabook AZ";
+       compatible = "compal,paz00", "nvidia,tegra20";
 
        aliases {
                usb0 = "/usb@c5008000";
+               sdhci0 = "/sdhci@c8000600";
+               sdhci1 = "/sdhci@c8000000";
        };
 
        memory {
                status = "disabled";
        };
 
+       sdhci@c8000000 {
+               status = "okay";
+               cd-gpios = <&gpio 173 1>; /* gpio PV5 */
+               wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+               power-gpios = <&gpio 169 0>; /* gpio PV1 */
+               bus-width = <4>;
+       };
+
+       sdhci@c8000600 {
+               status = "okay";
+               bus-width = <8>;
+       };
+
        lcd_panel: panel {
                /* PAZ00 has 1024x600 */
                clock = <54030000>;
index 1447f47..d6e5c37 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
 #ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
        /* SDMMC4: config 3, x8 on 2nd set of pins */
        pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
@@ -51,25 +46,6 @@ static void pin_mux_mmc(void)
        /* For CD GPIO PV5 */
        pinmux_tristate_disable(PINGRP_GPV);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-       debug("board_mmc_init called\n");
-
-       /* Enable muxes, etc. for SDMMC controllers */
-       pin_mux_mmc();
-
-       debug("board_mmc_init: init eMMC\n");
-       /* init dev 0, eMMC chip, with 8-bit bus */
-       tegra_mmc_init(0, 8, -1, -1);
-
-       debug("board_mmc_init: init SD slot\n");
-       /* init dev 3, SD slot, with 4-bit bus */
-       tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
-
-       return 0;
-}
 #endif
 
 #ifdef CONFIG_LCD
index 7aeed67..ee31476 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20.dtsi"
 
 / {
        model = "Compulab TrimSlice board";
@@ -9,6 +9,8 @@
        aliases {
                usb0 = "/usb@c5008000";
                usb1 = "/usb@c5000000";
+               sdhci0 = "/sdhci@c8000600";
+               sdhci1 = "/sdhci@c8000000";
        };
 
        memory {
        usb@c5004000 {
                status = "disabled";
        };
+
+       sdhci@c8000000 {
+               status = "okay";
+               bus-width = <4>;
+       };
+
+       sdhci@c8000600 {
+               status = "okay";
+               cd-gpios = <&gpio 121 1>; /* gpio PP1 */
+               wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+               bus-width = <4>;
+       };
 };
index 8f4dd09..8401100 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
 #include <i2c.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
 
 void pin_mux_usb(void)
 {
@@ -52,7 +48,7 @@ void pin_mux_spi(void)
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
        funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT);
        funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
@@ -60,20 +56,3 @@ static void pin_mux_mmc(void)
        /* For CD GPIO PP1 */
        pinmux_tristate_disable(PINGRP_DAP3);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-       debug("board_mmc_init called\n");
-
-       /* Enable muxes, etc. for SDMMC controllers */
-       pin_mux_mmc();
-
-       /* init dev 0 (SDMMC4), (micro-SD slot) with 4-bit bus */
-       tegra_mmc_init(0, 4, -1, GPIO_PP1);
-
-       /* init dev 3 (SDMMC1), (SD slot) with 4-bit bus */
-       tegra_mmc_init(3, 4, -1, -1);
-
-       return 0;
-}
index df4cb6b..3544b41 100644 (file)
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010-2012
+ *  (C) Copyright 2010-2013
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * See file CREDITS for list of people who contributed to this
 
 #include <common.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
 #include "pinmux-config-cardhu.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS                0x2D
+#define MAX_I2C_RETRY          3
 
 /*
  * Routine: pinmux_init
@@ -36,4 +41,54 @@ void pinmux_init(void)
 
        pinmux_config_table(unused_pins_lowpower,
                ARRAY_SIZE(unused_pins_lowpower));
+
+       /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+       padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
+}
+
+#if defined(CONFIG_TEGRA_MMC)
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+       uchar reg, data_buffer[1];
+       int i;
+
+       i2c_set_bus_num(0);     /* PMU is on bus 0 */
+
+       /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
+       data_buffer[0] = 0x65;
+       reg = 0x32;
+
+       for (i = 0; i < MAX_I2C_RETRY; ++i) {
+               if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                       udelay(100);
+       }
+
+       /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */
+       data_buffer[0] = 0x09;
+       reg = 0x67;
+
+       for (i = 0; i < MAX_I2C_RETRY; ++i) {
+               if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
+                       udelay(100);
+       }
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+       /*
+        * NOTE: We don't do mmc-specific pin muxes here.
+        * They were done globally in pinmux_init().
+        */
+
+       /* Bring up the SDIO1 power rail */
+       board_sdmmc_voltage_init();
 }
+#endif /* MMC */
diff --git a/board/nvidia/cardhu/cardhu.c.mmc b/board/nvidia/cardhu/cardhu.c.mmc
deleted file mode 100644 (file)
index 9e83b6f..0000000
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- *  (C) Copyright 2010-2012
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-#include "pinmux-config-cardhu.h"
-
-#include <asm/arch/clock.h>
-#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pmu.h>
-#include <asm/arch/sdmmc.h>
-#include <asm/arch-tegra/mmc.h>
-#include <asm/arch-tegra/tegra_mmc.h>
-#include <mmc.h>
-#include <i2c.h>
-
-/*
- * Routine: pinmux_init
- * Description: Do individual peripheral pinmux configs
- */
-void pinmux_init(void)
-{
-       pinmux_config_table(tegra3_pinmux_common,
-               ARRAY_SIZE(tegra3_pinmux_common));
-
-       pinmux_config_table(unused_pins_lowpower,
-               ARRAY_SIZE(unused_pins_lowpower));
-}
-
-#if defined(CONFIG_MMC)
-/*
- * Routine: pin_mux_mmc
- * Description: setup the pin muxes/tristate values for the SDMMC(s)
- */
-static void pin_mux_mmc(void)
-{
-}
-
-/* Do I2C/PMU writes to bring up SD card bus power */
-static void board_sdmmc_voltage_init(void)
-{
-        uchar reg, data_buffer[1];
-        int i;
-
-        i2c_set_bus_num(0);             /* PMU is on bus 0 */
-
-        data_buffer[0] = 0x65;
-        reg = 0x32;
-
-        for (i = 0; i < MAX_I2C_RETRY; ++i) {
-                if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
-                        udelay(100);
-        }
-
-        data_buffer[0] = 0x09;
-        reg = 0x67;
-
-        for (i = 0; i < MAX_I2C_RETRY; ++i) {
-                if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
-                        udelay(100);
-        }
-}
-
-static void pad_init_mmc(struct tegra_mmc *reg)
-{
-        struct apb_misc_gp_ctlr *const gpc =
-                (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
-        struct sdmmc_ctlr *const sdmmc = (struct sdmmc_ctlr *)reg;
-        u32 val, offset = (unsigned int)reg;
-        u32 padcfg, padmask;
-
-        debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)sdmmc);
-
-        /* Set the pad drive strength for SDMMC1 or 3 only */
-        if (offset != TEGRA_SDMMC1_BASE && offset != TEGRA_SDMMC3_BASE) {
-                debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
-                        __func__);
-                return;
-        }
-
-        /* Set pads as per T30 TRM, section 24.6.1.2 */
-        padcfg = (GP_SDIOCFG_DRVUP_SLWF | GP_SDIOCFG_DRVDN_SLWR | \
-                GP_SDIOCFG_DRVUP | GP_SDIOCFG_DRVDN);
-        padmask = 0x00000FFF;
-        if (offset == TEGRA_SDMMC1_BASE) {
-                val = readl(&gpc->sdio1cfg);
-                val &= padmask;
-                val |= padcfg;
-                writel(val, &gpc->sdio1cfg);
-        } else {                                /* SDMMC3 */
-                val = readl(&gpc->sdio3cfg);
-                val &= padmask;
-                val |= padcfg;
-                writel(val, &gpc->sdio3cfg);
-        }
-
-        val = readl(&sdmmc->sdmmc_sdmemcomp_pad_ctrl);
-        val &= 0xFFFFFFF0;
-        val |= MEMCOMP_PADCTRL_VREF;
-        writel(val, &sdmmc->sdmmc_sdmemcomp_pad_ctrl);
-
-        val = readl(&sdmmc->sdmmc_auto_cal_config);
-        val &= 0xFFFF0000;
-        val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
-        writel(val, &sdmmc->sdmmc_auto_cal_config);
-}
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-       debug("board_mmc_init called\n");
-
-       /* Turn on SD-card bus power */
-       board_sdmmc_voltage_init();
-
-       /* Set up the SDMMC pads as per the TRM */
-       pad_init_mmc((struct tegra_mmc *)TEGRA_SDMMC1_BASE);
-
-       /* Enable muxes, etc. for SDMMC controllers */
-       pin_mux_mmc();
-
-       /* init dev 0 (SDMMC4), ("HSMMC") with 8-bit bus */
-       tegra_mmc_init(0, 8, -1, -1);
-
-       /* init dev 1 (SDMMC0), ("SDIO") with 8-bit bus */
-       tegra_mmc_init(1, 8, -1, -1);
-
-       return 0;
-}
-#endif /* MMC */
index 8428bba..51d2b94 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
                .ioreset        = PMUX_PIN_IO_RESET_##_ioreset  \
        }
 
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+       {                                                       \
+               .padgrp         = PDRIVE_PINGROUP_##_padgrp,    \
+               .slwf           = _slwf,                        \
+               .slwr           = _slwr,                        \
+               .drvup          = _drvup,                       \
+               .drvdn          = _drvdn,                       \
+               .lpmd           = PGRP_LPMD_##_lpmd,            \
+               .schmt          = PGRP_SCHMT_##_schmt,          \
+               .hsm            = PGRP_HSM_##_hsm,              \
+       }
+
 static struct pingroup_config tegra3_pinmux_common[] = {
        /* SDMMC1 pinmux */
        DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
@@ -326,4 +338,9 @@ static struct pingroup_config unused_pins_lowpower[] = {
        DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
 };
 
-#endif /* _PINMUX_CONFIG_CARDHU_H_ */
+static struct padctrl_config cardhu_padctrl[] = {
+       /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+       DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
+               SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_CARDHU_H_ */
index d1d8a29..7d9f361 100644 (file)
 #include <asm/arch/emc.h>
 #endif
 #ifdef CONFIG_USB_EHCI_TEGRA
-#include <asm/arch/usb.h>
+#include <asm/arch-tegra/usb.h>
+#endif
+#ifdef CONFIG_TEGRA_MMC
+#include <asm/arch-tegra/tegra_mmc.h>
+#include <asm/arch-tegra/mmc.h>
 #endif
 #include <i2c.h>
 #include <spi.h>
@@ -221,3 +225,53 @@ int board_late_init(void)
 #endif
        return 0;
 }
+
+#if defined(CONFIG_TEGRA_MMC)
+void __pin_mux_mmc(void)
+{
+}
+
+void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc")));
+
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+       debug("%s called\n", __func__);
+
+       /* Enable muxes, etc. for SDMMC controllers */
+       pin_mux_mmc();
+
+       debug("%s: init MMC\n", __func__);
+       tegra_mmc_init();
+
+       return 0;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+#if defined(CONFIG_TEGRA30)
+       enum periph_id id = host->mmc_id;
+       u32 val;
+
+       debug("%s: sdmmc address = %08x, id = %d\n", __func__,
+               (unsigned int)host->reg, id);
+
+       /* Set the pad drive strength for SDMMC1 or 3 only */
+       if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
+               debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
+                       __func__);
+               return;
+       }
+
+       val = readl(&host->reg->sdmemcmppadctl);
+       val &= 0xFFFFFFF0;
+       val |= MEMCOMP_PADCTRL_VREF;
+       writel(val, &host->reg->sdmemcmppadctl);
+
+       val = readl(&host->reg->autocalcfg);
+       val &= 0xFFFF0000;
+       val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
+       writel(val, &host->reg->autocalcfg);
+#endif /* T30 */
+}
+#endif /* MMC */
index aca3c7d..2020a5f 100644 (file)
@@ -24,6 +24,9 @@
  */
 void pinmux_init(void)
 {
+       pinmux_config_table(tegra114_pinmux_set_nontristate,
+               ARRAY_SIZE(tegra114_pinmux_set_nontristate));
+
        pinmux_config_table(tegra114_pinmux_common,
                ARRAY_SIZE(tegra114_pinmux_common));
 
index 3dd47da..3ef6f4e 100644 (file)
@@ -17,7 +17,7 @@
 #ifndef _PINMUX_CONFIG_DALMORE_H_
 #define _PINMUX_CONFIG_DALMORE_H_
 
-#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)   \
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)      \
        {                                                       \
                .pingroup       = PINGRP_##_pingroup,           \
                .func           = PMUX_FUNC_##_mux,             \
                .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
        }
 
-#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
+       {                                                       \
+               .pingroup       = PINGRP_##_pingroup,           \
+               .func           = PMUX_FUNC_##_mux,             \
+               .pull           = PMUX_PULL_##_pull,            \
+               .tristate       = PMUX_TRI_##_tri,              \
+               .io             = PMUX_PIN_##_io,               \
+               .lock           = PMUX_PIN_LOCK_##_lock,        \
+               .rcv_sel        = PMUX_PIN_RCV_SEL_##_rcv_sel,  \
+               .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
+       }
+
+#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
        {                                                       \
                .pingroup       = PINGRP_##_pingroup,           \
                .func           = PMUX_FUNC_##_mux,             \
                .io             = PMUX_PIN_##_io,               \
                .lock           = PMUX_PIN_LOCK_##_lock,        \
                .od             = PMUX_PIN_OD_DEFAULT,          \
-               .ioreset        = PMUX_PIN_IO_RESET_##_ioreset  \
+               .ioreset        = PMUX_PIN_IO_RESET_##_ioreset  \
+       }
+
+#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od)      \
+       {                                                               \
+               .pingroup   = PINGRP_##_pingroup,                       \
+               .func       = PMUX_FUNC_##_mux,                         \
+               .pull       = PMUX_PULL_##_pull,                        \
+               .tristate   = PMUX_TRI_##_tri,                          \
+               .io         = PMUX_PIN_##_io,                           \
+               .lock       = PMUX_PIN_LOCK_##_lock,                    \
+               .od         = PMUX_PIN_OD_##_od,                        \
+               .ioreset    = PMUX_PIN_IO_RESET_DEFAULT,                \
+       }
+
+#define USB_PINMUX CEC_PINMUX
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+       {                                               \
+               .padgrp = PDRIVE_PINGROUP_##_padgrp,    \
+               .slwf   = _slwf,                        \
+               .slwr   = _slwr,                        \
+               .drvup  = _drvup,                       \
+               .drvdn  = _drvdn,                       \
+               .lpmd   = PGRP_LPMD_##_lpmd,            \
+               .schmt  = PGRP_SCHMT_##_schmt,          \
+               .hsm    = PGRP_HSM_##_hsm,              \
        }
 
 static struct pingroup_config tegra114_pinmux_common[] = {
+       /* EXTPERIPH1 pinmux */
+       DEFAULT_PINMUX(CLK1_OUT,      EXTPERIPH1,  NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2S0 pinmux */
+       DEFAULT_PINMUX(DAP1_DIN,      I2S0,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,     I2S0,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP1_FS,       I2S0,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,     I2S0,        NORMAL,    NORMAL,   INPUT),
+
+       /* I2S1 pinmux */
+       DEFAULT_PINMUX(DAP2_DIN,      I2S1,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,     I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_FS,       I2S1,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,     I2S1,        NORMAL,    NORMAL,   INPUT),
+
+       /* I2S3 pinmux */
+       DEFAULT_PINMUX(DAP4_DIN,      I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,     I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_FS,       I2S3,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,     I2S3,        NORMAL,    NORMAL,   INPUT),
+
+       /* CLDVFS pinmux */
+       DEFAULT_PINMUX(DVFS_PWM,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(DVFS_CLK,      CLDVFS,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* ULPI pinmux */
+       DEFAULT_PINMUX(ULPI_CLK,      ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA0,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA1,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA2,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA3,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA4,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA5,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA6,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DATA7,    ULPI,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(ULPI_DIR,      ULPI,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(ULPI_NXT,      ULPI,        NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(ULPI_STP,      ULPI,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+       /* VI pinmux */
+       VI_PINMUX(CAM_MCLK, VI_ALT3,  NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* VI_ALT1 pinmux */
+       VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* VGP4 pinmux */
+       VI_PINMUX(GPIO_PBB4, VGP4,    NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+       /* UARTD pinmux */
+       DEFAULT_PINMUX(GMI_A16,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,       UARTD,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_A18,       UARTD,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_A19,       UARTD,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* SPI4 pinmux */
+       DEFAULT_PINMUX(GMI_AD5,       SPI4,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD6,       SPI4,        UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD7,       SPI4,        UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD12,      RSVD1,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,     SPI4,        NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_WR_N,      SPI4,        NORMAL,    NORMAL,   INPUT),
+
+       /* PWM1 pinmux */
+       DEFAULT_PINMUX(GMI_AD9,       PWM1,        NORMAL,    NORMAL,   OUTPUT),
+
+       /* SOC pinmux */
+       DEFAULT_PINMUX(GMI_CS1_N,     SOC,         NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(GMI_OE_N,      SOC,         NORMAL,    TRISTATE, INPUT),
+
+       /* EXTPERIPH2 pinmux */
+       DEFAULT_PINMUX(CLK2_OUT,      EXTPERIPH2,  NORMAL,    NORMAL,   OUTPUT),
+
        /* SDMMC1 pinmux */
-       DEFAULT_PINMUX(SDMMC1_CLK,      SDMMC1,   NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_CMD,      SDMMC1,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT3,     SDMMC1,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT2,     SDMMC1,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT1,     SDMMC1,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_DAT0,     SDMMC1,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC1_WP_N,     SDMMC1,   UP,     NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_CLK,    SDMMC1,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,    SDMMC1,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,   SDMMC1,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,   SDMMC1,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,   SDMMC1,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,   SDMMC1,      UP,        NORMAL,   INPUT),
 
        /* SDMMC3 pinmux */
-       DEFAULT_PINMUX(SDMMC3_CLK,      SDMMC3,   NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3,  NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, NORMAL, NORMAL,   OUTPUT),
-
-       DEFAULT_PINMUX(SDMMC3_CMD,      SDMMC3,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT0,     SDMMC3,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT1,     SDMMC3,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT2,     SDMMC3,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,   UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3,   UP,     NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK,    SDMMC3,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,    SDMMC3,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,   SDMMC3,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,   SDMMC3,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,   SDMMC3,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,   SDMMC3,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_IN,  SDMMC3,  UP,        TRISTATE, INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3,  DOWN,      NORMAL,   INPUT),
 
        /* SDMMC4 pinmux */
-       LV_PINMUX(SDMMC4_CLK,  SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_CMD,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT0, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT1, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT2, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT3, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT4, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT5, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT6, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_DAT7, SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
-       LV_PINMUX(SDMMC4_RST_N, RSVD1, DOWN,   NORMAL, INPUT, DISABLE, DISABLE),
+       DEFAULT_PINMUX(SDMMC4_CLK,    SDMMC4,      NORMAL,    NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,    SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,   SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,   SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,   SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,   SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,   SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,   SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,   SDMMC4,      UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,   SDMMC4,      UP,        NORMAL,   INPUT),
+
+       /* BLINK pinmux */
+       DEFAULT_PINMUX(CLK_32K_OUT,   BLINK,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* KBC pinmux */
+       DEFAULT_PINMUX(KB_COL0,       KBC,         UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_COL1,       KBC,         UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_COL2,       KBC,         UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_ROW0,       KBC,         UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_ROW1,       KBC,         UP,        NORMAL,   INPUT),
+       DEFAULT_PINMUX(KB_ROW2,       KBC,         UP,        NORMAL,   INPUT),
+
+       /*Audio Codec*/
+       DEFAULT_PINMUX(DAP3_DIN,      RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,     RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV0,      RSVD1,       NORMAL,    TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(KB_ROW7,       RSVD1,       UP,        NORMAL,   INPUT),
+
+       /* UARTA pinmux */
+       DEFAULT_PINMUX(KB_ROW10,      UARTA,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(KB_ROW9,       UARTA,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* I2CPWR pinmux (I2C5) */
+       I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+       I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+
+       /* SYSCLK pinmux */
+       DEFAULT_PINMUX(SYS_CLK_REQ,   SYSCLK,      NORMAL,    NORMAL,   OUTPUT),
+
+       /* RTCK pinmux */
+       DEFAULT_PINMUX(JTAG_RTCK,     RTCK,        NORMAL,    NORMAL,   INPUT),
+
+       /* CLK pinmux */
+       DEFAULT_PINMUX(CLK_32K_IN,    CLK,         NORMAL,    TRISTATE, INPUT),
+
+       /* PWRON pinmux */
+       DEFAULT_PINMUX(CORE_PWR_REQ,  PWRON,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* CPU pinmux */
+       DEFAULT_PINMUX(CPU_PWR_REQ,   CPU,         NORMAL,    NORMAL,   OUTPUT),
+
+       /* PMI pinmux */
+       DEFAULT_PINMUX(PWR_INT_N,     PMI,         NORMAL,    TRISTATE, INPUT),
+
+       /* RESET_OUT_N pinmux */
+       DEFAULT_PINMUX(RESET_OUT_N,   RESET_OUT_N, NORMAL,    NORMAL,   OUTPUT),
+
+       /* EXTPERIPH3 pinmux */
+       DEFAULT_PINMUX(CLK3_OUT,      EXTPERIPH3,  NORMAL,    NORMAL,   OUTPUT),
 
        /* I2C1 pinmux */
-       I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL,  NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL,  NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
+       I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
 
-       /* I2C2 pinmux */
-       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL,  NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL,  NORMAL, INPUT, DISABLE, ENABLE),
+       /* UARTB pinmux */
+       DEFAULT_PINMUX(UART2_CTS_N,   UARTB,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,   UARTB,       NORMAL,    NORMAL,   OUTPUT),
 
-       /* I2C3 pinmux */
-       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL,   NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL,   NORMAL, INPUT, DISABLE, ENABLE),
+       /* IRDA pinmux */
+       DEFAULT_PINMUX(UART2_RXD,     UARTB,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART2_TXD,     UARTB,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* UARTC pinmux */
+       DEFAULT_PINMUX(UART3_CTS_N,   UARTC,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,   UARTC,       NORMAL,    NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,     UARTC,       NORMAL,    TRISTATE, INPUT),
+       DEFAULT_PINMUX(UART3_TXD,     UARTC,       NORMAL,    NORMAL,   OUTPUT),
+
+       /* OWR pinmux */
+       DEFAULT_PINMUX(OWR,           OWR,         NORMAL,    NORMAL,   INPUT),
+
+       /* CEC pinmux */
+       CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
 
        /* I2C4 pinmux */
-       I2C_PINMUX(DDC_SCL,     I2C4, NORMAL,   NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(DDC_SDA,     I2C4, NORMAL,   NORMAL, INPUT, DISABLE, ENABLE),
-
-       /* Power I2C pinmux */
-       I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-       I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
-
-       DEFAULT_PINMUX(ULPI_DATA0,      UARTA,    NORMAL, NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(ULPI_DATA1,      UARTA,    UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_DATA2,      UARTA,    NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(ULPI_DATA3,      UARTA,    NORMAL, NORMAL,   INPUT),
-
-       DEFAULT_PINMUX(ULPI_DATA4,      UARTA,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(ULPI_DATA5,      UARTA,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(ULPI_DATA6,      UARTA,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(ULPI_DATA7,      UARTA,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(ULPI_CLK,        UARTD,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(ULPI_DIR,        UARTD,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(ULPI_NXT,        UARTD,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(ULPI_STP,        UARTD,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(DAP3_FS,         I2S2,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(DAP3_DIN,        I2S2,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(CLK2_OUT,        EXTPERIPH2, NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(CLK2_REQ,        DAP,      NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(UART2_RXD,       UARTB,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(UART2_TXD,       UARTB,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(UART2_RTS_N,     UARTB,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(UART2_CTS_N,     UARTB,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(UART3_TXD,       UARTC,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(UART3_RXD,       UARTC,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(UART3_CTS_N,     UARTC,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(UART3_RTS_N,     UARTC,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(GPIO_PU0,        RSVD1,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PU1,        RSVD1,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(GPIO_PU2,        RSVD1,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PU3,        RSVD1,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PU4,        PWM1,     NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(GPIO_PU5,        PWM2,     NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(GPIO_PU6,        RSVD1,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(DAP4_FS,         I2S3,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(DAP4_DIN,        I2S3,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(DAP4_DOUT,       I2S3,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(DAP4_SCLK,       I2S3,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(CLK3_OUT,        EXTPERIPH3, NORMAL, NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(CLK3_REQ,        DEV3,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GMI_WP_N,        GMI,      NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GMI_CS2_N,       RSVD1,    UP,     NORMAL,     INPUT),
-       DEFAULT_PINMUX(GMI_AD8,         PWM0,     NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(GMI_AD10,        NAND,     NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(GMI_A16,         UARTD,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(GMI_A17,         UARTD,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GMI_A18,         UARTD,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GMI_A19,         UARTD,    NORMAL, NORMAL,     OUTPUT),
-       DEFAULT_PINMUX(CAM_MCLK,        VI_ALT2,  UP,     NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PCC1,       RSVD1,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PBB0,       RSVD1,    NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PBB3,       VGP3,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PBB5,       VGP5,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PBB6,       VGP6,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PBB7,       I2S4,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(GPIO_PCC2,       I2S4,     NORMAL, NORMAL,     INPUT),
-       DEFAULT_PINMUX(JTAG_RTCK,       RTCK,     NORMAL, NORMAL,     OUTPUT),
-
-       /*  KBC keys */
-       DEFAULT_PINMUX(KB_ROW0,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW1,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW2,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW3,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW4,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW5,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW6,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW7,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW8,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW9,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_ROW10,   KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL0,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL1,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL2,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL3,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL4,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL5,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL6,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(KB_COL7,    KBC,    UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(GPIO_PV0,   RSVD1,  UP,    NORMAL,    INPUT),
-       DEFAULT_PINMUX(GPIO_PV1,   RSVD1,  UP,    NORMAL,    INPUT),
-
-       DEFAULT_PINMUX(CLK_32K_OUT,     BLINK,    NORMAL, NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(SYS_CLK_REQ,     SYSCLK,   NORMAL, NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(OWR,             OWR,      NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(DAP1_FS,         I2S0,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(DAP1_DIN,        I2S0,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(DAP1_DOUT,       I2S0,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(DAP1_SCLK,       I2S0,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(CLK1_REQ,        DAP,      NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(CLK1_OUT,        EXTPERIPH1, NORMAL, NORMAL, INPUT),
-       DEFAULT_PINMUX(SPDIF_IN,        SPDIF,    NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SPDIF_OUT,       SPDIF,    NORMAL, NORMAL,   OUTPUT),
-       DEFAULT_PINMUX(DAP2_FS,         I2S1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(DAP2_DIN,        I2S1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(DAP2_DOUT,       I2S1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(DAP2_SCLK,       I2S1,     NORMAL, NORMAL,   INPUT),
-
-       DEFAULT_PINMUX(SPI1_MOSI,       SPI1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SPI1_SCK,        SPI1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SPI1_CS0_N,      SPI1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SPI1_CS1_N,      SPI1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SPI1_CS2_N,      SPI1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(SPI1_MISO,       SPI1,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(HDMI_CEC,        CEC,      NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(HDMI_INT,        RSVD1,    NORMAL, TRISTATE, INPUT),
-
-       /* GPIOs */
-       /* SDMMC1 CD gpio */
-       DEFAULT_PINMUX(GMI_IORDY,       RSVD1,    UP,     NORMAL,   INPUT),
-
-       /* Touch RESET */
-       DEFAULT_PINMUX(GMI_AD14,        NAND,     NORMAL, NORMAL,   OUTPUT),
-
-       /* Power rails GPIO */
-       DEFAULT_PINMUX(SPI2_SCK,        GMI,      NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(GPIO_PBB4,       VGP4,     NORMAL, NORMAL,   INPUT),
-       DEFAULT_PINMUX(KB_ROW8,         KBC,      UP,     NORMAL,   INPUT),
+       DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+       DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
+
+       /* USB pinmux */
+       USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
+
+       /* nct */
+       DEFAULT_PINMUX(GPIO_X6_AUD,   SPI6,        UP,        TRISTATE, INPUT),
 };
 
 static struct pingroup_config unused_pins_lowpower[] = {
-       DEFAULT_PINMUX(GMI_CS0_N,       NAND,     UP,     TRISTATE, OUTPUT),
-       DEFAULT_PINMUX(GMI_CS3_N,       NAND,     UP,     TRISTATE, OUTPUT),
-       DEFAULT_PINMUX(GMI_CS4_N,       NAND,     UP,     TRISTATE, OUTPUT),
-       DEFAULT_PINMUX(GMI_CS7_N,       NAND,     UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(GMI_AD0,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD1,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD2,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD3,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD4,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD5,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD6,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD7,         NAND,     NORMAL, TRISTATE, INPUT),
-       DEFAULT_PINMUX(GMI_AD9,         PWM1,     NORMAL, TRISTATE, OUTPUT),
-       DEFAULT_PINMUX(GMI_AD11,        NAND,     NORMAL, TRISTATE, OUTPUT),
-       DEFAULT_PINMUX(GMI_AD13,        NAND,     UP,     NORMAL,   INPUT),
-       DEFAULT_PINMUX(GMI_WR_N,        NAND,     NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(CLK1_REQ,      RSVD3,       DOWN, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(USB_VBUS_EN1,  RSVD3,       DOWN, TRISTATE, OUTPUT),
 };
 
-#endif /* _PINMUX_CONFIG_DALMORE_H_ */
+/* Initially setting all used GPIO's to non-TRISTATE */
+static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
+       DEFAULT_PINMUX(GPIO_X4_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_X5_AUD,     RSVD1,  UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X6_AUD,     RSVD3,  UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X7_AUD,     RSVD1,  DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_W2_AUD,     RSVD1,  UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_W3_AUD,     SPI6,   UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X1_AUD,     RSVD3,  DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_X3_AUD,     RSVD3,  UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(DAP3_FS,         I2S2,   DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_DIN,        I2S2,   DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,   DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,   DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV0,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PV1,        RSVD1,  NORMAL,  NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GPIO_PBB3,       RSVD3,  DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB5,       RSVD3,  DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB6,       RSVD3,  DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PBB7,       RSVD3,  DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PCC1,       RSVD3,  DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PCC2,       RSVD3,  DOWN,    NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(GMI_AD0,         GMI,    NORMAL,  NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD1,         GMI,    NORMAL,  NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD10,        GMI,    DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD11,        GMI,    DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD12,        GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD13,        GMI,    DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_AD2,         GMI,    NORMAL,  NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD3,         GMI,    NORMAL,  NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_AD8,         GMI,    DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,       GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CLK,         GMI,    DOWN,    NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_CS0_N,       GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS2_N,       GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,       GMI,    UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GMI_CS4_N,       GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,       GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_DQS,         GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_IORDY,       GMI,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(GMI_WP_N,        GMI,    UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(SDMMC1_WP_N,     SPI4,   UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(CLK2_REQ,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+
+       DEFAULT_PINMUX(KB_COL3,         KBC,    UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_COL4,         SDMMC3, UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_COL5,         KBC,    UP,      NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_COL6,         KBC,    UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_COL7,         KBC,    UP,      NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(KB_ROW3,         KBC,    DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW4,         KBC,    DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW6,         KBC,    DOWN,    NORMAL,    INPUT),
+       DEFAULT_PINMUX(KB_ROW8,         KBC,    UP,      NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(CLK3_REQ,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU4,        RSVD3,  NORMAL,  NORMAL,    OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU5,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+       DEFAULT_PINMUX(GPIO_PU6,        RSVD3,  NORMAL,  NORMAL,    INPUT),
+
+       DEFAULT_PINMUX(HDMI_INT,        RSVD1,   DOWN,    NORMAL,   INPUT),
+
+       DEFAULT_PINMUX(GMI_AD9,         PWM1,   NORMAL,   NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(SPDIF_IN,        USB,    NORMAL,   NORMAL,   INPUT),
+
+       DEFAULT_PINMUX(SDMMC3_CD_N,     SDMMC3, UP,       NORMAL,   INPUT),
+};
+#endif /* PINMUX_CONFIG_COMMON_H */
index 7315577..30cf1fb 100644 (file)
@@ -1,13 +1,46 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra114.dtsi"
 
 / {
        model = "NVIDIA Dalmore";
        compatible = "nvidia,dalmore", "nvidia,tegra114";
 
+       aliases {
+               i2c0 = "/i2c@7000d000";
+               i2c1 = "/i2c@7000c000";
+               i2c2 = "/i2c@7000c400";
+               i2c3 = "/i2c@7000c500";
+               i2c4 = "/i2c@7000c700";
+       };
+
        memory {
                device_type = "memory";
                reg = <0x80000000 0x80000000>;
        };
+
+       i2c@7000c000 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c400 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c500 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c700 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000d000 {
+               status = "okay";
+               clock-frequency = <400000>;
+       };
 };
index aeda3a1..7934e4a 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20.dtsi"
 
 / {
        model = "NVIDIA Tegra20 Harmony evaluation board";
@@ -9,6 +9,8 @@
        aliases {
                usb0 = "/usb@c5008000";
                usb1 = "/usb@c5004000";
+               sdhci0 = "/sdhci@c8000600";
+               sdhci1 = "/sdhci@c8000200";
        };
 
        memory {
        usb@c5004000 {
                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
        };
+
+       sdhci@c8000200 {
+               status = "okay";
+               cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+               wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+               power-gpios = <&gpio 155 0>; /* gpio PT3 */
+               bus-width = <4>;
+       };
+
+       sdhci@c8000600 {
+               status = "okay";
+               cd-gpios = <&gpio 58 1>; /* gpio PH2 */
+               wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+               power-gpios = <&gpio 70 0>; /* gpio PI6 */
+               bus-width = <8>;
+       };
 };
index 527a296..c0e2e1e 100644 (file)
@@ -1,7 +1,6 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
-/include/ ARCH_CPU_DTS
+#include "tegra20.dtsi"
 
 / {
        model = "NVIDIA Seaboard";
        };
 
        aliases {
-               /* This defines the order of our USB ports */
+               /* This defines the order of our ports */
                usb0 = "/usb@c5008000";
                usb1 = "/usb@c5000000";
-
                i2c0 = "/i2c@7000d000";
                i2c1 = "/i2c@7000c000";
                i2c2 = "/i2c@7000c400";
                i2c3 = "/i2c@7000c500";
+               sdhci0 = "/sdhci@c8000600";
+               sdhci1 = "/sdhci@c8000400";
        };
 
        memory {
        };
 
        sdhci@c8000400 {
-               cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+               status = "okay";
+               cd-gpios = <&gpio 69 1>; /* gpio PI5 */
                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+               bus-width = <4>;
        };
 
        sdhci@c8000600 {
-               support-8bit;
+               status = "okay";
+               bus-width = <8>;
        };
 
        lcd_panel: panel {
index 3e5e39d..e1a3d1e 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20.dtsi"
 
 / {
        model = "NVIDIA Tegra20 Ventana evaluation board";
@@ -8,6 +8,8 @@
 
        aliases {
                usb0 = "/usb@c5008000";
+               sdhci0 = "/sdhci@c8000600";
+               sdhci1 = "/sdhci@c8000400";
        };
 
        memory {
        usb@c5004000 {
                status = "disabled";
        };
+
+       sdhci@c8000400 {
+               status = "okay";
+               cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+               wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+               power-gpios = <&gpio 70 0>; /* gpio PI6 */
+               bus-width = <4>;
+       };
+
+       sdhci@c8000600 {
+               status = "okay";
+               bus-width = <8>;
+       };
 };
index 4579557..eb92264 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20.dtsi"
 
 / {
        model = "NVIDIA Tegra20 Whistler evaluation board";
@@ -9,6 +9,8 @@
        aliases {
                i2c0 = "/i2c@7000d000";
                usb0 = "/usb@c5008000";
+               sdhci0 = "/sdhci@c8000600";
+               sdhci1 = "/sdhci@c8000400";
        };
 
        memory {
        usb@c5004000 {
                status = "disabled";
        };
+
+       sdhci@c8000400 {
+               status = "okay";
+               wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+               bus-width = <8>;
+       };
+
+       sdhci@c8000600 {
+               status = "okay";
+               bus-width = <8>;
+       };
 };
index f9f80c5..4d22b48 100644 (file)
@@ -1,7 +1,6 @@
 /dts-v1/;
 
-/memreserve/ 0x1c000000 0x04000000;
-/include/ ARCH_CPU_DTS
+#include "tegra30.dtsi"
 
 / {
        model = "NVIDIA Cardhu";
@@ -13,6 +12,8 @@
                i2c2 = "/i2c@7000c400";
                i2c3 = "/i2c@7000c500";
                i2c4 = "/i2c@7000c700";
+               sdhci0 = "/sdhci@78000600";
+               sdhci1 = "/sdhci@78000000";
        };
 
        memory {
        };
 
        i2c@7000c000 {
+               status = "okay";
                clock-frequency = <100000>;
        };
 
        i2c@7000c400 {
+               status = "okay";
                clock-frequency = <100000>;
        };
 
        i2c@7000c500 {
+               status = "okay";
                clock-frequency = <100000>;
        };
 
        i2c@7000c700 {
+               status = "okay";
                clock-frequency = <100000>;
        };
 
        i2c@7000d000 {
+               status = "okay";
                clock-frequency = <100000>;
        };
 
                status = "okay";
                spi-max-frequency = <25000000>;
        };
+
+       sdhci@78000000 {
+               status = "okay";
+               cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+               wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+               power-gpios = <&gpio 31 0>; /* gpio PD7 */
+               bus-width = <4>;
+       };
+
+       sdhci@78000600 {
+               status = "okay";
+               bus-width = <8>;
+       };
 };
index 93430ed..3122441 100644 (file)
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
 #ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
        funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
        funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
@@ -54,25 +49,6 @@ static void pin_mux_mmc(void)
        /* For CD GPIO PI5 */
        pinmux_tristate_disable(PINGRP_ATC);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-       debug("board_mmc_init called\n");
-
-       /* Enable muxes, etc. for SDMMC controllers */
-       pin_mux_mmc();
-
-       debug("board_mmc_init: init SD slot J26\n");
-       /* init dev 0, SD slot J26, with 8-bit bus */
-       tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
-
-       debug("board_mmc_init: init SD slot J5\n");
-       /* init dev 2, SD slot J5, with 4-bit bus */
-       tegra_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
-
-       return 0;
-}
 #endif
 
 void pin_mux_usb(void)
index 3e33da0..e581fdd 100644 (file)
 #include <asm/arch/funcmux.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
 
 /* TODO: Remove this code when the SPI switch is working */
 #if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
@@ -51,7 +47,7 @@ void gpio_early_init_uart(void)
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
+void pin_mux_mmc(void)
 {
        funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
        funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
@@ -61,25 +57,6 @@ static void pin_mux_mmc(void)
        /* For CD GPIO PI5 */
        pinmux_tristate_disable(PINGRP_ATC);
 }
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
-{
-       debug("board_mmc_init called\n");
-
-       /* Enable muxes, etc. for SDMMC controllers */
-       pin_mux_mmc();
-
-       debug("board_mmc_init: init eMMC\n");
-       /* init dev 0, eMMC chip, with 8-bit bus */
-       tegra_mmc_init(0, 8, -1, -1);
-
-       debug("board_mmc_init: init SD slot\n");
-       /* init dev 1, SD slot, with 4-bit bus */
-       tegra_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
-
-       return 0;
-}
 #endif
 
 void pin_mux_usb(void)
index 592cd6b..f18aa27 100644 (file)
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch-tegra/mmc.h>
 #include <asm/gpio.h>
 #include <i2c.h>
-#ifdef CONFIG_TEGRA_MMC
-#include <mmc.h>
-#endif
-
 
+#ifdef CONFIG_TEGRA_MMC
 /*
  * Routine: pin_mux_mmc
  * Description: setup the pin muxes/tristate values for the SDMMC(s)
  */
-static void pin_mux_mmc(void)
-{
-       funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
-       funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
-}
-
-/* this is a weak define that we are overriding */
-int board_mmc_init(bd_t *bd)
+void pin_mux_mmc(void)
 {
        uchar val;
        int ret;
 
-       debug("board_mmc_init called\n");
-
        /* Turn on MAX8907B LDO12 to 2.8V for J40 power */
        ret = i2c_set_bus_num(0);
        if (ret)
@@ -70,17 +57,10 @@ int board_mmc_init(bd_t *bd)
        if (ret)
                printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
 
-       /* Enable muxes, etc. for SDMMC controllers */
-       pin_mux_mmc();
-
-       /* init dev 0 (SDMMC4), (J29 "HSMMC") with 8-bit bus */
-       tegra_mmc_init(0, 8, -1, -1);
-
-       /* init dev 1 (SDMMC3), (J40 "SDIO3") with 8-bit bus */
-       tegra_mmc_init(1, 8, -1, -1);
-
-       return 0;
+       funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_SLXA_8BIT);
+       funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATC_ATD_8BIT);
 }
+#endif
 
 /* this is a weak define that we are overriding */
 void pin_mux_usb(void)
index e40a986..aa76f65 100644 (file)
@@ -19,7 +19,6 @@
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch-tegra/board.h>
-#include <asm/arch-tegra/mmc.h>
 
 #include "../colibri_t20-common/colibri_t20-common.h"
 
@@ -34,13 +33,13 @@ void pin_mux_usb(void)
 #endif
 
 #ifdef CONFIG_TEGRA_MMC
-int board_mmc_init(bd_t *bd)
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+void pin_mux_mmc(void)
 {
        funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
        pinmux_tristate_disable(PINGRP_GMB);
-
-       tegra_mmc_init(0, 4, -1, GPIO_PC7);
-
-       return 0;
 }
 #endif
index c29b43a..c0e54af 100644 (file)
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ ARCH_CPU_DTS
+#include "tegra20.dtsi"
 
 / {
        model = "Toradex Colibri T20";
@@ -10,6 +10,7 @@
                usb0 = "/usb@c5008000";
                usb1 = "/usb@c5000000";
                usb2 = "/usb@c5004000";
+               sdhci0 = "/sdhci@c8000600";
        };
 
        usb@c5000000 {
                        compatible = "nand-flash";
                };
        };
+
+       sdhci@c8000600 {
+               status = "okay";
+               cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+               bus-width = <4>;
+       };
 };
index 58a4563..d73625c 100644 (file)
 #define PRINTF(fmt,args...)
 #endif
 
-/* Rather than repeat this expression each time, add a define for it */
-#if (defined(CONFIG_CMD_IDE) || \
-     defined(CONFIG_CMD_SATA) || \
-     defined(CONFIG_CMD_SCSI) || \
-     defined(CONFIG_CMD_USB) || \
-     defined(CONFIG_MMC) || \
-     defined(CONFIG_SYSTEMACE) )
-#define HAVE_BLOCK_DEVICE
-#endif
-
 struct block_drvr {
        char *name;
        block_dev_desc_t* (*get_dev)(int dev);
index dc7d462..0e6d82d 100644 (file)
 #include <ide.h>
 #include "part_amiga.h"
 
-#if defined(CONFIG_CMD_IDE) || \
-    defined(CONFIG_CMD_SCSI) || \
-    defined(CONFIG_CMD_USB) || \
-    defined(CONFIG_MMC) || \
-    defined(CONFIG_SYSTEMACE)
+#ifdef HAVE_BLOCK_DEVICE
 
 #undef AMIGA_DEBUG
 
index 3fe901b..37087a6 100644 (file)
 #include <ide.h>
 #include "part_dos.h"
 
-#if defined(CONFIG_CMD_IDE) || \
-    defined(CONFIG_CMD_SATA) || \
-    defined(CONFIG_CMD_SCSI) || \
-    defined(CONFIG_CMD_USB) || \
-    defined(CONFIG_MMC) || \
-    defined(CONFIG_SYSTEMACE)
+#ifdef HAVE_BLOCK_DEVICE
 
 /* Convert char[4] in little endian format to the host format integer
  */
index 7665017..b3fd0e9 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_CMD_IDE) || \
-    defined(CONFIG_CMD_SATA) || \
-    defined(CONFIG_CMD_SCSI) || \
-    defined(CONFIG_CMD_USB) || \
-    defined(CONFIG_MMC) || \
-    defined(CONFIG_SYSTEMACE)
-
+#ifdef HAVE_BLOCK_DEVICE
 /**
  * efi_crc32() - EFI version of crc32 function
  * @buf: buffer to calculate crc32 of
index 4401790..49639af 100644 (file)
 #include <command.h>
 #include "part_iso.h"
 
-#if defined(CONFIG_CMD_IDE) || \
-    defined(CONFIG_CMD_SCSI) || \
-    defined(CONFIG_CMD_SATA) || \
-    defined(CONFIG_CMD_USB) || \
-    defined(CONFIG_MMC) || \
-    defined(CONFIG_SYSTEMACE)
+#ifdef HAVE_BLOCK_DEVICE
 
 /* #define     ISO_PART_DEBUG */
 
index cb443ac..74dc12f 100644 (file)
 #include <ide.h>
 #include "part_mac.h"
 
-#if defined(CONFIG_CMD_IDE) || \
-    defined(CONFIG_CMD_SCSI) || \
-    defined(CONFIG_CMD_SATA) || \
-    defined(CONFIG_CMD_USB) || \
-    defined(CONFIG_MMC) || \
-    defined(CONFIG_SYSTEMACE)
+#ifdef HAVE_BLOCK_DEVICE
 
 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
 #ifndef __ldiv_t_defined
index efc77fa..ca71cd3 100644 (file)
@@ -46,6 +46,7 @@ struct i2c_bus {
        struct i2c_control      *control;
        struct i2c_ctlr         *regs;
        int                     is_dvc; /* DVC type, rather than I2C */
+       int                     is_scs; /* single clock source (T114+) */
        int                     inited; /* bus is inited */
 };
 
@@ -88,7 +89,28 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus)
         * 16 to get the right frequency.
         */
        clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
-                              i2c_bus->speed * 2 * 8);
+               i2c_bus->speed * 2 * 8);
+
+       if (i2c_bus->is_scs) {
+               /*
+                * T114 I2C went to a single clock source for standard/fast and
+                * HS clock speeds. The new clock rate setting calculation is:
+                *  SCL = CLK_SOURCE.I2C /
+                *   (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
+                *   I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
+                *
+                * NOTE: We do this here, after the initial clock/pll start,
+                * because if we read the clk_div reg before the controller
+                * is running, we hang, and we need it for the new calc.
+                */
+               int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
+               debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
+                       clk_div_stdfst_mode);
+
+               clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
+                       CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) *
+                       i2c_bus->speed * 2);
+       }
 
        /* Reset I2C controller. */
        i2c_reset_controller(i2c_bus);
@@ -352,10 +374,11 @@ static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
  * @param node_list    list of nodes to process (any <=0 are ignored)
  * @param count                number of nodes to process
  * @param is_dvc       1 if these are DVC ports, 0 if standard I2C
+ * @param is_scs       1 if this HW uses a single clock source (T114+)
  * @return 0 if ok, -1 on error
  */
 static int process_nodes(const void *blob, int node_list[], int count,
-                        int is_dvc)
+                        int is_dvc, int is_scs)
 {
        struct i2c_bus *i2c_bus;
        int i;
@@ -375,6 +398,8 @@ static int process_nodes(const void *blob, int node_list[], int count,
                        return -1;
                }
 
+               i2c_bus->is_scs = is_scs;
+
                i2c_bus->is_dvc = is_dvc;
                if (is_dvc) {
                        i2c_bus->control =
@@ -403,18 +428,25 @@ void i2c_init_board(void)
        const void *blob = gd->fdt_blob;
        int count;
 
-       /* First get the normal i2c ports */
+       /* First check for newer (T114+) I2C ports */
+       count = fdtdec_find_aliases_for_id(blob, "i2c",
+                       COMPAT_NVIDIA_TEGRA114_I2C, node_list,
+                       TEGRA_I2C_NUM_CONTROLLERS);
+       if (process_nodes(blob, node_list, count, 0, 1))
+               return;
+
+       /* Now get the older (T20/T30) normal I2C ports */
        count = fdtdec_find_aliases_for_id(blob, "i2c",
                        COMPAT_NVIDIA_TEGRA20_I2C, node_list,
                        TEGRA_I2C_NUM_CONTROLLERS);
-       if (process_nodes(blob, node_list, count, 0))
+       if (process_nodes(blob, node_list, count, 0, 0))
                return;
 
        /* Now look for dvc ports */
        count = fdtdec_add_aliases_for_id(blob, "i2c",
                        COMPAT_NVIDIA_TEGRA20_DVC, node_list,
                        TEGRA_I2C_NUM_CONTROLLERS);
-       if (process_nodes(blob, node_list, count, 1))
+       if (process_nodes(blob, node_list, count, 1, 0))
                return;
 }
 
index 7258619..e86bc68 100644 (file)
@@ -2,7 +2,7 @@
  * (C) Copyright 2009 SAMSUNG Electronics
  * Minkyu Kang <mk7.kang@samsung.com>
  * Jaehoon Chung <jh80.chung@samsung.com>
- * Portions Copyright 2011-2012 NVIDIA Corporation
+ * Portions Copyright 2011-2013 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 #include <asm/arch-tegra/tegra_mmc.h>
 #include <mmc.h>
 
-/* support 4 mmc hosts */
-struct mmc mmc_dev[4];
-struct mmc_host mmc_host[4];
+DECLARE_GLOBAL_DATA_PTR;
 
+struct mmc mmc_dev[MAX_HOSTS];
+struct mmc_host mmc_host[MAX_HOSTS];
 
-/**
- * Get the host address and peripheral ID for a device. Devices are numbered
- * from 0 to 3.
- *
- * @param host         Structure to fill in (base, reg, mmc_id)
- * @param dev_index    Device index (0-3)
- */
-static void tegra_get_setup(struct mmc_host *host, int dev_index)
+#ifndef CONFIG_OF_CONTROL
+#error "Please enable device tree support to use this driver"
+#endif
+
+static void mmc_set_power(struct mmc_host *host, unsigned short power)
 {
-       debug("tegra_get_setup: dev_index = %d\n", dev_index);
-
-       switch (dev_index) {
-       case 1:
-               host->base = TEGRA_SDMMC3_BASE;
-               host->mmc_id = PERIPH_ID_SDMMC3;
-               break;
-       case 2:
-               host->base = TEGRA_SDMMC2_BASE;
-               host->mmc_id = PERIPH_ID_SDMMC2;
-               break;
-       case 3:
-               host->base = TEGRA_SDMMC1_BASE;
-               host->mmc_id = PERIPH_ID_SDMMC1;
-               break;
-       case 0:
-       default:
-               host->base = TEGRA_SDMMC4_BASE;
-               host->mmc_id = PERIPH_ID_SDMMC4;
-               break;
+       u8 pwr = 0;
+       debug("%s: power = %x\n", __func__, power);
+
+       if (power != (unsigned short)-1) {
+               switch (1 << power) {
+               case MMC_VDD_165_195:
+                       pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
+                       break;
+               case MMC_VDD_29_30:
+               case MMC_VDD_30_31:
+                       pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
+                       break;
+               case MMC_VDD_32_33:
+               case MMC_VDD_33_34:
+                       pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
+                       break;
+               }
        }
+       debug("%s: pwr = %X\n", __func__, pwr);
 
-       host->reg = (struct tegra_mmc *)host->base;
+       /* Set the bus voltage first (if any) */
+       writeb(pwr, &host->reg->pwrcon);
+       if (pwr == 0)
+               return;
+
+       /* Now enable bus power */
+       pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
+       writeb(pwr, &host->reg->pwrcon);
 }
 
 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data,
@@ -363,8 +365,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
        debug(" mmc_change_clock called\n");
 
        /*
-        * Change Tegra SDMMCx clock divisor here. Source is 216MHz,
-        * PLLP_OUT0
+        * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
         */
        if (clock == 0)
                goto out;
@@ -439,7 +440,7 @@ static void mmc_set_ios(struct mmc *mmc)
        debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 }
 
-static void mmc_reset(struct mmc_host *host)
+static void mmc_reset(struct mmc_host *host, struct mmc *mmc)
 {
        unsigned int timeout;
        debug(" mmc_reset called\n");
@@ -465,6 +466,14 @@ static void mmc_reset(struct mmc_host *host)
                timeout--;
                udelay(1000);
        }
+
+       /* Set SD bus voltage & enable bus power */
+       mmc_set_power(host, fls(mmc->voltages) - 1);
+       debug("%s: power control = %02X, host control = %02X\n", __func__,
+               readb(&host->reg->pwrcon), readb(&host->reg->hostctl));
+
+       /* Make sure SDIO pads are set up */
+       pad_init_mmc(host);
 }
 
 static int mmc_core_init(struct mmc *mmc)
@@ -473,7 +482,7 @@ static int mmc_core_init(struct mmc *mmc)
        unsigned int mask;
        debug(" mmc_core_init called\n");
 
-       mmc_reset(host);
+       mmc_reset(host, mmc);
 
        host->version = readw(&host->reg->hcver);
        debug("host version = %x\n", host->version);
@@ -518,41 +527,43 @@ int tegra_mmc_getcd(struct mmc *mmc)
 
        debug("tegra_mmc_getcd called\n");
 
-       if (host->cd_gpio >= 0)
-               return !gpio_get_value(host->cd_gpio);
+       if (fdt_gpio_isvalid(&host->cd_gpio))
+               return fdtdec_get_gpio(&host->cd_gpio);
 
        return 1;
 }
 
-int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
+static int do_mmc_init(int dev_index)
 {
        struct mmc_host *host;
        char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
        struct mmc *mmc;
 
-       debug(" tegra_mmc_init: index %d, bus width %d "
-               "pwr_gpio %d cd_gpio %d\n",
-               dev_index, bus_width, pwr_gpio, cd_gpio);
-
+       /* DT should have been read & host config filled in */
        host = &mmc_host[dev_index];
+       if (!host->enabled)
+               return -1;
 
-       host->clock = 0;
-       host->pwr_gpio = pwr_gpio;
-       host->cd_gpio = cd_gpio;
-       tegra_get_setup(host, dev_index);
+       debug(" do_mmc_init: index %d, bus width %d "
+               "pwr_gpio %d cd_gpio %d\n",
+               dev_index, host->width,
+               host->pwr_gpio.gpio, host->cd_gpio.gpio);
 
+       host->clock = 0;
        clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
 
-       if (host->pwr_gpio >= 0) {
+       if (fdt_gpio_isvalid(&host->pwr_gpio)) {
                sprintf(gpusage, "SD/MMC%d PWR", dev_index);
-               gpio_request(host->pwr_gpio, gpusage);
-               gpio_direction_output(host->pwr_gpio, 1);
+               gpio_request(host->pwr_gpio.gpio, gpusage);
+               gpio_direction_output(host->pwr_gpio.gpio, 1);
+               debug(" Power GPIO name = %s\n", host->pwr_gpio.name);
        }
 
-       if (host->cd_gpio >= 0) {
+       if (fdt_gpio_isvalid(&host->cd_gpio)) {
                sprintf(gpusage, "SD/MMC%d CD", dev_index);
-               gpio_request(host->cd_gpio, gpusage);
-               gpio_direction_input(host->cd_gpio);
+               gpio_request(host->cd_gpio.gpio, gpusage);
+               gpio_direction_input(host->cd_gpio.gpio);
+               debug(" CD GPIO name = %s\n", host->cd_gpio.name);
        }
 
        mmc = &mmc_dev[dev_index];
@@ -567,9 +578,9 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 
        mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
        mmc->host_caps = 0;
-       if (bus_width == 8)
+       if (host->width == 8)
                mmc->host_caps |= MMC_MODE_8BIT;
-       if (bus_width >= 4)
+       if (host->width >= 4)
                mmc->host_caps |= MMC_MODE_4BIT;
        mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
 
@@ -578,8 +589,6 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
         *  low-speed SDIO card frequency (actually 400KHz)
         * max freq is highest HS eMMC clock as per the SD/MMC spec
         *  (actually 52MHz)
-        * Both of these are the closest equivalents w/216MHz source
-        *  clock and Tegra SDMMC divisors.
         */
        mmc->f_min = 375000;
        mmc->f_max = 48000000;
@@ -588,3 +597,104 @@ int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
 
        return 0;
 }
+
+/**
+ * Get the host address and peripheral ID for a node.
+ *
+ * @param blob         fdt blob
+ * @param node         Device index (0-3)
+ * @param host         Structure to fill in (reg, width, mmc_id)
+ */
+static int mmc_get_config(const void *blob, int node, struct mmc_host *host)
+{
+       debug("%s: node = %d\n", __func__, node);
+
+       host->enabled = fdtdec_get_is_enabled(blob, node);
+
+       host->reg = (struct tegra_mmc *)fdtdec_get_addr(blob, node, "reg");
+       if ((fdt_addr_t)host->reg == FDT_ADDR_T_NONE) {
+               debug("%s: no sdmmc base reg info found\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       host->mmc_id = clock_decode_periph_id(blob, node);
+       if (host->mmc_id == PERIPH_ID_NONE) {
+               debug("%s: could not decode periph id\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       /*
+        * NOTE: mmc->bus_width is determined by mmc.c dynamically.
+        * TBD: Override it with this value?
+        */
+       host->width = fdtdec_get_int(blob, node, "bus-width", 0);
+       if (!host->width)
+               debug("%s: no sdmmc width found\n", __func__);
+
+       /* These GPIOs are optional */
+       fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
+       fdtdec_decode_gpio(blob, node, "wp-gpios", &host->wp_gpio);
+       fdtdec_decode_gpio(blob, node, "power-gpios", &host->pwr_gpio);
+
+       debug("%s: found controller at %p, width = %d, periph_id = %d\n",
+               __func__, host->reg, host->width, host->mmc_id);
+       return 0;
+}
+
+/*
+ * Process a list of nodes, adding them to our list of SDMMC ports.
+ *
+ * @param blob          fdt blob
+ * @param node_list     list of nodes to process (any <=0 are ignored)
+ * @param count         number of nodes to process
+ * @return 0 if ok, -1 on error
+ */
+static int process_nodes(const void *blob, int node_list[], int count)
+{
+       struct mmc_host *host;
+       int i, node;
+
+       debug("%s: count = %d\n", __func__, count);
+
+       /* build mmc_host[] for each controller */
+       for (i = 0; i < count; i++) {
+               node = node_list[i];
+               if (node <= 0)
+                       continue;
+
+               host = &mmc_host[i];
+               host->id = i;
+
+               if (mmc_get_config(blob, node, host)) {
+                       printf("%s: failed to decode dev %d\n", __func__, i);
+                       return -1;
+               }
+               do_mmc_init(i);
+       }
+       return 0;
+}
+
+void tegra_mmc_init(void)
+{
+       int node_list[MAX_HOSTS], count;
+       const void *blob = gd->fdt_blob;
+       debug("%s entry\n", __func__);
+
+       /* See if any Tegra30 MMC controllers are present */
+       count = fdtdec_find_aliases_for_id(blob, "sdhci",
+               COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
+       debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
+       if (process_nodes(blob, node_list, count)) {
+               printf("%s: Error processing T30 mmc node(s)!\n", __func__);
+               return;
+       }
+
+       /* Now look for any Tegra20 MMC controllers */
+       count = fdtdec_find_aliases_for_id(blob, "sdhci",
+               COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
+       debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
+       if (process_nodes(blob, node_list, count)) {
+               printf("%s: Error processing T20 mmc node(s)!\n", __func__);
+               return;
+       }
+}
index a1c43f8..554145a 100644 (file)
@@ -1,5 +1,7 @@
 /*
+ * Copyright (c) 2011 The Chromium OS Authors.
  * Copyright (c) 2009-2012 NVIDIA Corporation
+ * Copyright (c) 2013 Lucas Stach
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  */
 
 #include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch-tegra/usb.h>
 #include <usb.h>
+#include <usb/ulpi.h>
+#include <libfdt.h>
+#include <fdtdec.h>
 
 #include "ehci.h"
 
-#include <asm/errno.h>
-#include <asm/arch/usb.h>
+#ifdef CONFIG_USB_ULPI
+       #ifndef CONFIG_USB_ULPI_VIEWPORT
+       #error  "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
+               define CONFIG_USB_ULPI_VIEWPORT"
+       #endif
+#endif
+
+enum {
+       USB_PORTS_MAX   = 3,            /* Maximum ports we allow */
+};
+
+/* Parameters we need for USB */
+enum {
+       PARAM_DIVN,                     /* PLL FEEDBACK DIVIDer */
+       PARAM_DIVM,                     /* PLL INPUT DIVIDER */
+       PARAM_DIVP,                     /* POST DIVIDER (2^N) */
+       PARAM_CPCON,                    /* BASE PLLC CHARGE Pump setup ctrl */
+       PARAM_LFCON,                    /* BASE PLLC LOOP FILter setup ctrl */
+       PARAM_ENABLE_DELAY_COUNT,       /* PLL-U Enable Delay Count */
+       PARAM_STABLE_COUNT,             /* PLL-U STABLE count */
+       PARAM_ACTIVE_DELAY_COUNT,       /* PLL-U Active delay count */
+       PARAM_XTAL_FREQ_COUNT,          /* PLL-U XTAL frequency count */
+       PARAM_DEBOUNCE_A_TIME,          /* 10MS DELAY for BIAS_DEBOUNCE_A */
+       PARAM_BIAS_TIME,                /* 20US DELAY AFter bias cell op */
+
+       PARAM_COUNT
+};
+
+/* Possible port types (dual role mode) */
+enum dr_mode {
+       DR_MODE_NONE = 0,
+       DR_MODE_HOST,           /* supports host operation */
+       DR_MODE_DEVICE,         /* supports device operation */
+       DR_MODE_OTG,            /* supports both */
+};
+
+/* Information about a USB port */
+struct fdt_usb {
+       struct usb_ctlr *reg;   /* address of registers in physical memory */
+       unsigned utmi:1;        /* 1 if port has external tranceiver, else 0 */
+       unsigned ulpi:1;        /* 1 if port has external ULPI transceiver */
+       unsigned enabled:1;     /* 1 to enable, 0 to disable */
+       unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
+       unsigned initialized:1; /* has this port already been initialized? */
+       enum dr_mode dr_mode;   /* dual role mode */
+       enum periph_id periph_id;/* peripheral id */
+       struct fdt_gpio_state vbus_gpio;        /* GPIO for vbus enable */
+       struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
+};
+
+static struct fdt_usb port[USB_PORTS_MAX];     /* List of valid USB ports */
+static unsigned port_count;                    /* Number of available ports */
+
+/*
+ * This table has USB timing parameters for each Oscillator frequency we
+ * support. There are four sets of values:
+ *
+ * 1. PLLU configuration information (reference clock is osc/clk_m and
+ * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
+ *
+ *  Reference frequency     13.0MHz      19.2MHz      12.0MHz      26.0MHz
+ *  ----------------------------------------------------------------------
+ *      DIVN                960 (0x3c0)  200 (0c8)    960 (3c0h)   960 (3c0)
+ *      DIVM                13 (0d)      4 (04)       12 (0c)      26 (1a)
+ * Filter frequency (MHz)   1            4.8          6            2
+ * CPCON                    1100b        0011b        1100b        1100b
+ * LFCON0                   0            0            0            0
+ *
+ * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
+ *
+ * Reference frequency     13.0MHz         19.2MHz         12.0MHz     26.0MHz
+ * ---------------------------------------------------------------------------
+ * PLLU_ENABLE_DLY_COUNT   02 (0x02)       03 (03)         02 (02)     04 (04)
+ * PLLU_STABLE_COUNT       51 (33)         75 (4B)         47 (2F)    102 (66)
+ * PLL_ACTIVE_DLY_COUNT    05 (05)         06 (06)         04 (04)     09 (09)
+ * XTAL_FREQ_COUNT        127 (7F)        187 (BB)        118 (76)    254 (FE)
+ *
+ * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
+ * SessEnd. Each of these signals have their own debouncer and for each of
+ * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
+ * BIAS_DEBOUNCE_B).
+ *
+ * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
+ *    0xffff -> No debouncing at all
+ *    <n> ms = <n> *1000 / (1/19.2MHz) / 4
+ *
+ * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
+ * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4  = 4800 = 0x12c0
+ *
+ * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
+ * values, so we can keep those to default.
+ *
+ * 4. The 20 microsecond delay after bias cell operation.
+ */
+static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+       /* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+       { 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
+       { 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
+       { 0x3C0, 0x0C, 0x00, 0xC,   0,  0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
+       { 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+};
+
+/* UTMIP Idle Wait Delay */
+static const u8 utmip_idle_wait_delay = 17;
+
+/* UTMIP Elastic limit */
+static const u8 utmip_elastic_limit = 16;
+
+/* UTMIP High Speed Sync Start Delay */
+static const u8 utmip_hs_sync_start_delay = 9;
 
 /*
  * A known hardware issue where Connect Status Change bit of PORTSC register
@@ -45,32 +163,428 @@ void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
                *reg |= EHCI_PS_CSC;
 }
 
-/*
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+/* Put the port into host mode */
+static void set_host_mode(struct fdt_usb *config)
+{
+       /*
+        * If we are an OTG port, check if remote host is driving VBus and
+        * bail out in this case.
+        */
+       if (config->dr_mode == DR_MODE_OTG &&
+               (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
+               return;
+
+       /*
+        * If not driving, we set the GPIO to enable VBUS. We assume
+        * that the pinmux is set up correctly for this.
+        */
+       if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+               fdtdec_setup_gpio(&config->vbus_gpio);
+               gpio_direction_output(config->vbus_gpio.gpio,
+                       (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+                                0 : 1);
+               debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
+                       (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+                               "low" : "high");
+       }
+}
+
+void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
+{
+       /* Reset the USB controller with 2us delay */
+       reset_periph(config->periph_id, 2);
+
+       /*
+        * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
+        * base address
+        */
+       if (config->has_legacy_mode)
+               setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
+
+       /* Put UTMIP1/3 in reset */
+       setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+       /* Enable the UTMIP PHY */
+       if (config->utmi)
+               setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
+}
+
+/* set up the UTMI USB controller with the parameters provided */
+static int init_utmi_usb_controller(struct fdt_usb *config)
 {
-       u32 our_hccr, our_hcor;
+       u32 val;
+       int loop_count;
+       const unsigned *timing;
+       struct usb_ctlr *usbctlr = config->reg;
+
+       clock_enable(config->periph_id);
+
+       /* Reset the usb controller */
+       usbf_reset_controller(config, usbctlr);
+
+       /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
+       clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+       /* Follow the crystal clock disable by >100ns delay */
+       udelay(1);
+
+       /*
+        * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
+        * mux must be switched to actually use a_sess_vld threshold.
+        */
+       if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+               clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
+                       VBUS_SENSE_CTL_MASK,
+                       VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
+       }
+
+       /*
+        * PLL Delay CONFIGURATION settings. The following parameters control
+        * the bring up of the plls.
+        */
+       timing = usb_pll[clock_get_osc_freq()];
+
+       val = readl(&usbctlr->utmip_misc_cfg1);
+       clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+               timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
+       clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+               timing[PARAM_ACTIVE_DELAY_COUNT] <<
+                       UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+       writel(val, &usbctlr->utmip_misc_cfg1);
+
+       /* Set PLL enable delay count and crystal frequency count */
+       val = readl(&usbctlr->utmip_pll_cfg1);
+       clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+               timing[PARAM_ENABLE_DELAY_COUNT] <<
+                       UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+       clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+               timing[PARAM_XTAL_FREQ_COUNT] <<
+                       UTMIP_XTAL_FREQ_COUNT_SHIFT);
+       writel(val, &usbctlr->utmip_pll_cfg1);
+
+       /* Setting the tracking length time */
+       clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
+               UTMIP_BIAS_PDTRK_COUNT_MASK,
+               timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
+
+       /* Program debounce time for VBUS to become valid */
+       clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
+               UTMIP_DEBOUNCE_CFG0_MASK,
+               timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
+
+       setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
+
+       /* Disable battery charge enabling bit */
+       setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
+
+       clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
+       setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
 
        /*
-        * Select the first port, as we don't have a way of selecting others
-        * yet
+        * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
+        * Setting these fields, together with default values of the
+        * other fields, results in programming the registers below as
+        * follows:
+        *         UTMIP_HSRX_CFG0 = 0x9168c000
+        *         UTMIP_HSRX_CFG1 = 0x13
         */
-       if (tegrausb_start_port(index, &our_hccr, &our_hcor))
+
+       /* Set PLL enable delay count and Crystal frequency count */
+       val = readl(&usbctlr->utmip_hsrx_cfg0);
+       clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
+               utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
+       clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
+               utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
+       writel(val, &usbctlr->utmip_hsrx_cfg0);
+
+       /* Configure the UTMIP_HS_SYNC_START_DLY */
+       clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
+               UTMIP_HS_SYNC_START_DLY_MASK,
+               utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
+
+       /* Preceed the crystal clock disable by >100ns delay. */
+       udelay(1);
+
+       /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
+       setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
+
+       /* Finished the per-controller init. */
+
+       /* De-assert UTMIP_RESET to bring out of reset. */
+       clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
+
+       /* Wait for the phy clock to become valid in 100 ms */
+       for (loop_count = 100000; loop_count != 0; loop_count--) {
+               if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+                       break;
+               udelay(1);
+       }
+       if (!loop_count)
+               return -1;
+
+       /* Disable ICUSB FS/LS transceiver */
+       clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+       /* Select UTMI parallel interface */
+       clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+                       PTS_UTMI << PTS_SHIFT);
+       clrbits_le32(&usbctlr->port_sc1, STS);
+
+       /* Deassert power down state */
+       clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
+               UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
+       clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
+               UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+
+       return 0;
+}
+
+#ifdef CONFIG_USB_ULPI
+/* if board file does not set a ULPI reference frequency we default to 24MHz */
+#ifndef CONFIG_ULPI_REF_CLK
+#define CONFIG_ULPI_REF_CLK 24000000
+#endif
+
+/* set up the ULPI USB controller with the parameters provided */
+static int init_ulpi_usb_controller(struct fdt_usb *config)
+{
+       u32 val;
+       int loop_count;
+       struct ulpi_viewport ulpi_vp;
+       struct usb_ctlr *usbctlr = config->reg;
+
+       /* set up ULPI reference clock on pllp_out4 */
+       clock_enable(PERIPH_ID_DEV2_OUT);
+       clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
+
+       /* reset ULPI phy */
+       if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
+               fdtdec_setup_gpio(&config->phy_reset_gpio);
+               gpio_direction_output(config->phy_reset_gpio.gpio, 0);
+               mdelay(5);
+               gpio_set_value(config->phy_reset_gpio.gpio, 1);
+       }
+
+       /* Reset the usb controller */
+       clock_enable(config->periph_id);
+       usbf_reset_controller(config, usbctlr);
+
+       /* enable pinmux bypass */
+       setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
+                       ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
+
+       /* Select ULPI parallel interface */
+       clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+
+       /* enable ULPI transceiver */
+       setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
+
+       /* configure ULPI transceiver timings */
+       val = 0;
+       writel(val, &usbctlr->ulpi_timing_ctrl_1);
+
+       val |= ULPI_DATA_TRIMMER_SEL(4);
+       val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
+       val |= ULPI_DIR_TRIMMER_SEL(4);
+       writel(val, &usbctlr->ulpi_timing_ctrl_1);
+       udelay(10);
+
+       val |= ULPI_DATA_TRIMMER_LOAD;
+       val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
+       val |= ULPI_DIR_TRIMMER_LOAD;
+       writel(val, &usbctlr->ulpi_timing_ctrl_1);
+
+       /* set up phy for host operation with external vbus supply */
+       ulpi_vp.port_num = 0;
+       ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
+
+       if (ulpi_init(&ulpi_vp)) {
+               printf("Tegra ULPI viewport init failed\n");
+               return -1;
+       }
+
+       ulpi_set_vbus(&ulpi_vp, 1, 1);
+       ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
+
+       /* enable wakeup events */
+       setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
+
+       /* Enable and wait for the phy clock to become valid in 100 ms */
+       setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
+       for (loop_count = 100000; loop_count != 0; loop_count--) {
+               if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+                       break;
+               udelay(1);
+       }
+       if (!loop_count)
+               return -1;
+       clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
+
+       return 0;
+}
+#else
+static int init_ulpi_usb_controller(struct fdt_usb *config)
+{
+       printf("No code to set up ULPI controller, please enable"
+                       "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
+       return -1;
+}
+#endif
+
+static void config_clock(const u32 timing[])
+{
+       clock_start_pll(CLOCK_ID_USB,
+               timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
+               timing[PARAM_CPCON], timing[PARAM_LFCON]);
+}
+
+int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
+{
+       const char *phy, *mode;
+
+       config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
+       mode = fdt_getprop(blob, node, "dr_mode", NULL);
+       if (mode) {
+               if (0 == strcmp(mode, "host"))
+                       config->dr_mode = DR_MODE_HOST;
+               else if (0 == strcmp(mode, "peripheral"))
+                       config->dr_mode = DR_MODE_DEVICE;
+               else if (0 == strcmp(mode, "otg"))
+                       config->dr_mode = DR_MODE_OTG;
+               else {
+                       debug("%s: Cannot decode dr_mode '%s'\n", __func__,
+                             mode);
+                       return -FDT_ERR_NOTFOUND;
+               }
+       } else {
+               config->dr_mode = DR_MODE_HOST;
+       }
+
+       phy = fdt_getprop(blob, node, "phy_type", NULL);
+       config->utmi = phy && 0 == strcmp("utmi", phy);
+       config->ulpi = phy && 0 == strcmp("ulpi", phy);
+       config->enabled = fdtdec_get_is_enabled(blob, node);
+       config->has_legacy_mode = fdtdec_get_bool(blob, node,
+                                                 "nvidia,has-legacy-mode");
+       config->periph_id = clock_decode_periph_id(blob, node);
+       if (config->periph_id == PERIPH_ID_NONE) {
+               debug("%s: Missing/invalid peripheral ID\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+       fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
+       fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
+                       &config->phy_reset_gpio);
+       debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
+               "vbus=%d, phy_reset=%d, dr_mode=%d\n",
+               config->enabled, config->has_legacy_mode, config->utmi,
+               config->ulpi, config->periph_id, config->vbus_gpio.gpio,
+               config->phy_reset_gpio.gpio, config->dr_mode);
+
+       return 0;
+}
+
+int board_usb_init(const void *blob)
+{
+       struct fdt_usb config;
+       enum clock_osc_freq freq;
+       int node_list[USB_PORTS_MAX];
+       int node, count, i;
+
+       /* Set up the USB clocks correctly based on our oscillator frequency */
+       freq = clock_get_osc_freq();
+       config_clock(usb_pll[freq]);
+
+       /* count may return <0 on error */
+       count = fdtdec_find_aliases_for_id(blob, "usb",
+                       COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
+       for (i = 0; i < count; i++) {
+               if (port_count == USB_PORTS_MAX) {
+                       printf("tegrausb: Cannot register more than %d ports\n",
+                               USB_PORTS_MAX);
+                       return -1;
+               }
+
+               debug("USB %d: ", i);
+               node = node_list[i];
+               if (!node)
+                       continue;
+               if (fdt_decode_usb(blob, node, &config)) {
+                       debug("Cannot decode USB node %s\n",
+                             fdt_get_name(blob, node, NULL));
+                       return -1;
+               }
+               config.initialized = 0;
+
+               /* add new USB port to the list of available ports */
+               port[port_count++] = config;
+       }
+
+       return 0;
+}
+
+/**
+ * Start up the given port number (ports are numbered from 0 on each board).
+ * This returns values for the appropriate hccr and hcor addresses to use for
+ * USB EHCI operations.
+ *
+ * @param index        port number to start
+ * @param hccr         returns start address of EHCI HCCR registers
+ * @param hcor         returns start address of EHCI HCOR registers
+ * @return 0 if ok, -1 on error (generally invalid port number)
+ */
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+       struct fdt_usb *config;
+       struct usb_ctlr *usbctlr;
+
+       if (index >= port_count)
                return -1;
 
-       *hccr = (struct ehci_hccr *)our_hccr;
-       *hcor = (struct ehci_hcor *)our_hcor;
+       config = &port[index];
+
+       /* skip init, if the port is already initialized */
+       if (config->initialized)
+               goto success;
+
+       if (config->utmi && init_utmi_usb_controller(config)) {
+               printf("tegrausb: Cannot init port %d\n", index);
+               return -1;
+       }
+
+       if (config->ulpi && init_ulpi_usb_controller(config)) {
+               printf("tegrausb: Cannot init port %d\n", index);
+               return -1;
+       }
 
+       set_host_mode(config);
+
+       config->initialized = 1;
+
+success:
+       usbctlr = config->reg;
+       *hccr = (struct ehci_hccr *)&usbctlr->cap_length;
+       *hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
        return 0;
 }
 
 /*
- * Destroy the appropriate control structures corresponding
- * the the EHCI host controller.
+ * Bring down the specified USB controller
  */
 int ehci_hcd_stop(int index)
 {
-       return tegrausb_stop_port(index);
+       struct usb_ctlr *usbctlr;
+
+       usbctlr = port[index].reg;
+
+       /* Stop controller */
+       writel(0, &usbctlr->usb_cmd);
+       udelay(1000);
+
+       /* Initiate controller reset */
+       writel(2, &usbctlr->usb_cmd);
+       udelay(1000);
+
+       port[index].initialized = 0;
+
+       return 0;
 }
index 922c78c..6f36153 100644 (file)
@@ -38,7 +38,8 @@ Please define CONFIG_ARCH_DEVICE_TREE))
 # We preprocess the device tree file provide a useful define
 DTS_CPPFLAGS := -x assembler-with-cpp \
                -DARCH_CPU_DTS=\"$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\" \
-               -DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\"
+               -DBOARD_DTS=\"$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\" \
+               -I$(SRCTREE)/board/$(VENDOR)/dts -I$(SRCTREE)/arch/$(ARCH)/dts
 
 all:   $(obj).depend $(LIB)
 
index bfb9680..9298d0e 100644 (file)
 #define CONFIG_EXT4_WRITE
 #endif
 
+/* Rather than repeat this expression each time, add a define for it */
+#if defined(CONFIG_CMD_IDE) || \
+       defined(CONFIG_CMD_SATA) || \
+       defined(CONFIG_CMD_SCSI) || \
+       defined(CONFIG_CMD_USB) || \
+       defined(CONFIG_CMD_PART) || \
+       defined(CONFIG_MMC) || \
+       defined(CONFIG_SYSTEMACE)
+#define HAVE_BLOCK_DEVICE
+#endif
+
 #endif /* __CONFIG_FALLBACKS_H */
index 1616b39..55dc83d 100644 (file)
 #define CONFIG_SYS_I2C_SPEED           100000
 #define CONFIG_CMD_I2C
 
-#define CONFIG_ENV_IS_NOWHERE
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET              ((512 * 1024) - CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_SYS_MMC_ENV_PART                2
 
 /* SPI */
 #define CONFIG_TEGRA_SLINK
index 0e5f281..856c860 100644 (file)
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
-/* File system support */
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
 /* USB host support */
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_TEGRA
index ce32c80..b1a6e34 100644 (file)
 #define CONFIG_MACH_TYPE               MACH_TYPE_DALMORE
 
 #define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_TEGRA_I2C
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS         TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_CMD_I2C
+
 #define CONFIG_ENV_IS_NOWHERE
 
 #define MACH_TYPE_DALMORE      4304    /* not yet in mach-types.h */
index 8d1fd47..0c73f86 100644 (file)
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-
 /* NAND support */
 #define CONFIG_CMD_NAND
 #define CONFIG_TEGRA_NAND
index bae4ba0..57a50d7 100644 (file)
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
 #define CONFIG_FIT
 
 #define CONFIG_BOOTCOMMAND                             \
index 2edb4aa..eac1ef9 100644 (file)
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
index deee237..4cfe88a 100644 (file)
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
 #define CONFIG_FIT
 
 #define CONFIG_BOOTCOMMAND                             \
index de0c777..f66173e 100644 (file)
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_OFFSET ((512 * 1024) - CONFIG_ENV_SIZE)
index caeb9cd..f90f5c7 100644 (file)
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-
 #define CONFIG_FIT
 
 #define CONFIG_BOOTCOMMAND                             \
index 4a656bb..4cc35e5 100644 (file)
@@ -21,8 +21,8 @@
  * MA 02111-1307 USA
  */
 
-#ifndef __TEGRA_COMMON_H
-#define __TEGRA_COMMON_H
+#ifndef _TEGRA_COMMON_H_
+#define _TEGRA_COMMON_H_
 #include <asm/sizes.h>
 #include <linux/stringify.h>
 
 #define CONFIG_SYS_MALLOC_LEN          (4 << 20)       /* 4MB  */
 
 /*
- * PllX Configuration
+ * NS16550 Configuration
  */
-#define CONFIG_SYS_CPU_OSC_FREQUENCY   1000000 /* Set CPU clock to 1GHz */
-
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    (-4)
 #define CONFIG_COMMAND_HISTORY
 #define CONFIG_AUTO_COMPLETE
 
+/* turn on commonly used storage-related commands */
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_FS_EXT4
+#define CONFIG_FS_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_PART
+
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
 
+/* Misc utility code */
+#define CONFIG_BOUNCE_BUFFER
+
 #endif /* _TEGRA_COMMON_H_ */
index 0033530..c2986d8 100644 (file)
@@ -76,4 +76,7 @@
 
 #define CONFIG_SPL_LDSCRIPT            "$(CPUDIR)/tegra114/u-boot-spl.lds"
 
+/* Total I2C ports on Tegra114 */
+#define TEGRA_I2C_NUM_CONTROLLERS      5
+
 #endif /* _TEGRA114_COMMON_H_ */
index 186e023..e464e06 100644 (file)
 /* Total I2C ports on Tegra20 */
 #define TEGRA_I2C_NUM_CONTROLLERS      4
 
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
-
 #define CONFIG_SYS_NAND_SELF_INIT
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
-/* Misc utility code */
-#define CONFIG_BOUNCE_BUFFER
-
 #endif /* _TEGRA20_COMMON_H_ */
index 334d3a3..0644f7a 100644 (file)
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-
 /* Environment in SPI */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_MAX_HZ          48000000
index b55ebc9..5755f11 100644 (file)
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_OFFSET ((1024 * 1024) - CONFIG_ENV_SIZE)
index 1e554d8..9542c7e 100644 (file)
 #define CONFIG_TEGRA_MMC
 #define CONFIG_CMD_MMC
 
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#define CONFIG_FS_EXT4
-#define CONFIG_FS_FAT
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-
 /*
  * Environment in eMMC, at the end of 2nd "boot sector". Note: This assumes
  * the user plugged the standard 8MB MoviNAND card into J29/HSMMC/POP. If
index 77f244f..2189483 100644 (file)
@@ -62,6 +62,7 @@ struct fdt_memory {
 enum fdt_compat_id {
        COMPAT_UNKNOWN,
        COMPAT_NVIDIA_TEGRA20_USB,      /* Tegra20 USB port */
+       COMPAT_NVIDIA_TEGRA114_I2C,     /* Tegra114 I2C w/single clock source */
        COMPAT_NVIDIA_TEGRA20_I2C,      /* Tegra20 i2c */
        COMPAT_NVIDIA_TEGRA20_DVC,      /* Tegra20 dvc (really just i2c) */
        COMPAT_NVIDIA_TEGRA20_EMC,      /* Tegra20 memory controller */
@@ -70,6 +71,8 @@ enum fdt_compat_id {
        COMPAT_NVIDIA_TEGRA20_NAND,     /* Tegra2 NAND controller */
        COMPAT_NVIDIA_TEGRA20_PWM,      /* Tegra 2 PWM controller */
        COMPAT_NVIDIA_TEGRA20_DC,       /* Tegra 2 Display controller */
+       COMPAT_NVIDIA_TEGRA30_SDMMC,    /* Tegra30 SDMMC controller */
+       COMPAT_NVIDIA_TEGRA20_SDMMC,    /* Tegra20 SDMMC controller */
        COMPAT_NVIDIA_TEGRA20_SFLASH,   /* Tegra 2 SPI flash controller */
        COMPAT_NVIDIA_TEGRA20_SLINK,    /* Tegra 2 SPI SLINK controller */
        COMPAT_SMSC_LAN9215,            /* SMSC 10/100 Ethernet LAN9215 */
index 3ae348d..43f29f5 100644 (file)
@@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static const char * const compat_names[COMPAT_COUNT] = {
        COMPAT(UNKNOWN, "<none>"),
        COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
+       COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"),
        COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
        COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
        COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
@@ -45,6 +46,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
        COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
        COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
        COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+       COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
+       COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
        COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),
        COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"),
        COMPAT(SMSC_LAN9215, "smsc,lan9215"),