Merge branch 'master' of git://git.denx.de/u-boot-video
authorTom Rini <trini@ti.com>
Tue, 25 Sep 2012 23:18:22 +0000 (16:18 -0700)
committerTom Rini <trini@ti.com>
Tue, 25 Sep 2012 23:18:22 +0000 (16:18 -0700)
422 files changed:
.gitignore
MAINTAINERS
MAKEALL
Makefile
README
arch/arm/cpu/arm1136/mx31/generic.c
arch/arm/cpu/arm1136/mx31/timer.c
arch/arm/cpu/arm1136/mx35/generic.c
arch/arm/cpu/arm1136/mx35/timer.c
arch/arm/cpu/arm1176/bcm2835/Makefile
arch/arm/cpu/arm1176/bcm2835/init.c [new file with mode: 0644]
arch/arm/cpu/arm1176/cpu.c
arch/arm/cpu/arm720t/tegra20/cpu.c
arch/arm/cpu/arm926ejs/mx25/generic.c
arch/arm/cpu/arm926ejs/mx25/timer.c
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
arch/arm/cpu/arm926ejs/orion5x/cpu.c
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/tegra20/cmd_enterrcm.c
arch/arm/cpu/armv7/tegra20/usb.c
arch/arm/cpu/tegra20-common/Makefile
arch/arm/cpu/tegra20-common/ap20.c
arch/arm/cpu/tegra20-common/board.c
arch/arm/cpu/tegra20-common/funcmux.c
arch/arm/cpu/tegra20-common/warmboot.c
arch/arm/cpu/tegra20-common/warmboot_avp.c
arch/arm/dts/tegra20.dtsi
arch/arm/imx-common/Makefile [moved from arch/arm/cpu/armv7/imx-common/Makefile with 94% similarity]
arch/arm/imx-common/cmd_bmode.c [moved from arch/arm/cpu/armv7/imx-common/cmd_bmode.c with 100% similarity]
arch/arm/imx-common/cpu.c [moved from arch/arm/cpu/armv7/imx-common/cpu.c with 100% similarity]
arch/arm/imx-common/i2c-mxv7.c [moved from arch/arm/cpu/armv7/imx-common/i2c.c with 100% similarity]
arch/arm/imx-common/iomux-v3.c [moved from arch/arm/cpu/armv7/imx-common/iomux-v3.c with 100% similarity]
arch/arm/imx-common/speed.c [moved from arch/arm/cpu/armv7/imx-common/speed.c with 100% similarity]
arch/arm/imx-common/timer.c [moved from arch/arm/cpu/armv7/imx-common/timer.c with 100% similarity]
arch/arm/include/asm/arch-exynos/mmc.h
arch/arm/include/asm/arch-kirkwood/spi.h
arch/arm/include/asm/arch-mx25/clock.h
arch/arm/include/asm/arch-mx31/clock.h
arch/arm/include/asm/arch-mx35/clock.h
arch/arm/include/asm/arch-mx35/crm_regs.h
arch/arm/include/asm/arch-mx6/iomux.h
arch/arm/include/asm/arch-omap24xx/omap2420.h
arch/arm/include/asm/arch-omap3/dss.h
arch/arm/include/asm/arch-omap3/mux.h
arch/arm/include/asm/arch-omap4/cpu.h
arch/arm/include/asm/arch-omap4/i2c.h
arch/arm/include/asm/arch-s5pc1xx/mmc.h
arch/arm/include/asm/arch-tegra20/ap20.h
arch/arm/include/asm/arch-tegra20/funcmux.h
arch/arm/include/asm/arch-tegra20/mmc.h
arch/arm/include/asm/arch-tegra20/sys_proto.h
arch/arm/include/asm/arch-tegra20/tegra20.h
arch/arm/include/asm/arch-tegra20/tegra_mmc.h [moved from drivers/mmc/tegra_mmc.h with 96% similarity]
arch/arm/include/asm/arch-tegra20/tegra_spi.h
arch/arm/include/asm/arch-tegra20/timer.h
arch/arm/lib/board.c
arch/m68k/cpu/mcf5227x/cpu.c
arch/m68k/cpu/mcf5227x/cpu_init.c
arch/m68k/cpu/mcf5227x/interrupts.c
arch/m68k/cpu/mcf5227x/speed.c
arch/m68k/cpu/mcf523x/cpu.c
arch/m68k/cpu/mcf523x/cpu_init.c
arch/m68k/cpu/mcf523x/interrupts.c
arch/m68k/cpu/mcf523x/speed.c
arch/m68k/cpu/mcf52x2/cpu.c
arch/m68k/cpu/mcf52x2/cpu_init.c
arch/m68k/cpu/mcf52x2/interrupts.c
arch/m68k/cpu/mcf52x2/speed.c
arch/m68k/cpu/mcf532x/cpu.c
arch/m68k/cpu/mcf532x/cpu_init.c
arch/m68k/cpu/mcf532x/interrupts.c
arch/m68k/cpu/mcf532x/speed.c
arch/m68k/cpu/mcf5445x/cpu.c
arch/m68k/cpu/mcf5445x/cpu_init.c
arch/m68k/cpu/mcf5445x/interrupts.c
arch/m68k/cpu/mcf5445x/pci.c
arch/m68k/cpu/mcf5445x/speed.c
arch/m68k/cpu/mcf547x_8x/cpu.c
arch/m68k/cpu/mcf547x_8x/cpu_init.c
arch/m68k/cpu/mcf547x_8x/interrupts.c
arch/m68k/cpu/mcf547x_8x/pci.c
arch/m68k/cpu/mcf547x_8x/slicetimer.c
arch/m68k/include/asm/bitops.h
arch/m68k/include/asm/coldfire/flexbus.h
arch/m68k/include/asm/coldfire/qspi.h
arch/m68k/include/asm/io.h
arch/m68k/include/asm/m5271.h
arch/microblaze/config.mk
arch/microblaze/cpu/interrupts.c
arch/microblaze/cpu/start.S
arch/microblaze/cpu/timer.c
arch/microblaze/cpu/u-boot.lds
arch/microblaze/include/asm/global_data.h
arch/microblaze/include/asm/microblaze_intc.h
arch/microblaze/include/asm/microblaze_timer.h
arch/microblaze/include/asm/processor.h
arch/microblaze/lib/board.c
arch/mips/config.mk
arch/mips/cpu/mips32/config.mk
arch/mips/cpu/xburst/config.mk
arch/mips/cpu/xburst/cpu.c
arch/mips/cpu/xburst/timer.c
arch/mips/lib/Makefile
arch/mips/lib/ashldi3.c [new file with mode: 0644]
arch/mips/lib/ashrdi3.c [new file with mode: 0644]
arch/mips/lib/libgcc.h [new file with mode: 0644]
arch/mips/lib/lshrdi3.c [new file with mode: 0644]
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
arch/powerpc/cpu/mpc85xx/p3060_ids.c [deleted file]
arch/powerpc/cpu/mpc85xx/p3060_serdes.c [deleted file]
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
arch/powerpc/cpu/mpc8xxx/ddr/main.c
arch/powerpc/cpu/mpc8xxx/ddr/options.c
arch/powerpc/cpu/mpc8xxx/ddr/util.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
arch/powerpc/cpu/mpc8xxx/srio.c
arch/powerpc/include/asm/config.h
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_ddr_dimm_params.h
arch/powerpc/include/asm/fsl_ddr_sdram.h
arch/powerpc/include/asm/fsl_ifc.h
arch/powerpc/include/asm/fsl_law.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/fsl_srio.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/io.h
arch/powerpc/include/asm/mmu.h
arch/powerpc/include/asm/mp.h
arch/powerpc/include/asm/processor.h
arch/powerpc/lib/board.c
arch/sparc/cpu/leon2/interrupts.c
arch/sparc/cpu/leon3/interrupts.c
arch/sparc/lib/board.c
board/BuS/eb_cpux9k2/cpux9k2.c
board/Marvell/sheevaplug/kwbimage.cfg
board/apollon/apollon.c [deleted file]
board/apollon/config.mk [deleted file]
board/apollon/lowlevel_init.S [deleted file]
board/apollon/mem.c [deleted file]
board/apollon/mem.h [deleted file]
board/apollon/sys_info.c [deleted file]
board/atmel/atngw100mkii/Makefile [moved from board/apollon/Makefile with 67% similarity]
board/atmel/atngw100mkii/atngw100mkii.c [new file with mode: 0644]
board/avionic-design/common/tamonten.c
board/avionic-design/dts/tegra20-tec.dts
board/buffalo/lsxl/lsxl.c
board/compal/paz00/paz00.c
board/compulab/trimslice/trimslice.c
board/freescale/common/Makefile
board/freescale/common/fman.c
board/freescale/common/fman.h
board/freescale/common/p_corenet/law.c
board/freescale/common/p_corenet/tlb.c
board/freescale/corenet_ds/eth_p4080.c
board/freescale/corenet_ds/pbi.cfg [new file with mode: 0644]
board/freescale/corenet_ds/rcw_p3041ds.cfg [new file with mode: 0644]
board/freescale/corenet_ds/rcw_p4080ds.cfg [new file with mode: 0644]
board/freescale/corenet_ds/rcw_p5020ds.cfg [new file with mode: 0644]
board/freescale/m5208evbe/m5208evbe.c
board/freescale/m52277evb/m52277evb.c
board/freescale/m5235evb/m5235evb.c
board/freescale/m5253demo/m5253demo.c
board/freescale/m5253evbe/m5253evbe.c
board/freescale/m5272c3/m5272c3.c
board/freescale/m5275evb/m5275evb.c
board/freescale/m53017evb/m53017evb.c
board/freescale/m5329evb/m5329evb.c
board/freescale/m5329evb/nand.c
board/freescale/m5373evb/m5373evb.c
board/freescale/m5373evb/nand.c
board/freescale/m54451evb/m54451evb.c
board/freescale/m54455evb/m54455evb.c
board/freescale/m547xevb/m547xevb.c
board/freescale/m548xevb/m548xevb.c
board/freescale/mpc8308rdb/mpc8308rdb.c
board/freescale/mpc8540ads/mpc8540ads.c
board/freescale/mpc8541cds/mpc8541cds.c
board/freescale/mpc8555cds/mpc8555cds.c
board/freescale/mpc8560ads/mpc8560ads.c
board/freescale/mx28evk/iomux.c
board/freescale/mx28evk/mx28evk.c
board/freescale/mx35pdk/README
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx6qsabrelite/mx6qsabrelite.c
board/freescale/p1010rdb/ddr.c
board/freescale/p1_p2_rdb_pc/law.c
board/freescale/p3060qds/README [deleted file]
board/freescale/p3060qds/ddr.c [deleted file]
board/freescale/p3060qds/eth.c [deleted file]
board/freescale/p3060qds/fixed_ddr.c [deleted file]
board/freescale/p3060qds/p3060qds.c [deleted file]
board/freescale/p3060qds/p3060qds_qixis.h [deleted file]
board/genesi/mx51_efikamx/Makefile
board/genesi/mx51_efikamx/efikamx-usb.c
board/genesi/mx51_efikamx/efikamx.c
board/keymile/common/ivm.c
board/keymile/km_arm/km_arm.c
board/nvidia/common/board.c
board/nvidia/dts/tegra20-harmony.dts
board/nvidia/dts/tegra20-seaboard.dts
board/nvidia/harmony/Makefile
board/nvidia/harmony/harmony.c
board/nvidia/seaboard/Makefile
board/nvidia/seaboard/seaboard.c
board/nvidia/ventana/Makefile
board/nvidia/whistler/Makefile
board/nvidia/whistler/whistler.c
board/qi/qi_lb60/qi_lb60.c
board/samsung/common/Makefile [moved from board/freescale/p3060qds/Makefile with 72% similarity]
board/samsung/common/multi_i2c.c [new file with mode: 0644]
board/samsung/goni/lowlevel_init.S
board/samsung/smdkc100/lowlevel_init.S
board/samsung/trats/trats.c
board/taskit/stamp9g20/stamp9g20.c
board/technexion/twister/twister.c
board/teejet/mt_ventoux/mt_ventoux.c
board/teejet/mt_ventoux/mt_ventoux.h
board/xilinx/microblaze-generic/microblaze-generic.c
boards.cfg
common/Makefile
common/cmd_bdinfo.c
common/cmd_disk.c [new file with mode: 0644]
common/cmd_ext2.c
common/cmd_ext4.c [new file with mode: 0644]
common/cmd_ext_common.c [new file with mode: 0644]
common/cmd_fat.c
common/cmd_fdt.c
common/cmd_ide.c
common/cmd_mmc.c
common/cmd_nand.c
common/cmd_nvedit.c
common/cmd_part.c [new file with mode: 0644]
common/cmd_reiser.c
common/cmd_scsi.c
common/cmd_usb.c
common/cmd_zfs.c
common/dlmalloc.c
common/env_common.c
common/env_mmc.c
common/env_nand.c
common/env_remote.c
common/image.c
common/usb_hub.c
disk/part.c
disk/part_dos.c
disk/part_dos.h
disk/part_efi.c
doc/README.ext4 [new file with mode: 0644]
doc/README.fsl-ddr
doc/README.kwbimage
doc/README.nand
doc/README.pblimage [new file with mode: 0644]
doc/README.scrapyard
doc/README.srio-boot-corenet [deleted file]
doc/README.srio-pcie-boot-corenet [new file with mode: 0644]
doc/device-tree-bindings/nand/nvidia,tegra20-nand.txt [new file with mode: 0644]
drivers/block/systemace.c
drivers/dfu/dfu_mmc.c
drivers/gpio/tegra_gpio.c
drivers/i2c/omap24xx_i2c.c
drivers/i2c/tegra_i2c.c
drivers/input/Makefile
drivers/misc/fsl_law.c
drivers/mmc/arm_pl180_mmci.c
drivers/mmc/mmc.c
drivers/mmc/mxsmmc.c
drivers/mmc/pxa_mmc_gen.c
drivers/mmc/s5p_sdhci.c
drivers/mmc/sdhci.c
drivers/mmc/sh_mmcif.c
drivers/mmc/tegra_mmc.c
drivers/mtd/nand/Makefile
drivers/mtd/nand/mxc_nand.c
drivers/mtd/nand/mxs_nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_util.c
drivers/mtd/nand/tegra_nand.c [new file with mode: 0644]
drivers/mtd/nand/tegra_nand.h [new file with mode: 0644]
drivers/net/fm/Makefile
drivers/net/fm/init.c
drivers/net/fm/p3060.c [deleted file]
drivers/net/greth.c
drivers/pci/fsl_pci_init.c
drivers/pci/pci.c
drivers/pci/pci_auto.c
drivers/qe/uec.c
drivers/serial/serial_xuartlite.c
drivers/spi/Makefile
drivers/spi/cf_qspi.c [new file with mode: 0644]
drivers/spi/kirkwood_spi.c
drivers/spi/mpc8xxx_spi.c
drivers/spi/mxs_spi.c
drivers/spi/tegra_spi.c
drivers/spi/xilinx_spi.c
drivers/usb/host/ehci-hcd.c
drivers/video/omap3_dss.c
fs/Makefile
fs/ext2/dev.c [deleted file]
fs/ext2/ext2fs.c [deleted file]
fs/ext4/Makefile [moved from fs/ext2/Makefile with 86% similarity]
fs/ext4/crc16.c [new file with mode: 0644]
fs/ext4/crc16.h [new file with mode: 0644]
fs/ext4/dev.c [new file with mode: 0644]
fs/ext4/ext4_common.c [new file with mode: 0644]
fs/ext4/ext4_common.h [new file with mode: 0644]
fs/ext4/ext4_journal.c [new file with mode: 0644]
fs/ext4/ext4_journal.h [new file with mode: 0644]
fs/ext4/ext4fs.c [new file with mode: 0644]
fs/fat/fat.c
fs/reiserfs/dev.c
fs/ubifs/ubifs.c
fs/zfs/dev.c
include/asm-generic/gpio.h
include/command.h
include/configs/M5373EVB.h
include/configs/MPC8308RDB.h
include/configs/P2041RDB.h
include/configs/P3060QDS.h [deleted file]
include/configs/P4080DS.h
include/configs/P5020DS.h
include/configs/apollon.h [deleted file]
include/configs/atngw100mkii.h [new file with mode: 0644]
include/configs/corenet_ds.h
include/configs/eb_cpux9k2.h
include/configs/edminiv2.h
include/configs/flea3.h
include/configs/harmony.h
include/configs/ima3-mx53.h
include/configs/imx31_litekit.h
include/configs/imx31_phycore.h
include/configs/integrator-common.h [new file with mode: 0644]
include/configs/integratorap.h
include/configs/integratorcp.h
include/configs/km/keymile-common.h
include/configs/km/km_arm.h
include/configs/m28evk.h
include/configs/medcom.h
include/configs/microblaze-generic.h
include/configs/mt_ventoux.h
include/configs/mx25pdk.h
include/configs/mx28evk.h
include/configs/mx31ads.h
include/configs/mx31pdk.h
include/configs/mx35pdk.h
include/configs/p1_p2_rdb_pc.h
include/configs/paz00.h
include/configs/plutux.h
include/configs/qemu-mips.h
include/configs/qi_lb60.h
include/configs/qong.h
include/configs/sc_sps_1.h
include/configs/seaboard.h
include/configs/stamp9g20.h
include/configs/tam3517-common.h
include/configs/tec.h
include/configs/tegra-common-post.h [moved from include/configs/tegra20-common-post.h with 96% similarity]
include/configs/tegra20-common.h
include/configs/trats.h
include/configs/trimslice.h
include/configs/tt01.h
include/configs/tx25.h
include/configs/ventana.h
include/configs/whistler.h
include/configs/zmx25.h
include/ddr_spd.h
include/environment.h
include/ext2fs.h [deleted file]
include/ext4fs.h [new file with mode: 0644]
include/ext_common.h [new file with mode: 0644]
include/fdtdec.h
include/fm_eth.h
include/fsl_nfc.h
include/i2c.h
include/image.h
include/linux/mtd/nand.h
include/mmc.h
include/nand.h
include/part.h
include/reiserfs.h
include/sdhci.h
include/search.h
include/serial.h
include/zfs_common.h
lib/fdtdec.c
lib/hashtable.c
nand_spl/board/freescale/common.c [moved from onenand_ipl/onenand_boot.c with 56% similarity]
nand_spl/board/freescale/p1010rdb/Makefile
nand_spl/board/freescale/p1010rdb/nand_boot.c
nand_spl/board/freescale/p1023rds/Makefile
nand_spl/board/freescale/p1023rds/nand_boot.c
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
nand_spl/nand_boot_fsl_elbc.c
nand_spl/nand_boot_fsl_nfc.c
onenand_ipl/board/apollon/Makefile [deleted file]
onenand_ipl/board/apollon/apollon.c [deleted file]
onenand_ipl/board/apollon/config.mk [deleted file]
onenand_ipl/board/apollon/low_levelinit.S [deleted file]
onenand_ipl/board/apollon/u-boot.onenand.lds [deleted file]
onenand_ipl/onenand_ipl.h [deleted file]
onenand_ipl/onenand_read.c [deleted file]
spl/Makefile
tools/Makefile
tools/env/fw_env.c
tools/mkimage.c
tools/mkimage.h
tools/pblimage.c [new file with mode: 0644]
tools/pblimage.h [moved from board/freescale/p3060qds/p3060qds.h with 60% similarity]

index 2e6fde8..d91e91b 100644 (file)
@@ -75,10 +75,5 @@ cscope.*
 /ctags
 /etags
 
-# OneNAND IPL files
-/onenand_ipl/onenand-ipl*
-/onenand_ipl/board/*/onenand*
-/onenand_ipl/board/*/*.S
-
 # spl ais files
 /spl/*.ais
index 4aabcff..aa54fe1 100644 (file)
@@ -777,10 +777,6 @@ Nagendra T S  <nagendra@mistralsolutions.com>
 
    am3517_crane    ARM ARMV7 (AM35x SoC)
 
-Kyungmin Park <kyungmin.park@samsung.com>
-
-       apollon         ARM1136EJS
-
 Sandeep Paulraj <s-paulraj@ti.com>
 
        davinci_dm355evm        ARM926EJS
@@ -1112,6 +1108,7 @@ Wolfgang Wegner <w.wegner@astro-kom.de>
 
 Andreas Bießmann <andreas.devel@googlemail.com>
        grasshopper             AT32AP7000
+       atngw100mkii            AT32AP7000
 
 Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
 
diff --git a/MAKEALL b/MAKEALL
index eb7dd02..806f21f 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -333,6 +333,12 @@ LIST_ppc="         \
 
 LIST_SA="$(boards_by_cpu sa1100)"
 
+#########################################################################
+## ARM7 Systems
+#########################################################################
+
+LIST_ARM7="$(boards_by_cpu arm720t)"
+
 #########################################################################
 ## ARM9 Systems
 #########################################################################
@@ -340,12 +346,15 @@ LIST_SA="$(boards_by_cpu sa1100)"
 LIST_ARM9="$(boards_by_cpu arm920t)    \
        $(boards_by_cpu arm926ejs)      \
        $(boards_by_cpu arm925t)        \
+       $(boards_by_cpu arm946es)       \
 "
 
 #########################################################################
 ## ARM11 Systems
 #########################################################################
-LIST_ARM11="$(boards_by_cpu arm1136)"
+LIST_ARM11="$(boards_by_cpu arm1136)   \
+       $(boards_by_cpu arm1176)        \
+"
 
 #########################################################################
 ## ARMV7 Systems
@@ -371,16 +380,7 @@ LIST_ixp="$(boards_by_cpu ixp)"
 ## ARM groups
 #########################################################################
 
-LIST_arm="                     \
-       ${LIST_SA}              \
-       ${LIST_ARM9}            \
-       ${LIST_ARM10}           \
-       ${LIST_ARM11}           \
-       ${LIST_ARMV7}   \
-       ${LIST_at91}            \
-       ${LIST_pxa}             \
-       ${LIST_ixp}             \
-"
+LIST_arm="$(boards_by_arch arm)"
 
 #########################################################################
 ## MIPS Systems                (default = big endian)
@@ -388,6 +388,9 @@ LIST_arm="                  \
 
 LIST_mips4kc="         \
        incaip          \
+       incaip_100MHz   \
+       incaip_133MHz   \
+       incaip_150MHz   \
        qemu_mips       \
        vct_platinum    \
        vct_platinum_small      \
@@ -461,14 +464,7 @@ LIST_microblaze="$(boards_by_arch microblaze)"
 ## ColdFire Systems
 #########################################################################
 
-LIST_m68k="$(boards_by_arch m68k)
-       EB+MCF-EV123            \
-       EB+MCF-EV123_internal   \
-       M52277EVB               \
-       M5235EVB                \
-       M54451EVB               \
-       M54455EVB               \
-"
+LIST_m68k="$(boards_by_arch m68k)"
 LIST_coldfire=${LIST_m68k}
 
 #########################################################################
index 058fb53..cbab571 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -22,9 +22,9 @@
 #
 
 VERSION = 2012
-PATCHLEVEL = 07
+PATCHLEVEL = 10
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 else
@@ -242,9 +242,15 @@ LIBS-y += arch/arm/cpu/ixp/npe/libnpe.o
 endif
 LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
 LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o fs/fat/libfat.o fs/fdos/libfdos.o fs/jffs2/libjffs2.o \
-       fs/reiserfs/libreiserfs.o fs/ext2/libext2fs.o fs/yaffs2/libyaffs2.o \
-       fs/ubifs/libubifs.o fs/zfs/libzfs.o
+LIBS-y += fs/cramfs/libcramfs.o \
+       fs/ext4/libext4fs.o \
+       fs/fat/libfat.o \
+       fs/fdos/libfdos.o \
+       fs/jffs2/libjffs2.o \
+       fs/reiserfs/libreiserfs.o \
+       fs/ubifs/libubifs.o \
+       fs/yaffs2/libyaffs2.o \
+       fs/zfs/libzfs.o
 LIBS-y += net/libnet.o
 LIBS-y += disk/libdisk.o
 LIBS-y += drivers/bios_emulator/libatibiosemu.o
@@ -307,11 +313,8 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-ifeq ($(SOC),mx5)
-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
-endif
-ifeq ($(SOC),mx6)
-LIBS-y += $(CPUDIR)/imx-common/libimx-common.o
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
 endif
 
 ifeq ($(SOC),s5pc1xx)
@@ -378,7 +381,6 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
-ONENAND_BIN ?= $(obj)onenand_ipl/onenand-ipl-2k.bin
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 
@@ -436,6 +438,11 @@ $(obj)u-boot.kwb:       $(obj)u-boot.bin
                $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
                -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
 
+$(obj)u-boot.pbl:      $(obj)u-boot.bin
+               $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \
+               -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \
+               -d $< $@
+
 $(obj)u-boot.sha1:     $(obj)u-boot.bin
                $(obj)tools/ubsha1 $(obj)u-boot.bin
 
@@ -550,12 +557,6 @@ nand_spl:  $(TIMESTAMP_FILE) $(VERSION_FILE) depend
 $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
                cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
 
-onenand_ipl:   $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
-               $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all
-
-$(obj)u-boot-onenand.bin:      onenand_ipl $(obj)u-boot.bin
-               cat $(ONENAND_BIN) $(obj)u-boot.bin > $(obj)u-boot-onenand.bin
-
 $(obj)spl/u-boot-spl.bin:      $(SUBDIR_TOOLS) depend
                $(MAKE) -C spl all
 
@@ -777,6 +778,7 @@ clean:
               $(obj)tools/gen_eth_addr    $(obj)tools/img2srec           \
               $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk         \
               $(obj)tools/mk{smdk5250,}spl                               \
+              $(obj)tools/mxsboot                                        \
               $(obj)tools/ncb             $(obj)tools/ubsha1
        @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image}        \
               $(obj)board/matrix_vision/*/bootscript.img                 \
@@ -790,9 +792,7 @@ clean:
        @rm -f $(obj)include/generated/asm-offsets.h
        @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
        @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
-       @rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
        @rm -f $(ONENAND_BIN)
-       @rm -f $(obj)onenand_ipl/u-boot.lds
        @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
        @rm -f $(obj)MLO
        @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -813,6 +813,7 @@ clobber:    tidy
                $(obj)cscope.* $(obj)*.*~
        @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y)
        @rm -f $(obj)u-boot.kwb
+       @rm -f $(obj)u-boot.pbl
        @rm -f $(obj)u-boot.imx
        @rm -f $(obj)u-boot.ubl
        @rm -f $(obj)u-boot.ais
@@ -825,7 +826,6 @@ clobber:    tidy
        @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
        @rm -fr $(obj)include/generated
        @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
-       @[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f
        @rm -f $(obj)dts/*.tmp
        @rm -f $(obj)spl/u-boot-spl{,-pad}.ais
 
diff --git a/README b/README
index 4428205..5793b0a 100644 (file)
--- a/README
+++ b/README
@@ -383,6 +383,31 @@ The following options need to be configured:
                symbol should be set to the TLB1 entry to be used for this
                purpose.
 
+               CONFIG_SYS_FSL_ERRATUM_A004510
+
+               Enables a workaround for erratum A004510.  If set,
+               then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
+               CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
+
+               CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
+               CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
+
+               Defines one or two SoC revisions (low 8 bits of SVR)
+               for which the A004510 workaround should be applied.
+
+               The rest of SVR is either not relevant to the decision
+               of whether the erratum is present (e.g. p2040 versus
+               p2041) or is implied by the build target, which controls
+               whether CONFIG_SYS_FSL_ERRATUM_A004510 is set.
+
+               See Freescale App Note 4493 for more information about
+               this erratum.
+
+               CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+
+               This is the value to write into CCSR offset 0x18600
+               according to the A004510 workaround.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -3100,12 +3125,12 @@ to save the current settings.
          These two #defines specify the address and size of the
          environment area within the remote memory space. The
          local device can get the environment from remote memory
-         space by SRIO or other links.
+         space by SRIO or PCIE links.
 
 BE CAREFUL! For some special cases, the local device can not use
 "saveenv" command. For example, the local device will get the
-environment stored in a remote NOR flash by SRIO link, but it can
-not erase, write this NOR flash by SRIO interface.
+environment stored in a remote NOR flash by SRIO or PCIE link,
+but it can not erase, write this NOR flash by SRIO or PCIE interface.
 
 - CONFIG_ENV_IS_IN_NAND:
 
@@ -3553,9 +3578,9 @@ within that device.
 - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
        Specifies that QE/FMAN firmware is located in the remote (master)
        memory space.   CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
-       can be mapped from slave TLB->slave LAW->slave SRIO outbound window
-       ->master inbound window->master LAW->the ucode address in master's
-       NOR flash.
+       can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
+       window->master inbound window->master LAW->the ucode address in
+       master's memory space.
 
 Building the Software:
 ======================
index 8873fb7..93f429c 100644 (file)
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
        u32 mfi = GET_PLL_MFI(reg);
-       u32 mfn = GET_PLL_MFN(reg);
+       s32 mfn = GET_PLL_MFN(reg);
        u32 mfd = GET_PLL_MFD(reg);
        u32 pd =  GET_PLL_PD(reg);
 
        mfi = mfi <= 5 ? 5 : mfi;
+       mfn = mfn >= 512 ? mfn - 1024 : mfn;
        mfd += 1;
        pd += 1;
 
-       return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
-               (mfd * pd)) << 10;
+       return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+               mfd * pd);
 }
 
 static u32 mx31_get_mpl_dpdgck_clk(void)
@@ -47,9 +49,9 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
        u32 infreq;
 
        if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
-               infreq = CONFIG_MX31_CLK32 * 1024;
+               infreq = MXC_CLK32 * 1024;
        else
-               infreq = CONFIG_MX31_HCLK_FREQ;
+               infreq = MXC_HCLK;
 
        return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
index 72081a8..36266da 100644 (file)
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <div64.h>
 #include <watchdog.h>
 #include <asm/io.h>
@@ -53,28 +54,27 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, CONFIG_MX31_CLK32);
+       do_div(tick, MXC_CLK32);
        return tick;
 }
 
 static inline unsigned long long time_to_tick(unsigned long long time)
 {
-       time *= CONFIG_MX31_CLK32;
+       time *= MXC_CLK32;
        do_div(time, CONFIG_SYS_HZ);
        return time;
 }
 
 static inline unsigned long long us_to_tick(unsigned long long us)
 {
-       us = us * CONFIG_MX31_CLK32 + 999999;
+       us = us * MXC_CLK32 + 999999;
        do_div(us, 1000000);
        return us;
 }
 #else
 /* ~2% error */
-#define TICK_PER_TIME  ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
-                                                       / CONFIG_SYS_HZ)
-#define US_PER_TICK    (1000000 / CONFIG_MX31_CLK32)
+#define TICK_PER_TIME  ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK    (1000000 / MXC_CLK32)
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -128,7 +128,7 @@ ulong get_timer_masked(void)
 {
        /*
         * get_ticks() returns a long long (64 bit), it wraps in
-        * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+        * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
         * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
         * 5 * 10^6 days - long enough.
         */
@@ -159,7 +159,7 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-       return CONFIG_MX31_CLK32;
+       return MXC_CLK32;
 }
 
 void reset_cpu(ulong addr)
index d435e8a..ef65176 100644 (file)
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/arch/imx-regs.h>
@@ -129,15 +130,17 @@ static int get_ahb_div(u32 pdr0)
 static u32 decode_pll(u32 reg, u32 infreq)
 {
        u32 mfi = (reg >> 10) & 0xf;
-       u32 mfn = reg & 0x3f;
-       u32 mfd = (reg >> 16) & 0x3f;
+       s32 mfn = reg & 0x3ff;
+       u32 mfd = (reg >> 16) & 0x3ff;
        u32 pd = (reg >> 26) & 0xf;
 
        mfi = mfi <= 5 ? 5 : mfi;
+       mfn = mfn >= 512 ? mfn - 1024 : mfn;
        mfd += 1;
        pd += 1;
 
-       return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+       return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
+               mfd * pd);
 }
 
 static u32 get_mcu_main_clk(void)
@@ -146,9 +149,7 @@ static u32 get_mcu_main_clk(void)
        struct ccm_regs *ccm =
                (struct ccm_regs *)IMX_CCM_BASE;
        arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
-       fi *=
-               decode_pll(readl(&ccm->mpctl),
-                       CONFIG_MX35_HCLK_FREQ);
+       fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
        return fi / (arm_div * fd);
 }
 
@@ -171,17 +172,14 @@ static u32 get_ipg_per_clk(void)
        u32 pdr4 = readl(&ccm->pdr4);
        u32 div;
        if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
-               div = (CCM_GET_DIVIDER(pdr4,
-                       MXC_CCM_PDR4_PER0_PRDF_MASK,
-                       MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
-                       (CCM_GET_DIVIDER(pdr4,
+               div = CCM_GET_DIVIDER(pdr4,
                        MXC_CCM_PDR4_PER0_PODF_MASK,
-                       MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
+                       MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
        } else {
                div = CCM_GET_DIVIDER(pdr0,
                        MXC_CCM_PDR0_PER_PODF_MASK,
                        MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
-               freq /= get_ahb_div(pdr0);
+               div *= get_ahb_div(pdr0);
        }
        return freq / div;
 }
@@ -193,25 +191,20 @@ u32 imx_get_uartclk(void)
                (struct ccm_regs *)IMX_CCM_BASE;
        u32 pdr4 = readl(&ccm->pdr4);
 
-       if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
+       if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
                freq = get_mcu_main_clk();
-       } else {
-               freq = decode_pll(readl(&ccm->ppctl),
-                       CONFIG_MX35_HCLK_FREQ);
-       }
-       freq /= ((CCM_GET_DIVIDER(pdr4,
-                       MXC_CCM_PDR4_UART_PRDF_MASK,
-                       MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
-               (CCM_GET_DIVIDER(pdr4,
+       else
+               freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
+       freq /= CCM_GET_DIVIDER(pdr4,
                        MXC_CCM_PDR4_UART_PODF_MASK,
-                       MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
+                       MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
        return freq;
 }
 
 unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
 {
        u32 nfc_pdf, hsp_podf;
-       u32 pll, ret_val = 0, usb_prdf, usb_podf;
+       u32 pll, ret_val = 0, usb_podf;
        struct ccm_regs *ccm =
                (struct ccm_regs *)IMX_CCM_BASE;
 
@@ -255,16 +248,13 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
                ret_val = pll / (nfc_pdf + 1);
                break;
        case USB_CLK:
-               usb_prdf = (reg4 >> 25) & 0x7;
-               usb_podf = (reg4 >> 22) & 0x7;
-               if (reg4 & 0x200) {
+               usb_podf = (reg4 >> 22) & 0x3F;
+               if (reg4 & 0x200)
                        pll = get_mcu_main_clk();
-               } else {
-                       pll = decode_pll(readl(&ccm->ppctl),
-                               CONFIG_MX35_HCLK_FREQ);
-               }
+               else
+                       pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
 
-               ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+               ret_val = pll / (usb_podf + 1);
                break;
        default:
                printf("Unknown clock: %d\n", clk);
@@ -287,18 +277,16 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
        case UART2_BAUD:
        case UART3_BAUD:
                clk_sel = mpdr3 & (1 << 14);
-               pre_pdf = (mpdr4 >> 13) & 0x7;
-               pdf = (mpdr4 >> 10) & 0x7;
+               pdf = (mpdr4 >> 10) & 0x3F;
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-                               ((pre_pdf + 1) * (pdf + 1));
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
                break;
        case SSI1_BAUD:
                pre_pdf = (mpdr2 >> 24) & 0x7;
                pdf = mpdr2 & 0x3F;
                clk_sel = mpdr2 & (1 << 6);
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
                                ((pre_pdf + 1) * (pdf + 1));
                break;
        case SSI2_BAUD:
@@ -306,16 +294,14 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
                pdf = (mpdr2 >> 8) & 0x3F;
                clk_sel = mpdr2 & (1 << 6);
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
                                ((pre_pdf + 1) * (pdf + 1));
                break;
        case CSI_BAUD:
                clk_sel = mpdr2 & (1 << 7);
-               pre_pdf = (mpdr2 >> 16) & 0x7;
-               pdf = (mpdr2 >> 19) & 0x7;
+               pdf = (mpdr2 >> 16) & 0x3F;
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-                               ((pre_pdf + 1) * (pdf + 1));
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
                break;
        case MSHC_CLK:
                pre_pdf = readl(&ccm->pdr1);
@@ -323,39 +309,33 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
                pdf = (pre_pdf >> 22) & 0x3F;
                pre_pdf = (pre_pdf >> 28) & 0x7;
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
                                ((pre_pdf + 1) * (pdf + 1));
                break;
        case ESDHC1_CLK:
                clk_sel = mpdr3 & 0x40;
-               pre_pdf = mpdr3 & 0x7;
-               pdf = (mpdr3>>3) & 0x7;
+               pdf = mpdr3 & 0x3F;
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-                               ((pre_pdf + 1) * (pdf + 1));
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
                break;
        case ESDHC2_CLK:
                clk_sel = mpdr3 & 0x40;
-               pre_pdf = (mpdr3 >> 8) & 0x7;
-               pdf = (mpdr3 >> 11) & 0x7;
+               pdf = (mpdr3 >> 8) & 0x3F;
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-                               ((pre_pdf + 1) * (pdf + 1));
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
                break;
        case ESDHC3_CLK:
                clk_sel = mpdr3 & 0x40;
-               pre_pdf = (mpdr3 >> 16) & 0x7;
-               pdf = (mpdr3 >> 19) & 0x7;
+               pdf = (mpdr3 >> 16) & 0x3F;
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
-                               ((pre_pdf + 1) * (pdf + 1));
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
                break;
        case SPDIF_CLK:
                clk_sel = mpdr3 & 0x400000;
                pre_pdf = (mpdr3 >> 29) & 0x7;
                pdf = (mpdr3 >> 23) & 0x3F;
                ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
-                       decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+                       decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
                                ((pre_pdf + 1) * (pdf + 1));
                break;
        default:
index 04937a1..9680b7f 100644 (file)
@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <div64.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -37,43 +38,52 @@ DECLARE_GLOBAL_DATA_PTR;
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)        /* Software reset */
 #define GPTCR_FRR       (1<<9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32   (0x100<<6)        /* Clock source */
-#define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */
+#define GPTCR_CLKSOURCE_32   (4<<6)    /* Clock source */
 #define GPTCR_TEN       (1)    /* Timer enable */
 
-#define        TIMER_FREQ_HZ   mxc_get_clock(MXC_IPG_CLK)
-
+/*
+ * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
+ * "tick" is internal timer period
+ */
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, TIMER_FREQ_HZ);
+       do_div(tick, MXC_CLK32);
 
        return tick;
 }
 
-static inline unsigned long long us_to_tick(unsigned long long usec)
+static inline unsigned long long us_to_tick(unsigned long long us)
 {
-       usec *= TIMER_FREQ_HZ;
-       do_div(usec, 1000000);
+       us = us * MXC_CLK32 + 999999;
+       do_div(us, 1000000);
 
-       return usec;
+       return us;
 }
 
+/*
+ * nothing really to do with interrupts, just starts up a counter.
+ * The 32KHz 32-bit timer overruns in 134217 seconds
+ */
 int timer_init(void)
 {
        int i;
        struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
+       struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
 
        /* setup GP Timer 1 */
        writel(GPTCR_SWR, &gpt->ctrl);
-       for (i = 0; i < 100; i++)
-               writel(0, &gpt->ctrl);  /* We have no udelay by now */
 
-       writel(0, &gpt->pre);
-       /* Freerun Mode, PERCLK1 input */
-       writel(readl(&gpt->ctrl) |
-               GPTCR_CLKSOURCE_IPG | GPTCR_TEN,
-               &gpt->ctrl);
+       writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
+
+       for (i = 0; i < 100; i++)
+               writel(0, &gpt->ctrl); /* We have no udelay by now */
+       writel(0, &gpt->pre); /* prescaler = 1 */
+       /* Freerun Mode, 32KHz input */
+       writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
+                       &gpt->ctrl);
+       writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
 
        return 0;
 }
@@ -101,7 +111,7 @@ ulong get_timer_masked(void)
 {
        /*
         * get_ticks() returns a long long (64 bit), it wraps in
-        * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+        * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
         * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
         * 5 * 10^6 days - long enough.
         */
@@ -132,5 +142,5 @@ void __udelay(unsigned long usec)
  */
 ulong get_tbclk(void)
 {
-       return TIMER_FREQ_HZ;
+       return MXC_CLK32;
 }
index 4ea6d6b..95da6a8 100644 (file)
@@ -17,7 +17,7 @@ include $(TOPDIR)/config.mk
 LIB    = $(obj)lib$(SOC).o
 
 SOBJS  := lowlevel_init.o
-COBJS  := reset.o timer.o
+COBJS  := init.o reset.o timer.o
 
 SRCS   := $(SOBJS:.o=.c) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/arm1176/bcm2835/init.c b/arch/arm/cpu/arm1176/bcm2835/init.c
new file mode 100644 (file)
index 0000000..e90d3bb
--- /dev/null
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2012 Stephen Warren
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+
+       return 0;
+}
index 532a90b..c0fd114 100644 (file)
@@ -65,10 +65,3 @@ static void cache_flush (void)
        /* mem barrier to sync things */
        asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
 }
-
-int arch_cpu_init(void)
-{
-       icache_enable();
-
-       return 0;
-}
index 6d4d66b..ddf8d97 100644 (file)
@@ -105,14 +105,14 @@ static void enable_cpu_clock(int enable)
 
 static int is_cpu_powered(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
        return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
 }
 
 static void remove_cpu_io_clamps(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
        /* Remove the clamps on the CPU I/O signals */
@@ -126,7 +126,7 @@ static void remove_cpu_io_clamps(void)
 
 static void powerup_cpu(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
        int timeout = IO_STABILIZATION_DELAY;
 
@@ -157,7 +157,7 @@ static void powerup_cpu(void)
 
 static void enable_cpu_power_rail(void)
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
        reg = readl(&pmc->pmc_cntrl);
index a412a8f..90e584a 100644 (file)
@@ -64,7 +64,7 @@ static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
 static ulong imx_get_mpllclk(void)
 {
        struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-       ulong fref = 24000000;
+       ulong fref = MXC_HCLK;
 
        return imx_decode_pll(readl(&ccm->mpctl), fref);
 }
index 1cfd02b..4dc4041 100644 (file)
@@ -40,6 +40,7 @@
 #include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,28 +56,27 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
        tick *= CONFIG_SYS_HZ;
-       do_div(tick, CONFIG_MX25_CLK32);
+       do_div(tick, MXC_CLK32);
        return tick;
 }
 
 static inline unsigned long long time_to_tick(unsigned long long time)
 {
-       time *= CONFIG_MX25_CLK32;
+       time *= MXC_CLK32;
        do_div(time, CONFIG_SYS_HZ);
        return time;
 }
 
 static inline unsigned long long us_to_tick(unsigned long long us)
 {
-       us = us * CONFIG_MX25_CLK32 + 999999;
+       us = us * MXC_CLK32 + 999999;
        do_div(us, 1000000);
        return us;
 }
 #else
 /* ~2% error */
-#define TICK_PER_TIME  ((CONFIG_MX25_CLK32 + CONFIG_SYS_HZ / 2) / \
-               CONFIG_SYS_HZ)
-#define US_PER_TICK    (1000000 / CONFIG_MX25_CLK32)
+#define TICK_PER_TIME  ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK    (1000000 / MXC_CLK32)
 
 static inline unsigned long long tick_to_time(unsigned long long tick)
 {
@@ -144,7 +144,7 @@ ulong get_timer_masked(void)
 {
        /*
         * get_ticks() returns a long long (64 bit), it wraps in
-        * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+        * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
         * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
         * 5 * 10^6 days - long enough.
         */
@@ -177,6 +177,6 @@ ulong get_tbclk(void)
 {
        ulong tbclk;
 
-       tbclk = CONFIG_MX25_CLK32;
+       tbclk = MXC_CLK32;
        return tbclk;
 }
index ddafddb..ad66c57 100644 (file)
  * takes a few seconds to roll. The boot doesn't take that long, so to keep the
  * code simple, it doesn't take rolling into consideration.
  */
-#define        HW_DIGCTRL_MICROSECONDS 0x8001c0c0
 void early_delay(int delay)
 {
-       uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
+       struct mxs_digctl_regs *digctl_regs =
+               (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
+
+       uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
        st += delay;
-       while (st > readl(HW_DIGCTRL_MICROSECONDS))
+       while (st > readl(&digctl_regs->hw_digctl_microseconds))
                ;
 }
 
index 792b11d..c3948d3 100644 (file)
@@ -292,7 +292,9 @@ int arch_misc_init(void)
        writel(ORION5X_MPP0_7, ORION5X_MPP_BASE+0x00);
        writel(ORION5X_MPP8_15, ORION5X_MPP_BASE+0x04);
        writel(ORION5X_MPP16_23, ORION5X_MPP_BASE+0x50);
+       writel(ORION5X_GPIO_OUT_VALUE, ORION5X_GPIO_BASE+0x00);
        writel(ORION5X_GPIO_OUT_ENABLE, ORION5X_GPIO_BASE+0x04);
+       writel(ORION5X_GPIO_IN_POLARITY, ORION5X_GPIO_BASE+0x0c);
 
        /* initialize timer */
        timer_init_r();
index b387ac2..ecc2671 100644 (file)
@@ -37,7 +37,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 static const struct gpio_bank gpio_bank_am33xx[4] = {
@@ -119,22 +118,6 @@ static int read_eeprom(void)
 #define UART_SMART_IDLE_EN     (0x1 << 0x3)
 #endif
 
-#ifdef CONFIG_SPL_BUILD
-/* Initialize timer */
-static void init_timer(void)
-{
-       /* Reset the Timer */
-       writel(0x2, (&timer_base->tscir));
-
-       /* Wait until the reset is done */
-       while (readl(&timer_base->tiocp_cfg) & 1)
-               ;
-
-       /* Start the Timer */
-       writel(0x1, (&timer_base->tclr));
-}
-#endif
-
 /*
  * Determine what type of DDR we have.
  */
@@ -183,9 +166,6 @@ void s_init(void)
        regVal |= UART_SMART_IDLE_EN;
        writel(regVal, &uart_base->uartsyscfg);
 
-       /* Initialize the Timer */
-       init_timer();
-
        preloader_console_init();
 
        /* Initalize the board header */
index 75cadb0..925f841 100644 (file)
@@ -46,7 +46,7 @@
 static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
                       char * const argv[])
 {
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
        puts("Entering RCM...\n");
        udelay(50000);
index 178bb13..cac0918 100644 (file)
@@ -137,24 +137,29 @@ static const u8 utmip_elastic_limit = 16;
 /* UTMIP High Speed Sync Start Delay */
 static const u8 utmip_hs_sync_start_delay = 9;
 
-/* Put the port into host mode (this only works for OTG ports) */
+/* Put the port into host mode */
 static void set_host_mode(struct fdt_usb *config)
 {
-       if (config->dr_mode == DR_MODE_OTG) {
-               /* Check whether remote host from USB1 is driving VBus */
-               if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
-                       return;
-
-               /*
-                * If not driving, we set the GPIO to enable VBUS. We assume
-                * that the pinmux is set up correctly for this.
-                */
-               if (fdt_gpio_isvalid(&config->vbus_gpio)) {
-                       fdtdec_setup_gpio(&config->vbus_gpio);
-                       gpio_direction_output(config->vbus_gpio.gpio, 1);
-                       debug("set_host_mode: GPIO %d high\n",
-                             config->vbus_gpio.gpio);
-               }
+       /*
+        * If we are an OTG port, check if remote host is driving VBus and
+        * bail out in this case.
+        */
+       if (config->dr_mode == DR_MODE_OTG &&
+               (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
+               return;
+
+       /*
+        * If not driving, we set the GPIO to enable VBUS. We assume
+        * that the pinmux is set up correctly for this.
+        */
+       if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+               fdtdec_setup_gpio(&config->vbus_gpio);
+               gpio_direction_output(config->vbus_gpio.gpio,
+                       (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+                                0 : 1);
+               debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
+                       (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
+                               "low" : "high");
        }
 }
 
index 43c96c6..9e91e5c 100644 (file)
@@ -33,7 +33,7 @@ LIB   = $(obj)lib$(SOC)-common.o
 
 SOBJS += lowlevel_init.o
 COBJS-y        += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
-COBJS-$(CONFIG_TEGRA20_LP0) += warmboot.o crypto.o warmboot_avp.o
+COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
 COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
 
index 00588da..c0ca6eb 100644 (file)
@@ -32,7 +32,7 @@
 int tegra_get_chip_type(void)
 {
        struct apb_misc_gp_ctlr *gp;
-       struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
        uint tegra_sku_id, rev;
 
        /*
@@ -40,7 +40,7 @@ int tegra_get_chip_type(void)
         * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
         * Tegra30
         */
-       gp = (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+       gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
        rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
 
        tegra_sku_id = readl(&fuse->sku_info) & 0xff;
@@ -101,7 +101,7 @@ static u32 get_odmdata(void)
 
 static void init_pmc_scratch(void)
 {
-       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 odmdata;
        int i;
 
index 598023a..8a8d338 100644 (file)
@@ -47,7 +47,7 @@ enum {
 
 unsigned int query_sdram_size(void)
 {
-       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
        reg = readl(&pmc->pmc_scratch20);
@@ -81,11 +81,11 @@ int checkboard(void)
 #endif /* CONFIG_DISPLAY_BOARDINFO */
 
 static int uart_configs[] = {
-#if defined(CONFIG_TEGRA20_UARTA_UAA_UAB)
+#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
        FUNCMUX_UART1_UAA_UAB,
-#elif defined(CONFIG_TEGRA20_UARTA_GPU)
+#elif defined(CONFIG_TEGRA_UARTA_GPU)
        FUNCMUX_UART1_GPU,
-#elif defined(CONFIG_TEGRA20_UARTA_SDIO1)
+#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
        FUNCMUX_UART1_SDIO1,
 #else
        FUNCMUX_UART1_IRRX_IRTX,
@@ -125,13 +125,13 @@ void board_init_uart_f(void)
 {
        int uart_ids = 0;       /* bit mask of which UART ids to enable */
 
-#ifdef CONFIG_TEGRA20_ENABLE_UARTA
+#ifdef CONFIG_TEGRA_ENABLE_UARTA
        uart_ids |= UARTA;
 #endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTB
+#ifdef CONFIG_TEGRA_ENABLE_UARTB
        uart_ids |= UARTB;
 #endif
-#ifdef CONFIG_TEGRA20_ENABLE_UARTD
+#ifdef CONFIG_TEGRA_ENABLE_UARTD
        uart_ids |= UARTD;
 #endif
        setup_uarts(uart_ids);
index 8cfed64..b2129ad 100644 (file)
@@ -234,6 +234,13 @@ int funcmux_select(enum periph_id id, int config)
                }
                break;
 
+       case PERIPH_ID_NDFLASH:
+               if (config == FUNCMUX_NDFLASH_ATC) {
+                       pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
+                       pinmux_tristate_disable(PINGRP_ATC);
+               }
+               break;
+
        default:
                debug("%s: invalid periph_id %d", __func__, id);
                return -1;
index 809ea01..6ce995e 100644 (file)
@@ -39,7 +39,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_TEGRA_CLOCK_SCALING
-#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA20_LP0"
+#error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
 #endif
 
 /*
@@ -139,9 +139,9 @@ int warmboot_save_sdram_params(void)
        u32 ram_code;
        struct sdram_params sdram;
        struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        struct apb_misc_gp_ctlr *gp =
-                       (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+                       (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
        struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
        union scratch2_reg scratch2;
        union scratch4_reg scratch4;
@@ -205,7 +205,7 @@ static u32 get_major_version(void)
 {
        u32 major_id;
        struct apb_misc_gp_ctlr *gp =
-               (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+               (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
        major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
                        HIDREV_MAJORPREV_SHIFT;
@@ -229,7 +229,7 @@ static int is_failure_analysis_mode(struct fuse_regs *fuse)
 
 static int ap20_is_odm_production_mode(void)
 {
-       struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
        if (!is_failure_analysis_mode(fuse) &&
            is_odm_production_mode_fuse_set(fuse))
@@ -240,7 +240,7 @@ static int ap20_is_odm_production_mode(void)
 
 static int ap20_is_production_mode(void)
 {
-       struct fuse_regs *fuse = (struct fuse_regs *)TEGRA20_FUSE_BASE;
+       struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
 
        if (get_major_version() == 0)
                return 1;
@@ -257,7 +257,7 @@ static enum fuse_operating_mode fuse_get_operation_mode(void)
 {
        u32 chip_id;
        struct apb_misc_gp_ctlr *gp =
-               (struct apb_misc_gp_ctlr *)TEGRA20_APB_MISC_GP_BASE;
+               (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
 
        chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
                        HIDREV_CHIPID_SHIFT;
index cd01908..80a5a15 100644 (file)
@@ -38,7 +38,7 @@
 void wb_start(void)
 {
        struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA20_PMC_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
        struct clk_rst_ctlr *clkrst =
                        (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
index f95be58..d936b1e 100644 (file)
                compatible = "nvidia,tegra20-kbc";
                reg = <0x7000e200 0x0078>;
        };
+
+       nand: nand-controller@70008000 {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               compatible = "nvidia,tegra20-nand";
+               reg = <0x70008000 0x100>;
+       };
 };
similarity index 94%
rename from arch/arm/cpu/armv7/imx-common/Makefile
rename to arch/arm/imx-common/Makefile
index 16fba8d..b3e608e 100644 (file)
@@ -27,8 +27,10 @@ include $(TOPDIR)/config.mk
 
 LIB     = $(obj)libimx-common.o
 
+ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
 COBJS-y        = iomux-v3.o timer.o cpu.o speed.o
-COBJS-$(CONFIG_I2C_MXC) += i2c.o
+COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
+endif
 COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 COBJS  := $(sort $(COBJS-y))
 
index 0f701c9..afdfcf0 100644 (file)
 #define SDHCI_CTRL4_DRIVE_MASK(_x)     ((_x) << 16)
 #define SDHCI_CTRL4_DRIVE_SHIFT                (16)
 
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
 static inline unsigned int s5p_mmc_init(int index, int bus_width)
 {
        unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-       return s5p_sdhci_init(base, 52000000, 400000, index);
+       return s5p_sdhci_init(base, index, bus_width);
 }
 #endif
index c79bed7..113f258 100644 (file)
@@ -49,6 +49,7 @@ struct kwspi_registers {
 #define MISO_MPP11     (1 << 2)
 
 #define KWSPI_CLKPRESCL_MASK   0x1f
+#define KWSPI_CLKPRESCL_MIN    0x12
 #define KWSPI_CSN_ACT          1 /* Activates serial memory interface */
 #define KWSPI_SMEMRDY          (1 << 1) /* SerMem Data xfer ready */
 #define KWSPI_IRQUNMASK                1 /* unmask SPI interrupt */
index 0f47eaf..a313b80 100644 (file)
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_MX25_HCLK_FREQ
+#define MXC_HCLK       CONFIG_MX25_HCLK_FREQ
+#else
+#define MXC_HCLK       24000000
+#endif
+
+#ifdef CONFIG_MX25_CLK32
+#define MXC_CLK32      CONFIG_MX25_CLK32
+#else
+#define MXC_CLK32      32768
+#endif
+
 enum mxc_clock {
        MXC_CSI_CLK,
        MXC_EPIT_CLK,
index 852c19c..9468b45 100644 (file)
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_MX31_HCLK_FREQ
+#define MXC_HCLK       CONFIG_MX31_HCLK_FREQ
+#else
+#define MXC_HCLK       26000000
+#endif
+
+#ifdef CONFIG_MX31_CLK32
+#define MXC_CLK32      CONFIG_MX31_CLK32
+#else
+#define MXC_CLK32      32768
+#endif
+
 enum mxc_clock {
        MXC_ARM_CLK,
        MXC_IPG_CLK,
index e94f124..eb7458a 100644 (file)
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <common.h>
+
+#ifdef CONFIG_MX35_HCLK_FREQ
+#define MXC_HCLK       CONFIG_MX35_HCLK_FREQ
+#else
+#define MXC_HCLK       24000000
+#endif
+
+#ifdef CONFIG_MX35_CLK32
+#define MXC_CLK32      CONFIG_MX35_CLK32
+#else
+#define MXC_CLK32      32768
+#endif
+
 enum mxc_clock {
        MXC_ARM_CLK,
        MXC_AHB_CLK,
index 7a2d1bb..3fcde0b 100644 (file)
@@ -32,8 +32,8 @@
 #define MXC_CCM_CCMR_VOL_RDY_CNT_MASK          (0xF << 20)
 #define MXC_CCM_CCMR_ROMW_OFFSET               18
 #define MXC_CCM_CCMR_ROMW_MASK                 (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET               21
-#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 21)
+#define MXC_CCM_CCMR_RAMW_OFFSET               16
+#define MXC_CCM_CCMR_RAMW_MASK                 (0x3 << 16)
 #define MXC_CCM_CCMR_LPM_OFFSET                 14
 #define MXC_CCM_CCMR_LPM_MASK                   (0x3 << 14)
 #define MXC_CCM_CCMR_UPE                        (1 << 9)
@@ -47,7 +47,7 @@
 #define MXC_CCM_PDR0_CON_MUX_DIV_MASK           (0xF << 16)
 #define MXC_CCM_PDR0_CKIL_SEL                  (1 << 15)
 #define MXC_CCM_PDR0_PER_PODF_OFFSET            12
-#define MXC_CCM_PDR0_PER_PODF_MASK              (0xF << 12)
+#define MXC_CCM_PDR0_PER_PODF_MASK              (0x7 << 12)
 #define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET        9
 #define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK          (0x7 << 9)
 #define MXC_CCM_PDR0_AUTO_CON                  0x1
 #define MXC_CCM_PDR2_SSI2_PRDF_MASK             (0x7 << 27)
 #define MXC_CCM_PDR2_SSI1_PRDF_OFFSET           24
 #define MXC_CCM_PDR2_SSI1_PRDF_MASK             (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PRDF_OFFSET            19
-#define MXC_CCM_PDR2_CSI_PRDF_MASK              (0x7 << 19)
 #define MXC_CCM_PDR2_CSI_PODF_OFFSET            16
-#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x7 << 16)
+#define MXC_CCM_PDR2_CSI_PODF_MASK              (0x3F << 16)
 #define MXC_CCM_PDR2_SSI2_PODF_OFFSET           8
 #define MXC_CCM_PDR2_SSI2_PODF_MASK             (0x3F << 8)
 #define MXC_CCM_PDR2_CSI_M_U                   (1 << 7)
 #define MXC_CCM_PDR3_SPDIF_PODF_OFFSET          23
 #define MXC_CCM_PDR3_SPDIF_PODF_MASK            (0x3F << 23)
 #define MXC_CCM_PDR3_SPDIF_M_U                 (1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET         19
-#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK           (0x7 << 19)
 #define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET         16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x7 << 16)
-#define MXC_CCM_PDR3_UART_M_U                  (1 << 15)
-#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET         11
-#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK           (0x7 << 11)
+#define MXC_CCM_PDR3_ESDHC3_PODF_MASK           (0x3F << 16)
+#define MXC_CCM_PDR3_UART_M_U                  (1 << 14)
 #define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET         8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x7 << 8)
+#define MXC_CCM_PDR3_ESDHC2_PODF_MASK           (0x3F << 8)
 #define MXC_CCM_PDR3_ESDHC_M_U                 (1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET         3
-#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK           (0x7 << 3)
 #define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET         0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x7)
+#define MXC_CCM_PDR3_ESDHC1_PODF_MASK           (0x3F)
 
 #define MXC_CCM_PDR4_NFC_PODF_OFFSET           28
 #define MXC_CCM_PDR4_NFC_PODF_MASK             (0xF << 28)
-#define MXC_CCM_PDR4_USB_PRDF_OFFSET           25
-#define MXC_CCM_PDR4_USB_PRDF_MASK             (0x7 << 25)
 #define MXC_CCM_PDR4_USB_PODF_OFFSET           22
-#define MXC_CCM_PDR4_USB_PODF_MASK             (0x7 << 22)
-#define MXC_CCM_PDR4_PER0_PRDF_OFFSET          19
-#define MXC_CCM_PDR4_PER0_PRDF_MASK            (0x7 << 19)
+#define MXC_CCM_PDR4_USB_PODF_MASK             (0x3F << 22)
 #define MXC_CCM_PDR4_PER0_PODF_OFFSET          16
-#define MXC_CCM_PDR4_PER0_PODF_MASK            (0x7 << 16)
-#define MXC_CCM_PDR4_UART_PRDF_OFFSET          13
-#define MXC_CCM_PDR4_UART_PRDF_MASK            (0x7 << 13)
+#define MXC_CCM_PDR4_PER0_PODF_MASK            (0x3F << 16)
 #define MXC_CCM_PDR4_UART_PODF_OFFSET          10
-#define MXC_CCM_PDR4_UART_PODF_MASK            (0x7 << 10)
+#define MXC_CCM_PDR4_UART_PODF_MASK            (0x3F << 10)
 #define MXC_CCM_PDR4_USB_M_U                   (1 << 9)
 
 /* Bit definitions for RCSR */
 #define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK         (0xF << 0)
 
 /* Bit definitions for Clock gating Register*/
+#define MXC_CCM_CGR_CG_MASK                    0x3
+#define MXC_CCM_CGR_CG_OFF                     0x0
+#define MXC_CCM_CGR_CG_RUN_ON                  0x1
+#define MXC_CCM_CGR_CG_RUN_WAIT_ON             0x2
+#define MXC_CCM_CGR_CG_ON                      0x3
+
 #define MXC_CCM_CGR0_ASRC_OFFSET               0
 #define MXC_CCM_CGR0_ASRC_MASK                 (0x3 << 0)
 #define MXC_CCM_CGR0_ATA_OFFSET                        2
 #define MXC_CCM_COSR_CLKOSEL_OFFSET            0
 #define MXC_CCM_COSR_CLKOEN                    (1 << 5)
 #define MXC_CCM_COSR_CLKOUTDIV_1               (1 << 6)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK                (0x7 << 10)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET      10
-#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK                (0x7 << 13)
-#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET      13
+#define MXC_CCM_COSR_CLKOUT_DIV_MASK           (0x3F << 10)
+#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET         10
 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK      (0x3 << 16)
 #define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET    16
 #define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK      (0x3 << 18)
index a1255f9..d23abd7 100644 (file)
 #define IOMUXC_GPR13_SATA_PHY_2_MASK   (0x1f<<2)
 #define IOMUXC_GPR13_SATA_PHY_1_MASK   (3<<0)
 
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB     (0b000<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB     (0b001<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB     (0b010<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB     (0b011<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB     (0b100<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB     (0b101<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB     (0b110<<24)
-#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB     (0b111<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB     (0<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB     (1<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB     (2<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P0DB     (3<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_2P5DB     (4<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB     (5<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P5DB     (6<<24)
+#define IOMUXC_GPR13_SATA_PHY_8_RXEQ_4P0DB     (7<<24)
 
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0b10000<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0b11010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0b10010<<19)
-#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0b11010<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1I (0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1M (0x10<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA1X (0x1A<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2I (0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2M (0x12<<19)
+#define IOMUXC_GPR13_SATA_PHY_7_SATA2X (0x1A<<19)
 
 #define IOMUXC_GPR13_SATA_SPEED_1P5G   (0<<15)
 #define IOMUXC_GPR13_SATA_SPEED_3G     (1<<15)
 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16                (4<<11)
 #define IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_8_16                (5<<11)
 
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB        (0b0000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB        (0b0001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB        (0b0010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB        (0b0011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB        (0b0100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB        (0b0101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB        (0b0110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB        (0b0111<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB        (0b1000<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB        (0b1001<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB        (0b1010<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB        (0b1011<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB        (0b1100<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB        (0b1101<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB        (0b1110<<7)
-#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB        (0b1111<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB        (0<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P37_DB        (1<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P74_DB        (2<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P11_DB        (3<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P48_DB        (4<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_1P85_DB        (5<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P22_DB        (6<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P59_DB        (7<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_2P96_DB        (8<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB        (9<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P70_DB        (0xA<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P07_DB        (0xB<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P44_DB        (0xC<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_4P81_DB        (0xD<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P28_DB        (0xE<<7)
+#define IOMUXC_GPR13_SATA_PHY_3_TXBOOST_5P75_DB        (0xF<<7)
 
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V      (0b00000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V      (0b00001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V      (0b00010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V      (0b00011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V      (0b00100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V      (0b00101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V      (0b00110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V      (0b00111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V      (0b01000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V      (0b01001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V      (0b01010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V      (0b01011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V      (0b01100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V      (0b01101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V      (0b01110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V      (0b01111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V      (0b10000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V      (0b10001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V      (0b10010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V      (0b10011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V      (0b10100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V      (0b10101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V      (0b10110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V      (0b10111<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V      (0b11000<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V      (0b11001<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V      (0b11010<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V      (0b11011<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V      (0b11100<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V      (0b11101<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V      (0b11110<<2)
-#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V      (0b11111<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P937V      (0<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P947V      (1<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P957V      (2<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P966V      (3<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P976V      (4<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P986V      (5<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_0P996V      (6<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P005V      (7<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P015V      (8<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P025V      (9<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P035V      (0xA<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P045V      (0xB<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P054V      (0xC<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P064V      (0xD<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P074V      (0xE<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P084V      (0xF<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P094V      (0x10<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P104V      (0x11<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P113V      (0x12<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P123V      (0x13<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P133V      (0x14<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P143V      (0x15<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P152V      (0x16<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P162V      (0x17<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P172V      (0x18<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P182V      (0x19<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P191V      (0x1A<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P201V      (0x1B<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P211V      (0x1C<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P221V      (0x1D<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P230V      (0x1E<<2)
+#define IOMUXC_GPR13_SATA_PHY_2_TX_1P240V      (0x1F<<2)
 
 #define IOMUXC_GPR13_SATA_PHY_1_FAST   0
 #define IOMUXC_GPR13_SATA_PHY_1_MEDIUM 1
index 6032419..d8d5647 100644 (file)
 #define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
 #endif  /* endif CONFIG_2420H4 */
 
-#if defined(CONFIG_APOLLON)
-#define APOLLON_CS0_BASE       0x00000000      /* OneNAND */
-#define APOLLON_CS1_BASE       0x08000000      /* ethernet */
-#define APOLLON_CS2_BASE       0x10000000      /* OneNAND */
-#define APOLLON_CS3_BASE       0x18000000      /* NOR */
-
-#define ETH_CONTROL_REG                (APOLLON_CS1_BASE + 0x30b)
-#define LAN_RESET_REGISTER     (APOLLON_CS1_BASE + 0x1c)
-#endif /* endif CONFIG_APOLLON */
-
 /* Common */
 #define LOW_LEVEL_SRAM_STACK  0x4020FFFC
 
index a830c43..54add4b 100644 (file)
@@ -142,7 +142,6 @@ struct venc_regs {
 };
 
 /* Few Register Offsets */
-#define FRAME_MODE_SHIFT                       1
 #define TFTSTN_SHIFT                           3
 #define DATALINES_SHIFT                                8
 
@@ -182,6 +181,16 @@ struct panel_config {
        void *frame_buffer;
 };
 
+#define DSS_HBP(bp)    (((bp) - 1) << 20)
+#define DSS_HFP(fp)    (((fp) - 1) << 8)
+#define DSS_HSW(sw)    ((sw) - 1)
+#define DSS_VBP(bp)    ((bp) << 20)
+#define DSS_VFP(fp)    ((fp) << 8)
+#define DSS_VSW(sw)    ((sw) - 1)
+
+#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
+#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+
 /* Generic DSS Functions */
 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
                        u32 height, u32 width);
index 71f183d..6e92b23 100644 (file)
 #define CONTROL_PADCONF_GPIO128                0x0A58
 #define CONTROL_PADCONF_GPIO129                0x0A5A
 
+/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
+ * of the extended drain cells */
+#define OMAP34XX_CTRL_WKUP_CTRL                (OMAP34XX_CTRL_BASE + 0x0A5C)
+#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
+
 #define MUX_VAL(OFFSET,VALUE)\
        writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
 
index a8c4c60..3a0bfbf 100644 (file)
@@ -138,6 +138,7 @@ struct watchdog {
 #define I2C_BASE1              (OMAP44XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2              (OMAP44XX_L4_PER_BASE + 0x72000)
 #define I2C_BASE3              (OMAP44XX_L4_PER_BASE + 0x60000)
+#define I2C_BASE4              (OMAP44XX_L4_PER_BASE + 0x350000)
 
 /* MUSB base */
 #define MUSB_BASE              (OMAP44XX_L4_CORE_BASE + 0xAB000)
index a91b4c2..02ee2f8 100644 (file)
@@ -23,7 +23,7 @@
 #ifndef _OMAP4_I2C_H_
 #define _OMAP4_I2C_H_
 
-#define I2C_BUS_MAX    3
+#define I2C_BUS_MAX    4
 #define I2C_DEFAULT_BASE       I2C_BASE1
 
 struct i2c {
index 0f701c9..afdfcf0 100644 (file)
 #define SDHCI_CTRL4_DRIVE_MASK(_x)     ((_x) << 16)
 #define SDHCI_CTRL4_DRIVE_SHIFT                (16)
 
-int s5p_sdhci_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
 static inline unsigned int s5p_mmc_init(int index, int bus_width)
 {
        unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
-       return s5p_sdhci_init(base, 52000000, 400000, index);
+       return s5p_sdhci_init(base, index, bus_width);
 }
 #endif
index c84d22f..70d94c5 100644 (file)
@@ -95,9 +95,6 @@
 #define HALT_COP_EVENT_IRQ_1           (1 << 11)
 #define HALT_COP_EVENT_FIQ_1           (1 << 9)
 
-/* Start up the tegra20 SOC */
-void tegra20_start(void);
-
 /* This is the main entry into U-Boot, used by the Cortex-A9 */
 extern void _start(void);
 
index 258f7b6..bd511db 100644 (file)
@@ -57,6 +57,9 @@ enum {
 
        /* Serial Flash configs */
        FUNCMUX_SPI1_GMC_GMD = 0,
+
+       /* NAND flags */
+       FUNCMUX_NDFLASH_ATC = 0,
 };
 
 /**
index 916a353..5c95047 100644 (file)
@@ -19,9 +19,9 @@
  * MA 02111-1307 USA
  */
 
-#ifndef _TEGRA20_MMC_H_
-#define _TEGRA20_MMC_H_
+#ifndef _TEGRA_MMC_H_
+#define _TEGRA_MMC_H_
 
-int tegra20_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+int tegra_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
 
-#endif /* TEGRA20_MMC_H_ */
+#endif /* _TEGRA_MMC_H_ */
index 643d542..919aec7 100644 (file)
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-struct tegra20_sysinfo {
+struct tegra_sysinfo {
        char *board_string;
 };
 
 void invalidate_dcache(void);
 
-extern const struct tegra20_sysinfo sysinfo;
+extern const struct tegra_sysinfo sysinfo;
 
 #endif
index 6750754..c9485a1 100644 (file)
 #define NV_PA_GPIO_BASE                0x6000D000
 #define NV_PA_EVP_BASE         0x6000F000
 #define NV_PA_APB_MISC_BASE    0x70000000
-#define TEGRA20_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
+#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
 #define NV_PA_APB_UARTA_BASE   (NV_PA_APB_MISC_BASE + 0x6000)
 #define NV_PA_APB_UARTB_BASE   (NV_PA_APB_MISC_BASE + 0x6040)
 #define NV_PA_APB_UARTC_BASE   (NV_PA_APB_MISC_BASE + 0x6200)
 #define NV_PA_APB_UARTD_BASE   (NV_PA_APB_MISC_BASE + 0x6300)
 #define NV_PA_APB_UARTE_BASE   (NV_PA_APB_MISC_BASE + 0x6400)
-#define TEGRA20_SPI_BASE       (NV_PA_APB_MISC_BASE + 0xC380)
-#define TEGRA20_PMC_BASE       (NV_PA_APB_MISC_BASE + 0xE400)
-#define TEGRA20_FUSE_BASE      (NV_PA_APB_MISC_BASE + 0xF800)
+#define NV_PA_NAND_BASE                (NV_PA_APB_MISC_BASE + 0x8000)
+#define NV_PA_SPI_BASE         (NV_PA_APB_MISC_BASE + 0xC380)
+#define NV_PA_PMC_BASE         (NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_FUSE_BASE                (NV_PA_APB_MISC_BASE + 0xF800)
 #define NV_PA_CSITE_BASE       0x70040000
 #define TEGRA_USB1_BASE                0xC5000000
 #define TEGRA_USB3_BASE                0xC5008000
 #define TEGRA_USB_ADDR_MASK    0xFFFFC000
 
-#define TEGRA20_SDRC_CS0       NV_PA_SDRAM_BASE
+#define NV_PA_SDRC_CS0         NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK   0x4000FFFC
 #define EARLY_AVP_STACK                (NV_PA_SDRAM_BASE + 0x20000)
 #define EARLY_CPU_STACK                (EARLY_AVP_STACK - 4096)
@@ -85,7 +86,7 @@ enum {
 };
 
 #else  /* __ASSEMBLY__ */
-#define PRM_RSTCTRL            TEGRA20_PMC_BASE
+#define PRM_RSTCTRL            NV_PA_PMC_BASE
 #endif
 
 #endif /* TEGRA20_H */
similarity index 96%
rename from drivers/mmc/tegra_mmc.h
rename to arch/arm/include/asm/arch-tegra20/tegra_mmc.h
index b1f2564..dd746ca 100644 (file)
 #ifndef __TEGRA_MMC_H_
 #define __TEGRA_MMC_H_
 
-#define TEGRA20_SDMMC1_BASE    0xC8000000
-#define TEGRA20_SDMMC2_BASE    0xC8000200
-#define TEGRA20_SDMMC3_BASE    0xC8000400
-#define TEGRA20_SDMMC4_BASE    0xC8000600
+#define TEGRA_SDMMC1_BASE      0xC8000000
+#define TEGRA_SDMMC2_BASE      0xC8000200
+#define TEGRA_SDMMC3_BASE      0xC8000400
+#define TEGRA_SDMMC4_BASE      0xC8000600
 
 #ifndef __ASSEMBLY__
-struct tegra20_mmc {
+struct tegra_mmc {
        unsigned int    sysad;          /* _SYSTEM_ADDRESS_0 */
        unsigned short  blksize;        /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
        unsigned short  blkcnt;         /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
@@ -118,7 +118,7 @@ struct tegra20_mmc {
 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                    (1 << 1)
 
 struct mmc_host {
-       struct tegra20_mmc *reg;
+       struct tegra_mmc *reg;
        unsigned int version;   /* SDHCI spec. version */
        unsigned int clock;     /* Current clock (MHz) */
        unsigned int base;      /* Base address, SDMMC1/2/3/4 */
index 8978bea..d53a93f 100644 (file)
@@ -70,6 +70,6 @@ struct spi_tegra {
 #define SPI_STAT_CUR_BLKCNT            (1 << 15)
 
 #define SPI_TIMEOUT            1000
-#define TEGRA20_SPI_MAX_FREQ   52000000
+#define TEGRA_SPI_MAX_FREQ     52000000
 
 #endif /* _TEGRA_SPI_H_ */
index 43f7ab4..fdb99a7 100644 (file)
@@ -21,8 +21,8 @@
 
 /* Tegra20 timer functions */
 
-#ifndef _TEGRA20_TIMER_H
-#define _TEGRA20_TIMER_H
+#ifndef _TEGRA_TIMER_H
+#define _TEGRA_TIMER_H
 
 /* returns the current monotonic timer value in microseconds */
 unsigned long timer_get_us(void);
index f1951e8..109a1ac 100644 (file)
@@ -241,6 +241,9 @@ init_fnc_t *init_sequence[] = {
        fdtdec_check_fdt,
 #endif
        timer_init,             /* initialize timer */
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+       board_postclk_init,
+#endif
 #ifdef CONFIG_FSL_ESDHC
        get_clocks,
 #endif
index 09ef1d2..3a0ab97 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 #include <command.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+       rcm_t *rcm = (rcm_t *) (MMAP_RCM);
        udelay(1000);
-       rcm->rcr |= RCM_RCR_SOFTRST;
+       setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
        /* we don't return! */
        return 0;
@@ -45,14 +46,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-       volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+       ccm_t *ccm = (ccm_t *) MMAP_CCM;
        u16 msk;
        u16 id = 0;
        u8 ver;
 
        puts("CPU:   ");
-       msk = (ccm->cir >> 6);
-       ver = (ccm->cir & 0x003f);
+       msk = (in_be16(&ccm->cir) >> 6);
+       ver = (in_be16(&ccm->cir) & 0x003f);
        switch (msk) {
        case 0x6c:
                id = 52277;
index beb78f5..e23b20d 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -29,6 +29,7 @@
 #include <watchdog.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 #include <asm/rtc.h>
 
 /*
  */
 void cpu_init_f(void)
 {
-       volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-       volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-       volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+       pll_t *pll = (pll_t *)MMAP_PLL;
 
 #if !defined(CONFIG_CF_SBF)
        /* Workaround, must place before fbcs */
-       pll->psr = 0x12;
-
-       scm1->mpr = 0x77777777;
-       scm1->pacra = 0;
-       scm1->pacrb = 0;
-       scm1->pacrc = 0;
-       scm1->pacrd = 0;
-       scm1->pacre = 0;
-       scm1->pacrf = 0;
-       scm1->pacrg = 0;
-       scm1->pacri = 0;
+       out_be32(&pll->psr, 0x12);
+
+       out_be32(&scm1->mpr, 0x77777777);
+       out_be32(&scm1->pacra, 0);
+       out_be32(&scm1->pacrb, 0);
+       out_be32(&scm1->pacrc, 0);
+       out_be32(&scm1->pacrd, 0);
+       out_be32(&scm1->pacre, 0);
+       out_be32(&scm1->pacrf, 0);
+       out_be32(&scm1->pacrg, 0);
+       out_be32(&scm1->pacri, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-       fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-       fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-       fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+       out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+       out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+       out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 #endif                         /* CONFIG_CF_SBF */
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-       fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-       fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-       fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+       out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+       out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+       out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-       fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-       fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-       fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+       out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+       out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+       out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-       fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-       fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-       fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+       out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+       out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+       out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-       fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-       fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-       fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+       out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+       out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+       out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-       fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-       fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-       fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+       out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+       out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+       out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
+       out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
 #endif
 
        icache_enable();
@@ -115,11 +116,11 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFRTC
-       volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
-       volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+       rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+       rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 
-       rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
-       rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+       out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+       out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 #endif
 
        return (0);
@@ -127,27 +128,27 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->par_uart &=
-                   (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
-               gpio->par_uart |=
-                   (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+               clrbits_be16(&gpio->par_uart,
+                       ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
+               setbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
                break;
        case 1:
-               gpio->par_uart &=
-                   (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
-               gpio->par_uart |=
-                   (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+               clrbits_be16(&gpio->par_uart,
+                       ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
+               setbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
                break;
        case 2:
-               gpio->par_dspi &=
-                   (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
-               gpio->par_dspi =
-                   (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
+               clrbits_8(&gpio->par_dspi,
+                       ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
+               out_8(&gpio->par_dspi,
+                       GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
                break;
        }
 }
@@ -155,32 +156,32 @@ void uart_port_conf(int port)
 #ifdef CONFIG_CF_DSPI
 void cfspi_port_conf(void)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-       gpio->par_dspi =
-           GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-           GPIO_PAR_DSPI_SCK_SCK;
+       out_8(&gpio->par_dspi,
+               GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+               GPIO_PAR_DSPI_SCK_SCK);
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
 {
-       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-       if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+       if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
                return -1;
 
        /* Clear FIFO and resume transfer */
-       dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+       clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
        switch (cs) {
        case 0:
-               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
-               gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+               clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
+               setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
                break;
        case 2:
-               gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
-               gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+               clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
+               setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
                break;
        }
 
@@ -189,17 +190,18 @@ int cfspi_claim_bus(uint bus, uint cs)
 
 void cfspi_release_bus(uint bus, uint cs)
 {
-       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-       dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);  /* Clear FIFO */
+       /* Clear FIFO */
+       clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
        switch (cs) {
        case 0:
-               gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+               clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
                break;
        case 2:
-               gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
+               clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
                break;
        }
 }
index 85828a6..a2cf519 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
        /* Make sure all interrupts are disabled */
-       intp->imrh0 |= 0xFFFFFFFF;
-       intp->imrl0 |= 0xFFFFFFFF;
+       setbits_be32(&intp->imrh0, 0xffffffff);
+       setbits_be32(&intp->imrl0, 0xffffffff);
 
        enable_interrupts();
        return 0;
@@ -44,9 +45,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-       intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-       intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+       out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+       clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif
index 7e385d3..b94a9ed 100644 (file)
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -26,6 +26,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -44,7 +45,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void clock_enter_limp(int lpdiv)
 {
-       volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
+       ccm_t *ccm = (ccm_t *)MMAP_CCM;
        int i, j;
 
        /* Check bounds of divider */
@@ -57,10 +58,10 @@ void clock_enter_limp(int lpdiv)
        for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
        /* Apply the divider to the system clock */
-       ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
+       clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
 
        /* Enable Limp Mode */
-       ccm->misccr |= CCM_MISCCR_LIMP;
+       setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 }
 
 /*
@@ -69,14 +70,15 @@ void clock_enter_limp(int lpdiv)
  */
 void clock_exit_limp(void)
 {
-       volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-       volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+       ccm_t *ccm = (ccm_t *)MMAP_CCM;
+       pll_t *pll = (pll_t *)MMAP_PLL;
 
        /* Exit Limp mode */
-       ccm->misccr &= ~CCM_MISCCR_LIMP;
+       clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
        /* Wait for the PLL to lock */
-       while (!(pll->psr & PLL_PSR_LOCK)) ;
+       while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
+               ;
 }
 
 /*
@@ -85,12 +87,12 @@ void clock_exit_limp(void)
 int get_clocks(void)
 {
 
-       volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
-       volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+       ccm_t *ccm = (ccm_t *)MMAP_CCM;
+       pll_t *pll = (pll_t *)MMAP_PLL;
        int vco, temp, pcrvalue, pfdr;
        u8 bootmode;
 
-       pcrvalue = pll->pcr & 0xFF0F0FFF;
+       pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
        pfdr = pcrvalue >> 24;
 
        if (pfdr == 0x1E)
@@ -102,32 +104,32 @@ int get_clocks(void)
 
        if (bootmode == 0) {
                /* Normal mode */
-               vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+               vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
                if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
                        /* Default value */
-                       pcrvalue = (pll->pcr & 0x00FFFFFF);
+                       pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
                        pcrvalue |= 0x1E << 24;
-                       pll->pcr = pcrvalue;
+                       out_be32(&pll->pcr, pcrvalue);
                        vco =
-                           ((pll->pcr & 0xFF000000) >> 24) *
+                           ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
                            CONFIG_SYS_INPUT_CLKSRC;
                }
                gd->vco_clk = vco;      /* Vco clock */
        } else if (bootmode == 3) {
                /* serial mode */
-               vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+               vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
                gd->vco_clk = vco;      /* Vco clock */
        }
 
-       if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
+       if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
                /* Limp mode */
        } else {
                gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;  /* Input clock */
 
-               temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
+               temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
                gd->cpu_clk = vco / temp;       /* cpu clock */
 
-               temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
+               temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
                gd->flb_clk = vco / temp;       /* flexbus clock */
                gd->bus_clk = gd->flb_clk;
        }
index 2376f97..a3f5684 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+       ccm_t *ccm = (ccm_t *) MMAP_CCM;
 
-       ccm->rcr = CCM_RCR_SOFTRST;
+       out_8(&ccm->rcr, CCM_RCR_SOFTRST);
        /* we don't return! */
        return 0;
-};
+}
 
 int checkcpu(void)
 {
-       volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+       ccm_t *ccm = (ccm_t *) MMAP_CCM;
        u16 msk;
        u16 id = 0;
        u8 ver;
 
        puts("CPU:   ");
-       msk = (ccm->cir >> 6);
-       ver = (ccm->cir & 0x003f);
+       msk = (in_be16(&ccm->cir) >> 6);
+       ver = (in_be16(&ccm->cir) & 0x003f);
        switch (msk) {
        case 0x31:
                id = 5235;
@@ -76,19 +77,21 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-       volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+       wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
-       wdp->sr = 0x5555;       /* Count register */
+       /* Count register */
+       out_be16(&wdp->sr, 0x5555);
        asm("nop");
-       wdp->sr = 0xAAAA;       /* Count register */
+       out_be16(&wdp->sr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-       volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+       wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
        /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
-       wdp->cr |= WTM_WCR_HALTED;      /* halted watchdog timer */
+       /* halted watchdog timer */
+       setbits_be16(&wdp->cr, WTM_WCR_HALTED);
 
        puts("WATCHDOG:disabled\n");
        return (0);
@@ -96,15 +99,15 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-       volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+       wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
        u32 wdog_module = 0;
 
        /* set timeout and enable watchdog */
        wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) * CONFIG_WATCHDOG_TIMEOUT);
        wdog_module |= (wdog_module / 8192);
-       wdp->mr = wdog_module;
+       out_be16(&wdp->mr, wdog_module);
 
-       wdp->cr = WTM_WCR_EN;
+       out_be16(&wdp->cr, WTM_WCR_EN);
        puts("WATCHDOG:enabled\n");
 
        return (0);
index 0f299f0..d1c0b40 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
  */
 void cpu_init_f(void)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-       volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-       volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
-       volatile scm_t *scm = (scm_t *) MMAP_SCM;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+       wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+       scm_t *scm = (scm_t *) MMAP_SCM;
 
        /* watchdog is enabled by default - disable the watchdog */
 #ifndef CONFIG_WATCHDOG
-       wdog->cr = 0;
+       out_be16(&wdog->cr, 0);
 #endif
 
-       scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+       out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
 
        /* Port configuration */
-       gpio->par_cs = 0;
+       out_8(&gpio->par_cs, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-       fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-       fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-       fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+       out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+       out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+       out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS_CS1;
-       fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-       fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-       fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
+       out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+       out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+       out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS_CS2;
-       fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-       fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-       fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
+       out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+       out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+       out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS_CS3;
-       fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-       fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-       fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
+       out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+       out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+       out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS_CS4;
-       fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-       fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-       fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
+       out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+       out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+       out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS_CS5;
-       fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-       fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-       fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
+       out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+       out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+       out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS_CS6;
-       fbcs->csar6 = CONFIG_SYS_CS6_BASE;
-       fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
-       fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
+       out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+       out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+       out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS_CS7;
-       fbcs->csar7 = CONFIG_SYS_CS7_BASE;
-       fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
-       fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
+       out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+       out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+       out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
@@ -132,29 +133,33 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->par_uart &= ~(GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
-               gpio->par_uart |= (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+               clrbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
+               setbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
                break;
        case 1:
-               gpio->par_uart &=
-                   ~(GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
-               gpio->par_uart |=
-                   (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
+               clrbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
+               setbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
                break;
        case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-               gpio->par_uart &= ~(GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
-               gpio->par_uart |= (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+               clrbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
+               setbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
-               gpio->feci2c &=
-                   ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
-               gpio->feci2c |=
-                   (GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
+               clrbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
 #endif
                break;
        }
@@ -163,15 +168,16 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        if (setclear) {
-               gpio->par_feci2c |=
-                   (GPIO_PAR_FECI2C_EMDC_FECEMDC |
-                    GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_EMDC_FECEMDC |
+                       GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
        } else {
-               gpio->par_feci2c &=
-                   ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
+               clrbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_EMDC_MASK |
+                       GPIO_PAR_FECI2C_EMDIO_MASK);
        }
 
        return 0;
index db5ccdf..76115a4 100644 (file)
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
        /* Make sure all interrupts are disabled */
-       intp->imrl0 |= 0x1;
+       setbits_be32(&intp->imrl0, 0x1);
 
        enable_interrupts();
        return 0;
@@ -40,10 +41,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-       intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-       intp->imrl0 &= ~INTC_IPRL_INT0;
-       intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+       out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+       clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
+       clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif
index 6096ba4..e2a6ae3 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -29,6 +29,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 /*
@@ -36,11 +37,12 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int get_clocks(void)
 {
-       volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+       pll_t *pll = (pll_t *)(MMAP_PLL);
 
-       pll->syncr = PLL_SYNCR_MFD(1);
+       out_be32(&pll->syncr, PLL_SYNCR_MFD(1));
 
-       while (!(pll->synsr & PLL_SYNSR_LOCK));
+       while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK))
+               ;
 
        gd->bus_clk = CONFIG_SYS_CLK;
        gd->cpu_clk = (gd->bus_clk * 2);
index 571d078..7c6100c 100644 (file)
@@ -9,6 +9,8 @@
  * MCF5275 additions
  * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
  *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -32,6 +34,7 @@
 #include <watchdog.h>
 #include <command.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 #include <netdev.h>
 #include "cpu.h"
 
@@ -40,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_M5208
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+       rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 
        udelay(1000);
 
-       rcm->rcr = RCM_RCR_SOFTRST;
+       out_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
        /* we don't return! */
        return 0;
@@ -65,18 +68,21 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-       wdt->sr = 0x5555;
-       wdt->sr = 0xAAAA;
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+       out_be16(&wdt->sr, 0x5555);
+       out_be16(&wdt->sr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-       wdt->sr = 0x5555; /* reset watchdog counter */
-       wdt->sr = 0xAAAA;
-       wdt->cr = 0;    /* disable watchdog timer */
+       /* reset watchdog counter */
+       out_be16(&wdt->sr, 0x5555);
+       out_be16(&wdt->sr, 0xaaaa);
+       /* disable watchdog timer */
+       out_be16(&wdt->cr, 0);
 
        puts("WATCHDOG:disabled\n");
        return (0);
@@ -84,15 +90,18 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-       wdt->cr = 0;    /* disable watchdog */
+       /* disable watchdog */
+       out_be16(&wdt->cr, 0);
 
        /* set timeout and enable watchdog */
-       wdt->mr =
-               ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-       wdt->sr = 0x5555; /* reset watchdog counter */
-       wdt->sr = 0xAAAA;
+       out_be16(&wdt->mr,
+               (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+       /* reset watchdog counter */
+       out_be16(&wdt->sr, 0x5555);
+       out_be16(&wdt->sr, 0xaaaa);
 
        puts("WATCHDOG:enabled\n");
        return (0);
@@ -178,13 +187,13 @@ int watchdog_init(void)
 #ifdef CONFIG_M5272
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+       wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
-       wdp->wdog_wrrr = 0;
+       out_be16(&wdp->wdog_wrrr, 0);
        udelay(1000);
 
        /* enable watchdog, set timeout to 0 and wait */
-       wdp->wdog_wrrr = 1;
+       out_be16(&wdp->wdog_wrrr, 1);
        while (1) ;
 
        /* we don't return! */
@@ -193,12 +202,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-       volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
+       sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
        uchar msk;
        char *suf;
 
        puts("CPU:   ");
-       msk = (sysctrl->sc_dir > 28) & 0xf;
+       msk = (in_be32(&sysctrl->sc_dir) > 28) & 0xf;
        switch (msk) {
        case 0x2:
                suf = "1K75N";
@@ -221,17 +230,21 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-       wdt->wdog_wcr = 0;
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+       out_be16(&wdt->wdog_wcr, 0);
 }
 
 int watchdog_disable(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-       wdt->wdog_wcr = 0;      /* reset watchdog counter */
-       wdt->wdog_wirr = 0;     /* disable watchdog interrupt */
-       wdt->wdog_wrrr = 0;     /* disable watchdog timer */
+       /* reset watchdog counter */
+       out_be16(&wdt->wdog_wcr, 0);
+       /* disable watchdog interrupt */
+       out_be16(&wdt->wdog_wirr, 0);
+       /* disable watchdog timer */
+       out_be16(&wdt->wdog_wrrr, 0);
 
        puts("WATCHDOG:disabled\n");
        return (0);
@@ -239,14 +252,17 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-       wdt->wdog_wirr = 0;     /* disable watchdog interrupt */
+       /* disable watchdog interrupt */
+       out_be16(&wdt->wdog_wirr, 0);
 
        /* set timeout and enable watchdog */
-       wdt->wdog_wrrr =
-           ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-       wdt->wdog_wcr = 0;      /* reset watchdog counter */
+       out_be16(&wdt->wdog_wrrr,
+               (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+       /* reset watchdog counter */
+       out_be16(&wdt->wdog_wcr, 0);
 
        puts("WATCHDOG:enabled\n");
        return (0);
@@ -258,11 +274,11 @@ int watchdog_init(void)
 #ifdef CONFIG_M5275
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+       rcm_t *rcm = (rcm_t *)(MMAP_RCM);
 
        udelay(1000);
 
-       rcm->rcr = RCM_RCR_SOFTRST;
+       out_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
        /* we don't return! */
        return 0;
@@ -282,18 +298,22 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-       wdt->wsr = 0x5555;
-       wdt->wsr = 0xAAAA;
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+       out_be16(&wdt->wsr, 0x5555);
+       out_be16(&wdt->wsr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-       wdt->wsr = 0x5555; /* reset watchdog counter */
-       wdt->wsr = 0xAAAA;
-       wdt->wcr = 0;   /* disable watchdog timer */
+       /* reset watchdog counter */
+       out_be16(&wdt->wsr, 0x5555);
+       out_be16(&wdt->wsr, 0xaaaa);
+
+       /* disable watchdog timer */
+       out_be16(&wdt->wcr, 0);
 
        puts("WATCHDOG:disabled\n");
        return (0);
@@ -301,15 +321,18 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-       volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+       wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
 
-       wdt->wcr = 0;   /* disable watchdog */
+       /* disable watchdog */
+       out_be16(&wdt->wcr, 0);
 
        /* set timeout and enable watchdog */
-       wdt->wmr =
-               ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-       wdt->wsr = 0x5555; /* reset watchdog counter */
-       wdt->wsr = 0xAAAA;
+       out_be16(&wdt->wmr,
+               (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+       /* reset watchdog counter */
+       out_be16(&wdt->wsr, 0x5555);
+       out_be16(&wdt->wsr, 0xaaaa);
 
        puts("WATCHDOG:enabled\n");
        return (0);
index a98a926..5d0e9f0 100644 (file)
@@ -8,7 +8,7 @@
  * (c) Copyright 2010
  * Arcturus Networks Inc. <www.arcturusnetworks.com>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
@@ -37,6 +37,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
 /* Only 5272 Flexbus chipselect is different from the rest */
 void init_fbcs(void)
 {
-       volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
+       fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-       fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-       fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-       fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+       out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+       out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+       out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #else
 #warning "Chip Select 0 are not initialized/used"
 #endif
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-       fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-       fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-       fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+       out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+       out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+       out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-       fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-       fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-       fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+       out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+       out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+       out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-       fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-       fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-       fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+       out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+       out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+       out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-       fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-       fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-       fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+       out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+       out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+       out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-       fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-       fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-       fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+       out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+       out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+       out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
      && defined(CONFIG_SYS_CS6_CTRL))
-       fbcs->csar6 = CONFIG_SYS_CS6_BASE;
-       fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
-       fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
+       out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+       out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+       out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
      && defined(CONFIG_SYS_CS7_CTRL))
-       fbcs->csar7 = CONFIG_SYS_CS7_BASE;
-       fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
-       fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
+       out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+       out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+       out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif
 }
 #endif
@@ -106,22 +107,22 @@ void init_fbcs(void)
 #if defined(CONFIG_M5208)
 void cpu_init_f(void)
 {
-       volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 
 #ifndef CONFIG_WATCHDOG
-       volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
+       wdog_t *wdg = (wdog_t *) MMAP_WDOG;
 
        /* Disable the watchdog if we aren't using it */
-       wdg->cr = 0;
+       out_be16(&wdg->cr, 0);
 #endif
 
-       scm1->mpr = 0x77777777;
-       scm1->pacra = 0;
-       scm1->pacrb = 0;
-       scm1->pacrc = 0;
-       scm1->pacrd = 0;
-       scm1->pacre = 0;
-       scm1->pacrf = 0;
+       out_be32(&scm1->mpr, 0x77777777);
+       out_be32(&scm1->pacra, 0);
+       out_be32(&scm1->pacrb, 0);
+       out_be32(&scm1->pacrc, 0);
+       out_be32(&scm1->pacrd, 0);
+       out_be32(&scm1->pacre, 0);
+       out_be32(&scm1->pacrf, 0);
 
        /* FlexBus Chipselect */
        init_fbcs();
@@ -137,36 +138,36 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-               gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+               clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+               setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
                break;
        case 1:
-               gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-               gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
+               clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
+               setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
                break;
        case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-               gpio->par_timer &=
-                   (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
-               gpio->par_timer |=
-                   (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
+               clrbits_8(&gpio->par_timer,
+                       ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
+               setbits_8(&gpio->par_timer,
+                       GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-               gpio->par_feci2c &=
-                   (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
-               gpio->par_feci2c |=
-                   (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
+               clrbits_8(&gpio->par_feci2c,
+                       ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
 #endif
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-               gpio->par_feci2c &=
-                   (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
-               gpio->par_feci2c |=
-                   (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+               clrbits_8(&gpio->par_feci2c,
+                       ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
                break;
        }
@@ -175,17 +176,17 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        if (setclear) {
-               gpio->par_fec |=
-                   GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
-               gpio->par_feci2c |=
-                   GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
+               setbits_8(&gpio->par_fec,
+                       GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
        } else {
-               gpio->par_fec &=
-                   (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
-               gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
+               clrbits_8(&gpio->par_fec,
+                       ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
+               clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
        }
        return 0;
 }
@@ -249,17 +250,17 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile u32 *par = (u32 *) MMAP_PAR;
+       u32 *par = (u32 *) MMAP_PAR;
 
        /* Setup Ports: */
        switch (port) {
        case 1:
-               *par &= 0xFFE7FFFF;
-               *par |= 0x00180000;
+               clrbits_be32(par, 0x00180000);
+               setbits_be32(par, 0x00180000);
                break;
        case 2:
-               *par &= 0xFFFFFFFC;
-               *par &= 0x00000003;
+               clrbits_be32(par, 0x00000003);
+               clrbits_be32(par, 0xFFFFFFFC);
                break;
        }
 }
@@ -332,7 +333,20 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
        return 0;
 }
 #endif                         /* CONFIG_CMD_NET */
-#endif
+
+#if defined(CONFIG_CF_QSPI)
+
+/* Configure PIOs for SIN, SOUT, and SCK */
+void cfspi_port_conf(void)
+{
+       mbar_writeByte(MCF_GPIO_PAR_QSPI,
+                      MCF_GPIO_PAR_QSPI_SIN_SIN   |
+                      MCF_GPIO_PAR_QSPI_SOUT_SOUT |
+                      MCF_GPIO_PAR_QSPI_SCK_SCK);
+}
+#endif                         /* CONFIG_CF_QSPI */
+
+#endif                         /* CONFIG_M5271 */
 
 #if defined(CONFIG_M5272)
 /*
@@ -348,59 +362,59 @@ void cpu_init_f(void)
         * already initialized.
         */
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-       volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
-       volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
-       volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
+       sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
+       gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+       csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
 
-       sysctrl->sc_scr = CONFIG_SYS_SCR;
-       sysctrl->sc_spr = CONFIG_SYS_SPR;
+       out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
+       out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
 
        /* Setup Ports: */
-       gpio->gpio_pacnt = CONFIG_SYS_PACNT;
-       gpio->gpio_paddr = CONFIG_SYS_PADDR;
-       gpio->gpio_padat = CONFIG_SYS_PADAT;
-       gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
-       gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
-       gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
-       gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
+       out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
+       out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
+       out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
+       out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
+       out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
+       out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
+       out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
 
        /* Memory Controller: */
-       csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
-       csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
+       out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
+       out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
 
 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
-       csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
-       csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
+       out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
+       out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-       csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
-       csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
+       out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
+       out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
-       csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
-       csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
+       out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
+       out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
-       csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
-       csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
+       out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
+       out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
-       csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
-       csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
+       out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
+       out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
-       csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
-       csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
+       out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
+       out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
 #endif
 
 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
-       csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
-       csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
+       out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
+       out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
 #endif
 
 #endif                         /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
@@ -420,17 +434,21 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
-               gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+               clrbits_be32(&gpio->gpio_pbcnt,
+                       GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+               setbits_be32(&gpio->gpio_pbcnt,
+                       GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
                break;
        case 1:
-               gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
-               gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+               clrbits_be32(&gpio->gpio_pdcnt,
+                       GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+               setbits_be32(&gpio->gpio_pdcnt,
+                       GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
                break;
        }
 }
@@ -438,13 +456,14 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        if (setclear) {
-               gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
-                                   GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
-                                   GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
-                                   GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
+               setbits_be32(&gpio->gpio_pbcnt,
+                       GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
+                       GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
+                       GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
+                       GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
        } else {
        }
        return 0;
@@ -469,11 +488,11 @@ void cpu_init_f(void)
         */
 
 #ifndef CONFIG_MONITOR_IS_IN_RAM
-       volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
-       volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
+       wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
+       gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
 
        /* Kill watchdog so we can initialize the PLL */
-       wdog_reg->wcr = 0;
+       out_be16(&wdog_reg->wcr, 0);
 
        /* FlexBus Chipselect */
        init_fbcs();
@@ -498,21 +517,21 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->par_uart &= ~UART0_ENABLE_MASK;
-               gpio->par_uart |= UART0_ENABLE_MASK;
+               clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
+               setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
                break;
        case 1:
-               gpio->par_uart &= ~UART1_ENABLE_MASK;
-               gpio->par_uart |= UART1_ENABLE_MASK;
+               clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
+               setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
                break;
        case 2:
-               gpio->par_uart &= ~UART2_ENABLE_MASK;
-               gpio->par_uart |= UART2_ENABLE_MASK;
+               clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
+               setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
                break;
        }
 }
@@ -521,24 +540,24 @@ void uart_port_conf(int port)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
        struct fec_info_s *info = (struct fec_info_s *) dev->priv;
-       volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 
        if (setclear) {
                /* Enable Ethernet pins */
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-                       gpio->par_feci2c |= 0x0F00;
-                       gpio->par_fec0hl |= 0xC0;
+                       setbits_be16(&gpio->par_feci2c, 0x0f00);
+                       setbits_8(&gpio->par_fec0hl, 0xc0);
                } else {
-                       gpio->par_feci2c |= 0x00A0;
-                       gpio->par_fec1hl |= 0xC0;
+                       setbits_be16(&gpio->par_feci2c, 0x00a0);
+                       setbits_8(&gpio->par_fec1hl, 0xc0);
                }
        } else {
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-                       gpio->par_feci2c &= ~0x0F00;
-                       gpio->par_fec0hl &= ~0xC0;
+                       clrbits_be16(&gpio->par_feci2c, 0x0f00);
+                       clrbits_8(&gpio->par_fec0hl, 0xc0);
                } else {
-                       gpio->par_feci2c &= ~0x00A0;
-                       gpio->par_fec1hl &= ~0xC0;
+                       clrbits_be16(&gpio->par_feci2c, 0x00a0);
+                       clrbits_8(&gpio->par_fec1hl, 0xc0);
                }
        }
 
index dff8c6a..915eb70 100644 (file)
@@ -2,7 +2,7 @@
  * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #ifdef CONFIG_M5272
 int interrupt_init(void)
 {
-       volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
+       intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
 
        /* disable all external interrupts */
-       intp->int_icr1 = 0x88888888;
-       intp->int_icr2 = 0x88888888;
-       intp->int_icr3 = 0x88888888;
-       intp->int_icr4 = 0x88888888;
-       intp->int_pitr = 0x00000000;
+       out_be32(&intp->int_icr1, 0x88888888);
+       out_be32(&intp->int_icr2, 0x88888888);
+       out_be32(&intp->int_icr3, 0x88888888);
+       out_be32(&intp->int_icr4, 0x88888888);
+       out_be32(&intp->int_pitr, 0x00000000);
+
        /* initialize vector register */
-       intp->int_pivr = 0x40;
+       out_8(&intp->int_pivr, 0x40);
 
        enable_interrupts();
 
@@ -51,10 +53,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-       volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+       intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
 
-       intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
-       intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
+       clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
+       setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
 }
 #endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5272 */
@@ -63,14 +65,14 @@ void dtimer_intr_setup(void)
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
        /* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
-       intp->imrl0 = 0xFFFFFFFF;
-       intp->imrh0 = 0xFFFFFFFF;
+       out_be32(&intp->imrl0, 0xffffffff);
+       out_be32(&intp->imrh0, 0xffffffff);
 #else
-       intp->imrl0 |= 0x1;
+       setbits_be32(&intp->imrl0, 0x1);
 #endif
 
        enable_interrupts();
@@ -80,11 +82,11 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-       intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-       intp->imrl0 &= 0xFFFFFFFE;
-       intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+       out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+       clrbits_be32(&intp->imrl0, 0x00000001);
+       clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif                         /* CONFIG_MCFTMR */
 #endif                         /* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
index b485e1c..70abed2 100644 (file)
@@ -2,7 +2,7 @@
  * (C) Copyright 2003
  * Josef Baumgartner <josef.baumgartner@telex.de>
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -34,10 +35,10 @@ DECLARE_GLOBAL_DATA_PTR;
 int get_clocks (void)
 {
 #if defined(CONFIG_M5208)
-       volatile pll_t *pll = (pll_t *) MMAP_PLL;
+       pll_t *pll = (pll_t *) MMAP_PLL;
 
-       pll->odr = CONFIG_SYS_PLL_ODR;
-       pll->fdr = CONFIG_SYS_PLL_FDR;
+       out_8(&pll->odr, CONFIG_SYS_PLL_ODR);
+       out_8(&pll->fdr, CONFIG_SYS_PLL_FDR);
 #endif
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
@@ -70,14 +71,14 @@ int get_clocks (void)
 #endif                         /* CONFIG_M5249 || CONFIG_M5253 */
 
 #if defined(CONFIG_M5275)
-       volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+       pll_t *pll = (pll_t *)(MMAP_PLL);
 
        /* Setup PLL */
-       pll->syncr = 0x01080000;
-       while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+       out_be32(&pll->syncr, 0x01080000);
+       while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
                ;
-       pll->syncr = 0x01000000;
-       while (!(pll->synsr & FMPLL_SYNSR_LOCK))
+       out_be32(&pll->syncr, 0x01000000);
+       while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK))
                ;
 #endif
 
index 3346784..4f160a6 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+       rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 
        udelay(1000);
-       rcm->rcr |= RCM_RCR_SOFTRST;
+       setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
        /* we don't return! */
        return 0;
@@ -47,14 +48,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-       volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+       ccm_t *ccm = (ccm_t *) MMAP_CCM;
        u16 msk;
        u16 id = 0;
        u8 ver;
 
        puts("CPU:   ");
-       msk = (ccm->cir >> 6);
-       ver = (ccm->cir & 0x003f);
+       msk = (in_be16(&ccm->cir) >> 6);
+       ver = (in_be16(&ccm->cir) & 0x003f);
        switch (msk) {
 #ifdef CONFIG_MCF5301x
        case 0x78:
@@ -115,18 +116,20 @@ int checkcpu(void)
 /* Called by macro WATCHDOG_RESET */
 void watchdog_reset(void)
 {
-       volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+       wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
-       wdp->sr = 0x5555;       /* Count register */
-       wdp->sr = 0xAAAA;       /* Count register */
+       /* Count register */
+       out_be16(&wdp->sr, 0x5555);
+       out_be16(&wdp->sr, 0xaaaa);
 }
 
 int watchdog_disable(void)
 {
-       volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+       wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
 
        /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
-       wdp->cr |= WTM_WCR_HALTED;      /* halted watchdog timer */
+       /* halted watchdog timer */
+       setbits_be16(&wdp->cr, WTM_WCR_HALTED);
 
        puts("WATCHDOG:disabled\n");
        return (0);
@@ -134,18 +137,18 @@ int watchdog_disable(void)
 
 int watchdog_init(void)
 {
-       volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+       wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
        u32 wdog_module = 0;
 
        /* set timeout and enable watchdog */
        wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
 #ifdef CONFIG_M5329
-       wdp->mr = (wdog_module / 8192);
+       out_be16(&wdp->mr, wdog_module / 8192);
 #else
-       wdp->mr = (wdog_module / 4096);
+       out_be16(&wdp->mr, wdog_module / 4096);
 #endif
 
-       wdp->cr = WTM_WCR_EN;
+       out_be16(&wdp->cr, WTM_WCR_EN);
        puts("WATCHDOG:enabled\n");
 
        return (0);
index 6f551b6..f571fad 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
 #include <common.h>
 #include <watchdog.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
 #ifdef CONFIG_MCF5301x
 void cpu_init_f(void)
 {
-       volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-       volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
-       /* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
-       /*wdog->cr = 0; */
-#endif
-
-       scm1->mpr = 0x77777777;
-       scm1->pacra = 0;
-       scm1->pacrb = 0;
-       scm1->pacrc = 0;
-       scm1->pacrd = 0;
-       scm1->pacre = 0;
-       scm1->pacrf = 0;
-       scm1->pacrg = 0;
+       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+       out_be32(&scm1->mpr, 0x77777777);
+       out_be32(&scm1->pacra, 0);
+       out_be32(&scm1->pacrb, 0);
+       out_be32(&scm1->pacrc, 0);
+       out_be32(&scm1->pacrd, 0);
+       out_be32(&scm1->pacre, 0);
+       out_be32(&scm1->pacrf, 0);
+       out_be32(&scm1->pacrg, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS0_CS0;
-       fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-       fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-       fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS0_CS0);
+       out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+       out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+       out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS1_CS1;
-       fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-       fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-       fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS1_CS1);
+       out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+       out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+       out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-       fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-       fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-       fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+       out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+       out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+       out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-       fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-       fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-       fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+       out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+       out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+       out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS4;
-       fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-       fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-       fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+       out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+       out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+       out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS5;
-       fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-       fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-       fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+       out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+       out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+       out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
+       out_8(&gpio->par_feci2c,
+               GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL);
 #endif
 
        icache_enable();
@@ -113,21 +110,21 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFFEC
-       volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+       ccm_t *ccm = (ccm_t *) MMAP_CCM;
 #endif
 #ifdef CONFIG_MCFRTC
-       volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
-       volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
+       rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
+       rtcex_t *rtcex = (rtcex_t *) &rtc->extended;
 
-       rtcex->gocu = CONFIG_SYS_RTC_CNT;
-       rtcex->gocl = CONFIG_SYS_RTC_SETUP;
+       out_be32(&rtcex->gocu, CONFIG_SYS_RTC_CNT);
+       out_be32(&rtcex->gocl, CONFIG_SYS_RTC_SETUP);
 
 #endif
 #ifdef CONFIG_MCFFEC
        if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
-               ccm->misccr |= CCM_MISCCR_FECM;
+               setbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
        else
-               ccm->misccr &= ~CCM_MISCCR_FECM;
+               clrbits_be16(&ccm->misccr, CCM_MISCCR_FECM);
 #endif
 
        return (0);
@@ -135,41 +132,52 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->par_uart &= ~(GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
-               gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+               clrbits_8(&gpio->par_uart,
+                       GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
+               setbits_8(&gpio->par_uart,
+                       GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
                break;
        case 1:
 #ifdef CONFIG_SYS_UART1_ALT1_GPIO
-               gpio->par_simp1h &=
-                   ~(GPIO_PAR_SIMP1H_DATA1_UNMASK |
-                     GPIO_PAR_SIMP1H_VEN1_UNMASK);
-               gpio->par_simp1h |=
-                   (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
+               clrbits_8(&gpio->par_simp1h,
+                       GPIO_PAR_SIMP1H_DATA1_UNMASK |
+                       GPIO_PAR_SIMP1H_VEN1_UNMASK);
+               setbits_8(&gpio->par_simp1h,
+                       GPIO_PAR_SIMP1H_DATA1_U1TXD |
+                       GPIO_PAR_SIMP1H_VEN1_U1RXD);
 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
-               gpio->par_ssih &=
-                   ~(GPIO_PAR_SSIH_RXD_UNMASK | GPIO_PAR_SSIH_TXD_UNMASK);
-               gpio->par_ssih |=
-                   (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
+               clrbits_8(&gpio->par_ssih,
+                       GPIO_PAR_SSIH_RXD_UNMASK |
+                       GPIO_PAR_SSIH_TXD_UNMASK);
+               setbits_8(&gpio->par_ssih,
+                       GPIO_PAR_SSIH_RXD_U1RXD |
+                       GPIO_PAR_SSIH_TXD_U1TXD);
 #endif
                break;
        case 2:
 #ifdef CONFIG_SYS_UART2_PRI_GPIO
-               gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
+               setbits_8(&gpio->par_uart,
+                       GPIO_PAR_UART_U2TXD |
+                       GPIO_PAR_UART_U2RXD);
 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
-               gpio->par_dspih &=
-                   ~(GPIO_PAR_DSPIH_SIN_UNMASK | GPIO_PAR_DSPIH_SOUT_UNMASK);
-               gpio->par_dspih |=
-                   (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
+               clrbits_8(&gpio->par_dspih,
+                       GPIO_PAR_DSPIH_SIN_UNMASK |
+                       GPIO_PAR_DSPIH_SOUT_UNMASK);
+               setbits_8(&gpio->par_dspih,
+                       GPIO_PAR_DSPIH_SIN_U2RXD |
+                       GPIO_PAR_DSPIH_SOUT_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-               gpio->par_feci2c &=
-                   ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
-               gpio->par_feci2c |=
-                   (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
+               clrbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_SDA_UNMASK |
+                       GPIO_PAR_FECI2C_SCL_UNMASK);
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_SDA_U2TXD |
+                       GPIO_PAR_FECI2C_SCL_U2RXD);
 #endif
                break;
        }
@@ -178,30 +186,30 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
        struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
        if (setclear) {
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-                       gpio->par_fec |=
-                           GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
-                       gpio->par_feci2c |=
-                           GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
+                       setbits_8(&gpio->par_fec,
+                               GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+                       setbits_8(&gpio->par_feci2c,
+                               GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0);
                } else {
-                       gpio->par_fec |=
-                           GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
-                       gpio->par_feci2c |=
-                           GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
+                       setbits_8(&gpio->par_fec,
+                               GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+                       setbits_8(&gpio->par_feci2c,
+                               GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1);
                }
        } else {
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-                       gpio->par_fec &=
-                           ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
-                       gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_UNMASK;
+                       clrbits_8(&gpio->par_fec,
+                               GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
+                       clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII0_UNMASK);
                } else {
-                       gpio->par_fec &=
-                           ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
-                       gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_UNMASK;
+                       clrbits_8(&gpio->par_fec,
+                               GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
+                       clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII1_UNMASK);
                }
        }
        return 0;
@@ -212,80 +220,81 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 #ifdef CONFIG_MCF532x
 void cpu_init_f(void)
 {
-       volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-       volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-       volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-       volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+       scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+       wdog_t *wdog = (wdog_t *) MMAP_WDOG;
 
        /* watchdog is enabled by default - disable the watchdog */
 #ifndef CONFIG_WATCHDOG
-       wdog->cr = 0;
+       out_be16(&wdog->cr, 0);
 #endif
 
-       scm1->mpr0 = 0x77777777;
-       scm2->pacra = 0;
-       scm2->pacrb = 0;
-       scm2->pacrc = 0;
-       scm2->pacrd = 0;
-       scm2->pacre = 0;
-       scm2->pacrf = 0;
-       scm2->pacrg = 0;
-       scm1->pacrh = 0;
+       out_be32(&scm1->mpr0, 0x77777777);
+       out_be32(&scm2->pacra, 0);
+       out_be32(&scm2->pacrb, 0);
+       out_be32(&scm2->pacrc, 0);
+       out_be32(&scm2->pacrd, 0);
+       out_be32(&scm2->pacre, 0);
+       out_be32(&scm2->pacrf, 0);
+       out_be32(&scm2->pacrg, 0);
+       out_be32(&scm1->pacrh, 0);
 
        /* Port configuration */
-       gpio->par_cs = 0;
+       out_8(&gpio->par_cs, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
      && defined(CONFIG_SYS_CS0_CTRL))
-       fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-       fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-       fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+       out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+       out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+       out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
      && defined(CONFIG_SYS_CS1_CTRL))
        /* Latch chipselect */
-       gpio->par_cs |= GPIO_PAR_CS1;
-       fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-       fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-       fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS1);
+       out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+       out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+       out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
      && defined(CONFIG_SYS_CS2_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS2;
-       fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-       fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-       fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS2);
+       out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+       out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+       out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
      && defined(CONFIG_SYS_CS3_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS3;
-       fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-       fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-       fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS3);
+       out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+       out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+       out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
      && defined(CONFIG_SYS_CS4_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS4;
-       fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-       fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-       fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS4);
+       out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+       out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+       out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
      && defined(CONFIG_SYS_CS5_CTRL))
-       gpio->par_cs |= GPIO_PAR_CS5;
-       fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-       fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-       fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+       setbits_8(&gpio->par_cs, GPIO_PAR_CS5);
+       out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+       out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+       out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #ifdef CONFIG_FSL_I2C
-       gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+       out_8(&gpio->par_feci2c,
+               GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
 #endif
 
        icache_enable();
@@ -301,30 +310,35 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->par_uart &= ~(GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
-               gpio->par_uart |= (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+               clrbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
+               setbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
                break;
        case 1:
-               gpio->par_uart &=
-                   ~(GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
-               gpio->par_uart |=
-                   (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+               clrbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
+               setbits_be16(&gpio->par_uart,
+                       GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
                break;
        case 2:
 #ifdef CONFIG_SYS_UART2_ALT1_GPIO
-               gpio->par_timer &= 0x0F;
-               gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
+               clrbits_8(&gpio->par_timer, 0xf0);
+               setbits_8(&gpio->par_timer,
+                       GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-               gpio->par_feci2c &= 0xFF00;
-               gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
+               clrbits_8(&gpio->par_feci2c, 0x00ff);
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_SCL_UTXD2 | GPIO_PAR_FECI2C_SDA_URXD2);
 #elif defined(CONFIG_SYS_UART2_ALT3_GPIO)
-               gpio->par_ssi &= 0xF0FF;
-               gpio->par_ssi |= (GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
+               clrbits_be16(&gpio->par_ssi, 0x0f00);
+               setbits_be16(&gpio->par_ssi,
+                       GPIO_PAR_SSI_RXD(2) | GPIO_PAR_SSI_TXD(2));
 #endif
                break;
        }
@@ -333,16 +347,18 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        if (setclear) {
-               gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
-               gpio->par_feci2c |=
-                   GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
+               setbits_8(&gpio->par_fec,
+                       GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+               setbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
        } else {
-               gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
-               gpio->par_feci2c &=
-                   ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
+               clrbits_8(&gpio->par_fec,
+                       GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
+               clrbits_8(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
        }
        return 0;
 }
index d6c8205..d1ea2ff 100644 (file)
@@ -1,6 +1,6 @@
 /*
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 /* CPU specific interrupt routine */
 #include <common.h>
 #include <asm/immap.h>
+#include <asm/io.h>
 
 int interrupt_init(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
        /* Make sure all interrupts are disabled */
-       intp->imrh0 |= 0xFFFFFFFF;
-       intp->imrl0 |= 0xFFFFFFFF;
+       setbits_be32(&intp->imrh0, 0xffffffff);
+       setbits_be32(&intp->imrl0, 0xffffffff);
 
        enable_interrupts();
        return 0;
@@ -41,9 +42,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-       volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+       int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-       intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-       intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
+       out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+       clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
 }
 #endif
index 5a29e25..cfdcc8b 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -29,6 +29,7 @@
 #include <asm/processor.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,13 +66,13 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Get the value of the current system clock */
 int get_sys_clock(void)
 {
-       volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
-       volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+       ccm_t *ccm = (ccm_t *)(MMAP_CCM);
+       pll_t *pll = (pll_t *)(MMAP_PLL);
        int divider;
 
        /* Test to see if device is in LIMP mode */
-       if (ccm->misccr & CCM_MISCCR_LIMP) {
-               divider = ccm->cdr & CCM_CDR_LPDIV(0xF);
+       if (in_be16(&ccm->misccr) & CCM_MISCCR_LIMP) {
+               divider = in_be16(&ccm->cdr) & CCM_CDR_LPDIV(0xF);
 #ifdef CONFIG_MCF5301x
                return (FREF / (3 * (1 << divider)));
 #endif
@@ -80,14 +81,14 @@ int get_sys_clock(void)
 #endif
        } else {
 #ifdef CONFIG_MCF5301x
-               u32 pfdr = (pll->pcr & 0x3F) + 1;
-               u32 refdiv = (1 << ((pll->pcr & PLL_PCR_REFDIV(7)) >> 8));
-               u32 busdiv = ((pll->pdr & 0x00F0) >> 4) + 1;
+               u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1;
+               u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8));
+               u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1;
 
                return (((FREF * pfdr) / refdiv) / busdiv);
 #endif
 #ifdef CONFIG_MCF532x
-               return ((FREF * pll->pfdr) / (BUSDIV * 4));
+               return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4);
 #endif
        }
 }
@@ -103,7 +104,7 @@ int get_sys_clock(void)
  */
 int clock_limp(int div)
 {
-       volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+       ccm_t *ccm = (ccm_t *)(MMAP_CCM);
        u32 temp;
 
        /* Check bounds of divider */
@@ -113,12 +114,12 @@ int clock_limp(int div)
                div = MAX_LPD;
 
        /* Save of the current value of the SSIDIV so we don't overwrite the value */
-       temp = (ccm->cdr & CCM_CDR_SSIDIV(0xFF));
+       temp = (in_be16(&ccm->cdr) & CCM_CDR_SSIDIV(0xFF));
 
        /* Apply the divider to the system clock */
-       ccm->cdr = (CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
+       out_be16(&ccm->cdr, CCM_CDR_LPDIV(div) | CCM_CDR_SSIDIV(temp));
 
-       ccm->misccr |= CCM_MISCCR_LIMP;
+       setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
        return (FREF / (3 * (1 << div)));
 }
@@ -126,14 +127,15 @@ int clock_limp(int div)
 /* Exit low power LIMP mode */
 int clock_exit_limp(void)
 {
-       volatile ccm_t *ccm = (volatile ccm_t *)(MMAP_CCM);
+       ccm_t *ccm = (ccm_t *)(MMAP_CCM);
        int fout;
 
        /* Exit LIMP mode */
-       ccm->misccr &= (~CCM_MISCCR_LIMP);
+       clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 
        /* Wait for PLL to lock */
-       while (!(ccm->misccr & CCM_MISCCR_PLL_LOCK)) ;
+       while (!(in_be16(&ccm->misccr) & CCM_MISCCR_PLL_LOCK))
+               ;
 
        fout = get_sys_clock();
 
@@ -153,10 +155,10 @@ int clock_exit_limp(void)
 int clock_pll(int fsys, int flags)
 {
 #ifdef CONFIG_MCF532x
-       volatile u32 *sdram_workaround = (volatile u32 *)(MMAP_SDRAM + 0x80);
+       u32 *sdram_workaround = (u32 *)(MMAP_SDRAM + 0x80);
 #endif
-       volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
-       volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+       sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
+       pll_t *pll = (pll_t *)(MMAP_PLL);
        int fref, temp, fout, mfd;
        u32 i;
 
@@ -165,13 +167,13 @@ int clock_pll(int fsys, int flags)
        if (fsys == 0) {
                /* Return current PLL output */
 #ifdef CONFIG_MCF5301x
-               u32 busdiv = ((pll->pdr >> 4) & 0x0F) + 1;
-               mfd = (pll->pcr & 0x3F) + 1;
+               u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1;
+               mfd = (in_be32(&pll->pcr) & 0x3F) + 1;
 
                return (fref * mfd) / busdiv;
 #endif
 #ifdef CONFIG_MCF532x
-               mfd = pll->pfdr;
+               mfd = in_8(&pll->pfdr);
 
                return (fref * mfd / (BUSDIV * 4));
 #endif
@@ -211,8 +213,8 @@ int clock_pll(int fsys, int flags)
         * If it has then the SDRAM needs to be put into self refresh
         * mode before reprogramming the PLL.
         */
-       if (sdram->ctrl & SDRAMC_SDCR_REF)
-               sdram->ctrl &= ~SDRAMC_SDCR_CKE;
+       if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+               clrbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
 
        /*
         * Initialize the PLL to generate the new system clock frequency.
@@ -223,35 +225,36 @@ int clock_pll(int fsys, int flags)
        clock_limp(DEFAULT_LPD);
 
 #ifdef CONFIG_MCF5301x
-       pll->pdr =
-           PLL_PDR_OUTDIV1((BUSDIV / 3) - 1)   |
-           PLL_PDR_OUTDIV2(BUSDIV - 1) |
-           PLL_PDR_OUTDIV3((BUSDIV / 2) - 1)   |
-           PLL_PDR_OUTDIV4(USBDIV - 1);
-
-       pll->pcr &= PLL_PCR_FBDIV_UNMASK;
-       pll->pcr |= PLL_PCR_FBDIV(mfd - 1);
+       out_be32(&pll->pdr,
+               PLL_PDR_OUTDIV1((BUSDIV / 3) - 1) |
+               PLL_PDR_OUTDIV2(BUSDIV - 1)     |
+               PLL_PDR_OUTDIV3((BUSDIV / 2) - 1) |
+               PLL_PDR_OUTDIV4(USBDIV - 1));
+
+       clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK);
+       setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1));
 #endif
 #ifdef CONFIG_MCF532x
        /* Reprogram PLL for desired fsys */
-       pll->podr = (PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
+       out_8(&pll->podr,
+               PLL_PODR_CPUDIV(BUSDIV / 3) | PLL_PODR_BUSDIV(BUSDIV));
 
-       pll->pfdr = mfd;
+       out_8(&pll->pfdr, mfd);
 #endif
 
        /* Exit LIMP mode */
        clock_exit_limp();
 
        /* Return the SDRAM to normal operation if it is in use. */
-       if (sdram->ctrl & SDRAMC_SDCR_REF)
-               sdram->ctrl |= SDRAMC_SDCR_CKE;
+       if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF)
+               setbits_be32(&sdram->ctrl, SDRAMC_SDCR_CKE);
 
 #ifdef CONFIG_MCF532x
        /*
         * software workaround for SDRAM opeartion after exiting LIMP
         * mode errata
         */
-       *sdram_workaround = CONFIG_SYS_SDRAM_BASE;
+       out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE);
 #endif
 
        /* wait for DQS logic to relock */
index 323a54e..adfc708 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
 #include <netdev.h>
 
 #include <asm/immap.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-       volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+       rcm_t *rcm = (rcm_t *) (MMAP_RCM);
        udelay(1000);
-       rcm->rcr |= RCM_RCR_SOFTRST;
+       setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
        /* we don't return! */
        return 0;
@@ -46,14 +47,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 int checkcpu(void)
 {
-       volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+       ccm_t *ccm = (ccm_t *) MMAP_CCM;
        u16 msk;
        u16 id = 0;
        u8 ver;
 
        puts("CPU:   ");
-       msk = (ccm->cir >> 6);
-       ver = (ccm->cir & 0x003f);
+       msk = (in_be16(&ccm->cir) >> 6);
+       ver = (in_be16(&ccm->cir) & 0x003f);
        switch (msk) {
        case 0x48:
                id = 54455;
index fdcd185..3f9209f 100644 (file)
@@ -3,7 +3,7 @@
  * (C) Copyright 2000-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,6 +30,7 @@
 #include <asm/immap.h>
 #include <asm/processor.h>
 #include <asm/rtc.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
  */
 void cpu_init_f(void)
 {
-       volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-       volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
-       scm1->mpr = 0x77777777;
-       scm1->pacra = 0;
-       scm1->pacrb = 0;
-       scm1->pacrc = 0;
-       scm1->pacrd = 0;
-       scm1->pacre = 0;
-       scm1->pacrf = 0;
-       scm1->pacrg = 0;
+       scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+       out_be32(&scm1->mpr, 0x77777777);
+       out_be32(&scm1->pacra, 0);
+       out_be32(&scm1->pacrb, 0);
+       out_be32(&scm1->pacrc, 0);
+       out_be32(&scm1->pacrd, 0);
+       out_be32(&scm1->pacre, 0);
+       out_be32(&scm1->pacrf, 0);
+       out_be32(&scm1->pacrg, 0);
 
        /* FlexBus */
-       gpio->par_be =
-           GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
-           GPIO_PAR_BE_BE0_BE0;
-       gpio->par_fbctl =
-           GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
-           GPIO_PAR_FBCTL_TS_TS;
+       out_8(&gpio->par_be,
+               GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+               GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+       out_8(&gpio->par_fbctl,
+               GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+               GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
 
 #if !defined(CONFIG_CF_SBF)
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-       fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-       fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-       fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
+       out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+       out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+       out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
        /* Latch chipselect */
-       fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-       fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-       fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
+       out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+       out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+       out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
-       fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-       fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-       fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
+       out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+       out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+       out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
-       fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-       fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-       fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
+       out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+       out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+       out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
-       fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-       fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-       fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
+       out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+       out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+       out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
-       fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-       fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-       fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
+       out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+       out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+       out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
        /*
@@ -115,7 +116,8 @@ void cpu_init_f(void)
                setvbr(CONFIG_SYS_CS0_BASE);
 
 #ifdef CONFIG_FSL_I2C
-       gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
+       out_be16(&gpio->par_feci2c,
+               GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
 #endif
 
        icache_enable();
@@ -127,11 +129,11 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFRTC
-       volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
-       volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
+       rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
+       rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 
-       rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
-       rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
+       out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
+       out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 #endif
 
        return (0);
@@ -139,40 +141,40 @@ int cpu_init_r(void)
 
 void uart_port_conf(int port)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
        /* Setup Ports: */
        switch (port) {
        case 0:
-               gpio->par_uart &=
-                   ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
-               gpio->par_uart |=
-                   (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+               clrbits_8(&gpio->par_uart,
+                       GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
+               setbits_8(&gpio->par_uart,
+                       GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
                break;
        case 1:
 #ifdef CONFIG_SYS_UART1_PRI_GPIO
-               gpio->par_uart &=
-                   ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-               gpio->par_uart |=
-                   (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+               clrbits_8(&gpio->par_uart,
+                       GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
+               setbits_8(&gpio->par_uart,
+                       GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
-               gpio->par_ssi &=
-                   (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
-               gpio->par_ssi |=
-                   (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
+               clrbits_be16(&gpio->par_ssi,
+                       ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
+               setbits_be16(&gpio->par_ssi,
+                       GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
 #endif
                break;
        case 2:
 #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
-               gpio->par_timer &=
-                   (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
-               gpio->par_timer |=
-                   (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
+               clrbits_8(&gpio->par_timer,
+                       ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
+               setbits_8(&gpio->par_timer,
+                       GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-               gpio->par_timer &=
-                   (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
-               gpio->par_timer |=
-                   (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
+               clrbits_8(&gpio->par_timer,
+                       ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
+               setbits_8(&gpio->par_timer,
+                       GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
 #endif
                break;
        }
@@ -181,43 +183,43 @@ void uart_port_conf(int port)
 #if defined(CONFIG_CMD_NET)
 int fecpin_setclear(struct eth_device *dev, int setclear)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
        struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
        if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-                       gpio->par_feci2c |=
-                           (GPIO_PAR_FECI2C_MDC0_MDC0 |
-                            GPIO_PAR_FECI2C_MDIO0_MDIO0);
+                       setbits_be16(&gpio->par_feci2c,
+                               GPIO_PAR_FECI2C_MDC0_MDC0 |
+                               GPIO_PAR_FECI2C_MDIO0_MDIO0);
                else
-                       gpio->par_feci2c |=
-                           (GPIO_PAR_FECI2C_MDC1_MDC1 |
-                            GPIO_PAR_FECI2C_MDIO1_MDIO1);
+                       setbits_be16(&gpio->par_feci2c,
+                               GPIO_PAR_FECI2C_MDC1_MDC1 |
+                               GPIO_PAR_FECI2C_MDIO1_MDIO1);
 #else
-               gpio->par_feci2c |=
-                   (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+               setbits_be16(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 #endif
 
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
-                       gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
+                       setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
                else
-                       gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
+                       setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
        } else {
-               gpio->par_feci2c &=
-                   ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
+               clrbits_be16(&gpio->par_feci2c,
+                       GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
                if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 #ifdef CONFIG_SYS_FEC_FULL_MII
-                       gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII;
+                       setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
 #else
-                       gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
+                       clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
 #endif
                } else {
 #ifdef CONFIG_SYS_FEC_FULL_MII
-                       gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII;
+                       setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
 #else
-                       gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
+                       clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
 #endif
                }
        }
@@ -228,43 +230,45 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 #ifdef CONFIG_CF_DSPI
 void cfspi_port_conf(void)
 {
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-       gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
-           GPIO_PAR_DSPI_SCK_SCK;
+       out_8(&gpio->par_dspi,
+               GPIO_PAR_DSPI_SIN_SIN |
+               GPIO_PAR_DSPI_SOUT_SOUT |
+               GPIO_PAR_DSPI_SCK_SCK);
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
 {
-       volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
-       volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+       dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+       gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-       if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
+       if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
                return -1;
 
        /* Clear FIFO and resume transfer */
-       dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+       clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);