Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 885fb2d20e5a516432ed07a8ecce327dded9edb0..b935a29a3ca18aeec87287c4329925037562f348 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -149,3 +149,43 @@ int arch_misc_init(void)
 #endif
        return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+void rtc32k_enable(void)
+{
+       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+       /*
+        * Unlock the RTC's registers.  For more details please see the
+        * RTC_SS section of the TRM.  In order to unlock we need to
+        * write these specific values (keys) in this order.
+        */
+       writel(0x83e70b13, &rtc->kick0r);
+       writel(0x95a4f1e0, &rtc->kick1r);
+
+       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
+       writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+#define UART_RESET             (0x1 << 1)
+#define UART_CLK_RUNNING_MASK  0x1
+#define UART_SMART_IDLE_EN     (0x1 << 0x3)
+
+void uart_soft_reset(void)
+{
+       struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+       u32 regval;
+
+       regval = readl(&uart_base->uartsyscfg);
+       regval |= UART_RESET;
+       writel(regval, &uart_base->uartsyscfg);
+       while ((readl(&uart_base->uartsyssts) &
+               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+               ;
+
+       /* Disable smart idle */
+       regval = readl(&uart_base->uartsyscfg);
+       regval |= UART_SMART_IDLE_EN;
+       writel(regval, &uart_base->uartsyscfg);
+}
+#endif

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index a1efc7520a7c149dc93b388ca84bf8fc23ac4ed7..9c4d0b439316c9353774ecb11d0a69d418a389dd 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -246,7 +246,7 @@ static void enable_per_clocks(void)
                ;
 }
 
-static void mpu_pll_config(void)
+void mpu_pll_config_val(int mpull_m)
 {
        u32 clkmode, clksel, div_m2;
 
@@ -260,7 +260,7 @@ static void mpu_pll_config(void)
                ;
 
        clksel = clksel & (~CLK_SEL_MASK);
-       clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+       clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
        writel(clksel, &cmwkup->clkseldpllmpu);
 
        div_m2 = div_m2 & ~CLK_DIV_MASK;
@@ -274,6 +274,11 @@ static void mpu_pll_config(void)
                ;
 }
 
+static void mpu_pll_config(void)
+{
+       mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+}
+
 static void core_pll_config(void)
 {
        u32 clkmode, clksel, div_m4, div_m5, div_m6;

diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index fedc674031d2d3321cabc02754d456106cc1bb91..307ac28245a41419807190857078e056e8ec5ecd 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -32,6 +32,7 @@ extern struct ctrl_stat *cstat;
 u32 get_device_type(void);
 void save_omap_boot_params(void);
 void setup_clocks_for_console(void);
+void mpu_pll_config_val(int mpull_m);
 void ddr_pll_config(unsigned int ddrpll_M);
 
 void sdelay(unsigned long);
@@ -41,4 +42,7 @@ void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
                        u32 size);
 void omap_nand_switch_ecc(uint32_t, uint32_t);
+
+void rtc32k_enable(void);
+void uart_soft_reset(void);
 #endif

diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 826ceadd81d1139a1354b9613bbff8c1acac2e71..ea3bea50f503b48a68a1f0f84e7dcbd03db7268b 100644 (file)
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -36,37 +36,13 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define RMII_MODE_ENABLE       0x4D
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
        .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
@@ -131,23 +107,9 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regval;
-
        enable_uart0_pin_mux();
 
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_RESET;
-       writel(regval, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) &
-               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_SMART_IDLE_EN;
-       writel(regval, &uart_base->uartsyscfg);
-
+       uart_soft_reset();
        gd = &gdata;
 
        preloader_console_init();

diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 93c611dfc6e65c5a4e68047cc2b3dd60df4d808e..0cca8d75b59c2cc0279865b6ae159cc4c3f8def3 100644 (file)
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -39,9 +39,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE                0x0
@@ -50,31 +47,11 @@ static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
-/* UART defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
 /* DDR RAM defines */
 #define DDR_CLK_MHZ            303 /* DDR_DPLL_MULT value */
 
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr3_data = {
        .datardsratio0 = MT41J256M8HX15E_RD_DQS,
        .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
@@ -141,22 +118,8 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regval;
-
        enable_uart0_pin_mux();
-
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_RESET;
-       writel(regval, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
-               != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regval = readl(&uart_base->uartsyscfg);
-       regval |= UART_SMART_IDLE_EN;
-       writel(regval, &uart_base->uartsyscfg);
+       uart_soft_reset();
 
        gd = &gdata;
 

diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 06e8f07c4eeea150fda69da69770ec944e14cb7c..fb98df0f847e5235cb05bd23df52857f3a724323 100644 (file)
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -38,9 +38,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-#ifdef CONFIG_SPL_BUILD
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-#endif
 
 /* MII mode defines */
 #define MII_MODE_ENABLE                0x0
@@ -126,28 +123,7 @@ static int read_eeprom(void)
        return 0;
 }
 
-/* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static const struct ddr_data ddr2_data = {
        .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
                          (MT47H128M16RT25E_RD_DQS<<20) |
@@ -330,9 +306,6 @@ void s_init(void)
        /* Enable RTC32K clock */
        rtc32k_enable();
 
-       /* UART softreset */
-       u32 regVal;
-
 #ifdef CONFIG_SERIAL1
        enable_uart0_pin_mux();
 #endif /* CONFIG_SERIAL1 */
@@ -352,17 +325,7 @@ void s_init(void)
        enable_uart5_pin_mux();
 #endif /* CONFIG_SERIAL6 */
 
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_RESET;
-       writel(regVal, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) &
-               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_SMART_IDLE_EN;
-       writel(regVal, &uart_base->uartsyscfg);
+       uart_soft_reset();
 
        gd = &gdata;
 

diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 90ae29e7c64bc761b0a5b0a2993cf44ecf6db882..1da5b359c020d660d99816790e9b74922abcdd6e 100644 (file)
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -37,6 +37,11 @@
 #endif
 
 #define PANDA_ULPI_PHY_TYPE_GPIO       182
+#define PANDA_BOARD_ID_1_GPIO          101
+#define PANDA_ES_BOARD_ID_1_GPIO        48
+#define PANDA_BOARD_ID_2_GPIO          171
+#define PANDA_ES_BOARD_ID_3_GPIO         3
+#define PANDA_ES_BOARD_ID_4_GPIO         2
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -66,6 +71,73 @@ int board_eth_init(bd_t *bis)
        return 0;
 }
 
+/*
+* Routine: get_board_revision
+* Description: Detect if we are running on a panda revision A1-A6,
+*              or an ES panda board. This can be done by reading
+*              the level of GPIOs and checking the processor revisions.
+*              This should result in:
+*                      Panda 4430:
+*              GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
+*              GPIO171, GPIO101, GPIO182: 1 0 1 => A6
+*                      Panda ES:
+*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
+*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
+*/
+int get_board_revision(void)
+{
+       int board_id0, board_id1, board_id2;
+       int board_id3, board_id4;
+       int board_id;
+
+       int processor_rev = omap_revision();
+
+       /* Setup the mux for the common board ID pins (gpio 171 and 182) */
+       writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+       writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
+
+       board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
+       board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+
+       if ((processor_rev >= OMAP4460_ES1_0 &&
+            processor_rev <= OMAP4460_ES1_1)) {
+               /*
+                * Setup the mux for the ES specific board ID pins (gpio 101,
+                * 2 and 3.
+                */
+               writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+                               GPMC_A24);
+               writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+                               UNIPRO_RY0);
+               writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+                               UNIPRO_RX1);
+
+               board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
+               board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
+               board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+               setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
+#endif
+               board_id = ((board_id4 << 4) | (board_id3 << 3) |
+                       (board_id2 << 2) | (board_id1 << 1) | (board_id0));
+       } else {
+               /* Setup the mux for the Ax specific board ID pins (gpio 101) */
+               writew((IEN | M3), (*ctrl)->control_padconf_core_base +
+                               FREF_CLK2_OUT);
+
+               board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
+               board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+               if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
+                       setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
+#endif
+       }
+
+       return board_id;
+}
+
 /**
  * @brief misc_init_r - Configure Panda board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
@@ -82,11 +154,7 @@ int misc_init_r(void)
        if (omap_revision() == OMAP4430_ES1_0)
                return 0;
 
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-       if (omap_revision() >= OMAP4460_ES1_0 ||
-               omap_revision() <= OMAP4460_ES1_1)
-               setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
-#endif
+       get_board_revision();
 
        gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
        phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
@@ -106,7 +174,7 @@ int misc_init_r(void)
                auxclk |= AUXCLK_ENABLE_MASK;
 
                writel(auxclk, &scrm->auxclk3);
-       } else {
+       } else {
                /* ULPI PHY supplied by auxclk1 derived from PER dpll */
                debug("ULPI PHY supplied by auxclk1\n");
 
@@ -151,9 +219,9 @@ void set_muxconf_regs_essential(void)
 
        if (omap_revision() >= OMAP4460_ES1_0)
                do_set_mux((*ctrl)->control_padconf_wkup_base,
-                                wkup_padconf_array_essential_4460,
-                                sizeof(wkup_padconf_array_essential_4460) /
-                                sizeof(struct pad_conf_entry));
+                          wkup_padconf_array_essential_4460,
+                          sizeof(wkup_padconf_array_essential_4460) /
+                          sizeof(struct pad_conf_entry));
 }
 
 void set_muxconf_regs_non_essential(void)
@@ -165,14 +233,14 @@ void set_muxconf_regs_non_essential(void)
 
        if (omap_revision() < OMAP4460_ES1_0)
                do_set_mux((*ctrl)->control_padconf_core_base,
-                               core_padconf_array_non_essential_4430,
-                               sizeof(core_padconf_array_non_essential_4430) /
-                               sizeof(struct pad_conf_entry));
+                          core_padconf_array_non_essential_4430,
+                          sizeof(core_padconf_array_non_essential_4430) /
+                          sizeof(struct pad_conf_entry));
        else
                do_set_mux((*ctrl)->control_padconf_core_base,
-                               core_padconf_array_non_essential_4460,
-                               sizeof(core_padconf_array_non_essential_4460) /
-                               sizeof(struct pad_conf_entry));
+                          core_padconf_array_non_essential_4460,
+                          sizeof(core_padconf_array_non_essential_4460) /
+                          sizeof(struct pad_conf_entry));
 
        do_set_mux((*ctrl)->control_padconf_wkup_base,
                   wkup_padconf_array_non_essential,
@@ -181,9 +249,9 @@ void set_muxconf_regs_non_essential(void)
 
        if (omap_revision() < OMAP4460_ES1_0)
                do_set_mux((*ctrl)->control_padconf_wkup_base,
-                               wkup_padconf_array_non_essential_4430,
-                               sizeof(wkup_padconf_array_non_essential_4430) /
-                               sizeof(struct pad_conf_entry));
+                          wkup_padconf_array_non_essential_4430,
+                          sizeof(wkup_padconf_array_non_essential_4430) /
+                          sizeof(struct pad_conf_entry));
 }
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)

diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index 4759b167a46ab2f51d55c0b92fa41e599627c2bd..6ad3dd8fc74adf6e910abd68ca476ec4af4b4409 100644 (file)
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -37,49 +37,16 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #endif
 
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 /* UART Defines */
 #ifdef CONFIG_SPL_BUILD
-#define UART_RESET             (0x1 << 1)
-#define UART_CLK_RUNNING_MASK  0x1
-#define UART_SMART_IDLE_EN     (0x1 << 0x3)
-
-static void rtc32k_enable(void)
-{
-       struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
-
-       /*
-        * Unlock the RTC's registers.  For more details please see the
-        * RTC_SS section of the TRM.  In order to unlock we need to
-        * write these specific values (keys) in this order.
-        */
-       writel(0x83e70b13, &rtc->kick0r);
-       writel(0x95a4f1e0, &rtc->kick1r);
-
-       /* Enable the RTC 32K OSC by setting bits 3 and 6. */
-       writel((1 << 3) | (1 << 6), &rtc->osc);
-}
-
 static void uart_enable(void)
 {
-       u32 regVal;
-
        /* UART softreset */
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_RESET;
-       writel(regVal, &uart_base->uartsyscfg);
-       while ((readl(&uart_base->uartsyssts) &
-               UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-               ;
-
-       /* Disable smart idle */
-       regVal = readl(&uart_base->uartsyscfg);
-       regVal |= UART_SMART_IDLE_EN;
-       writel(regVal, &uart_base->uartsyscfg);
+       uart_soft_reset();
 }
 
 static void wdt_disable(void)

diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index b286ffc8d4fb2a729581964d184a1c4614747f5b..7cc3ef24acc30717e2252cb442dd5bd3e755ccb1 100644 (file)
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -60,7 +60,7 @@
        "rdaddr=0x81000000\0" \
        "bootdir=/boot\0" \
        "bootfile=uImage\0" \
-       "fdtfile=\0" \
+       "fdtfile=undefined\0" \
        "console=ttyO0,115200n8\0" \
        "optargs=\0" \
        "mtdids=" MTDIDS_DEFAULT "\0" \
@@ -145,8 +145,9 @@
                "if test $board_name = A33515BB; then " \
                        "setenv fdtfile am335x-evm.dtb; fi; " \
                "if test $board_name = A335X_SK; then " \
-                       "setenv fdtfile am335x-evmsk.dtb; fi\0" \
-
+                       "setenv fdtfile am335x-evmsk.dtb; fi " \
+               "if test $fdtfile = undefined; then " \
+                       "echo WARNING: Could not determine device tree to use; fi; \0"
 #endif
 
 #define CONFIG_BOOTCOMMAND \

diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 0eea28c80a6dd9b8bf08bc487ab93e647a74fd42..c11f005535d03916edc1b646dd3f8452273acfaf 100644 (file)
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -41,4 +41,7 @@
 #define CONFIG_BAUDRATE                        115200
 
 #define CONFIG_SYS_OMAP_ABE_SYSCK
+
+#define CONSOLEDEV             "ttyO0"
+
 #endif /* __CONFIG_DRA7XX_EVM_H */

diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h
index 3e5d36b21e0d552b031df9dd8ad1906d6036eeba..2fa4382c3ef54a3f39102a26eb717afcabd1bfe3 100644 (file)
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -150,6 +150,7 @@
        "console=ttyO2,115200n8\0" \
        "fdt_high=0xffffffff\0" \
        "fdtaddr=0x80f80000\0" \
+       "fdtfile=undefined\0" \
        "bootpart=0:2\0" \
        "bootdir=/boot\0" \
        "bootfile=zImage\0" \
@@ -177,8 +178,12 @@
                        "setenv fdtfile omap4-sdp.dtb; fi; " \
                "if test $board_name = panda; then " \
                        "setenv fdtfile omap4-panda.dtb; fi;" \
+               "if test $board_name = panda-a4; then " \
+                       "setenv fdtfile omap4-panda-a4.dtb; fi;" \
                "if test $board_name = panda-es; then " \
-                       "setenv fdtfile omap4-panda-es.dtb; fi; \0" \
+                       "setenv fdtfile omap4-panda-es.dtb; fi;" \
+               "if test $fdtfile = undefined; then " \
+                       "echo WARNING: Could not determine device tree to use; fi; \0" \
        "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
 
 #define CONFIG_BOOTCOMMAND \

diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h
index ddf2ad4fc2918307fe6489ef8788a36c057abc1d..b87ee422869246e3cabe68eba8d6011f5566104a 100644 (file)
--- a/include/configs/omap5_common.h
+++ b/include/configs/omap5_common.h
@@ -136,9 +136,10 @@
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "loadaddr=0x82000000\0" \
-       "console=ttyO2,115200n8\0" \
+       "console=" CONSOLEDEV ",115200n8\0" \
        "fdt_high=0xffffffff\0" \
        "fdtaddr=0x80f80000\0" \
+       "fdtfile=undefined\0" \
        "bootpart=0:2\0" \
        "bootdir=/boot\0" \
        "bootfile=zImage\0" \
@@ -166,7 +167,11 @@
                "bootz ${loadaddr} - ${fdtaddr}\0" \
        "findfdt="\
                "if test $board_name = omap5_uevm; then " \
-                       "setenv fdtfile omap5-uevm.dtb; fi;\0 " \
+                       "setenv fdtfile omap5-uevm.dtb; fi; " \
+               "if test $board_name = dra7xx; then " \
+                       "setenv fdtfile dra7-evm.dtb; fi;" \
+               "if test $fdtfile = undefined; then " \
+                       "echo WARNING: Could not determine device tree to use; fi; \0" \
        "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \
 
 #define CONFIG_BOOTCOMMAND \

diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index dea05bc911cf6970ebd8197921e72625dbed0f37..46dacc207442c03d843794d4f5c6c8cf8af3b18e 100644 (file)
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -53,7 +53,9 @@
 #define CONFIG_PARTITION_UUIDS
 #define CONFIG_CMD_PART
 
-#define CONFIG_SYS_PROMPT              "OMAP5430 EVM # "
+#define CONFIG_SYS_PROMPT              "OMAP5432 uEVM # "
+
+#define CONSOLEDEV             "ttyO2"
 
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC       16296
 #endif /* __CONFIG_OMAP5_EVM_H */