Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 23 May 2014 20:50:23 +0000 (22:50 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 23 May 2014 20:50:23 +0000 (22:50 +0200)
25 files changed:
Makefile
arch/arm/cpu/armv7/zynq/cpu.c
arch/arm/cpu/armv7/zynq/ddrc.c
arch/arm/cpu/armv7/zynq/slcr.c
arch/arm/cpu/armv7/zynq/spl.c
arch/arm/dts/zynq-7000.dtsi
arch/arm/dts/zynq-microzed.dts
arch/arm/dts/zynq-zc702.dts
arch/arm/dts/zynq-zc706.dts
arch/arm/dts/zynq-zc770-xm010.dts
arch/arm/dts/zynq-zc770-xm012.dts
arch/arm/dts/zynq-zc770-xm013.dts
arch/arm/dts/zynq-zed.dts
arch/arm/include/asm/arch-zynq/hardware.h
arch/arm/include/asm/arch-zynq/sys_proto.h
board/xilinx/zynq/.gitignore [new file with mode: 0644]
board/xilinx/zynq/Makefile
board/xilinx/zynq/board.c
board/xilinx/zynq/ps7_init.c [deleted file]
board/xilinx/zynq/xil_io.h [new file with mode: 0644]
drivers/usb/host/Makefile
drivers/usb/host/ehci-zynq.c [new file with mode: 0644]
include/configs/zynq-common.h
include/configs/zynq_zc70x.h
include/configs/zynq_zed.h

index 176ce10..1f56e85 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -752,6 +752,9 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
+ifeq ($(CONFIG_SPL_FRAMEWORK),y)
+ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
+endif
 ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
 ifneq ($(CONFIG_SPL_TARGET),)
 ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
@@ -854,6 +857,11 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
        $(call if_changed,mkimage)
 
+MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
+
+u-boot-dtb.img: u-boot-dtb.bin FORCE
+       $(call if_changed,mkimage)
+
 u-boot.sha1:   u-boot.bin
                tools/ubsha1 u-boot.bin
 
index 7626b5c..816d0c5 100644 (file)
@@ -14,6 +14,9 @@ void lowlevel_init(void)
 {
 }
 
+#define ZYNQ_SILICON_VER_MASK  0xF0000000
+#define ZYNQ_SILICON_VER_SHIFT 28
+
 int arch_cpu_init(void)
 {
        zynq_slcr_unlock();
@@ -42,6 +45,16 @@ int arch_cpu_init(void)
        return 0;
 }
 
+unsigned int zynq_get_silicon_version(void)
+{
+       unsigned int ver;
+
+       ver = (readl(&devcfg_base->mctrl) &
+              ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
+
+       return ver;
+}
+
 void reset_cpu(ulong addr)
 {
        zynq_slcr_cpu_reset();
index ba6a6ae..e0ed3bf 100644 (file)
@@ -40,11 +40,8 @@ void zynq_ddrc_init(void)
                 * first stage bootloader. To get ECC to work all memory has
                 * been initialized by writing any value.
                 */
-               memset(0, 0, 1 * 1024 * 1024);
+               memset((void *)0, 0, 1 * 1024 * 1024);
        } else {
                puts("Memory: ECC disabled\n");
        }
-
-       if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
-               gd->ram_size /= 2;
 }
index d7c1882..934ccc3 100644 (file)
@@ -8,26 +8,75 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/arch/clk.h>
 
 #define SLCR_LOCK_MAGIC                0x767B
 #define SLCR_UNLOCK_MAGIC      0xDF0D
 
+#define SLCR_USB_L1_SEL                        0x04
+
 #define SLCR_IDCODE_MASK       0x1F000
 #define SLCR_IDCODE_SHIFT      12
 
+/*
+ * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
+ *
+ * @peri_name: Name of the peripheral for checking MIO status
+ * @get_pins: Pointer to array of get pin for this peripheral
+ * @num_pins: Number of pins for this peripheral
+ * @mask: Mask value
+ * @check_val: Required check value to get the status of  periph
+ */
+struct zynq_slcr_mio_get_status {
+       const char *peri_name;
+       const int *get_pins;
+       int num_pins;
+       u32 mask;
+       u32 check_val;
+};
+
+static const int usb0_pins[] = {
+       28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
+};
+
+static const int usb1_pins[] = {
+       40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+
+static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+       {
+               "usb0",
+               usb0_pins,
+               ARRAY_SIZE(usb0_pins),
+               SLCR_USB_L1_SEL,
+               SLCR_USB_L1_SEL,
+       },
+       {
+               "usb1",
+               usb1_pins,
+               ARRAY_SIZE(usb1_pins),
+               SLCR_USB_L1_SEL,
+               SLCR_USB_L1_SEL,
+       },
+};
+
 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
 
 void zynq_slcr_lock(void)
 {
-       if (!slcr_lock)
+       if (!slcr_lock) {
                writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+               slcr_lock = 1;
+       }
 }
 
 void zynq_slcr_unlock(void)
 {
-       if (slcr_lock)
+       if (slcr_lock) {
                writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+               slcr_lock = 0;
+       }
 }
 
 /* Reset the entire system */
@@ -82,7 +131,7 @@ void zynq_slcr_devcfg_disable(void)
 {
        zynq_slcr_unlock();
 
-       /* Disable AXI interface */
+       /* Disable AXI interface by asserting FPGA resets */
        writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
 
        /* Set Level Shifters DT618760 */
@@ -98,7 +147,7 @@ void zynq_slcr_devcfg_enable(void)
        /* Set Level Shifters DT618760 */
        writel(0xF, &slcr_base->lvl_shftr_en);
 
-       /* Disable AXI interface */
+       /* Enable AXI interface by de-asserting FPGA resets */
        writel(0x0, &slcr_base->fpga_rst_ctrl);
 
        zynq_slcr_lock();
@@ -115,3 +164,33 @@ u32 zynq_slcr_get_idcode(void)
        return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
                                                        SLCR_IDCODE_SHIFT;
 }
+
+/*
+ * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
+ *
+ * @periph: Name of the peripheral
+ *
+ * Returns count to indicate the number of pins configured for the
+ * given @periph.
+ */
+int zynq_slcr_get_mio_pin_status(const char *periph)
+{
+       const struct zynq_slcr_mio_get_status *mio_ptr;
+       int val, i, j;
+       int mio = 0;
+
+       for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
+               if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
+                       mio_ptr = &mio_periphs[i];
+                       for (j = 0; j < mio_ptr->num_pins; j++) {
+                               val = readl(&slcr_base->mio_pin
+                                               [mio_ptr->get_pins[j]]);
+                               if ((val & mio_ptr->mask) == mio_ptr->check_val)
+                                       mio++;
+                       }
+                       break;
+               }
+       }
+
+       return mio;
+}
index fcad762..d73e5cb 100644 (file)
@@ -28,6 +28,13 @@ void board_init_f(ulong dummy)
        board_init_r(NULL, 0);
 }
 
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+       board_init();
+}
+#endif
+
 u32 spl_boot_device(void)
 {
        u32 mode;
@@ -67,3 +74,11 @@ int spl_start_uboot(void)
        return 0;
 }
 #endif
+
+__weak void ps7_init(void)
+{
+       /*
+        * This function is overridden by the one in
+        * board/xilinx/zynq/ps7_init.c, if it exists.
+        */
+}
index f20b8bd..2d076f1 100644 (file)
 
 / {
        compatible = "xlnx,zynq-7000";
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <0>;
+                       clocks = <&clkc 3>;
+                       clock-latency = <1000>;
+                       operating-points = <
+                               /* kHz    uV */
+                               666667  1000000
+                               333334  1000000
+                               222223  1000000
+                       >;
+               };
+
+               cpu@1 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <1>;
+                       clocks = <&clkc 3>;
+               };
+       };
+
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts = <0 5 4>, <0 6 4>;
+               interrupt-parent = <&intc>;
+               reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+       };
+
+       amba {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               interrupt-parent = <&intc>;
+               ranges;
+
+               i2c0: zynq-i2c@e0004000 {
+                       compatible = "cdns,i2c-r1p10";
+                       status = "disabled";
+                       clocks = <&clkc 38>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 25 4>;
+                       reg = <0xe0004000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               i2c1: zynq-i2c@e0005000 {
+                       compatible = "cdns,i2c-r1p10";
+                       status = "disabled";
+                       clocks = <&clkc 39>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 48 4>;
+                       reg = <0xe0005000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               intc: interrupt-controller@f8f01000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       #address-cells = <1>;
+                       interrupt-controller;
+                       reg = <0xF8F01000 0x1000>,
+                             <0xF8F00100 0x100>;
+               };
+
+               L2: cache-controller {
+                       compatible = "arm,pl310-cache";
+                       reg = <0xF8F02000 0x1000>;
+                       arm,data-latency = <3 2 2>;
+                       arm,tag-latency = <2 2 2>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+
+               uart0: uart@e0000000 {
+                       compatible = "xlnx,xuartps";
+                       status = "disabled";
+                       clocks = <&clkc 23>, <&clkc 40>;
+                       clock-names = "ref_clk", "aper_clk";
+                       reg = <0xE0000000 0x1000>;
+                       interrupts = <0 27 4>;
+               };
+
+               uart1: uart@e0001000 {
+                       compatible = "xlnx,xuartps";
+                       status = "disabled";
+                       clocks = <&clkc 24>, <&clkc 41>;
+                       clock-names = "ref_clk", "aper_clk";
+                       reg = <0xE0001000 0x1000>;
+                       interrupts = <0 50 4>;
+               };
+
+               gem0: ethernet@e000b000 {
+                       compatible = "cdns,gem";
+                       reg = <0xe000b000 0x4000>;
+                       status = "disabled";
+                       interrupts = <0 22 4>;
+                       clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
+                       clock-names = "pclk", "hclk", "tx_clk";
+               };
+
+               gem1: ethernet@e000c000 {
+                       compatible = "cdns,gem";
+                       reg = <0xe000c000 0x4000>;
+                       status = "disabled";
+                       interrupts = <0 45 4>;
+                       clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
+                       clock-names = "pclk", "hclk", "tx_clk";
+               };
+
+               sdhci0: ps7-sdhci@e0100000 {
+                       compatible = "arasan,sdhci-8.9a";
+                       status = "disabled";
+                       clock-names = "clk_xin", "clk_ahb";
+                       clocks = <&clkc 21>, <&clkc 32>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 24 4>;
+                       reg = <0xe0100000 0x1000>;
+               } ;
+
+               sdhci1: ps7-sdhci@e0101000 {
+                       compatible = "arasan,sdhci-8.9a";
+                       status = "disabled";
+                       clock-names = "clk_xin", "clk_ahb";
+                       clocks = <&clkc 22>, <&clkc 33>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 47 4>;
+                       reg = <0xe0101000 0x1000>;
+               } ;
+
+               slcr: slcr@f8000000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "xlnx,zynq-slcr", "syscon";
+                       reg = <0xF8000000 0x1000>;
+                       ranges;
+                       clkc: clkc@100 {
+                               #clock-cells = <1>;
+                               compatible = "xlnx,ps7-clkc";
+                               ps-clk-frequency = <33333333>;
+                               fclk-enable = <0>;
+                               clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                               "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                               "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                               "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                               "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                               "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                               "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                               "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                               "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                               "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                               "dbg_trc", "dbg_apb";
+                               reg = <0x100 0x100>;
+                       };
+               };
+
+               global_timer: timer@f8f00200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0xf8f00200 0x20>;
+                       interrupts = <1 11 0x301>;
+                       interrupt-parent = <&intc>;
+                       clocks = <&clkc 4>;
+               };
+
+               ttc0: ttc0@f8001000 {
+                       interrupt-parent = <&intc>;
+                       interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                       compatible = "cdns,ttc";
+                       clocks = <&clkc 6>;
+                       reg = <0xF8001000 0x1000>;
+               };
+
+               ttc1: ttc1@f8002000 {
+                       interrupt-parent = <&intc>;
+                       interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                       compatible = "cdns,ttc";
+                       clocks = <&clkc 6>;
+                       reg = <0xF8002000 0x1000>;
+               };
+               scutimer: scutimer@f8f00600 {
+                       interrupt-parent = <&intc>;
+                       interrupts = < 1 13 0x301 >;
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = < 0xf8f00600 0x20 >;
+                       clocks = <&clkc 4>;
+               } ;
+       };
 };
index 6da71c1..c373a2c 100644 (file)
 / {
        model = "Zynq MicroZED Board";
        compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 667dc28..4fa0b00 100644 (file)
 / {
        model = "Zynq ZC702 Board";
        compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 526fc88..2a80195 100644 (file)
 / {
        model = "Zynq ZC706 Board";
        compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 8b542a1..5e66174 100644 (file)
 / {
        model = "Zynq ZC770 XM010 Board";
        compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 0379a07..127a661 100644 (file)
 / {
        model = "Zynq ZC770 XM012 Board";
        compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index a4f9e05..c61c7e7 100644 (file)
 / {
        model = "Zynq ZC770 XM013 Board";
        compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 91a5deb..70cc8a6 100644 (file)
 / {
        model = "Zynq ZED Board";
        compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x20000000>;
+       };
 };
index 39184da..2aede0c 100644 (file)
 #define ZYNQ_SPI_BASEADDR0             0xE0006000
 #define ZYNQ_SPI_BASEADDR1             0xE0007000
 #define ZYNQ_DDRC_BASEADDR             0xF8006000
+#define ZYNQ_EFUSE_BASEADDR            0xF800D000
+#define ZYNQ_USB_BASEADDR0             0xE0002000
+#define ZYNQ_USB_BASEADDR1             0xE0003000
 
 /* Bootmode setting values */
-#define ZYNQ_BM_MASK           0xF
+#define ZYNQ_BM_MASK           0x7
 #define ZYNQ_BM_NOR            0x2
 #define ZYNQ_BM_SD             0x5
 #define ZYNQ_BM_JTAG           0x0
@@ -130,4 +133,12 @@ struct ddrc_regs {
 };
 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
 
+struct efuse_reg {
+       u32 reserved1[4];
+       u32 status;
+       u32 reserved2[3];
+};
+
+#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
+
 #endif /* _ASM_ARCH_HARDWARE_H */
index a68e1b3..53c30ec 100644 (file)
@@ -15,7 +15,9 @@ extern void zynq_slcr_devcfg_disable(void);
 extern void zynq_slcr_devcfg_enable(void);
 extern u32 zynq_slcr_get_boot_mode(void);
 extern u32 zynq_slcr_get_idcode(void);
+extern int zynq_slcr_get_mio_pin_status(const char *periph);
 extern void zynq_ddrc_init(void);
+extern unsigned int zynq_get_silicon_version(void);
 
 /* Driver extern functions */
 extern int zynq_sdhci_init(u32 regbase);
diff --git a/board/xilinx/zynq/.gitignore b/board/xilinx/zynq/.gitignore
new file mode 100644 (file)
index 0000000..68b8edd
--- /dev/null
@@ -0,0 +1 @@
+ps7_init.[ch]
index 3f19a1c..fd93f63 100644 (file)
@@ -6,4 +6,7 @@
 #
 
 obj-y  := board.o
-obj-$(CONFIG_SPL_BUILD)        += ps7_init.o
+
+# Please copy ps7_init.c/h from hw project to this directory
+obj-$(CONFIG_SPL_BUILD) += \
+               $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
index c8cc2bc..258632e 100644 (file)
@@ -6,6 +6,8 @@
 
 #include <common.h>
 #include <fdtdec.h>
+#include <fpga.h>
+#include <mmc.h>
 #include <netdev.h>
 #include <zynqpl.h>
 #include <asm/arch/hardware.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_FPGA
-xilinx_desc fpga;
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static xilinx_desc fpga;
 
 /* It can be done differently */
-xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
-xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
-xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
-xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
-xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
-xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
+static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
+static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
+static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
+static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
 int board_init(void)
 {
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
        u32 idcode;
 
        idcode = zynq_slcr_get_idcode();
@@ -54,7 +58,8 @@ int board_init(void)
        }
 #endif
 
-#ifdef CONFIG_FPGA
+#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
+    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
        fpga_init();
        fpga_add(fpga_xilinx, &fpga);
 #endif
diff --git a/board/xilinx/zynq/ps7_init.c b/board/xilinx/zynq/ps7_init.c
deleted file mode 100644 (file)
index c47da09..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * (C) Copyright 2014 Xilinx, Inc. Michal Simek
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-#include <common.h>
-#include <asm/arch/spl.h>
-
-__weak void ps7_init(void)
-{
-       puts("Please copy ps7_init.c/h from hw project\n");
-}
diff --git a/board/xilinx/zynq/xil_io.h b/board/xilinx/zynq/xil_io.h
new file mode 100644 (file)
index 0000000..e59a977
--- /dev/null
@@ -0,0 +1,13 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H
+
+/*
+ * This empty file is here because ps7_init.c exported by hw project
+ * has #include "xil_io.h" line.
+ */
+
+#endif /* XIL_IO_H */
index b301e28..7211c6a 100644 (file)
@@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
+obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
 obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c
new file mode 100644 (file)
index 0000000..7770d05
--- /dev/null
@@ -0,0 +1,104 @@
+/*
+ * (C) Copyright 2014, Xilinx, Inc
+ *
+ * USB Low level initialization(Specific to zynq)
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <usb.h>
+#include <usb/ehci-fsl.h>
+#include <usb/ulpi.h>
+
+#include "ehci.h"
+
+#define ZYNQ_USB_USBCMD_RST                    0x0000002
+#define ZYNQ_USB_USBCMD_STOP                   0x0000000
+#define ZYNQ_USB_NUM_MIO                       12
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index,  enum usb_init_type init, struct ehci_hccr **hccr,
+                 struct ehci_hcor **hcor)
+{
+       struct usb_ehci *ehci;
+       struct ulpi_viewport ulpi_vp;
+       int ret, mio_usb;
+       /* Used for writing the ULPI data address */
+       struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
+
+       if (!index) {
+               mio_usb = zynq_slcr_get_mio_pin_status("usb0");
+               if (mio_usb != ZYNQ_USB_NUM_MIO) {
+                       printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb,
+                              index);
+                       return -1;
+               }
+               ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
+       } else {
+               mio_usb = zynq_slcr_get_mio_pin_status("usb1");
+               if (mio_usb != ZYNQ_USB_NUM_MIO) {
+                       printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb,
+                              index);
+                       return -1;
+               }
+               ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
+       }
+
+       *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+       *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+                       HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
+
+       ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint;
+       ulpi_vp.port_num = 0;
+
+       ret = ulpi_init(&ulpi_vp);
+       if (ret) {
+               puts("zynq ULPI viewport init failed\n");
+               return -1;
+       }
+
+       /* ULPI set flags */
+       ulpi_write(&ulpi_vp, &ulpi->otg_ctrl,
+                  ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN |
+                  ULPI_OTG_EXTVBUSIND);
+       ulpi_write(&ulpi_vp, &ulpi->function_ctrl,
+                  ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL |
+                  ULPI_FC_SUSPENDM);
+       ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0);
+
+       /* Set VBus */
+       ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set,
+                  ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+
+       return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(int index)
+{
+       struct usb_ehci *ehci;
+
+       if (!index)
+               ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0;
+       else
+               ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1;
+
+       /* Stop controller */
+       writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd);
+       udelay(1000);
+
+       /* Initiate controller reset */
+       writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd);
+
+       return 0;
+}
index 9763245..dc5bc22 100644 (file)
 # define CONFIG_SDHCI
 # define CONFIG_ZYNQ_SDHCI
 # define CONFIG_CMD_MMC
-# define CONFIG_CMD_FAT
+#endif
+
+#ifdef CONFIG_ZYNQ_USB
+# define CONFIG_USB_EHCI
+# define CONFIG_CMD_USB
+# define CONFIG_USB_STORAGE
+# define CONFIG_USB_EHCI_ZYNQ
+# define CONFIG_USB_ULPI_VIEWPORT
+# define CONFIG_USB_ULPI
+# define CONFIG_EHCI_IS_TDI
+# define CONFIG_USB_MAX_CONTROLLER_COUNT       2
+#endif
+
+#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQ_USB)
 # define CONFIG_SUPPORT_VFAT
+# define CONFIG_CMD_FAT
 # define CONFIG_CMD_EXT2
+# define CONFIG_FAT_WRITE
 # define CONFIG_DOS_PARTITION
+# define CONFIG_CMD_EXT4
+# define CONFIG_CMD_EXT4_WRITE
 #endif
 
 #define CONFIG_SYS_I2C_ZYNQ
                "bootm ${load_addr}\0" \
        "jtagboot=echo TFTPing FIT to RAM... && " \
                "tftpboot ${load_addr} ${fit_image} && " \
-               "bootm ${load_addr}\0"
+               "bootm ${load_addr}\0" \
+       "usbboot=if usb start; then " \
+                       "echo Copying FIT from USB to RAM... && " \
+                       "fatload usb 0 ${load_addr} ${fit_image} && " \
+                       "bootm ${load_addr}\0" \
+               "fi\0"
+
 #define CONFIG_BOOTCOMMAND             "run $modeboot"
 #define CONFIG_BOOTDELAY               3 /* -1 to Disable autoboot */
 #define CONFIG_SYS_LOAD_ADDR           0 /* default? */
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CLOCKS
 #define CONFIG_CMD_CLK
-#define CONFIG_SYS_MAXARGS             15 /* max number of command args */
+#define CONFIG_SYS_MAXARGS             32 /* max number of command args */
 #define CONFIG_SYS_CBSIZE              256 /* Console I/O Buffer Size */
 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 #define CONFIG_RSA
 
 /* Extend size of kernel image for uncompression */
-#define CONFIG_SYS_BOOTM_LEN   (20 * 1024 * 1024)
+#define CONFIG_SYS_BOOTM_LEN   (60 * 1024 * 1024)
 
 /* Boot FreeBSD/vxWorks from an ELF image */
 #if defined(CONFIG_ZYNQ_BOOT_FREEBSD)
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
 
 #define CONFIG_SPL_LDSCRIPT    "arch/arm/cpu/armv7/zynq/u-boot-spl.lds"
 
-/* Disable dcache for SPL just for sure */
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_DCACHE_OFF
-#undef CONFIG_FPGA
-#undef CONFIG_OF_CONTROL
-#endif
-
 /* MMC support */
 #ifdef CONFIG_ZYNQ_SDHCI0
 #define CONFIG_SPL_MMC_SUPPORT
 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot.img"
+#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_OF_SEPARATE)
+# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
+#else
+# define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME     "u-boot.img"
+#endif
+#endif
+
+/* Disable dcache for SPL just for sure */
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_DCACHE_OFF
+#undef CONFIG_FPGA
+#undef CONFIG_OF_CONTROL
 #endif
 
 /* Address in RAM where the parameters must be copied by SPL. */
index de0e241..291a5fe 100644 (file)
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_NO_FLASH
 
 #define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_I2C0
 #define CONFIG_ZYNQ_EEPROM
 #define CONFIG_ZYNQ_BOOT_FREEBSD
index 274140c..ce17d40 100644 (file)
@@ -18,6 +18,7 @@
 
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_ZYNQ_USB
 #define CONFIG_ZYNQ_SDHCI0
 #define CONFIG_ZYNQ_BOOT_FREEBSD
 #define CONFIG_DEFAULT_DEVICE_TREE     zynq-zed