/u-boot.sha1
/u-boot.dis
/u-boot.lds
+/u-boot.lst
/u-boot.ubl
/u-boot.ais
/u-boot.dtb
Paul Gortmaker <paul.gortmaker@windriver.com>
sbc8349 MPC8349
- sbc8540 MPC8540
sbc8548 MPC8548
- sbc8560 MPC8560
sbc8641d MPC8641D
Frank Gottschling <fgottschling@eltec.de>
endif
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o \
+LIBS-y += fs/cbfs/libcbfs.o \
+ fs/cramfs/libcramfs.o \
fs/ext4/libext4fs.o \
fs/fat/libfat.o \
fs/fdos/libfdos.o \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
else
GEN_UBOOT = \
- UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
- sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \
+ UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+ sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+ $$UNDEF_LST $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
endif
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
-$(obj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
+$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
$(obj)u-boot.lds \
+ $(obj)include/u-boot.lst \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
@rm -f $(obj)u-boot.spr
- @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
- @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+ @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
+ @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
+ @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
+ @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
@rm -f $(obj)MLO
@rm -f $(obj)tools/xway-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
ICache only when Code runs from RAM.
- 85xx CPU Options:
+ CONFIG_SYS_PPC64
+
+ Specifies that the core is a 64-bit PowerPC implementation (implements
+ the "64" category of the Power ISA). This is necessary for ePAPR
+ compliance, among other possible reasons.
+
CONFIG_SYS_FSL_TBCLK_DIV
Defines the core time base clock divider ratio compared to the
CONFIG_CALXEDA_XGMAC
Support for the Calxeda XGMAC device
- CONFIG_DRIVER_LAN91C96
+ CONFIG_LAN91C96
Support for SMSC's LAN91C96 chips.
CONFIG_LAN91C96_BASE
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
- CONFIG_DRIVER_SMC91111
+ CONFIG_SMC91111
Support for SMSC's LAN91C111 chip
CONFIG_SMC91111_BASE
This will also enable the command "fatwrite" enabling the
user to write files to FAT.
+CBFS (Coreboot Filesystem) support
+ CONFIG_CMD_CBFS
+
+ Define this to enable support for reading from a Coreboot
+ filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
+ and cbfsload.
+
- Keyboard Support:
CONFIG_ISA_KEYBOARD
.got : { *(.got) }
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
__bss_start = .;
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(4);
__image_copy_end = .;
_end = .;
. = ALIGN(4);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
. = ALIGN(4);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
#include <asm/io.h>
#include <asm/imx-common/boot_mode.h>
#include <malloc.h>
+#include <command.h>
static const struct boot_mode *modes[2];
int size;
char *dest;
- if (__u_boot_cmd_bmode.usage) {
- free(__u_boot_cmd_bmode.usage);
- __u_boot_cmd_bmode.usage = NULL;
+ cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+ if (entry->usage) {
+ free(entry->usage);
+ entry->usage = NULL;
}
modes[0] = p;
dest = malloc(size);
if (dest) {
create_usage(dest);
- __u_boot_cmd_bmode.usage = dest;
+ entry->usage = dest;
}
}
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */
#include <miiphy.h>
#endif
-#ifdef CONFIG_DRIVER_SMC91111
-#include "../drivers/net/smc91111.h"
-#endif
-#ifdef CONFIG_DRIVER_LAN91C96
-#include "../drivers/net/lan91c96.h"
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
ulong monitor_flash_len;
/* enable exceptions */
enable_interrupts();
- /* Perform network card initialisation if necessary */
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
- /* XXX: this needs to be moved to board init */
- if (getenv("ethaddr")) {
- uchar enetaddr[6];
- eth_getenv_enetaddr("ethaddr", enetaddr);
- smc_set_mac_addr(enetaddr);
- }
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : {
- KEEP(*(.u_boot_cmd))
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end = .;
. = ALIGN(4);
_got = .;
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long stack_end; /* highest stack address */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
- unsigned long bi_baudrate;
+ unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
CONSTRUCTORS
} >ram_data
- .u_boot_cmd :
- {
- ___u_boot_cmd_start = .;
- *(.u_boot_cmd)
- ___u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
} >ram_data
.text_l1 :
bd_t *bd;
unsigned long flags;
unsigned long board_type;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
printf(" gd: %p\n", gd);
printf(" |-flags: %lx\n", gd->flags);
printf(" |-board_type: %lx\n", gd->board_type);
- printf(" |-baudrate: %lu\n", gd->baudrate);
+ printf(" |-baudrate: %u\n", gd->baudrate);
printf(" |-have_console: %lx\n", gd->have_console);
printf(" |-ram_size: %lx\n", gd->ram_size);
printf(" |-env_addr: %lx\n", gd->env_addr);
#include <asm/immap.h>
#include <asm/io.h>
#include <asm/rtc.h>
+#include <linux/compiler.h>
/*
* Breath some life into the CPU...
*/
void cpu_init_f(void)
{
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- pll_t *pll = (pll_t *)MMAP_PLL;
+ fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
#if !defined(CONFIG_CF_SBF)
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ pll_t *pll = (pll_t *)MMAP_PLL;
+
/* Workaround, must place before fbcs */
out_be32(&pll->psr, 0x12);
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
+# Copyright 2011-2012 Freescale Semiconductor, Inc.
+#
# See file CREDITS for list of people who contributed to this
# project.
#
#
PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
+
+ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
+PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
+else
PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
+endif
ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
ifneq (,$(findstring GOT,$(shell $(LD) --help)))
{
rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
+ out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
+ udelay(10000);
setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
/* we don't return! */
case 0x4f:
id = 54450;
break;
+ case 0x9F:
+ id = 54410;
+ break;
+ case 0xA0:
+ id = 54415;
+ break;
+ case 0xA1:
+ id = 54416;
+ break;
+ case 0xA2:
+ id = 54417;
+ break;
+ case 0xA3:
+ id = 54418;
+ break;
}
if (id) {
#include <asm/processor.h>
#include <asm/rtc.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <asm/fec.h>
#endif
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
+void init_fbcs(void)
{
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
- out_be32(&scm1->mpr, 0x77777777);
- out_be32(&scm1->pacra, 0);
- out_be32(&scm1->pacrb, 0);
- out_be32(&scm1->pacrc, 0);
- out_be32(&scm1->pacrd, 0);
- out_be32(&scm1->pacre, 0);
- out_be32(&scm1->pacrf, 0);
- out_be32(&scm1->pacrg, 0);
+ fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
- /* FlexBus */
- out_8(&gpio->par_be,
- GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
- GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
- out_8(&gpio->par_fbctl,
- GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
- GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+ scm_t *scm = (scm_t *) MMAP_SCM;
+ pm_t *pm = (pm_t *) MMAP_PM;
+
+ /* Disable Switch */
+ *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
+
+ /* Disable core watchdog */
+ out_be16(&scm->cwcr, 0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
+ GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+ GPIO_PAR_FBCTL_TA_TA);
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+
+ /* eDMA */
+ out_8(&pm->pmcr0, 17);
+
+ /* INTR0 - INTR2 */
+ out_8(&pm->pmcr0, 18);
+ out_8(&pm->pmcr0, 19);
+ out_8(&pm->pmcr0, 20);
+
+ /* I2C */
+ out_8(&pm->pmcr0, 22);
+ out_8(&pm->pmcr1, 4);
+ out_8(&pm->pmcr1, 7);
+
+ /* DTMR0 - DTMR3*/
+ out_8(&pm->pmcr0, 28);
+ out_8(&pm->pmcr0, 29);
+ out_8(&pm->pmcr0, 30);
+ out_8(&pm->pmcr0, 31);
+
+ /* PIT0 - PIT3 */
+ out_8(&pm->pmcr0, 32);
+ out_8(&pm->pmcr0, 33);
+ out_8(&pm->pmcr0, 34);
+ out_8(&pm->pmcr0, 35);
+
+ /* Edge Port */
+ out_8(&pm->pmcr0, 36);
+ out_8(&pm->pmcr0, 37);
+
+ /* USB OTG */
+ out_8(&pm->pmcr0, 44);
+ /* USB Host */
+ out_8(&pm->pmcr0, 45);
+
+ /* ESDHC */
+ out_8(&pm->pmcr0, 51);
+
+ /* ENET0 - ENET1 */
+ out_8(&pm->pmcr0, 53);
+ out_8(&pm->pmcr0, 54);
+
+ /* NAND */
+ out_8(&pm->pmcr0, 63);
+
+#ifdef CONFIG_SYS_I2C_0
+ out_8(&gpio->par_cani2c, 0xF0);
+ /* I2C0 pull up */
+ out_be16(&gpio->pcr_b, 0x003C);
+ /* I2C0 max speed */
+ out_8(&gpio->srcr_cani2c, 0x03);
+#endif
+#ifdef CONFIG_SYS_I2C_2
+ /* I2C2 */
+ out_8(&gpio->par_ssi0h, 0xA0);
+ /* I2C2, UART7 */
+ out_8(&gpio->par_ssi0h, 0xA8);
+ /* UART7 */
+ out_8(&gpio->par_ssi0l, 0x2);
+ /* UART8, UART9 */
+ out_8(&gpio->par_cani2c, 0xAA);
+ /* UART4, UART0 */
+ out_8(&gpio->par_uart0, 0xAF);
+ /* UART5, UART1 */
+ out_8(&gpio->par_uart1, 0xAF);
+ /* UART6, UART2 */
+ out_8(&gpio->par_uart2, 0xAF);
+ /* I2C2 pull up */
+ out_be16(&gpio->pcr_h, 0xF000);
+#endif
+#ifdef CONFIG_SYS_I2C_5
+ /* I2C5 */
+ out_8(&gpio->par_uart1, 0x0A);
+ /* I2C5 pull up */
+ out_be16(&gpio->pcr_e, 0x0003);
+ out_be16(&gpio->pcr_f, 0xC000);
+#endif
+
+ /* Lowest slew rate for UART0,1,2 */
+ out_8(&gpio->srcr_uart, 0x00);
+#endif /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
+
+ /* FlexBus */
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+ GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+
+#ifdef CONFIG_FSL_I2C
+ out_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
+#endif
+#endif /* CONFIG_MCF5445x */
+
+ /* FlexBus Chipselect */
+ init_fbcs();
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
if (CONFIG_SYS_CS0_BASE != 0)
setvbr(CONFIG_SYS_CS0_BASE);
-#ifdef CONFIG_FSL_I2C
- out_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-
icache_enable();
}
void uart_port_conf(int port)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *) MMAP_PM;
+#endif
/* Setup Ports: */
switch (port) {
+#ifdef CONFIG_MCF5441x
+ case 0:
+ /* UART0 */
+ out_8(&pm->pmcr0, 24);
+ clrbits_8(&gpio->par_uart0,
+ ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
+ setbits_8(&gpio->par_uart0,
+ GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
+ break;
+ case 1:
+ /* UART1 */
+ out_8(&pm->pmcr0, 25);
+ clrbits_8(&gpio->par_uart1,
+ ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
+ setbits_8(&gpio->par_uart1,
+ GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
+ break;
+ case 2:
+ /* UART2 */
+ out_8(&pm->pmcr0, 26);
+ clrbits_8(&gpio->par_uart2,
+ ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
+ setbits_8(&gpio->par_uart2,
+ GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
+ break;
+ case 3:
+ /* UART3 */
+ out_8(&pm->pmcr0, 27);
+ clrbits_8(&gpio->par_dspi0,
+ ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
+ setbits_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
+ break;
+ case 4:
+ /* UART4 */
+ out_8(&pm->pmcr1, 24);
+ clrbits_8(&gpio->par_uart0,
+ ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
+ setbits_8(&gpio->par_uart0,
+ GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
+ break;
+ case 5:
+ /* UART5 */
+ out_8(&pm->pmcr1, 25);
+ clrbits_8(&gpio->par_uart1,
+ ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
+ setbits_8(&gpio->par_uart1,
+ GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
+ break;
+ case 6:
+ /* UART6 */
+ out_8(&pm->pmcr1, 26);
+ clrbits_8(&gpio->par_uart2,
+ ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
+ setbits_8(&gpio->par_uart2,
+ GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
+ break;
+ case 7:
+ /* UART7 */
+ out_8(&pm->pmcr1, 27);
+ clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
+ clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
+ setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
+ setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
+ break;
+ case 8:
+ /* UART8 */
+ out_8(&pm->pmcr0, 28);
+ clrbits_8(&gpio->par_cani2c,
+ ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
+ setbits_8(&gpio->par_cani2c,
+ GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
+ break;
+ case 9:
+ /* UART9 */
+ out_8(&pm->pmcr1, 29);
+ clrbits_8(&gpio->par_cani2c,
+ ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
+ setbits_8(&gpio->par_cani2c,
+ GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
+ break;
+#endif
+#ifdef CONFIG_MCF5445x
case 0:
clrbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
break;
+#endif /* CONFIG_MCF5445x */
}
}
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
#endif
}
}
+#endif /* CONFIG_MCF5445x */
+
+#ifdef CONFIG_MCF5441x
+ if (setclear) {
+ out_8(&gpio->par_fec, 0x03);
+ out_8(&gpio->srcr_fec, 0x0F);
+ clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
+ GPIO_PAR_SIMP0H_DAT_GPIO);
+ clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
+ GPIO_PDDR_G4_OUTPUT);
+ clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
+
+ } else
+ clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
+#endif
return 0;
}
#endif
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *) MMAP_PM;
+
+ out_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+ GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+ out_8(&gpio->srcr_dspiow, 3);
+
+ /* DSPI0 */
+ out_8(&pm->pmcr0, 23);
+#endif
}
int cfspi_claim_bus(uint bus, uint cs)
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
+#endif
+
+#ifdef CONFIG_MCF5441x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
+ setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ break;
+ }
+#endif
return 0;
}
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
+#endif
+
+#ifdef CONFIG_MCF5441x
+ if (cs == 1)
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
}
#endif
/* Round divider down to nearest power of two */
for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
+#ifdef CONFIG_MCF5445x
/* Apply the divider to the system clock */
clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
+#endif
/* Enable Limp Mode */
setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
;
}
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
-int get_clocks(void)
+#ifdef CONFIG_MCF5441x
+void setup_5441x_clocks(void)
{
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ pll_t *pll = (pll_t *)MMAP_PLL;
+ int temp, vco = 0, bootmod_ccr, pdr;
+
+ bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
+
+ switch (bootmod_ccr) {
+ case 0:
+ out_be32(&pll->pcr, 0x00000013);
+ out_be32(&pll->pdr, 0x00e70c61);
+ clock_exit_limp();
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ }
+
+ /*Change frequency for Modelo SER1 USB host*/
+#ifdef CONFIG_LOW_MCFCLK
+ temp = in_be32(&pll->pcr);
+ temp &= ~0x3f;
+ temp |= 5;
+ out_be32(&pll->pcr, temp);
+
+ temp = in_be32(&pll->pdr);
+ temp &= ~0x001f0000;
+ temp |= 0x00040000;
+ out_be32(&pll->pdr, temp);
+ __asm__("tpf");
+#endif
+ setbits_be16(&ccm->misccr2, 0x02);
+
+ vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
+ CONFIG_SYS_INPUT_CLKSRC;
+ gd->vco_clk = vco;
+
+ gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
+
+ pdr = in_be32(&pll->pdr);
+ temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
+ gd->cpu_clk = vco / temp; /* cpu clock */
+ gd->flb_clk = vco / temp; /* FlexBus clock */
+ gd->flb_clk >>= 1;
+ if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
+ gd->flb_clk >>= 1;
+
+ temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
+ gd->bus_clk = vco / temp; /* bus clock */
+
+}
+#endif
+
+#ifdef CONFIG_MCF5445x
+void setup_5445x_clocks(void)
+{
ccm_t *ccm = (ccm_t *)MMAP_CCM;
pll_t *pll = (pll_t *)MMAP_PLL;
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
- int vco = 0, bPci, temp, fbtemp, pcrvalue;
+ int vco = 0, temp, fbtemp, pcrvalue;
int *pPllmult = NULL;
u16 fbpll_mask;
+#ifdef CONFIG_PCI
+ int bPci;
+#endif
#ifdef CONFIG_M54455EVB
u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
fbpll_mask = 3; /* 11b */
+#ifdef CONFIG_PCI
bPci = 1;
+#endif
} else {
pPllmult = &pllmult_nopci[0];
fbpll_mask = 7; /* 111b */
#ifdef CONFIG_PCI
gd->pci_clk = 0;
-#endif
bPci = 0;
+#endif
}
#ifdef CONFIG_M54455EVB
#endif
}
+#ifdef CONFIG_FSL_I2C
+ gd->i2c1_clk = gd->bus_clk;
+#endif
+}
+#endif
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#ifdef CONFIG_MCF5441x
+ setup_5441x_clocks();
+#endif
+#ifdef CONFIG_MCF5445x
+ setup_5445x_clocks();
+#endif
+
#ifdef CONFIG_FSL_I2C
gd->i2c1_clk = gd->bus_clk;
#endif
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm-offsets.h>
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
addl #60,%sp; /* space for 15 regs */ \
rte;
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
* These vectors are to catch any un-intended traps.
*/
_vectors:
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
INITSP: .long 0 /* Initial SP */
+#ifdef CONFIG_CF_SBF
INITPC: .long ASM_DRAMINIT /* Initial PC */
+#endif
+#ifdef CONFIG_SYS_NAND_BOOT
+INITPC: .long ASM_DRAMINIT_N /* Initial PC */
+#endif
#else
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
- .long 0x00030000 /* image length */
+ .long 0x00040000 /* image length */
.long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.w #0x2700,%sr /* Mask off Interrupt */
+#ifdef CONFIG_SYS_NAND_BOOT
+ /* for assembly stack */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+#endif
+
+#ifdef CONFIG_CF_SBF
move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_MCF5441x
+ /* TC: enable all peripherals,
+ in the future only enable certain peripherals */
+ move.l #0xFC04002D, %a1
+#if defined(CONFIG_CF_SBF)
+ move.b #23, (%a1) /* dspi */
+#endif
+ move.b #46, (%a1) /* DDR */
+
+ /* slew settings */
+ move.l #0xEC094060, %a1
+ move.b #0, (%a1)
+
+ /* use vco instead of cpu*2 clock for ddr clock */
+ move.l #0xEC09001A, %a1
+ move.w #0xE01D, (%a1)
+
+ /* DDR settings */
+ move.l #0xFC0B8180, %a1
+ move.l #0x00000000, (%a1)
+ move.l #0x40000000, (%a1)
+
+ move.l #0xFC0B81AC, %a1
+ move.l #0x01030203, (%a1)
+
+ move.l #0xFC0B8000, %a1
+ move.l #0x01010101, (%a1)+ /* 0x00 */
+ move.l #0x00000101, (%a1)+ /* 0x04 */
+ move.l #0x01010100, (%a1)+ /* 0x08 */
+ move.l #0x01010000, (%a1)+ /* 0x0C */
+ move.l #0x00010101, (%a1)+ /* 0x10 */
+ move.l #0xFC0B8018, %a1
+ move.l #0x00010100, (%a1)+ /* 0x18 */
+ move.l #0x00000001, (%a1)+ /* 0x1C */
+ move.l #0x01000001, (%a1)+ /* 0x20 */
+ move.l #0x00000100, (%a1)+ /* 0x24 */
+ move.l #0x00010001, (%a1)+ /* 0x28 */
+ move.l #0x00000200, (%a1)+ /* 0x2C */
+ move.l #0x01000002, (%a1)+ /* 0x30 */
+ move.l #0x00000000, (%a1)+ /* 0x34 */
+ move.l #0x00000100, (%a1)+ /* 0x38 */
+ move.l #0x02000100, (%a1)+ /* 0x3C */
+ move.l #0x02000407, (%a1)+ /* 0x40 */
+ move.l #0x02030007, (%a1)+ /* 0x44 */
+ move.l #0x02000100, (%a1)+ /* 0x48 */
+ move.l #0x0A030203, (%a1)+ /* 0x4C */
+ move.l #0x00020708, (%a1)+ /* 0x50 */
+ move.l #0x00050008, (%a1)+ /* 0x54 */
+ move.l #0x04030002, (%a1)+ /* 0x58 */
+ move.l #0x00000004, (%a1)+ /* 0x5C */
+ move.l #0x020A0000, (%a1)+ /* 0x60 */
+ move.l #0x0C00000E, (%a1)+ /* 0x64 */
+ move.l #0x00002004, (%a1)+ /* 0x68 */
+ move.l #0x00000000, (%a1)+ /* 0x6C */
+ move.l #0x00100010, (%a1)+ /* 0x70 */
+ move.l #0x00100010, (%a1)+ /* 0x74 */
+ move.l #0x00000000, (%a1)+ /* 0x78 */
+ move.l #0x07990000, (%a1)+ /* 0x7C */
+ move.l #0xFC0B80A0, %a1
+ move.l #0x00000000, (%a1)+ /* 0xA0 */
+ move.l #0x00C80064, (%a1)+ /* 0xA4 */
+ move.l #0x44520002, (%a1)+ /* 0xA8 */
+ move.l #0x00C80023, (%a1)+ /* 0xAC */
+ move.l #0xFC0B80B4, %a1
+ move.l #0x0000C350, (%a1) /* 0xB4 */
+ move.l #0xFC0B80E0, %a1
+ move.l #0x04000000, (%a1)+ /* 0xE0 */
+ move.l #0x03000304, (%a1)+ /* 0xE4 */
+ move.l #0x40040000, (%a1)+ /* 0xE8 */
+ move.l #0xC0004004, (%a1)+ /* 0xEC */
+ move.l #0x0642C000, (%a1)+ /* 0xF0 */
+ move.l #0x00000642, (%a1)+ /* 0xF4 */
+ move.l #0xFC0B8024, %a1
+ tpf
+ move.l #0x01000100, (%a1) /* 0x24 */
+
+ move.l #0x2000, %d1
+ jsr asm_delay
+#endif /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
/* Dram Initialization a1, a2, and d0 */
/* mscr sdram */
move.l #0xFC0A4074, %a1
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
-
+#ifdef CONFIG_SYS_NAND_BOOT
+ beq asm_nand_chk_status
+#endif
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
move.l #2000, %d1
jsr asm_delay
+#endif /* CONFIG_MCF5445x */
+#ifdef CONFIG_CF_SBF
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
asm_dspi_init:
+#ifdef CONFIG_MCF5441x
+ move.l #0xEC09404E, %a1
+ move.l #0xEC09404F, %a2
+ move.b #0xFF, (%a1)
+ move.b #0x80, (%a2)
+#endif
+
+#ifdef CONFIG_MCF5445x
move.l #0xFC0A4063, %a0
move.b #0x7F, (%a0)
-
+#endif
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0
+#ifdef CONFIG_MCF5441x
+ move.l #0x3E000016, (%a0)
+#endif
+#ifdef CONFIG_MCF5445x
move.l #0x3E000011, (%a0)
+#endif
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
move.b (%a3), %d1
rts
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+ /* copy 4 boot pages to dram as soon as possible */
+ /* each page is 996 bytes (1056 total with 60 ECC bytes */
+ move.l #0x00000000, %a1 /* src */
+ move.l #TEXT_BASE, %a2 /* dst */
+ move.l #0x3E0, %d0 /* sz in long */
+
+asm_boot_nand_copy:
+ move.l (%a1)+, (%a2)+
+ subq.l #1, %d0
+ bne asm_boot_nand_copy
+
+ /* jump to memory and execute */
+ move.l #(asm_nand_init), %a0
+ jmp (%a0)
+
+asm_nand_init:
+ /* exit nand boot-mode */
+ move.l #0xFC0FFF30, %a1
+ or.l #0x00000040, %d1
+ move.l %d1, (%a1)
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(CACR_STATUS), %a1 /* CACR */
+ move.l #(ICACHE_STATUS), %a2 /* icache */
+ move.l #(DCACHE_STATUS), %a3 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+ move.l %d0, (%a3)
+
+ /* invalidate and disable cache */
+ move.l #0x01004100, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+ movec %d0, %ACR2
+ movec %d0, %ACR3
+
+ /* Must disable global address */
+ move.l #0xFC008000, %a1
+ move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #0xFC008008, %a1
+ move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #0xFC008004, %a1
+ move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+
+ /* NAND port configuration */
+ move.l #0xEC094048, %a1
+ move.b #0xFD, (%a1)+
+ move.b #0x5F, (%a1)+
+ move.b #0x04, (%a1)+
+
+ /* reset nand */
+ move.l #0xFC0FFF38, %a1 /* isr */
+ move.l #0x000e0000, (%a1)
+ move.l #0xFC0FFF08, %a2
+ move.l #0x00000000, (%a2)+ /* car */
+ move.l #0x11000000, (%a2)+ /* rar */
+ move.l #0x00000000, (%a2)+ /* rpt */
+ move.l #0x00000000, (%a2)+ /* rai */
+ move.l #0xFC0FFF2c, %a2 /* cfg */
+ move.l #0x00000000, (%a2)+ /* secsz */
+ move.l #0x000e0681, (%a2)+
+ move.l #0xFC0FFF04, %a2 /* cmd2 */
+ move.l #0xFF404001, (%a2)
+ move.l #0x000e0000, (%a1)
+
+ move.l #0x2000, %d1
+ jsr asm_delay
+
+ /* setup nand */
+ move.l #0xFC0FFF00, %a1
+ move.l #0x30700000, (%a1)+ /* cmd1 */
+ move.l #0x007EF000, (%a1)+ /* cmd2 */
+
+ move.l #0xFC0FFF2C, %a1
+ move.l #0x00000841, (%a1)+ /* secsz */
+ move.l #0x000e0681, (%a1)+ /* cfg */
+
+ move.l #100, %d4 /* 100 pages ~200KB */
+ move.l #4, %d2 /* start at 4 */
+ move.l #0xFC0FFF04, %a0 /* cmd2 */
+ move.l #0xFC0FFF0C, %a1 /* rar */
+ move.l #(TEXT_BASE + 0xF80), %a2 /* dst */
+
+asm_nand_read:
+ move.l #0x11000000, %d0 /* rar */
+ or.l %d2, %d0
+ move.l %d0, (%a1)
+ add.l #1, %d2
+
+ move.l (%a0), %d0 /* cmd2 */
+ or.l #1, %d0
+ move.l %d0, (%a0)
+
+ move.l #0x200, %d1
+ jsr asm_delay
+
+asm_nand_chk_status:
+ move.l #0xFC0FFF38, %a4 /* isr */
+ move.l (%a4), %d0
+ and.l #0x40000000, %d0
+ tst.l %d0
+ beq asm_nand_chk_status
+
+ move.l #0xFC0FFF38, %a4 /* isr */
+ move.l (%a4), %d0
+ or.l #0x000E0000, %d0
+ move.l %d0, (%a4)
+
+ move.l #0x200, %d3
+ move.l #0xFC0FC000, %a3 /* buf 1 */
+asm_nand_copy:
+ move.l (%a3)+, (%a2)+
+ subq.l #1, %d3
+ bgt asm_nand_copy
+
+ subq.l #1, %d4
+ bgt asm_nand_read
+
+ /* jump to memory and execute */
+ move.l #(TEXT_BASE + 0x400), %a0
+ jmp (%a0)
+
+#endif /* CONFIG_SYS_NAND_BOOT */
asm_delay:
nop
subq.l #1, %d1
bne asm_delay
rts
-#endif /* CONFIG_CF_SBF */
+#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
.text
. = 0x400
.globl _start
_start:
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
+#else
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+#endif
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
-#endif
move.l #__got_start, %a5 /* put relocation table address to a5 */
move.l #__got_start, %a5 /* put relocation table address to a5 */
- bsr cpu_init_f /* run low-level CPU init code (from flash) */
- bsr board_init_f /* run low-level board init code (from flash) */
+ jbsr cpu_init_f /* run low-level CPU init code (from flash) */
+ jbsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
/*
* ColdFire cache
*
- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
#define CONFIG_CF_V4
-#if defined(CONFIG_MCF5441x)
+#elif defined(CONFIG_MCF5441x)
#define CONFIG_CF_V4E /* Four Extra ACRn */
#endif
-#endif
/* ***** CACR ***** */
/* V2 Core */
#endif /* CONFIG_CF_V3 */
/* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_CACR_DEC (1 << 31)
#define CF_CACR_DW (1 << 30)
#define CF_CACR_IDSP (1 << 7)
#define CF_CACR_EUSP (1 << 5)
-#ifdef CONFIG_MCF5445x
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
#define CF_CACR_IVO (1 << 20)
#define CF_CACR_SPA (1 << 14)
#else
#endif /* CONFIG_CF_V2 */
/* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
#define CF_ACR_AMM (1 << 10)
#define CF_ACR_SP (1 << 3)
#endif /* CONFIG_CF_V4 */
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#ifdef CONFIG_PCI
/*
* ColdFire Internal Memory Map and Defines
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_SYS_NUM_IRQS (128)
#endif /* CONFIG_M5329 && CONFIG_M5373 */
+#if defined(CONFIG_M54418)
+#include <asm/immap_5441x.h>
+#include <asm/m5441x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
+
+#if (CONFIG_SYS_UART_PORT < 4)
+#define CONFIG_SYS_UART_BASE (MMAP_UART0 + \
+ (CONFIG_SYS_UART_PORT * 0x4000))
+#else
+#define CONFIG_SYS_UART_BASE (MMAP_UART4 + \
+ ((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+#endif
+
+#define MMAP_DSPI MMAP_DSPI0
+#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI (6)
+#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE (6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS (128)
+
+#endif /* CONFIG_M54418 */
+
#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>
--- /dev/null
+/*
+ * MCF5441x Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5441X__
+#define __IMMAP_5441X__
+
+/* Module Base Addresses */
+#define MMAP_XBS 0xFC004000
+#define MMAP_FBCS 0xFC008000
+#define MMAP_CAN0 0xFC020000
+#define MMAP_CAN1 0xFC024000
+#define MMAP_I2C1 0xFC038000
+#define MMAP_DSPI1 0xFC03C000
+#define MMAP_SCM 0xFC040000
+#define MMAP_PM 0xFC04002C
+#define MMAP_EDMA 0xFC044000
+#define MMAP_INTC0 0xFC048000
+#define MMAP_INTC1 0xFC04C000
+#define MMAP_INTC2 0xFC050000
+#define MMAP_IACK 0xFC054000
+#define MMAP_I2C0 0xFC058000
+#define MMAP_DSPI0 0xFC05C000
+#define MMAP_UART0 0xFC060000
+#define MMAP_UART1 0xFC064000
+#define MMAP_UART2 0xFC068000
+#define MMAP_UART3 0xFC06C000
+#define MMAP_DTMR0 0xFC070000
+#define MMAP_DTMR1 0xFC074000
+#define MMAP_DTMR2 0xFC078000
+#define MMAP_DTMR3 0xFC07C000
+#define MMAP_PIT0 0xFC080000
+#define MMAP_PIT1 0xFC084000
+#define MMAP_PIT2 0xFC088000
+#define MMAP_PIT3 0xFC08C000
+#define MMAP_EPORT0 0xFC090000
+#define MMAP_ADC 0xFC094000
+#define MMAP_DAC0 0xFC098000
+#define MMAP_DAC1 0xFC09C000
+#define MMAP_RRTC 0xFC0A8000
+#define MMAP_SIM 0xFC0AC000
+#define MMAP_USBOTG 0xFC0B0000
+#define MMAP_USBEHCI 0xFC0B4000
+#define MMAP_SDRAM 0xFC0B8000
+#define MMAP_SSI0 0xFC0BC000
+#define MMAP_PLL 0xFC0C0000
+#define MMAP_RNG 0xFC0C4000
+#define MMAP_SSI1 0xFC0C8000
+#define MMAP_ESDHC 0xFC0CC000
+#define MMAP_FEC0 0xFC0D4000
+#define MMAP_FEC1 0xFC0D8000
+#define MMAP_L2_SW0 0xFC0DC000
+#define MMAP_L2_SW1 0xFC0E0000
+
+#define MMAP_NFC_RAM 0xFC0FC000
+#define MMAP_NFC 0xFC0FF000
+
+#define MMAP_1WIRE 0xEC008000
+#define MMAP_I2C2 0xEC010000
+#define MMAP_I2C3 0xEC014000
+#define MMAP_I2C4 0xEC018000
+#define MMAP_I2C5 0xEC01C000
+#define MMAP_DSPI2 0xEC038000
+#define MMAP_DSPI3 0xEC03C000
+#define MMAP_UART4 0xEC060000
+#define MMAP_UART5 0xEC064000
+#define MMAP_UART6 0xEC068000
+#define MMAP_UART7 0xEC06C000
+#define MMAP_UART8 0xEC070000
+#define MMAP_UART9 0xEC074000
+#define MMAP_RCM 0xEC090000
+#define MMAP_CCM 0xEC090000
+#define MMAP_GPIO 0xEC094000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+ u8 resv0[0x18];
+ u16 sbfsr; /* Serial Boot Facility Status */
+ u8 resv1[0x6];
+ u16 sbfcr; /* Serial Boot Facility Control */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+ u8 ccm_resv0[0x4]; /* 0x00 */
+ u16 ccr; /* 0x04 Chip Configuration */
+ u8 resv1[0x2]; /* 0x06 */
+ u16 rcon; /* 0x08 Reset Configuration */
+ u16 cir; /* 0x0A Chip Identification */
+ u8 resv2[0x2]; /* 0x0C */
+ u16 misccr; /* 0x0E Miscellaneous Control */
+ u16 cdrh; /* 0x10 Clock Divider */
+ u16 cdrl; /* 0x12 Clock Divider */
+ u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
+ u16 uhcsr; /* 0x16 */
+ u16 misccr3; /* 0x18 */
+ u16 misccr2; /* 0x1A */
+ u16 adctsr; /* 0x1C */
+ u16 dactsr; /* 0x1E */
+ u16 sbfsr; /* 0x20 */
+ u16 sbfcr; /* 0x22 */
+ u32 fnacr; /* 0x24 */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+ u8 podr_a; /* 0x00 */
+ u8 podr_b; /* 0x01 */
+ u8 podr_c; /* 0x02 */
+ u8 podr_d; /* 0x03 */
+ u8 podr_e; /* 0x04 */
+ u8 podr_f; /* 0x05 */
+ u8 podr_g; /* 0x06 */
+ u8 podr_h; /* 0x07 */
+ u8 podr_i; /* 0x08 */
+ u8 podr_j; /* 0x09 */
+ u8 podr_k; /* 0x0A */
+ u8 rsvd0; /* 0x0B */
+
+ u8 pddr_a; /* 0x0C */
+ u8 pddr_b; /* 0x0D */
+ u8 pddr_c; /* 0x0E */
+ u8 pddr_d; /* 0x0F */
+ u8 pddr_e; /* 0x10 */
+ u8 pddr_f; /* 0x11 */
+ u8 pddr_g; /* 0x12 */
+ u8 pddr_h; /* 0x13 */
+ u8 pddr_i; /* 0x14 */
+ u8 pddr_j; /* 0x15 */
+ u8 pddr_k; /* 0x16 */
+ u8 rsvd1; /* 0x17 */
+
+ u8 ppdsdr_a; /* 0x18 */
+ u8 ppdsdr_b; /* 0x19 */
+ u8 ppdsdr_c; /* 0x1A */
+ u8 ppdsdr_d; /* 0x1B */
+ u8 ppdsdr_e; /* 0x1C */
+ u8 ppdsdr_f; /* 0x1D */
+ u8 ppdsdr_g; /* 0x1E */
+ u8 ppdsdr_h; /* 0x1F */
+ u8 ppdsdr_i; /* 0x20 */
+ u8 ppdsdr_j; /* 0x21 */
+ u8 ppdsdr_k; /* 0x22 */
+ u8 rsvd2; /* 0x23 */
+
+ u8 pclrr_a; /* 0x24 */
+ u8 pclrr_b; /* 0x25 */
+ u8 pclrr_c; /* 0x26 */
+ u8 pclrr_d; /* 0x27 */
+ u8 pclrr_e; /* 0x28 */
+ u8 pclrr_f; /* 0x29 */
+ u8 pclrr_g; /* 0x2A */
+ u8 pclrr_h; /* 0x2B */
+ u8 pclrr_i; /* 0x2C */
+ u8 pclrr_j; /* 0x2D */
+ u8 pclrr_k; /* 0x2E */
+ u8 rsvd3; /* 0x2F */
+
+ u16 pcr_a; /* 0x30 */
+ u16 pcr_b; /* 0x32 */
+ u16 pcr_c; /* 0x34 */
+ u16 pcr_d; /* 0x36 */
+ u16 pcr_e; /* 0x38 */
+ u16 pcr_f; /* 0x3A */
+ u16 pcr_g; /* 0x3C */
+ u16 pcr_h; /* 0x3E */
+ u16 pcr_i; /* 0x40 */
+ u16 pcr_j; /* 0x42 */
+ u16 pcr_k; /* 0x44 */
+ u16 rsvd4; /* 0x46 */
+
+ u8 par_fbctl; /* 0x48 */
+ u8 par_be; /* 0x49 */
+ u8 par_cs; /* 0x4A */
+ u8 par_cani2c; /* 0x4B */
+ u8 par_irqh; /* 0x4C */
+ u8 par_irql; /* 0x4D */
+ u8 par_dspi0; /* 0x4E */
+ u8 par_dspiow; /* 0x4F */
+ u8 par_timer; /* 0x50 */
+ u8 par_uart2; /* 0x51 */
+ u8 par_uart1; /* 0x52 */
+ u8 par_uart0; /* 0x53 */
+ u8 par_sdhch; /* 0x54 */
+ u8 par_sdhcl; /* 0x55 */
+ u8 par_simp0h; /* 0x56 */
+ u8 par_simp1h; /* 0x57 */
+ u8 par_ssi0h; /* 0x58 */
+ u8 par_ssi0l; /* 0x59 */
+ u8 par_dbg1h; /* 0x5A */
+ u8 par_dbg0h; /* 0x5B */
+ u8 par_dbgl; /* 0x5C */
+ u8 rsvd5; /* 0x5D */
+ u8 par_fec; /* 0x5E */
+ u8 rsvd6; /* 0x5F */
+
+ u8 mscr_sdram; /* 0x60 */
+ u8 rsvd7[3]; /* 0x61-0x63 */
+
+ u8 srcr_fb1; /* 0x64 */
+ u8 srcr_fb2; /* 0x65 */
+ u8 srcr_fb3; /* 0x66 */
+ u8 srcr_fb4; /* 0x67 */
+ u8 srcr_dspiow; /* 0x68 */
+ u8 srcr_cani2c; /* 0x69 */
+ u8 srcr_irq; /* 0x6A */
+ u8 srcr_timer; /* 0x6B */
+ u8 srcr_uart; /* 0x6C */
+ u8 srcr_fec; /* 0x6D */
+ u8 srcr_sdhc; /* 0x6E */
+ u8 srcr_simp0; /* 0x6F */
+ u8 srcr_ssi0; /* 0x70 */
+ u8 rsvd8[3]; /* 0x71-0x73 */
+
+ u16 urts_pol; /* 0x74 */
+ u16 ucts_pol; /* 0x76 */
+ u16 utxd_wom; /* 0x78 */
+ u32 urxd_wom; /* 0x7c */
+
+ u32 hcr1; /* 0x80 */
+ u32 hcr0; /* 0x84 */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+ u32 cr00; /* 0x00 */
+ u32 cr01; /* 0x04 */
+ u32 cr02; /* 0x08 */
+ u32 cr03; /* 0x0C */
+ u32 cr04; /* 0x10 */
+ u32 cr05; /* 0x14 */
+ u32 cr06; /* 0x18 */
+ u32 cr07; /* 0x1C */
+
+ u32 cr08; /* 0x20 */
+ u32 cr09; /* 0x24 */
+ u32 cr10; /* 0x28 */
+ u32 cr11; /* 0x2C */
+ u32 cr12; /* 0x30 */
+ u32 cr13; /* 0x34 */
+ u32 cr14; /* 0x38 */
+ u32 cr15; /* 0x3C */
+
+ u32 cr16; /* 0x40 */
+ u32 cr17; /* 0x44 */
+ u32 cr18; /* 0x48 */
+ u32 cr19; /* 0x4C */
+ u32 cr20; /* 0x50 */
+ u32 cr21; /* 0x54 */
+ u32 cr22; /* 0x58 */
+ u32 cr23; /* 0x5C */
+
+ u32 cr24; /* 0x60 */
+ u32 cr25; /* 0x64 */
+ u32 cr26; /* 0x68 */
+ u32 cr27; /* 0x6C */
+ u32 cr28; /* 0x70 */
+ u32 cr29; /* 0x74 */
+ u32 cr30; /* 0x78 */
+ u32 cr31; /* 0x7C */
+
+ u32 cr32; /* 0x80 */
+ u32 cr33; /* 0x84 */
+ u32 cr34; /* 0x88 */
+ u32 cr35; /* 0x8C */
+ u32 cr36; /* 0x90 */
+ u32 cr37; /* 0x94 */
+ u32 cr38; /* 0x98 */
+ u32 cr39; /* 0x9C */
+
+ u32 cr40; /* 0xA0 */
+ u32 cr41; /* 0xA4 */
+ u32 cr42; /* 0xA8 */
+ u32 cr43; /* 0xAC */
+ u32 cr44; /* 0xB0 */
+ u32 cr45; /* 0xB4 */
+ u32 cr46; /* 0xB8 */
+ u32 cr47; /* 0xBC */
+ u32 cr48; /* 0xC0 */
+ u32 cr49; /* 0xC4 */
+ u32 cr50; /* 0xC8 */
+ u32 cr51; /* 0xCC */
+ u32 cr52; /* 0xD0 */
+ u32 cr53; /* 0xD4 */
+ u32 cr54; /* 0xD8 */
+ u32 cr55; /* 0xDC */
+ u32 cr56; /* 0xE0 */
+ u32 cr57; /* 0xE4 */
+ u32 cr58; /* 0xE8 */
+ u32 cr59; /* 0xEC */
+ u32 cr60; /* 0xF0 */
+ u32 cr61; /* 0xF4 */
+ u32 cr62; /* 0xF8 */
+ u32 cr63; /* 0xFC */
+
+ u32 rsvd3[32]; /* 0xF4-0x1A8 */
+
+ u32 rcrcr; /* 0x180 */
+ u32 swrcr; /* 0x184 */
+ u32 rcr; /* 0x188 */
+ u32 msovr; /* 0x18C */
+ u32 rcrdbg; /* 0x190 */
+ u32 sl0adj; /* 0x194 */
+ u32 sl1adj; /* 0x198 */
+ u32 sl2adj; /* 0x19C */
+ u32 sl3adj; /* 0x1A0 */
+ u32 sl4adj; /* 0x1A4 */
+ u32 flight_tm; /* 0x1A8 */
+ u32 padcr; /* 0x1AC */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+ u32 pcr; /* Control */
+ u32 pdr; /* Divider */
+ u32 psr; /* Status */
+} pll_t;
+
+typedef struct scm {
+ u8 rsvd1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 */
+ u16 rsvd2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 */
+ u8 rsvd3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B */
+ u8 rsvd4[3]; /* 0x1C - 0x1E */
+ u8 scmisr; /* 0x1F */
+ u32 rsvd5; /* 0x20 - 0x23 */
+ u32 bcr; /* 0x24 */
+ u8 rsvd6[72]; /* 0x28 - 0x6F */
+ u32 cfadr; /* 0x70 */
+ u8 rsvd7; /* 0x74 */
+ u8 cfier; /* 0x75 */
+ u8 cfloc; /* 0x76 */
+ u8 cfatr; /* 0x77 */
+ u32 rsvd8; /* 0x78 - 0x7B */
+ u32 cfdtr; /* 0x7C */
+} scm_t;
+
+typedef struct pm {
+ u8 pmsr0; /* */
+ u8 pmcr0;
+ u8 pmsr1;
+ u8 pmcr1;
+ u32 pmhr0;
+ u32 pmlr0;
+ u32 pmhr1;
+ u32 pmlr1;
+} pm_t;
+
+#endif /* __IMMAP_5441X__ */
--- /dev/null
+/*
+ * MCF5441X Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5441X__
+#define __MCF5441X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_UART3 (29)
+#define INT0_LO_I2C0 (30)
+#define INT0_LO_DSPI0 (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_MACNET0_TXF (36)
+#define INT0_HI_MACNET0_TXB (37)
+#define INT0_HI_MACNET0_UN (38)
+#define INT0_HI_MACNET0_RL (39)
+#define INT0_HI_MACNET0_RXF (40)
+#define INT0_HI_MACNET0_RXB (41)
+#define INT0_HI_MACNET0_MII (42)
+#define INT0_HI_MACNET0_LC (43)
+/* not used 44 */
+#define INT0_HI_MACNET0_GRA (45)
+#define INT0_HI_MACNET0_EBERR (46)
+#define INT0_HI_MACNET0_BABT (47)
+#define INT0_HI_MACNET0_BABR (48)
+#define INT0_HI_MACNET1_TXF (49)
+#define INT0_HI_MACNET1_TXB (50)
+#define INT0_HI_MACNET1_UN (51)
+#define INT0_HI_MACNET1_RL (52)
+#define INT0_HI_MACNET1_RXF (53)
+#define INT0_HI_MACNET1_RXB (54)
+#define INT0_HI_MACNET1_MII (55)
+#define INT0_HI_MACNET1_LC (56)
+/* not used 57 */
+#define INT0_HI_MACNET1_GRA (58)
+#define INT0_HI_MACNET1_EBERR (59)
+#define INT0_HI_MACNET1_BABT (60)
+#define INT0_HI_MACNET1_BABR (61)
+#define INT0_HI_SCMIR (62)
+#define INT0_HI_OW (63)
+
+#define INT1_LO_CAN0_IFG (0)
+#define INT1_LO_CAN0_BOFF (1)
+/* not used 2 */
+#define INT1_LO_CAN0_TXRXWRN (3)
+#define INT1_LO_CAN1_IFG (4)
+#define INT1_LO_CAN1_BOFF (5)
+/* not used 6 */
+#define INT1_LO_CAN1_TXRXWRN (7)
+#define INT1_LO_EDMA_16 (8)
+#define INT1_LO_EDMA_17 (9)
+#define INT1_LO_EDMA_18 (10)
+#define INT1_LO_EDMA_19 (11)
+#define INT1_LO_EDMA_20 (12)
+#define INT1_LO_EDMA_21 (13)
+#define INT1_LO_EDMA_22 (14)
+#define INT1_LO_EDMA_23 (15)
+#define INT1_LO_EDMA_24 (16)
+#define INT1_LO_EDMA_25 (17)
+#define INT1_LO_EDMA_26 (18)
+#define INT1_LO_EDMA_27 (19)
+#define INT1_LO_EDMA_28 (20)
+#define INT1_LO_EDMA_29 (21)
+#define INT1_LO_EDMA_30 (22)
+#define INT1_LO_EDMA_31 (23)
+#define INT1_LO_EDMA_32 (24)
+#define INT1_LO_EDMA_33 (25)
+#define INT1_LO_EDMA_34 (26)
+#define INT1_LO_EDMA_35 (27)
+#define INT1_LO_EDMA_36 (28)
+#define INT1_LO_EDMA_37 (29)
+#define INT1_LO_EDMA_38 (30)
+#define INT1_LO_EDMA_39 (31)
+#define INT1_LO_EDMA_40 (32)
+#define INT1_HI_EDMA_41 (33)
+#define INT1_HI_EDMA_42 (34)
+#define INT1_HI_EDMA_43 (35)
+#define INT1_HI_EDMA_44 (36)
+#define INT1_HI_EDMA_45 (37)
+#define INT1_HI_EDMA_46 (38)
+#define INT1_HI_EDMA_47 (39)
+#define INT1_HI_EDMA_48 (40)
+#define INT1_HI_EDMA_49 (41)
+#define INT1_HI_EDMA_50 (42)
+#define INT1_HI_EDMA_51 (43)
+#define INT1_HI_EDMA_52 (44)
+#define INT1_HI_EDMA_53 (45)
+#define INT1_HI_EDMA_54 (46)
+#define INT1_HI_EDMA_55 (47)
+#define INT1_HI_UART4 (48)
+#define INT1_HI_UART5 (49)
+#define INT1_HI_UART6 (50)
+#define INT1_HI_UART7 (51)
+#define INT1_HI_UART8 (52)
+#define INT1_HI_UART9 (53)
+#define INT1_HI_DSPI1 (54)
+#define INT1_HI_DSPI2 (55)
+#define INT1_HI_DSPI3 (56)
+#define INT1_HI_I2C1 (57)
+#define INT1_HI_I2C2 (58)
+#define INT1_HI_I2C3 (59)
+#define INT1_HI_I2C4 (60)
+#define INT1_HI_I2C5 (61)
+
+#define INT2_LO_EDMA56_63 (0)
+#define INT2_LO_PWM_SM0SR_CF (1)
+#define INT2_LO_PWM_SM1SR_CF (2)
+#define INT2_LO_PWM_SM2SR_CF (3)
+#define INT2_LO_PWM_SM3SR_CF (4)
+#define INT2_LO_PWM_SM0SR_RF (5)
+#define INT2_LO_PWM_SM1SR_RF (6)
+#define INT2_LO_PWM_SM2SR_RF (7)
+#define INT2_LO_PWM_SM3SR_RF (8)
+#define INT2_LO_PWM_FSR (9)
+#define INT2_LO_PWM_SMSR_REF (10)
+#define INT2_LO_PLL_SR_LOCF (11)
+#define INT2_LO_PLL_SR_LOLF (12)
+#define INT2_LO_PIT0_PIF (13)
+#define INT2_LO_PIT1_PIF (14)
+#define INT2_LO_PIT2_PIF (15)
+#define INT2_LO_PIT3_PIF (16)
+#define INT2_LO_USBOTG_USBSTS (17)
+#define INT2_LO_USBH_USBSTS (18)
+/* not used 19-20 */
+#define INT2_LO_SSI0 (21)
+#define INT2_LO_SSI1 (22)
+#define INT2_LO_NFC (23)
+/* not used 24-25 */
+#define INT2_LO_RTC (26)
+#define INT2_LO_CCM_UOCSR (27)
+#define INT2_LO_RNG_EI (28)
+#define INT2_LO_SIM1_DATA (29)
+#define INT2_LO_SIM1 (30)
+#define INT2_LO_SDHC (31)
+/* not used 32-37 */
+#define INT2_HI_L2SW_BERR (38)
+#define INT2_HI_L2SW_RXB (39)
+#define INT2_HI_L2SW_RXF (40)
+#define INT2_HI_L2SW_TXB (41)
+#define INT2_HI_L2SW_TXF (42)
+#define INT2_HI_L2SW_QM (43)
+#define INT2_HI_L2SW_OD0 (44)
+#define INT2_HI_L2SW_OD1 (45)
+#define INT2_HI_L2SW_OD2 (46)
+#define INT2_HI_L2SW_LRN (47)
+#define INT2_HI_MACNET0_TS (48)
+#define INT2_HI_MACNET0_WAKE (49)
+#define INT2_HI_MACNET0_PLR (50)
+/* not used 51-54 */
+#define INT2_HI_MACNET1_TS (51)
+#define INT2_HI_MACNET1_WAKE (52)
+#define INT2_HI_MACNET1_PLR (53)
+
+/* Serial Boot Facility (SBF) */
+#define SBF_SBFCR_BLDIV(x) (((x)&0x000F))
+#define SBF_SBFCR_FR (0x0010)
+
+/* Reset Controller Module (RCM) */
+#define RCM_RCR_SOFTRST (0x80)
+#define RCM_RCR_FRCRSTOUT (0x40)
+
+#define RCM_RSR_SOFT (0x20)
+#define RCM_RSR_LOC (0x10)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_LOL (0x01)
+
+/* Chip Configuration Module (CCM) */
+#define CCM_CCR_BOOTMOD (0xC000)
+#define CCM_CCR_PLLMULT (0x0FC0)
+#define CCM_CCR_BOOTPS (0x0030)
+#define CCM_CCR_BOOTPS_32 (0x0000)
+#define CCM_CCR_BOOTPS_16 (0x0020)
+#define CCM_CCR_BOOTPS_8 (0x0010)
+#define CCM_CCR_BOOTPS_ (0x0000)
+#define CCM_CCR_ALESEL (0x0008)
+#define CCM_CCR_OSCMOD (0x0004)
+#define CCM_CCR_PLLMOD (0x0002)
+#define CCM_CCR_BOOTMEM (0x0001)
+
+#define CCM_CIR_PIN_MASK (0xFFC0)
+#define CCM_CIR_PRN_MASK (0x003F)
+#define CCM_CIR_PIN_MCF54410 (0x9F<<6)
+#define CCM_CIR_PIN_MCF54415 (0xA0<<6)
+#define CCM_CIR_PIN_MCF54416 (0xA1<<6)
+#define CCM_CIR_PIN_MCF54417 (0xA2<<6)
+#define CCM_CIR_PIN_MCF54418 (0xA3<<6)
+
+#define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
+#define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
+#define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
+#define CCM_MISCCR_LIMP (0x1000)
+#define CCM_MISCCR_BME (0x0800)
+#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
+#define CCM_MISCCR_BMT_65536 (0)
+#define CCM_MISCCR_BMT_32768 (1)
+#define CCM_MISCCR_BMT_16384 (2)
+#define CCM_MISCCR_BMT_8192 (3)
+#define CCM_MISCCR_BMT_4096 (4)
+#define CCM_MISCCR_BMT_2048 (5)
+#define CCM_MISCCR_BMT_1024 (6)
+#define CCM_MISCCR_BMT_512 (7)
+#define CCM_MISCCR_SDHCSRC (0x0040)
+#define CCM_MISCCR_SSI1SRC (0x0020)
+#define CCM_MISCCR_SSI0SRC (0x0010)
+#define CCM_MISCCR_USBHOC (0x0008)
+#define CCM_MISCCR_USBOOC (0x0004)
+#define CCM_MISCCR_USBPUE (0x0002)
+#define CCM_MISCCR_USBSRC (0x0001)
+
+#define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
+#define CCM_CDRH_SSI0DIV_MASK (0x00FF)
+#define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
+#define CCM_CDRH_SSI1DIV_MASK (0xFF00)
+#define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
+#define CCM_CDRL_LPDIV_MASK (0xFF0F)
+#define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
+
+#define CCM_UOCSR_DPPD (0x2000)
+#define CCM_UOCSR_DMPD (0x1000)
+#define CCM_UOCSR_DRV_VBUS (0x0800)
+#define CCM_UOCSR_CRG_VBUS (0x0400)
+#define CCM_UOCSR_DCR_VBUS (0x0200)
+#define CCM_UOCSR_DPPU (0x0100)
+#define CCM_UOCSR_AVLD (0x0080)
+#define CCM_UOCSR_BVLD (0x0040)
+#define CCM_UOCSR_VVLD (0x0020)
+#define CCM_UOCSR_SEND (0x0010)
+#define CCM_UOCSR_PWRFLT (0x0008)
+#define CCM_UOCSR_WKUP (0x0004)
+#define CCM_UOCSR_UOMIE (0x0002)
+#define CCM_UOCSR_XPDE (0x0001)
+
+#define CCM_UHCSR_DRV_VBUS (0x0010)
+#define CCM_UHCSR_PWRFLT (0x0008)
+#define CCM_UHCSR_WKUP (0x0004)
+#define CCM_UHCSR_UOMIE (0x0002)
+#define CCM_UHCSR_XPDE (0x0001)
+
+#define CCM_MISCCR3_TMR_ENET (0x1000)
+#define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8)
+#define CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
+#define CCM_MISCCR3_ENETCLK_MII (0x0700)
+#define CCM_MISCCR3_ENETCLK_OSC (0x0600)
+#define CCM_MISCCR3_ENETCLK_USB (0x0500)
+#define CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
+#define CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
+#define CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
+#define CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
+#define CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
+
+#define CCM_MISCCR2_EXTCLKBYP (0x8000)
+#define CCM_MISCCR2_DDR2CLK (0x4000)
+#define CCM_MISCCR2_RGPIO_HALF (0x2000)
+#define CCM_MISCCR2_SWTSCR (0x1000)
+#define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
+#define CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
+#define CCM_MISCCR2_DCCBYP (0x0080)
+#define CCM_MISCCR2_DAC1SEL (0x0040)
+#define CCM_MISCCR2_DAC0SEL (0x0020)
+#define CCM_MISCCR2_ADCEN (0x0010)
+#define CCM_MISCCR2_ADC7SEL (0x0008)
+#define CCM_MISCCR2_ADC3SEL (0x0004)
+#define CCM_MISCCR2_FBHALF (0x0002)
+#define CCM_MISCCR2_ULPI (0x0001)
+
+#define CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
+#define CCM_FNACR_PCR_MASK (0xF0FFFFFF)
+#define CCM_FNACR_MCC(x) ((x)&0xFFFF)
+#define CCM_FNACR_MCC_MASK (0xFFFF0000)
+
+/* General Purpose I/O Module (GPIO) */
+#define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
+#define GPIO_PAR_FBCTL_ALE_MASK (0x3F)
+#define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
+#define GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
+#define GPIO_PAR_FBCTL_ALE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
+#define GPIO_PAR_FBCTL_OE_MASK (0xCF)
+#define GPIO_PAR_FBCTL_OE_FB_OE (0x30)
+#define GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
+#define GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
+#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_FBCLK (0x08)
+#define GPIO_PAR_FBCTL_RW (0x04)
+#define GPIO_PAR_FBCTL_TA(x) ((x)&3)
+#define GPIO_PAR_FBCTL_TA_MASK (0xFC)
+#define GPIO_PAR_FBCTL_TA_TA (0x03)
+#define GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
+#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
+
+#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK (0x3F)
+#define GPIO_PAR_BE_BE3_BE3 (0xC0)
+#define GPIO_PAR_BE_BE3_CS3 (0x80)
+#define GPIO_PAR_BE_BE3_FB_A1 (0x40)
+#define GPIO_PAR_BE_BE3_NFC_ALE (0x40)
+#define GPIO_PAR_BE_BE3_GPIO (0x00)
+#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_BE_BE2_MASK (0xCF)
+#define GPIO_PAR_BE_BE2_BE2 (0x30)
+#define GPIO_PAR_BE_BE2_CS2 (0x20)
+#define GPIO_PAR_BE_BE2_FB_A0 (0x10)
+#define GPIO_PAR_BE_BE2_NFC_CLE (0x10)
+#define GPIO_PAR_BE_BE2_GPIO (0x00)
+#define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_BE_BE1_MASK (0xF3)
+#define GPIO_PAR_BE_BE1_BE1 (0x0C)
+#define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
+#define GPIO_PAR_BE_BE1_GPIO (0x00)
+#define GPIO_PAR_BE_BS0(x) ((x)&0x03)
+#define GPIO_PAR_BE_BE0_MASK (0xFC)
+#define GPIO_PAR_BE_BE0_BE0 (0x03)
+#define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
+#define GPIO_PAR_BE_BE0_GPIO (0x00)
+
+#define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
+#define GPIO_PAR_CS_CS5_MASK (0x3F)
+#define GPIO_PAR_CS_CS5_CS5 (0xC0)
+#define GPIO_PAR_CS_CS5_DACK1 (0x80)
+#define GPIO_PAR_CS_CS5_GPIO (0x00)
+#define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
+#define GPIO_PAR_CS_CS4_MASK (0xCF)
+#define GPIO_PAR_CS_CS4_CS4 (0x30)
+#define GPIO_PAR_CS_CS4_DREQ1 (0x20)
+#define GPIO_PAR_CS_CS4_GPIO (0x00)
+#define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_CS_CS1_MASK (0xF3)
+#define GPIO_PAR_CS_CS1_CS1 (0x0C)
+#define GPIO_PAR_CS_CS1_NFC_CE (0x04)
+#define GPIO_PAR_CS_CS1_GPIO (0x00)
+#define GPIO_PAR_CS_CS0_CS0 (0x01)
+
+#define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
+#define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
+#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
+#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
+#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
+#define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
+#define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
+#define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
+#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
+#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
+#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
+#define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
+#define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
+#define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
+#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
+#define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
+#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
+#define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
+#define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
+#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
+#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
+#define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
+
+#define GPIO_PAR_IRQH_IRQ7 (0x10)
+#define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
+#define GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
+#define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
+#define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
+#define GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
+#define GPIO_PAR_IRQH_IRQ1 (0x03)
+
+#define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
+#define GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
+#define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
+#define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
+#define GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
+#define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
+#define GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
+#define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
+#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
+#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
+#define GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
+#define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
+#define GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
+#define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
+#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
+#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
+#define GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
+
+#define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_DSPI0_SIN_MASK (0x3F)
+#define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
+#define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
+#define GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
+#define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
+#define GPIO_PAR_DSPI0_SIN_GPIO (0x00)
+#define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
+#define GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
+#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
+#define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
+#define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
+#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
+#define GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
+#define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
+#define GPIO_PAR_DSPI0_SCK_MASK (0xF3)
+#define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
+#define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
+#define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
+#define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
+#define GPIO_PAR_DSPI0_SCK_GPIO (0x00)
+#define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
+#define GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
+#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
+#define GPIO_PAR_DSPI0_PCS0_SS (0x03)
+#define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
+#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
+#define GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
+
+#define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
+#define GPIO_PAR_DSPIOW_SBF_CS (0x80)
+#define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
+#define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
+#define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
+#define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
+#define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
+
+#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
+#define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
+#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
+#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
+#define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
+#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
+#define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
+#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
+#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
+#define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
+#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
+#define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
+
+#define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART2_U2CTS_MASK (0x3F)
+#define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
+#define GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
+#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
+#define GPIO_PAR_UART2_U2CTS_GPIO (0x00)
+#define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART2_U2RTS_MASK (0xCF)
+#define GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
+#define GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
+#define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
+#define GPIO_PAR_UART2_U2RTS_GPIO (0x00)
+#define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART2_U2RXD_MASK (0xF3)
+#define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
+#define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
+#define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
+#define GPIO_PAR_UART2_U2RXD_GPIO (0x00)
+#define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART2_U2TXD_MASK (0xFC)
+#define GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
+#define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
+#define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
+#define GPIO_PAR_UART2_U2TXD_GPIO (0x00)
+
+#define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART1_U1CTS_MASK (0x3F)
+#define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
+#define GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
+#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
+#define GPIO_PAR_UART1_U1CTS_GPIO (0x00)
+#define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART1_U1RTS_MASK (0xCF)
+#define GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
+#define GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
+#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
+#define GPIO_PAR_UART1_U1RTS_GPIO (0x00)
+#define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART1_U1RXD_MASK (0xF3)
+#define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
+#define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
+#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
+#define GPIO_PAR_UART1_U1RXD_GPIO (0x00)
+#define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART1_U1TXD_MASK (0xFC)
+#define GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
+#define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
+#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
+#define GPIO_PAR_UART1_U1TXD_GPIO (0x00)
+
+#define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART0_U0CTS_MASK (0x3F)
+#define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
+#define GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
+#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
+#define GPIO_PAR_UART0_U0CTS_GPIO (0x00)
+#define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART0_U0RTS_MASK (0xCF)
+#define GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
+#define GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
+#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
+#define GPIO_PAR_UART0_U0RTS_GPIO (0x00)
+#define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART0_U0RXD_MASK (0xF3)
+#define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
+#define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
+#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
+#define GPIO_PAR_UART0_U0RXD_GPIO (0x00)
+#define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART0_U0TXD_MASK (0xFC)
+#define GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
+#define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
+#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
+#define GPIO_PAR_UART0_U0TXD_GPIO (0x00)
+
+#define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
+#define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
+#define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
+#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
+#define GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
+#define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
+#define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
+#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
+#define GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
+#define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
+#define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
+#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
+#define GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
+#define GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
+#define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
+#define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
+#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
+#define GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
+
+#define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCL_CMD_MASK (0xF3)
+#define GPIO_PAR_SDHCL_CMD_CMD (0x0C)
+#define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
+#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
+#define GPIO_PAR_SDHCL_CMD_GPIO (0x00)
+#define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
+#define GPIO_PAR_SDHCL_CLK_MASK (0xFC)
+#define GPIO_PAR_SDHCL_CLK_CLK (0x03)
+#define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
+#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
+#define GPIO_PAR_SDHCL_CLK_GPIO (0x00)
+
+#define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
+#define GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
+#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
+#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
+#define GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
+#define GPIO_PAR_SIMP0H_VEN_VEN (0x30)
+#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
+#define GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SIMP0H_RST_MASK (0xF3)
+#define GPIO_PAR_SIMP0H_RST_RST (0x0C)
+#define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
+#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
+#define GPIO_PAR_SIMP0H_RST_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
+#define GPIO_PAR_SIMP0H_PD_MASK (0xFC)
+#define GPIO_PAR_SIMP0H_PD_PD (0x03)
+#define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
+#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
+#define GPIO_PAR_SIMP0H_PD_GPIO (0x00)
+
+#define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
+#define GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
+#define GPIO_PAR_SIMP0L_CLK_CLK (0x03)
+#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
+#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
+#define GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
+
+#define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SSI0H_RXD_MASK (0x3F)
+#define GPIO_PAR_SSI0H_RXD_RXD (0xC0)
+#define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
+#define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
+#define GPIO_PAR_SSI0H_RXD_GPIO (0x00)
+#define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SSI0H_TXD_MASK (0xCF)
+#define GPIO_PAR_SSI0H_TXD_TXD (0x30)
+#define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
+#define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
+#define GPIO_PAR_SSI0H_TXD_GPIO (0x00)
+#define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SSI0H_FS_MASK (0xF3)
+#define GPIO_PAR_SSI0H_FS_FS (0x0C)
+#define GPIO_PAR_SSI0H_FS_U7TXD (0x08)
+#define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
+#define GPIO_PAR_SSI0H_FS_GPIO (0x00)
+#define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
+#define GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
+#define GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
+#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
+#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
+#define GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
+
+#define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
+#define GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
+#define GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
+#define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
+#define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
+#define GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
+
+#define GPIO_PAR_DEBUGH1_DAT3 (0x40)
+#define GPIO_PAR_DEBUGH1_DAT2 (0x10)
+#define GPIO_PAR_DEBUGH1_DAT1 (0x04)
+#define GPIO_PAR_DEBUGH1_DAT0 (0x01)
+
+#define GPIO_PAR_DEBUGH0_PST3 (0x40)
+#define GPIO_PAR_DEBUGH0_PST2 (0x10)
+#define GPIO_PAR_DEBUGH0_PST1 (0x04)
+#define GPIO_PAR_DEBUGH0_PST0 (0x01)
+
+#define GPIO_PODR_G4_VAL (0x01 << 4)
+#define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL)
+#define GPIO_PDDR_G4_OUTPUT (0x01 << 4)
+#define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT)
+
+#define GPIO_PAR_DEBUGL_ALLPST (0x01)
+
+#define GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
+#define GPIO_PAR_FEC_FEC_MASK (0xF0)
+#define GPIO_PAR_FEC_FEC_GPIO (0x0D)
+#define GPIO_PAR_FEC_FEC_RMII1 (0x0C)
+#define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
+#define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
+#define GPIO_PAR_FEC_FEC_RMII0 (0x09)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
+#define GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
+#define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
+/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
+#define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
+#define GPIO_PAR_FEC_FEC_MIIFUL (0x00)
+
+
+/* TC: Need to edit here.... */
+
+/* Mode Select Control */
+#define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03)
+#define GPIO_MSCR_SDRAM_MSC_MASK (0xFC)
+
+/* Slew Rate Control */
+
+#define GPIO_SRCR_FB3_FB3(x) ((x)&0x03)
+#define GPIO_SRCR_FB3_FB3_MASK (0xFC)
+
+#define GPIO_SRCR_FB2_FB2(x) ((x)&0x03)
+#define GPIO_SRCR_FB2_FB2_MASK (0xFC)
+
+#define GPIO_SRCR_FB1_FB1(x) ((x)&0x03)
+#define GPIO_SRCR_FB1_FB1_MASK (0xFC)
+
+#define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_FB4_FB5_MASK (0xF3)
+#define GPIO_SRCR_FB4_FB4(x) ((x)&0x03)
+#define GPIO_SRCR_FB4_FB4_MASK (0xFC)
+
+#define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF)
+#define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03)
+#define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC)
+
+#define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3)
+#define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03)
+#define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC)
+
+#define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03)
+#define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC)
+
+#define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6)
+#define GPIO_SRCR_TIMER_TMR3_MASK (0x3F)
+#define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_TIMER_TMR2_MASK (0xCF)
+#define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_TIMER_TMR1_MASK (0xF3)
+#define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03)
+#define GPIO_SRCR_TIMER_TMR0_MASK (0xFC)
+
+#define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_UART_U2_MASK (0xCF)
+#define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_UART_U1_MASK (0xF3)
+#define GPIO_SRCR_UART_U0(x) ((x)&0x03)
+#define GPIO_SRCR_UART_U0_MASK (0xFC)
+
+#define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_FEC_RMII0_MASK (0xF3)
+#define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03)
+#define GPIO_SRCR_FEC_RMII1_MASK (0xFC)
+
+#define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03)
+#define GPIO_SRCR_SDHC_SDHC_MASK (0xFC)
+
+#define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03)
+#define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC)
+
+#define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03)
+#define GPIO_SRCR_SSI0_SSI0_MASK (0xFC)
+
+#define GPIO_PCR_URTS_U2 (0x0004)
+#define GPIO_PCR_URTS_U1 (0x0002)
+#define GPIO_PCR_URTS_U0 (0x0001)
+
+#define GPIO_PCR_UCTS_U2 (0x0004)
+#define GPIO_PCR_UCTS_U1 (0x0002)
+#define GPIO_PCR_UCTS_U0 (0x0001)
+
+#define GPIO_UTXD_WOM_U9 (0x0200)
+#define GPIO_UTXD_WOM_U8 (0x0100)
+#define GPIO_UTXD_WOM_U7 (0x0080)
+#define GPIO_UTXD_WOM_U6 (0x0040)
+#define GPIO_UTXD_WOM_U5 (0x0020)
+#define GPIO_UTXD_WOM_U4 (0x0010)
+#define GPIO_UTXD_WOM_U3 (0x0008)
+#define GPIO_UTXD_WOM_U2 (0x0004)
+#define GPIO_UTXD_WOM_U1 (0x0002)
+#define GPIO_UTXD_WOM_U0 (0x0001)
+
+#define GPIO_URXD_WOM_U9(x) (((x)&3)<<18)
+#define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF)
+#define GPIO_URXD_WOM_U8(x) (((x)&3)<<16)
+#define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF)
+#define GPIO_URXD_WOM_U7(x) (((x)&3)<<14)
+#define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF)
+#define GPIO_URXD_WOM_U6(x) (((x)&3)<<12)
+#define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF)
+#define GPIO_URXD_WOM_U5(x) (((x)&3)<<10)
+#define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF)
+#define GPIO_URXD_WOM_U4(x) (((x)&3)<<8)
+#define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF)
+#define GPIO_URXD_WOM_U3(x) (((x)&3)<<6)
+#define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F)
+#define GPIO_URXD_WOM_U2(x) (((x)&3)<<4)
+#define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF)
+#define GPIO_URXD_WOM_U1(x) (((x)&3)<<2)
+#define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3)
+#define GPIO_URXD_WOM_U0(x) ((x)&3)
+#define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC)
+
+#define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27)
+#define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF)
+#define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22)
+#define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF)
+#define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15)
+#define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF)
+#define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10)
+#define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF)
+#define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3)
+#define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07)
+#define GPIO_HCR1_PB2_0(x) ((x)&7)
+#define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8)
+
+#define GPIO_HCR0_PK3 (0x00000400)
+#define GPIO_HCR0_PK0 (0x00000200)
+#define GPIO_HCR0_PD2_0(x) (((x)&7)<<6)
+#define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F)
+#define GPIO_HCR0_PE7 (0x00000020)
+#define GPIO_HCR0_PH7_3(x) ((x)&0x1F)
+#define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0)
+
+/* SDRAM Controller (SDRAMC) */
+
+/* Phase Locked Loop (PLL) */
+#define PLL_CR_LOCIRQ (0x00040000)
+#define PLL_CR_LOCRE (0x00020000)
+#define PLL_CR_LOCEN (0x00010000)
+#define PLL_CR_LOLIRQ (0x00004000)
+#define PLL_CR_LOLRE (0x00002000)
+#define PLL_CR_LOLEN (0x00001000)
+#define PLL_CR_REFDIV(x) (((x)&7)<<8)
+#define PLL_CR_REFDIV_MASK (0xFFFFF8FF)
+#define PLL_CR_FBKDIV(x) ((x)&0x3F)
+#define PLL_CR_FBKDIV_MASK (0xFFFFFFC0)
+#define PLL_CR_FBKDIV_BITS (0x3F)
+
+#define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21)
+#define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF)
+#define PLL_DR_OUTDIV5_BITS (0x03E00000)
+#define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16)
+#define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF)
+#define PLL_DR_OUTDIV4_BITS (0x001F0000)
+#define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10)
+#define PLL_DR_OUTDIV3_MASK (0xFFFF83FF)
+#define PLL_DR_OUTDIV3_BITS (0x00007C00)
+#define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5)
+#define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F)
+#define PLL_DR_OUTDIV2_BITS (0x000003E0)
+#define PLL_DR_OUTDIV1(x) ((x)&0x1F)
+#define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0)
+#define PLL_DR_OUTDIV1_BITS (0x0000001F)
+
+#define PLL_SR_LOCF (0x00000200)
+#define PLL_SR_LOC (0x00000100)
+#define PLL_SR_LOLF (0x00000040)
+#define PLL_SR_LOCKS (0x00000020)
+#define PLL_SR_LOCK (0x00000010)
+#define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */
+#define PLL_SR_MODE(x) ((x)&7)
+#define PLL_SR_MODE_MASK (0xFFFFFFF8)
+
+#endif /* __MCF5441X__ */
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
+#include <linux/compiler.h>
#include <asm/immap.h>
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
- char *s;
+ char *s __maybe_unused;
bd_t *bd;
#ifndef CONFIG_ENV_IS_NOWHERE
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
__data_end = .;
}
- .u_boot_cmd ALIGN(0x4):
- {
- . = .;
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
.bss ALIGN(0x4):
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
LIB = $(obj)lib$(SOC).o
-COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
+ * (C) Copyright 2000-2011
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
- *
* See file CREDITS for list of people who contributed to this
* project.
*
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
*/
-#ifndef __M48_T59_Y_H
-#define __M48_T59_Y_H
-
-/*
- * M48 T59Y -Timekeeping Battery backed SRAM.
- */
-
-int m48_tod_init(void);
-
-int m48_tod_set(int year,
- int month,
- int day,
- int hour,
- int minute,
- int second);
-
-int m48_tod_get(int *year,
- int *month,
- int *day,
- int *hour,
- int *minute,
- int *second);
-
-int m48_tod_get_second(void);
-
-void m48_watchdog_arm(int usec);
+#include <common.h>
+#include <ide.h>
-#endif /*!__M48_T59_Y_H */
+/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ ide_input_data(dev, sect_buf, words);
+}
*uart_tx = (u32)c;
}
-static void au1x00_serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
static int au1x00_serial_getc(void)
{
volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
.stop = NULL,
.setbrg = au1x00_serial_setbrg,
.putc = au1x00_serial_putc,
- .puts = au1x00_serial_puts,
+ .puts = default_serial_puts,
.getc = au1x00_serial_getc,
.tstc = au1x00_serial_tstc,
};
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
-2: cache_op Fill t0
+2: cache_op FILL t0
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
return;
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
}
}
-static void asc_serial_puts(const char *s)
-{
- while (*s)
- {
- serial_putc (*s++);
- }
-}
-
static int asc_serial_getc(void)
{
ulong symbol_mask;
.stop = NULL,
.setbrg = asc_serial_setbrg,
.putc = asc_serial_putc,
- .puts = asc_serial_puts,
+ .puts = default_serial_puts,
.getc = asc_serial_getc,
.tstc = asc_serial_tstc,
};
--- /dev/null
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+COBJS-y = cpu.o interrupts.o time.o cache.o
+
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
--- /dev/null
+/*
+ * Cache-handling routined for MIPS CPUs
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#define RA t9
+
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE 0x10000
+
+#define INDEX_BASE CKSEG0
+
+ .macro cache_op op addr
+ .set push
+ .set noreorder
+ .set mips3
+ cache \op, 0(\addr)
+ .set pop
+ .endm
+
+ .macro f_fill64 dst, offset, val
+ LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+ LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+ .endm
+
+/*
+ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
+ */
+LEAF(mips_init_icache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear tag to invalidate */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* fill once, so data field parity is correct */
+ PTR_LI t0, INDEX_BASE
+2: cache_op FILL t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* invalidate again - prudent but not strictly neccessary */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_icache)
+
+/*
+ * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
+ */
+LEAF(mips_init_dcache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* load from each line (in cached space) */
+ PTR_LI t0, INDEX_BASE
+2: LONG_L zero, 0(t0)
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_dcache)
+
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity. It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
+NESTED(mips_cache_reset, 0, ra)
+ move RA, ra
+ li t2, CONFIG_SYS_ICACHE_SIZE
+ li t3, CONFIG_SYS_DCACHE_SIZE
+ li t8, CONFIG_SYS_CACHELINE_SIZE
+
+ li v0, MIPS_MAX_CACHE_SIZE
+
+ /*
+ * Now clear that much memory starting from zero.
+ */
+ PTR_LI a0, CKSEG1
+ PTR_ADDU a1, a0, v0
+2: PTR_ADDIU a0, 64
+ f_fill64 a0, -64, zero
+ bne a0, a1, 2b
+
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
+
+ /*
+ * Assume bottom of RAM will generate good parity for the cache.
+ */
+
+ /*
+ * Initialize the I-cache first,
+ */
+ move a1, t2
+ move a2, t8
+ PTR_LA v1, mips_init_icache
+ jalr v1
+
+ /*
+ * then initialize D-cache.
+ */
+ move a1, t3
+ move a2, t8
+ PTR_LA v1, mips_init_dcache
+ jalr v1
+
+ jr RA
+ END(mips_cache_reset)
+
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
+LEAF(dcache_status)
+ mfc0 t0, CP0_CONFIG
+ li t1, CONF_CM_UNCACHED
+ andi t0, t0, CONF_CM_CMASK
+ move v0, zero
+ beq t0, t1, 2f
+ li v0, 1
+2: jr ra
+ END(dcache_status)
+
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_disable)
+ mfc0 t0, CP0_CONFIG
+ li t1, -8
+ and t0, t0, t1
+ ori t0, t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_disable)
+
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_enable)
+ mfc0 t0, CP0_CONFIG
+ ori t0, CONF_CM_CMASK
+ xori t0, CONF_CM_CMASK
+ ori t0, CONF_CM_CACHABLE_NONCOHERENT
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_enable)
--- /dev/null
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Default optimization level for MIPS64
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips64
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS += -m elf64btsmip
+else
+PLATFORM_LDFLAGS += -m elf64ltsmip
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op, addr) \
+ __asm__ __volatile__( \
+ " .set push\n" \
+ " .set noreorder\n" \
+ " .set mips64\n" \
+ " cache %0, %1\n" \
+ " .set pop\n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+ fprintf(stderr, "*** reset failed ***\n");
+
+ while (1)
+ /* NOP */;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_INVALIDATE_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * Startup Code for MIPS64 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+ /*
+ * For the moment disable interrupts, mark the kernel mode and
+ * set ST0_KX so that the CPU does not spit fire when using
+ * 64-bit addresses.
+ */
+ .macro setup_c0_status set clr
+ .set push
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_CU0 | \set | 0x1f | \clr
+ xor t0, 0x1f | \clr
+ mtc0 t0, CP0_STATUS
+ .set noreorder
+ sll zero, 3 # ehb
+ .set pop
+ .endm
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .org 0x000
+ b reset
+ nop
+ .org 0x080
+ b romReserved
+ nop
+ .org 0x100
+ b romReserved
+ nop
+ .org 0x180
+ b romReserved
+ nop
+ .org 0x200
+ b romReserved
+ nop
+ .org 0x280
+ b romReserved
+ nop
+ .org 0x300
+ b romReserved
+ nop
+ .org 0x380
+ b romReserved
+ nop
+ .org 0x480
+ b romReserved
+ nop
+
+ /*
+ * We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+ .org 0x500
+ .align 4
+reset:
+
+ /* Clear watch registers */
+ dmtc0 zero, CP0_WATCHLO
+ dmtc0 zero, CP0_WATCHHI
+
+ /* WP(Watch Pending), SW0/1 should be cleared */
+ mtc0 zero, CP0_CAUSE
+
+ setup_c0_status ST0_KX 0
+
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* CONFIG0 register */
+ dli t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Initialize $gp */
+ bal 1f
+ nop
+ .dword _gp
+1:
+ ld gp, 0(ra)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
+ dla t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* Initialize caches... */
+ dla t9, mips_cache_reset
+ jalr t9
+ nop
+
+ /* ... and enable them */
+ dli t0, CONFIG_SYS_MIPS_CACHE_MODE
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Set up temporary stack */
+ dli t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ dla sp, 0(t0)
+
+ dla t9, board_init_f
+ jr t9
+ nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl relocate_code
+ .ent relocate_code
+relocate_code:
+ move sp, a0 # set new stack pointer
+
+ dli t0, CONFIG_SYS_MONITOR_BASE
+ dla t3, in_ram
+ ld t2, -24(t3) # t2 <-- uboot_end_data
+ move t1, a2
+ move s2, a2 # s2 <-- destination address
+
+ /*
+ * Fix $gp:
+ *
+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+ */
+ move t8, gp
+ dsub gp, CONFIG_SYS_MONITOR_BASE
+ dadd gp, a2 # gp now adjusted
+ dsub s1, gp, t8 # s1 <-- relocation offset
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+
+ /*
+ * Save destination address and size for dlater usage in flush_cache()
+ */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ dsub a1, t2, t0 # a1 <-- size
+
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ daddu t0, 4
+ ble t0, t2, 1b
+ daddu t1, 4
+
+ /* If caches were enabled, we would have to flush them here. */
+
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ dla t9, flush_cache
+ jalr t9
+ nop
+
+ /* Jump to where we've relocated ourselves */
+ daddi t0, s2, in_ram - _start
+ jr t0
+ nop
+
+ .dword _gp
+ .dword _GLOBAL_OFFSET_TABLE_
+ .dword uboot_end_data
+ .dword uboot_end
+ .dword num_got_entries
+
+in_ram:
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+ ld t3, -8(t0) # t3 <-- num_got_entries
+ ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ ld t9, -40(t0) # t9 <-- _gp
+ dsub t8, t9 # compute offset
+ dadd t8, t8, gp # t8 now holds relocated _G_O_T_
+ daddi t8, t8, 16 # skipping first two entries
+ dli t2, 2
+1:
+ ld t1, 0(t8)
+ beqz t1, 2f
+ dadd t1, s1
+ sd t1, 0(t8)
+2:
+ daddi t2, 1
+ blt t2, t3, 1b
+ daddi t8, 8
+
+ /* Clear BSS */
+ ld t1, -24(t0) # t1 <-- uboot_end_data
+ ld t2, -16(t0) # t2 <-- uboot_end
+ dadd t1, s1 # adjust pointers
+ dadd t2, s1
+
+ dsub t1, 8
+1:
+ daddi t1, 8
+ bltl t1, t2, 1b
+ sd zero, 0(t1)
+
+ move a0, s0 # a0 <-- gd
+ dla t9, board_init_r
+ jr t9
+ move a1, s2
+
+ .end relocate_code
+
+ /* Exception handlers */
+romReserved:
+ b romReserved
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY \
+ (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) < 0x7fffffff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return timestamp - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+ while ((tmo - read_c0_count()) < 0x7fffffff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
}
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
void flush_icache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Store_Tag_I, addr);
+ cache_op(INDEX_STORE_TAG_I, addr);
}
/* invalidate btb */
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Writeback_Inv_D, addr);
+ cache_op(INDEX_WRITEBACK_INV_D, addr);
}
__asm__ __volatile__("sync");
return readb(&uart->rbr_thr_dllr);
}
-static void jz_serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
static struct serial_device jz_serial_drv = {
.name = "jz_serial",
.start = jz_serial_init,
.stop = NULL,
.setbrg = jz_serial_setbrg,
.putc = jz_serial_putc,
- .puts = jz_serial_puts,
+ .puts = default_serial_puts,
.getc = jz_serial_getc,
.tstc = jz_serial_tstc,
};
li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2:
- cache Index_Writeback_Inv_D, 0(t0)
+ cache INDEX_WRITEBACK_INV_D, 0(t0)
bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE
li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3:
- cache Index_Invalidate_I, 0(t0)
+ cache INDEX_INVALIDATE_I, 0(t0)
bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
-#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
+#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
#else
#define R10KCBARRIER(addr)
#endif
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
+#define INDEX_INVALIDATE_I 0x00
+#define INDEX_WRITEBACK_INV_D 0x01
+#define INDEX_LOAD_TAG_I 0x04
+#define INDEX_LOAD_TAG_D 0x05
+#define INDEX_STORE_TAG_I 0x08
+#define INDEX_STORE_TAG_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I 0x00
+#define HIT_INVALIDATE_I 0x00
#else
-#define Hit_Invalidate_I 0x10
+#define HIT_INVALIDATE_I 0x10
#endif
-#define Hit_Invalidate_D 0x11
-#define Hit_Writeback_Inv_D 0x15
+#define HIT_INVALIDATE_D 0x11
+#define HIT_WRITEBACK_INV_D 0x15
/*
* R4000-specific cacheops
*/
-#define Create_Dirty_Excl_D 0x0d
-#define Fill 0x14
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
+#define CREATE_DIRTY_EXCL_D 0x0d
+#define FILL 0x14
+#define HIT_WRITEBACK_I 0x18
+#define HIT_WRITEBACK_D 0x19
/*
* R4000SC and R4400SC-specific cacheops
*/
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_SD 0x1b
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
+#define INDEX_INVALIDATE_SI 0x02
+#define INDEX_WRITEBACK_INV_SD 0x03
+#define INDEX_LOAD_TAG_SI 0x06
+#define INDEX_LOAD_TAG_SD 0x07
+#define INDEX_STORE_TAG_SI 0x0A
+#define INDEX_STORE_TAG_SD 0x0B
+#define CREATE_DIRTY_EXCL_SD 0x0f
+#define HIT_INVALIDATE_SI 0x12
+#define HIT_INVALIDATE_SD 0x13
+#define HIT_WRITEBACK_INV_SD 0x17
+#define HIT_WRITEBACK_SD 0x1b
+#define HIT_SET_VIRTUAL_SI 0x1e
+#define HIT_SET_VIRTUAL_SD 0x1f
/*
* R5000-specific cacheops
*/
-#define R5K_Page_Invalidate_S 0x17
+#define R5K_PAGE_INVALIDATE_S 0x17
/*
* RM7000-specific cacheops
*/
-#define Page_Invalidate_T 0x16
+#define PAGE_INVALIDATE_T 0x16
/*
* R10000-specific cacheops
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
-#define Index_Writeback_Inv_S 0x03
-#define Index_Load_Tag_S 0x07
-#define Index_Store_Tag_S 0x0B
-#define Hit_Invalidate_S 0x13
-#define Cache_Barrier 0x14
-#define Hit_Writeback_Inv_S 0x17
-#define Index_Load_Data_I 0x18
-#define Index_Load_Data_D 0x19
-#define Index_Load_Data_S 0x1b
-#define Index_Store_Data_I 0x1c
-#define Index_Store_Data_D 0x1d
-#define Index_Store_Data_S 0x1f
+#define INDEX_WRITEBACK_INV_S 0x03
+#define INDEX_LOAD_TAG_S 0x07
+#define INDEX_STORE_TAG_S 0x0B
+#define HIT_INVALIDATE_S 0x13
+#define CACHE_BARRIER 0x14
+#define HIT_WRITEBACK_INV_S 0x17
+#define INDEX_LOAD_DATA_I 0x18
+#define INDEX_LOAD_DATA_D 0x19
+#define INDEX_LOAD_DATA_S 0x1b
+#define INDEX_STORE_DATA_I 0x1c
+#define INDEX_STORE_DATA_D 0x1d
+#define INDEX_STORE_DATA_S 0x1f
#endif /* __ASM_CACHEOPS_H */
unsigned long tbl;
unsigned long lastinc;
#endif
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
typedef int __kernel_ipc_pid_t;
typedef int __kernel_uid_t;
typedef int __kernel_gid_t;
+#if _MIPS_SZLONG != 64
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
}
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long reloc_off; /* Relocation Offset */
#include <environment.h>
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
serial_initialize();
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
#define _U_BOOT_H_
typedef struct bd_info {
- unsigned long bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#endif
}
-static void mpc5xx_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s);
- ++s;
- }
-}
-
static struct serial_device mpc5xx_serial_drv = {
.name = "mpc5xx_serial",
.start = mpc5xx_serial_init,
.stop = NULL,
.setbrg = mpc5xx_serial_setbrg,
.putc = mpc5xx_serial_putc,
- .puts = mpc5xx_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc5xx_serial_getc,
.tstc = mpc5xx_serial_tstc,
};
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
psc->xmitbuf[0] = c;
}
-static void mpc8220_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc8220_serial_getc(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
.stop = NULL,
.setbrg = mpc8220_serial_setbrg,
.putc = mpc8220_serial_putc,
- .puts = mpc8220_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc8220_serial_getc,
.tstc = mpc8220_serial_tstc,
};
cpu_init_f (void)
{
/* MOUSSE board is initialized in asm */
-#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
+#if !defined(CONFIG_MOUSSE)
register unsigned long val;
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
__asm__ __volatile__("eieio");
-#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
+#endif /* !CONFIG_MOUSSE */
}
in_flash:
-#if defined(CONFIG_BMW)
- bl early_init_f /* Must be ASM: no stack yet! */
-#endif
/*
* Setup BATs - cannot be done in C since we don't have a stack yet
*/
mfmsr r3
ori r3, r3, (MSR_IR | MSR_DR)
mtmsr r3
-#if !defined(CONFIG_BMW)
+
/* Enable and invalidate data cache.
*/
mfspr r3, HID0
ori r3, r3, 0x0080
sync
mtspr 1011, r3
-#endif /* !CONFIG_BMW */
+
/*
* Thisk the stack pointer *somewhere* sensible. Doesnt
* matter much where as we'll move it when we relocate
bdnz 3b
4:
-#if !defined(CONFIG_BMW)
/* Unlock the data cache and invalidate locked area */
xor r0, r0, r0
mtspr 1011, r0
dcbi r0, r4
addi r4, r4, 32
bdnz 41b
-#endif
/*
* Now flush the cache: note that we must start from a cache aligned
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
tbdf->cbd_sc |= BD_SC_READY;
}
-static void mpc8260_scc_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc8260_scc_serial_getc(void)
{
volatile cbd_t *rbdf;
.stop = NULL,
.setbrg = mpc8260_scc_serial_setbrg,
.putc = mpc8260_scc_serial_putc,
- .puts = mpc8260_scc_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc8260_scc_serial_getc,
.tstc = mpc8260_scc_serial_tstc,
};
rtx->txbd.cbd_sc |= BD_SC_READY;
}
-static void mpc8260_smc_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc8260_smc_serial_getc(void)
{
volatile smc_uart_t *up;
.stop = NULL,
.setbrg = mpc8260_smc_serial_setbrg,
.putc = mpc8260_smc_serial_putc,
- .puts = mpc8260_smc_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc8260_smc_serial_getc,
.tstc = mpc8260_smc_serial_tstc,
};
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
u32 partid;
} cpu_type_list [] = {
CPU_TYPE_ENTRY(8308),
+ CPU_TYPE_ENTRY(8309),
CPU_TYPE_ENTRY(8311),
CPU_TYPE_ENTRY(8313),
CPU_TYPE_ENTRY(8314),
#ifdef CONFIG_SYS_SICRL
__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
#endif
+#ifdef CONFIG_SYS_GPR1
+ __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
#endif
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ u32 usbdr_clk;
#endif
#ifdef CONFIG_MPC834x
u32 usbmph_clk;
#if defined(CONFIG_FSL_ESDHC)
u32 sdhc_clk;
#endif
+#if !defined(CONFIG_MPC8309)
u32 enc_clk;
+#endif
u32 lbiu_clk;
u32 lclk_clk;
u32 mem_clk;
#if defined(CONFIG_MPC8360)
u32 mem_sec_clk;
#endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
u32 qepmf;
u32 qepdf;
u32 qe_clk;
/* unkown SCCR_TSEC1CM value */
return -2;
}
+#endif
+#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
+ defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
usbdr_clk = 0;
return -6;
}
#endif
+#if !defined(CONFIG_MPC8309)
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
enc_clk = 0;
/* unkown SCCR_ENCCM value */
return -7;
}
+#endif
#if defined(CONFIG_FSL_ESDHC)
switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
i2c1_clk = sdhc_clk;
#elif defined(CONFIG_MPC837x)
i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC8309)
+ i2c1_clk = csb_clk;
#endif
#if !defined(CONFIG_MPC832x)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
return -13;
}
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ gd->usbdr_clk = usbdr_clk;
#endif
#if defined(CONFIG_MPC834x)
gd->usbmph_clk = usbmph_clk;
#if !defined(CONFIG_MPC832x)
gd->i2c2_clk = i2c2_clk;
#endif
+#if !defined(CONFIG_MPC8309)
gd->enc_clk = enc_clk;
+#endif
gd->lbiu_clk = lbiu_clk;
gd->lclk_clk = lclk_clk;
gd->mem_clk = mem_clk;
#if defined(CONFIG_MPC8360)
gd->mem_sec_clk = mem_sec_clk;
#endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
#endif
printf("Clock configuration:\n");
printf(" Core: %-4s MHz\n", strmhz(buf, gd->core_clk));
printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
printf(" QE: %-4s MHz\n", strmhz(buf, gd->qe_clk));
printf(" BRG: %-4s MHz\n", strmhz(buf, gd->brg_clk));
#endif
#if defined(CONFIG_MPC8360)
printf(" DDR Secondary: %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
#endif
+#if !defined(CONFIG_MPC8309)
printf(" SEC: %-4s MHz\n", strmhz(buf, gd->enc_clk));
+#endif
printf(" I2C1: %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
#if !defined(CONFIG_MPC832x)
printf(" I2C2: %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
printf(" TSEC1: %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
printf(" TSEC2: %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+#elif defined(CONFIG_MPC8309)
+ printf(" USB DR: %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
#endif
#if defined(CONFIG_MPC834x)
printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o
COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
COBJS-$(CONFIG_QE) += qe_io.o
COBJS-$(CONFIG_CPM2) += serial_scc.o
-COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
COBJS = $(COBJS-y)
COBJS += cpu.o
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 27, 1, 0),
+ SET_QP_INFO(2, 28, 1, 0),
+ SET_QP_INFO(3, 29, 1, 1),
+ SET_QP_INFO(4, 30, 1, 1),
+ SET_QP_INFO(5, 31, 1, 2),
+ SET_QP_INFO(6, 32, 1, 2),
+ SET_QP_INFO(7, 33, 1, 3),
+ SET_QP_INFO(8, 34, 1, 3),
+ SET_QP_INFO(9, 35, 1, 0),
+ SET_QP_INFO(10, 36, 1, 0),
+ SET_QP_INFO(11, 37, 1, 1),
+ SET_QP_INFO(12, 38, 1, 1),
+ SET_QP_INFO(13, 39, 1, 2),
+ SET_QP_INFO(14, 40, 1, 2),
+ SET_QP_INFO(15, 41, 1, 3),
+ SET_QP_INFO(16, 42, 1, 3),
+ SET_QP_INFO(17, 43, 1, 0),
+ SET_QP_INFO(18, 44, 1, 0),
+ SET_QP_INFO(19, 45, 1, 1),
+ SET_QP_INFO(20, 46, 1, 1),
+ SET_QP_INFO(21, 47, 1, 2),
+ SET_QP_INFO(22, 48, 1, 2),
+ SET_QP_INFO(23, 49, 1, 3),
+ SET_QP_INFO(24, 50, 1, 3),
+ SET_QP_INFO(25, 51, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+ SET_SRIO_LIODN_1(1, 307),
+ SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(62),
+ SET_BMAN_LIODN(63),
+#endif
+
+ SET_SDHC_LIODN(1, 552),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+
+ SET_DMA_LIODN(1, 147),
+ SET_DMA_LIODN(2, 227),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+ /* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_1G_LIODN(1, 1, 89),
+ SET_FMAN_RX_1G_LIODN(1, 2, 90),
+ SET_FMAN_RX_1G_LIODN(1, 3, 91),
+ SET_FMAN_RX_1G_LIODN(1, 4, 92),
+ SET_FMAN_RX_1G_LIODN(1, 5, 93),
+ SET_FMAN_RX_10G_LIODN(1, 0, 94),
+ SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+ SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+ SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+ SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+ SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+ SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+ SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+ SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+ SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+ SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+ SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+ SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+ /* Set RMan block 0-3 liodn offset */
+ SET_RMAN_LIODN(0, 678),
+ SET_RMAN_LIODN(1, 679),
+ SET_RMAN_LIODN(2, 680),
+ SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+ u8 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x30, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x32, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x33, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x34, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1}},
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ AURORA, AURORA, SRIO1, SRIO1}},
+ {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ AURORA, AURORA, SRIO1, SRIO1}},
+ {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ AURORA, AURORA, SRIO1, SRIO1}},
+ {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ AURORA, AURORA,
+ SRIO1, SRIO1}},
+ {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2, AURORA, AURORA,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2, AURORA, AURORA,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SRIO2, SRIO2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {0x9A, {PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XFI_FM1_MAC9, XFI_FM1_MAC10}},
+ {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
puts("Work-around for Erratum ESDHC111 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+ puts("Work-around for Erratum A004468 enabled\n");
+#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
puts("Work-around for Erratum ESDHC135 enabled\n");
#endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
- puts("Work-around for Erratum ESDHC136 enabled\n");
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
+ if (SVR_MAJ(svr) < 3)
+ puts("Work-around for Erratum ESDHC13 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
puts("Work-around for Erratum ESDHC-A001 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts("Work-around for Erratum A004510 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+ puts("Work-around for Erratum SRIO-A004034 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+ puts("Work-around for Erratum A004934 enabled\n");
#endif
return 0;
}
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if (defined(CONFIG_DDR_CLK_FREQ) || \
+ defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
- u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
- >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#else
+
+ /*
+ * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
+ * mode. Previous platform use ddr ratio to do the same. This
+ * information is only for display here.
+ */
#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ u32 ddr_sync = 0; /* only async mode is supported */
+#else
u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#else /* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
+ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+ >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
u32 ddr_ratio = 0;
-#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_FSL_CORENET */
+
unsigned int i, core, nr_cores = cpu_numcores();
u32 mask = cpu_mask();
printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
+ if (nr_cores > CONFIG_MAX_CPUS) {
+ panic("\nUnexpected number of cores: %d, max is %d\n",
+ nr_cores, CONFIG_MAX_CPUS);
+ }
+
get_sys_info(&sysinfo);
puts("Clock Configuration:");
}
#endif
+#if defined(CONFIG_FSL_IFC)
+ printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+#endif
+
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif
}
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
+#endif
+
#ifdef CONFIG_SYS_DPAA_PME
printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
#endif
/*
* Clear TSR(WIS) bit by writing 1
*/
- unsigned long val;
- val = mfspr(SPRN_TSR);
- val |= TSR_WIS;
- mtspr(SPRN_TSR, val);
+ mtspr(SPRN_TSR, TSR_WIS);
}
#endif /* CONFIG_WATCHDOG */
}
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int enable_cluster_l2(void)
+{
+ int i = 0;
+ u32 cluster;
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct ccsr_cluster_l2 __iomem *l2cache;
+
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+ if (cluster & TP_CLUSTER_EOC)
+ return 0;
+
+ /* The first cache has already been set up, so skip it */
+ i++;
+
+ /* Look through the remaining clusters, and set up their caches */
+ do {
+ l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+ cluster = in_be32(&gur->tp_cluster[i].lower);
+
+ /* set stash ID to (cluster) * 2 + 32 + 1 */
+ clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+
+ printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+ out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+ while ((in_be32(&l2cache->l2csr0) &
+ (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+ ;
+ out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+ i++;
+ } while (!(cluster & TP_CLUSTER_EOC));
+
+ return 0;
+}
+#endif
+
/*
* Initialize L2 as cache.
*
{
__maybe_unused u32 svr = get_svr();
#ifdef CONFIG_SYS_LBC_LCRR
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
+#endif
+#ifdef CONFIG_L2_CACHE
+ ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+ struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
- volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
volatile uint cache_ctl;
uint ver;
u32 l2siz_field;
}
skip_l2:
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+ if (l2cache->l2csr0 & L2CSR0_L2E)
+ printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
+
+ enable_cluster_l2();
#else
puts("disabled\n");
#endif
#ifdef CONFIG_SYS_SRIO
srio_init();
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
char *s = getenv("bootmaster");
if (s) {
if (!strcmp(s, "SRIO1")) {
setup_mp();
#endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
{
- void *p;
- p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
- setbits_be32(p, 1 << (31 - 14));
+ if (SVR_MAJ(svr) < 3) {
+ void *p;
+ p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+ setbits_be32(p, 1 << (31 - 14));
+ }
}
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
- unsigned int i;
+ unsigned int i, bus_width;
volatile ccsr_ddr_t *ddr;
u32 temp_sdram_cfg;
+ u32 total_gb_size_per_controller;
+ int timeout;
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ int timeout_save;
volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
- u32 total_gb_size_per_controller;
unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
int csn = -1;
#endif
return;
}
- out_be32(&ddr->eor, regs->ddr_eor);
-
+ if (regs->ddr_eor)
+ out_be32(&ddr->eor, regs->ddr_eor);
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
debug("Workaround for ERRATUM_DDR111_DDR134\n");
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+ if (regs->ddr_wrlvl_cntl_2)
+ out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+ if (regs->ddr_wrlvl_cntl_3)
+ out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
out_be32(&ddr->debug[i], regs->debug[i]);
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+ out_be32(&ddr->debug[28], 0x00003000);
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
out_be32(&ddr->debug[12], 0x00000015);
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ if (!(regs->cs[i].config & 0x80000000))
+ continue;
+ total_gb_size_per_controller += 1 << (
+ ((regs->cs[i].config >> 14) & 0x3) + 2 +
+ ((regs->cs[i].config >> 8) & 0x7) + 12 +
+ ((regs->cs[i].config >> 0) & 0x7) + 8 +
+ 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+ 26); /* minus 26 (count of 64M) */
+ }
+ if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
+ total_gb_size_per_controller *= 3;
+ else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
+ total_gb_size_per_controller <<= 1;
+ /*
+ * total memory / bus width = transactions needed
+ * transactions needed / data rate = seconds
+ * to add plenty of buffer, double the time
+ * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+ * Let's wait for 800ms
+ */
+ bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ >> SDRAM_CFG_DBW_SHIFT);
+ timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+ (get_ddr_freq(0) >> 20)) << 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ timeout_save = timeout;
+#endif
+ total_gb_size_per_controller >>= 4; /* shift down to gb size */
+ debug("total %d GB\n", total_gb_size_per_controller);
+ debug("Need to wait up to %d * 10ms\n", timeout);
+
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
- while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
+ while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
/* continue this workaround */
while (in_be32(&ddr->debug[1]) & 0x400)
udelay(10000); /* throttle polling rate */
- /* 7. Wait for 400ms/GB */
- total_gb_size_per_controller = 0;
- for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
- if (i == csn) {
- total_gb_size_per_controller +=
- ((csn_bnds_backup & 0xFFFF) >> 6)
- - (csn_bnds_backup >> 22) + 1;
- } else {
- total_gb_size_per_controller +=
- ((regs->cs[i].bnds & 0xFFFF) >> 6)
- - (regs->cs[i].bnds >> 22) + 1;
- }
- }
- if (in_be32(&ddr->sdram_cfg) & 0x80000)
- total_gb_size_per_controller <<= 1;
- debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
- udelay(total_gb_size_per_controller * 400000);
+ /* 7. Wait for state machine 2nd run, roughly 400ms/GB */
+ debug("Wait for %d * 10ms\n", timeout_save);
+ udelay(timeout_save * 10000);
/* 8. Set sdram_cfg_2[dinit] if options requires */
setbits_be32(&ddr->sdram_cfg_2,
debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
/* 9. Poll until dinit is cleared */
- while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
- udelay(10000);
+ timeout = timeout_save;
+ debug("Need to wait up to %d * 10ms\n", timeout);
+ while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+ (timeout >= 0)) {
+ udelay(10000); /* throttle polling rate */
+ timeout--;
+ }
+
+ if (timeout <= 0)
+ printf("Waiting for D_INIT timeout. Memory may not work.\n");
/* 10. Clear EEBACR[3] */
clrbits_be32(&ecm->eebacr, 10000000);
void ft_fixup_cpu(void *blob, u64 memory_limit)
{
int off;
- ulong spin_tbl_addr = get_spin_phys_addr();
- u32 bootpg = determine_mp_bootpg();
+ phys_addr_t spin_tbl_addr = get_spin_phys_addr();
+ u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
if ((u64)bootpg < memory_limit) {
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
if (off < 0)
- printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
+ printf("Failed to reserve memory for bootpg: %s\n",
+ fdt_strerror(off));
+ }
+ /* Reserve spin table page */
+ if (spin_tbl_addr < memory_limit) {
+ off = fdt_add_mem_rsv(blob,
+ (spin_tbl_addr & ~0xffful), 4096);
+ if (off < 0)
+ printf("Failed to reserve memory for spin table: %s\n",
+ fdt_strerror(off));
}
}
#endif
/* we dont bother w/L3 since no platform of this type has one */
}
-#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+#elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
+ defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
static inline void ft_fixup_l2cache(void *blob)
{
int off, l2_off, l3_off = -1;
u32 *ph;
+#ifdef CONFIG_BACKSIDE_L2_CACHE
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+#else
+ struct ccsr_cluster_l2 *l2cache =
+ (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+ u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
+#endif
u32 size, line_size, num_ways, num_sets;
int has_l2 = 1;
if (has_l2) {
#ifdef CONFIG_SYS_CACHE_STASHING
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ /* Only initialize every eighth thread */
+ if (reg && !((*reg) % 8))
+#else
if (reg)
+#endif
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
#endif
#endif
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ do_fixup_by_compat_u32(blob, "fsl,qman",
+ "clock-frequency", sysinfo.freqQMAN, 1);
+#endif
+
#ifdef CONFIG_SYS_DPAA_PME
do_fixup_by_compat_u32(blob, "fsl,pme",
"clock-frequency", sysinfo.freqPME, 1);
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/fsl_law.h>
+#include <asm/errno.h>
+#include "fsl_corenet2_serdes.h"
+
+static u64 serdes1_prtcl_map;
+static u64 serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+static u64 serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+static u64 serdes4_prtcl_map;
+#endif
+
+#ifdef DEBUG
+static const char *serdes_prtcl_str[] = {
+ [NONE] = "NA",
+ [PCIE1] = "PCIE1",
+ [PCIE2] = "PCIE2",
+ [PCIE3] = "PCIE3",
+ [PCIE4] = "PCIE4",
+ [SATA1] = "SATA1",
+ [SATA2] = "SATA2",
+ [SRIO1] = "SRIO1",
+ [SRIO2] = "SRIO2",
+ [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
+ [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
+ [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
+ [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
+ [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
+ [SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
+ [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
+ [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
+ [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
+ [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+ [XAUI_FM1] = "XAUI_FM1",
+ [XAUI_FM2] = "XAUI_FM2",
+ [AURORA] = "DEBUG",
+ [CPRI1] = "CPRI1",
+ [CPRI2] = "CPRI2",
+ [CPRI3] = "CPRI3",
+ [CPRI4] = "CPRI4",
+ [CPRI5] = "CPRI5",
+ [CPRI6] = "CPRI6",
+ [CPRI7] = "CPRI7",
+ [CPRI8] = "CPRI8",
+ [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
+ [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
+ [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
+ [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
+ [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
+ [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
+ [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
+ [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
+ [QSGMII_FM1_A] = "QSGMII_FM1_A",
+ [QSGMII_FM1_B] = "QSGMII_FM1_B",
+ [QSGMII_FM2_A] = "QSGMII_FM2_A",
+ [QSGMII_FM2_B] = "QSGMII_FM2_B",
+ [XFI_FM1_MAC9] = "XFI_FM1_MAC9",
+ [XFI_FM1_MAC10] = "XFI_FM1_MAC10",
+ [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
+ [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
+ [INTERLAKEN] = "INTERLAKEN",
+};
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ u64 ret = 0;
+
+ ret |= (1ULL << device) & serdes1_prtcl_map;
+ ret |= (1ULL << device) & serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+ ret |= (1ULL << device) & serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+ ret |= (1ULL << device) & serdes4_prtcl_map;
+#endif
+
+ return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 cfg = in_be32(&gur->rcwsr[4]);
+ int i;
+
+ switch (sd) {
+ case FSL_SRDS_1:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ break;
+ case FSL_SRDS_2:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ break;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+ case FSL_SRDS_3:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+ break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+ case FSL_SRDS_4:
+ cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+ cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+ break;
+#endif
+ default:
+ printf("invalid SerDes%d\n", sd);
+ break;
+ }
+ /* Is serdes enabled at all? */
+ if (unlikely(cfg == 0))
+ return -ENODEV;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_get_prtcl(sd, cfg, i) == device)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u64 serdes_prtcl_map = 0;
+ u32 cfg;
+ int lane;
+
+ cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
+ /* Is serdes enabled at all? */
+ if (!cfg) {
+ printf("SERDES%d is not enabled\n", sd + 1);
+ return 0;
+ }
+
+ cfg >>= sd_prctl_shift;
+ printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg);
+ if (!is_serdes_prtcl_valid(sd, cfg))
+ printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+ serdes_prtcl_map |= (1ULL << lane_prtcl);
+ }
+
+ return serdes_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+
+ serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+ serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#ifdef CONFIG_SYS_FSL_SRDS_3
+ serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+ serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
+ CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+#endif
+
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_CORENET2_SERDES_H
+#define __FSL_CORENET2_SERDES_H
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+#endif /* __FSL_CORENET2_SERDES_H */
{ 17, 163, FSL_SRDS_BANK_2 },
{ 18, 164, FSL_SRDS_BANK_2 },
{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
{ 20, 170, FSL_SRDS_BANK_3 },
{ 21, 171, FSL_SRDS_BANK_3 },
{ 22, 172, FSL_SRDS_BANK_3 },
{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+ { 20, 166, FSL_SRDS_BANK_3 },
+ { 21, 167, FSL_SRDS_BANK_3 },
+ { 22, 168, FSL_SRDS_BANK_3 },
+ { 23, 169, FSL_SRDS_BANK_3 },
+#endif
};
int serdes_get_lane_idx(int lane)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int cfg;
serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+ serdes_corenet_t *srds2_regs;
+#endif
int lane, bank, idx;
int have_bank[SRDS_MAX_BANK] = {};
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
}
}
+#ifdef CONFIG_PPC_P5040
+ /*
+ * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+ * protocols, these lanes are routed to SATA. We use serdes_prtcl_map
+ * to decide whether a protocol is supported on a given lane, so SATA
+ * will be identified as not supported, and therefore not initialized.
+ * So for protocols which use SATA on bank4, we add SATA support in
+ * serdes_prtcl_map.
+ */
+ switch (cfg) {
+ case 0x0:
+ case 0x1:
+ case 0x2:
+ case 0x3:
+ case 0x4:
+ case 0x5:
+ case 0x6:
+ case 0x7:
+ serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
+ break;
+ default:
+ srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+
+ /* We don't need bank 4, so power it down */
+ setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
+ }
+#endif
+
soc_serdes_init();
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
}
}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
+ /*
+ * To avoid the situation that resulted in the P4080 erratum
+ * SERDES-8, a given SerDes bank will use the PLLs from the previous
+ * bank if one of the PLL frequencies is a multiple of the other. For
+ * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
+ * then bank 3 will use bank 2's PLL. P5040 Erratum A-004699 says
+ * that, in this situation, lane synchronization is not initiated. So
+ * when we detect a bank with a "borrowed" PLL, we have to manually
+ * initiate lane synchronization.
+ */
+ for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
+ /* Determine the first lane for this bank */
+ unsigned int lane;
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++)
+ if (lanes[lane].bank == bank)
+ break;
+ idx = lanes[lane].idx;
+
+ /*
+ * Check if the PLL for the bank is borrowed. The UOTHL
+ * bit of the first lane will tell us that.
+ */
+ if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
+ /* Manually start lane synchronization */
+ setbits_be32(&srds_regs->bank[bank].pllcr0,
+ SRDS_PLLCR0_PVCOCNT_EN);
+ }
+ }
+#endif
+
#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl;
#ifndef __FSL_CORENET_SERDES_H
#define __FSL_CORENET_SERDES_H
-#define SRDS_MAX_LANES 18
-#define SRDS_MAX_BANK 3
-
enum srds_bank {
FSL_SRDS_BANK_1 = 0,
FSL_SRDS_BANK_2 = 1,
return liodn_bases[dpaa_dev].num_ids;
}
+#ifdef CONFIG_SYS_SRIO
static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
{
int i;
}
}
}
+#endif
static void set_liodn(struct liodn_id_table *tbl, int size)
{
/* setup general liodn offsets */
set_liodn(liodn_tbl, liodn_tbl_sz);
+#ifdef CONFIG_SYS_SRIO
/* setup SRIO port liodns */
set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz);
+#endif
/* setup SEC block liodn bases & offsets if we have one */
if (IS_E_PROCESSOR(get_svr())) {
#endif
}
+#ifdef CONFIG_SYS_SRIO
static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
{
int i, srio_off;
}
}
}
+#endif
+
+#define CONFIG_SYS_MAX_PCI_EPS 8
+#define CONFIG_SYS_PCI_EP_LIODN_START 256
+
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+{
+ int off, pci_idx = 0, pci_cnt = 0, i, rc;
+ const uint32_t *base_liodn;
+ uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+
+ /*
+ * Count the number of pci nodes.
+ * It's needed later when the interleaved liodn offsets are generated.
+ */
+ off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ while (off != -FDT_ERR_NOTFOUND) {
+ pci_cnt++;
+ off = fdt_node_offset_by_compatible(fdt, off, compat);
+ }
+
+ for (off = fdt_node_offset_by_compatible(fdt, -1, compat);
+ off != -FDT_ERR_NOTFOUND;
+ off = fdt_node_offset_by_compatible(fdt, off, compat)) {
+ base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc);
+ if (!base_liodn) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Could not get liodn of node %s: %s\n",
+ path, fdt_strerror(rc));
+ continue;
+ }
+ for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+ liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+ i * pci_cnt + pci_idx - *base_liodn;
+ rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
+ liodn_offs, sizeof(liodn_offs));
+ if (rc) {
+ char path[64];
+
+ if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+ strcpy(path, "(unknown)");
+ printf("WARNING Unable to set fsl,liodn-offset-list for "
+ "node %s: %s\n", path, fdt_strerror(rc));
+ continue;
+ }
+ pci_idx++;
+ }
+}
static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
{
void fdt_fixup_liodn(void *blob)
{
+#ifdef CONFIG_SYS_SRIO
fdt_fixup_srio_liodn(blob, srio_liodn_tbl);
+#endif
fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_RMAN
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
+
+ fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
}
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
+u32 fsl_ddr_get_intl3r(void);
+
+extern u32 __spin_table[];
u32 get_my_id()
{
return 0;
if (nr == id) {
- table = (u32 *)get_spin_virt_addr();
+ table = (u32 *)&__spin_table;
printf("table base @ 0x%p\n", table);
} else {
- table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+ table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
printf("Running on cpu %d\n", id);
printf("\n");
printf("table @ 0x%p\n", table);
printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
- printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
- printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
+ printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
}
return 0;
0,
BOOT_ENTRY_PIR,
BOOT_ENTRY_R3_LOWER,
- BOOT_ENTRY_R6_LOWER,
};
int cpu_release(int nr, int argc, char * const argv[])
{
- u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+ u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
u64 boot_addr;
if (hold_cores_in_reset(1))
boot_addr = simple_strtoull(argv[0], NULL, 16);
- /* handle pir, r3, r6 */
- for (i = 1; i < 4; i++) {
+ /* handle pir, r3 */
+ for (i = 1; i < 3; i++) {
if (argv[i][0] != '-') {
u8 entry = boot_entry_map[i];
val = simple_strtoul(argv[i], NULL, 16);
return 0;
}
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
{
- /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
- if ((u64)gd->ram_size > 0xfffff000)
- return (0xfffff000);
+ u32 bootpg;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+ u32 svr = get_svr();
+ u32 granule_size, check;
+ struct law_entry e;
+#endif
- return (gd->ram_size - 4096);
-}
-ulong get_spin_phys_addr(void)
-{
- extern ulong __secondary_start_page;
- extern ulong __spin_table;
+ /* use last 4K of mapped memory */
+ bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+ CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
+ CONFIG_SYS_SDRAM_BASE - 4096;
+ if (pagesize)
+ *pagesize = 4096;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+/*
+ * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
+ * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
+ * the way boot page chosen in u-boot avoids hitting this erratum. So only
+ * thw workaround for 3-way interleaving is needed.
+ *
+ * To make sure boot page translation works with 3-Way DDR interleaving
+ * enforce a check for the following constrains
+ * 8K granule size requires BRSIZE=8K and
+ * bootpg >> log2(BRSIZE) %3 == 1
+ * 4K and 1K granule size requires BRSIZE=4K and
+ * bootpg >> log2(BRSIZE) %3 == 0
+ */
+ if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
+ e = find_law(bootpg);
+ switch (e.trgt_id) {
+ case LAW_TRGT_IF_DDR_INTLV_123:
+ granule_size = fsl_ddr_get_intl3r() & 0x1f;
+ if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
+ if (pagesize)
+ *pagesize = 8192;
+ bootpg &= 0xffffe000; /* align to 8KB */
+ check = bootpg >> 13;
+ while ((check % 3) != 1)
+ check--;
+ bootpg = check << 13;
+ debug("Boot page (8K) at 0x%08x\n", bootpg);
+ break;
+ } else {
+ bootpg &= 0xfffff000; /* align to 4KB */
+ check = bootpg >> 12;
+ while ((check % 3) != 0)
+ check--;
+ bootpg = check << 12;
+ debug("Boot page (4K) at 0x%08x\n", bootpg);
+ }
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
- return (determine_mp_bootpg() +
- (ulong)&__spin_table - (ulong)&__secondary_start_page);
+ return bootpg;
}
-ulong get_spin_virt_addr(void)
+phys_addr_t get_spin_phys_addr(void)
{
- extern ulong __secondary_start_page;
- extern ulong __spin_table;
-
- return (CONFIG_BPTR_VIRT_ADDR +
- (ulong)&__spin_table - (ulong)&__secondary_start_page);
+ return virt_to_phys(&__spin_table);
}
#ifdef CONFIG_FSL_CORENET
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
{
- u32 cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_virt_addr();
+ u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
+ u32 *table = (u32 *)&__spin_table;
volatile ccsr_gur_t *gur;
volatile ccsr_local_t *ccm;
volatile ccsr_rcpm_t *rcpm;
out_be32(&ccm->bstrl, bootpg);
e = find_law(bootpg);
- out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
+ /* pagesize is only 4K or 8K */
+ if (pagesize == 8192)
+ brsize = LAW_SIZE_8K;
+ out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
+ debug("BRSIZE is 0x%x\n", brsize);
/* readback to sync write */
in_be32(&ccm->bstrar);
#endif
}
#else
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
{
u32 up, cpu_up_mask, whoami;
- u32 *table = (u32 *)get_spin_virt_addr();
+ u32 *table = (u32 *)&__spin_table;
volatile u32 bpcr;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
void cpu_mp_lmb_reserve(struct lmb *lmb)
{
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
lmb_reserve(lmb, bootpg, 4096);
}
void setup_mp(void)
{
- extern ulong __secondary_start_page;
- extern ulong __bootpg_addr;
- ulong fixup = (ulong)&__secondary_start_page;
- u32 bootpg = determine_mp_bootpg();
+ extern u32 __secondary_start_page;
+ extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
+
+ int i;
+ ulong fixup = (u32)&__secondary_start_page;
+ u32 bootpg, bootpg_map, pagesize;
+
+ bootpg = determine_mp_bootpg(&pagesize);
+
+ /*
+ * pagesize is only 4K or 8K
+ * we only use the last 4K of boot page
+ * bootpg_map saves the address for the boot page
+ * 8K is used for the workaround of 3-way DDR interleaving
+ */
+
+ bootpg_map = bootpg;
+
+ if (pagesize == 8192)
+ bootpg += 4096; /* use 2nd half */
/* Some OSes expect secondary cores to be held in reset */
if (hold_cores_in_reset(0))
return;
- /* Store the bootpg's SDRAM address for use by secondary CPU cores */
- __bootpg_addr = bootpg;
+ /*
+ * Store the bootpg's cache-able half address for use by secondary
+ * CPU cores to continue to boot
+ */
+ __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
+
+ /* Store spin table's physical address for use by secondary cores */
+ __spin_table_addr = (u32)get_spin_phys_addr();
+
+ /* flush bootpg it before copying invalidate any staled cacheline */
+ flush_cache(bootpg, 4096);
/* look for the tlb covering the reset page, there better be one */
- int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+ i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
/* we found a match */
if (i != -1) {
memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
- plat_mp_up(bootpg);
+ plat_mp_up(bootpg_map, pagesize);
} else {
puts("WARNING: No reset page TLB. "
"Skipping secondary core setup\n");
#include <asm/mp.h>
-ulong get_spin_phys_addr(void);
-ulong get_spin_virt_addr(void);
+phys_addr_t get_spin_phys_addr(void);
u32 get_my_id(void);
int hold_cores_in_reset(int verbose);
#define BOOT_ENTRY_PIR 5
#define BOOT_ENTRY_R6_UPPER 6
#define BOOT_ENTRY_R6_LOWER 7
-#define NUM_BOOT_ENTRY 8
+#define NUM_BOOT_ENTRY 16 /* pad to 64 bytes */
#define SIZE_BOOT_ENTRY (NUM_BOOT_ENTRY * sizeof(u32))
#endif
--- /dev/null
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 2, 1, 0),
+ SET_QP_INFO(3, 4, 2, 1),
+ SET_QP_INFO(5, 6, 3, 2),
+ SET_QP_INFO(7, 8, 4, 3),
+ SET_QP_INFO(9, 10, 5, 0),
+ SET_QP_INFO(11, 12, 6, 1),
+ SET_QP_INFO(13, 14, 7, 2),
+ SET_QP_INFO(15, 16, 8, 3),
+ SET_QP_INFO(17, 18, 9, 0), /* for now, set sdest to 0 */
+ SET_QP_INFO(19, 20, 10, 0), /* for now, set sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(31),
+ SET_BMAN_LIODN(32),
+#endif
+
+ SET_SDHC_LIODN(1, 64),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 93),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 94),
+
+ SET_SATA_LIODN(1, 95),
+ SET_SATA_LIODN(2, 96),
+
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
+ SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
+
+ SET_DMA_LIODN(1, 193),
+ SET_DMA_LIODN(2, 194),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 6),
+ SET_FMAN_RX_1G_LIODN(1, 1, 7),
+ SET_FMAN_RX_1G_LIODN(1, 2, 8),
+ SET_FMAN_RX_1G_LIODN(1, 3, 9),
+ SET_FMAN_RX_1G_LIODN(1, 4, 10),
+ SET_FMAN_RX_10G_LIODN(1, 0, 11),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(2, 0, 12),
+ SET_FMAN_RX_1G_LIODN(2, 1, 13),
+ SET_FMAN_RX_1G_LIODN(2, 2, 14),
+ SET_FMAN_RX_1G_LIODN(2, 3, 15),
+ SET_FMAN_RX_1G_LIODN(2, 4, 16),
+ SET_FMAN_RX_10G_LIODN(2, 0, 17),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+ SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+ SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+ SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 89),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 90),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 91),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 92),
+ SET_SEC_DECO_LIODN_ENTRY(0, 139, 140),
+ SET_SEC_DECO_LIODN_ENTRY(1, 141, 142),
+ SET_SEC_DECO_LIODN_ENTRY(2, 143, 144),
+ SET_SEC_DECO_LIODN_ENTRY(3, 145, 146),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct liodn_id_table raide_liodn_tbl[] = {
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
+ SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
+};
+int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 101),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
+#endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+ [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(49),
+#endif
+};
--- /dev/null
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+/*
+ * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
+ * U-boot only supports one SerDes controller. Therefore, we ignore bank 4 in
+ * this table. This works because most of the SerDes code is for errata
+ * work-arounds, and there are no P5040 errata that effect bank 4.
+ */
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+ [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
+ [0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ /* SATA1, SATA2 */ },
+ [0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ /* SATA1, SATA2 */ },
+ [0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, /* SATA1, SATA2 */ },
+ [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
+ /* NONE, NONE */ },
+ [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+ NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
+ [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+ AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
+ XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
+ [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, /* NONE, NONE */ },
+ [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+ XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
+ /* NONE, NONE */ },
+ [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+ AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+ NONE, SATA1, SATA2, /* NONE, NONE */ },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+ if (!serdes_lane_enabled(lane))
+ return NONE;
+
+ return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+ int i;
+
+ if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_cfg_tbl[prtcl][i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
{
int off, err;
unsigned int maj, min;
+ unsigned int ip_cfg;
u32 rev_1 = in_be32(&qman->ip_rev_1);
+ u32 rev_2 = in_be32(&qman->ip_rev_2);
char compat[64];
int compat_len;
maj = (rev_1 >> 8) & 0xff;
min = rev_1 & 0xff;
+ ip_cfg = rev_2 & 0xff;
- compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1;
+ compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
{
int off, err;
unsigned int maj, min;
+ unsigned int ip_cfg;
u32 rev_1 = in_be32(&bman->ip_rev_1);
+ u32 rev_2 = in_be32(&bman->ip_rev_2);
char compat[64];
int compat_len;
maj = (rev_1 >> 8) & 0xff;
min = rev_1 & 0xff;
- compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1;
+ ip_cfg = rev_2 & 0xff;
+
+ compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+ maj, min, ip_cfg) + 1;
compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
#define toreset(x) (x - __secondary_start_page + 0xfffff000)
/* get our PIR to figure out our table entry */
- lis r3,toreset(__spin_table)@h
- ori r3,r3,toreset(__spin_table)@l
+ lis r3,toreset(__spin_table_addr)@h
+ ori r3,r3,toreset(__spin_table_addr)@l
+ lwz r3,0(r3)
- /* r10 has the base address for the entry */
+ /*
+ * r10 has the base address for the entry.
+ * we cannot access it yet before setting up a new TLB
+ */
mfspr r0,SPRN_PIR
#if defined(CONFIG_E6500)
/*
* PIR definition for E6500
* 0-17 Reserved (logic 0s)
- * 8-19 CHIP_ID, 2’b00 - SoC 1
+ * 8-19 CHIP_ID, 2'b00 - SoC 1
* all others - reserved
- * 20-24 CLUSTER_ID 5’b00000 - CCM 1
+ * 20-24 CLUSTER_ID 5'b00000 - CCM 1
* all others - reserved
- * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1
- * 2’b01 - cluster 2
- * 2’b10 - cluster 3
- * 2’b11 - cluster 4
- * 27-28 CORE_ID 2’b00 - core 0
- * 2’b01 - core 1
- * 2’b10 - core 2
- * 2’b11 - core 3
- * 29-31 THREAD_ID 3’b000 - thread 0
- * 3’b001 - thread 1
+ * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
+ * 2'b01 - cluster 2
+ * 2'b10 - cluster 3
+ * 2'b11 - cluster 4
+ * 27-28 CORE_ID 2'b00 - core 0
+ * 2'b01 - core 1
+ * 2'b10 - core 2
+ * 2'b11 - core 3
+ * 29-31 THREAD_ID 3'b000 - thread 0
+ * 3'b001 - thread 1
*/
rlwinm r4,r0,29,25,31
#elif defined(CONFIG_E500MC)
#else
mr r4,r0
#endif
- slwi r8,r4,5
+ slwi r8,r4,6 /* spin table is padded to 64 byte */
add r10,r3,r8
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
- /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
- slwi r8,r4,1
- addi r8,r8,32
- mtspr L1CSR2,r8
-#endif
-
#ifdef CONFIG_E6500
mfspr r0,SPRN_PIR
/*
mtspr SPRN_PIR,r4 /* write to PIR register */
+#ifdef CONFIG_SYS_CACHE_STASHING
+ /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+ slwi r8,r4,1
+ addi r8,r8,32
+ mtspr L1CSR2,r8
+#endif
+
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
/*
beq 2b
#endif
3:
-
-#define EPAPR_MAGIC (0x45504150)
-#define ENTRY_ADDR_UPPER 0
-#define ENTRY_ADDR_LOWER 4
-#define ENTRY_R3_UPPER 8
-#define ENTRY_R3_LOWER 12
-#define ENTRY_RESV 16
-#define ENTRY_PIR 20
-#define ENTRY_R6_UPPER 24
-#define ENTRY_R6_LOWER 28
-#define ENTRY_SIZE 32
-
- /* setup the entry */
- li r3,0
- li r8,1
- stw r4,ENTRY_PIR(r10)
- stw r3,ENTRY_ADDR_UPPER(r10)
- stw r8,ENTRY_ADDR_LOWER(r10)
- stw r3,ENTRY_R3_UPPER(r10)
- stw r4,ENTRY_R3_LOWER(r10)
- stw r3,ENTRY_R6_UPPER(r10)
- stw r3,ENTRY_R6_LOWER(r10)
-
- /* load r13 with the address of the 'bootpg' in SDRAM */
- lis r13,toreset(__bootpg_addr)@h
- ori r13,r13,toreset(__bootpg_addr)@l
+ /* setup mapping for the spin table, WIMGE=0b00100 */
+ lis r13,toreset(__spin_table_addr)@h
+ ori r13,r13,toreset(__spin_table_addr)@l
lwz r13,0(r13)
+ /* mask by 4K */
+ rlwinm r13,r13,0,0,19
- /* setup mapping for AS = 1, and jump there */
lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
mtspr SPRN_MAS0,r11
lis r11,(MAS1_VALID|MAS1_IPROT)@h
ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
mtspr SPRN_MAS1,r11
- oris r11,r13,(MAS2_I|MAS2_G)@h
- ori r11,r13,(MAS2_I|MAS2_G)@l
+ oris r11,r13,(MAS2_M|MAS2_G)@h
+ ori r11,r13,(MAS2_M|MAS2_G)@l
mtspr SPRN_MAS2,r11
oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
mtspr SPRN_MAS3,r11
+ li r11,0
+ mtspr SPRN_MAS7,r11
tlbwe
- bl 1f
-1: mflr r11
/*
- * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
- * this mask to fixup the cpu spin table and the address that we want
- * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
- * bootpg is at 0x7ffff000 in SDRAM.
+ * __bootpg_addr has the address of __second_half_boot_page
+ * jump there in AS=1 space with cache enabled
*/
- ori r13,r13,0xfff
- and r11, r11, r13
- and r10, r10, r13
-
- addi r11,r11,(2f-1b)
+ lis r13,toreset(__bootpg_addr)@h
+ ori r13,r13,toreset(__bootpg_addr)@l
+ lwz r11,0(r13)
+ mtspr SPRN_SRR0,r11
mfmsr r13
ori r12,r13,MSR_IS|MSR_DS@l
-
- mtspr SPRN_SRR0,r11
mtspr SPRN_SRR1,r12
rfi
+ /*
+ * Allocate some space for the SDRAM address of the bootpg.
+ * This variable has to be in the boot page so that it can
+ * be accessed by secondary cores when they come out of reset.
+ */
+ .align L1_CACHE_SHIFT
+ .globl __bootpg_addr
+__bootpg_addr:
+ .long 0
+
+ .global __spin_table_addr
+__spin_table_addr:
+ .long 0
+
+ /*
+ * This variable is set by cpu_init_r() after parsing hwconfig
+ * to enable workaround for erratum NMG_CPU_A011.
+ */
+ .align L1_CACHE_SHIFT
+ .global enable_cpu_a011_workaround
+enable_cpu_a011_workaround:
+ .long 1
+
+ /* Fill in the empty space. The actual reset vector is
+ * the last word of the page */
+__secondary_start_code_end:
+ .space 4092 - (__secondary_start_code_end - __secondary_start_page)
+__secondary_reset_vector:
+ b __secondary_start_page
+
+
+/* this is a separated page for the spin table and cacheable boot code */
+ .align L1_CACHE_SHIFT
+ .global __second_half_boot_page
+__second_half_boot_page:
+#define EPAPR_MAGIC 0x45504150
+#define ENTRY_ADDR_UPPER 0
+#define ENTRY_ADDR_LOWER 4
+#define ENTRY_R3_UPPER 8
+#define ENTRY_R3_LOWER 12
+#define ENTRY_RESV 16
+#define ENTRY_PIR 20
+#define ENTRY_SIZE 64
+ /*
+ * setup the entry
+ * r10 has the base address of the spin table.
+ * spin table is defined as
+ * struct {
+ * uint64_t entry_addr;
+ * uint64_t r3;
+ * uint32_t rsvd1;
+ * uint32_t pir;
+ * };
+ * we pad this struct to 64 bytes so each entry is in its own cacheline
+ */
+ li r3,0
+ li r8,1
+ mfspr r4,SPRN_PIR
+ stw r3,ENTRY_ADDR_UPPER(r10)
+ stw r3,ENTRY_R3_UPPER(r10)
+ stw r4,ENTRY_R3_LOWER(r10)
+ stw r3,ENTRY_RESV(r10)
+ stw r4,ENTRY_PIR(r10)
+ msync
+ stw r8,ENTRY_ADDR_LOWER(r10)
+
/* spin waiting for addr */
-2:
- lwz r4,ENTRY_ADDR_LOWER(r10)
+3: lwz r4,ENTRY_ADDR_LOWER(r10)
andi. r11,r4,1
- bne 2b
+ bne 3b
isync
/* setup IVORs to match fixed offsets */
/* mask by ~64M to setup our tlb we will jump to */
rlwinm r12,r4,0,0,5
- /* setup r3, r4, r5, r6, r7, r8, r9 */
+ /*
+ * setup r3, r4, r5, r6, r7, r8, r9
+ * r3 contains the value to put in the r3 register at secondary cpu
+ * entry. The high 32-bits are ignored on 32-bit chip implementations.
+ * 64-bit chip implementations however shall load all 64-bits
+ */
+#ifdef CONFIG_SYS_PPC64
+ ld r3,ENTRY_R3_UPPER(r10)
+#else
lwz r3,ENTRY_R3_LOWER(r10)
+#endif
li r4,0
li r5,0
- lwz r6,ENTRY_R6_LOWER(r10)
+ li r6,0
lis r7,(64*1024*1024)@h
li r8,0
li r9,0
mtspr SPRN_SRR1,r13
rfi
- /*
- * Allocate some space for the SDRAM address of the bootpg.
- * This variable has to be in the boot page so that it can
- * be accessed by secondary cores when they come out of reset.
- */
- .globl __bootpg_addr
-__bootpg_addr:
- .long 0
- .align L1_CACHE_SHIFT
+ .align 6
.globl __spin_table
__spin_table:
.space CONFIG_MAX_CPUS*ENTRY_SIZE
-
- /*
- * This variable is set by cpu_init_r() after parsing hwconfig
- * to enable workaround for erratum NMG_CPU_A011.
- */
- .align L1_CACHE_SHIFT
- .global enable_cpu_a011_workaround
-enable_cpu_a011_workaround:
- .long 1
-
- /* Fill in the empty space. The actual reset vector is
- * the last word of the page */
-__secondary_start_code_end:
- .space 4092 - (__secondary_start_code_end - __secondary_start_page)
-__secondary_reset_vector:
- b __secondary_start_page
+__spin_table_end:
+ .space 4096 - (__spin_table_end - __spin_table)
tbdf->cbd_sc |= BD_SC_READY;
}
-static void mpc85xx_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int mpc85xx_serial_getc(void)
{
volatile cbd_t *rbdf;
.stop = NULL,
.setbrg = mpc85xx_serial_setbrg,
.putc = mpc85xx_serial_putc,
- .puts = mpc85xx_serial_puts,
+ .puts = default_serial_puts,
.getc = mpc85xx_serial_getc,
.tstc = mpc85xx_serial_tstc,
};
void get_sys_info (sys_info_t * sysInfo)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
[13] = 2, /* CC4 PPL / 2 */
[14] = 4, /* CC4 PPL / 4 */
};
- uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
- uint ratio[4];
+ uint i, freqCC_PLL[6], rcw_tmp;
+ uint ratio[6];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
sysInfo->freqSystemBus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
+#else
sysInfo->freqDDRBus = sysclk;
+#endif
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
- mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+ mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+ & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
if (mem_pll_rat > 2)
sysInfo->freqDDRBus *= mem_pll_rat;
else
ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
- for (i = 0; i < 4; i++) {
+ ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
+ ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
+ for (i = 0; i < 6; i++) {
if (ratio[i] > 4)
freqCC_PLL[i] = sysclk * ratio[i];
else
freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
}
- rcw_tmp = in_be32(&gur->rcwsr[3]);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ /*
+ * Each cluster has up to 4 cores, sharing the same PLL selection.
+ * The cluster assignment is fixed per SoC. There is no way identify the
+ * assignment so far, presuming the "first configuration" which is to
+ * fill the lower cluster group first before moving up to next group.
+ * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
+ * and core 4~7 on cluster 2
+ * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
+ * and core 12~15 on cluster 4 if existing
+ */
for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
- u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
+ & 0xf;
u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+ if (cplx_pll > 3)
+ printf("Unsupported architecture configuration"
+ " in function %s\n", __func__);
+ cplx_pll += (cpu / 8) * 3;
sysInfo->freqProcessor[cpu] =
freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
}
+#define PME_CLK_SEL 0xe0000000
+#define PME_CLK_SHIFT 29
+#define FM1_CLK_SEL 0x1c000000
+#define FM1_CLK_SHIFT 26
+ rcw_tmp = in_be32(&gur->rcwsr[7]);
+
+#ifdef CONFIG_SYS_DPAA_PME
+ switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
+ case 1:
+ sysInfo->freqPME = freqCC_PLL[0];
+ break;
+ case 2:
+ sysInfo->freqPME = freqCC_PLL[0] / 2;
+ break;
+ case 3:
+ sysInfo->freqPME = freqCC_PLL[0] / 3;
+ break;
+ case 4:
+ sysInfo->freqPME = freqCC_PLL[0] / 4;
+ break;
+ case 6:
+ sysInfo->freqPME = freqCC_PLL[1] / 2;
+ break;
+ case 7:
+ sysInfo->freqPME = freqCC_PLL[1] / 3;
+ break;
+ default:
+ printf("Error: Unknown PME clock select!\n");
+ case 0:
+ sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
+ case 1:
+ sysInfo->freqFMan[0] = freqCC_PLL[3];
+ break;
+ case 2:
+ sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
+ break;
+ case 3:
+ sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
+ break;
+ case 4:
+ sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
+ break;
+ case 6:
+ sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
+ break;
+ case 7:
+ sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
+ break;
+ default:
+ printf("Error: Unknown FMan1 clock select!\n");
+ case 0:
+ sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+ break;
+ }
+#if (CONFIG_SYS_NUM_FMAN) == 2
+#define FM2_CLK_SEL 0x00000038
+#define FM2_CLK_SHIFT 3
+ rcw_tmp = in_be32(&gur->rcwsr[15]);
+ switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
+ case 1:
+ sysInfo->freqFMan[1] = freqCC_PLL[4];
+ break;
+ case 2:
+ sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
+ break;
+ case 3:
+ sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
+ break;
+ case 4:
+ sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
+ break;
+ case 6:
+ sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
+ break;
+ case 7:
+ sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
+ break;
+ default:
+ printf("Error: Unknown FMan2 clock select!\n");
+ case 0:
+ sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+ break;
+ }
+#endif /* CONFIG_SYS_NUM_FMAN == 2 */
+#endif /* CONFIG_SYS_DPAA_FMAN */
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+ for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+ u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+ u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+
+ sysInfo->freqProcessor[cpu] =
+ freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+ }
#define PME_CLK_SEL 0x80000000
#define FM1_CLK_SEL 0x40000000
#define FM2_CLK_SEL 0x20000000
#define HWA_ASYNC_DIV 0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL 1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
+#define HWA_CC_PLL 2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL 2
#else
#endif
#endif
-#else
- uint plat_ratio,e500_ratio,half_freqSystemBus;
-#if defined(CONFIG_FSL_LBC)
- uint lcrr_div;
-#endif
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#else /* CONFIG_FSL_CORENET */
+ uint plat_ratio, e500_ratio, half_freqSystemBus;
int i;
#ifdef CONFIG_QE
__maybe_unused u32 qe_ratio;
#endif /* CONFIG_FSL_CORENET */
#if defined(CONFIG_FSL_LBC)
+ uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
sysInfo->freqLocalBus = lcrr_div;
}
#endif
+
+#if defined(CONFIG_FSL_IFC)
+ ccr = in_be32(&ifc_regs->ifc_ccr);
+ ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+ sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
+#endif
}
*
*/
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+#ifdef CONFIG_SYS_CACHE_STASHING
/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
li r2,(32 + 0)
mtspr L1CSR2,r2
andi. r1,r3,L1CSR0_DCE@l
beq 2b
+ .macro create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
+ lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+ mtspr MAS0, \scratch
+ lis \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
+ mtspr MAS1, \scratch
+ lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+ mtspr MAS2, \scratch
+ lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+ mtspr MAS3, \scratch
+ lis \scratch, \phy_high@h
+ ori \scratch, \scratch, \phy_high@l
+ mtspr MAS7, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
+ .macro create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
+ lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+ mtspr MAS0, \scratch
+ lis \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
+ mtspr MAS1, \scratch
+ lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+ mtspr MAS2, \scratch
+ lis \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+ mtspr MAS3, \scratch
+ lis \scratch, \phy_high@h
+ ori \scratch, \scratch, \phy_high@l
+ mtspr MAS7, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
+ .macro delete_tlb1_entry esel scratch
+ lis \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+ mtspr MAS0, \scratch
+ li \scratch, 0
+ mtspr MAS1, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
+ .macro delete_tlb0_entry esel epn wimg scratch
+ lis \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+ mtspr MAS0, \scratch
+ li \scratch, 0
+ mtspr MAS1, \scratch
+ lis \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+ ori \scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+ mtspr MAS2, \scratch
+ isync
+ msync
+ tlbwe
+ isync
+ .endm
+
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
/*
* TLB entry for debuggging in AS1
* in AS1.
*/
- lis r6,FSL_BOOKE_MAS0(1,
- CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
- ori r6,r6,FSL_BOOKE_MAS0(1,
- CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
-
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
* and this window is outside of 4K boot window.
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
- (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
- (MAS2_I|MAS2_G))@l
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_4M, \
+ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
- /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
- lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
* because "nexti" will resize TLB to 4K
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
- (MAS2_I))@l
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+ 0, BOOKE_PAGESZ_256K, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I, \
+ CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#endif
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- tlbwe
- isync
#endif
/*
*/
/* create a temp mapping TLB0[0] for LBCR */
- lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
- ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
-
- lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
-
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- isync
- msync
- tlbwe
+ create_tlb0_entry 0, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
+ CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
+ 0, r6
/* Set LBCR register */
lis r4,CONFIG_SYS_LBCR_ADDR@h
ori r8, r8, CONFIG_SYS_CCSRBAR@l
lis r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
ori r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
- lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
- lis r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
- ori r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
- lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
- ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
- lis r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
- ori r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
- mtspr MAS7, r7
-#endif
- mtspr MAS0, r0
- mtspr MAS1, r1
- mtspr MAS2, r2
- mtspr MAS3, r3
- isync
- msync
- tlbwe
-
+ create_tlb0_entry 0, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
/*
* Create a TLB for the current location of CCSR. Register R9 is reserved
* for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
*/
create_ccsr_old_tlb:
- lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
- lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
- ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
- li r7, 0 /* The default CCSR address is always a 32-bit number */
- mtspr MAS7, r7
-#endif
- mtspr MAS0, r0
- /* MAS1 is the same as above */
- mtspr MAS2, r2
- mtspr MAS3, r3
- isync
- msync
- tlbwe
+ create_tlb0_entry 1, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
+ 0, r3 /* The default CCSR address is always a 32-bit number */
+
/*
* We have a TLB for what we think is the current (old) CCSR. Let's
/* Delete the temporary TLBs */
delete_temp_tlbs:
- lis r0, FSL_BOOKE_MAS0(0, 0, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
- li r1, 0
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
- mtspr MAS0, r0
- mtspr MAS1, r1
- mtspr MAS2, r2
- isync
- msync
- tlbwe
+ delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
+ delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
- lis r0, FSL_BOOKE_MAS0(0, 1, 0)@h
- ori r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
- lis r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
- ori r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
- mtspr MAS0, r0
- mtspr MAS2, r2
- isync
- msync
- tlbwe
#endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+create_ccsr_l2_tlb:
+ /*
+ * Create a TLB for the MMR location of CCSR
+ * to access L2CSR0 register
+ */
+ create_tlb0_entry 0, \
+ 0, BOOKE_PAGESZ_4K, \
+ CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+
+enable_l2_cluster_l2:
+ /* enable L2 cache */
+ lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
+ ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+ li r4, 33 /* stash id */
+ stw r4, 4(r3)
+ lis r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
+ ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
+ sync
+ stw r4, 0(r3) /* invalidate L2 */
+1: sync
+ lwz r0, 0(r3)
+ twi 0, r0, 0
+ isync
+ and. r1, r0, r4
+ bne 1b
+ lis r4, L2CSR0_L2E@h
+ sync
+ stw r4, 0(r3) /* eanble L2 */
+delete_ccsr_l2_tlb:
+ delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
#define DCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
#define LAW_SIZE_1M 0x13
#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
/* create a temp mapping in AS=1 to the 4M boot window */
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_4M, \
+ CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+ 0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
-
- /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
- lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
/* create a temp mapping in AS = 1 for Flash mapping
* created by PBL for ISBC code
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+ CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
* image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
*/
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+ CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#endif
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- isync
- msync
- tlbwe
-
/* create a temp mapping in AS=1 to the stack */
- lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
- ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
-
- lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
- ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
-
- lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
- ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
-
#if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
- (MAS3_SX|MAS3_SW|MAS3_SR))@l
- li r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
- mtspr MAS7,r10
+ create_tlb1_entry 14, \
+ 1, BOOKE_PAGESZ_16K, \
+ CONFIG_SYS_INIT_RAM_ADDR, 0, \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
+
#else
- lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
- ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+ create_tlb1_entry 14, \
+ 1, BOOKE_PAGESZ_16K, \
+ CONFIG_SYS_INIT_RAM_ADDR, 0, \
+ CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
#endif
- mtspr MAS0,r6
- mtspr MAS1,r7
- mtspr MAS2,r8
- mtspr MAS3,r9
- isync
- msync
- tlbwe
-
lis r6,MSR_IS|MSR_DS|MSR_DE@h
ori r6,r6,MSR_IS|MSR_DS|MSR_DE@l
lis r7,switch_as@h
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ /* dqrr liodn, frame data liodn, liodn off, sdest */
+ SET_QP_INFO(1, 27, 1, 0),
+ SET_QP_INFO(2, 28, 1, 0),
+ SET_QP_INFO(3, 29, 1, 1),
+ SET_QP_INFO(4, 30, 1, 1),
+ SET_QP_INFO(5, 31, 1, 2),
+ SET_QP_INFO(6, 32, 1, 2),
+ SET_QP_INFO(7, 33, 1, 3),
+ SET_QP_INFO(8, 34, 1, 3),
+ SET_QP_INFO(9, 35, 1, 4),
+ SET_QP_INFO(10, 36, 1, 4),
+ SET_QP_INFO(11, 37, 1, 5),
+ SET_QP_INFO(12, 38, 1, 5),
+ SET_QP_INFO(13, 39, 1, 6),
+ SET_QP_INFO(14, 40, 1, 6),
+ SET_QP_INFO(15, 41, 1, 7),
+ SET_QP_INFO(16, 42, 1, 7),
+ SET_QP_INFO(17, 43, 1, 8),
+ SET_QP_INFO(18, 44, 1, 8),
+ SET_QP_INFO(19, 45, 1, 9),
+ SET_QP_INFO(20, 46, 1, 9),
+ SET_QP_INFO(21, 47, 1, 10),
+ SET_QP_INFO(22, 48, 1, 10),
+ SET_QP_INFO(23, 49, 1, 11),
+ SET_QP_INFO(24, 50, 1, 11),
+ SET_QP_INFO(65, 89, 1, 0),
+ SET_QP_INFO(66, 90, 1, 0),
+ SET_QP_INFO(67, 91, 1, 1),
+ SET_QP_INFO(68, 92, 1, 1),
+ SET_QP_INFO(69, 93, 1, 2),
+ SET_QP_INFO(70, 94, 1, 2),
+ SET_QP_INFO(71, 95, 1, 3),
+ SET_QP_INFO(72, 96, 1, 3),
+ SET_QP_INFO(73, 97, 1, 4),
+ SET_QP_INFO(74, 98, 1, 4),
+ SET_QP_INFO(75, 99, 1, 5),
+ SET_QP_INFO(76, 100, 1, 5),
+ SET_QP_INFO(77, 101, 1, 6),
+ SET_QP_INFO(78, 102, 1, 6),
+ SET_QP_INFO(79, 103, 1, 7),
+ SET_QP_INFO(80, 104, 1, 7),
+ SET_QP_INFO(81, 105, 1, 8),
+ SET_QP_INFO(82, 106, 1, 8),
+ SET_QP_INFO(83, 107, 1, 9),
+ SET_QP_INFO(84, 108, 1, 9),
+ SET_QP_INFO(85, 109, 1, 10),
+ SET_QP_INFO(86, 110, 1, 10),
+ SET_QP_INFO(87, 111, 1, 11),
+ SET_QP_INFO(88, 112, 1, 11),
+ SET_QP_INFO(25, 51, 1, 0),
+ SET_QP_INFO(26, 52, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+ SET_SRIO_LIODN_1(1, 307),
+ SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_LIODN(62),
+ SET_BMAN_LIODN(63),
+#endif
+
+ SET_SDHC_LIODN(1, 552),
+
+ SET_PME_LIODN(117),
+
+ SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+ SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+ SET_SATA_LIODN(1, 555),
+ SET_SATA_LIODN(2, 556),
+
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+ SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+ SET_DMA_LIODN(1, 147),
+ SET_DMA_LIODN(2, 227),
+
+ SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+ SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+ SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+ SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+ SET_PMAN_LIODN(1, 513),
+ SET_PMAN_LIODN(2, 514),
+ SET_PMAN_LIODN(3, 515),
+#endif
+
+ /* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_1G_LIODN(1, 1, 89),
+ SET_FMAN_RX_1G_LIODN(1, 2, 90),
+ SET_FMAN_RX_1G_LIODN(1, 3, 91),
+ SET_FMAN_RX_1G_LIODN(1, 4, 92),
+ SET_FMAN_RX_1G_LIODN(1, 5, 93),
+ SET_FMAN_RX_10G_LIODN(1, 0, 94),
+ SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+ SET_FMAN_RX_1G_LIODN(2, 0, 88),
+ SET_FMAN_RX_1G_LIODN(2, 1, 89),
+ SET_FMAN_RX_1G_LIODN(2, 2, 90),
+ SET_FMAN_RX_1G_LIODN(2, 3, 91),
+ SET_FMAN_RX_1G_LIODN(2, 4, 92),
+ SET_FMAN_RX_1G_LIODN(2, 5, 93),
+ SET_FMAN_RX_10G_LIODN(2, 0, 94),
+ SET_FMAN_RX_10G_LIODN(2, 1, 95),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+ SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+ SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+ SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+ SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+ SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+ SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+ SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+ SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+ SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+ SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+ SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+ SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+ SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+ SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+ SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+ SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+ /* Set RMan block 0-3 liodn offset */
+ SET_RMAN_LIODN(0, 678),
+ SET_RMAN_LIODN(1, 679),
+ SET_RMAN_LIODN(2, 680),
+ SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+ [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694),
+#endif
+ [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+ [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ [FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+ [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+ [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+ XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+ {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+ HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+ /* SerDes 2 */
+ {1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC10, XAUI_FM2_MAC10,
+ XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
+ {2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+ HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {38, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM1_A, NONE}},
+ {56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, XFI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, XFI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {}
+};
+static struct serdes_config serdes3_cfg_tbl[] = {
+ /* SerDes 3 */
+ {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+ {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+ {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+ {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+ {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+ {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+ {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2}},
+ {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2}},
+ {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1}},
+ {}
+};
+static struct serdes_config serdes4_cfg_tbl[] = {
+ /* SerDes 4 */
+ {2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+ {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+ {6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
+ {12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
+ {14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+ {16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+ {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
+ {}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+ serdes2_cfg_tbl,
+ serdes3_cfg_tbl,
+ serdes4_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
{
int i;
unsigned int tlb_size;
- unsigned int wimge = 0;
+ unsigned int wimge = MAS2_M;
unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
unsigned int max_cam;
u64 size, memsize = (u64)memsize_in_meg << 20;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
}
_edata = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(8);
__init_begin = .;
__init_end = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
{
#ifdef CONFIG_MP
int off;
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
return 1;
}
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
{
+ if (pagesize)
+ *pagesize = 4096;
+
/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
if ((u64)gd->ram_size > 0xfffff000)
return (0xfff00000);
void cpu_mp_lmb_reserve(struct lmb *lmb)
{
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
/* tell u-boot we stole a page */
lmb_reserve(lmb, bootpg, 4096);
{
extern ulong __secondary_start_page;
ulong fixup = (ulong)&__secondary_start_page;
- u32 bootpg = determine_mp_bootpg();
+ u32 bootpg = determine_mp_bootpg(NULL);
u32 bootpg_va;
if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
CPU_TYPE_ENTRY(P4080, P4080, 8),
CPU_TYPE_ENTRY(P5010, P5010, 1),
CPU_TYPE_ENTRY(P5020, P5020, 2),
+ CPU_TYPE_ENTRY(P5021, P5021, 2),
+ CPU_TYPE_ENTRY(P5040, P5040, 4),
+ CPU_TYPE_ENTRY(T4240, T4240, 0),
+ CPU_TYPE_ENTRY(T4120, T4120, 0),
+ CPU_TYPE_ENTRY(B4860, B4860, 0),
+ CPU_TYPE_ENTRY(G4860, G4860, 0),
+ CPU_TYPE_ENTRY(G4060, G4060, 0),
+ CPU_TYPE_ENTRY(B4440, B4440, 0),
+ CPU_TYPE_ENTRY(G4440, G4440, 0),
+ CPU_TYPE_ENTRY(B4420, B4420, 0),
+ CPU_TYPE_ENTRY(B4220, B4220, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),
CPU_TYPE_ENTRY(BSC9131, 9131, 1),
#elif defined(CONFIG_MPC86xx)
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
#if !defined(CONFIG_FSL_DDR1)
+static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
+{
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
+ if (dimm_params[0].n_ranks == 4)
+ return 1;
+#endif
+
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
+ if ((dimm_params[0].n_ranks == 2) &&
+ (dimm_params[1].n_ranks == 2))
+ return 1;
+
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ if (dimm_params[0].n_ranks == 4)
+ return 1;
+#endif
+#endif
+ return 0;
+}
+
/*
* DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
*
* dreams up non-zero default values to be backwards compatible.
*/
static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
- const memctl_options_t *popts)
+ const memctl_options_t *popts,
+ const dimm_params_t *dimm_params)
{
unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
unsigned int data_rate = get_ddr_freq(0);
tmrd_mclk = 4;
/* set the turnaround time */
- trwt_mclk = 1;
+
+ /*
+ * for single quad-rank DIMM and two dual-rank DIMMs
+ * to avoid ODT overlap
+ */
+ if (avoid_odt_overlap(dimm_params)) {
+ twwt_mclk = 2;
+ trrt_mclk = 1;
+ }
+ /* for faster clock, need more time for data setup */
+ trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
+
if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
twrt_mclk = 1;
| ((caslat_ctrl & 0xF) << 16)
| ((refrec_ctrl & 0xF) << 12)
| ((wrrec_mclk & 0x0F) << 8)
- | ((acttoact_mclk & 0x07) << 4)
- | ((wrtord_mclk & 0x07) << 0)
+ | ((acttoact_mclk & 0x0F) << 4)
+ | ((wrtord_mclk & 0x0F) << 0)
);
debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
}
unsigned int dqs_cfg; /* DQS configuration */
unsigned int odt_cfg = 0; /* ODT configuration */
unsigned int num_pr; /* Number of posted refreshes */
+ unsigned int slow = 0; /* DDR will be run less than 1250 */
unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
unsigned int ap_en; /* Address Parity Enable */
unsigned int d_init; /* DRAM data initialization */
obc_cfg = 0;
#endif
+#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
+ slow = get_ddr_freq(0) < 1249000000;
+#endif
+
if (popts->registered_dimm_en) {
rcw_en = 1;
ap_en = popts->ap_en;
| ((dqs_cfg & 0x3) << 26)
| ((odt_cfg & 0x3) << 21)
| ((num_pr & 0xf) << 12)
+ | ((slow & 1) << 11)
| (qd_en << 9)
| (unq_mrs_en << 8)
| ((obc_cfg & 0x1) << 6)
| ((wrlvl_start & 0x1F) << 0)
);
debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
+ ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
+ debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
+ ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
+ debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
+
}
/* DDR Self Refresh Counter (DDR_SR_CNTR) */
debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
}
+static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+ ddr->ddr_cdr2 = popts->ddr_cdr2;
+ debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
+}
+
unsigned int
check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
{
break;
}
sa = common_dimm->base_address;
- ea = common_dimm->total_mem - 1;
+ ea = sa + common_dimm->total_mem - 1;
} else if (!popts->memctl_interleaving) {
/*
* If memory interleaving between controllers is NOT
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
sa = common_dimm->base_address;
- ea = common_dimm->total_mem - 1;
+ ea = sa + common_dimm->total_mem - 1;
break;
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
if ((i >= 2) && (dimm_number == 0)) {
sa >>= 24;
ea >>= 24;
- ddr->cs[i].bnds = (0
- | ((sa & 0xFFF) << 16) /* starting address MSB */
- | ((ea & 0xFFF) << 0) /* ending address MSB */
- );
+ if (cs_en) {
+ ddr->cs[i].bnds = (0
+ | ((sa & 0xFFF) << 16)/* starting address MSB */
+ | ((ea & 0xFFF) << 0) /* ending address MSB */
+ );
+ } else {
+ debug("FSLDDR: setting bnds to 0 for inactive CS\n");
+ ddr->cs[i].bnds = 0;
+ }
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
- if (cs_en) {
- set_csn_config(dimm_number, i, ddr, popts, dimm_params);
- set_csn_config_2(i, ddr);
- } else
- debug("CS%d is disabled.\n", i);
+ set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+ set_csn_config_2(i, ddr);
}
/*
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_FSL_DDR1)
- set_timing_cfg_0(ddr, popts);
+ set_timing_cfg_0(ddr, popts, dimm_params);
#endif
set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
cas_latency, additive_latency);
set_ddr_cdr1(ddr, popts);
+ set_ddr_cdr2(ddr, popts);
set_ddr_sdram_cfg(ddr, popts, common_dimm);
ip_rev = fsl_ddr_get_version();
if (ip_rev > 0x40400)
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
+ CTRL_OPTIONS(ddr_cdr1),
+ CTRL_OPTIONS(ddr_cdr2),
CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
CTRL_OPTIONS(tFAW_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CFG_REGS(timing_cfg_5),
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
+ CFG_REGS(ddr_wrlvl_cntl_2),
+ CFG_REGS(ddr_wrlvl_cntl_3),
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_cdr2),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
+ CFG_REGS(ddr_eor),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
CFG_REGS(timing_cfg_5),
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
+ CFG_REGS(ddr_wrlvl_cntl_2),
+ CFG_REGS(ddr_wrlvl_cntl_3),
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(err_int_en),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_sdram_rcw_2),
-
+ CFG_REGS(ddr_eor),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
+ CTRL_OPTIONS_HEX(ddr_cdr1),
+ CTRL_OPTIONS_HEX(ddr_cdr2),
CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
CTRL_OPTIONS(tFAW_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
* doesn't return
*/
do_reset(NULL, 0, 0, NULL);
+ printf("Reset didn't work\n");
}
if (strcmp(argv[0], "recompute") == 0) {
unsigned int
compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
common_timing_params_t *outpdimm,
- unsigned int number_of_dimms)
+ const unsigned int number_of_dimms)
{
unsigned int i, j;
temp1++;
continue;
}
+
+ /*
+ * check if quad-rank DIMM is plugged if
+ * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
+ * Only the board with proper design is capable
+ */
+#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
if (dimm_params[i].n_ranks == 4 && \
CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
printf("Found Quad-rank DIMM, not able to support.");
temp1++;
continue;
}
-
+#endif
/*
* Find minimum tCKmax_ps to find fastest slow speed,
* i.e., this is the slowest the whole system can go.
if (outpdimm->all_DIMMs_registered)
for (j = 0; j < 16; j++) {
outpdimm->rcw[j] = dimm_params[0].rcw[j];
- for (i = 1; i < number_of_dimms; i++)
+ for (i = 1; i < number_of_dimms; i++) {
+ if (!dimm_params[i].n_ranks)
+ continue;
if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
temp1 = 1;
break;
}
+ }
}
if (temp1 != 0)
sizeof(generic_spd_eeprom_t));
if (ret) {
- printf("DDR: failed to read SPD from address %u\n", i2c_address);
+ if (i2c_address ==
+#ifdef SPD_EEPROM_ADDRESS
+ SPD_EEPROM_ADDRESS
+#elif defined(SPD_EEPROM_ADDRESS1)
+ SPD_EEPROM_ADDRESS1
+#endif
+ ) {
+ printf("DDR: failed to read SPD from address %u\n",
+ i2c_address);
+ } else {
+ debug("DDR: failed to read SPD from address %u\n",
+ i2c_address);
+ }
memset(spd, 0, sizeof(generic_spd_eeprom_t));
}
}
#endif
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
+ /* setup 3-way interleaving before enabling DDRC */
+ switch (info.memctl_opts[0].memctl_interleaving_mode) {
+ case FSL_DDR_3WAY_1KB_INTERLEAVING:
+ case FSL_DDR_3WAY_4KB_INTERLEAVING:
+ case FSL_DDR_3WAY_8KB_INTERLEAVING:
+ fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
+ break;
+ default:
+ break;
+ }
+
/* Program configuration registers. */
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
debug("Programming controller %u\n", i);
case FSL_DDR_3WAY_8KB_INTERLEAVING:
law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
if (i == 0) {
- fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
fsl_ddr_set_lawbar(&info.common_timing_params[i],
law_memctl, i);
}
}
};
#endif
+
+/*
+ * Automatically seleect bank interleaving mode based on DIMMs
+ * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
+ * This function only deal with one or two slots per controller.
+ */
+static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
+{
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+ if (pdimm[0].n_ranks == 4)
+ return FSL_DDR_CS0_CS1_CS2_CS3;
+ else if (pdimm[0].n_ranks == 2)
+ return FSL_DDR_CS0_CS1;
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ if (pdimm[0].n_ranks == 4)
+ return FSL_DDR_CS0_CS1_CS2_CS3;
+#endif
+ if (pdimm[0].n_ranks == 2) {
+ if (pdimm[1].n_ranks == 2)
+ return FSL_DDR_CS0_CS1_CS2_CS3;
+ else
+ return FSL_DDR_CS0_CS1;
+ }
+#endif
+ return 0;
+}
+
unsigned int populate_memctl_options(int all_DIMMs_registered,
memctl_options_t *popts,
dimm_params_t *pdimm,
}
} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
switch (pdimm[0].n_ranks) {
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ case 4:
+ pdodt = single_Q;
+ if (pdimm[1].n_ranks)
+ printf("Error: Quad- and Dual-rank DIMMs "
+ "cannot be used together\n");
+ break;
+#endif
case 2:
switch (pdimm[1].n_ranks) {
case 2:
else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
"cs0_cs1_cs2_cs3", buf))
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+ else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+ "auto", buf))
+ popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
else
printf("hwconfig has unrecognized parameter for bank_intlv.\n");
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
"interleaving disabled!\n", ctrl_num);
}
#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ if (pdimm[0].n_ranks == 4)
+ break;
+#endif
if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
popts->ba_intlv_ctl = 0;
printf("Not enough bank(chip-select) for "
break;
}
debug("%d of %d controllers are interleaving.\n", j, k);
- if (j != k) {
+ if (j && (j != k)) {
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
pinfo->memctl_opts[i].memctl_interleaving = 0;
printf("Not all controllers have compatible "
#endif
}
+u32 fsl_ddr_get_intl3r(void)
+{
+ u32 val = 0;
+#ifdef CONFIG_E6500
+ u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+ val = *mcintl3r;
+#endif
+ return val;
+}
+
void board_add_ram_info(int use_default)
{
#if defined(CONFIG_MPC83xx)
uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
int cas_lat;
+#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+ if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+ ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+ sdram_cfg = in_be32(&ddr->sdram_cfg);
+ }
+#endif
+#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+ if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+ ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+ sdram_cfg = in_be32(&ddr->sdram_cfg);
+ }
+#endif
puts(" (DDR");
switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
SDRAM_CFG_SDRAM_TYPE_SHIFT) {
const char *phys[] = { "ulpi", "utmi" };
const char *mode = NULL;
const char *phy_type = NULL;
+ const char *dr_mode_type = NULL;
+ const char *dr_phy_type = NULL;
char usb1_defined = 0;
int usb_mode_off = -1;
int usb_phy_off = -1;
break;
}
}
+
for (j = 0; j < ARRAY_SIZE(phys); j++) {
if (hwconfig_subarg_cmp(str, "phy_type",
phys[j])) {
break;
}
}
- if (mode_idx >= 0) {
- usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
- modes[mode_idx], NULL, usb_mode_off);
- if (usb_mode_off < 0)
- return;
- }
- if (phy_idx >= 0) {
- usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
- NULL, phys[phy_idx], usb_phy_off);
- if (usb_phy_off < 0)
- return;
- }
+
+ dr_mode_type = modes[mode_idx];
+ dr_phy_type = phys[phy_idx];
+
+ /* use usb_dr_mode and usb_phy_type if
+ usb1_defined = 0; these variables are to
+ be deprecated */
if (!strcmp(str, "usb1"))
usb1_defined = 1;
- if (mode_idx < 0 && phy_idx < 0)
+
+ if (mode_idx < 0 && phy_idx < 0) {
printf("WARNING: invalid phy or mode\n");
+ return;
+ }
}
+
+ usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+ dr_mode_type, NULL, usb_mode_off);
+
+ if (usb_mode_off < 0)
+ return;
+
+ usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+ NULL, dr_phy_type, usb_phy_off);
+
+ if (usb_phy_off < 0)
+ return;
}
+
if (!usb1_defined) {
int usb_off = -1;
mode = getenv("usb_dr_mode");
phy_type = getenv("usb_phy_type");
- if (!mode && !phy_type)
- return;
- fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
+ if (mode || phy_type) {
+ printf("WARNING: usb_dr_mode and usb_phy_type "
+ "are to be deprecated soon. Use "
+ "hwconfig to set these values instead!!\n");
+ fdt_fixup_usb_mode_phy_type(blob, mode,
+ phy_type, usb_off);
+ }
}
}
#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
+#include <asm/errno.h>
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x10000001
#define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000
#define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
#define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
#define SRIO_LCSBA1CSR 0x60000000
+#endif
#if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
+ #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
+#else
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+#endif
#define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
#error "No defines for DEVDISR_SRIO"
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+/*
+ * Erratum A-004034
+ * Affects: SRIO
+ * Description: During port initialization, the SRIO port performs
+ * lane synchronization (detecting valid symbols on a lane) and
+ * lane alignment (coordinating multiple lanes to receive valid data
+ * across lanes). Internal errors in lane synchronization and lane
+ * alignment may cause failure to achieve link initialization at
+ * the configured port width.
+ * An SRIO port configured as a 4x port may see one of these scenarios:
+ * 1. One or more lanes fails to achieve lane synchronization. Depending
+ * on which lanes fail, this may result in downtraining from 4x to 1x
+ * on lane 0, 4x to 1x on lane R (redundant lane).
+ * 2. The link may fail to achieve lane alignment as a 4x, even though
+ * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
+ * An SRIO port configured as a 1x port may fail to complete port
+ * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
+ * Impact: SRIO port may downtrain to 1x, or may fail to complete
+ * link initialization. Once a port completes link initialization
+ * successfully, it will operate normally.
+ */
+static int srio_erratum_a004034(u8 port)
+{
+ serdes_corenet_t *srds_regs;
+ u32 conf_lane;
+ u32 init_lane;
+ int idx, first, last;
+ u32 i;
+ unsigned long long end_tick;
+ struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+ srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
+ >> (12 - port * 4)) & 0x3;
+ init_lane = (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr) >> 27) & 0x7;
+
+ /*
+ * Start a counter set to ~2 ms after the SERDES reset is
+ * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
+ * corresponding to the SERDES bank/PLL for the SRIO port).
+ */
+ if (in_be32((void *)&srds_regs->bank[0].rstctl)
+ & SRDS_RSTCTL_RSTDONE) {
+ /*
+ * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
+ * PO=1 or the counter expires. If the counter expires, the
+ * port has failed initialization: go to recover steps. If PO=1
+ * and the desired port width is 1x, go to normal steps. If
+ * PO = 1 and the desired port width is 4x, go to recover steps.
+ */
+ end_tick = usec2ticks(2000) + get_ticks();
+ do {
+ if (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pescsr) & 0x2) {
+ if (conf_lane == 0x1)
+ goto host_ok;
+ else {
+ if (init_lane == 0x2)
+ goto host_ok;
+ else
+ break;
+ }
+ }
+ } while (end_tick > get_ticks());
+
+ /* recover at most 3 times */
+ for (i = 0; i < 3; i++) {
+ /* Set SRIO PnCCSR[PD]=1 */
+ setbits_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr,
+ 0x800000);
+ /*
+ * Set SRIO PnPCR[OBDEN] on the host to
+ * enable the discarding of any pending packets.
+ */
+ setbits_be32((void *)&srio_regs->impl.port[port].pcr,
+ 0x04);
+ /* Wait 50 us */
+ udelay(50);
+ /* Run sync command */
+ isync();
+
+ if (port)
+ first = serdes_get_first_lane(SRIO2);
+ else
+ first = serdes_get_first_lane(SRIO1);
+ if (unlikely(first < 0))
+ return -ENODEV;
+ if (conf_lane == 0x1)
+ last = first;
+ else
+ last = first + 3;
+ /*
+ * Set SERDES BnGCRm0[RRST]=0 for each SRIO
+ * bank n and lane m.
+ */
+ for (idx = first; idx <= last; idx++)
+ clrbits_be32(&srds_regs->lane[idx].gcr0,
+ SRDS_GCR0_RRST);
+ /*
+ * Read SERDES BnGCRm0 for each SRIO
+ * bank n and lane m
+ */
+ for (idx = first; idx <= last; idx++)
+ in_be32(&srds_regs->lane[idx].gcr0);
+ /* Run sync command */
+ isync();
+ /* Wait >= 100 ns */
+ udelay(1);
+ /*
+ * Set SERDES BnGCRm0[RRST]=1 for each SRIO
+ * bank n and lane m.
+ */
+ for (idx = first; idx <= last; idx++)
+ setbits_be32(&srds_regs->lane[idx].gcr0,
+ SRDS_GCR0_RRST);
+ /*
+ * Read SERDES BnGCRm0 for each SRIO
+ * bank n and lane m
+ */
+ for (idx = first; idx <= last; idx++)
+ in_be32(&srds_regs->lane[idx].gcr0);
+ /* Run sync command */
+ isync();
+ /* Wait >= 300 ns */
+ udelay(1);
+
+ /* Write 1 to clear all bits in SRIO PnSLCSR */
+ out_be32((void *)&srio_regs->impl.port[port].slcsr,
+ 0xffffffff);
+ /* Clear SRIO PnPCR[OBDEN] on the host */
+ clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
+ 0x04);
+ /* Set SRIO PnCCSR[PD]=0 */
+ clrbits_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr,
+ 0x800000);
+ /* Wait >= 24 ms */
+ udelay(24000);
+ /* Poll the state of the port again */
+ init_lane =
+ (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pccsr) >> 27) & 0x7;
+ if (in_be32((void *)&srio_regs->lp_serial
+ .port[port].pescsr) & 0x2) {
+ if (conf_lane == 0x1)
+ goto host_ok;
+ else {
+ if (init_lane == 0x2)
+ goto host_ok;
+ }
+ }
+ if (i == 2)
+ return -ENODEV;
+ }
+ } else
+ return -ENODEV;
+
+host_ok:
+ /* Poll PnESCSR[OES] on the host until it is clear */
+ end_tick = usec2ticks(1000000) + get_ticks();
+ do {
+ if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
+ & 0x10000)) {
+ out_be32(((void *)&srio_regs->lp_serial
+ .port[port].pescsr), 0xffffffff);
+ out_be32(((void *)&srio_regs->phys_err
+ .port[port].edcsr), 0);
+ out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
+ return 0;
+ }
+ } while (end_tick > get_ticks());
+
+ return -ENODEV;
+}
+#endif
+
void srio_init(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
int srio1_used = 0, srio2_used = 0;
+ u32 *devdisr;
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ devdisr = &gur->devdisr3;
+#else
+ devdisr = &gur->devdisr;
+#endif
if (is_serdes_configured(SRIO1)) {
set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
LAW_TRGT_IF_RIO_1);
srio1_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+ if (srio_erratum_a004034(0) < 0)
+ printf("SRIO1: enabled but port error\n");
+ else
+#endif
printf("SRIO1: enabled\n");
} else {
printf("SRIO1: disabled\n");
law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
LAW_TRGT_IF_RIO_2);
srio2_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+ if (srio_erratum_a004034(1) < 0)
+ printf("SRIO2: enabled but port error\n");
+ else
+#endif
printf("SRIO2: enabled\n");
+
} else {
printf("SRIO2: disabled\n");
}
#ifdef CONFIG_FSL_CORENET
/* On FSL_CORENET devices we can disable individual ports */
if (!srio1_used)
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+ setbits_be32(devdisr, _DEVDISR_SRIO1);
if (!srio2_used)
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+ setbits_be32(devdisr, _DEVDISR_SRIO2);
#endif
/* neither port is used - disable everything */
if (!srio1_used && !srio2_used) {
- setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
- setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
- setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+ setbits_be32(devdisr, _DEVDISR_SRIO1);
+ setbits_be32(devdisr, _DEVDISR_SRIO2);
+ setbits_be32(devdisr, _DEVDISR_RMU);
}
}
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
#endif
+#define FSL_DDR_VER_4_7 47
+
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS 64
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P3041)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 8
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
#define CONFIG_SYS_P4080_ERRATUM_CPU22
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_P4080_ERRATUM_SERDES8
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+
+#elif defined(CONFIG_PPC_P5040)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 5
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_NUM_FM2_DTSEC 5
+#define CONFIG_SYS_NUM_FM2_10GEC 1
+#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_ERRATUM_A004699
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_BSC9131)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#elif defined(CONFIG_PPC_T4240)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_MAX_CPUS 12
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 2
+#define CONFIG_SYS_NUM_FM1_DTSEC 8
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_SYS_NUM_FM2_DTSEC 8
+#define CONFIG_SYS_NUM_FM2_10GEC 2
+#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+
+#elif defined(CONFIG_PPC_B4860)
+#define CONFIG_SYS_PPC64 /* 64-bit core */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
+#define CONFIG_SYS_FSL_NUM_LAWS 32
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 6
+#define CONFIG_SYS_NUM_FM1_10GEC 2
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV 16
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+
#else
#error Processor type not defined for this platform
#endif
#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C
#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D
+#define SDRAM_CS_CONFIG_EN 0x80000000
+
/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
*/
#define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#define SDRAM_CFG_DBW_MASK 0x00180000
+#define SDRAM_CFG_DBW_SHIFT 19
#define SDRAM_CFG_32_BE 0x00080000
#define SDRAM_CFG_16_BE 0x00100000
#define SDRAM_CFG_8_BE 0x00040000
/* DDR_CDR1 */
#define DDR_CDR1_DHC_EN 0x80000000
+#define DDR_CDR1_ODT_SHIFT 17
+#define DDR_CDR1_ODT_MASK 0x6
+#define DDR_CDR2_ODT_MASK 0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_120ohm 0x1
+#define DDR_CDR_ODT_180ohm 0x2
+#define DDR_CDR_ODT_75ohm 0x3
+#define DDR_CDR_ODT_110ohm 0x4
+#define DDR_CDR_ODT_60hm 0x5
+#define DDR_CDR_ODT_70ohm 0x6
+#define DDR_CDR_ODT_47ohm 0x7
+#else
+#define DDR_CDR_ODT_75ohm 0x0
+#define DDR_CDR_ODT_55ohm 0x1
+#define DDR_CDR_ODT_60ohm 0x2
+#define DDR_CDR_ODT_50ohm 0x3
+#define DDR_CDR_ODT_150ohm 0x4
+#define DDR_CDR_ODT_43ohm 0x5
+#define DDR_CDR_ODT_120ohm 0x6
+#endif
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
unsigned int timing_cfg_5;
unsigned int ddr_zq_cntl;
unsigned int ddr_wrlvl_cntl;
+ unsigned int ddr_wrlvl_cntl_2;
+ unsigned int ddr_wrlvl_cntl_3;
unsigned int ddr_sr_cntr;
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
+ unsigned int wrlvl_ctl_2;
+ unsigned int wrlvl_ctl_3;
unsigned int half_strength_driver_enable;
unsigned int twoT_en;
unsigned int rcw_2;
/* control register 1 */
unsigned int ddr_cdr1;
+ unsigned int ddr_cdr2;
unsigned int trwt_override;
unsigned int trwt; /* read-to-write turnaround */
extern int fsl_use_spd(void);
extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num);
+u32 fsl_ddr_get_intl3r(void);
/*
* The 85xx boards have a common prototype for fixed_sdram so put the
u8 res[4*1024];
} fm_10gec_mdio_t;
+typedef struct fm_memac {
+ u8 res[4*1024];
+} fm_memac_t;
+
+typedef struct fm_memac_mdio {
+ u8 res[4*1024];
+} fm_memac_mdio_t;
+
typedef struct fm_1588 {
u8 res[4*1024];
} fm_1588_t;
u8 res1[8*1024];
fm_soft_parser_t fm_soft_parser;
u8 res2[96*1024];
+#ifdef CONFIG_SYS_FMAN_V3
+ struct {
+ fm_memac_t fm_memac;
+ fm_memac_mdio_t fm_memac_mdio;
+ } memac[10];
+ u8 res4[32*1024];
+ fm_memac_mdio_t fm_dedicated_mdio[2];
+#else
struct {
fm_dtsec_t fm_dtesc;
fm_mdio_t fm_mdio;
fm_10gec_mdio_t fm_10gec_mdio;
} mac_10g[1];
u8 res4[48*1024];
+#endif
fm_1588_t fm_1588;
u8 res5[4*1024];
} ccsr_fman_t;
SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+ SET_LIODN_ENTRY_1(compat, liodn,\
+ offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+ CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, liodn) \
SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+#define SET_PMAN_LIODN(num, liodn) \
+ SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
+ offsetof(struct ccsr_pman, ppa1) + \
+ CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+ CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+
/* -1 from portID due to how immap has the registers */
#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];
extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+#ifdef CONFIG_SYS_SRIO
extern struct srio_liodn_id_table srio_liodn_tbl[];
+extern int srio_liodn_tbl_sz;
+#endif
extern struct liodn_id_table rman_liodn_tbl[];
extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
-extern int srio_liodn_tbl_sz;
extern int rman_liodn_tbl_sz;
#endif
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MEMAC_H__
+#define __MEMAC_H__
+
+#include <phy.h>
+
+struct memac {
+ /* memac general control and status registers */
+ u32 res_0[2];
+ u32 command_config; /* Control and configuration register */
+ u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
+ u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
+ u32 maxfrm; /* Maximum frame length register */
+ u32 res_18[5];
+ u32 hashtable_ctrl; /* Hash table control register */
+ u32 res_30[4];
+ u32 ievent; /* Interrupt event register */
+ u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
+ u32 res_48;
+ u32 imask; /* interrupt mask register */
+ u32 res_50;
+ u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
+ u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
+ u32 rx_pause_status; /* Receive pause status register */
+ u32 res_78[2];
+ u32 mac_addr[14]; /* MAC address */
+ u32 lpwake_timer; /* EEE low power wakeup timer register */
+ u32 sleep_timer; /* Transmit EEE Low Power Timer register */
+ u32 res_c0[8];
+ u32 statn_config; /* Statistics configuration register */
+ u32 res_e4[7];
+
+ /* memac statistics counter registers */
+ u32 rx_eoct_l; /* Rx ethernet octests lower */
+ u32 rx_eoct_u; /* Rx ethernet octests upper */
+ u32 rx_oct_l; /* Rx octests lower */
+ u32 rx_oct_u; /* Rx octests upper */
+ u32 rx_align_err_l; /* Rx alignment error lower */
+ u32 rx_align_err_u; /* Rx alignment error upper */
+ u32 rx_pause_frame_l; /* Rx valid pause frame upper */
+ u32 rx_pause_frame_u; /* Rx valid pause frame upper */
+ u32 rx_frame_l; /* Rx frame counter lower */
+ u32 rx_frame_u; /* Rx frame counter upper */
+ u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+ u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+ u32 rx_vlan_l; /* Rx VLAN frame lower */
+ u32 rx_vlan_u; /* Rx VLAN frame upper */
+ u32 rx_err_l; /* Rx frame error lower */
+ u32 rx_err_u; /* Rx frame error upper */
+ u32 rx_uni_l; /* Rx unicast frame lower */
+ u32 rx_uni_u; /* Rx unicast frame upper */
+ u32 rx_multi_l; /* Rx multicast frame lower */
+ u32 rx_multi_u; /* Rx multicast frame upper */
+ u32 rx_brd_l; /* Rx broadcast frame lower */
+ u32 rx_brd_u; /* Rx broadcast frame upper */
+ u32 rx_drop_l; /* Rx dropped packets lower */
+ u32 rx_drop_u; /* Rx dropped packets upper */
+ u32 rx_pkt_l; /* Rx packets lower */
+ u32 rx_pkt_u; /* Rx packets upper */
+ u32 rx_undsz_l; /* Rx undersized packet lower */
+ u32 rx_undsz_u; /* Rx undersized packet upper */
+ u32 rx_64_l; /* Rx 64 oct packet lower */
+ u32 rx_64_u; /* Rx 64 oct packet upper */
+ u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
+ u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
+ u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
+ u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
+ u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
+ u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
+ u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
+ u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
+ u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
+ u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
+ u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
+ u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
+ u32 rx_oversz_l; /* Rx oversized packet lower */
+ u32 rx_oversz_u; /* Rx oversized packet upper */
+ u32 rx_jabber_l; /* Rx Jabber packet lower */
+ u32 rx_jabber_u; /* Rx Jabber packet upper */
+ u32 rx_frag_l; /* Rx Fragment packet lower */
+ u32 rx_frag_u; /* Rx Fragment packet upper */
+ u32 rx_cnp_l; /* Rx control packet lower */
+ u32 rx_cnp_u; /* Rx control packet upper */
+ u32 rx_drntp_l; /* Rx dripped not truncated packet lower */
+ u32 rx_drntp_u; /* Rx dripped not truncated packet upper */
+ u32 res_1d0[0xc];
+
+ u32 tx_eoct_l; /* Tx ethernet octests lower */
+ u32 tx_eoct_u; /* Tx ethernet octests upper */
+ u32 tx_oct_l; /* Tx octests lower */
+ u32 tx_oct_u; /* Tx octests upper */
+ u32 res_210[0x2];
+ u32 tx_pause_frame_l; /* Tx valid pause frame lower */
+ u32 tx_pause_frame_u; /* Tx valid pause frame upper */
+ u32 tx_frame_l; /* Tx frame counter lower */
+ u32 tx_frame_u; /* Tx frame counter upper */
+ u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */
+ u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */
+ u32 tx_vlan_l; /* Tx VLAN frame lower */
+ u32 tx_vlan_u; /* Tx VLAN frame upper */
+ u32 tx_frame_err_l; /* Tx frame error lower */
+ u32 tx_frame_err_u; /* Tx frame error upper */
+ u32 tx_uni_l; /* Tx unicast frame lower */
+ u32 tx_uni_u; /* Tx unicast frame upper */
+ u32 tx_multi_l; /* Tx multicast frame lower */
+ u32 tx_multi_u; /* Tx multicast frame upper */
+ u32 tx_brd_l; /* Tx broadcast frame lower */
+ u32 tx_brd_u; /* Tx broadcast frame upper */
+ u32 res_258[0x2];
+ u32 tx_pkt_l; /* Tx packets lower */
+ u32 tx_pkt_u; /* Tx packets upper */
+ u32 tx_undsz_l; /* Tx undersized packet lower */
+ u32 tx_undsz_u; /* Tx undersized packet upper */
+ u32 tx_64_l; /* Tx 64 oct packet lower */
+ u32 tx_64_u; /* Tx 64 oct packet upper */
+ u32 tx_127_l; /* Tx 65 to 127 oct packet lower */
+ u32 tx_127_u; /* Tx 65 to 127 oct packet upper */
+ u32 tx_255_l; /* Tx 128 to 255 oct packet lower */
+ u32 tx_255_u; /* Tx 128 to 255 oct packet upper */
+ u32 tx_511_l; /* Tx 256 to 511 oct packet lower */
+ u32 tx_511_u; /* Tx 256 to 511 oct packet upper */
+ u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */
+ u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */
+ u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */
+ u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */
+ u32 tx_1519_l; /* Tx 1519 to max oct packet lower */
+ u32 tx_1519_u; /* Tx 1519 to max oct packet upper */
+ u32 res_2a8[0x6];
+ u32 tx_cnp_l; /* Tx control packet lower */
+ u32 tx_cnp_u; /* Tx control packet upper */
+ u32 res_2c8[0xe];
+
+ /* Line interface control register */
+ u32 if_mode; /* interface mode control */
+ u32 if_status; /* interface status */
+ u32 res_308[0xe];
+
+ /* HiGig/2 Register */
+ u32 hg_config; /* HiGig2 control and configuration */
+ u32 res_344[0x3];
+ u32 hg_pause_quanta; /* HiGig2 pause quanta */
+ u32 res_354[0x3];
+ u32 hg_pause_thresh; /* HiGig2 pause quanta threshold */
+ u32 res_364[0x3];
+ u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */
+ u32 hg_fifos_status; /* HiGig2 fifos status */
+ u32 rhm; /* Rx HiGig2 message counter register */
+ u32 thm;/* Tx HiGig2 message counter register */
+ u32 res_380[0x320];
+};
+
+/* COMMAND_CONFIG - command and configuration register */
+#define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
+#define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
+#define MEMAC_CMD_CFG_RXTX_EN (MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL 0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT 0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT 0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER 0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL 0xffffffff
+
+/* IF_MODE - Interface Mode Register */
+#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
+#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
+#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
+#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */
+#define IF_MODE_RG 0x00000004 /* 1- RGMII */
+#define IF_MODE_RM 0x00000008 /* 1- RGMII */
+
+#define IF_DEFAULT (IF_GMII)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET 0x8000
+#define PHY_SGMII_CR_RESET_AN 0x0200
+#define PHY_SGMII_CR_DEF_VAL 0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN 0x0002
+#define PHY_SGMII_IF_MODE_SGMII 0x0001
+
+struct memac_mdio_controller {
+ u32 res0[0xc];
+ u32 mdio_stat; /* MDIO configuration and status */
+ u32 mdio_ctl; /* MDIO control */
+ u32 mdio_data; /* MDIO data */
+ u32 mdio_addr; /* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY (1 << 0)
+#define MDIO_STAT_RD_ER (1 << 1)
+#define MDIO_STAT_PRE (1 << 5)
+#define MDIO_STAT_ENC (1 << 6)
+#define MDIO_STAT_HOLD_15_CLK (7 << 2)
+
+#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS (1 << 10)
+#define MDIO_CTL_SCAN_EN (1 << 11)
+#define MDIO_CTL_POST_INC (1 << 14)
+#define MDIO_CTL_READ (1 << 15)
+
+#define MDIO_DATA(x) (x & 0xffff)
+#define MDIO_DATA_BSY (1 << 31)
+
+struct fsl_enet_mac;
+
+void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
+ int max_rx_len);
+
+#endif
FSL_HW_PORTAL_FMAN2,
#endif
#endif
-#ifdef CONFIG_SYS_DPAA_PME
FSL_HW_PORTAL_PME,
-#endif
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
FSL_HW_PORTAL_RAID_ENGINE,
#endif
#ifdef CONFIG_SYS_DPAA_RMAN
FSL_HW_PORTAL_RMAN,
#endif
+#ifdef CONFIG_SYS_DPAA_DCE
+ FSL_HW_PORTAL_DCE,
+#endif
};
SGMII_FM1_DTSEC3,
SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
SGMII_FM2_DTSEC1,
SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3,
SGMII_FM2_DTSEC4,
SGMII_FM2_DTSEC5,
+ SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC10,
SGMII_TSEC1,
SGMII_TSEC2,
SGMII_TSEC3,
XAUI_FM1,
XAUI_FM2,
AURORA,
+ CPRI1,
+ CPRI2,
+ CPRI3,
+ CPRI4,
+ CPRI5,
+ CPRI6,
+ CPRI7,
+ CPRI8,
+ XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10,
+ XAUI_FM2_MAC9,
+ XAUI_FM2_MAC10,
+ HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10,
+ HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10,
+ QSGMII_FM1_A, /* A indicates MACs 1-4 */
+ QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
+ QSGMII_FM2_A,
+ QSGMII_FM2_B,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ XFI_FM2_MAC9,
+ XFI_FM2_MAC10,
+ INTERLAKEN,
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
+ FSL_SRDS_3 = 2,
+ FSL_SRDS_4 = 3,
};
int is_serdes_configured(enum srds_prtcl device);
void fsl_serdes_init(void);
#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+#else
int serdes_get_first_lane(enum srds_prtcl device);
+#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
void serdes_reset_rx(enum srds_prtcl device);
#endif
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#if defined(CONFIG_8xx)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+ u32 usbdr_clk;
#endif
#if defined (CONFIG_MPC834x)
u32 usbmph_clk;
u32 obir; /* Output Buffer Impedance Register */
u8 res8[0xC];
u32 pecr1; /* PCI Express control register 1 */
-#ifdef CONFIG_MPC8308
- u32 sdhccr; /* eSDHC Control Registers for MPC8308 */
+#if defined(CONFIG_MPC830x)
+ u32 sdhccr; /* eSDHC Control Registers for MPC830x */
#else
u32 pecr2; /* PCI Express control register 2 */
#endif
+#if defined(CONFIG_MPC8309)
+ u32 can_dbg_ctrl;
+ u32 res9a;
+ u32 gpr1;
+ u8 res9b[0xAC];
+#else
u8 res9[0xB8];
+#endif
} sysconf83xx_t;
/*
* On Chip ROM
*/
typedef struct rom83xx {
+#if defined(CONFIG_MPC8309)
+ u8 mem[0x8000];
+#else
u8 mem[0x10000];
+#endif
} rom83xx_t;
/*
u8 res8[0xC0000];
u8 qe[0x100000]; /* QE block */
} immap_t;
+#elif defined(CONFIG_MPC8309)
+typedef struct immap {
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t gpio[2]; /* General purpose I/O module */
+ u8 res0[0x500]; /* res0 1.25 KBytes added for 8309 */
+ qepi83xx_t qepi; /* QE Ports Interrupts Registers */
+ qepio83xx_t qepio; /* QE Parallel I/O ports */
+ u8 res1[0x800];
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
+ fsl_i2c_t i2c[2]; /* I2C Controllers */
+ u8 res2[0x1300];
+ duart83xx_t duart[2]; /* DUART */
+ u8 res3[0x200];
+ duart83xx_t duart1[2]; /* DUART */
+ u8 res4[0x500];
+ fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
+ u8 res5[0x1000];
+ u8 spi[0x100];
+ u8 res6[0xf00];
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[1]; /* PCI Configuration Registers */
+ u8 res7[0x80];
+ ios83xx_t ios; /* Sequencer (IOS) */
+ pcictrl83xx_t pci_ctrl[1]; /* PCI Control & Status Registers */
+ u8 res8[0x13A00];
+ u8 can1[0x1000]; /* Flexcan 1 */
+ u8 can2[0x1000]; /* Flexcan 2 */
+ u8 res9[0x5000];
+ usb83xx_t usb;
+ u8 res10[0x5000];
+ u8 can3[0x1000]; /* Flexcan 3 */
+ u8 can4[0x1000]; /* Flexcan 4 */
+ u8 res11[0x1000];
+ u8 dma1[0x2000]; /* DMA */
+ sdhc83xx_t sdhc; /* SDHC Controller */
+ u8 res12[0xC1000];
+ rom83xx_t rom; /* On Chip ROM */
+ u8 res13[0x8000];
+ u8 qe[0x100000]; /* QE block */
+ u8 res14[0xE00000];/* Added for 8309 */
+} immap_t;
#endif
#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
u32 cfg_addr; /* PCIX Configuration Addr */
u32 cfg_data; /* PCIX Configuration Data */
u32 int_ack; /* PCIX IRQ Acknowledge */
- u8 res1[3060];
+ u8 res000c[52];
+ u32 liodn_base; /* PCIX LIODN base register */
+ u8 res0044[3004];
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
u32 alt_pmuxcr; /* Alt function signal multiplex control */
u8 res6[12];
u32 devdisr; /* Device disable control */
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ u32 devdisr5; /* Device disable control 5 */
+#define FSL_CORENET_DEVDISR_PBL 0x80000000
+#define FSL_CORENET_DEVDISR_PMAN 0x40000000
+#define FSL_CORENET_DEVDISR_ESDHC 0x20000000
+#define FSL_CORENET_DEVDISR_DMA1 0x00800000
+#define FSL_CORENET_DEVDISR_DMA2 0x00400000
+#define FSL_CORENET_DEVDISR_USB1 0x00080000
+#define FSL_CORENET_DEVDISR_USB2 0x00040000
+#define FSL_CORENET_DEVDISR_SATA1 0x00008000
+#define FSL_CORENET_DEVDISR_SATA2 0x00004000
+#define FSL_CORENET_DEVDISR_PME 0x00000800
+#define FSL_CORENET_DEVDISR_SEC 0x00000200
+#define FSL_CORENET_DEVDISR_RMU 0x00000080
+#define FSL_CORENET_DEVDISR_DCE 0x00000040
+#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
+#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
+#define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
+#define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
+#define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
+#define FSL_CORENET_DEVDISR2_FM1 0x00000080
+#define FSL_CORENET_DEVDISR2_FM2 0x00000040
+#define FSL_CORENET_DEVDISR2_CPRI 0x00000008
+#define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
+#define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
+#define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
+#define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
+#define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
+#define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
+#define FSL_CORENET_DEVDISR3_QMAN 0x00080000
+#define FSL_CORENET_DEVDISR3_BMAN 0x00040000
+#define FSL_CORENET_DEVDISR3_LA1 0x00008000
+#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
+#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
+#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
+#define FSL_CORENET_DEVDISR4_I2C1 0x80000000
+#define FSL_CORENET_DEVDISR4_I2C2 0x40000000
+#define FSL_CORENET_DEVDISR4_DUART1 0x20000000
+#define FSL_CORENET_DEVDISR4_DUART2 0x10000000
+#define FSL_CORENET_DEVDISR4_ESPI 0x08000000
+#define FSL_CORENET_DEVDISR5_DDR1 0x80000000
+#define FSL_CORENET_DEVDISR5_DDR2 0x40000000
+#define FSL_CORENET_DEVDISR5_DDR3 0x20000000
+#define FSL_CORENET_DEVDISR5_CPC1 0x08000000
+#define FSL_CORENET_DEVDISR5_CPC2 0x04000000
+#define FSL_CORENET_DEVDISR5_CPC3 0x02000000
+#define FSL_CORENET_DEVDISR5_IFC 0x00800000
+#define FSL_CORENET_DEVDISR5_GPIO 0x00400000
+#define FSL_CORENET_DEVDISR5_DBG 0x00200000
+#define FSL_CORENET_DEVDISR5_NAL 0x00100000
+#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
+#define FSL_CORENET_NUM_DEVDISR 5
+#else
#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
#define FSL_CORENET_DEVDISR_PCIE2 0x40000000
#define FSL_CORENET_DEVDISR_PCIE3 0x20000000
#define FSL_CORENET_DEVDISR_I2C2 0x00000010
#define FSL_CORENET_DEVDISR_DUART1 0x00000002
#define FSL_CORENET_DEVDISR_DUART2 0x00000001
- u32 devdisr2; /* Device disable control 2 */
#define FSL_CORENET_DEVDISR2_PME 0x80000000
#define FSL_CORENET_DEVDISR2_SEC 0x40000000
#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
#define FSL_CORENET_NUM_DEVDISR 2
- u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
+#endif
u8 res8[12];
u32 coredisru; /* uppper portion for support of 64 cores */
u32 coredisrl; /* lower portion for support of 64 cores */
u32 brrl; /* Boot release */
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
+#elif defined(CONFIG_PPC_B4860)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
+#endif
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
+#define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
#define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
+#endif
+#if defined(CONFIG_PPC_P5040)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
+#define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
+#endif
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#endif
u8 res18[192];
u32 scratchrw[4]; /* Scratch Read/Write */
#define rmuliodnr rio1maintliodnr
typedef struct ccsr_clk {
- u32 clkc0csr; /* Core 0 Clock control/status */
+ u32 clkc0csr; /* 0x000 Core 0 Clock control/status */
u8 res1[0x1c];
- u32 clkc1csr; /* Core 1 Clock control/status */
+ u32 clkc1csr; /* 0x020 Core 1 Clock control/status */
u8 res2[0x1c];
- u32 clkc2csr; /* Core 2 Clock control/status */
+ u32 clkc2csr; /* 0x040 Core 2 Clock control/status */
u8 res3[0x1c];
- u32 clkc3csr; /* Core 3 Clock control/status */
+ u32 clkc3csr; /* 0x060 Core 3 Clock control/status */
u8 res4[0x1c];
- u32 clkc4csr; /* Core 4 Clock control/status */
+ u32 clkc4csr; /* 0x080 Core 4 Clock control/status */
u8 res5[0x1c];
- u32 clkc5csr; /* Core 5 Clock control/status */
+ u32 clkc5csr; /* 0x0a0 Core 5 Clock control/status */
u8 res6[0x1c];
- u32 clkc6csr; /* Core 6 Clock control/status */
+ u32 clkc6csr; /* 0x0c0 Core 6 Clock control/status */
u8 res7[0x1c];
- u32 clkc7csr; /* Core 7 Clock control/status */
+ u32 clkc7csr; /* 0x0e0 Core 7 Clock control/status */
u8 res8[0x71c];
- u32 pllc1gsr; /* Cluster PLL 1 General Status */
+ u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */
u8 res10[0x1c];
- u32 pllc2gsr; /* Cluster PLL 2 General Status */
+ u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */
u8 res11[0x1c];
- u32 pllc3gsr; /* Cluster PLL 3 General Status */
+ u32 pllc3gsr; /* 0x840 Cluster PLL 3 General Status */
u8 res12[0x1c];
- u32 pllc4gsr; /* Cluster PLL 4 General Status */
- u8 res13[0x39c];
- u32 pllpgsr; /* Platform PLL General Status */
+ u32 pllc4gsr; /* 0x860 Cluster PLL 4 General Status */
+ u8 res13[0x1c];
+ u32 pllc5gsr; /* 0x880 Cluster PLL 5 General Status */
u8 res14[0x1c];
- u32 plldgsr; /* DDR PLL General Status */
- u8 res15[0x3dc];
+ u32 pllc6gsr; /* 0x8a0 Cluster PLL 6 General Status */
+ u8 res15[0x35c];
+ u32 pllpgsr; /* 0xc00 Platform PLL General Status */
+ u8 res16[0x1c];
+ u32 plldgsr; /* 0xc20 DDR PLL General Status */
+ u8 res17[0x3dc];
} ccsr_clk_t;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define MAX_SERDES 4
+#define SRDS_MAX_LANES 8
+#define SRDS_MAX_BANK 2
+typedef struct serdes_corenet {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+#define SRDS_RSTCTL_RST 0x80000000
+#define SRDS_RSTCTL_RSTDONE 0x40000000
+#define SRDS_RSTCTL_RSTERR 0x20000000
+#define SRDS_RSTCTL_SWRST 0x10000000
+#define SRDS_RSTCTL_SDPD 0x00000020
+ u32 pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF 0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+ u32 pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+ u32 res_0c; /* 0x00c */
+ u32 pllcr3;
+ u32 pllcr4;
+ u8 res_18[0x20-0x18];
+ } bank[2];
+ u8 res_40[0x90-0x40];
+ u32 srdstcalcr; /* 0x90 TX Calibration Control */
+ u8 res_94[0xa0-0x94];
+ u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
+ u8 res_a4[0xb0-0xa4];
+ u32 srdsgr0; /* 0xb0 General Register 0 */
+ u8 res_b4[0xe0-0xb4];
+ u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
+ u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
+ u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
+ u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
+ u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
+ u8 res_f4[0x100-0xf4];
+ struct {
+ u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+ u8 res_104[0x120-0x104];
+ } srdslnpssr[8];
+ u8 res_200[0x800-0x200];
+ struct {
+ u32 gcr0; /* 0x800 General Control Register 0 */
+ u32 gcr1; /* 0x804 General Control Register 1 */
+ u32 gcr2; /* 0x808 General Control Register 2 */
+ u32 res_80c;
+ u32 recr0; /* 0x810 Receive Equalization Control */
+ u32 res_814;
+ u32 tecr0; /* 0x818 Transmit Equalization Control */
+ u32 res_81c;
+ u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
+ u8 res_824[0x840-0x824];
+ } lane[8]; /* Lane A, B, C, D, E, F, G, H */
+ u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
+} serdes_corenet_t;
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define SRDS_MAX_LANES 18
+#define SRDS_MAX_BANK 3
typedef struct serdes_corenet {
struct {
u32 rstctl; /* Reset Control Register */
#define SRDS_RSTCTL_RSTERR 0x20000000
#define SRDS_RSTCTL_SDPD 0x00000020
u32 pllcr0; /* PLL Control Register 0 */
-#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
u32 gcr0; /* General Control Register 0 */
#define SRDS_GCR0_RRST 0x00400000
#define SRDS_GCR0_1STLANE 0x00010000
+#define SRDS_GCR0_UOTHL 0x00100000
u32 gcr1; /* General Control Register 1 */
#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
} lane[24];
u32 res6[384];
} serdes_corenet_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
enum {
FSL_SRDS_B1_LANE_A = 0,
struct {
u32 ms; /* DECO LIODN Register, MS */
u32 ls; /* DECO LIODN Register, LS */
- } decoliodnr[5];
- u8 res4[0x58];
+ } decoliodnr[8];
+ u8 res4[0x40];
u32 dar; /* DECO Avail Register */
u32 drr; /* DECO Reset Register */
u8 res5[0xe78];
#endif
typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ u8 res0[0x200];
+#else
struct {
u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
u32 res;
u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
} qcsp[32];
-
+#endif
/* Not actually reserved, but irrelevant to u-boot */
u8 res[0xbf8 - 0x200];
u32 ip_rev_1;
u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
u8 res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+ struct {
+ u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
+ u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
+ u32 res;
+ u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
+ } qcsp[50];
+#endif
} ccsr_qman_t;
typedef struct ccsr_bman {
};
#endif
+#ifdef CONFIG_SYS_PMAN
+struct ccsr_pman {
+ u8 res_00[0x40];
+ u32 poes1; /* PMAN Operation Error Status Register 1 */
+ u32 poes2; /* PMAN Operation Error Status Register 2 */
+ u32 poeah; /* PMAN Operation Error Address High */
+ u32 poeal; /* PMAN Operation Error Address Low */
+ u8 res_50[0x50];
+ u32 pr1; /* PMAN Revision Register 1 */
+ u32 pr2; /* PMAN Revision Register 2 */
+ u8 res_a8[0x8];
+ u32 pcap; /* PMAN Capabilities Register */
+ u8 res_b4[0xc];
+ u32 pc1; /* PMAN Control Register 1 */
+ u32 pc2; /* PMAN Control Register 2 */
+ u32 pc3; /* PMAN Control Register 3 */
+ u32 pc4; /* PMAN Control Register 4 */
+ u32 pc5; /* PMAN Control Register 5 */
+ u32 pc6; /* PMAN Control Register 6 */
+ u8 res_d8[0x8];
+ u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
+ u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
+ u8 res_e8[0x8];
+ u32 pics; /* PMAN Interrupt Control and Status */
+ u8 res_f4[0xf0c];
+};
+#endif
+
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#ifdef CONFIG_SYS_PMAN
+#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
+#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
+#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
+#endif
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
+#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
+#else
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
+#endif
#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
#define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
+#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
+#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
+#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
#define CONFIG_SYS_MPC85xx_USB_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+struct ccsr_cluster_l2 {
+ u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
+ u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
+ u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
+ u8 res_0c[500];/* 0x00c - 0x1ff */
+ u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
+ u8 res_204[4];
+ u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
+ u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
+ u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
+ u8 res_214[4];
+ u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
+ u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
+ u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
+ u8 res_224[4];
+ u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
+ u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
+ u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
+ u8 res_234[4];
+ u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
+ u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
+ u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
+ u8 res244[4];
+ u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
+ u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
+ u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
+ u8 res_254[4];
+ u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
+ u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
+ u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
+ u8 res_264[4];
+ u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
+ u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
+ u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
+ u8 res274[4];
+ u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
+ u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
+ u8 res_280[0xb80]; /* 0x280 - 0xdff */
+ u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
+ u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
+ u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
+ u8 res_e0c[20]; /* 0xe0c - 0x01f */
+ u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
+ u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
+ u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
+ u8 res_e2c[20]; /* 0xe2c - 0xe3f */
+ u32 l2errdet; /* 0xe40 L2 cache error detect */
+ u32 l2errdis; /* 0xe44 L2 cache error disable */
+ u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
+ u32 l2errattr; /* 0xe4c L2 cache error attribute */
+ u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
+ u32 l2erraddr; /* 0xe54 L2 cache error address */
+ u32 l2errctl; /* 0xe58 L2 cache error control */
+};
+#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#endif /*__IMMAP_85xx__*/
#define QE_MURAM_SIZE 0xc000UL
#define MAX_QE_RISC 2
#define QE_NUM_OF_SNUM 28
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
#define QE_MURAM_SIZE 0x4000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
void setup_mp(void);
void cpu_mp_lmb_reserve(struct lmb *lmb);
-u32 determine_mp_bootpg(void);
+u32 determine_mp_bootpg(unsigned int *pagesize);
int is_core_disabled(int nr);
#ifdef CONFIG_E6500
static inline int gpio_direction_output(unsigned gpio, int value)
{
- mpc85xx_gpio_set_low(1U << gpio);
+ if (value)
+ mpc85xx_gpio_set_high(1U << gpio);
+ else
+ mpc85xx_gpio_set_low(1U << gpio);
return 0;
}
#define SVR_P4080 0x820000
#define SVR_P5010 0x822100
#define SVR_P5020 0x822000
+#define SVR_P5021 0X820500
+#define SVR_P5040 0x820400
+#define SVR_T4240 0x824000
+#define SVR_T4120 0x824001
+#define SVR_B4860 0X868000
+#define SVR_G4860 0x868001
+#define SVR_G4060 0x868003
+#define SVR_B4440 0x868100
+#define SVR_G4440 0x868101
+#define SVR_B4420 0x868102
+#define SVR_B4220 0x868103
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
COBJS-y += extable.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
+COBJS-${CONFIG_CMD_IDE} += ide.o
COBJS-y += time.o
# Workaround for local bus unaligned access problems
* We need to make sure the location we intend to put secondary core
* boot code is reserved and not used by any part of u-boot
*/
- if (addr > determine_mp_bootpg()) {
- addr = determine_mp_bootpg();
+ if (addr > determine_mp_bootpg(NULL)) {
+ addr = determine_mp_bootpg(NULL);
debug("Reserving MP boot page to %08lx\n", addr);
}
#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Code taken from cmd_ide.c */
+#include <common.h>
+#include <ata.h>
+#include "ide.h"
+
+#ifdef CONFIG_IDE_8xx_DIRECT
+#include <mpc8xx.h>
+#include <pcmcia.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timings for IDE Interface
+ *
+ * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk
+ * 70 165 30 PIO-Mode 0, [ns]
+ * 4 9 2 [Cycles]
+ * 50 125 20 PIO-Mode 1, [ns]
+ * 3 7 2 [Cycles]
+ * 30 100 15 PIO-Mode 2, [ns]
+ * 2 6 1 [Cycles]
+ * 30 80 10 PIO-Mode 3, [ns]
+ * 2 5 1 [Cycles]
+ * 25 70 10 PIO-Mode 4, [ns]
+ * 2 4 1 [Cycles]
+ */
+
+static const pio_config_t pio_config_ns[IDE_MAX_PIO_MODE+1] = {
+ /* Setup Length Hold */
+ { 70, 165, 30 }, /* PIO-Mode 0, [ns] */
+ { 50, 125, 20 }, /* PIO-Mode 1, [ns] */
+ { 30, 101, 15 }, /* PIO-Mode 2, [ns] */
+ { 30, 80, 10 }, /* PIO-Mode 3, [ns] */
+ { 25, 70, 10 }, /* PIO-Mode 4, [ns] */
+};
+
+static pio_config_t pio_config_clk[IDE_MAX_PIO_MODE+1];
+
+#ifndef CONFIG_SYS_PIO_MODE
+#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */
+#endif
+static int pio_mode = CONFIG_SYS_PIO_MODE;
+
+/* Make clock cycles and always round up */
+
+#define PCMCIA_MK_CLKS(t, T) (((t) * (T) + 999U) / 1000U)
+
+static void set_pcmcia_timing(int pmode)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+ ulong timings;
+
+ debug("Set timing for PIO Mode %d\n", pmode);
+
+ timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold)
+ | PCMCIA_SST(pio_config_clk[pmode].t_setup)
+ | PCMCIA_SL(pio_config_clk[pmode].t_length);
+
+ /*
+ * IDE 0
+ */
+ pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0;
+#if (CONFIG_SYS_PCMCIA_POR0 != 0)
+ pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 | timings;
+#else
+ pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0;
+#endif
+ debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0);
+
+ pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1;
+#if (CONFIG_SYS_PCMCIA_POR1 != 0)
+ pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 | timings;
+#else
+ pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1;
+#endif
+ debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1);
+
+ pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2;
+#if (CONFIG_SYS_PCMCIA_POR2 != 0)
+ pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 | timings;
+#else
+ pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2;
+#endif
+ debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2);
+
+ pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3;
+#if (CONFIG_SYS_PCMCIA_POR3 != 0)
+ pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 | timings;
+#else
+ pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3;
+#endif
+ debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3);
+
+ /*
+ * IDE 1
+ */
+ pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4;
+#if (CONFIG_SYS_PCMCIA_POR4 != 0)
+ pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 | timings;
+#else
+ pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4;
+#endif
+ debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4);
+
+ pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5;
+#if (CONFIG_SYS_PCMCIA_POR5 != 0)
+ pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 | timings;
+#else
+ pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5;
+#endif
+ debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5);
+
+ pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6;
+#if (CONFIG_SYS_PCMCIA_POR6 != 0)
+ pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 | timings;
+#else
+ pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6;
+#endif
+ debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6);
+
+ pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7;
+#if (CONFIG_SYS_PCMCIA_POR7 != 0)
+ pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 | timings;
+#else
+ pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7;
+#endif
+ debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7);
+
+}
+
+int ide_preinit(void)
+{
+ int i;
+ /* Initialize PIO timing tables */
+ for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) {
+ pio_config_clk[i].t_setup =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk);
+ pio_config_clk[i].t_length =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_length, gd->bus_clk);
+ pio_config_clk[i].t_hold =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk);
+ debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk"
+ " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup,
+ pio_config_clk[i].t_setup, pio_config_ns[i].t_length,
+ pio_config_clk[i].t_length, pio_config_ns[i].t_hold,
+ pio_config_clk[i].t_hold);
+ }
+
+ return 0;
+}
+
+int ide_init_postreset(void)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+
+ /* PCMCIA / IDE initialization for common mem space */
+ pcmp->pcmc_pgcrb = 0;
+
+ /* start in PIO mode 0 - most relaxed timings */
+ pio_mode = 0;
+ set_pcmcia_timing(pio_mode);
+ return 0;
+}
+#endif /* CONFIG_IDE_8xx_DIRECT */
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+int ide_preinit(void)
+{
+ ide_devices_found = 0;
+ /* initialize the PCMCIA IDE adapter card */
+ pcmcia_on();
+ if (!ide_devices_found)
+ return 1;
+ udelay(1000000);/* 1 s */
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _MPC8XX_IDE_H_
+#define _MPC8XX_IDE_H_ 1
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+int pcmcia_on(void);
+extern int ide_devices_found;
+#endif
+#endif
SECTIONS
{
- __u_boot_cmd_start = .;
- _u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__u_boot_sandbox_option_start = .;
_u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
{
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
unsigned long bi_boot_params; /* where this board expects params */
} bd_t;
leon2_serial_putc_raw(c);
}
-static void leon2_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
static int leon2_serial_getc(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
.stop = NULL,
.setbrg = leon2_serial_setbrg,
.putc = leon2_serial_putc,
- .puts = leon2_serial_puts,
+ .puts = default_serial_puts,
.getc = leon2_serial_getc,
.tstc = leon2_serial_tstc,
};
leon3_serial_putc_raw(c);
}
-static void leon3_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
static int leon3_serial_getc(void)
{
if (!leon3_apbuart)
.stop = NULL,
.setbrg = leon3_serial_setbrg,
.putc = leon3_serial_putc,
- .puts = leon3_serial_puts,
+ .puts = default_serial_puts,
.getc = leon3_serial_getc,
.tstc = leon3_serial_tstc,
};
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
.text : { *(.text*); }
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
unsigned long gd_addr; /* Location of Global Data */
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
#endif /* CONFIG_MPSC */
-static void marvell_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device marvell_serial_drv = {
.name = "marvell_serial",
.start = marvell_serial_init,
.stop = NULL,
.setbrg = marvell_serial_setbrg,
.putc = marvell_serial_putc,
- .puts = marvell_serial_puts,
+ .puts = default_serial_puts,
.getc = marvell_serial_getc,
.tstc = marvell_serial_tstc,
};
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ } >.sram
+ . = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
*/
OUTPUT_ARCH(m68k)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/m68k/cpu/mcf532x/start.o (.text)
- arch/m68k/lib/traps.o (.text)
- arch/m68k/lib/interrupts.o (.text)
- common/dlmalloc.o (.text)
- lib/zlib.o (.text)
+ arch/m68k/cpu/mcf532x/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text*)
- *(.text)
-/* *(.fixup)*/
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
.reloc :
{
__got_start = .;
- *(.got)
+ KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
.bss :
{
_sbss = .;
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
+++ /dev/null
-Broadcom 95xx BMW CPCI Platform
-
-Overview
-=========
-BMW is an MPC8245 system controller featuring:
-* 3U CPCI Form Factor
-* BCM5703 Gigabit Ethernet
-* M48T59Y NVRAM
-* 16MB DOC
-* DIP Socket for Socketed DOC up to 1GB
-* 64MB SDRAM
-* LCD Display
-* Configurable Jumper options for 66,85, and 100Mhz memory bus
-
-
-BMW System Address Map
-======================
-BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual
-(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found
-onboard the processor module are listed briefly below:
-
-0x00000000 - 0x40000000 - 64MB SDRAM SIMM
- (Unregistered PC-100 SDRAM DIMM Module)
-
-0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000
- TSOP 16MB (MD2211-D16-V3)
-
-0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000
- DIP32 (Socketed 16MB - 1GB ) *
- NOTE: this is not populated on all systems.
-
-0x7c000000 - 0x7c000000 - Reset Register
- (Write 0 to reset)
-
-0x7c000001 - 0x7c000001 - System LED
- (Clear Bit 7 to turn on, set to shut off)
-
-0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3
- (Clear bit 7 to reset, set to assert IRQ3)
-
-0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register
- (Clear bit 7 to make R/W, set to make R/O)
-
-0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character
- 5x7 Dot Matrix Alphanumeric Display
- (Each byte sets the appropriate character)
-
-0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC
- NVRAM Memory Region
-
-0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC
- Realtime Clock Registers
-
-0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom
- (AMD AM29F040, ST 29W040B)
-
-0xFFF00100 - System Reset Vector
-
-
-IO/MMU (BAT) Configuration
-======================
-The following Block-Address-Translation (BAT) configuration
-is recommended to access all I/O devices.
-
-#define CONFIG_SYS_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-
-Interrupt Mappings
-======================
-BMW uses MPC8245 discrete mode interrupts. With the following
-hardwired mappings:
-
-BCM5701 10/100/1000 Ethernet IRQ1
-CompactPCI Interrupt A IRQ2
-RTC/Watchdog Interrupt IRQ3
-Internal NS16552 UART IRQ4
-
-
-Jumper Settings
-======================
-
-BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus.
-A jumper (X) is a 0 bit.
-
-Hence 66= 10110
- 85= 11000
- 100= 10000
-
-Jumper Settings for various Speeds
-=======================
-J1 J2 J3 J4 J5
- X X 66Mhz
-=======================
-J1 J2 J3 J4 J5
- X X X 85Mhz
-=======================
-J1 J2 J3 J4 J5
- X X X X 100Mhz
-=======================
-
-Obviously, 100Mhz memory bus is recommended for optimum performance.
-
-
-U-Boot
-===============
-Broadcom BMW board is supported under config_BWM option.
-Supported features:
-
-- NVRAM setenv/getenv (used by Linux Kernel for configuration variables)
-- BCM570x TFTP file transfer support
-- LCD Display Support
-- DOC Support - (underway)
-
-
-U-Boot 1.2.0 (Aug 6 2002 - 17:44:48)
-
-CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug 6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM: 64 MB
-FLASH: 4095 MB
-In: serial
-Out: serial
-Err: serial
-DOC: No DiskOnChip found
-Hit any key to stop autoboot: 0
-=>printenv
-bootdelay=5
-baudrate=9600
-clocks_in_mhz=1
-hostname=switch-2
-bootcmd=tftp 100000 vmlinux.img;bootm
-gateway=10.16.64.1
-ethaddr=00:00:10:18:10:10
-nfsroot=172.16.40.111:/boot/root-fs
-filesize=5ec8c
-netmask=255.255.240.0
-ipaddr=172.16.40.114
-serverip=172.16.40.111
-root=/dev/nfs
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 315/8172 bytes
-=>boot
-
-
-DevTools
-========
-ELDK
- DENX Embedded Linux Development Kit
-
-ROM Emulator
- Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time)
- Grammar Engine PL32E 32Pin PLCC Emulation cables
- Grammar Engine 3VA8CON (3Volt adapter with Short cables)
- Grammar Engine FPNET PromICE Ethernet Adapters
-
-ICE
- WRS/EST VisionICE-II (PPC8240)
-
-
-=>reset
-
-
-U-Boot 1.2.0 (Aug 6 2002 - 17:44:48)
-
-CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug 6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM: 64 MB
-FLASH: 4095 MB
-In: serial
-Out: serial
-Err: serial
-DOC: No DiskOnChip found
-Hit any key to stop autoboot: 0
-
-Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000
-BCM570x PCI Memory base address @0x80100000
-eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF
-eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010
-eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found
-eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON
-ARP broadcast 1
-TFTP from server 172.16.40.111; our IP address is 172.16.40.114
-Filename 'vmlinux.img'.
-Load address: 0x100000
-Loading: #################################################################
- ####################################T #############################
- ######################
-done
-Bytes transferred = 777199 (bdbef hex)
-
-eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline.
-## Booting image at 00100000 ...
- Image Name: vmlinux.bin.gz
- Created: 2002-08-06 6:30:13 UTC
- Image Type: PowerPC Linux Kernel Image (gzip compressed)
- Data Size: 777135 Bytes = 758 kB = 0 MB
- Load Address: 00000000
- Entry Point: 00000000
- Verifying Checksum ... OK
- Uncompressing Kernel Image ... OK
-Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002
-CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000
-U-Boot Environment: 0xc01b08f0
-IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10>
-cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e
-NOTICE: mounting root file system via NFS
-IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111
-On node 0 totalpages: 16384
-zone(0): 16384 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111
-root_dev_setup:/dev/nfs or 00:ff
-time_init: decrementer frequency = 16.501145 MHz
-Calibrating delay loop... 175.71 BogoMIPS
-Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem)
-Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
-Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
-Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
-Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
-Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
-POSIX conformance testing by UNIFIX
-PCI: Probing PCI hardware
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Initializing RT netlink socket
-Starting kswapd
-devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au)
-devfs: devfs_debug: 0x0
-devfs: boot_options: 0x1
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
-pty: 256 Unix98 ptys configured
-Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
-Testing ttyS0 (0xf7f51500, 0xf7f51500)...
-Testing ttyS1 (0xfc004600, 0xfc004600)...
-ttyS00 at 0xf7f51500 (irq = 24) is a ST16650
-ttyS01 at 0xfc004600 (irq = 25) is a 16550A
-Real Time Clock Driver v1.10e
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-loop: loaded (max 8 devices)
-TFFS 5.1.1 Flash disk driver for DiskOnChip
-Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd.
-DOC device(s) found: 1
-fl_init: registered device at major: 100
-fl_geninit: registered device at major: 100
-Partition check:
- fla: p1
-partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB
-partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB
-partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02)
-eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010
-eth0: Broadcom BCM5701 Integrated Copper transceiver found
-eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON
-bond0 registered without MII link monitoring, in bonding mode.
-rtc: unable to get misc minor
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP, IGMP
-IP: routing cache hash table of 512 buckets, 4Kbytes
-TCP: Hash tables configured (established 4096 bind 4096)
-bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex
-IP-Config: Gateway not on directly connected network.
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-802.1Q VLAN Support v1.7 Ben Greear <greearb@candelatech.com>
-All bugs added by David S. Miller <davem@redhat.com>
-Looking up port of RPC 100003/2 on 172.16.40.111
-Looking up port of RPC 100005/1 on 172.16.40.111
-VFS: Mounted root (nfs filesystem).
-Mounted devfs on /dev
-Freeing unused kernel memory: 100k init
-INIT: version 2.78 booting
-Mounting local filesystems...
-not mounted anything
-Setting up symlinks in /dev...done.
-Setting up extra devices in /dev...done.
-Starting devfsd...Started device management daemon for /dev
-INIT: Entering runlevel: 2
-Starting internet superserver: inetd.
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-switch-2 login: root
-Password:
-PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0)
-Last login: Thu Nov 25 11:51:14 1920 on console
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-login[49]: ROOT LOGIN on `console'
-
-root@switch-2:~# cat /proc/cpuinfo
-cpu : 82xx
-revision : 16.20 (pvr 8081 1014)
-bogomips : 175.71
-vendor : Broadcom
-machine : BMW/MPC8245
-root@switch-2:~#
+++ /dev/null
-/*
- * (C) Copyright 2002
- * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <net.h>
-#include <timestamp.h>
-#include <dtt.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <linux/mtd/doc2000.h>
-
-#include "bmw.h"
-#include "m48t59y.h"
-#include <pci.h>
-
-
-int checkboard(void)
-{
- ulong busfreq = get_bus_freq(0);
- char buf[32];
-
- puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
- printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
- /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */
- printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- return 64*1024*1024;
-}
-
-
-void
-get_tod(void)
-{
- int year, month, day, hour, minute, second;
-
- m48_tod_get(&year,
- &month,
- &day,
- &hour,
- &minute,
- &second);
-
- printf(" Current date/time: %d/%d/%d %d:%d:%d \n",
- month, day, year, hour, minute, second);
-
-}
-
-/*
- * EPIC, PCI, and I/O devices.
- * Initialize Mousse Platform, probe for PCI devices,
- * Query configuration parameters if not set.
- */
-int misc_init_f (void)
-{
-#if 0
- m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */
- printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n",
- TOD_NVRAM_SIZE);
- get_tod();
-#endif
-
- sys_led_msg("BOOT");
- return 0;
-}
-
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-struct pci_controller hose;
-
-void pci_init_board (void)
-{
- pci_mpc824x_init(&hose);
- /* pci_dev_init(0); */
-}
-
-/*
- * Write characters to LCD display.
- * Note that the bytes for the first character is the last address.
- */
-void
-sys_led_msg(char* msg)
-{
- LED_REG(0) = msg[3];
- LED_REG(1) = msg[2];
- LED_REG(2) = msg[1];
- LED_REG(3) = msg[0];
-}
-
-#ifdef CONFIG_CMD_DOC
-/*
- * Map onboard TSOP-16MB DOC FLASH chip.
- */
-void doc_init (void)
-{
- doc_probe(DOC_BASE_ADDR);
-}
-#endif
-
-#define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR)
-
-/* Read from NVRAM */
-void*
-nvram_read(void *dest, const long src, size_t count)
-{
- int i;
- volatile unsigned char* d = (unsigned char*)dest;
- volatile unsigned char* s = (unsigned char*)src;
-
- for( i = 0; i < count;i++)
- d[i] = s[i];
-
- return dest;
-}
-
-/* Write to NVRAM */
-void
-nvram_write(long dest, const void *src, size_t count)
-{
- int i;
- volatile unsigned char* d = (unsigned char*)dest;
- volatile unsigned char* s = (unsigned char*)src;
-
- SYS_TOD_UNPROTECT();
-
- for( i = 0; i < count;i++)
- d[i] = s[i];
-
- SYS_TOD_PROTECT();
-}
+++ /dev/null
-/*
- * BMW/MPC8245 Board definitions.
- * For more info, see http://www.vooha.com/
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * James Dougherty (jfd@broadcom.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BMW_H
-#define __BMW_H
-
-/* System addresses */
-
-#define PCI_SPECIAL_BASE 0xfe000000
-#define PCI_SPECIAL_SIZE 0x01000000
-
-#define EUMBBAR_VAL 0x80500000 /* Location of EUMB region */
-#define EUMBSIZE 0x00100000 /* Size of EUMB region */
-
-/* Extended ROM space devices */
-#define DOC_BASE_ADDR 0xff000000 /* Onboard DOC TSOP 16MB */
-#define DOC2_BASE_ADDR 0x70000000 /* DIP32 socket -> 1GB */
-#define XROM_BASE_ADDR 0x7c000000 /* RCS2 (PAL / Satellite IO) */
-#define PLD_REG_BASE XROM_BASE_ADDR
-#define LED_REG_BASE (XROM_BASE_ADDR | 0x2000)
-#define TOD_BASE (XROM_BASE_ADDR | 0x4000)
-#define LED_REG(x) (*(volatile unsigned char *) \
- (LED_REG_BASE + (x)))
-#define XROM_DEV_SIZE 0x00006000
-
-#define ENET_DEV_BASE 0x80000000
-
-#define PLD_REG(off) (*(volatile unsigned char *)\
- (PLD_REG_BASE + (off)))
-
-#define PLD_REVID_B1 0x7f /* Fix me */
-#define PLD_REVID_B2 0x01 /* Fix me */
-
-#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
-#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f)
-#define SYS_LED_OFF() (PLD_REG(1) |= 0x80)
-#define SYS_LED_ON() (PLD_REG(1) &= ~0x80)
-#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80)
-#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80)
-#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80)
-#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80)
-
-#define TOD_REG_BASE (TOD_BASE | 0x1ff0)
-#define TOD_NVRAM_BASE TOD_BASE
-#define TOD_NVRAM_SIZE 0x1ff0
-#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
-#define RTC(r) (TOD_BASE + r)
-
-/* Onboard BCM570x device */
-#define PCI_ENET_IOADDR 0x80000000
-#define PCI_ENET_MEMADDR 0x80000000
-
-
-#ifndef __ASSEMBLY__
-/* C Function prototypes */
-void sys_led_msg(char* msg);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __BMW_H */
+++ /dev/null
-#include <ppc_asm.tmpl>
-#include <mpc824x.h>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */
-
-
-/*
- * Initialize the MMU using BAT entries and hardwired TLB
- * This obviates the need for any code in cpu_init_f which
- * configures the BAT registers.
-*/
-#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */
- .global iommu_setup
- /* Initialize IO/MMU mappings via BAT method Ch. 7,
- * PPC Programming Reference
- */
-iommu_setup:
-
-/* initialize the BAT registers (SPRs 528 - 543 */
-#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */
-#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */
-#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */
-#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */
-#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */
-#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */
-#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */
-#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */
-#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */
-#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */
-#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */
-#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */
-#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */
-#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */
-#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */
-#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */
-
-
-/* PowerPC processors do not necessarily initialize the BAT
- registers on power-up or reset. So they are in an unknown
- state. Before programming the BATs for the first time, all
- BAT registers MUST have their Vs and Vp bits cleared in the
- upper BAT half in order to avoid possibly having 2 BATs
- valid and mapping the same memory region.
-
- The reason for this is that, even with address translation
- disabled, multiple BAT hits for an address are treated as
- programming errors and can cause unpredictable results.
-
- It is up to the software to make sure it never has 2 IBAT
- mappings or 2 DBAT mappings that are valid for the same
- addresses. It is not necessary to perform this code
- sequence every time the BATs are programmed, only when
- there is a possibility that there may be overlapping BAT
- entries.
-
- When programming the BATs in non-reset scenarios, even if
- you are sure that your new mapping will not temporarily
- create overlapping regions, it is still a wise idea to
- invalidate a BAT entry by setting its upper BAT register to
- all 0's before programming it. This will avoid having a
- BAT marked valid that is in an unknown or transient state
-*/
-
- addis r5,0,0x0000
- mtibat0u(r5)
- mtibat0l(r5)
- mtibat1u(r5)
- mtibat1l(r5)
- mtibat2u(r5)
- mtibat2l(r5)
- mtibat3u(r5)
- mtibat3l(r5)
- mtdbat0u(r5)
- mtdbat0l(r5)
- mtdbat1u(r5)
- mtdbat1l(r5)
- mtdbat2u(r5)
- mtdbat2l(r5)
- mtdbat3u(r5)
- mtdbat3l(r5)
- isync
-
-/*
- * Set up I/D BAT0
- */
- lis r4, CONFIG_SYS_DBAT0L@h
- ori r4, r4, CONFIG_SYS_DBAT0L@l
- lis r3, CONFIG_SYS_DBAT0U@h
- ori r3, r3, CONFIG_SYS_DBAT0U@l
-
- mtdbat0l(r4)
- isync
- mtdbat0u(r3)
- isync
- sync
-
- lis r4, CONFIG_SYS_IBAT0L@h
- ori r4, r4, CONFIG_SYS_IBAT0L@l
- lis r3, CONFIG_SYS_IBAT0U@h
- ori r3, r3, CONFIG_SYS_IBAT0U@l
-
- isync
- mtibat0l(r4)
- isync
- mtibat0u(r3)
- isync
-
-/*
- * Set up I/D BAT1
- */
- lis r4, CONFIG_SYS_IBAT1L@h
- ori r4, r4, CONFIG_SYS_IBAT1L@l
- lis r3, CONFIG_SYS_IBAT1U@h
- ori r3, r3, CONFIG_SYS_IBAT1U@l
-
- isync
- mtibat1l(r4)
- isync
- mtibat1u(r3)
- isync
- mtdbat1l(r4)
- isync
- mtdbat1u(r3)
- isync
- sync
-
-/*
- * Set up I/D BAT2
- */
- lis r4, CONFIG_SYS_IBAT2L@h
- ori r4, r4, CONFIG_SYS_IBAT2L@l
- lis r3, CONFIG_SYS_IBAT2U@h
- ori r3, r3, CONFIG_SYS_IBAT2U@l
-
- isync
- mtibat2l(r4)
- isync
- mtibat2u(r3)
- isync
- mtdbat2l(r4)
- isync
- mtdbat2u(r3)
- isync
- sync
-
-/*
- * Setup I/D BAT3
- */
- lis r4, CONFIG_SYS_IBAT3L@h
- ori r4, r4, CONFIG_SYS_IBAT3L@l
- lis r3, CONFIG_SYS_IBAT3U@h
- ori r3, r3, CONFIG_SYS_IBAT3U@l
-
- isync
- mtibat3l(r4)
- isync
- mtibat3u(r3)
- isync
- mtdbat3l(r4)
- isync
- mtdbat3u(r3)
- isync
- sync
-
-
-/*
- * Invalidate all 64 TLB's
- */
- lis r3, 0
- mtctr r3
- lis r5, 4
-
-tlblp:
- tlbie r3
- sync
- addi r3, r3, 0x1000
- cmplw r3, r5
- blt tlblp
-
- sync
-
-/*
- * Enable Data Translation
- */
- lis r4, MEMORY_MGMT_MSR_BITS@h
- ori r4, r4, MEMORY_MGMT_MSR_BITS@l
- mfmsr r3
- or r3, r4, r3
- mtmsr r3
- isync
- sync
-
- blr
-
-
-#ifdef USE_V2_INIT
-/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */
-/* Macro for hiadjust and lo */
-#define HIADJ(arg) arg@ha
-#define HI(arg) arg@h
-#define LO(arg) arg@l
-
-#undef LOADPTR
-#define LOADPTR(reg,const32) \
- addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
-
-.globl early_init_f
-
-early_init_f:
-/* MPC8245/BMW CPCI System Init
- * Jimmy Blair, Broadcom Corp, 2002.
- */
- mflr r11
- /* Zero-out registers */
-
- addis r0,r0,0
- mtspr SPRG0,r0
- mtspr SPRG1,r0
- mtspr SPRG2,r0
- mtspr SPRG3,r0
-
- /* Set MPU/MSR to a known state. Turn on FP */
-
- LOADPTR (r3, MSR_FP)
- sync
- mtmsr r3
- isync
-
- /* Init the floating point control/status register */
-
- mtfsfi 7,0x0
- mtfsfi 6,0x0
- mtfsfi 5,0x0
- mtfsfi 4,0x0
- mtfsfi 3,0x0
- mtfsfi 2,0x0
- mtfsfi 1,0x0
- mtfsfi 0,0x0
- isync
-
- /* Set MPU/MSR to a known state. Turn off FP */
-
-#if 1 /* Turn off floating point (remove to keep FP on) */
- andi. r3, r3, 0
- sync
- mtmsr r3
- isync
-#endif
-
- /* Init the Segment registers */
-
- andi. r3, r3, 0
- isync
- mtsr 0,r3
- isync
- mtsr 1,r3
- isync
- mtsr 2,r3
- isync
- mtsr 3,r3
- isync
- mtsr 4,r3
- isync
- mtsr 5,r3
- isync
- mtsr 6,r3
- isync
- mtsr 7,r3
- isync
- mtsr 8,r3
- isync
- mtsr 9,r3
- isync
- mtsr 10,r3
- isync
- mtsr 11,r3
- isync
- mtsr 12,r3
- isync
- mtsr 13,r3
- isync
- mtsr 14,r3
- isync
- mtsr 15,r3
- isync
-
- /* Turn off data and instruction cache control bits */
-
- mfspr r3, HID0
- isync
- rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */
- sync
- isync
- mtspr HID0, r4 /* HID0 = r4 */
- isync
-
- /* Get cpu type */
-
- mfspr r28, PVR
- rlwinm r28, r28, 16, 16, 31
-
- /* invalidate the MPU's data/instruction caches */
-
- lis r3, 0x0
- cmpli 0, 0, r28, CPU_TYPE_603
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_603E
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_603P
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_604R
- bne cpuNot604R
-
-cpuIs604R:
- lis r3, 0x0
- mtspr HID0, r3 /* disable the caches */
- isync
- ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */
-
-cpuNot604R:
- ori r3, r3, (HID0_ICFI |HID0_DCI)
-
-cpuIs603:
- ori r3, r3, (HID0_ICE | HID0_DCE)
- or r4, r4, r3 /* set bits */
- sync
- isync
- mtspr HID0, r4 /* HID0 = r4 */
- andc r4, r4, r3 /* clear bits */
- isync
- cmpli 0, 0, r28, CPU_TYPE_604
- beq cpuIs604
- cmpli 0, 0, r28, CPU_TYPE_604E
- beq cpuIs604
- cmpli 0, 0, r28, CPU_TYPE_604R
- beq cpuIs604
- mtspr HID0, r4
- isync
-
-#ifdef USER_I_CACHE_ENABLE
- b instCacheOn603
-#else
- b cacheEnableDone
-#endif
-
-cpuIs604:
- LOADPTR (r5, 0x1000) /* loop count, 0x1000 */
- mtspr CTR, r5
-loopDelay:
- nop
- bdnz loopDelay
- isync
- mtspr HID0, r4
- isync
-
- /* turn the Instruction cache ON for faster FLASH ROM boots */
-
-#ifdef USER_I_CACHE_ENABLE
-
- ori r4, r4, (HID0_ICE | HID0_ICFI)
- isync /* Synchronize for ICE enable */
- b writeReg4
-instCacheOn603:
- ori r4, r4, (HID0_ICE | HID0_ICFI)
- rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
-
- /*
- * The setting of the instruction cache enable (ICE) bit must be
- * preceded by an isync instruction to prevent the cache from being
- * enabled or disabled while an instruction access is in progress.
- */
- isync
-writeReg4:
- mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
- cmpli 0, 0, r28, CPU_TYPE_604
- beq cacheEnableDone
- cmpli 0, 0, r28, CPU_TYPE_604E
- beq cacheEnableDone
-
- mtspr HID0, r3 /* using 2 consec instructions */
- /* PPC603 recommendation */
-#endif
-cacheEnableDone:
-
- /* Detect map A or B */
-
- addis r5,r0, HI(CHRP_REG_ADDR)
- addis r6,r0, HI(CHRP_REG_DATA)
- LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */
- LOADPTR (r8, BMC_BASE)
-
- stwbrx r8,0,(r5)
- lwbrx r3,0,(r6) /* Store read value to r3 */
- cmp 0,0,r3,r7
- beq cr0, X4_KAHLUA_START
-
- /* It's not an 8240, is it an 8245? */
-
- LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */
- cmp 0,0,r3,r7
- beq cr0, X4_KAHLUA_START
-
- /* Save the PCI controller type in r7 */
- mr r7, r3
-
- LOADPTR (r5, PREP_REG_ADDR)
- LOADPTR (r6, PREP_REG_DATA)
-
-X4_KAHLUA_START:
- /* MPC8245 changes begin here */
- LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */
- stwbrx r3,0,r5
- li r4, 6 /* Command register value */
- sthbrx r4, 0, r6
-
- LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */
- stwbrx r3,0,r5
- li r4, -1 /* Write-to-clear all bits */
- li r3, 2 /* PCI_STATUS is at +2 offset */
- sthbrx r4, r3, r6
-
- /*-------PROC_INT1_ADR */
-
- LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xff141b98)
- stwbrx r4,0,r6
-
- /*-------PROC_INT2_ADR */
-
- LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */
- stwbrx r3,0,r5
- lis r4, 0x2000 /* Flush PCI config writes */
- stwbrx r4,0,r6
-
- LOADPTR (r9, KAHLUA2_ID)
- cmpl 0, 0, r7, r9
- bne L1not8245
-
- /* MIOCR1 -- turn on bit for DLL delay */
-
- LOADPTR (r3, MIOCR1_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x04
- stb r4, MIOCR1_SHIFT(r6)
-
- /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
- /* SDRAM_CLK_DEL (0x77)*/
-
- LOADPTR (r3, MIOCR2_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x10
- stb r4, MIOCR2_SHIFT(r6)
-
- /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
-
- LOADPTR (r3, PMCR2_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x20
- stb r4, PMCR2_SHIFT(r6)
-
- /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
-
- LOADPTR (r3, EUMBBAR)
- stwbrx r3,0,r5
- LOADPTR (r4, CONFIG_SYS_EUMB_ADDR)
- stwbrx r4,0,r6
-
-L1not8245:
-
- /* Toggle the DLL reset bit in AMBOR */
-
- LOADPTR (r3, AMBOR)
- stwbrx r3,0,r5
- lbz r4, 0(r6)
-
- andi. r4, r4, 0xdf
- stb r4, 0(r6) /* Clear DLL_RESET */
- sync
-
- ori r4, r4, 0x20 /* Set DLL_RESET */
- stb r4, 0(r6)
- sync
-
- andi. r4, r4, 0xdf
- stb r4, 0(r6) /* Clear DLL_RESET */
-
-
- /* Enable RCS2, use supplied timings */
- LOADPTR (r3, ERCR1)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x80408000)
- stwbrx r4,0,r6
-
- /* Disable RCS3 parameters */
- LOADPTR (r3, ERCR2)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- /* RCS3 at 0x70000000, 64KBytes */
- LOADPTR (r3, ERCR2)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000004)
- stwbrx r4,0,r6
-
- /*-------MCCR1 */
-
-#ifdef INCLUDE_ECC
-#define MC_ECC 1
-#else /* INCLUDE_ECC */
-#define MC_ECC 0
-#endif /* INCLUDE_ECC */
-
-#define MC1_ROMNAL 8 /* 0-15 */
-#define MC1_ROMFAL 11 /* 0-31 */
-#define MC1_DBUS_SIZE 0 /* 0-3, read only */
-#define MC1_BURST 0 /* 0-1 */
-#define MC1_MEMGO 0 /* 0-1 */
-#define MC1_SREN 1 /* 0-1 */
-#define MC1_RAM_TYPE 0 /* 0-1 */
-#define MC1_PCKEN MC_ECC /* 0-1 */
-#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */
-
- LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
- MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
- MC1_MEMGO << 19 | MC1_SREN << 18 | \
- MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
- li r3, MC1_BANKBITS
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne BankBitsAdd
- cmpli 0, 0, r3, 0x5555
- beq K2BankBitsHack /* On 8245, 5555 ==> 0 */
-BankBitsAdd:
- ori r4, r3, 0
-K2BankBitsHack:
- stwbrx r4, 0, r6
-
- /*------- MCCR2 */
-
-#define MC2_TS_WAIT_TIMER 0 /* 0-7 */
-#define MC2_ASRISE 8 /* 0-15 */
-#define MC2_ASFALL 4 /* 0-15 */
-#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */
-#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */
-#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */
-#define MC2_ECC_EN 0 /* 0-1 */
-#define MC2_EDO 0 /* 0-1 */
-/*
-* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM.
-* May need to be decreased for 100 MHz
-*/
-#define MC2_REFINT 0x3a5 /* 0-0x3fff */
-#define MC2_RSV_PG 0 /* 0-1 */
-#define MC2_RMW_PAR MC_ECC /* 0-1 */
-
- LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
- MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
- MC2_WRITE_PARITY_CHK_EN << 19 | \
- MC2_INLRD_PARECC_CHK_EN << 18 | \
- MC2_ECC_EN << 17 | MC2_EDO << 16 | \
- MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne notK2
- /* clear Kahlua2 reserved bits */
- LOADPTR (r3, 0xfffcffff)
- and r4, r4, r3
-notK2:
- stwbrx r4,0,r6
-
- /*------- MCCR3 */
-
-#define MC_BSTOPRE 0x079 /* 0-0x7ff */
-
-#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf)
-#define MC3_REFREC 8 /* 0-15 */
-#define MC3_RDLAT (4+MC_ECC) /* 0-15 */
-#define MC3_CPX 0 /* 0-1 */
-#define MC3_RAS6P 0 /* 0-15 */
-#define MC3_CAS5 0 /* 0-7 */
-#define MC3_CP4 0 /* 0-7 */
-#define MC3_CAS3 0 /* 0-7 */
-#define MC3_RCD2 0 /* 0-7 */
-#define MC3_RP1 0 /* 0-7 */
-
- LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
- MC3_RDLAT << 20 | MC3_CPX << 19 | \
- MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
- MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne notK2b
- /* clear Kahlua2 reserved bits */
- LOADPTR (r3, 0xff000000)
- and r4, r4, r3
-notK2b:
- stwbrx r4,0,r6
-
- /*------- MCCR4 */
-
-#define MC4_PRETOACT 3 /* 0-15 */
-#define MC4_ACTOPRE 5 /* 0-15 */
-#define MC4_WMODE 0 /* 0-1 */
-#define MC4_INLINE MC_ECC /* 0-1 */
-#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */
-#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3)
-#define MC4_REGDIMM 0 /* 0-1 */
-#define MC4_SDMODE_CAS 2 /* 0-7 */
-#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */
-#define MC4_SDMODE_WRAP 0 /* 0-1 */
-#define MC4_SDMODE_BURST 2 /* 0-7 */
-#define MC4_ACTORW 3 /* 0-15 */
-#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf)
-
- LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
- MC4_WMODE << 23 | MC4_INLINE << 22 | \
- MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
- MC4_DBUS_RCS1 << 17 | \
- MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
- MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
- MC4_ACTORW << 4 | MC4_BSTOPRE_L)
- cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */
- bne notK2c
- /* Turn on Kahlua2 extended ROM space */
- LOADPTR (r3, 0x00200000)
- or r4, r4, r3
-notK2c:
- stwbrx r4,0,r6
-
-#ifdef INCLUDE_ECC
- /*------- MEM_ERREN1 */
-
- LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */
- stwbrx r3,0,r5
- lwbrx r4,0,r6
- ori r4,r4,4 /* Set MEM_PERR_EN */
- stwbrx r4,0,r6
-#endif /* INCLUDE_ECC */
-
- /*------- MSAR/MEAR */
-
- LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xc0804000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xc0804000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x01010101)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xffbf7f3f)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xffbf7f3f)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x01010101)
- stwbrx r4,0,r6
-
- /*-------ODCR */
-
- LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */
- stwbrx r3,0,r5
-
- li r4, 0x7f
- stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */
-
- /*-------MBEN */
-
- LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */
- stwbrx r3,0,r5
- li r4, 0x01 /* Enable bank 0 */
- stb r4, 0(r6) /* MBEN is at +0 offset */
-
-#if 0 /* Jimmy: I think page made is broken */
- /*-------PGMAX */
-
- LOADPTR (r3, MPM_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x32
- stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */
-#endif
-
- /* Wait before initializing other registers */
-
- lis r4,0x0001
- mtctr r4
-
-KahluaX4wait200us:
- bdnz KahluaX4wait200us
-
- /* Set MEMGO bit */
-
- LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */
- stwbrx r3,0,r5
- lwbrx r4,0,r6 /* old MCCR1 */
- oris r4,r4,0x0008 /* MEMGO=1 */
- stwbrx r4, 0, r6
-
- /* Wait again */
-
- addis r4,r0,0x0002
- ori r4,r4,0xffff
-
- mtctr r4
-
-KahluaX4wait8ref:
- bdnz KahluaX4wait8ref
-
- sync
- eieio
- mtlr r11
- blr
-
-#else /* USE_V2_INIT */
-
-
-/* U-Boot works, but memory will not run reliably for all address ranges.
- * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
- * initialized correctly. Could work if debugged.
- */
-/* PCI Support routines */
-
- .globl __pci_config_read_32
-__pci_config_read_32:
- lis r4, 0xfec0
- stwbrx r3, r0, r4
- sync
- lis r4, 0xfee0
- lwbrx r3, 0, r4
- blr
- .globl __pci_config_read_16
-__pci_config_read_16:
- lis r4, 0xfec0
- andi. r5, r3, 2
- stwbrx r3, r0, r4
- sync
- oris r4, r5, 0xfee0
- lhbrx r3, r0, r4
- blr
- .globl __pci_config_read_8
-__pci_config_read_8:
- lis r4, 0xfec0
- andi. r5, r3, 3
- stwbrx r3, r0, r4
- sync
- oris r4, r5, 0xfee0
- lbz r3, 0(4)
- blr
- .globl __pci_config_write_32
-__pci_config_write_32:
- lis r5, 0xfec0
- stwbrx r3, r0, r5
- sync
- lis r5, 0xfee0
- stwbrx r4, r0, r5
- sync
- blr
- .globl __pci_config_write_16
-__pci_config_write_16:
- lis r5, 0xfec0
- andi. r6, r3, 2
- stwbrx r3, r0, 5
- sync
- oris r5, r6, 0xfee0
- sthbrx r4, r0, r5
- sync
- blr
- .globl __pci_config_write_8
-__pci_config_write_8:
- lis r5, 0xfec0
- andi. r6, r3, 3
- stwbrx r3, r0, r5
- sync
- oris r5, r6, 0xfee0
- stb r4, 0(r5)
- sync
- blr
- .globl in_8
-in_8:
- oris r3, r3, 0xfe00
- lbz r3,0(r3)
- blr
- .globl in_16
-in_16:
- oris r3, r3, 0xfe00
- lhbrx r3, 0, r3
- blr
- .globl in_16_ne
-in_16_ne:
- oris r3, r3, 0xfe00
- lhzx r3, 0, r3
- blr
- .globl in_32
-in_32:
- oris r3, r3, 0xfe00
- lwbrx r3, 0, r3
- blr
- .globl out_8
-out_8:
- oris r3, r3, 0xfe00
- stb r4, 0(r3)
- eieio
- blr
- .globl out_16
-out_16:
- oris r3, r3, 0xfe00
- sthbrx r4, 0, r3
- eieio
- blr
- .globl out_16_ne
-out_16_ne:
- oris r3, r3, 0xfe00
- sth r4, 0(r3)
- eieio
- blr
- .globl out_32
-out_32:
- oris r3, r3, 0xfe00
- stwbrx r4, 0, r3
- eieio
- blr
- .globl read_8
-read_8:
- lbz r3,0(r3)
- blr
- .globl read_16
-read_16:
- lhbrx r3, 0, r3
- blr
- .globl read_32
-read_32:
- lwbrx r3, 0, r3
- blr
- .globl read_32_ne
-read_32_ne:
- lwz r3, 0(r3)
- blr
- .globl write_8
-write_8:
- stb r4, 0(r3)
- eieio
- blr
- .globl write_16
-write_16:
- sthbrx r4, 0, r3
- eieio
- blr
- .globl write_32
-write_32:
- stwbrx r4, 0, r3
- eieio
- blr
- .globl write_32_ne
-write_32_ne:
- stw r4, 0(r3)
- eieio
- blr
-
-
-.globl early_init_f
-
-early_init_f:
- mflr r11
- lis r10, 0x8000
-
- /* PCI Latency Timer */
- li r4, 0x0d
- ori r3, r10, PLTR@l
- bl __pci_config_write_8
-
- /* Cache Line Size */
- li r4, 0x08
- ori r3, r10, PCLSR@l
- bl __pci_config_write_8
-
- /* PCI Cmd */
- li r4, 6
- ori r3, r10, PCICR@l
- bl __pci_config_write_16
-
-#if 1
- /* PCI Stat */
- ori r3, r10, PCISR@l
- bl __pci_config_read_16
- ori r4, r4, 0xffff
- ori r3, r10, PCISR@l
- bl __pci_config_write_16
-#endif
-
- /* PICR1 */
- lis r4, 0xff14
- ori r4, r4, 0x1b98
- ori r3, r10, PICR1@l
- bl __pci_config_write_32
-
-
- /* PICR2 */
- lis r4, 0x0404
- ori r4, r4, 0x0004
- ori r3, r10, PICR2@l
- bl __pci_config_write_32
-
- /* MIOCR1 */
- li r4, 0x04
- ori r3, r10, MIOCR1@l
- bl __pci_config_write_8
-
- /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
- /* SDRAM_CLK_DEL (0x77)*/
- li r4, 0x10
- ori r3, r10, MIOCR2@l
- bl __pci_config_write_8
-
- /* EUMBBAR */
- lis r4, 0xfc00
- ori r3, r10, EUMBBAR@l
- bl __pci_config_write_32
-
- /* AMBOR */
-
- /* Even if Address Map B is not being used (though it should),
- * the memory DLL needs to be cleared/set/cleared before using memory.
- */
-
- ori r3, r10, AMBOR@l
- bl __pci_config_read_8 /* get Current bits */
-
- andi. r4, r4, 0xffdf
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Clear DLL_RESET */
-
- ori r4, r4, 0x0020
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Set DLL_RESET */
-
- andi. r4, r4, 0xffdf
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Clear DLL_RESET */
-
- /* ERCR1 */
- lis r4, 0x8040 /* Enable RCS2, use supplied timings */
- ori r4, r4, 0x8000
- ori r3, r10, ERCR1@l
- bl __pci_config_write_32
-
- /* ERCR2 */
- lis r4, 0x0000 /* Disable RCS3 parms */
- ori r4, r4, 0x0000
- ori r3, r10, ERCR2@l
- bl __pci_config_write_32
-
- /* ERCR3 */
- lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */
- ori r4, r4, 0x0004
- ori r3, r10, ERCR2@l
- bl __pci_config_write_32
-
- /* Preserve memgo bit */
- /* MCCR1 */
-
-/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */
- lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */
-/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */
-/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */
-/* oris r4, r4, 0x0004 / Self-refresh enable */
-
-/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */
-/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */
-/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */
- ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */
-
- ori r3, r10, MCCR1@l
- bl __pci_config_write_32
-
- /* MCCR2 */
-
- lis r4,0x0000
-/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */
- oris r4,r4,0x1000 /* ASRISE = 8 clocks */
- oris r4,r4,0x0080 /* ASFALL = 8 clocks */
-/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */
-/* oris r4,r4,0x0008 / Write parity check */
-/* oris r4,r4,0x0004 / SDRAM inline reads */
-
-
-/* Select a refresh rate; it needs to match the bus speed; if too */
-/* slow, data may be lost; if too fast, performance is lost. We */
-/* use the fastest value so we run at all speeds. */
-/* Refresh = (15600ns/busclk) - (213 (see UM)). */
-
-/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */
-/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */
-/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */
-/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */
- ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */
-/* ori r4,r4,0x0002 / Reserve a page */
-/* ori r4,r4,0x0001 / RWM parity */
-
- ori r3, r10, MCCR2@l
- bl __pci_config_write_32
-
-
- /* MCCR3 */
- lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */
- oris r4,r4,0x0500 /* REFREC = 8 clocks */
- ori r3, r10, MCCR3@l
- bl __pci_config_write_32
-
- /* MCCR4 */ /* Turn on registered buffer mode */
- lis r4, 0x2000 /* PRETOACT = 3 clocks */
- oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */
-/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */
-/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */
- oris r4,r4,0x0020 /* EXTROM enabled */
- oris r4,r4,0x0010 /* Registered buffers */
-/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */
- oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */
-
-/* ori r4,r4,0x8000 / Registered DIMMs */
- ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */
-/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */
-/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */
- ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */
- ori r4,r4,0x0030 /* ACTORW = 3 clocks */
- ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */
-
- ori r3, r10, MCCR4@l
- bl __pci_config_write_32
-
- /* MSAR1 */
- lis r4, 0xc0804000@h
- ori r4, r4, 0xc0804000@l
- ori r3, r10, MSAR1@l
- bl __pci_config_write_32
-
- /* MSAR2 */
- lis r4, 0xc0804000@h
- ori r4, r4, 0xc0804000@l
- ori r3, r10, MSAR2@l
- bl __pci_config_write_32
-
- /* MESAR1 */
- lis r4, 0x00000000@h
- ori r4, r4, 0x00000000@l
- ori r3, r10, EMSAR1@l
- bl __pci_config_write_32
-
- /* MESAR2 */
- lis r4, 0x01010101@h
- ori r4, r4, 0x01010101@l
- ori r3, r10, EMSAR2@l
- bl __pci_config_write_32
-
- /* MEAR1 */
- lis r4, 0xffbf7f3f@h
- ori r4, r4, 0xffbf7f3f@l
- ori r3, r10, MEAR1@l
- bl __pci_config_write_32
-
- /* MEAR2 */
- lis r4, 0xffbf7f3f@h
- ori r4, r4, 0xffbf7f3f@l
- ori r3, r10, MEAR2@l
- bl __pci_config_write_32
-
- /* MEEAR1 */
- lis r4, 0x00000000@h
- ori r4, r4, 0x00000000@l
- ori r3, r10, EMEAR1@l
- bl __pci_config_write_32
-
- /* MEEAR2 */
- lis r4, 0x01010101@h
- ori r4, r4, 0x01010101@l
- ori r3, r10, EMEAR2@l
- bl __pci_config_write_32
-
- /* ODCR */
- li r4, 0x7f
- ori r3, r10, ODCR@l
- bl __pci_config_write_8
-
- /* MBER */
- li r4, 0x01
- ori r3, r10, MBER@l
- bl __pci_config_write_8
-
- /* Page CTR aka PGMAX */
- li r4, 0x32
- ori r3, r10, 0x70
- bl __pci_config_write_8
-
-#if 0
- /* CLK Drive */
- ori r4, r10, 0xfc01 /* Top bit will be ignored */
- ori r3, r10, 0x74
- bl __pci_config_write_16
-#endif
-
- /* delay */
- lis r7, 1
- mtctr r7
-label1: bdnz label1
-
- /* Set memgo bit */
- /* MCCR1 */
- ori r3, r10, MCCR1@l
- bl __pci_config_read_32
- lis r7, 0x0008
- or r4, r3, r7
- ori r3, r10, MCCR1@l
- bl __pci_config_write_32
-
- /* delay again */
- lis r7, 1
- mtctr r7
-label2: bdnz label2
-#if 0
-/* DEBUG: Infinite loop, write then read */
-loop:
- lis r7, 0xffff
- mtctr r7
- li r3, 0x5004
- lis r4, 0xa0a0
- ori r4, r4, 0x5050
- bl write_32_ne
- li r3, 0x5004
- bl read_32_ne
- bdnz loop
-#endif
- mtlr r11
- blr
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info);
-#endif /* 0 */
-
-/*flash command address offsets*/
-
-#if 0
-#define ADDR0 (0x555)
-#define ADDR1 (0x2AA)
-#define ADDR3 (0x001)
-#else
-#define ADDR0 (0xAAA)
-#define ADDR1 (0x555)
-#define ADDR3 (0x001)
-#endif
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-#if 0
-static int byte_parity_odd (unsigned char x) __attribute__ ((const));
-#endif /* 0 */
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
- __attribute__ ((const));
-
-typedef struct {
- FLASH_WORD_SIZE extval;
- unsigned short intval;
-} map_entry;
-
-#if 0
-static int byte_parity_odd (unsigned char x)
-{
- x ^= x >> 4;
- x ^= x >> 2;
- x ^= x >> 1;
- return (x & 0x1) != 0;
-}
-#endif /* 0 */
-
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-{
- static const map_entry mfct_map[] = {
- {(FLASH_WORD_SIZE) AMD_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
- {(FLASH_WORD_SIZE) FUJ_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
- {(FLASH_WORD_SIZE) STM_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
- {(FLASH_WORD_SIZE) MT_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
- {(FLASH_WORD_SIZE) INTEL_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
- {(FLASH_WORD_SIZE) INTEL_ALT_MANU,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
- };
-
- static const map_entry chip_map[] = {
- {AMD_ID_F040B, FLASH_AM040},
- {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
- };
-
- const map_entry *p;
- unsigned long result = FLASH_UNKNOWN;
-
- /* find chip id */
- for (p = &chip_map[0];
- p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
- if (p->extval == chip) {
- result = FLASH_VENDMASK | p->intval;
- break;
- }
-
- /* find vendor id */
- for (p = &mfct_map[0];
- p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
- if (p->extval == mfct) {
- result &= ~FLASH_VENDMASK;
- result |= (unsigned long) p->intval << 16;
- break;
- }
-
- return result;
-}
-
-
-unsigned long flash_init (void)
-{
- unsigned long i;
- unsigned char j;
- static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
-
- pflinfo->flash_id = FLASH_UNKNOWN;
- pflinfo->size = 0;
- pflinfo->sector_count = 0;
- }
-
- for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
- const unsigned long base_address = flash_banks[i];
- volatile FLASH_WORD_SIZE *const flash =
- (FLASH_WORD_SIZE *) base_address;
-#if 0
- volatile FLASH_WORD_SIZE *addr2;
-#endif
-#if 0
- /* write autoselect sequence */
- flash[0x5555] = 0xaa;
- flash[0x2aaa] = 0x55;
- flash[0x5555] = 0x90;
-#else
- flash[0xAAA << (3 * i)] = 0xaa;
- flash[0x555 << (3 * i)] = 0x55;
- flash[0xAAA << (3 * i)] = 0x90;
-#endif
- __asm__ __volatile__ ("sync");
-
-#if 0
- pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]);
-#else
- pflinfo->flash_id =
- flash_id (flash[0x0], flash[0x2 + 14 * i]);
-#endif
-
- switch (pflinfo->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 8;
- for (j = 0; j < 8; j++) {
- pflinfo->start[j] =
- base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_STM800AB:
- pflinfo->size = 0x00100000;
- pflinfo->sector_count = 19;
- pflinfo->start[0] = base_address;
- pflinfo->start[1] = base_address + 0x4000;
- pflinfo->start[2] = base_address + 0x6000;
- pflinfo->start[3] = base_address + 0x8000;
- for (j = 1; j < 16; j++) {
- pflinfo->start[j + 3] =
- base_address + 0x00010000 * j;
- }
-#if 0
- /* check for protected sectors */
- for (j = 0; j < pflinfo->sector_count; j++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE
- *) (pflinfo->start[j]);
- if (pflinfo->flash_id & FLASH_MAN_SST)
- pflinfo->protect[j] = 0;
- else
- pflinfo->protect[j] = addr2[2] & 1;
- }
-#endif
- break;
- }
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* reset device to read mode */
- flash[0x0000] = 0xf0;
- __asm__ __volatile__ ("sync");
- }
-
- return flash_info[0].size + flash_info[1].size;
-}
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-#endif /* 0 */
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if (info->flash_id != FLASH_UNKNOWN) {
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- mfct = "AMD";
- break;
- case FLASH_MAN_FUJ:
- mfct = "FUJITSU";
- break;
- case FLASH_MAN_STM:
- mfct = "STM";
- break;
- case FLASH_MAN_SST:
- mfct = "SST";
- break;
- case FLASH_MAN_BM:
- mfct = "Bright Microelectonics";
- break;
- case FLASH_MAN_INTEL:
- mfct = "Intel";
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- type = "AM29F040B (512K * 8, uniform sector size)";
- break;
- case FLASH_AM400B:
- type = "AM29LV400B (4 Mbit, bottom boot sect)";
- break;
- case FLASH_AM400T:
- type = "AM29LV400T (4 Mbit, top boot sector)";
- break;
- case FLASH_AM800B:
- type = "AM29LV800B (8 Mbit, bottom boot sect)";
- break;
- case FLASH_AM800T:
- type = "AM29LV800T (8 Mbit, top boot sector)";
- break;
- case FLASH_AM160T:
- type = "AM29LV160T (16 Mbit, top boot sector)";
- break;
- case FLASH_AM320B:
- type = "AM29LV320B (32 Mbit, bottom boot sect)";
- break;
- case FLASH_AM320T:
- type = "AM29LV320T (32 Mbit, top boot sector)";
- break;
- case FLASH_STM800AB:
- type = "M29W800AB (8 Mbit, bottom boot sect)";
- break;
- case FLASH_SST800A:
- type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
- break;
- case FLASH_SST160A:
- type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
- break;
- }
- }
-
- printf ("\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct, type, info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++) {
- unsigned long size;
- unsigned int erased;
- unsigned long *flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size = (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for (flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size)
- && erased; flash++)
- erased = *flash == ~0x0UL;
-
- printf ("%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ", info->protect[i] ? "RO" : " ");
- }
-
- puts ("\n");
- return;
-}
-
-#if 0
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- printf ("flash_get_size: \n");
- /* Write auto select command: read Manufacturer ID */
- eieio ();
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90;
- value = addr2[0];
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
- printf ("recognised manufacturer");
-
- value = addr2[ADDR3]; /* device ID */
- debug ("\ndev_code=%x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id,
- info->sector_count, info->size);
- /* set up sector start address table */
- if (info->flash_id & FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- if (info->flash_id & FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-#endif
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned char sh8b;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
- start
- [sect]
- -
- info->
- start
- [0]) <<
- sh8b));
- if (info->flash_id & FLASH_MAN_SST) {
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- udelay (30000); /* wait 30 ms */
- } else
- addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
- info->
- start[0]) << sh8b));
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
- volatile FLASH_WORD_SIZE *dest2;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int flag;
- int i;
- unsigned char sh8b;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
- info->start[0]);
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i << sh8b] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
- * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
- * registers which are used to set/get the internal date/time functions.
- *
- * This module implements Y2K compliance by taking full year numbers
- * and translating back and forth from the TOD 2-digit year.
- *
- * NOTE: for proper interaction with an operating system, the TOD should
- * be used to store Universal Coordinated Time (GMT) and timezone
- * conversions should be used.
- *
- * Here is a diagram of the memory layout:
- *
- * +---------------------------------------------+ 0xffe0a000
- * | Non-volatile memory | .
- * | | .
- * | (8176 bytes of Non-volatile memory) | .
- * | | .
- * +---------------------------------------------+ 0xffe0bff0
- * | Flags |
- * +---------------------------------------------+ 0xffe0bff1
- * | Unused |
- * +---------------------------------------------+ 0xffe0bff2
- * | Alarm Seconds |
- * +---------------------------------------------+ 0xffe0bff3
- * | Alarm Minutes |
- * +---------------------------------------------+ 0xffe0bff4
- * | Alarm Date |
- * +---------------------------------------------+ 0xffe0bff5
- * | Interrupts |
- * +---------------------------------------------+ 0xffe0bff6
- * | WatchDog |
- * +---------------------------------------------+ 0xffe0bff7
- * | Calibration |
- * +---------------------------------------------+ 0xffe0bff8
- * | Seconds |
- * +---------------------------------------------+ 0xffe0bff9
- * | Minutes |
- * +---------------------------------------------+ 0xffe0bffa
- * | Hours |
- * +---------------------------------------------+ 0xffe0bffb
- * | Day |
- * +---------------------------------------------+ 0xffe0bffc
- * | Date |
- * +---------------------------------------------+ 0xffe0bffd
- * | Month |
- * +---------------------------------------------+ 0xffe0bffe
- * | Year (2 digits only) |
- * +---------------------------------------------+ 0xffe0bfff
- */
-#include <common.h>
-#include <rtc.h>
-#include "bmw.h"
-
-/*
- * Imported from mousse.h:
- *
- * TOD_REG_BASE Base of m48t59y TOD registers
- * SYS_TOD_UNPROTECT() Disable NVRAM write protect
- * SYS_TOD_PROTECT() Re-enable NVRAM write protect
- */
-
-#define YEAR 0xf
-#define MONTH 0xe
-#define DAY 0xd
-#define DAY_OF_WEEK 0xc
-#define HOUR 0xb
-#define MINUTE 0xa
-#define SECOND 0x9
-#define CONTROL 0x8
-#define WATCH 0x7
-#define INTCTL 0x6
-#define WD_DATE 0x5
-#define WD_HOUR 0x4
-#define WD_MIN 0x3
-#define WD_SEC 0x2
-#define _UNUSED 0x1
-#define FLAGS 0x0
-
-#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE)
-
-int m48_tod_init(void)
-{
- SYS_TOD_UNPROTECT();
-
- M48_ADDR[CONTROL] = 0;
- M48_ADDR[WATCH] = 0;
- M48_ADDR[INTCTL] = 0;
-
- /*
- * If the oscillator is currently stopped (as on a new part shipped
- * from the factory), start it running.
- *
- * Here is an example of the TOD bytes on a brand new M48T59Y part:
- * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
- */
-
- if (M48_ADDR[SECOND] & 0x80)
- M48_ADDR[SECOND] = 0;
-
- /* Is battery low */
- if ( M48_ADDR[FLAGS] & 0x10) {
- printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
- }
-
- SYS_TOD_PROTECT();
-
- return 0;
-}
-
-/*
- * m48_tod_set
- */
-
-static int to_bcd(int value)
-{
- return value / 10 * 16 + value % 10;
-}
-
-static int from_bcd(int value)
-{
- return value / 16 * 10 + value % 16;
-}
-
-static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */
-{
- static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
- y -= m < 3;
- return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
-}
-
-/*
- * Note: the TOD should store the current GMT
- */
-
-int m48_tod_set(int year, /* 1980-2079 */
- int month, /* 01-12 */
- int day, /* 01-31 */
- int hour, /* 00-23 */
- int minute, /* 00-59 */
- int second) /* 00-59 */
-
-{
- SYS_TOD_UNPROTECT();
-
- M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */
-
- M48_ADDR[YEAR] = to_bcd(year % 100);
- M48_ADDR[MONTH] = to_bcd(month);
- M48_ADDR[DAY] = to_bcd(day);
- M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
- M48_ADDR[HOUR] = to_bcd(hour);
- M48_ADDR[MINUTE] = to_bcd(minute);
- M48_ADDR[SECOND] = to_bcd(second);
-
- M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */
-
- SYS_TOD_PROTECT();
-
- return 0;
-}
-
-/*
- * Note: the TOD should store the current GMT
- */
-
-int m48_tod_get(int *year, /* 1980-2079 */
- int *month, /* 01-12 */
- int *day, /* 01-31 */
- int *hour, /* 00-23 */
- int *minute, /* 00-59 */
- int *second) /* 00-59 */
-{
- int y;
-
- SYS_TOD_UNPROTECT();
-
- M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */
-
- y = from_bcd(M48_ADDR[YEAR]);
- *year = y < 80 ? 2000 + y : 1900 + y;
- *month = from_bcd(M48_ADDR[MONTH]);
- *day = from_bcd(M48_ADDR[DAY]);
- /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
- *hour = from_bcd(M48_ADDR[HOUR]);
- *minute = from_bcd(M48_ADDR[MINUTE]);
- *second = from_bcd(M48_ADDR[SECOND] & 0x7f);
-
- M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */
-
- SYS_TOD_PROTECT();
-
- return 0;
-}
-
-int m48_tod_get_second(void)
-{
- return from_bcd(M48_ADDR[SECOND] & 0x7f);
-}
-
-/*
- * Watchdog function
- *
- * If usec is 0, the watchdog timer is disarmed.
- *
- * If usec is non-zero, the watchdog timer is armed (or re-armed) for
- * approximately usec microseconds (if the exact requested usec is
- * not supported by the chip, the next higher available value is used).
- *
- * Minimum watchdog timeout = 62500 usec
- * Maximum watchdog timeout = 124 sec (124000000 usec)
- */
-
-void m48_watchdog_arm(int usec)
-{
- int mpy, res;
-
- SYS_TOD_UNPROTECT();
-
- if (usec == 0) {
- res = 0;
- mpy = 0;
- } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */
- res = 0;
- mpy = (usec + 62499) / 62500;
- } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */
- res = 1;
- mpy = (usec + 249999) / 250000;
- } else if (usec < 32000000) { /* Resolution: 1s if below 32s */
- res = 2;
- mpy = (usec + 999999) / 1000000;
- } else { /* Resolution: 4s up to 124s */
- res = 3;
- mpy = (usec + 3999999) / 4000000;
- if (mpy > 31)
- mpy = 31;
- }
-
- M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */
- mpy << 2 |
- res);
-
- SYS_TOD_PROTECT();
-}
-
-/*
- * U-Boot RTC support.
- */
-int
-rtc_get( struct rtc_time *tmp )
-{
- m48_tod_get(&tmp->tm_year,
- &tmp->tm_mon,
- &tmp->tm_mday,
- &tmp->tm_hour,
- &tmp->tm_min,
- &tmp->tm_sec);
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
-
-#ifdef RTC_DEBUG
- printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
-#endif
-
- return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
- m48_tod_set(tmp->tm_year, /* 1980-2079 */
- tmp->tm_mon, /* 01-12 */
- tmp->tm_mday, /* 01-31 */
- tmp->tm_hour, /* 00-23 */
- tmp->tm_min, /* 00-59 */
- tmp->tm_sec); /* 00-59 */
-
-#ifdef RTC_DEBUG
- printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-
- return 0;
-}
-
-void
-rtc_reset (void)
-{
- m48_tod_init();
-}
+++ /dev/null
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-typedef struct NS16550 *NS16550_t;
-
-const NS16550_t COM_PORTS[] =
- { (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500),
-(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) };
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
- volatile struct NS16550 *com_port;
-
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS; /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
- return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS; /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
- while ((com_port->lsr & LSR_THRE) == 0);
- com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
- while ((com_port->lsr & LSR_DR) == 0);
- return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
- return ((com_port->lsr & LSR_DR) != 0);
-}
+++ /dev/null
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- * further modified to support the 8245 duart
- * modifications (c) Paul Jimenez, Musenki, Inc. 2001.
- */
-
-
-struct NS16550 {
- unsigned char rbrthrdlb; /* 0 */
- unsigned char ierdmb; /* 1 */
- unsigned char iirfcrafr; /* 2 */
- unsigned char lcr; /* 3 */
- unsigned char mcr; /* 4 */
- unsigned char lsr; /* 5 */
- unsigned char msr; /* 6 */
- unsigned char scr; /* 7 */
- unsigned char reserved[2]; /* 8 & 9 */
- unsigned char dsr; /* 10 */
- unsigned char dcr; /* 11 */
-};
-
-
-#define rbr rbrthrdlb
-#define thr rbrthrdlb
-#define dll rbrthrdlb
-#define ier ierdmb
-#define dlm ierdmb
-#define iir iirfcrafr
-#define fcr iirfcrafr
-#define afr iirfcrafr
-
-#define FCR_FIFO_EN 0x01 /*fifo enable */
-#define FCR_RXSR 0x02 /*receiver soft reset */
-#define FCR_TXSR 0x04 /*transmitter soft reset */
-#define FCR_DMS 0x08 /* DMA Mode Select */
-
-#define MCR_RTS 0x02 /* Readyu to Send */
-#define MCR_LOOP 0x10 /* Local loopback mode enable */
-/* #define MCR_DTR 0x01 noton 8245 duart */
-/* #define MCR_DMA_EN 0x04 noton 8245 duart */
-/* #define MCR_TX_DFR 0x08 noton 8245 duart */
-
-#define LCR_WLS_MSK 0x03 /* character length slect mask */
-#define LCR_WLS_5 0x00 /* 5 bit character length */
-#define LCR_WLS_6 0x01 /* 6 bit character length */
-#define LCR_WLS_7 0x02 /* 7 bit character length */
-#define LCR_WLS_8 0x03 /* 8 bit character length */
-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN 0x08 /* Parity eneble */
-#define LCR_EPS 0x10 /* Even Parity Select */
-#define LCR_STKP 0x20 /* Stick Parity */
-#define LCR_SBRK 0x40 /* Set Break */
-#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */
-
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1 0x03
-
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc (volatile struct NS16550 *com_port);
-int NS16550_tstc (volatile struct NS16550 *com_port);
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_CONS_INDEX == 1
-static struct NS16550 *console =
- (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
-#elif CONFIG_CONS_INDEX == 2
-static struct NS16550 *console =
- (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
-#else
-#error no valid console defined
-#endif
-
-extern ulong get_bus_freq (ulong);
-
-static int bmw_serial_init(void)
-{
- int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
-
- NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
-
- return (0);
-}
-
-static void bmw_serial_putc(const char c)
-{
- if (c == '\n') {
- serial_putc ('\r');
- }
- NS16550_putc (console, c);
-}
-
-static void bmw_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-
-static int bmw_serial_getc(void)
-{
- return NS16550_getc (console);
-}
-
-static int bmw_serial_tstc(void)
-{
- return NS16550_tstc (console);
-}
-
-static void bmw_serial_setbrg(void)
-{
- int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
-
- NS16550_reinit (console, clock_divisor);
-}
-
-static struct serial_device bmw_serial_drv = {
- .name = "bmw_serial",
- .start = bmw_serial_init,
- .stop = NULL,
- .setbrg = bmw_serial_setbrg,
- .putc = bmw_serial_putc,
- .puts = bmw_serial_puts,
- .getc = bmw_serial_getc,
- .tstc = bmw_serial_tstc,
-};
-
-void bmw_serial_initialize(void)
-{
- serial_register(&bmw_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &bmw_serial_drv;
-}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
cma_mb_reg_write (&mbsp->ser_thr, c);
}
-static void cogent_serial_puts(const char *s)
-{
- while (*s != '\0')
- serial_putc (*s++);
-}
-
static int cogent_serial_getc(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
.stop = NULL,
.setbrg = cogent_serial_setbrg,
.putc = cogent_serial_putc,
- .puts = cogent_serial_puts,
+ .puts = default_serial_puts,
.getc = cogent_serial_getc,
.tstc = cogent_serial_tstc,
};
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o plx9030.o pd67290.o
+COBJS = $(BOARD).o flash.o plx9030.o pd67290.o ide.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#endif
-# ifdef CONFIG_IDE_LED
-void ide_led (uchar led, uchar status)
-{
- u_char val;
- /* We have one PCMCIA slot and use LED H4 for the IDE Interface */
- val = readb(BCSR_BASE + 0x04);
- if (status) { /* led on */
- val |= B_CTRL_LED0;
- } else {
- val &= ~B_CTRL_LED0;
- }
- writeb(val, BCSR_BASE + 0x04);
-}
-# endif
-
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <ata.h>
+#include <asm/io.h>
+
+#define EIEIO __asm__ volatile ("eieio")
+#define SYNC __asm__ volatile ("sync")
+
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ uchar i;
+ volatile uchar *pbuf_even =
+ (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ volatile uchar *pbuf_odd =
+ (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ ushort *dbuf = (ushort *) sect_buf;
+
+ while (words--) {
+ for (i = 0; i < 2; i++) {
+ *(((uchar *) (dbuf)) + 1) = *pbuf_even;
+ *(uchar *) dbuf = *pbuf_odd;
+ dbuf += 1;
+ }
+ }
+}
+
+void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (words--) {
+ *dbuf++ = *pbuf_even;
+ EIEIO;
+ SYNC;
+ *dbuf++ = *pbuf_odd;
+ EIEIO;
+ SYNC;
+ *dbuf++ = *pbuf_even;
+ EIEIO;
+ SYNC;
+ *dbuf++ = *pbuf_odd;
+ EIEIO;
+ SYNC;
+ }
+}
+
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (shorts--) {
+ EIEIO;
+ *dbuf++ = *pbuf_even;
+ EIEIO;
+ *dbuf++ = *pbuf_odd;
+ }
+}
+
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (words--) {
+ EIEIO;
+ *pbuf_even = *dbuf++;
+ EIEIO;
+ *pbuf_odd = *dbuf++;
+ EIEIO;
+ *pbuf_even = *dbuf++;
+ EIEIO;
+ *pbuf_odd = *dbuf++;
+ }
+}
+
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (shorts--) {
+ EIEIO;
+ *pbuf_even = *dbuf++;
+ EIEIO;
+ *pbuf_odd = *dbuf++;
+ }
+}
+
+void ide_led(uchar led, uchar status)
+{
+ u_char val;
+ /* We have one PCMCIA slot and use LED H4 for the IDE Interface */
+ val = readb(BCSR_BASE + 0x04);
+ if (status) /* led on */
+ val |= B_CTRL_LED0;
+ else
+ val &= ~B_CTRL_LED0;
+
+ writeb(val, BCSR_BASE + 0x04);
+}
+
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ } >.sram
+
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.data.rel.ro)
}
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(4);
__rel_dyn_start = .;
__rel_dyn_end = .;
.sdata : { *(.sdata*) }
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <ide.h>
#include <pci.h>
-extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
int cpci_hd_type;
int ata_device(int dev)
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
-
-static void cpci750_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device cpci750_serial_drv = {
.name = "cpci750_serial",
.start = cpci750_serial_init,
.stop = NULL,
.setbrg = cpci750_serial_setbrg,
.putc = cpci750_serial_putc,
- .puts = cpci750_serial_puts,
+ .puts = default_serial_puts,
.getc = cpci750_serial_getc,
.tstc = cpci750_serial_tstc,
};
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#endif /* CONFIG_MPSC */
-static void evb64260_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device evb64260_serial_drv = {
.name = "evb64260_serial",
.start = evb64260_serial_init,
.stop = NULL,
.setbrg = evb64260_serial_setbrg,
.putc = evb64260_serial_putc,
- .puts = evb64260_serial_puts,
+ .puts = default_serial_puts,
.getc = evb64260_serial_getc,
.tstc = evb64260_serial_tstc,
};
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
+COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
void qixis_reset(void)
{
- QIXIS_WRITE(rst_ctl, 0x83);
+ QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
}
void qixis_bank_reset(void)
{
- QIXIS_WRITE(rcfg_ctl, 0x20);
- QIXIS_WRITE(rcfg_ctl, 0x21);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
}
-/* Set the boot bank to the power-on default bank0 */
+/* Set the boot bank to the power-on default bank */
void clear_altbank(void)
{
u8 reg;
reg = QIXIS_READ(brdcfg[0]);
- reg = reg & ~QIXIS_LBMAP_MASK;
+ reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
QIXIS_WRITE(brdcfg[0], reg);
}
printf("ctl_sys = %02x\n", QIXIS_READ(ctl_sys));
printf("rcw_ctl = %02x\n", QIXIS_READ(rcw_ctl));
printf("present = %02x\n", QIXIS_READ(present));
+ printf("present2 = %02x\n", QIXIS_READ(present2));
printf("clk_spd = %02x\n", QIXIS_READ(clk_spd));
printf("stat_dut = %02x\n", QIXIS_READ(stat_dut));
printf("stat_sys = %02x\n", QIXIS_READ(stat_sys));
printf("stat_alrm = %02x\n", QIXIS_READ(stat_alrm));
- printf("ctl_sys2 = %02x\n", QIXIS_READ(ctl_sys2));
}
#endif
for (i = 0; i < ARRAY_SIZE(period); i++) {
if (strcmp(argv[2], period[i]) == 0) {
/* disable watchdog */
- QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
+ QIXIS_WRITE(rcfg_ctl,
+ rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
QIXIS_WRITE(watch, ((i<<2) - 1));
QIXIS_WRITE(rcfg_ctl, rcfg);
return 0;
u8 stat_sys;
u8 stat_alrm;
u8 present;
- u8 ctl_sys2;
+ u8 present2; /* Presence Status Register 2,0x0c */
u8 rcw_ctl;
u8 ctl_led;
u8 i2cblk;
u8 res15[16];
};
-#define QIXIS_BASE 0xffdf0000
-#define QIXIS_LBMAP_SWITCH 7
-#define QIXIS_LBMAP_MASK 0x0f
-#define QIXIS_LBMAP_SHIFT 0
-#define QIXIS_LBMAP_ALTBANK 0x04
-
u8 qixis_read(unsigned int reg);
void qixis_write(unsigned int reg, u8 value);
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "vsc3316_3308.h"
+
+#define REVISION_ID_REG 0x7E
+#define INTERFACE_MODE_REG 0x79
+#define CURRENT_PAGE_REGISTER 0x7F
+#define CONNECTION_CONFIG_PAGE 0x00
+#define INPUT_STATE_REG 0x13
+#define GLOBAL_INPUT_ISE1 0x51
+#define GLOBAL_INPUT_ISE2 0x52
+#define GLOBAL_INPUT_LOS 0x55
+#define GLOBAL_CORE_CNTRL 0x5D
+#define OUTPUT_MODE_PAGE 0x23
+#define CORE_CONTROL_PAGE 0x25
+#define CORE_CONFIG_REG 0x75
+
+int vsc_if_enable(unsigned int vsc_addr)
+{
+ u8 data;
+
+ debug("VSC:Configuring VSC at I2C address 0x%2x"
+ " for 2-wire interface\n", vsc_addr);
+
+ /* enable 2-wire Serial InterFace (I2C) */
+ data = 0x02;
+ return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
+}
+
+int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con)
+{
+ unsigned int i;
+ u8 rev_id = 0;
+ int ret;
+
+ debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
+ " for Tx\n", vsc_addr);
+
+ ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+ if (ret < 0) {
+ printf("VSC:0x%x could not read REV_ID from device.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ if (rev_id != 0xab) {
+ printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+ vsc_addr);
+ return -ENODEV;
+ }
+
+ ret = vsc_if_enable(vsc_addr);
+ if (ret) {
+ printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ /* config connections - page 0x00 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+ /* Making crosspoint connections, by connecting required
+ * input to output */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+ /* input state - page 0x13 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+ /* Configuring the required input of the switch */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][0], 0x80);
+
+ /* Setting Global Input LOS threshold value */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+ /* config output mode - page 0x23 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+ /* Turn ON the Output driver correspond to required output*/
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], 0);
+
+ /* configure global core control register, Turn on Global core power */
+ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+ vsc_wp_config(vsc_addr);
+
+ return 0;
+}
+
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con)
+{
+ unsigned int i;
+ u8 rev_id = 0;
+ int ret;
+
+ debug("VSC:Initializing VSC3308 at I2C address 0x%x"
+ " for Tx\n", vsc_addr);
+
+ ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
+ if (ret < 0) {
+ printf("VSC:0x%x could not read REV_ID from device.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ if (rev_id != 0xab) {
+ printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
+ vsc_addr);
+ return -ENODEV;
+ }
+
+ ret = vsc_if_enable(vsc_addr);
+ if (ret) {
+ printf("VSC:0x%x could not configured for 2-wire I/F.\n",
+ vsc_addr);
+ return ret;
+ }
+
+ /* config connections - page 0x00 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
+
+ /* Making crosspoint connections, by connecting required
+ * input to output */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
+
+ /*Configure Global Input ISE and gain */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12);
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12);
+
+ /* input state - page 0x13 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
+ /* Turning ON the required input of the switch */
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][0], 0);
+
+ /* Setting Global Input LOS threshold value */
+ i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
+
+ /* config output mode - page 0x23 */
+ i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
+ /* Turn ON the Output driver correspond to required output*/
+ for (i = 0; i < num_con ; i++)
+ i2c_reg_write(vsc_addr, con_arr[i][1], 0);
+
+ /* configure global core control register, Turn on Global core power */
+ i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
+
+ vsc_wp_config(vsc_addr);
+
+ return 0;
+}
+
+void vsc_wp_config(unsigned int vsc_addr)
+{
+ debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr);
+
+ /* For new crosspoint configuration to occur, WP bit of
+ * CORE_CONFIG_REG should be set 1 and then reset to 0 */
+ i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
+ i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __VSC_CROSSBAR_H_
+#define __VSC_CROSSBAR_H 1_
+
+#include <common.h>
+#include <i2c.h>
+#include <errno.h>
+
+int vsc_if_enable(unsigned int vsc_addr);
+int vsc3316_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con);
+int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
+ unsigned int num_con);
+void vsc_wp_config(unsigned int vsc_addr);
+
+#endif /* __VSC_CROSSBAR_H_ */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
*(.text*)
}
_etext = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
#
# See file CREDITS for list of people who contributed to this
# project.
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
-
-SOBJS = early_init.o
+COBJS = $(BOARD).o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Copyright 2010-2012 Freescale Semiconductor, Inc.
+# TsiChung Liew (Tsi-Chung.Liew@freescale.com)
#
# See file CREDITS for list of people who contributed to this
# project.
# MA 02111-1307 USA
#
-#
-# BMW board
-#
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-# NOTE: The flags below affect how the BCM570x driver is compiled
-PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
- -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
--- /dev/null
+/*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ /*
+ * need to to:
+ * Check serial flash size. if 2mb evb, else 8mb demo
+ */
+ puts("Board: ");
+ puts("Freescale MCF54418 Tower System\n");
+ return 0;
+};
+
+phys_size_t initdram(int board_type)
+{
+ u32 dramsize;
+
+#if defined(CONFIG_SERIAL_BOOT)
+ /*
+ * Serial Boot: The dram is already initialized in start.S
+ * only require to return DRAM size
+ */
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
+ sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
+ ccm_t *ccm = (ccm_t *)MMAP_CCM;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ pm_t *pm = (pm_t *) MMAP_PM;
+ u32 i;
+
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+ for (i = 0x13; i < 0x20; i++) {
+ if (dramsize == (1 << i))
+ break;
+ }
+
+ out_8(&pm->pmcr0, 0x2E);
+ out_8(&gpio->mscr_sdram, 1);
+
+ clrbits_be16(&ccm->misccr2, CCM_MISCCR2_FBHALF);
+ setbits_be16(&ccm->misccr2, CCM_MISCCR2_DDR2CLK);
+
+ out_be32(&sdram->rcrcr, 0x40000000);
+ out_be32(&sdram->padcr, 0x01030203);
+
+ out_be32(&sdram->cr00, 0x01010101);
+ out_be32(&sdram->cr01, 0x00000101);
+ out_be32(&sdram->cr02, 0x01010100);
+ out_be32(&sdram->cr03, 0x01010000);
+ out_be32(&sdram->cr04, 0x00010101);
+ out_be32(&sdram->cr06, 0x00010100);
+ out_be32(&sdram->cr07, 0x00000001);
+ out_be32(&sdram->cr08, 0x01000001);
+ out_be32(&sdram->cr09, 0x00000100);
+ out_be32(&sdram->cr10, 0x00010001);
+ out_be32(&sdram->cr11, 0x00000200);
+ out_be32(&sdram->cr12, 0x01000002);
+ out_be32(&sdram->cr13, 0x00000000);
+ out_be32(&sdram->cr14, 0x00000100);
+ out_be32(&sdram->cr15, 0x02000100);
+ out_be32(&sdram->cr16, 0x02000407);
+ out_be32(&sdram->cr17, 0x02030007);
+ out_be32(&sdram->cr18, 0x02000100);
+ out_be32(&sdram->cr19, 0x0A030203);
+ out_be32(&sdram->cr20, 0x00020708);
+ out_be32(&sdram->cr21, 0x00050008);
+ out_be32(&sdram->cr22, 0x04030002);
+ out_be32(&sdram->cr23, 0x00000004);
+ out_be32(&sdram->cr24, 0x020A0000);
+ out_be32(&sdram->cr25, 0x0C00000E);
+ out_be32(&sdram->cr26, 0x00002004);
+ out_be32(&sdram->cr28, 0x00100010);
+ out_be32(&sdram->cr29, 0x00100010);
+ out_be32(&sdram->cr31, 0x07990000);
+ out_be32(&sdram->cr40, 0x00000000);
+ out_be32(&sdram->cr41, 0x00C80064);
+ out_be32(&sdram->cr42, 0x44520002);
+ out_be32(&sdram->cr43, 0x00C80023);
+ out_be32(&sdram->cr45, 0x0000C350);
+ out_be32(&sdram->cr56, 0x04000000);
+ out_be32(&sdram->cr57, 0x03000304);
+ out_be32(&sdram->cr58, 0x40040000);
+ out_be32(&sdram->cr59, 0xC0004004);
+ out_be32(&sdram->cr60, 0x0642C000);
+ out_be32(&sdram->cr61, 0x00000642);
+ asm("tpf");
+
+ out_be32(&sdram->cr09, 0x01000100);
+
+ udelay(100);
+#endif
+ return dramsize;
+};
+
+int testdram(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ .text :
+ {
+ arch/m68k/cpu/mcf5445x/start.o (.text*)
+
+ *(.text*)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+
+ .reloc :
+ {
+ __got_start = .;
+ KEEP(*(.got))
+ __got_end = .;
+ _GOT2_TABLE_ = .;
+ KEEP(*(.got2))
+ _FIXUP_TABLE_ = .;
+ KEEP(*(.fixup))
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ _sbss = .;
+ *(.bss*)
+ *(.sbss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ }
+ __bss_end__ = . ;
+ PROVIDE (end = .);
+}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
#
-# (C) Copyright 2004-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
-# Added support for Wind River SBC8560 board
+# Copyright 2012 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
LIB = $(obj)lib$(BOARD).o
COBJS-y += $(BOARD).o
+COBJS-y += ddr.o
+COBJS-$(CONFIG_T4240QDS)+= eth.o
+COBJS-$(CONFIG_PCI) += pci.o
COBJS-y += law.o
COBJS-y += tlb.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS))
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {4, 1350, 5, 9, 0x08070605, 0x07080805, 0xff, 2, 0},
+ {4, 1666, 5, 8, 0x08070605, 0x07080805, 0xff, 2, 0},
+ {4, 2140, 5, 8, 0x08070605, 0x07081805, 0xff, 2, 0},
+ {2, 1350, 5, 7, 0x0809090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {2, 2140, 5, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {1, 1350, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1900, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0},
+ {1, 2140, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twoT_en = pbsp->force_2T;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found "
+ "for data rate %lu MT/s\n"
+ "Trying to use the highest speed (%u) parameters\n",
+ ddr_freq, pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twoT_en = pbsp_highest->force_2T;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+
+#include "t4240qds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII 0
+#define EMI1_SLOT1 1
+#define EMI1_SLOT2 2
+#define EMI1_SLOT3 3
+#define EMI1_SLOT4 4
+#define EMI1_SLOT5 5
+#define EMI1_SLOT7 7
+#define EMI2 8 /* tmp, FIXME */
+/* Slot6 and Slot8 do not have EMI connections */
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char *mdio_names[] = {
+ "T4240QDS_MDIO0",
+ "T4240QDS_MDIO1",
+ "T4240QDS_MDIO2",
+ "T4240QDS_MDIO3",
+ "T4240QDS_MDIO4",
+ "T4240QDS_MDIO5",
+ "NULL",
+ "T4240QDS_MDIO7",
+ "T4240QDS_10GC",
+};
+
+static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2};
+static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4};
+
+static const char *t4240qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = t4240qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct t4240qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void t4240qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+ if ((muxval < 6) || (muxval == 7)) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct t4240qds_mdio *priv = bus->priv;
+
+ t4240qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct t4240qds_mdio *priv = bus->priv;
+
+ t4240qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int t4240qds_mdio_reset(struct mii_dev *bus)
+{
+ struct t4240qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int t4240qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct t4240qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate T4240QDS MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate T4240QDS private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = t4240qds_mdio_read;
+ bus->write = t4240qds_mdio_write;
+ bus->reset = t4240qds_mdio_reset;
+ sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
+ enum fm_port port, int offset)
+{
+ if (mdio_mux[port] == EMI1_RGMII)
+ fdt_set_phy_handle(blob, prop, pa, "phy_rgmii");
+
+ /* TODO: will do with dts */
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ /* TODO: will do with dts */
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
+ t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+
+ switch (srds_prtcl_s1) {
+ case 1:
+ case 2:
+ case 4:
+ /* XAUI/HiGig in Slot1 and Slot2 */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+ break;
+ case 28:
+ case 36:
+ /* SGMII in Slot1 and Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+ fm_info_set_phy_address(FM1_DTSEC9,
+ SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10,
+ SGMII_CARD_PORT3_PHY_ADDR);
+ }
+ break;
+ case 38:
+ fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR);
+ if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+ fm_info_set_phy_address(FM1_DTSEC9,
+ QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10,
+ QSGMII_CARD_PHY_ADDR);
+ }
+ break;
+ case 40:
+ case 46:
+ case 48:
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
+ fm_info_set_phy_address(FM1_DTSEC10,
+ SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC9,
+ SGMII_CARD_PORT4_PHY_ADDR);
+ }
+ fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ break;
+ default:
+ puts("Invalid SerDes1 protocol for T4240QDS\n");
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ int idx = i - FM1_DTSEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm1[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /* FM1 DTSEC5 routes to RGMII with EC2 */
+ debug("FM1@DTSEC%u is RGMII at address %u\n",
+ idx + 1, 2);
+ if (i == FM1_DTSEC5)
+ fm_info_set_phy_address(i, 2);
+ mdio_mux[i] = EMI1_RGMII;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+ switch (srds_prtcl_s2) {
+ case 1:
+ case 2:
+ case 4:
+ /* XAUI/HiGig in Slot3 and Slot4 */
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
+ break;
+ case 7:
+ case 13:
+ case 14:
+ case 16:
+ case 22:
+ case 23:
+ case 25:
+ case 26:
+ /* XAUI/HiGig in Slot3, SGMII in Slot4 */
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 28:
+ case 36:
+ /* SGMII in Slot3 and Slot4 */
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ break;
+ case 38:
+ /* QSGMII in Slot3 and Slot4 */
+ fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR);
+ break;
+ case 40:
+ case 46:
+ case 48:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
+ /* QSGMII in Slot4 */
+ fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ break;
+ case 50:
+ case 52:
+ case 54:
+ fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR);
+ break;
+ case 56:
+ case 57:
+ /* XFI in Slot3, SGMII in Slot4 */
+ fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ default:
+ puts("Invalid SerDes2 protocol for T4240QDS\n");
+ break;
+ }
+
+ for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
+ int idx = i - FM2_DTSEC1, lane, slot;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_2,
+ SGMII_FM2_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot_fsm2[lane];
+ debug("FM2@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ switch (slot) {
+ case 3:
+ mdio_mux[i] = EMI1_SLOT3;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ case 4:
+ mdio_mux[i] = EMI1_SLOT4;
+ fm_info_set_mdio(i,
+ mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ /*
+ * If DTSEC5 is RGMII, then it's routed via via EC1 to
+ * the first on-board RGMII port. If DTSEC6 is RGMII,
+ * then it's routed via via EC2 to the second on-board
+ * RGMII port.
+ */
+ debug("FM2@DTSEC%u is RGMII at address %u\n",
+ idx + 1, i == FM2_DTSEC5 ? 1 : 2);
+ fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
+ mdio_mux[i] = EMI1_RGMII;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+#endif /* CONFIG_SYS_NUM_FMAN */
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
--- /dev/null
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
--- /dev/null
+/*
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __T4020QDS_QIXIS_H__
+#define __T4020QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T4020QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+#define BRDCFG5_RESET 0x00
+
+#define BRDCFG12_SD3EN_MASK 0x20
+#define BRDCFG12_SD3MX_MASK 0x08
+#define BRDCFG12_SD3MX_SLOT5 0x08
+#define BRDCFG12_SD3MX_SLOT6 0x00
+#define BRDCFG12_SD4EN_MASK 0x04
+#define BRDCFG12_SD4MX_MASK 0x03
+#define BRDCFG12_SD4MX_SLOT7 0x02
+#define BRDCFG12_SD4MX_SLOT8 0x01
+#define BRDCFG12_SD4MX_AURO_SATA 0x00
+#endif
--- /dev/null
+/*
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t4qds.h"
+#include "t4240qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ u8 sw;
+ struct cpu_type *cpu = gd->cpu;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ unsigned int i;
+
+ printf("Board: %sQDS, ", cpu->name);
+ printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank: %d\n", sw);
+ else if (sw == 0x8)
+ puts("Promjet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ /* Display the RCW, so that no one gets confused as to what RCW
+ * we're actually using for this boot.
+ */
+ puts("Reset Configuration Word (RCW):");
+ for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+ u32 rcw = in_be32(&gur->rcwsr[i]);
+
+ if ((i % 4) == 0)
+ printf("\n %08x:", i * 4);
+ printf(" %08x", rcw);
+ }
+ puts("\n");
+
+ /*
+ * Display the actual SERDES reference clocks as configured by the
+ * dip switches on the board. Note that the SWx registers could
+ * technically be set to force the reference clocks to match the
+ * values that the SERDES expects (or vice versa). For now, however,
+ * we just display both values and hope the user notices when they
+ * don't match.
+ */
+ puts("SERDES Reference Clocks: ");
+ sw = QIXIS_READ(brdcfg[2]);
+ for (i = 0; i < MAX_SERDES; i++) {
+ static const char *freq[] = {
+ "100", "125", "156.25", "161.1328125"};
+ unsigned int clock = (sw >> (2 * i)) & 3;
+
+ printf("SERDES%u=%sMHz ", i+1, freq[clock]);
+ }
+ puts("\n");
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+/* Configure Crossbar switches for Front-Side SerDes Ports */
+int config_frontside_crossbar_vsc3316(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+ int ret;
+
+ ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
+ if (ret)
+ return ret;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ if (srds_prtcl_s1) {
+ ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
+ if (ret)
+ return ret;
+ }
+
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ if (srds_prtcl_s2) {
+ ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int config_backside_crossbar_mux(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s3, srds_prtcl_s4;
+ u8 brdcfg;
+
+ srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+ srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+ switch (srds_prtcl_s3) {
+ case 0:
+ /* SerDes3 is not enabled */
+ break;
+ case 2:
+ case 9:
+ case 10:
+ /* SD3(0:7) => SLOT5(0:7) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD3MX_MASK;
+ brdcfg |= BRDCFG12_SD3MX_SLOT5;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ case 4:
+ case 6:
+ case 8:
+ case 12:
+ case 14:
+ case 16:
+ case 17:
+ case 19:
+ case 20:
+ /* SD3(4:7) => SLOT6(0:3) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD3MX_MASK;
+ brdcfg |= BRDCFG12_SD3MX_SLOT6;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes3 Protocol %d\n",
+ srds_prtcl_s3);
+ return -1;
+ }
+
+ srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+ srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+ switch (srds_prtcl_s4) {
+ case 0:
+ /* SerDes4 is not enabled */
+ break;
+ case 2:
+ /* 10b, SD4(0:7) => SLOT7(0:7) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD4MX_MASK;
+ brdcfg |= BRDCFG12_SD4MX_SLOT7;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ case 4:
+ case 6:
+ case 8:
+ /* x1b, SD4(4:7) => SLOT8(0:3) */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD4MX_MASK;
+ brdcfg |= BRDCFG12_SD4MX_SLOT8;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ case 10:
+ case 12:
+ case 14:
+ case 16:
+ case 18:
+ /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
+ brdcfg = QIXIS_READ(brdcfg[12]);
+ brdcfg &= ~BRDCFG12_SD4MX_MASK;
+ brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
+ QIXIS_WRITE(brdcfg[12], brdcfg);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes4 Protocol %d\n",
+ srds_prtcl_s4);
+ return -1;
+ }
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ /* Disable remote I2C connectoin */
+ QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
+
+ /* Configure board SERDES ports crossbar */
+ config_frontside_crossbar_vsc3316();
+ config_backside_crossbar_mux();
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ case SRDS_PLLCR0_RFCK_SEL_161_13:
+ return "161.1328125";
+ default:
+ return "???";
+ }
+}
+
+int misc_init_r(void)
+{
+ u8 sw;
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 actual[MAX_SERDES];
+ unsigned int i;
+
+ sw = QIXIS_READ(brdcfg[2]);
+ for (i = 0; i < MAX_SERDES; i++) {
+ unsigned int clock = (sw >> (2 * i)) & 3;
+ switch (clock) {
+ case 0:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
+ break;
+ case 1:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
+ break;
+ case 2:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
+ break;
+ case 3:
+ actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
+ break;
+ }
+ }
+
+ for (i = 0; i < MAX_SERDES; i++) {
+ u32 pllcr0 = srds_regs->bank[i].pllcr0;
+ u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+ if (expected != actual[i]) {
+ printf("Warning: SERDES%u expects reference clock"
+ " %sMHz, but actual is %sMHz\n", i + 1,
+ serdes_clock_to_string(expected),
+ serdes_clock_to_string(actual[i]));
+ }
+ }
+
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
--- /dev/null
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+ {8, 8}, {9, 9}, {14, 14}, {15, 15} };
+
+static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+ {10, 10}, {11, 11}, {12, 12}, {13, 13} };
+
+static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+ {10, 11}, {11, 10}, {12, 2}, {13, 3} };
+
+static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+ {8, 9}, {9, 8}, {14, 1}, {15, 0} };
+#endif
--- /dev/null
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+ CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_1M, 1),
+#endif
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
.sdata : { *(.sdata*) }
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
void ide_set_reset (int on)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ int i;
/*
* Configure PC for IDE Reset Pin
*/
if (on) { /* assert RESET */
immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
+
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+ /* 12V Enable output OFF */
+ immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
+
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
+ immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
+
+ /* wait 500 ms for the voltage to stabilize */
+ for (i = 0; i < 500; ++i)
+ udelay(1000);
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
} else { /* release RESET */
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+ /* 12V Enable output ON */
+ immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
+
+#ifdef CONFIG_SYS_PB_IDE_MOTOR
+ /* configure IDE Motor voltage monitor pin as input */
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+ immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+
+/* wait up to 1 s for the motor voltage to stabilize */
+ for (i = 0; i < 1000; ++i) {
+ if ((immr->im_cpm.cp_pbdat
+ & CONFIG_SYS_PB_IDE_MOTOR) != 0)
+ break;
+ udelay(1000);
+ }
+
+ if (i == 1000) { /* Timeout */
+ printf("\nWarning: 5V for IDE Motor missing\n");
+#ifdef CONFIG_STATUS_LED
+#ifdef STATUS_LED_YELLOW
+ status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
+#endif
+#ifdef STATUS_LED_GREEN
+ status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
+#endif
+#endif /* CONFIG_STATUS_LED */
+ }
+#endif /* CONFIG_SYS_PB_IDE_MOTOR */
+
immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
-#else
+#elif !defined(CONFIG_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
#define SMSTPCR1_CMT0 (1 << 24)
#define SMSTPCR1_I2C0 (1 << 16)
#define SMSTPCR3_USB (1 << 22)
+#define SMSTPCR3_I2C1 (1 << 23)
#define PORT32CR (0xE6051020)
#define PORT33CR (0xE6051021)
clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
- clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
- clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
+ clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
+ clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
writel(VCLKCR1_D, &cpg->vclkcr1);
/* Setup SCIF4 / workaround */
gpio_direction_output(GPIO_PORT15, 1);
/* I2C */
+ gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+ gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
#define IT8212_PCI_IdeBusSkewCONTROL 0x4c
#define IT8212_PCI_IdeDrivingCURRENT 0x42
-extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
extern struct pci_controller hose;
int ide_preinit (void)
#include <netdev.h>
#include <asm/arch/pxa.h>
#include <asm/arch/pxa-regs.h>
+#include <asm/arch/regs-mmc.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
int board_late_init(void)
{
setenv("stdout", "serial");
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
.sdata : { *(.sdata*) }
. = ALIGN(4);
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
}
. = ALIGN(4);
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
} > ram
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) } > ram
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
_endtext = .;
} > ram
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) } > ram
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.rodata : {
*(.rodata);
#include <serial.h>
#include <asm/io.h>
#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
int dram_init(void)
{
pxa2xx_dram_init();
.sdata : { *(.sdata*) }
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
}
}
-void fpga_serial_puts (const char *s)
-{
- while (*s) {
- fpga_serial_print (*s++);
- }
-}
-
int fpga_serial_getc (void)
{
while ((in8 (UART (LSR)) & 0x01) == 0);
extern void fpga_serial_init (int);
extern void fpga_serial_putc (char);
-extern void fpga_serial_puts (const char *);
extern int fpga_serial_getc (void);
extern int fpga_serial_tstc (void);
extern void fpga_serial_setbrg (void);
#include <watchdog.h>
#include <pci.h>
#include <netdev.h>
+#include <serial.h>
#include "hardware.h"
#include "pcippc2.h"
fpga_serial_init (sconsole_get_baudrate ());
sconsole_putc = fpga_serial_putc;
- sconsole_puts = fpga_serial_puts;
+ sconsole_puts = default_serial_puts;
sconsole_getc = fpga_serial_getc;
sconsole_tstc = fpga_serial_tstc;
sconsole_setbrg = fpga_serial_setbrg;
#include <sha1.h>
#include <asm/io.h>
#include <net.h>
+#include <ata.h>
DECLARE_GLOBAL_DATA_PTR;
* ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
* These values are shifted
*/
-extern ulong *ide_bus_offset;
void inline ide_outb(int dev, int port, unsigned char val)
{
debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
udelay (10000);
}
#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+
+/* this is motly the same as it should, causing a little code duplication */
+#if defined(CONFIG_CMD_IDE)
+#define EIEIO __asm__ volatile ("eieio")
+
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ volatile ushort *pbuf =
+ (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ ushort *dbuf = (ushort *) sect_buf;
+
+ debug("in input swap data base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (words--) {
+ *dbuf++ = *pbuf;
+ *dbuf++ = *pbuf;
+ }
+}
+
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *) sect_buf;
+ while (words--) {
+ EIEIO;
+ *pbuf = ld_le16(dbuf++);
+ EIEIO;
+ *pbuf = ld_le16(dbuf++);
+ }
+}
+
+void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *) sect_buf;
+
+ debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+ while (words--) {
+ EIEIO;
+ *dbuf++ = ld_le16(pbuf);
+ EIEIO;
+ *dbuf++ = ld_le16(pbuf);
+ }
+}
+
+#endif
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
-
-static void p3mx_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device p3mx_serial_drv = {
.name = "p3mx_serial",
.start = p3mx_serial_init,
.stop = NULL,
.setbrg = p3mx_serial_setbrg,
.putc = p3mx_serial_putc,
- .puts = p3mx_serial_puts,
+ .puts = default_serial_puts,
.getc = p3mx_serial_getc,
.tstc = p3mx_serial_tstc,
};
#include <command.h>
#include <asm/io.h>
#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
+
int board_late_init(void)
{
setenv("stdout", "serial");
+++ /dev/null
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
+#else
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
. = ALIGN(4);
.sdata : { *(.sdata*) }
- . = .;
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) >> 3;
+#else
num_got_entries = (__got_end - __got_start) >> 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
.sdata : { *(.sdata*) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ } >.sram
+ . = ALIGN(4);
+
/* Align .machine_param on 256 byte boundary for easier searching */
.machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
. = ALIGN(4);
. = ALIGN(4);
.got : { *(.got) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
- . = ALIGN(4);
+ . = align(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = align(4);
.mmudata : { *(.mmudata) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
+++ /dev/null
-The port was tested on Wind River System Sbc8560 board
-<www.windriver.com>. U-Boot was installed on the flash memory of the
-CPU card (no the SODIMM).
-
-NOTE: Please configure uboot compile to the proper PCI frequency and
-setup the appropriate DIP switch settings.
-
-SBC8560 board:
-
-Make sure boards switches are set to their appropriate conditions.
-Refer to the Engineering Reference Guide ERG-00300-002. Of particular
-importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which
-select the on-board FLASH device (Intel 28F128Jx); 2) The settings
-for the Clock SW9 (33 MHz or 66 MHz).
-
- Note: SW9 Settings: 66 MHz
- 4:1 ratio CCB clocks:SYSCLK
- 3:1 ration e500 Core:CCB
- pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on
- Note: SW9 Settings: 33 MHz
- 8:1 ratio CCB clocks:SYSCLK
- 3:1 ration e500 Core:CCB
- pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on
-
-
-Flashing the FLASH device with the "Wind River ICE":
-
-1) Properly connect and configure the Wind River ICE to the target
- JTAG port. This includes running the SBC8560 register script. Make
- sure target memory can be read and written.
-
-2) Build the u-boot image:
- make distclean
- make SBC8560_66_config or SBC8560_33_config
- make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
-
- Note: reference is made to the ELDK3.0 compiler. Further, it seems
- the ppc_8xx compiler is required for the 85xx (no 85xx
- designated compiler in ELDK3.0)
-
-3) Convert the uboot (.elf) file to a uboot.bin file (using
- visionClick converter). The bin file should be converted from
- fffc0000 to ffffffff
-
-4) Setup the Flash Utility (tools menu) for:
-
- Do a "dc clr" [visionClick] to load the default register settings
- Determine the clock speed of the PCI bus and set SW9 accordingly
- Note: the speed of the PCI bus defaults to the slowest PCI card
- PlayBack the "default" register file for the SBC8560
- Select the uboot.bin file with zero bias
- Select the initialize Target prior to programming
- Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm
- Select the erase base address from FFFC0000 to FFFFFFFF
- Select the start address from 0 with size of 4000
-
-5) Erase and Program
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(512M) -or- larger
- * c000_0000-cfff_ffff: PCI(256M)
- * d000_0000-dfff_ffff: RapidIO(256M)
- * e000_0000-ffff_ffff: localbus(512M)
- * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
- * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
- * e800_0000-efff_ffff: LBC 128M, nothing here
- * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
- * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
- * f800_0000-fdff_ffff: LBC 64M, nothing here
- * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
- * fd00_0000-fdff_ffff: LBC 16M, nothing here
- * fe00_0000-feff_ffff: LBC 16M, nothing here
- * ff00_0000-ff6f_ffff: LBC 7M, nothing here
- * ff70_0000-ff7f_ffff: CCSRBAR 1M
- * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- * Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-#endif
- SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-/*
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
- /* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */
- /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-int board_early_init_f (void)
-{
-#if defined(CONFIG_PCI)
- volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-
- pci->peer &= 0xfffffffdf; /* disable master abort */
-#endif
- return 0;
-}
-
-void reset_phy (void)
-{
-#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
- volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
-#endif
- /* reset Giga bit Ethernet port if needed here */
-
- /* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
- bcsr[0] &= ~0x20;
- udelay(2);
- bcsr[0] |= 0x20;
- udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
- bcsr[0] &= ~0x10;
- udelay(2);
- bcsr[0] |= 0x10;
- udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- /* reset PHY */
- miiphy_reset("FCC1", 0x0);
-
- /* change PHY address to 0x02 */
- bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
-
- bb_miiphy_write(NULL, 0x02, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_MII */
-}
-
-int checkboard (void)
-{
- sys_info_t sysinfo;
- char buf[32];
-
- get_sys_info (&sysinfo);
-
-#ifdef CONFIG_SBC8560
- printf ("Board: Wind River SBC8560 Board\n");
-#else
- printf ("Board: Wind River SBC8540 Board\n");
-#endif
- printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
- printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
- printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
- if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
- || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
- printf ("\tLBC: %s MHz\n",
- strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
- } else {
- printf("\tLBC: unknown\n");
- }
- printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
- printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
- return (0);
-}
-
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000
-
- #ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
-#if (CONFIG_SYS_SDRAM_SIZE == 512)
- ddr->cs0_bnds = 0x0000000f;
-#else
- ddr->cs0_bnds = 0x00000007;
-#endif
- ddr->cs1_bnds = 0x0010001f;
- ddr->cs2_bnds = 0x00000000;
- ddr->cs3_bnds = 0x00000000;
- ddr->cs0_config = 0x80000102;
- ddr->cs1_config = 0x80000102;
- ddr->cs2_config = 0x00000000;
- ddr->cs3_config = 0x00000000;
- ddr->timing_cfg_1 = 0x37334321;
- ddr->timing_cfg_2 = 0x00000800;
- ddr->sdram_cfg = 0x42000000;
- ddr->sdram_mode = 0x00000022;
- ddr->sdram_interval = 0x05200100;
- ddr->err_sbe = 0x00ff0000;
- #if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- #endif
- asm("sync;isync;msync");
- udelay(500);
- #if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
- #else
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- #endif
- asm("sync; isync; msync");
- udelay(500);
- #endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- int node;
-#ifdef CONFIG_PCI
- const char *path;
-#endif
-
- ft_cpu_setup(blob, bd);
-
- node = fdt_path_offset(blob, "/aliases");
- if (node >= 0) {
-#ifdef CONFIG_PCI
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = hose.last_busno - hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
- }
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-/* TLB for CCSRBAR (IMMR) */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-/* TLB for Local Bus stuff, just map the whole 512M */
-/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
-
- SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_16K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
******************************************************************/
void ether_init (void)
{
-#ifdef CONFIG_DRIVER_LAN91C96
+#ifdef CONFIG_LAN91C96
int cnt = 20;
__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/pxa.h>
+#include <asm/arch/regs-mmc.h>
#include <netdev.h>
#include <asm/io.h>
return dm9000_initialize(bis);
}
#endif
+
+#ifdef CONFIG_CMD_MMC
+int board_mmc_init(bd_t *bis)
+{
+ pxa_mmc_register(0);
+ return 0;
+}
+#endif
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
*(.data)
}
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(4);
.rel.dyn : {
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
M5329AFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=0
M5329BFEE m68k mcf532x m5329evb freescale - M5329EVB:NANDFLASH_SIZE=16
M5373EVB m68k mcf532x m5373evb freescale - M5373EVB:NANDFLASH_SIZE=16
+M54418TWR m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
+M54418TWR_nand_mii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000
+M54418TWR_nand_rmii m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
+M54418TWR_nand_rmii_lowfreq m68k mcf5445x m54418twr freescale - M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
+M54418TWR_serial_mii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000
+M54418TWR_serial_rmii m68k mcf5445x m54418twr freescale - M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000
M54451EVB m68k mcf5445x m54451evb freescale - M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000
M54451EVB_stmicro m68k mcf5445x m54451evb freescale - M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000
M54455EVB m68k mcf5445x m54455evb freescale - M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
+qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN
+qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
sorcery powerpc mpc8220
Yukon8220 powerpc mpc8220 alaska
A3000 powerpc mpc824x a3000
-BMW powerpc mpc824x bmw
CPC45 powerpc mpc824x cpc45 - - CPC45
CPC45_ROMBOOT powerpc mpc824x cpc45 - - CPC45:BOOT_ROM
CU824 powerpc mpc824x cu824
SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
TQM834x powerpc mpc83xx tqm834x tqc
-suvd3 powerpc mpc83xx km83xx keymile
+suvd3 powerpc mpc83xx km83xx keymile - suvd3:SUVD3
+kmvect1 powerpc mpc83xx km83xx keymile - suvd3:KMVECT1
tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,TUGE1
tuxx1 powerpc mpc83xx km83xx keymile
kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,KMSUPX5
-sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
-sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
-sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540
sbc8548 powerpc mpc85xx sbc8548 - - sbc8548
sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE
sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66
sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE
-sbc8560 powerpc mpc85xx sbc8560 - - sbc8560
-sbc8560_33 powerpc mpc85xx sbc8560 - - sbc8560
-sbc8560_66 powerpc mpc85xx sbc8560 - - sbc8560
socrates powerpc mpc85xx socrates
HWW1U1A powerpc mpc85xx hww1u1a exmeritus
MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
+T4240QDS powerpc mpc85xx t4qds freescale
+T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
+T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
xpedite520x powerpc mpc85xx - xes
xpedite537x powerpc mpc85xx - xes
xpedite550x powerpc mpc85xx - xes
COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o
+COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
endif
+COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
COBJS-y += console.o
COBJS-y += dlmalloc.o
COBJS-y += image.o
--- /dev/null
+/*
+ * Generic bounce buffer implementation
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <bouncebuf.h>
+
+static int addr_aligned(void *data, size_t len)
+{
+ const ulong align_mask = ARCH_DMA_MINALIGN - 1;
+
+ /* Check if start is aligned */
+ if ((ulong)data & align_mask) {
+ debug("Unaligned start address %p\n", data);
+ return 0;
+ }
+
+ data += len;
+
+ /* Check if end is aligned */
+ if ((ulong)data & align_mask) {
+ debug("Unaligned end address %p\n", data);
+ return 0;
+ }
+
+ /* Aligned */
+ return 1;
+}
+
+int bounce_buffer_start(void **data, size_t len, void **backup, uint8_t flags)
+{
+ void *tmp;
+ size_t alen;
+
+ if (addr_aligned(*data, len)) {
+ *backup = NULL;
+ return 0;
+ }
+
+ alen = roundup(len, ARCH_DMA_MINALIGN);
+ tmp = memalign(ARCH_DMA_MINALIGN, alen);
+
+ if (!tmp)
+ return -ENOMEM;
+
+ if (flags & GEN_BB_READ)
+ memcpy(tmp, *data, len);
+
+ *backup = *data;
+ *data = tmp;
+
+ return 0;
+}
+
+int bounce_buffer_stop(void **data, size_t len, void **backup, uint8_t flags)
+{
+ void *tmp = *data;
+
+ /* The buffer was already aligned, since "backup" is NULL. */
+ if (!*backup)
+ return 0;
+
+ if (flags & GEN_BB_WRITE)
+ memcpy(*backup, *data, len);
+
+ *data = *backup;
+ free(tmp);
+
+ return 0;
+}
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
printf("IP addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %6ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", bd->bi_baudrate);
print_num("relocaddr", gd->relocaddr);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
+ printf("baudrate = %u bps\n", (ulong)bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %6ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", bd->bi_baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %lu bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
print_num("TLB addr", gd->tlb_addr);
#endif
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CBFS commands
+ */
+#include <common.h>
+#include <command.h>
+#include <cbfs.h>
+
+int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ uintptr_t end_of_rom = 0xffffffff;
+ char *ep;
+
+ if (argc > 2) {
+ printf("usage: cbfsls [end of rom]>\n");
+ return 0;
+ }
+ if (argc == 2) {
+ end_of_rom = (int)simple_strtoul(argv[1], &ep, 16);
+ if (*ep) {
+ puts("\n** Invalid end of ROM **\n");
+ return 1;
+ }
+ }
+ file_cbfs_init(end_of_rom);
+ if (file_cbfs_result != CBFS_SUCCESS) {
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsinit, 2, 0, do_cbfs_init,
+ "initialize the cbfs driver",
+ "[end of rom]\n"
+ " - Initialize the cbfs driver. The optional 'end of rom'\n"
+ " parameter specifies where the end of the ROM is that the\n"
+ " CBFS is in. It defaults to 0xFFFFFFFF\n"
+);
+
+int do_cbfs_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct cbfs_cachenode *file;
+ unsigned long offset;
+ unsigned long count;
+ char buf[12];
+ long size;
+
+ if (argc < 3) {
+ printf("usage: cbfsload <addr> <filename> [bytes]\n");
+ return 1;
+ }
+
+ /* parse offset and count */
+ offset = simple_strtoul(argv[1], NULL, 16);
+ if (argc == 4)
+ count = simple_strtoul(argv[3], NULL, 16);
+ else
+ count = 0;
+
+ file = file_cbfs_find(argv[2]);
+ if (!file) {
+ if (file_cbfs_result == CBFS_FILE_NOT_FOUND)
+ printf("%s: %s\n", file_cbfs_error(), argv[2]);
+ else
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+
+ printf("reading %s\n", file_cbfs_name(file));
+
+ size = file_cbfs_read(file, (void *)offset, count);
+
+ printf("\n%ld bytes read\n", size);
+
+ sprintf(buf, "%lX", size);
+ setenv("filesize", buf);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsload, 4, 0, do_cbfs_fsload,
+ "load binary file from a cbfs filesystem",
+ "<addr> <filename> [bytes]\n"
+ " - load binary file 'filename' from the cbfs to address 'addr'\n"
+);
+
+int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct cbfs_cachenode *file = file_cbfs_get_first();
+ int files = 0;
+
+ if (!file) {
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+
+ printf(" size type name\n");
+ printf("------------------------------------------\n");
+ while (file) {
+ u32 type = file_cbfs_type(file);
+ char *type_name = NULL;
+ const char *filename = file_cbfs_name(file);
+
+ printf(" %8d", file_cbfs_size(file));
+
+ switch (type) {
+ case CBFS_TYPE_STAGE:
+ type_name = "stage";
+ break;
+ case CBFS_TYPE_PAYLOAD:
+ type_name = "payload";
+ break;
+ case CBFS_TYPE_OPTIONROM:
+ type_name = "option rom";
+ break;
+ case CBFS_TYPE_BOOTSPLASH:
+ type_name = "boot splash";
+ break;
+ case CBFS_TYPE_RAW:
+ type_name = "raw";
+ break;
+ case CBFS_TYPE_VSA:
+ type_name = "vsa";
+ break;
+ case CBFS_TYPE_MBI:
+ type_name = "mbi";
+ break;
+ case CBFS_TYPE_MICROCODE:
+ type_name = "microcode";
+ break;
+ case CBFS_COMPONENT_CMOS_DEFAULT:
+ type_name = "cmos default";
+ break;
+ case CBFS_COMPONENT_CMOS_LAYOUT:
+ type_name = "cmos layout";
+ break;
+ case -1UL:
+ type_name = "null";
+ break;
+ }
+ if (type_name)
+ printf(" %16s", type_name);
+ else
+ printf(" %16d", type);
+
+ if (filename[0])
+ printf(" %s\n", filename);
+ else
+ printf(" %s\n", "(empty)");
+ file_cbfs_get_next(&file);
+ files++;
+ }
+
+ printf("\n%d file(s)\n\n", files);
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsls, 1, 1, do_cbfs_ls,
+ "list files",
+ " - list the files in the cbfs\n"
+);
+
+int do_cbfs_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct cbfs_header *header = file_cbfs_get_header();
+
+ if (!header) {
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+
+ printf("\n");
+ printf("CBFS version: %#x\n", header->version);
+ printf("ROM size: %#x\n", header->rom_size);
+ printf("Boot block size: %#x\n", header->boot_block_size);
+ printf("CBFS size: %#x\n",
+ header->rom_size - header->boot_block_size - header->offset);
+ printf("Alignment: %d\n", header->align);
+ printf("Offset: %#x\n", header->offset);
+ printf("\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsinfo, 1, 1, do_cbfs_fsinfo,
+ "print information about filesystem",
+ " - print information about the cbfs filesystem\n"
+);
#define MAX_LEVEL 32 /* how deeply nested we will go */
#define SCRATCHPAD 1024 /* bytes of scratchpad memory */
+#ifndef CONFIG_CMD_FDT_MAX_DUMP
+#define CONFIG_CMD_FDT_MAX_DUMP 64
+#endif
/*
* Global data (for the gd->bd)
static int fdt_valid(void);
static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
static int fdt_print(const char *pathp, char *prop, int depth);
+static int is_printable_string(const void *data, int len);
/*
* The working_fdt points to our working flattened device tree.
setenv("fdtaddr", buf);
}
+/*
+ * Get a value from the fdt and format it to be set in the environment
+ */
+static int fdt_value_setenv(const void *nodep, int len, const char *var)
+{
+ if (is_printable_string(nodep, len))
+ setenv(var, (void *)nodep);
+ else if (len == 4) {
+ char buf[11];
+
+ sprintf(buf, "0x%08X", *(uint32_t *)nodep);
+ setenv(var, buf);
+ } else if (len%4 == 0 && len <= 20) {
+ /* Needed to print things like sha1 hashes. */
+ char buf[41];
+ int i;
+
+ for (i = 0; i < len; i += sizeof(unsigned int))
+ sprintf(buf + (i * 2), "%08x",
+ *(unsigned int *)(nodep + i));
+ setenv(var, buf);
+ } else {
+ printf("error: unprintable value\n");
+ return 1;
+ }
+ return 0;
+}
+
/*
* Flattened Device Tree command, see the help for parameter definitions.
*/
return 1;
}
+ /********************************************************************
+ * Get the value of a property in the working_fdt.
+ ********************************************************************/
+ } else if (argv[1][0] == 'g') {
+ char *subcmd; /* sub-command */
+ char *pathp; /* path */
+ char *prop; /* property */
+ char *var; /* variable to store result */
+ int nodeoffset; /* node offset from libfdt */
+ const void *nodep; /* property node pointer */
+ int len = 0; /* new length of the property */
+
+ /*
+ * Parameters: Node path, property, optional value.
+ */
+ if (argc < 5)
+ return CMD_RET_USAGE;
+
+ subcmd = argv[2];
+
+ if (argc < 6 && subcmd[0] != 's')
+ return CMD_RET_USAGE;
+
+ var = argv[3];
+ pathp = argv[4];
+ prop = argv[5];
+
+ nodeoffset = fdt_path_offset(working_fdt, pathp);
+ if (nodeoffset < 0) {
+ /*
+ * Not found or something else bad happened.
+ */
+ printf("libfdt fdt_path_offset() returned %s\n",
+ fdt_strerror(nodeoffset));
+ return 1;
+ }
+
+ if (subcmd[0] == 'n' || (subcmd[0] == 's' && argc == 5)) {
+ int reqIndex = -1;
+ int startDepth = fdt_node_depth(
+ working_fdt, nodeoffset);
+ int curDepth = startDepth;
+ int curIndex = -1;
+ int nextNodeOffset = fdt_next_node(
+ working_fdt, nodeoffset, &curDepth);
+
+ if (subcmd[0] == 'n')
+ reqIndex = simple_strtoul(argv[5], NULL, 16);
+
+ while (curDepth > startDepth) {
+ if (curDepth == startDepth + 1)
+ curIndex++;
+ if (subcmd[0] == 'n' && curIndex == reqIndex) {
+ const char *nodeName = fdt_get_name(
+ working_fdt, nextNodeOffset, NULL);
+
+ setenv(var, (char *)nodeName);
+ return 0;
+ }
+ nextNodeOffset = fdt_next_node(
+ working_fdt, nextNodeOffset, &curDepth);
+ if (nextNodeOffset < 0)
+ break;
+ }
+ if (subcmd[0] == 's') {
+ /* get the num nodes at this level */
+ char buf[11];
+
+ sprintf(buf, "%d", curIndex + 1);
+ setenv(var, buf);
+ } else {
+ /* node index not found */
+ printf("libfdt node not found\n");
+ return 1;
+ }
+ } else {
+ nodep = fdt_getprop(
+ working_fdt, nodeoffset, prop, &len);
+ if (len == 0) {
+ /* no property value */
+ setenv(var, "");
+ return 0;
+ } else if (len > 0) {
+ if (subcmd[0] == 'v') {
+ int ret;
+
+ ret = fdt_value_setenv(nodep, len, var);
+ if (ret != 0)
+ return ret;
+ } else if (subcmd[0] == 'a') {
+ /* Get address */
+ char buf[11];
+
+ sprintf(buf, "0x%08X", (uint32_t)nodep);
+ setenv(var, buf);
+ } else if (subcmd[0] == 's') {
+ /* Get size */
+ char buf[11];
+
+ sprintf(buf, "0x%08X", len);
+ setenv(var, buf);
+ } else
+ return CMD_RET_USAGE;
+ return 0;
+ } else {
+ printf("libfdt fdt_getprop(): %s\n",
+ fdt_strerror(len));
+ return 1;
+ }
+ }
+
/*
* Print (recursive) / List (single level)
*/
if (len == 0)
return 0;
- /* must terminate with zero */
- if (s[len - 1] != '\0')
+ /* must terminate with zero or '\n' */
+ if (s[len - 1] != '\0' && s[len - 1] != '\n')
return 0;
/* printable or a null byte (concatenated strings) */
- while (((*s == '\0') || isprint(*s)) && (len > 0)) {
+ while (((*s == '\0') || isprint(*s) || isspace(*s)) && (len > 0)) {
/*
* If we see a null, there are three possibilities:
* 1) If len == 1, it is the end of the string, printable
}
if ((len %4) == 0) {
- const u32 *p;
-
- printf("<");
- for (j = 0, p = data; j < len/4; j ++)
- printf("0x%x%s", fdt32_to_cpu(p[j]), j < (len/4 - 1) ? " " : "");
- printf(">");
+ if (len > CONFIG_CMD_FDT_MAX_DUMP)
+ printf("* 0x%08x [0x%08x]", (unsigned int)data, len);
+ else {
+ const u32 *p;
+
+ printf("<");
+ for (j = 0, p = data; j < len/4; j++)
+ printf("0x%08x%s", fdt32_to_cpu(p[j]),
+ j < (len/4 - 1) ? " " : "");
+ printf(">");
+ }
} else { /* anything else... hexdump */
- const u8 *s;
-
- printf("[");
- for (j = 0, s = data; j < len; j++)
- printf("%02x%s", s[j], j < len - 1 ? " " : "");
- printf("]");
+ if (len > CONFIG_CMD_FDT_MAX_DUMP)
+ printf("* 0x%08x [0x%08x]", (unsigned int)data, len);
+ else {
+ const u8 *s;
+
+ printf("[");
+ for (j = 0, s = data; j < len; j++)
+ printf("%02x%s", s[j], j < len - 1 ? " " : "");
+ printf("]");
+ }
}
}
"fdt resize - Resize fdt to size + padding to 4k addr\n"
"fdt print <path> [<prop>] - Recursive print starting at <path>\n"
"fdt list <path> [<prop>] - Print one level starting at <path>\n"
+ "fdt get value <var> <path> <prop> - Get <property> and store in <var>\n"
+ "fdt get name <var> <path> <index> - Get name of node <index> and store in <var>\n"
+ "fdt get addr <var> <path> <prop> - Get start address of <property> and store in <var>\n"
+ "fdt get size <var> <path> [<prop>] - Get size of [<property>] or num nodes and store in <var>\n"
"fdt set <path> <prop> [<val>] - Set <property> [to <val>]\n"
"fdt mknode <path> <node> - Create a new node after <path>\n"
"fdt rm <path> [<prop>] - Delete the node or <property>\n"
int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- return _do_help(&__u_boot_cmd_start,
- &__u_boot_cmd_end - &__u_boot_cmd_start,
- cmdtp, flag, argc, argv);
+ cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
+ const int len = ll_entry_count(cmd_tbl_t, cmd);
+ return _do_help(start, len, cmdtp, flag, argc, argv);
}
U_BOOT_CMD(
);
/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
-cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
+ll_entry_declare(cmd_tbl_t, question_mark, cmd, cmd) = {
"?", CONFIG_SYS_MAXARGS, 1, do_help,
"alias for 'help'",
#ifdef CONFIG_SYS_LONGHELP
return 0;
}
+static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u_char chip;
+ uint devaddr, alen, length;
+ u_char *memaddr;
+
+ if (argc != 5)
+ return cmd_usage(cmdtp);
+
+ /*
+ * memaddr is the address where to store things in memory
+ */
+ memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
+
+ /*
+ * I2C chip address
+ */
+ chip = simple_strtoul(argv[2], NULL, 16);
+
+ /*
+ * I2C data address within the chip. This can be 1 or
+ * 2 bytes long. Some day it might be 3 bytes long :-).
+ */
+ devaddr = simple_strtoul(argv[3], NULL, 16);
+ alen = get_alen(argv[3]);
+ if (alen > 3)
+ return cmd_usage(cmdtp);
+
+ /*
+ * Length is the number of objects, not number of bytes.
+ */
+ length = simple_strtoul(argv[4], NULL, 16);
+
+ while (length-- > 0) {
+ if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
+ puts("Error writing to the chip.\n");
+ return 1;
+ }
+/*
+ * No write delay with FRAM devices.
+ */
+#if !defined(CONFIG_SYS_I2C_FRAM)
+ udelay(11000);
+#endif
+ }
+ return 0;
+}
+
/*
* Syntax:
* i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
/*
* Syntax:
- * i2c probe {addr}{.0, .1, .2}
+ * i2c probe {addr}
+ *
+ * Returns zero (success) if one or more I2C devices was found
*/
static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int j;
+ int addr = -1;
+ int found = 0;
#if defined(CONFIG_SYS_I2C_NOPROBES)
int k, skip;
uchar bus = GET_BUS_NUM;
#endif /* NOPROBES */
+ if (argc == 2)
+ addr = simple_strtol(argv[1], 0, 16);
+
puts ("Valid chip addresses:");
for (j = 0; j < 128; j++) {
+ if ((0 <= addr) && (j != addr))
+ continue;
+
#if defined(CONFIG_SYS_I2C_NOPROBES)
skip = 0;
for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
if (skip)
continue;
#endif
- if (i2c_probe(j) == 0)
+ if (i2c_probe(j) == 0) {
printf(" %02X", j);
+ found++;
+ }
}
putc ('\n');
putc ('\n');
#endif
- return 0;
+ return (0 == found);
}
/*
U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
+ U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
#if defined(CONFIG_CMD_SDRAM)
U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
- "i2c probe - show devices on the I2C bus\n"
+ "i2c probe [address] - test for and show device(s) on the I2C bus\n"
"i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
+ "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
"i2c reset - re-init the I2C Controller\n"
#if defined(CONFIG_CMD_SDRAM)
"i2c sdram chip - print SDRAM configuration information\n"
# include <pcmcia.h>
#endif
-#ifdef CONFIG_8xx
-# include <mpc8xx.h>
-#endif
-
-#ifdef CONFIG_MPC5xxx
-#include <mpc5xxx.h>
-#endif
-
#include <ide.h>
#include <ata.h>
# include <status_led.h>
#endif
-#ifdef CONFIG_IDE_8xx_DIRECT
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
#ifdef __PPC__
# define EIEIO __asm__ volatile ("eieio")
# define SYNC __asm__ volatile ("sync")
# define SYNC /* nothing */
#endif
-#ifdef CONFIG_IDE_8xx_DIRECT
-/* Timings for IDE Interface
- *
- * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk
- * 70 165 30 PIO-Mode 0, [ns]
- * 4 9 2 [Cycles]
- * 50 125 20 PIO-Mode 1, [ns]
- * 3 7 2 [Cycles]
- * 30 100 15 PIO-Mode 2, [ns]
- * 2 6 1 [Cycles]
- * 30 80 10 PIO-Mode 3, [ns]
- * 2 5 1 [Cycles]
- * 25 70 10 PIO-Mode 4, [ns]
- * 2 4 1 [Cycles]
- */
-
-const static pio_config_t pio_config_ns [IDE_MAX_PIO_MODE+1] =
-{
- /* Setup Length Hold */
- { 70, 165, 30 }, /* PIO-Mode 0, [ns] */
- { 50, 125, 20 }, /* PIO-Mode 1, [ns] */
- { 30, 101, 15 }, /* PIO-Mode 2, [ns] */
- { 30, 80, 10 }, /* PIO-Mode 3, [ns] */
- { 25, 70, 10 }, /* PIO-Mode 4, [ns] */
-};
-
-static pio_config_t pio_config_clk [IDE_MAX_PIO_MODE+1];
-
-#ifndef CONFIG_SYS_PIO_MODE
-#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */
-#endif
-static int pio_mode = CONFIG_SYS_PIO_MODE;
-
-/* Make clock cycles and always round up */
-
-#define PCMCIA_MK_CLKS( t, T ) (( (t) * (T) + 999U ) / 1000U )
-
-#endif /* CONFIG_IDE_8xx_DIRECT */
-
/* ------------------------------------------------------------------------- */
/* Current I/O Device */
block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_LED
-# if !defined(CONFIG_BMS2003) && \
- !defined(CONFIG_CPC45) && \
- !defined(CONFIG_KUP4K) && \
- !defined(CONFIG_KUP4X)
-static void ide_led (uchar led, uchar status);
-#else
-extern void ide_led (uchar led, uchar status);
-#endif
-#else
-#define ide_led(a,b) /* dummy */
-#endif
-
#ifdef CONFIG_IDE_RESET
static void ide_reset (void);
#else
#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-static void input_data(int dev, ulong *sect_buf, int words);
-static void output_data(int dev, const ulong *sect_buf, int words);
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
#ifndef CONFIG_SYS_ATA_PORT_ADDR
#endif
-#ifdef CONFIG_IDE_8xx_DIRECT
-static void set_pcmcia_timing (int pmode);
-#endif
-
/* ------------------------------------------------------------------------- */
int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
/* ------------------------------------------------------------------------- */
+void __ide_led(uchar led, uchar status)
+{
+#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
+ static uchar led_buffer; /* Buffer for current LED status */
+
+ uchar *led_port = LED_PORT;
+
+ if (status) /* switch LED on */
+ led_buffer |= led;
+ else /* switch LED off */
+ led_buffer &= ~led;
+
+ *led_port = led_buffer;
+#endif
+}
+
+void ide_led(uchar led, uchar status)
+ __attribute__ ((weak, alias("__ide_led")));
+
+#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
+# define DEVICE_LED(x) 0
+# define LED_IDE1 1
+# define LED_IDE2 2
+#endif
+
+/* ------------------------------------------------------------------------- */
+
inline void __ide_outb(int dev, int port, unsigned char val)
{
debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
void ide_init(void)
{
-
-#ifdef CONFIG_IDE_8xx_DIRECT
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
-#endif
unsigned char c;
int i, bus;
-#if defined(CONFIG_SC3)
- unsigned int ata_reset_time = ATA_RESET_TIME;
-#endif
#ifdef CONFIG_IDE_8xx_PCCARD
- extern int pcmcia_on(void);
extern int ide_devices_found; /* Initialized in check_ide_device() */
#endif /* CONFIG_IDE_8xx_PCCARD */
#ifdef CONFIG_IDE_PREINIT
- extern int ide_preinit(void);
-
WATCHDOG_RESET();
if (ide_preinit()) {
}
#endif /* CONFIG_IDE_PREINIT */
-#ifdef CONFIG_IDE_8xx_PCCARD
- extern int pcmcia_on(void);
- extern int ide_devices_found; /* Initialized in check_ide_device() */
-
- WATCHDOG_RESET();
-
- ide_devices_found = 0;
- /* initialize the PCMCIA IDE adapter card */
- pcmcia_on();
- if (!ide_devices_found)
- return;
- udelay(1000000); /* 1 s */
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
WATCHDOG_RESET();
-#ifdef CONFIG_IDE_8xx_DIRECT
- /* Initialize PIO timing tables */
- for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) {
- pio_config_clk[i].t_setup =
- PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk);
- pio_config_clk[i].t_length =
- PCMCIA_MK_CLKS(pio_config_ns[i].t_length,
- gd->bus_clk);
- pio_config_clk[i].t_hold =
- PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk);
- debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk"
- " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup,
- pio_config_clk[i].t_setup, pio_config_ns[i].t_length,
- pio_config_clk[i].t_length, pio_config_ns[i].t_hold,
- pio_config_clk[i].t_hold);
- }
-#endif /* CONFIG_IDE_8xx_DIRECT */
-
/*
* Reset the IDE just to be sure.
* Light LED's to show
/* ATAPI Drives seems to need a proper IDE Reset */
ide_reset();
-#ifdef CONFIG_IDE_8xx_DIRECT
- /* PCMCIA / IDE initialization for common mem space */
- pcmp->pcmc_pgcrb = 0;
+#ifdef CONFIG_IDE_INIT_POSTRESET
+ WATCHDOG_RESET();
- /* start in PIO mode 0 - most relaxed timings */
- pio_mode = 0;
- set_pcmcia_timing(pio_mode);
-#endif /* CONFIG_IDE_8xx_DIRECT */
+ if (ide_init_postreset()) {
+ puts("ide_preinit_postreset failed\n");
+ return;
+ }
+#endif /* CONFIG_IDE_INIT_POSTRESET */
/*
* Wait for IDE to get ready.
c = ide_inb(dev, ATA_STATUS);
i++;
-#if defined(CONFIG_SC3)
- if (i > (ata_reset_time * 100)) {
-#else
if (i > (ATA_RESET_TIME * 100)) {
-#endif
puts("** Timeout **\n");
/* LED's off */
ide_led((LED_IDE1 | LED_IDE2), 0);
curr_device = -1;
for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-#ifdef CONFIG_IDE_LED
int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
-#endif
ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
ide_dev_desc[i].if_type = IF_TYPE_IDE;
ide_dev_desc[i].dev = i;
}
#endif
+/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_8xx_DIRECT
-
-static void set_pcmcia_timing(int pmode)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
- ulong timings;
-
- debug("Set timing for PIO Mode %d\n", pmode);
-
- timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold)
- | PCMCIA_SST(pio_config_clk[pmode].t_setup)
- | PCMCIA_SL(pio_config_clk[pmode].t_length);
-
- /*
- * IDE 0
- */
- pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0;
- pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0
-#if (CONFIG_SYS_PCMCIA_POR0 != 0)
- | timings
-#endif
- ;
- debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0);
-
- pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1;
- pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1
-#if (CONFIG_SYS_PCMCIA_POR1 != 0)
- | timings
-#endif
- ;
- debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1);
-
- pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2;
- pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2
-#if (CONFIG_SYS_PCMCIA_POR2 != 0)
- | timings
-#endif
- ;
- debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2);
-
- pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3;
- pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3
-#if (CONFIG_SYS_PCMCIA_POR3 != 0)
- | timings
-#endif
- ;
- debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3);
-
- /*
- * IDE 1
- */
- pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4;
- pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4
-#if (CONFIG_SYS_PCMCIA_POR4 != 0)
- | timings
-#endif
- ;
- debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4);
-
- pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5;
- pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5
-#if (CONFIG_SYS_PCMCIA_POR5 != 0)
- | timings
-#endif
- ;
- debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5);
-
- pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6;
- pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6
-#if (CONFIG_SYS_PCMCIA_POR6 != 0)
- | timings
-#endif
- ;
- debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6);
-
- pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7;
- pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7
-#if (CONFIG_SYS_PCMCIA_POR7 != 0)
- | timings
-#endif
- ;
- debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7);
-
-}
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+ __attribute__ ((weak, alias("__ide_input_swap_data")));
-#endif /* CONFIG_IDE_8xx_DIRECT */
+void ide_input_data(int dev, ulong *sect_buf, int words)
+ __attribute__ ((weak, alias("__ide_input_data")));
-/* ------------------------------------------------------------------------- */
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+ __attribute__ ((weak, alias("__ide_output_data")));
/* We only need to swap data if we are running on a big endian cpu. */
-/* But Au1x00 cpu:s already swaps data in big endian mode! */
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SOC_AU1X00)
-#define input_swap_data(x,y,z) input_data(x,y,z)
-#else
-static void input_swap_data(int dev, ulong *sect_buf, int words)
+#if defined(__LITTLE_ENDIAN)
+void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_CPC45)
- uchar i;
- volatile uchar *pbuf_even =
- (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- volatile uchar *pbuf_odd =
- (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- ushort *dbuf = (ushort *) sect_buf;
-
- while (words--) {
- for (i = 0; i < 2; i++) {
- *(((uchar *) (dbuf)) + 1) = *pbuf_even;
- *(uchar *) dbuf = *pbuf_odd;
- dbuf += 1;
- }
- }
+ ide_input_data(dev, sect_buf, words);
+}
#else
+void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
volatile ushort *pbuf =
(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf = (ushort *) sect_buf;
#ifdef __MIPS__
*dbuf++ = swab16p((u16 *) pbuf);
*dbuf++ = swab16p((u16 *) pbuf);
-#elif defined(CONFIG_PCS440EP)
- *dbuf++ = *pbuf;
- *dbuf++ = *pbuf;
#else
*dbuf++ = ld_le16(pbuf);
*dbuf++ = ld_le16(pbuf);
#endif /* !MIPS */
}
-#endif
}
-#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
+#endif /* __LITTLE_ENDIAN */
#if defined(CONFIG_IDE_SWAP_IO)
-static void output_data(int dev, const ulong *sect_buf, int words)
+void __ide_output_data(int dev, const ulong *sect_buf, int words)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (words--) {
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *) sect_buf;
while (words--) {
-#if defined(CONFIG_PCS440EP)
- /* not tested, because CF was write protected */
- EIEIO;
- *pbuf = ld_le16(dbuf++);
- EIEIO;
- *pbuf = ld_le16(dbuf++);
-#else
EIEIO;
*pbuf = *dbuf++;
EIEIO;
*pbuf = *dbuf++;
-#endif
}
-#endif
}
#else /* ! CONFIG_IDE_SWAP_IO */
-static void output_data(int dev, const ulong *sect_buf, int words)
+void __ide_output_data(int dev, const ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_write_data(dev, sect_buf, words);
#endif /* CONFIG_IDE_SWAP_IO */
#if defined(CONFIG_IDE_SWAP_IO)
-static void input_data(int dev, ulong *sect_buf, int words)
+void __ide_input_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (words--) {
- *dbuf++ = *pbuf_even;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_odd;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_even;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_odd;
- EIEIO;
- SYNC;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
debug("in input data base for read is %lx\n", (unsigned long) pbuf);
while (words--) {
-#if defined(CONFIG_PCS440EP)
- EIEIO;
- *dbuf++ = ld_le16(pbuf);
- EIEIO;
- *dbuf++ = ld_le16(pbuf);
-#else
EIEIO;
*dbuf++ = *pbuf;
EIEIO;
*dbuf++ = *pbuf;
-#endif
}
-#endif
}
#else /* ! CONFIG_IDE_SWAP_IO */
-static void input_data(int dev, ulong *sect_buf, int words)
+void __ide_input_data(int dev, ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_read_data(dev, sect_buf, words);
return;
#endif
- input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
+ ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
ident_cpy((unsigned char *) dev_desc->revision, iop.fw_rev,
sizeof(dev_desc->revision));
break;
}
- input_data(device, buffer, ATA_SECTORWORDS);
+ ide_input_data(device, buffer, ATA_SECTORWORDS);
(void) ide_inb(device, ATA_STATUS); /* clear IRQ */
++n;
goto WR_OUT;
}
- output_data(device, buffer, ATA_SECTORWORDS);
+ ide_output_data(device, buffer, ATA_SECTORWORDS);
c = ide_inb(device, ATA_STATUS); /* clear IRQ */
++n;
++blknr;
static void ide_reset(void)
{
-#if defined(CONFIG_SYS_PB_12V_ENABLE) || defined(CONFIG_SYS_PB_IDE_MOTOR)
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-#endif
int i;
curr_device = -1;
WATCHDOG_RESET();
-#ifdef CONFIG_SYS_PB_12V_ENABLE
- /* 12V Enable output OFF */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
-
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
-
- /* wait 500 ms for the voltage to stabilize */
- for (i = 0; i < 500; ++i)
- udelay(1000);
-
- /* 12V Enable output ON */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
-#endif /* CONFIG_SYS_PB_12V_ENABLE */
-
-#ifdef CONFIG_SYS_PB_IDE_MOTOR
- /* configure IDE Motor voltage monitor pin as input */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
-
- /* wait up to 1 s for the motor voltage to stabilize */
- for (i = 0; i < 1000; ++i) {
- if ((immr->im_cpm.cp_pbdat & CONFIG_SYS_PB_IDE_MOTOR) != 0) {
- break;
- }
- udelay(1000);
- }
-
- if (i == 1000) { /* Timeout */
- printf("\nWarning: 5V for IDE Motor missing\n");
-#ifdef CONFIG_STATUS_LED
-#ifdef STATUS_LED_YELLOW
- status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
-#endif
-#ifdef STATUS_LED_GREEN
- status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
-#endif
-#endif /* CONFIG_STATUS_LED */
- }
-#endif /* CONFIG_SYS_PB_IDE_MOTOR */
-
- WATCHDOG_RESET();
-
/* de-assert RESET signal */
ide_set_reset(0);
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_IDE_LED) && \
- !defined(CONFIG_CPC45) && \
- !defined(CONFIG_KUP4K) && \
- !defined(CONFIG_KUP4X)
-
-static uchar led_buffer; /* Buffer for current LED status */
-
-static void ide_led(uchar led, uchar status)
-{
- uchar *led_port = LED_PORT;
-
- if (status) /* switch LED on */
- led_buffer |= led;
- else /* switch LED off */
- led_buffer &= ~led;
-
- *led_port = led_buffer;
-}
-
-#endif /* CONFIG_IDE_LED */
-
#if defined(CONFIG_OF_IDE_FIXUP)
int ide_device_present(int dev)
{
* ATAPI Support
*/
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+ __attribute__ ((weak, alias("__ide_input_data_shorts")));
+
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+ __attribute__ ((weak, alias("__ide_output_data_shorts")));
+
+
#if defined(CONFIG_IDE_SWAP_IO)
/* since ATAPI may use commands with not 4 bytes alligned length
* we have our own transfer functions, 2 bytes alligned */
-static void output_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- while (shorts--) {
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
EIEIO;
*pbuf = *dbuf++;
}
-#endif
}
-static void input_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- while (shorts--) {
- EIEIO;
- *dbuf++ = *pbuf_even;
- EIEIO;
- *dbuf++ = *pbuf_odd;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
EIEIO;
*dbuf++ = *pbuf;
}
-#endif
}
#else /* ! CONFIG_IDE_SWAP_IO */
-static void output_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
-static void input_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
}
/* write command block */
- output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
+ ide_output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
/* ATAPI Command written wait for completition */
udelay(5000); /* device must set bsy */
/* ok now decide if it is an in or output */
if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
debug("Write to device\n");
- output_data_shorts(device, (unsigned short *) buffer,
- n);
+ ide_output_data_shorts(device,
+ (unsigned short *) buffer, n);
} else {
debug("Read from device @ %p shorts %d\n", buffer, n);
- input_data_shorts(device, (unsigned short *) buffer,
- n);
+ ide_input_data_shorts(device,
+ (unsigned short *) buffer, n);
}
}
udelay(5000); /* seems that some CD ROMs need this... */
cmd_tbl_t *find_cmd (const char *cmd)
{
- int len = &__u_boot_cmd_end - &__u_boot_cmd_start;
- return find_cmd_tbl(cmd, &__u_boot_cmd_start, len);
+ cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
+ const int len = ll_entry_count(cmd_tbl_t, cmd);
+ return find_cmd_tbl(cmd, start, len);
}
int cmd_usage(const cmd_tbl_t *cmdtp)
static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
{
- cmd_tbl_t *cmdtp;
+ cmd_tbl_t *cmdtp = ll_entry_start(cmd_tbl_t, cmd);
+ const int count = ll_entry_count(cmd_tbl_t, cmd);
+ const cmd_tbl_t *cmdend = cmdtp + count;
const char *p;
int len, clen;
int n_found = 0;
if (argc == 0) {
/* output full list of commands */
- for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ for (; cmdtp != cmdend; cmdtp++) {
if (n_found >= maxv - 2) {
- cmdv[n_found++] = "...";
+ cmdv[n_found] = "...";
break;
}
- cmdv[n_found++] = cmdtp->name;
+ cmdv[n_found] = cmdtp->name;
}
cmdv[n_found] = NULL;
return n_found;
len = p - cmd;
/* return the partial matches */
- for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ for (; cmdtp != cmdend; cmdtp++) {
clen = strlen(cmdtp->name);
if (clen < len)
/************************************************************************
* Default settings to be used when no valid environment is found
*/
-
-const uchar default_environment[] = {
-#ifdef CONFIG_BOOTARGS
- "bootargs=" CONFIG_BOOTARGS "\0"
-#endif
-#ifdef CONFIG_BOOTCOMMAND
- "bootcmd=" CONFIG_BOOTCOMMAND "\0"
-#endif
-#ifdef CONFIG_RAMBOOTCOMMAND
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#ifdef CONFIG_NFSBOOTCOMMAND
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
-#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
-#endif
-#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
-#endif
-#ifdef CONFIG_ETHADDR
- "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
-#endif
-#ifdef CONFIG_ETH1ADDR
- "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH2ADDR
- "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH4ADDR
- "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH5ADDR
- "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
-#endif
-#ifdef CONFIG_ETHPRIME
- "ethprime=" CONFIG_ETHPRIME "\0"
-#endif
-#ifdef CONFIG_IPADDR
- "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
-#endif
-#ifdef CONFIG_SERVERIP
- "serverip=" __stringify(CONFIG_SERVERIP) "\0"
-#endif
-#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
-#endif
-#ifdef CONFIG_PREBOOT
- "preboot=" CONFIG_PREBOOT "\0"
-#endif
-#ifdef CONFIG_ROOTPATH
- "rootpath=" CONFIG_ROOTPATH "\0"
-#endif
-#ifdef CONFIG_GATEWAYIP
- "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
-#endif
-#ifdef CONFIG_NETMASK
- "netmask=" __stringify(CONFIG_NETMASK) "\0"
-#endif
-#ifdef CONFIG_HOSTNAME
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
-#endif
-#ifdef CONFIG_BOOTFILE
- "bootfile=" CONFIG_BOOTFILE "\0"
-#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
-#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=1\0"
-#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
-#endif
-#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
- "arch=" CONFIG_SYS_ARCH "\0"
- "cpu=" CONFIG_SYS_CPU "\0"
- "board=" CONFIG_SYS_BOARD "\0"
-#ifdef CONFIG_SYS_VENDOR
- "vendor=" CONFIG_SYS_VENDOR "\0"
-#endif
-#ifdef CONFIG_SYS_SOC
- "soc=" CONFIG_SYS_SOC "\0"
-#endif
-#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
- CONFIG_EXTRA_ENV_SETTINGS
-#endif
- "\0"
-};
+#include <env_default.h>
struct hsearch_data env_htab = {
.apply = env_check_apply,
# define ENV_CRC (~0)
#endif
-env_t environment __PPCENV__ = {
- ENV_CRC, /* CRC Sum */
-#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
- 1, /* Flags: valid */
-#endif
- {
-#if defined(CONFIG_BOOTARGS)
- "bootargs=" CONFIG_BOOTARGS "\0"
-#endif
-#if defined(CONFIG_BOOTCOMMAND)
- "bootcmd=" CONFIG_BOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_RAMBOOTCOMMAND)
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_NFSBOOTCOMMAND)
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
-#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
-#endif
-#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
-#endif
-#ifdef CONFIG_ETHADDR
- "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
-#endif
-#ifdef CONFIG_ETH1ADDR
- "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH2ADDR
- "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH4ADDR
- "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH5ADDR
- "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
-#endif
-#ifdef CONFIG_ETHPRIME
- "ethprime=" CONFIG_ETHPRIME "\0"
-#endif
-#ifdef CONFIG_IPADDR
- "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
-#endif
-#ifdef CONFIG_SERVERIP
- "serverip=" __stringify(CONFIG_SERVERIP) "\0"
-#endif
-#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
-#endif
-#ifdef CONFIG_ROOTPATH
- "rootpath=" CONFIG_ROOTPATH "\0"
-#endif
-#ifdef CONFIG_GATEWAYIP
- "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
-#endif
-#ifdef CONFIG_NETMASK
- "netmask=" __stringify(CONFIG_NETMASK) "\0"
-#endif
-#ifdef CONFIG_HOSTNAME
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
-#endif
-#ifdef CONFIG_BOOTFILE
- "bootfile=" CONFIG_BOOTFILE "\0"
-#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
-#endif
-#ifdef CONFIG_PREBOOT
- "preboot=" CONFIG_PREBOOT "\0"
-#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=" "1" "\0"
-#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
-#endif
-#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
- "arch=" CONFIG_SYS_ARCH "\0"
- "cpu=" CONFIG_SYS_CPU "\0"
- "board=" CONFIG_SYS_BOARD "\0"
-#ifdef CONFIG_SYS_VENDOR
- "vendor=" CONFIG_SYS_VENDOR "\0"
-#endif
-#ifdef CONFIG_SYS_SOC
- "soc=" CONFIG_SYS_SOC "\0"
-#endif
-#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
- CONFIG_EXTRA_ENV_SETTINGS
-#endif
- "\0" /* Term. env_t.data with 2 NULs */
- }
-};
+#define DEFAULT_ENV_INSTANCE_EMBEDDED
+#include <env_default.h>
+
#ifdef CONFIG_ENV_ADDR_REDUND
env_t redundand_environment __PPCENV__ = {
0, /* CRC Sum: invalid */
return 0;
}
+#ifndef USE_HOSTCC
+/**
+ * fit_image_hash_get_ignore - get hash ignore flag
+ * @fit: pointer to the FIT format image header
+ * @noffset: hash node offset
+ * @ignore: pointer to an int, will hold hash ignore flag
+ *
+ * fit_image_hash_get_ignore() finds hash ignore property in a given hash node.
+ * If the property is found and non-zero, the hash algorithm is not verified by
+ * u-boot automatically.
+ *
+ * returns:
+ * 0, on ignore not found
+ * value, on ignore found
+ */
+int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore)
+{
+ int len;
+ int *value;
+
+ value = (int *)fdt_getprop(fit, noffset, FIT_IGNORE_PROP, &len);
+ if (value == NULL || len != sizeof(int))
+ *ignore = 0;
+ else
+ *ignore = *value;
+
+ return 0;
+}
+#endif
+
/**
* fit_set_timestamp - set node timestamp property
* @fit: pointer to the FIT format image header
char *algo;
uint8_t *fit_value;
int fit_value_len;
+#ifndef USE_HOSTCC
+ int ignore;
+#endif
uint8_t value[FIT_MAX_HASH_LEN];
int value_len;
int noffset;
}
printf("%s", algo);
+#ifndef USE_HOSTCC
+ fit_image_hash_get_ignore(fit, noffset, &ignore);
+ if (ignore) {
+ printf("-skipped ");
+ continue;
+ }
+#endif
+
if (fit_image_hash_get_value(fit, noffset, &fit_value,
&fit_value_len)) {
err_msg = " error!\nCan't get hash value "
}
}
+ if (noffset == -FDT_ERR_TRUNCATED || noffset == -FDT_ERR_BADSTRUCTURE) {
+ err_msg = " error!\nCorrupted or truncated tree";
+ goto error;
+ }
+
return 1;
error:
tmp = le16_to_cpu(config->wTotalLength);
if (tmp > USB_BUFSIZ) {
- USB_PRINTF("usb_get_configuration_no: failed to get " \
- "descriptor - too long: %d\n", tmp);
+ printf("usb_get_configuration_no: failed to get " \
+ "descriptor - too long: %d\n", tmp);
return -1;
}
le16_to_cpus(&dev->descriptor.idProduct);
le16_to_cpus(&dev->descriptor.bcdDevice);
/* only support for one config for now */
- usb_get_configuration_no(dev, tmpbuf, 0);
+ err = usb_get_configuration_no(dev, tmpbuf, 0);
+ if (err < 0) {
+ printf("usb_new_device: Cannot read configuration, " \
+ "skipping device %04x:%04x\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+ return -1;
+ }
usb_parse_config(dev, tmpbuf, 0);
usb_set_maxpacket(dev);
/* we set the default configuration here */
int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
struct us_data *ss);
unsigned long usb_stor_read(int device, unsigned long blknr,
- unsigned long blkcnt, void *buffer);
+ lbaint_t blkcnt, void *buffer);
unsigned long usb_stor_write(int device, unsigned long blknr,
- unsigned long blkcnt, const void *buffer);
+ lbaint_t blkcnt, const void *buffer);
struct usb_device * usb_get_dev_index(int index);
void uhci_show_temp_int_td(void);
#endif /* CONFIG_USB_BIN_FIXUP */
unsigned long usb_stor_read(int device, unsigned long blknr,
- unsigned long blkcnt, void *buffer)
+ lbaint_t blkcnt, void *buffer)
{
- unsigned long start, blks, buf_addr;
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
unsigned short smallblks;
struct usb_device *dev;
struct us_data *ss;
start = blknr;
blks = blkcnt;
- USB_STOR_PRINTF("\nusb_read: dev %d startblk %lx, blccnt %lx"
+ USB_STOR_PRINTF("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF
" buffer %lx\n", device, start, blks, buf_addr);
do {
} while (blks != 0);
ss->flags &= ~USB_READY;
- USB_STOR_PRINTF("usb_read: end startblk %lx, blccnt %x buffer %lx\n",
+ USB_STOR_PRINTF("usb_read: end startblk " LBAF
+ ", blccnt %x buffer %lx\n",
start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
}
unsigned long usb_stor_write(int device, unsigned long blknr,
- unsigned long blkcnt, const void *buffer)
+ lbaint_t blkcnt, const void *buffer)
{
- unsigned long start, blks, buf_addr;
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
unsigned short smallblks;
struct usb_device *dev;
struct us_data *ss;
start = blknr;
blks = blkcnt;
- USB_STOR_PRINTF("\nusb_write: dev %d startblk %lx, blccnt %lx"
+ USB_STOR_PRINTF("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF
" buffer %lx\n", device, start, blks, buf_addr);
do {
} while (blks != 0);
ss->flags &= ~USB_READY;
- USB_STOR_PRINTF("usb_write: end startblk %lx, blccnt %x buffer %lx\n",
+ USB_STOR_PRINTF("usb_write: end startblk " LBAF
+ ", blccnt %x buffer %lx\n",
start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
#########################################################################
+include $(TOPDIR)/helper.mk
+
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
#define PRINTF(fmt,args...)
#endif
+/* Rather than repeat this expression each time, add a define for it */
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) )
+#define HAVE_BLOCK_DEVICE
+#endif
struct block_drvr {
char *name;
DECLARE_GLOBAL_DATA_PTR;
+#ifdef HAVE_BLOCK_DEVICE
block_dev_desc_t *get_dev(const char *ifname, int dev)
{
const struct block_drvr *drvr = block_drvr;
}
#endif
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) )
+#ifdef HAVE_BLOCK_DEVICE
/* ------------------------------------------------------------------------- */
/*
}
#endif
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) )
-
-#if defined(CONFIG_MAC_PARTITION) || \
- defined(CONFIG_DOS_PARTITION) || \
- defined(CONFIG_ISO_PARTITION) || \
- defined(CONFIG_AMIGA_PARTITION) || \
- defined(CONFIG_EFI_PARTITION)
+#ifdef HAVE_BLOCK_DEVICE
void init_part (block_dev_desc_t * dev_desc)
{
}
+#if defined(CONFIG_MAC_PARTITION) || \
+ defined(CONFIG_DOS_PARTITION) || \
+ defined(CONFIG_ISO_PARTITION) || \
+ defined(CONFIG_AMIGA_PARTITION) || \
+ defined(CONFIG_EFI_PARTITION)
+
static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
{
puts ("\nPartition Map for ");
dev_desc->dev, type);
}
+#endif /* any CONFIG_..._PARTITION */
+
void print_part (block_dev_desc_t * dev_desc)
{
puts ("## Unknown partition table\n");
}
-
-#else /* neither MAC nor DOS nor ISO nor AMIGA nor EFI partition configured */
-# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION
-# error nor CONFIG_ISO_PARTITION nor CONFIG_AMIGA_PARTITION
-# error nor CONFIG_EFI_PARTITION configured!
-#endif
-
-#endif
+#endif /* HAVE_BLOCK_DEVICE */
int get_partition_info(block_dev_desc_t *dev_desc, int part
, disk_partition_t *info)
{
-#if defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE)
+#ifdef HAVE_BLOCK_DEVICE
#ifdef CONFIG_PARTITION_UUIDS
/* The common case is no UUID support */
default:
break;
}
-#endif
+#endif /* HAVE_BLOCK_DEVICE */
return -1;
}
info->size = (*dev_desc)->lba;
info->blksz = (*dev_desc)->blksz;
info->bootable = 0;
+ strcpy((char *)info->type, BOOT_PART_TYPE);
+ strcpy((char *)info->name, "Whole Disk");
#ifdef CONFIG_PARTITION_UUIDS
info->uuid[0] = 0;
#endif
*/
if (p == MAX_SEARCH_PARTITIONS + 1)
*info = tmpinfo;
- ret = 0;
} else {
printf("** No valid partitions found **\n");
+ ret = -1;
goto cleanup;
}
}
return p->boot_ind == 0x80;
}
-static void print_one_part (dos_partition_t *p, int ext_part_sector, int part_num)
+static void print_one_part(dos_partition_t *p, int ext_part_sector,
+ int part_num, unsigned int disksig)
{
int lba_start = ext_part_sector + le32_to_int (p->start4);
int lba_size = le32_to_int (p->size4);
- printf("%5d\t\t%10d\t%10d\t%2x%s%s\n",
- part_num, lba_start, lba_size, p->sys_ind,
+ printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n",
+ part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
(is_extended(p->sys_ind) ? " Extd" : ""),
(is_bootable(p) ? " Boot" : ""));
}
/* Print a partition that is relative to its Extended partition table
*/
-static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative,
- int part_num)
+static void print_partition_extended(block_dev_desc_t *dev_desc,
+ int ext_part_sector, int relative,
+ int part_num, unsigned int disksig)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
return;
}
+ if (!ext_part_sector)
+ disksig = le32_to_int(&buffer[DOS_PART_DISKSIG_OFFSET]);
+
/* Print all primary/logical partitions */
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if ((pt->sys_ind != 0) &&
(ext_part_sector == 0 || !is_extended (pt->sys_ind)) ) {
- print_one_part (pt, ext_part_sector, part_num);
+ print_one_part(pt, ext_part_sector, part_num, disksig);
}
/* Reverse engr the fdisk part# assignment rule! */
if (is_extended (pt->sys_ind)) {
int lba_start = le32_to_int (pt->start4) + relative;
- print_partition_extended (dev_desc, lba_start,
- ext_part_sector == 0 ? lba_start
- : relative,
- part_num);
+ print_partition_extended(dev_desc, lba_start,
+ ext_part_sector == 0 ? lba_start : relative,
+ part_num, disksig);
}
}
void print_part_dos (block_dev_desc_t *dev_desc)
{
- printf ("Partition Start Sector Num Sectors Type\n");
- print_partition_extended (dev_desc, 0, 0, 1);
+ printf("Part\tStart Sector\tNum Sectors\tUUID\t\tType\n");
+ print_partition_extended(dev_desc, 0, 0, 1, 0);
}
int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition_t * info)
return name;
}
+static void uuid_string(unsigned char *uuid, char *str)
+{
+ static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
+ 12, 13, 14, 15};
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ sprintf(str, "%02x", uuid[le[i]]);
+ str += 2;
+ switch (i) {
+ case 3:
+ case 5:
+ case 7:
+ case 9:
+ *str++ = '-';
+ break;
+ }
+ }
+}
+
+static efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
+
+static inline int is_bootable(gpt_entry *p)
+{
+ return p->attributes.fields.legacy_bios_bootable ||
+ !memcmp(&(p->partition_type_guid), &system_guid,
+ sizeof(efi_guid_t));
+}
+
/*
* Public Functions (include/part.h)
*/
ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
gpt_entry *gpt_pte = NULL;
int i = 0;
+ char uuid[37];
if (!dev_desc) {
printf("%s: Invalid Argument(s)\n", __func__);
debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
- printf("Part\tName\t\t\tStart LBA\tEnd LBA\n");
+ printf("Part\tStart LBA\tEnd LBA\t\tName\n");
+ printf("\tAttributes\n");
+ printf("\tType UUID\n");
+ printf("\tPartition UUID\n");
+
for (i = 0; i < le32_to_int(gpt_head->num_partition_entries); i++) {
+ /* Stop at the first non valid PTE */
+ if (!is_pte_valid(&gpt_pte[i]))
+ break;
- if (is_pte_valid(&gpt_pte[i])) {
- printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1),
- print_efiname(&gpt_pte[i]),
- le64_to_int(gpt_pte[i].starting_lba),
- le64_to_int(gpt_pte[i].ending_lba));
- } else {
- break; /* Stop at the first non valid PTE */
- }
+ printf("%3d\t0x%08llx\t0x%08llx\t\"%s\"\n", (i + 1),
+ le64_to_int(gpt_pte[i].starting_lba),
+ le64_to_int(gpt_pte[i].ending_lba),
+ print_efiname(&gpt_pte[i]));
+ printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw);
+ uuid_string(gpt_pte[i].partition_type_guid.b, uuid);
+ printf("\ttype:\t%s\n", uuid);
+ uuid_string(gpt_pte[i].unique_partition_guid.b, uuid);
+ printf("\tuuid:\t%s\n", uuid);
}
/* Remember to free pte */
return;
}
-#ifdef CONFIG_PARTITION_UUIDS
-static void uuid_string(unsigned char *uuid, char *str)
-{
- static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
- 12, 13, 14, 15};
- int i;
-
- for (i = 0; i < 16; i++) {
- sprintf(str, "%02x", uuid[le[i]]);
- str += 2;
- switch (i) {
- case 3:
- case 5:
- case 7:
- case 9:
- *str++ = '-';
- break;
- }
- }
-}
-#endif
-
int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
disk_partition_t * info)
{
sprintf((char *)info->name, "%s",
print_efiname(&gpt_pte[part - 1]));
sprintf((char *)info->type, "U-Boot");
+ info->bootable = is_bootable(&gpt_pte[part - 1]);
#ifdef CONFIG_PARTITION_UUIDS
uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid);
#endif
count = le32_to_int(pgpt_head->num_partition_entries) *
le32_to_int(pgpt_head->sizeof_partition_entry);
- debug("%s: count = %lu * %lu = %u\n", __func__,
+ debug("%s: count = %lu * %lu = %zu\n", __func__,
le32_to_int(pgpt_head->num_partition_entries),
le32_to_int(pgpt_head->sizeof_partition_entry), count);
}
if (count == 0 || pte == NULL) {
- printf("%s: ERROR: Can't allocate 0x%X bytes for GPT Entries\n",
+ printf("%s: ERROR: Can't allocate 0x%zX "
+ "bytes for GPT Entries\n",
__func__, count);
return NULL;
}
sizeof(unused_guid.b)) == 0) {
debug("%s: Found an unused PTE GUID at 0x%08X\n", __func__,
- (unsigned int)pte);
+ (unsigned int)(uintptr_t)pte);
return 0;
} else {
unsigned char reserved2[GPT_BLOCK_SIZE - 92];
} __attribute__ ((packed)) gpt_header;
-typedef struct _gpt_entry_attributes {
- unsigned long long required_to_function:1;
- unsigned long long reserved:47;
- unsigned long long type_guid_specific:16;
+typedef union _gpt_entry_attributes {
+ struct {
+ unsigned long long required_to_function:1;
+ unsigned long long no_block_io_protocol:1;
+ unsigned long long legacy_bios_bootable:1;
+ unsigned long long reserved:45;
+ unsigned long long type_guid_specific:16;
+ } fields;
+ unsigned long long raw;
} __attribute__ ((packed)) gpt_entry_attributes;
#define PARTNAME_SZ (72 / sizeof(efi_char16_t))
include $(TOPDIR)/config.mk
-DOCBOOKS :=
+DOCBOOKS := linker_lists.xml stdio.xml
###
# The build process is as follows (targets):
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+ "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
+
+<book id="UBootLGArrays">
+ <bookinfo>
+ <title>The U-Boot Linker-Generated Arrays</title>
+
+ <legalnotice>
+ <para>
+ This documentation is free software; you can redistribute
+ it and/or modify it under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later
+ version.
+ </para>
+
+ <para>
+ This program is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU General Public License for more details.
+ </para>
+
+ <para>
+ You should have received a copy of the GNU General Public
+ License along with this program; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ MA 02111-1307 USA
+ </para>
+
+ <para>
+ For more details see the file COPYING in the source
+ distribution of U-Boot Bootloader.
+ </para>
+ </legalnotice>
+ </bookinfo>
+
+<toc></toc>
+
+ <chapter id="adt">
+ <title>Linker-Generated Arrays</title>
+!Iinclude/linker_lists.h
+ </chapter>
+
+</book>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+ "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
+
+<book id="UBootSTDIO">
+ <bookinfo>
+ <title>The U-Boot STDIO subsystem</title>
+
+ <legalnotice>
+ <para>
+ This documentation is free software; you can redistribute
+ it and/or modify it under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later
+ version.
+ </para>
+
+ <para>
+ This program is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU General Public License for more details.
+ </para>
+
+ <para>
+ You should have received a copy of the GNU General Public
+ License along with this program; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ MA 02111-1307 USA
+ </para>
+
+ <para>
+ For more details see the file COPYING in the source
+ distribution of U-Boot Bootloader.
+ </para>
+ </legalnotice>
+ </bookinfo>
+
+<toc></toc>
+
+ <chapter id="adt">
+ <title>U-Boot Serial subsystem</title>
+!Idrivers/serial/serial.c
+ </chapter>
+
+</book>
--- /dev/null
+This file contains API information of the initialization code written for
+Vitesse cross-point devices, VSC3316 and VSC3308 for board B4860QDS
+
+Author: Shaveta Leekha <shaveta@freescale.com>
+
+About Device:
+=============
+VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch capable of data rates upto 11.5Gbps.
+
+VSC3316 has 16 input and 16 output ports whereas VSC3308 has 8 input and 8 output ports. Programming of these devices are performed by two-wire or four-wire serial interface.
+
+Initialization:
+===============
+On reset, VSC devices are in low-power state with all inputs, outputs and connections in an off state.
+First thing required is to program it to interface with either two-wire or four-wire interface.
+In our case the interface is two-wire I2C serial interface. So the value in Interface mode register at address 79.h to be written is 0x02 for two-wire interface. Also for crosspoint connections to be activated, 01.h value need to be written in 75.h (core configuration register).
+
+API Overview:
+=============
+
+ vsc_if_enable(u8 vsc_addr):
+ --------------------------
+ This API programs VSC to interface with either two-wire or four-wire interface. In our case the interface is two-wire I2C serial interface. So the value in Interface mode register at address 79.h to be written is 0x02 for two-wire interface.
+ Parameters:
+ vsc_addr - Address of the VSC device on board.
+
+
+ vsc3316_config(u8 vsc_addr, int con_arr[][2], u8 num_con):
+ ---------------------------------------------------------
+ This API configures the VSC3316 device for required connections. Connection through the VSC device requires the inputs and outputs to be properly configured.
+ Connection registers are on page 00. It Configures the selected input and output correctly and join them to make a connection. It also program Input state register, Global input ISE, Global input LOS, Global core control, Output mode register and core control registers etc.
+ vsc3308_config(u8 vsc_addr, int con_arr[][2], u8 num_con) does the essential configurations for VSC3308.
+
+ Parameters:
+ vsc_addr - Address of the VSC device on board.
+ con_arr - connection array
+ num_con - number of connections to be configured
+
+ vsc_wp_config(u8 vsc_addr):
+ --------------------------
+ For crosspoint connections to be activated, 01.h value need to be written in 75.h (core configuration register), which is done by this API.
+ Parameters:
+ vsc_addr - Address of the VSC device on board.
**** Behind the scene ******
-The structure created is named with a special prefix (__u_boot_cmd_)
+The structure created is named with a special prefix (__u_boot_list_cmd_)
and placed by the linker in a special section.
This makes it possible for the final link to extract all commands
compiled into any object code and construct a static array so the
-command can be found in an array starting at __u_boot_cmd_start.
+command can be found in an array starting at _u_boot_list_cmd__start.
To ensure that the linker does not discard these symbols when linking
full U-Boot we generate a list of all the commands we have built (based
by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these
3 lines:
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include "u-boot.lst";
+ }
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
+ # bank(chip-select) interleaving (auto)
+ setenv hwconfig "fsl_ddr:bank_intlv=auto"
+ This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
+ on DIMMs.
+
Memory controller address hashing
==================================
If the DDR controller supports address hashing, it can be enabled by hwconfig.
--- /dev/null
+Freescale MCF54418TWR ColdFire Development Board
+================================================
+
+TsiChung Liew(Tsi-Chung.Liew@freescale.com)
+Created Mar 22, 2012
+===========================================
+
+
+Changed files:
+==============
+
+- board/freescale/m54418twr/m54418twr.c Dram setup
+- board/freescale/m54418twr/Makefile Makefile
+- board/freescale/m54418twr/config.mk config make
+- board/freescale/m54418twr/u-boot.lds Linker description
+
+- arch/m68k/cpu/mcf5445x/cpu.c cpu specific code
+- arch/m68k/cpu/mcf5445x/cpu_init.c Flexbus ChipSelect, Mux pins setup, icache and RTC extra regs
+- arch/m68k/cpu/mcf5445x/interrupts.c cpu specific interrupt support
+- arch/m68k/cpu/mcf5445x/speed.c system, pci, flexbus, and cpu clock
+- arch/m68k/cpu/mcf5445x/Makefile Makefile
+- arch/m68k/cpu/mcf5445x/config.mk config make
+- arch/m68k/cpu/mcf5445x/start.S start up assembly code
+
+- doc/README.m54418twr This readme file
+
+- drivers/net/mcffec.c ColdFire common FEC driver
+- drivers/net/mcfmii.c ColdFire common MII driver
+- drivers/serial/mcfuart.c ColdFire common UART driver
+
+- arch/m68k/include/asm/bitops.h Bit operation function export
+- arch/m68k/include/asm/byteorder.h Byte order functions
+- arch/m68k/include/asm/fec.h FEC structure and definition
+- arch/m68k/include/asm/global_data.h Global data structure
+- arch/m68k/include/asm/immap.h ColdFire specific header file and driver macros
+- arch/m68k/include/asm/immap_5441x.h mcf5441x specific header file
+- arch/m68k/include/asm/io.h io functions
+- arch/m68k/include/asm/m5441x.h mcf5441x specific header file
+- arch/m68k/include/asm/posix_types.h Posix
+- arch/m68k/include/asm/processor.h header file
+- arch/m68k/include/asm/ptrace.h Exception structure
+- arch/m68k/include/asm/rtc.h Realtime clock header file
+- arch/m68k/include/asm/string.h String function export
+- arch/m68k/include/asm/timer.h Timer structure and definition
+- arch/m68k/include/asm/types.h Data types definition
+- arch/m68k/include/asm/uart.h Uart structure and definition
+- arch/m68k/include/asm/u-boot.h u-boot structure
+
+- include/configs/M54418TWR.h Board specific configuration file
+
+- arch/m68k/lib/board.c board init function
+- arch/m68k/lib/cache.c
+- arch/m68k/lib/interrupts.c Coldfire common interrupt functions
+- arch/m68k/lib/time.c Timer functions (Dma timer and PIT)
+- arch/m68k/lib/traps.c Exception init code
+
+1 MCF5441x specific Options/Settings
+====================================
+1.1 pre-loader is no longer suppoer in thie coldfire family
+
+1.2 Configuration settings for M54418TWR Development Board
+CONFIG_MCF5441x -- define for all MCF5441x CPUs
+CONFIG_M54418 -- define for all Freescale MCF54418 CPUs
+CONFIG_M54418TWR -- define for M54418TWR board
+
+CONFIG_MCFUART -- define to use common CF Uart driver
+CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
+CONFIG_BAUDRATE -- define UART baudrate
+
+CONFIG_MCFFEC -- define to use common CF FEC driver
+CONFIG_MII -- enable to use MII driver
+CONFIG_SYS_DISCOVER_PHY -- enable PHY discovery
+CONFIG_SYS_RX_ETH_BUFFER -- Set FEC Receive buffer
+CONFIG_SYS_FAULT_ECHO_LINK_DOWN --
+CONFIG_SYS_FEC0_PINMUX -- Set FEC0 Pin configuration
+CONFIG_SYS_FEC1_PINMUX -- Set FEC1 Pin configuration
+CONFIG_SYS_FEC0_MIIBASE -- Set FEC0 MII base register
+CONFIG_SYS_FEC1_MIIBASE -- Set FEC0 MII base register
+MCFFEC_TOUT_LOOP -- set FEC timeout loop
+CONFIG_HAS_ETH1 -- define to enable second FEC in u-boot
+
+CONFIG_MCFTMR -- define to use DMA timer
+
+CONFIG_SYS_IMMR -- define for MBAR offset
+
+CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
+
+CONFIG_SYS_MBAR -- define MBAR offset
+
+CONFIG_MONITOR_IS_IN_RAM -- Not support
+
+CONFIG_SYS_INIT_RAM_ADDR -- defines the base address of the MCF54455 internal SRAM
+
+CONFIG_SYS_CSn_BASE -- defines the Chip Select Base register
+CONFIG_SYS_CSn_MASK -- defines the Chip Select Mask register
+CONFIG_SYS_CSn_CTRL -- defines the Chip Select Control register
+
+CONFIG_SYS_SDRAM_BASE -- defines the DRAM Base
+
+2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
+===========================================
+2.1. System memory map:
+ MRAM: 0x00000000-0x0003FFFF (256KB)
+ DDR: 0x40000000-0x47FFFFFF (128MB)
+ SRAM: 0x80000000-0x8000FFFF (64KB)
+ IP: 0xE0000000-0xFFFFFFFF (512MB)
+
+3. COMPILATION
+==============
+3.1 To create U-Boot the gcc-4.x compiler set (ColdFire ELF version)
+from codesourcery.com was used. Download it from:
+http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
+
+3.2 Compilation
+ export CROSS_COMPILE=cross-compile-prefix
+ cd u-boot
+ make distclean
+ make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
+ make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
+ make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
+ make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
+ make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
+ make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
+ make
+
+4. SCREEN DUMP
+==============
+4.1 M54418TWR Development board
+ Boot from NAND flash (NOTE: May not show exactly the same)
+
+U-Boot 2012.10-00209-g12ae1d8-dirty (Oct 18 2012 - 15:54:54)
+
+CPU: Freescale MCF54418 (Mask:a3 Version:1)
+ CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
+ INP CLK 50 MHz VCO CLK 500 MHz
+Board: Freescale MCF54418 Tower System
+SPI: ready
+DRAM: 128 MiB
+NAND: 256 MiB
+In: serial
+Out: serial
+Err: serial
+Net: FEC0, FEC1
+-> pri
+baudrate=115200
+bootargs=root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(k
+ernel)ro,-(jffs2) console=ttyS0,115200
+bootdelay=2
+eth1addr=00:e0:0c:bc:e5:61
+ethact=FEC0
+ethaddr=00:e0:0c:bc:e5:60
+fileaddr=40010000
+filesize=27354
+gatewayip=192.168.1.1
+hostname=M54418TWR
+inpclk=50000000
+ipaddr=192.168.1.2
+load=tftp ${loadaddr} ${u-boot};
+loadaddr=0x40010000
+mem=129024k
+netdev=eth0
+netmask=255.255.255.0
+prog=nand device 0;nand erase 0 40000;nb_update ${loadaddr} ${filesize};save
+serverip=192.168.1.1
+stderr=serial
+stdin=serial
+stdout=serial
+u-boot=u-boot.bin
+upd=run load; run prog
+
+Environment size: 653/131068 bytes
+-> bdinfo
+memstart = 0x40000000
+memsize = 0x08000000
+flashstart = 0x00000000
+flashsize = 0x00000000
+flashoffset = 0x00000000
+sramstart = 0x80000000
+sramsize = 0x00010000
+mbar = 0xFC000000
+cpufreq = 250 MHz
+busfreq = 125 MHz
+flbfreq = 125 MHz
+inpfreq = 50 MHz
+vcofreq = 500 MHz
+ethaddr = 00:e0:0c:bc:e5:60
+eth1addr = 00:e0:0c:bc:e5:61
+ip_addr = 192.168.1.2
+baudrate = 115200 bps
+-> help
+? - alias for 'help'
+base - print or set address offset
+bdinfo - print Board Info structure
+boot - boot default, i.e., run 'bootcmd'
+bootd - boot default, i.e., run 'bootcmd'
+bootelf - Boot from an ELF image in memory
+bootm - boot application image from memory
+bootp - boot image via network using BOOTP/TFTP protocol
+bootvx - Boot vxWorks from an ELF image
+cmp - memory compare
+coninfo - print console devices and information
+cp - memory copy
+crc32 - checksum calculation
+dcache - enable or disable data cache
+dhcp - boot image via network using DHCP/TFTP protocol
+echo - echo args to console
+editenv - edit environment variable
+env - environment handling commands
+exit - exit script
+false - do nothing, unsuccessfully
+go - start application at address 'addr'
+help - print command description/usage
+icache - enable or disable instruction cache
+iminfo - print header information for application image
+imxtract- extract a part of a multi-image
+itest - return true/false on integer compare
+loop - infinite loop on address range
+md - memory display
+mdio - MDIO utility commands
+mii - MII utility commands
+mm - memory modify (auto-incrementing address)
+mtest - simple RAM read/write test
+mw - memory write (fill)
+nand - NAND sub-system
+nb_update- Nand boot update program
+nboot - boot from NAND device
+nfs - boot image via network using NFS protocol
+nm - memory modify (constant address)
+ping - send ICMP ECHO_REQUEST to network host
+printenv- print environment variables
+reginfo - print register information
+reset - Perform RESET of the CPU
+run - run commands in an environment variable
+saveenv - save environment variables to persistent storage
+setenv - set environment variables
+sf - SPI flash sub-system
+showvar - print local hushshell variables
+sleep - delay execution for some time
+source - run script from memory
+sspi - SPI utility command
+test - minimal test like /bin/sh
+tftpboot- boot image via network using TFTP protocol
+true - do nothing, successfully
+version - print monitor, compiler and linker version
--- /dev/null
+Spin table in cache
+=====================================
+As specified by ePAPR v1.1, the spin table needs to be in cached memory. After
+DDR is initialized and U-boot relocates itself into DDR, the spin table is
+accessible for core 0. It is part of release.S, within 4KB range after
+__secondary_start_page. For other cores to use the spin table, the booting
+process is described below:
+
+Core 0 sets up the reset page on the top 4K of memory (or 4GB if total memory
+is more than 4GB), and creates a TLB to map it to 0xffff_f000, regardless of
+the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot
+page translation for secondary cores to use this page of memory. Then 4KB
+memory is copied from __secondary_start_page to the boot page, after flusing
+cache because this page is mapped as normal DDR. Before copying the reset page,
+core 0 puts the physical address of the spin table (which is in release.S and
+relocated to the top of mapped memory) into a variable __spin_table_addr so
+that secondary cores can see it.
+
+When secondary cores boot up from 0xffff_f000 page, they only have one default
+TLB. While booting, they set up another TLB in AS=1 space and jump into
+the new space. The new TLB covers the physical address of the spin table page,
+with WIMGE =0b00100. Now secondary cores can keep polling the spin table
+without stress DDR bus because both the code and the spin table is in cache.
+
+For the above to work, DDR has to set the 'M' bit of WIMGE, in order to keep
+cache coherence.
--- /dev/null
+Overview
+--------
+The T4240QDS is a high-performance computing evaluation, development and test
+platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
+optimized to support the high-bandwidth DDR3 memory ports, as well as the
+highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
+
+Board Features
+ SERDES Connections
+ 32 lanes grouped into four 8-lane banks
+ Two “front side” banks dedicated to Ethernet
+ - High-speed crosspoint switch fabric on selected lanes
+ - Two PCI Express slots with side-band connector supporting
+ - SGMII
+ - XAUI
+ - HiGig
+ - I-pass connectors allow board-to-board and loopback support
+ Two “back side” banks dedicated to other protocols
+ - High-speed crosspoint switch fabric on all lanes
+ - Four PCI Express slots with side-band connector supporting
+ - PCI Express 3.0
+ - SATA 2.0
+ - SRIO 2.0
+ - Supports 4X Aurora debug with two connectors
+ DDR Controllers
+ Three independant 64-bit DDR3 controllers
+ Supports rates of 1866 up to 2133 MHz data-rate
+ Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
+ DDR power supplies 1.5V to all devices with automatic tracking of VTT.
+ Power software-switchable to 1.35V if software detects all DDR3LP devices.
+ MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
+ 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
+ increases by 1 clock.
+
+ IFC/Local Bus
+ NAND flash: 8-bit, async or sync, up to 2GB.
+ NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
+ NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
+ - NOR devices support 16 virtual banks
+ GASIC: Minimal target within Qixis FPGA
+ PromJET rapid memory download support
+ Address demultiplexing handled within FPGA.
+ - Flexible demux allows 8 or 16 bit evaluation.
+ IFC Debug/Development card
+ - Support for 32-bit devices
+ Ethernet
+ Support two on-board RGMII 10/100/1G ethernet ports.
+ SGMII and XAUI support via SERDES block (see above).
+ 1588 support via Symmetricom board.
+ QIXIS System Logic FPGA
+ Manages system power and reset sequencing
+ Manages DUT, board, clock, etc. configuration for dynamic shmoo
+ Collects V-I-T data in background for code/power profiling.
+ Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
+ General fault monitoring and logging
+ Runs from ATX “hot” power rails allowing operation while system is off.
+ Clocks
+ System and DDR clock (SYSCLK, “DDRCLK”)
+ - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
+ - Software selectable in 1MHz increments from 1-200MHz.
+ SERDES clocks
+ - Provides clocks to all SerDes blocks and slots
+ - 100, 125 and 156.25 MHz
+ Power Supplies
+ Dedicated regulators for VDD
+ - Adjustable from (0.7V to 1.3V at 80A
+ - Regulators can be controlled by VID and/or software
+ Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
+ - VTT/MVREF automatically track operating voltage
+ Dedicated regulators/filters for AVDD supplies
+ Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
+ USB
+ Supports two USB 2.0 ports with integrated PHYs
+ - One type A, one type micro-AB with 1.0A power per port.
+ Other IO
+ eSDHC/MMC
+ - SDHC card slot
+ eSPI port
+ - High-speed serial flash
+ Two Serial port
+ Four I2C ports
+
+Memory map
+----------
+The addresses in brackets are physical addresses.
+
+0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
+0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
+0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff 4MB DCSR
+0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
+0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
+0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
+0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
+0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
+0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
+0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
+
+The physical address of the last (boot page translation) varies with the actual DDR size.
#define SH_I2C_ICCR_SCP (1 << 0)
/* ICSR / ICIC */
-#define SH_IC_BUSY (1 << 3)
+#define SH_IC_BUSY (1 << 4)
#define SH_IC_TACK (1 << 2)
#define SH_IC_WAIT (1 << 1)
#define SH_IC_DTE (1 << 0)
-static u8 iccl, icch;
+#ifdef CONFIG_SH_I2C_8BIT
+/* store 8th bit of iccl and icch in ICIC register */
+#define SH_I2C_ICIC_ICCLB8 (1 << 7)
+#define SH_I2C_ICIC_ICCHB8 (1 << 6)
+#endif
+
+static u16 iccl, icch;
#define IRQ_WAIT 1000
}
}
+static int irq_dte_with_tack(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i < IRQ_WAIT ; i++) {
+ if (SH_IC_DTE & readb(&base->icsr))
+ break;
+ if (SH_IC_TACK & readb(&base->icsr))
+ return -1;
+ udelay(10);
+ }
+ return 0;
+}
+
static void irq_busy(struct sh_i2c *base)
{
int i;
}
}
-static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
- writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
- writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr);
-
- writeb(iccl, &base->iccl);
- writeb(icch, &base->icch);
- writeb(0, &base->icic);
+ u8 icic = SH_IC_TACK;
+
+ clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+ setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+
+ writeb(iccl & 0xff, &base->iccl);
+ writeb(icch & 0xff, &base->icch);
+#ifdef CONFIG_SH_I2C_8BIT
+ if (iccl > 0xff)
+ icic |= SH_I2C_ICIC_ICCLB8;
+ if (icch > 0xff)
+ icic |= SH_I2C_ICIC_ICCHB8;
+#endif
+ writeb(icic, &base->icic);
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
irq_dte(base);
+ clrbits_8(&base->icsr, SH_IC_TACK);
writeb(id << 1, &base->icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb(reg, &base->icdr);
if (stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
+ return 0;
}
static void i2c_finish(struct sh_i2c *base)
{
writeb(0, &base->icsr);
- writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
+ clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
}
-static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
{
- i2c_set_addr(base, id, reg, 0);
+ int ret = -1;
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ goto exit0;
udelay(10);
writeb(val, &base->icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
irq_busy(base);
-
+ ret = 0;
+exit0:
i2c_finish(base);
+ return ret;
}
-static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
{
- u8 ret;
-
- i2c_set_addr(base, id, reg, 1);
+ int ret = -1;
+
+#if defined(CONFIG_SH73A0)
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ goto exit0;
+#else
+ if (i2c_set_addr(base, id, reg, 1) != 0)
+ goto exit0;
udelay(100);
+#endif
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
irq_dte(base);
writeb(id << 1 | 0x01, &base->icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
- ret = readb(&base->icdr);
+ ret = readb(&base->icdr) & 0xff;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
readb(&base->icdr); /* Dummy read */
irq_busy(base);
-
+exit0:
i2c_finish(base);
return ret;
case 1:
base = (void *)CONFIG_SH_I2C_BASE1;
break;
+#ifdef CONFIG_SH_I2C_BASE2
+ case 2:
+ base = (void *)CONFIG_SH_I2C_BASE2;
+ break;
+#endif
+#ifdef CONFIG_SH_I2C_BASE3
+ case 3:
+ base = (void *)CONFIG_SH_I2C_BASE3;
+ break;
+#endif
+#ifdef CONFIG_SH_I2C_BASE4
+ case 4:
+ base = (void *)CONFIG_SH_I2C_BASE4;
+ break;
+#endif
default:
return -1;
}
denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
tmp = num * 10 / denom;
if (tmp % 10 >= 5)
- iccl = (u8)((num/denom) + 1);
+ iccl = (u16)((num/denom) + 1);
else
- iccl = (u8)(num/denom);
+ iccl = (u16)(num/denom);
/* Calculate the value for icch. From the data sheet:
icch = (p clock / transfer rate) * (H / (L + H)) */
num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
tmp = num * 10 / denom;
if (tmp % 10 >= 5)
- icch = (u8)((num/denom) + 1);
+ icch = (u16)((num/denom) + 1);
else
- icch = (u8)(num/denom);
+ icch = (u16)(num/denom);
}
/*
*/
int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
{
+ int ret;
int i = 0;
- for (i = 0 ; i < len ; i++)
- buffer[i] = i2c_raw_read(base, chip, addr + i);
-
+ for (i = 0 ; i < len ; i++) {
+ ret = i2c_raw_read(base, chip, addr + i);
+ if (ret < 0)
+ return -1;
+ buffer[i] = ret & 0xff;
+ }
return 0;
}
{
int i = 0;
for (i = 0; i < len ; i++)
- i2c_raw_write(base, chip, addr + i, buffer[i]);
-
+ if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
+ return -1;
return 0;
}
*/
int i2c_probe(u8 chip)
{
- return 0;
+ int ret;
+
+ ret = i2c_set_addr(base, chip, 0, 1);
+ i2c_finish(base);
+ return ret;
}
/* includes */
#include <common.h>
+#include <linux/compiler.h>
#ifdef CONFIG_USE_CPCIDVI
extern u8 gt_cpcidvi_in8(u32 offset);
return in8(I8042_STATUS_REG) != 0xff;
}
+/*
+ * Implement a weak default function for boards that optionally
+ * need to skip the i8042 initialization.
+ */
+int __weak board_i8042_skip(void)
+{
+ /* As default, don't skip */
+ return 0;
+}
+
+void i8042_flush(void)
+{
+ int timeout;
+
+ /*
+ * The delay is to give the keyboard controller some time to fill the
+ * next byte.
+ */
+ while (1) {
+ timeout = 100; /* wait for no longer than 100us */
+ while (timeout > 0 && !(in8(I8042_STATUS_REG) & 0x01)) {
+ udelay(1);
+ timeout--;
+ }
+
+ /* Try to pull next byte if not timeout. */
+ if (in8(I8042_STATUS_REG) & 0x01)
+ in8(I8042_DATA_REG);
+ else
+ break;
+ }
+}
+
+int i8042_disable(void)
+{
+ if (kbd_input_empty() == 0)
+ return -1;
+
+ /* Disable keyboard */
+ out8(I8042_COMMAND_REG, 0xad);
+
+ if (kbd_input_empty() == 0)
+ return -1;
+
+ return 0;
+}
+
+
/*******************************************************************************
*
* i8042_kbd_init - reset keyboard and init state flags
int keymap, try;
char *penv;
- if (!kbd_controller_present())
+ if (!kbd_controller_present() || board_i8042_skip())
return -1;
#ifdef CONFIG_USE_CPCIDVI
static int kbd_input_empty(void)
{
- int kbdTimeout = KBD_TIMEOUT;
+ int kbdTimeout = KBD_TIMEOUT * 1000;
+
+ while ((in8(I8042_STATUS_REG) & I8042_STATUS_IN_DATA) && kbdTimeout--)
+ udelay(1);
+
+ return kbdTimeout != -1;
+}
+
+/******************************************************************************/
+
+static int wait_until_kbd_output_full(void)
+{
+ int kbdTimeout = KBD_TIMEOUT * 1000;
- /* wait for input buf empty */
- while ((in8(I8042_STATUS_REG) & 0x02) && kbdTimeout--)
- udelay(1000);
+ while (((in8(I8042_STATUS_REG) & 0x01) == 0) && kbdTimeout--)
+ udelay(1);
return kbdTimeout != -1;
}
static int kbd_reset(void)
{
+ /* KB Reset */
if (kbd_input_empty() == 0)
return -1;
out8(I8042_DATA_REG, 0xff);
- udelay(250000);
+ if (wait_until_kbd_output_full() == 0)
+ return -1;
+
+ if (in8(I8042_DATA_REG) != 0xfa) /* ACK */
+ return -1;
+
+ if (wait_until_kbd_output_full() == 0)
+ return -1;
+
+ if (in8(I8042_DATA_REG) != 0xaa) /* Test Pass*/
+ return -1;
if (kbd_input_empty() == 0)
return -1;
-#ifdef CONFIG_USE_CPCIDVI
+ /* Set KBC mode */
out8(I8042_COMMAND_REG, 0x60);
-#else
- out8(I8042_DATA_REG, 0x60);
-#endif
if (kbd_input_empty() == 0)
return -1;
out8(I8042_DATA_REG, 0x45);
-
if (kbd_input_empty() == 0)
return -1;
+ /* Enable Keyboard */
out8(I8042_COMMAND_REG, 0xae);
if (kbd_input_empty() == 0)
'\r', 0xff, 0xff
};
+/*
+ * Scan key code to ANSI 3.64 escape sequence table. This table is
+ * incomplete in that it does not include all possible extra keys.
+ */
+static struct {
+ int kbd_scan_code;
+ char *escape;
+} kbd_to_ansi364[] = {
+ { KEY_UP, "\033[A"},
+ { KEY_DOWN, "\033[B"},
+ { KEY_RIGHT, "\033[C"},
+ { KEY_LEFT, "\033[D"},
+};
+
+/* Maximum number of output characters that an ANSI sequence expands to */
+#define ANSI_CHAR_MAX 3
int input_queue_ascii(struct input_config *config, int ch)
{
}
/**
+ * Checks and converts a special key code into ANSI 3.64 escape sequence.
+ *
+ * @param config Input state
+ * @param keycode Key code to examine
+ * @param output_ch Buffer to place output characters into. It should
+ * be at least ANSI_CHAR_MAX bytes long, to allow for
+ * an ANSI sequence.
+ * @param max_chars Maximum number of characters to add to output_ch
+ * @return number of characters output, if the key was converted, otherwise 0.
+ * This may be larger than max_chars, in which case the overflow
+ * characters are not output.
+ */
+static int input_keycode_to_ansi364(struct input_config *config,
+ int keycode, char output_ch[], int max_chars)
+{
+ const char *escape;
+ int ch_count;
+ int i;
+
+ for (i = ch_count = 0; i < ARRAY_SIZE(kbd_to_ansi364); i++) {
+ if (keycode != kbd_to_ansi364[i].kbd_scan_code)
+ continue;
+ for (escape = kbd_to_ansi364[i].escape; *escape; escape++) {
+ if (ch_count < max_chars)
+ output_ch[ch_count] = *escape;
+ ch_count++;
+ }
+ return ch_count;
+ }
+
+ return 0;
+}
+
+/**
+ * Converts and queues a list of key codes in escaped ASCII string form
* Convert a list of key codes into ASCII
*
* You must call input_check_keycodes() before this. It turns the keycode
- * list into a list of ASCII characters which are ready to send to the
- * input layer.
+ * list into a list of ASCII characters and sends them to the input layer.
*
* Characters which were seen last time do not generate fresh ASCII output.
+ * The output (calls to queue_ascii) may be longer than num_keycodes, if the
+ * keycode contains special keys that was encoded to longer escaped sequence.
*
* @param config Input state
* @param keycode List of key codes to examine
* @param num_keycodes Number of key codes
+ * @param output_ch Buffer to place output characters into. It should
+ * be at last ANSI_CHAR_MAX * num_keycodes, to allow for
+ * ANSI sequences.
+ * @param max_chars Maximum number of characters to add to output_ch
* @param same Number of key codes which are the same
+ * @return number of characters written into output_ch, or -1 if we would
+ * exceed max_chars chars.
*/
static int input_keycodes_to_ascii(struct input_config *config,
- int keycode[], int num_keycodes, char output_ch[], int same)
+ int keycode[], int num_keycodes, char output_ch[],
+ int max_chars, int same)
{
struct input_key_xlate *table;
- int ch_count;
+ int ch_count = 0;
int i;
table = &config->table[0];
}
}
- /* now find normal keys */
- for (i = ch_count = 0; i < num_keycodes; i++) {
+ /* Start conversion by looking for the first new keycode (by same). */
+ for (i = same; i < num_keycodes; i++) {
int key = keycode[i];
+ int ch = (key < table->num_entries) ? table->xlate[key] : 0xff;
- if (key < table->num_entries && i >= same) {
- int ch = table->xlate[key];
-
- /* If a normal key with an ASCII value, add it! */
- if (ch != 0xff)
- output_ch[ch_count++] = (uchar)ch;
+ /*
+ * For a normal key (with an ASCII value), add it; otherwise
+ * translate special key to escape sequence if possible.
+ */
+ if (ch != 0xff) {
+ if (ch_count < max_chars)
+ output_ch[ch_count] = (uchar)ch;
+ ch_count++;
+ } else {
+ ch_count += input_keycode_to_ansi364(config, key,
+ output_ch, max_chars);
}
}
+ if (ch_count > max_chars) {
+ debug("%s: Output char buffer overflow size=%d, need=%d\n",
+ __func__, max_chars, ch_count);
+ return -1;
+ }
+
/* ok, so return keys */
return ch_count;
}
int input_send_keycodes(struct input_config *config,
int keycode[], int num_keycodes)
{
- char ch[num_keycodes];
+ char ch[num_keycodes * ANSI_CHAR_MAX];
int count, i, same = 0;
int is_repeat = 0;
unsigned delay_ms;
}
count = input_keycodes_to_ascii(config, keycode, num_keycodes,
- ch, is_repeat ? 0 : same);
+ ch, sizeof(ch), is_repeat ? 0 : same);
for (i = 0; i < count; i++)
input_queue_ascii(config, ch[i]);
delay_ms = is_repeat ?
config->repeat_delay_ms;
config->next_repeat_ms = get_timer(0) + delay_ms;
- return 0;
+
+ return count;
}
int input_add_table(struct input_config *config, int left_keycode,
COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
-COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
COBJS-$(CONFIG_SDHCI) += sdhci.o
COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
+COBJS-$(CONFIG_DWMMC) += dw_mmc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ * Rajeshawari Shinde <rajeshwari.s@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <dwmmc.h>
+#include <asm/arch/clk.h>
+#include <asm-generic/errno.h>
+
+#define PAGE_SIZE 4096
+
+static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
+{
+ unsigned long timeout = 1000;
+ u32 ctrl;
+
+ dwmci_writel(host, DWMCI_CTRL, value);
+
+ while (timeout--) {
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ if (!(ctrl & DWMCI_RESET_ALL))
+ return 1;
+ }
+ return 0;
+}
+
+static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
+ u32 desc0, u32 desc1, u32 desc2)
+{
+ struct dwmci_idmac *desc = idmac;
+
+ desc->flags = desc0;
+ desc->cnt = desc1;
+ desc->addr = desc2;
+ desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
+}
+
+static void dwmci_prepare_data(struct dwmci_host *host,
+ struct mmc_data *data)
+{
+ unsigned long ctrl;
+ unsigned int i = 0, flags, cnt, blk_cnt;
+ ulong data_start, data_end, start_addr;
+ ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data->blocks);
+
+
+ blk_cnt = data->blocks;
+
+ dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+
+ data_start = (ulong)cur_idmac;
+ dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
+
+ if (data->flags == MMC_DATA_READ)
+ start_addr = (unsigned int)data->dest;
+ else
+ start_addr = (unsigned int)data->src;
+
+ do {
+ flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
+ flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
+ if (blk_cnt <= 8) {
+ flags |= DWMCI_IDMAC_LD;
+ cnt = data->blocksize * blk_cnt;
+ } else
+ cnt = data->blocksize * 8;
+
+ dwmci_set_idma_desc(cur_idmac, flags, cnt,
+ start_addr + (i * PAGE_SIZE));
+
+ if(blk_cnt < 8)
+ break;
+ blk_cnt -= 8;
+ cur_idmac++;
+ i++;
+ } while(1);
+
+ data_end = (ulong)cur_idmac;
+ flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+
+ ctrl = dwmci_readl(host, DWMCI_BMOD);
+ ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
+ dwmci_writel(host, DWMCI_BMOD, ctrl);
+
+ dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
+ dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
+}
+
+static int dwmci_set_transfer_mode(struct dwmci_host *host,
+ struct mmc_data *data)
+{
+ unsigned long mode;
+
+ mode = DWMCI_CMD_DATA_EXP;
+ if (data->flags & MMC_DATA_WRITE)
+ mode |= DWMCI_CMD_RW;
+
+ return mode;
+}
+
+static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+ struct mmc_data *data)
+{
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ int flags = 0, i;
+ unsigned int timeout = 100000;
+ u32 retry = 10000;
+ u32 mask, ctrl;
+
+ while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
+ if (timeout == 0) {
+ printf("Timeout on data busy\n");
+ return TIMEOUT;
+ }
+ timeout--;
+ }
+
+ dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
+
+ if (data)
+ dwmci_prepare_data(host, data);
+
+
+ dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
+
+ if (data)
+ flags = dwmci_set_transfer_mode(host, data);
+
+ if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
+ return -1;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ flags |= DWMCI_CMD_ABORT_STOP;
+ else
+ flags |= DWMCI_CMD_PRV_DAT_WAIT;
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ flags |= DWMCI_CMD_RESP_EXP;
+ if (cmd->resp_type & MMC_RSP_136)
+ flags |= DWMCI_CMD_RESP_LENGTH;
+ }
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ flags |= DWMCI_CMD_CHECK_CRC;
+
+ flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
+
+ debug("Sending CMD%d\n",cmd->cmdidx);
+
+ dwmci_writel(host, DWMCI_CMD, flags);
+
+ for (i = 0; i < retry; i++) {
+ mask = dwmci_readl(host, DWMCI_RINTSTS);
+ if (mask & DWMCI_INTMSK_CDONE) {
+ if (!data)
+ dwmci_writel(host, DWMCI_RINTSTS, mask);
+ break;
+ }
+ }
+
+ if (i == retry)
+ return TIMEOUT;
+
+ if (mask & DWMCI_INTMSK_RTO) {
+ debug("Response Timeout..\n");
+ return TIMEOUT;
+ } else if (mask & DWMCI_INTMSK_RE) {
+ debug("Response Error..\n");
+ return -1;
+ }
+
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
+ cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
+ cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
+ cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
+ } else {
+ cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
+ }
+ }
+
+ if (data) {
+ do {
+ mask = dwmci_readl(host, DWMCI_RINTSTS);
+ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
+ debug("DATA ERROR!\n");
+ return -1;
+ }
+ } while (!(mask & DWMCI_INTMSK_DTO));
+
+ dwmci_writel(host, DWMCI_RINTSTS, mask);
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl &= ~(DWMCI_DMA_EN);
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+ }
+
+ udelay(100);
+
+ return 0;
+}
+
+static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
+{
+ u32 div, status;
+ int timeout = 10000;
+ unsigned long sclk;
+
+ if (freq == host->clock)
+ return 0;
+
+ /*
+ * If host->mmc_clk didn't define,
+ * then assume that host->bus_hz is source clock value.
+ * host->bus_hz should be set from user.
+ */
+ if (host->mmc_clk)
+ sclk = host->mmc_clk(host->dev_index);
+ else if (host->bus_hz)
+ sclk = host->bus_hz;
+ else {
+ printf("Didn't get source clock value..\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(sclk, 2 * freq);
+
+ dwmci_writel(host, DWMCI_CLKENA, 0);
+ dwmci_writel(host, DWMCI_CLKSRC, 0);
+
+ dwmci_writel(host, DWMCI_CLKDIV, div);
+ dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
+ DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+
+ do {
+ status = dwmci_readl(host, DWMCI_CMD);
+ if (timeout-- < 0) {
+ printf("TIMEOUT error!!\n");
+ return -ETIMEDOUT;
+ }
+ } while (status & DWMCI_CMD_START);
+
+ dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
+ DWMCI_CLKEN_LOW_PWR);
+
+ dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
+ DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
+
+ timeout = 10000;
+ do {
+ status = dwmci_readl(host, DWMCI_CMD);
+ if (timeout-- < 0) {
+ printf("TIMEOUT error!!\n");
+ return -ETIMEDOUT;
+ }
+ } while (status & DWMCI_CMD_START);
+
+ host->clock = freq;
+
+ return 0;
+}
+
+static void dwmci_set_ios(struct mmc *mmc)
+{
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ u32 ctype;
+
+ debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
+
+ dwmci_setup_bus(host, mmc->clock);
+ switch (mmc->bus_width) {
+ case 8:
+ ctype = DWMCI_CTYPE_8BIT;
+ break;
+ case 4:
+ ctype = DWMCI_CTYPE_4BIT;
+ break;
+ default:
+ ctype = DWMCI_CTYPE_1BIT;
+ break;
+ }
+
+ dwmci_writel(host, DWMCI_CTYPE, ctype);
+
+ if (host->clksel)
+ host->clksel(host);
+}
+
+static int dwmci_init(struct mmc *mmc)
+{
+ struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
+ u32 fifo_size, fifoth_val;
+
+ dwmci_writel(host, DWMCI_PWREN, 1);
+
+ if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
+ debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
+ return -1;
+ }
+
+ dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
+ dwmci_writel(host, DWMCI_INTMASK, 0);
+
+ dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
+
+ dwmci_writel(host, DWMCI_IDINTEN, 0);
+ dwmci_writel(host, DWMCI_BMOD, 1);
+
+ fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+ if (host->fifoth_val)
+ fifoth_val = host->fifoth_val;
+ else
+ fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size/2 -1) |
+ TX_WMARK(fifo_size/2);
+ dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
+
+ dwmci_writel(host, DWMCI_CLKENA, 0);
+ dwmci_writel(host, DWMCI_CLKSRC, 0);
+
+ return 0;
+}
+
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+{
+ struct mmc *mmc;
+ int err = 0;
+
+ mmc = malloc(sizeof(struct mmc));
+ if (!mmc) {
+ printf("mmc malloc fail!\n");
+ return -1;
+ }
+
+ mmc->priv = host;
+ host->mmc = mmc;
+
+ sprintf(mmc->name, "%s", host->name);
+ mmc->send_cmd = dwmci_send_cmd;
+ mmc->set_ios = dwmci_set_ios;
+ mmc->init = dwmci_init;
+ mmc->f_min = min_clk;
+ mmc->f_max = max_clk;
+
+ mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+
+ mmc->host_caps = host->caps;
+
+ if (host->buswidth == 8) {
+ mmc->host_caps |= MMC_MODE_8BIT;
+ mmc->host_caps &= ~MMC_MODE_4BIT;
+ } else {
+ mmc->host_caps |= MMC_MODE_4BIT;
+ mmc->host_caps &= ~MMC_MODE_8BIT;
+ }
+ mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+
+ err = mmc_register(mmc);
+
+ return err;
+}
int board_mmc_getcd(struct mmc *mmc)__attribute__((weak,
alias("__board_mmc_getcd")));
-#ifdef CONFIG_MMC_BOUNCE_BUFFER
-static int mmc_bounce_need_bounce(struct mmc_data *orig)
-{
- ulong addr, len;
-
- if (orig->flags & MMC_DATA_READ)
- addr = (ulong)orig->dest;
- else
- addr = (ulong)orig->src;
-
- if (addr % ARCH_DMA_MINALIGN) {
- debug("MMC: Unaligned data destination address %08lx!\n", addr);
- return 1;
- }
-
- len = (ulong)(orig->blocksize * orig->blocks);
- if (len % ARCH_DMA_MINALIGN) {
- debug("MMC: Unaligned data destination length %08lx!\n", len);
- return 1;
- }
-
- return 0;
-}
-
-static int mmc_bounce_buffer_start(struct mmc_data *backup,
- struct mmc_data *orig)
-{
- ulong origlen, len;
- void *buffer;
-
- if (!orig)
- return 0;
-
- if (!mmc_bounce_need_bounce(orig))
- return 0;
-
- memcpy(backup, orig, sizeof(struct mmc_data));
-
- origlen = orig->blocksize * orig->blocks;
- len = roundup(origlen, ARCH_DMA_MINALIGN);
- buffer = memalign(ARCH_DMA_MINALIGN, len);
- if (!buffer) {
- puts("MMC: Error allocating MMC bounce buffer!\n");
- return 1;
- }
-
- if (orig->flags & MMC_DATA_READ) {
- orig->dest = buffer;
- } else {
- memcpy(buffer, orig->src, origlen);
- orig->src = buffer;
- }
-
- return 0;
-}
-
-static void mmc_bounce_buffer_stop(struct mmc_data *backup,
- struct mmc_data *orig)
-{
- ulong len;
-
- if (!orig)
- return;
-
- if (!mmc_bounce_need_bounce(backup))
- return;
-
- if (backup->flags & MMC_DATA_READ) {
- len = backup->blocksize * backup->blocks;
- memcpy(backup->dest, orig->dest, len);
- free(orig->dest);
- orig->dest = backup->dest;
- } else {
- free((void *)orig->src);
- orig->src = backup->src;
- }
-
- return;
-
-}
-#else
-static inline int mmc_bounce_buffer_start(struct mmc_data *backup,
- struct mmc_data *orig) { return 0; }
-static inline void mmc_bounce_buffer_stop(struct mmc_data *backup,
- struct mmc_data *orig) { }
-#endif
-
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct mmc_data backup;
memset(&backup, 0, sizeof(backup));
- ret = mmc_bounce_buffer_start(&backup, data);
- if (ret)
- return ret;
-
#ifdef CONFIG_MMC_TRACE
int i;
u8 *ptr;
#else
ret = mmc->send_cmd(mmc, cmd, data);
#endif
- mmc_bounce_buffer_stop(&backup, data);
return ret;
}
u8 r1;
int i;
int ret = 0;
- debug("%s:cmd%d %x %x %x\n", __func__,
- cmd->cmdidx, cmd->resp_type, cmd->cmdarg, cmd->flags);
+ debug("%s:cmd%d %x %x\n", __func__,
+ cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
spi_claim_bus(spi);
spi_cs_activate(spi);
r1 = mmc_spi_sendcmd(mmc, cmd->cmdidx, cmd->cmdarg);
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>
+#include <bouncebuf.h>
struct mxsmmc_priv {
int id;
static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
{
uint32_t data_count = data->blocksize * data->blocks;
- uint32_t cache_data_count;
+ uint32_t cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
int dmach;
struct mxs_dma_desc *desc = priv->desc;
+ void *addr, *backup;
+ uint8_t flags;
memset(desc, 0, sizeof(struct mxs_dma_desc));
desc->address = (dma_addr_t)desc;
- if (data_count % ARCH_DMA_MINALIGN)
- cache_data_count = roundup(data_count, ARCH_DMA_MINALIGN);
- else
- cache_data_count = data_count;
-
if (data->flags & MMC_DATA_READ) {
priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
- priv->desc->cmd.address = (dma_addr_t)data->dest;
+ addr = data->dest;
+ flags = GEN_BB_WRITE;
} else {
priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
- priv->desc->cmd.address = (dma_addr_t)data->src;
+ addr = (void *)data->src;
+ flags = GEN_BB_READ;
+ }
+
+ bounce_buffer_start(&addr, data_count, &backup, flags);
+
+ priv->desc->cmd.address = (dma_addr_t)addr;
+ if (data->flags & MMC_DATA_WRITE) {
/* Flush data to DRAM so DMA can pick them up */
- flush_dcache_range((uint32_t)priv->desc->cmd.address,
- (uint32_t)(priv->desc->cmd.address + cache_data_count));
+ flush_dcache_range((uint32_t)addr,
+ (uint32_t)(addr) + cache_data_count);
}
/* Invalidate the area, so no writeback into the RAM races with DMA */
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
mxs_dma_desc_append(dmach, priv->desc);
- if (mxs_dma_go(dmach))
+ if (mxs_dma_go(dmach)) {
+ bounce_buffer_stop(&addr, data_count, &backup, flags);
return COMM_ERR;
+ }
/* The data arrived into DRAM, invalidate cache over them */
if (data->flags & MMC_DATA_READ) {
- invalidate_dcache_range((uint32_t)priv->desc->cmd.address,
- (uint32_t)(priv->desc->cmd.address + cache_data_count));
+ invalidate_dcache_range((uint32_t)addr,
+ (uint32_t)(addr) + cache_data_count);
}
+ bounce_buffer_stop(&addr, data_count, &backup, flags);
+
return 0;
}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <mmc.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <part.h>
-#include <asm/io.h>
-
-#include "pxa_mmc.h"
-
-extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no);
-
-static block_dev_desc_t mmc_dev;
-
-block_dev_desc_t *mmc_get_dev(int dev)
-{
- return ((block_dev_desc_t *) & mmc_dev);
-}
-
-/*
- * FIXME needs to read cid and csd info to determine block size
- * and other parameters
- */
-static uchar mmc_buf[MMC_BLOCK_SIZE];
-static uchar spec_ver;
-static int mmc_ready = 0;
-static int wide = 0;
-
-static uint32_t *
-/****************************************************/
-mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
-/****************************************************/
-{
- static uint32_t resp[4], a, b, c;
- uint32_t status;
- int i;
-
- debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
- cmdat | wide);
- writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
- writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK);
- while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF))
- ;
- writel(cmd, MMC_CMD);
- writel(argh, MMC_ARGH);
- writel(argl, MMC_ARGL);
- writel(cmdat | wide, MMC_CMDAT);
- writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK);
- writel(MMC_STRPCL_START_CLK, MMC_STRPCL);
- while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES))
- ;
-
- status = readl(MMC_STAT);
- debug("MMC status 0x%08x\n", status);
- if (status & MMC_STAT_TIME_OUT_RESPONSE) {
- return 0;
- }
-
- /* Linux says:
- * Did I mention this is Sick. We always need to
- * discard the upper 8 bits of the first 16-bit word.
- */
- a = (readl(MMC_RES) & 0xffff);
- for (i = 0; i < 4; i++) {
- b = (readl(MMC_RES) & 0xffff);
- c = (readl(MMC_RES) & 0xffff);
- resp[i] = (a << 24) | (b << 8) | (c >> 8);
- a = c;
- debug("MMC resp[%d] = %#08x\n", i, resp[i]);
- }
-
- return resp;
-}
-
-int
-/****************************************************/
-mmc_block_read(uchar * dst, uint32_t src, int len)
-/****************************************************/
-{
- ushort argh, argl;
- ulong status;
-
- if (len == 0) {
- return 0;
- }
-
- debug("mmc_block_rd dst %p src %08x len %d\n", dst, src, len);
-
- argh = len >> 16;
- argl = len & 0xffff;
-
- /* set block len */
- mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
-
- /* send read command */
- argh = src >> 16;
- argl = src & 0xffff;
- writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
- writel(0xffff, MMC_RDTO);
- writel(1, MMC_NOB);
- writel(len, MMC_BLKLEN);
- mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl,
- MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK |
- MMC_CMDAT_DATA_EN);
-
- writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
- while (len) {
- if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
-#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- int i;
- for (i = min(len, 32); i; i--) {
- *dst++ = readb(MMC_RXFIFO);
- len--;
- }
-#else
- *dst++ = readb(MMC_RXFIFO);
- len--;
-#endif
- }
- status = readl(MMC_STAT);
- if (status & MMC_STAT_ERRORS) {
- printf("MMC_STAT error %lx\n", status);
- return -1;
- }
- }
- writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
- while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
- ;
- status = readl(MMC_STAT);
- if (status & MMC_STAT_ERRORS) {
- printf("MMC_STAT error %lx\n", status);
- return -1;
- }
- return 0;
-}
-
-int
-/****************************************************/
-mmc_block_write(ulong dst, uchar * src, int len)
-/****************************************************/
-{
- ushort argh, argl;
- ulong status;
-
- if (len == 0) {
- return 0;
- }
-
- debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong) src, len);
-
- argh = len >> 16;
- argl = len & 0xffff;
-
- /* set block len */
- mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
-
- /* send write command */
- argh = dst >> 16;
- argl = dst & 0xffff;
- writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
- writel(1, MMC_NOB);
- writel(len, MMC_BLKLEN);
- mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl,
- MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK |
- MMC_CMDAT_DATA_EN);
-
- writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK);
- while (len) {
- if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) {
- int i, bytes = min(32, len);
-
- for (i = 0; i < bytes; i++) {
- writel(*src++, MMC_TXFIFO);
- }
- if (bytes < 32) {
- writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF);
- }
- len -= bytes;
- }
- status = readl(MMC_STAT);
- if (status & MMC_STAT_ERRORS) {
- printf("MMC_STAT error %lx\n", status);
- return -1;
- }
- }
- writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
- while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
- ;
- writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK);
- while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE))
- ;
- status = readl(MMC_STAT);
- if (status & MMC_STAT_ERRORS) {
- printf("MMC_STAT error %lx\n", status);
- return -1;
- }
- return 0;
-}
-
-int
-/****************************************************/
-pxa_mmc_read(long src, uchar * dst, int size)
-/****************************************************/
-{
- ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
- ulong mmc_block_size, mmc_block_address;
-
- if (size == 0) {
- return 0;
- }
-
- if (!mmc_ready) {
- printf("Please initial the MMC first\n");
- return -1;
- }
-
- mmc_block_size = MMC_BLOCK_SIZE;
- mmc_block_address = ~(mmc_block_size - 1);
-
- src -= CONFIG_SYS_MMC_BASE;
- end = src + size;
- part_start = ~mmc_block_address & src;
- part_end = ~mmc_block_address & end;
- aligned_start = mmc_block_address & src;
- aligned_end = mmc_block_address & end;
-
- /* all block aligned accesses */
- debug
- ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if (part_start) {
- part_len = mmc_block_size - part_start;
- debug
- ("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) <
- 0) {
- return -1;
- }
- memcpy(dst, mmc_buf + part_start, part_len);
- dst += part_len;
- src += part_len;
- }
- debug
- ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
- aligned_end);
- for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
- debug
- ("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if ((mmc_block_read((uchar *) (dst), src, mmc_block_size)) < 0) {
- return -1;
- }
- }
- debug
- ("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if (part_end && src < end) {
- debug
- ("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, (ulong) dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
- return -1;
- }
- memcpy(dst, mmc_buf, part_end);
- }
- return 0;
-}
-
-int
-/****************************************************/
-pxa_mmc_write(uchar * src, uint32_t dst, int size)
-/****************************************************/
-{
- ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
- ulong mmc_block_size, mmc_block_address;
-
- if (size == 0) {
- return 0;
- }
-
- if (!mmc_ready) {
- printf("Please initial the MMC first\n");
- return -1;
- }
-
- mmc_block_size = MMC_BLOCK_SIZE;
- mmc_block_address = ~(mmc_block_size - 1);
-
- dst -= CONFIG_SYS_MMC_BASE;
- end = dst + size;
- part_start = ~mmc_block_address & dst;
- part_end = ~mmc_block_address & end;
- aligned_start = mmc_block_address & dst;
- aligned_end = mmc_block_address & end;
-
- /* all block aligned accesses */
- debug
- ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if (part_start) {
- part_len = mmc_block_size - part_start;
- debug
- ("ps src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) <
- 0) {
- return -1;
- }
- memcpy(mmc_buf + part_start, src, part_len);
- if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) <
- 0) {
- return -1;
- }
- dst += part_len;
- src += part_len;
- }
- debug
- ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, dst, end, part_start, part_end, aligned_start,
- aligned_end);
- for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
- debug
- ("al src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if ((mmc_block_write(dst, (uchar *) src, mmc_block_size)) < 0) {
- return -1;
- }
- }
- debug
- ("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if (part_end && dst < end) {
- debug
- ("pe src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
- src, dst, end, part_start, part_end, aligned_start,
- aligned_end);
- if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
- return -1;
- }
- memcpy(mmc_buf, src, part_end);
- if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
- return -1;
- }
- }
- return 0;
-}
-
-static ulong
-/****************************************************/
-mmc_bread(int dev_num, ulong blknr, lbaint_t blkcnt, void *dst)
-/****************************************************/
-{
- int mmc_block_size = MMC_BLOCK_SIZE;
- ulong src = blknr * mmc_block_size + CONFIG_SYS_MMC_BASE;
-
- pxa_mmc_read(src, (uchar *) dst, blkcnt * mmc_block_size);
- return blkcnt;
-}
-
-#ifdef __GNUC__
-#define likely(x) __builtin_expect(!!(x), 1)
-#define unlikely(x) __builtin_expect(!!(x), 0)
-#else
-#define likely(x) (x)
-#define unlikely(x) (x)
-#endif
-
-#define UNSTUFF_BITS(resp,start,size) \
- ({ \
- const int __size = size; \
- const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \
- const int32_t __off = 3 - ((start) / 32); \
- const int32_t __shft = (start) & 31; \
- uint32_t __res; \
- \
- __res = resp[__off] >> __shft; \
- if (__size + __shft > 32) \
- __res |= resp[__off-1] << ((32 - __shft) % 32); \
- __res & __mask; \
- })
-
-/*
- * Given the decoded CSD structure, decode the raw CID to our CID structure.
- */
-static void mmc_decode_cid(uint32_t * resp)
-{
- if (IF_TYPE_SD == mmc_dev.if_type) {
- /*
- * SD doesn't currently have a version field so we will
- * have to assume we can parse this.
- */
- sprintf((char *)mmc_dev.vendor,
- "Man %02x OEM %c%c \"%c%c%c%c%c\" Date %02u/%04u",
- UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, 112, 8),
- UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, 96, 8),
- UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, 80, 8),
- UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, 64, 8),
- UNSTUFF_BITS(resp, 8, 4), UNSTUFF_BITS(resp, 12,
- 8) + 2000);
- sprintf((char *)mmc_dev.revision, "%d.%d",
- UNSTUFF_BITS(resp, 60, 4), UNSTUFF_BITS(resp, 56, 4));
- sprintf((char *)mmc_dev.product, "%u",
- UNSTUFF_BITS(resp, 24, 32));
- } else {
- /*
- * The selection of the format here is based upon published
- * specs from sandisk and from what people have reported.
- */
- switch (spec_ver) {
- case 0: /* MMC v1.0 - v1.2 */
- case 1: /* MMC v1.4 */
- sprintf((char *)mmc_dev.vendor,
- "Man %02x%02x%02x \"%c%c%c%c%c%c%c\" Date %02u/%04u",
- UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp,
- 112,
- 8),
- UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp,
- 96, 8),
- UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp,
- 80, 8),
- UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp,
- 64, 8),
- UNSTUFF_BITS(resp, 56, 8), UNSTUFF_BITS(resp,
- 48, 8),
- UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8,
- 4) +
- 1997);
- sprintf((char *)mmc_dev.revision, "%d.%d",
- UNSTUFF_BITS(resp, 44, 4), UNSTUFF_BITS(resp,
- 40, 4));
- sprintf((char *)mmc_dev.product, "%u",
- UNSTUFF_BITS(resp, 16, 24));
- break;
-
- case 2: /* MMC v2.0 - v2.2 */
- case 3: /* MMC v3.1 - v3.3 */
- case 4: /* MMC v4 */
- sprintf((char *)mmc_dev.vendor,
- "Man %02x OEM %04x \"%c%c%c%c%c%c\" Date %02u/%04u",
- UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp,
- 104,
- 16),
- UNSTUFF_BITS(resp, 96, 8), UNSTUFF_BITS(resp,
- 88, 8),
- UNSTUFF_BITS(resp, 80, 8), UNSTUFF_BITS(resp,
- 72, 8),
- UNSTUFF_BITS(resp, 64, 8), UNSTUFF_BITS(resp,
- 56, 8),
- UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8,
- 4) +
- 1997);
- sprintf((char *)mmc_dev.product, "%u",
- UNSTUFF_BITS(resp, 16, 32));
- sprintf((char *)mmc_dev.revision, "N/A");
- break;
-
- default:
- printf("MMC card has unknown MMCA version %d\n",
- spec_ver);
- break;
- }
- }
- printf("%s card.\nVendor: %s\nProduct: %s\nRevision: %s\n",
- (IF_TYPE_SD == mmc_dev.if_type) ? "SD" : "MMC", mmc_dev.vendor,
- mmc_dev.product, mmc_dev.revision);
-}
-
-/*
- * Given a 128-bit response, decode to our card CSD structure.
- */
-static void mmc_decode_csd(uint32_t * resp)
-{
- unsigned int mult, csd_struct;
-
- if (IF_TYPE_SD == mmc_dev.if_type) {
- csd_struct = UNSTUFF_BITS(resp, 126, 2);
- if (csd_struct != 0) {
- printf("SD: unrecognised CSD structure version %d\n",
- csd_struct);
- return;
- }
- } else {
- /*
- * We only understand CSD structure v1.1 and v1.2.
- * v1.2 has extra information in bits 15, 11 and 10.
- */
- csd_struct = UNSTUFF_BITS(resp, 126, 2);
- if (csd_struct != 1 && csd_struct != 2) {
- printf("MMC: unrecognised CSD structure version %d\n",
- csd_struct);
- return;
- }
-
- spec_ver = UNSTUFF_BITS(resp, 122, 4);
- mmc_dev.if_type = IF_TYPE_MMC;
- }
-
- mult = 1 << (UNSTUFF_BITS(resp, 47, 3) + 2);
- mmc_dev.lba = (1 + UNSTUFF_BITS(resp, 62, 12)) * mult;
- mmc_dev.blksz = 1 << UNSTUFF_BITS(resp, 80, 4);
-
- /* FIXME: The following just makes assumes that's the partition type -- should really read it */
- mmc_dev.part_type = PART_TYPE_DOS;
- mmc_dev.dev = 0;
- mmc_dev.lun = 0;
- mmc_dev.type = DEV_TYPE_HARDDISK;
- mmc_dev.removable = 0;
- mmc_dev.block_read = mmc_bread;
-
- printf("Detected: %lu blocks of %lu bytes (%luMB) ",
- mmc_dev.lba,
- mmc_dev.blksz,
- mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
-}
-
-int
-/****************************************************/
-mmc_legacy_init(int verbose)
-/****************************************************/
-{
- int retries, rc = -ENODEV;
- uint32_t cid_resp[4];
- uint32_t *resp;
- uint16_t rca = 0;
-
- /* Reset device interface type */
- mmc_dev.if_type = IF_TYPE_UNKNOWN;
-
-#ifdef CONFIG_CPU_MONAHANS /* pxa3xx */
- writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA);
-#else /* pxa2xx */
- writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */
-#endif
- writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT);
- writel(MMC_RES_TO_MAX, MMC_RESTO);
- writel(MMC_SPI_DISABLE, MMC_SPI);
-
- /* reset */
- mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0);
- udelay(200000);
- retries = 3;
- while (retries--) {
- resp = mmc_cmd(MMC_CMD_APP_CMD, 0, 0, MMC_CMDAT_R1);
- if (!(resp[0] & 0x00000020)) { /* Card does not support APP_CMD */
- debug("Card does not support APP_CMD\n");
- break;
- }
-
- /* Select 3.2-3.3V and 3.3-3.4V */
- resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0030, 0x0000,
- MMC_CMDAT_R3 | (retries < 2 ? 0
- : MMC_CMDAT_INIT));
- if (resp[0] & 0x80000000) {
- mmc_dev.if_type = IF_TYPE_SD;
- debug("Detected SD card\n");
- break;
- }
- udelay(200000);
- }
-
- if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) {
- debug("Failed to detect SD Card, trying MMC\n");
- resp =
- mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, MMC_CMDAT_R3);
-
- retries = 10;
- while (retries-- && resp && !(resp[0] & 0x80000000)) {
- udelay(200000);
- resp =
- mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000,
- MMC_CMDAT_R3);
- }
- }
-
- /* try to get card id */
- resp =
- mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, 0, MMC_CMDAT_R2 | MMC_CMDAT_BUSY);
- if (resp) {
- memcpy(cid_resp, resp, sizeof(cid_resp));
-
- /* MMC exists, get CSD too */
- resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1);
- if (IF_TYPE_SD == mmc_dev.if_type)
- rca = ((resp[0] & 0xffff0000) >> 16);
- resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2);
- if (resp) {
- mmc_decode_csd(resp);
- rc = 0;
- mmc_ready = 1;
- }
-
- mmc_decode_cid(cid_resp);
- }
-
- writel(0, MMC_CLKRT); /* 20 MHz */
- resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
-
-#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
- if (IF_TYPE_SD == mmc_dev.if_type) {
- resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1);
- resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1);
- wide = MMC_CMDAT_SD_4DAT;
- }
-#endif
-
- fat_register_device(&mmc_dev, 1); /* partitions start counting with 1 */
-
- return rc;
-}
host->ioaddr = (void *)regbase;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
- SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR;
+ SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
+ SDHCI_QUIRK_WAIT_SEND_CMD;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
+#ifdef CONFIG_MMC_SDMA
+ unsigned char ctrl;
+ ctrl = sdhci_readl(host, SDHCI_HOST_CONTROL);
+ ctrl &= ~SDHCI_CTRL_DMA_MASK;
+ ctrl |= SDHCI_CTRL_SDMA;
+ sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL);
+#endif
- timeout = 10000;
+ timeout = 1000000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
do {
if (!ret && data)
ret = sdhci_transfer_data(host, data, start_addr);
+ if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
+ udelay(1000);
+
stat = sdhci_readl(host, SDHCI_INT_STATUS);
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
if (!ret) {
COBJS-y += tgec.o
COBJS-y += tgec_phy.o
+# Soc have FMAN v3 with mEMAC
+COBJS-$(CONFIG_SYS_FMAN_V3) += memac_phy.o
+COBJS-$(CONFIG_SYS_FMAN_V3) += memac.o
+
# SoC specific SERDES support
COBJS-$(CONFIG_P1017) += p1023.o
COBJS-$(CONFIG_P1023) += p1023.o
COBJS-$(CONFIG_PPC_P3041) += p5020.o
COBJS-$(CONFIG_PPC_P4080) += p4080.o
COBJS-$(CONFIG_PPC_P5020) += p5020.o
+COBJS-$(CONFIG_PPC_T4240) += t4240.o
+COBJS-$(CONFIG_PPC_B4860) += b4860.o
endif
COBJS := $(COBJS-y)
/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_tgec.h>
+#include <asm/fsl_memac.h>
#include "fm.h"
/* Configure the TBI for SGMII operation */
void dtsec_configure_serdes(struct fm_eth *priv)
{
+#ifdef CONFIG_SYS_FMAN_V3
+ u32 value;
+ struct mii_dev bus;
+ bus.priv = priv->mac->phyregs;
+
+ /* SGMII IF mode + AN enable */
+ value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+
+ /* Dev ability according to SGMII specification */
+ value = PHY_SGMII_DEV_ABILITY_SGMII;
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+
+ /* Adjust link timer for SGMII -
+ 1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+
+ /* Restart AN */
+ value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
+ memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+#else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
TBIANA_SGMII_ACK);
tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
TBI_CR, TBICR_SETTINGS);
+#endif
}
static void dtsec_init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
- struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
+#ifndef CONFIG_SYS_FMAN_V3
+ struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
+#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
dtsec_configure_serdes(fm_eth);
num = fm_eth->num;
+#ifdef CONFIG_SYS_FMAN_V3
+ base = ®->memac[num].fm_memac;
+ phyregs = ®->memac[num].fm_memac_mdio;
+#else
/* Get the mac registers base address */
if (fm_eth->type == FM_ETH_1G_E) {
base = ®->mac_1g[num].fm_dtesc;
base = ®->mac_10g[num].fm_10gec;
phyregs = ®->mac_10g[num].fm_10gec_mdio;
}
+#endif
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
/* save the mac to fm_eth struct */
fm_eth->mac = mac;
+#ifdef CONFIG_SYS_FMAN_V3
+ init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
+#else
if (fm_eth->type == FM_ETH_1G_E)
init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
else
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
+#endif
return 1;
}
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(1, 5),
#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 6)
+ FM_DTSEC_INFO_INITIALIZER(1, 6),
+#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 7)
+ FM_DTSEC_INFO_INITIALIZER(1, 9),
+#endif
+#if (CONFIG_SYS_NUM_FM1_DTSEC >= 8)
+ FM_DTSEC_INFO_INITIALIZER(1, 10),
+#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(2, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(2, 5),
#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 6)
+ FM_DTSEC_INFO_INITIALIZER(2, 6),
+#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 7)
+ FM_DTSEC_INFO_INITIALIZER(2, 9),
+#endif
+#if (CONFIG_SYS_NUM_FM2_DTSEC >= 8)
+ FM_DTSEC_INFO_INITIALIZER(2, 10),
+#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* MAXFRM - maximum frame length */
+#define MAXFRM_MASK 0x0000ffff
+
+#include <common.h>
+#include <phy.h>
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/fsl_enet.h>
+#include <asm/fsl_memac.h>
+
+#include "fm.h"
+
+static void memac_init_mac(struct fsl_enet_mac *mac)
+{
+ struct memac *regs = mac->base;
+
+ /* mask all interrupt */
+ out_be32(®s->imask, IMASK_MASK_ALL);
+
+ /* clear all events */
+ out_be32(®s->ievent, IEVENT_CLEAR_ALL);
+
+ /* set the max receive length */
+ out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK);
+
+ /* multicast frame reception for the hash entry disable */
+ out_be32(®s->hashtable_ctrl, 0);
+}
+
+static void memac_enable_mac(struct fsl_enet_mac *mac)
+{
+ struct memac *regs = mac->base;
+
+ setbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN);
+}
+
+static void memac_disable_mac(struct fsl_enet_mac *mac)
+{
+ struct memac *regs = mac->base;
+
+ clrbits_be32(®s->command_config, MEMAC_CMD_CFG_RXTX_EN);
+}
+
+static void memac_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
+{
+ struct memac *regs = mac->base;
+ u32 mac_addr0, mac_addr1;
+
+ /*
+ * if a station address of 0x12345678ABCD, perform a write to
+ * MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
+ */
+ mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
+ (mac_addr[1] << 8) | (mac_addr[0]);
+ out_be32(®s->mac_addr_0, mac_addr0);
+
+ mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
+ out_be32(®s->mac_addr_1, mac_addr1);
+}
+
+static void memac_set_interface_mode(struct fsl_enet_mac *mac,
+ phy_interface_t type, int speed)
+{
+ /* Roy need more work here */
+
+ struct memac *regs = mac->base;
+ u32 if_mode, if_status;
+
+ /* clear all bits relative with interface mode */
+ if_mode = in_be32(®s->if_mode);
+ if_status = in_be32(®s->if_status);
+
+ /* set interface mode */
+ switch (type) {
+ case PHY_INTERFACE_MODE_GMII:
+ if_mode &= ~IF_MODE_MASK;
+ if_mode |= IF_MODE_GMII;
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if_mode |= (IF_MODE_GMII | IF_MODE_RG);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ if_mode |= (IF_MODE_GMII | IF_MODE_RM);
+ break;
+ case PHY_INTERFACE_MODE_SGMII:
+ if_mode &= ~IF_MODE_MASK;
+ if_mode |= (IF_MODE_GMII);
+ break;
+ default:
+ break;
+ }
+ /* Enable automatic speed selection */
+ if_mode |= IF_MODE_EN_AUTO;
+
+ debug(" %s, if_mode = %x\n", __func__, if_mode);
+ debug(" %s, if_status = %x\n", __func__, if_status);
+ out_be32(®s->if_mode, if_mode);
+ return;
+}
+
+void init_memac(struct fsl_enet_mac *mac, void *base,
+ void *phyregs, int max_rx_len)
+{
+ mac->base = base;
+ mac->phyregs = phyregs;
+ mac->max_rx_len = max_rx_len;
+ mac->init_mac = memac_init_mac;
+ mac->enable_mac = memac_enable_mac;
+ mac->disable_mac = memac_disable_mac;
+ mac->set_mac_addr = memac_set_mac_addr;
+ mac->set_if_mode = memac_set_interface_mode;
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Andy Fleming <afleming@freescale.com>
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ * Some part is taken from tsec.c
+ */
+#include <common.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <asm/fsl_memac.h>
+#include <fm_eth.h>
+
+/*
+ * Write value to the PHY for this device to the register at regnum, waiting
+ * until the write is done before it returns. All PHY configuration has to be
+ * done through the TSEC1 MIIM regs
+ */
+int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum, u16 value)
+{
+ u32 mdio_ctl;
+ struct memac_mdio_controller *regs = bus->priv;
+ u32 c45 = 1; /* Default to 10G interface */
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ c45 = 0; /* clause 22 */
+ dev_addr = regnum & 0x1f;
+ clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
+ } else {
+ setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
+ setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
+ }
+
+ /* Wait till the bus is free */
+ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Set the port and dev addr */
+ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
+ out_be32(®s->mdio_ctl, mdio_ctl);
+
+ /* Set the register address */
+ if (c45)
+ out_be32(®s->mdio_addr, regnum & 0xffff);
+
+ /* Wait till the bus is free */
+ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Write the value to the register */
+ out_be32(®s->mdio_data, MDIO_DATA(value));
+
+ /* Wait till the MDIO write is complete */
+ while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
+ ;
+
+ return 0;
+}
+
+/*
+ * Reads from register regnum in the PHY for device dev, returning the value.
+ * Clears miimcom first. All PHY configuration has to be done through the
+ * TSEC1 MIIM regs
+ */
+int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum)
+{
+ u32 mdio_ctl;
+ struct memac_mdio_controller *regs = bus->priv;
+ u32 c45 = 1;
+
+ if (dev_addr == MDIO_DEVAD_NONE) {
+ c45 = 0; /* clause 22 */
+ dev_addr = regnum & 0x1f;
+ clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
+ } else {
+ setbits_be32(®s->mdio_stat, MDIO_STAT_ENC);
+ setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK);
+ }
+
+ /* Wait till the bus is free */
+ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Set the Port and Device Addrs */
+ mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
+ out_be32(®s->mdio_ctl, mdio_ctl);
+
+ /* Set the register address */
+ if (c45)
+ out_be32(®s->mdio_addr, regnum & 0xffff);
+
+ /* Wait till the bus is free */
+ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
+ ;
+
+ /* Initiate the read */
+ mdio_ctl |= MDIO_CTL_READ;
+ out_be32(®s->mdio_ctl, mdio_ctl);
+
+ /* Wait till the MDIO write is complete */
+ while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
+ ;
+
+ /* Return all Fs if nothing was there */
+ if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
+ return 0xffff;
+
+ return in_be32(®s->mdio_data) & 0xffff;
+}
+
+int memac_mdio_reset(struct mii_dev *bus)
+{
+ return 0;
+}
+
+int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate FM TGEC MDIO bus\n");
+ return -1;
+ }
+
+ bus->read = memac_mdio_read;
+ bus->write = memac_mdio_write;
+ bus->reset = memac_mdio_reset;
+ sprintf(bus->name, info->name);
+
+ bus->priv = info->regs;
+
+ return mdio_register(bus);
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <phy.h>
+#include <fm_eth.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+u32 port_to_devdisr[] = {
+ [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
+ [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
+ [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
+ [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
+ [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
+ [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
+ [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
+ [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
+ [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
+ [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
+ [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
+ [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
+ [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
+ [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
+ [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
+ [FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
+ [FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
+ [FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
+ [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
+ [FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
+};
+
+static int is_device_disabled(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr2 = in_be32(&gur->devdisr2);
+
+ return port_to_devdisr[port] & devdisr2;
+}
+
+void fman_disable_port(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
+}
+
+phy_interface_t fman_port_enet_if(enum fm_port port)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+
+ if (is_device_disabled(port))
+ return PHY_INTERFACE_MODE_NONE;
+
+ if ((port == FM1_10GEC1 || port == FM1_10GEC2)
+ && (is_serdes_configured(XAUI_FM1)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+ if ((port == FM2_10GEC1 || port == FM2_10GEC2)
+ && (is_serdes_configured(XAUI_FM2)))
+ return PHY_INTERFACE_MODE_XGMII;
+
+#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
+#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
+ /* handle RGMII first */
+ if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
+ FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+
+ if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
+ return PHY_INTERFACE_MODE_RGMII;
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC3:
+ case FM1_DTSEC4:
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ case FM2_DTSEC1:
+ case FM2_DTSEC2:
+ case FM2_DTSEC3:
+ case FM2_DTSEC4:
+ case FM2_DTSEC5:
+ case FM2_DTSEC6:
+ case FM2_DTSEC9:
+ case FM2_DTSEC10:
+ if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
+ return PHY_INTERFACE_MODE_SGMII;
+ break;
+ default:
+ return PHY_INTERFACE_MODE_NONE;
+ }
+
+ return PHY_INTERFACE_MODE_NONE;
+}
int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
- short rdreg; /* register working value */
-
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
- rdreg = mii_send(mk_mii_write(addr, reg, value));
+ mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
return 1;
}
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
static void fsl_pcie_boot_master(pit_t *pi)
{
/* configure inbound window for slave's u-boot image */
release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
+#ifdef CONFIG_SYS_PCIE2_MEM_VIRT
case 2:
release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
+#endif
+#ifdef CONFIG_SYS_PCIE3_MEM_VIRT
case 3:
release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
+ CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
break;
+#endif
default:
release_addr = 0;
break;
/* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
char *s = getenv("bootmaster");
char pcie[6];
}
#ifndef CONFIG_PCI_NOSCAN
- pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
-
- /* Programming Interface (PCI_CLASS_PROG)
- * 0 == pci host or pcie root-complex,
- * 1 == pci agent or pcie end-point
- */
- if (!temp8) {
+ if (!fsl_is_pci_agent(hose)) {
debug(" Scanning PCI bus %02x\n",
hose->current_busno);
hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
int fsl_is_pci_agent(struct pci_controller *hose)
{
- u8 prog_if;
+ u8 pcie_cap;
pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
- pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
+ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+ if (pcie_cap == PCI_CAP_ID_EXP) {
+ u8 header_type;
- return (prog_if == FSL_PROG_IF_AGENT);
+ pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
+ &header_type);
+ return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
+ } else {
+ u8 prog_if;
+
+ pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
+ return (prog_if == FSL_PROG_IF_AGENT);
+ }
}
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
if (fsl_is_pci_agent(hose)) {
fsl_pci_config_unlock(hose);
hose->last_busno = hose->first_busno;
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
} else {
/* boot from PCIE --master releases slave's core 0 */
char *s = getenv("bootmaster");
void fsl_pci_config_unlock(struct pci_controller *hose)
{
pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
- u8 agent;
u8 pcie_cap;
u16 pbfr;
- pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
- if (!agent)
+ if (!fsl_is_pci_agent(hose))
return;
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
}
#if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
+ #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
+ #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
+ #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
+#else
#define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
#define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
#define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
#define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
+#endif
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
#define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
{
struct fsl_pci_info pci_info;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
- u32 devdisr = in_be32(&gur->devdisr);
+ u32 devdisr;
+ u32 *addr;
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ addr = &gur->devdisr3;
+#else
+ addr = &gur->devdisr;
+#endif
+ devdisr = in_be32(addr);
#ifdef CONFIG_PCIE1
SET_STD_PCIE_INFO(pci_info, 1);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
+ setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
#endif
#ifdef CONFIG_PCIE2
SET_STD_PCIE_INFO(pci_info, 2);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
+ setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE3
SET_STD_PCIE_INFO(pci_info, 3);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */
+ setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE4
SET_STD_PCIE_INFO(pci_info, 4);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
#else
- setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */
+ setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
#endif
return busno;
* we just need to know what the SNUMs are for the threads.
*/
static u8 thread_snum[] = {
+/* Evthreads 16-29 are not supported in MPC8309 */
+#if !defined(CONFIG_MPC8309)
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
- 0x34, 0x35, 0x88, 0x89,
- 0x98, 0x99, 0xa8, 0xa9,
- 0xb8, 0xb9, 0xc8, 0xc9,
- 0xd8, 0xd9, 0xe8, 0xe9,
- 0x08, 0x09, 0x18, 0x19,
- 0x28, 0x29, 0x38, 0x39,
- 0x48, 0x49, 0x58, 0x59,
- 0x68, 0x69, 0x78, 0x79,
- 0x80, 0x81
+ 0x34, 0x35,
+#endif
+ 0x88, 0x89, 0x98, 0x99,
+ 0xa8, 0xa9, 0xb8, 0xb9,
+ 0xc8, 0xc9, 0xd8, 0xd9,
+ 0xe8, 0xe9, 0x08, 0x09,
+ 0x18, 0x19, 0x28, 0x29,
+ 0x38, 0x39, 0x48, 0x49,
+ 0x58, 0x59, 0x68, 0x69,
+ 0x78, 0x79, 0x80, 0x81
};
static void qe_snums_init(void)
writel ((unsigned char)c, &jtag->data);
}
-static void altera_jtag_serial_puts(const char *s)
-{
- while (*s != 0)
- serial_putc (*s++);
-}
-
static int altera_jtag_serial_tstc(void)
{
return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
.stop = NULL,
.setbrg = altera_jtag_serial_setbrg,
.putc = altera_jtag_serial_putc,
- .puts = altera_jtag_serial_puts,
+ .puts = default_serial_puts,
.getc = altera_jtag_serial_getc,
.tstc = altera_jtag_serial_tstc,
};
writel ((unsigned char)c, &uart->txdata);
}
-static void altera_serial_puts(const char *s)
-{
- while (*s != 0) {
- serial_putc (*s++);
- }
-}
-
static int altera_serial_tstc(void)
{
return (readl (&uart->status) & NIOS_UART_RRDY);
.stop = NULL,
.setbrg = altera_serial_setbrg,
.putc = altera_serial_putc,
- .puts = altera_serial_puts,
+ .puts = default_serial_puts,
.getc = altera_serial_getc,
.tstc = altera_serial_tstc,
};
writel(c, &usart->thr);
}
-static void atmel_serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
static int atmel_serial_getc(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
.stop = NULL,
.setbrg = atmel_serial_setbrg,
.putc = atmel_serial_putc,
- .puts = atmel_serial_puts,
+ .puts = default_serial_puts,
.getc = atmel_serial_getc,
.tstc = atmel_serial_tstc,
};
return 0;
}
-static void lpc32xx_serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
static struct serial_device lpc32xx_serial_drv = {
.name = "lpc32xx_serial",
.start = lpc32xx_serial_init,
.stop = NULL,
.setbrg = lpc32xx_serial_setbrg,
.putc = lpc32xx_serial_putc,
- .puts = lpc32xx_serial_puts,
+ .puts = default_serial_puts,
.getc = lpc32xx_serial_getc,
.tstc = lpc32xx_serial_tstc,
};
*/
#include <common.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include <asm/immap.h>
#include <asm/uart.h>
uart->utb = c;
}
-static void mcf_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
static int mcf_serial_getc(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
.stop = NULL,
.setbrg = mcf_serial_setbrg,
.putc = mcf_serial_putc,
- .puts = mcf_serial_puts,
+ .puts = default_serial_puts,
.getc = mcf_serial_getc,
.tstc = mcf_serial_tstc,
};
CONSOLE) = c;
}
-/***********************************************************************
- * @Function: serial_puts
- * @Return: n/a
- * @Descr: writes non-zero string to the FIFO.
- ***********************************************************************/
-
-static void ns9750_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc( *s++ );
- }
-}
-
/***********************************************************************
* @Function: serial_getc
* @Return: the character read
.stop = NULL,
.setbrg = ns9750_serial_setbrg,
.putc = ns9750_serial_putc,
- .puts = ns9750_serial_puts,
+ .puts = default_serial_puts,
.getc = ns9750_serial_getc,
.tstc = ns9750_serial_tstc,
};
writel((unsigned char)c, &uart->data);
}
-static void oc_serial_puts(const char *s)
-{
- while (*s != 0) {
- serial_putc (*s++);
- }
-}
-
-
static int oc_serial_tstc(void)
{
unsigned status ;
.stop = NULL,
.setbrg = oc_serial_setbrg,
.putc = oc_serial_putc,
- .puts = oc_serial_puts,
+ .puts = default_serial_puts,
.getc = oc_serial_getc,
.tstc = oc_serial_tstc,
};
static void s3c4510b_serial_puts(const char *s)
{
- while (*s) {
- serial_putc (*s++);
- }
+ default_serial_puts(s);
/* busy wait for tx complete */
- while ( !uart->m_stat.bf.txComplete);
+ while (!uart->m_stat.bf.txComplete);
/* clear break */
uart->m_ctrl.bf.sendBreak = 0;
return uart->UTRSTAT & 0x1;
}
-static void s3c64xx_serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
static struct serial_device s3c64xx_serial_drv = {
.name = "s3c64xx_serial",
.start = s3c64xx_serial_init,
.stop = NULL,
.setbrg = s3c64xx_serial_setbrg,
.putc = s3c64xx_serial_putc,
- .puts = s3c64xx_serial_puts,
+ .puts = default_serial_puts,
.getc = s3c64xx_serial_getc,
.tstc = s3c64xx_serial_tstc,
};
#include <stdio_dev.h>
#include <post.h>
#include <linux/compiler.h>
+#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
static struct serial_device *serial_devices;
static struct serial_device *serial_current;
+/**
+ * serial_null() - Void registration routine of a serial driver
+ *
+ * This routine implements a void registration routine of a serial
+ * driver. The registration routine of a particular driver is aliased
+ * to this empty function in case the driver is not compiled into
+ * U-Boot.
+ */
static void serial_null(void)
{
}
+/**
+ * serial_initfunc() - Forward declare of driver registration routine
+ * @name: Name of the real driver registration routine.
+ *
+ * This macro expands onto forward declaration of a driver registration
+ * routine, which is then used below in serial_initialize() function.
+ * The declaration is made weak and aliases to serial_null() so in case
+ * the driver is not compiled in, the function is still declared and can
+ * be used, but aliases to serial_null() and thus is optimized away.
+ */
#define serial_initfunc(name) \
void name(void) \
__attribute__((weak, alias("serial_null")));
serial_initfunc(sa1100_serial_initialize);
serial_initfunc(sh_serial_initialize);
+/**
+ * serial_register() - Register serial driver with serial driver core
+ * @dev: Pointer to the serial driver structure
+ *
+ * This function registers the serial driver supplied via @dev with
+ * serial driver core, thus making U-Boot aware of it and making it
+ * available for U-Boot to use. On platforms that still require manual
+ * relocation of constant variables, relocation of the supplied structure
+ * is performed.
+ */
void serial_register(struct serial_device *dev)
{
#ifdef CONFIG_NEEDS_MANUAL_RELOC
serial_devices = dev;
}
+/**
+ * serial_initialize() - Register all compiled-in serial port drivers
+ *
+ * This function registers all serial port drivers that are compiled
+ * into the U-Boot binary with the serial core, thus making them
+ * available to U-Boot to use. Lastly, this function assigns a default
+ * serial port to the serial core. That serial port is then used as a
+ * default output.
+ */
void serial_initialize(void)
{
mpc8xx_serial_initialize();
serial_assign(default_serial_console()->name);
}
+/**
+ * serial_stdio_init() - Register serial ports with STDIO core
+ *
+ * This function generates a proxy driver for each serial port driver.
+ * These proxy drivers then register with the STDIO core, making the
+ * serial drivers available as STDIO devices.
+ */
void serial_stdio_init(void)
{
struct stdio_dev dev;
}
}
+/**
+ * serial_assign() - Select the serial output device by name
+ * @name: Name of the serial driver to be used as default output
+ *
+ * This function configures the serial output multiplexing by
+ * selecting which serial device will be used as default. In case
+ * the STDIO "serial" device is selected as stdin/stdout/stderr,
+ * the serial device previously configured by this function will be
+ * used for the particular operation.
+ *
+ * Returns 0 on success, negative on error.
+ */
int serial_assign(const char *name)
{
struct serial_device *s;
for (s = serial_devices; s; s = s->next) {
- if (strcmp(s->name, name) == 0) {
- serial_current = s;
- return 0;
- }
+ if (strcmp(s->name, name))
+ continue;
+ serial_current = s;
+ return 0;
}
- return 1;
+ return -EINVAL;
}
+/**
+ * serial_reinit_all() - Reinitialize all compiled-in serial ports
+ *
+ * This function reinitializes all serial ports that are compiled
+ * into U-Boot by calling their serial_start() functions.
+ */
void serial_reinit_all(void)
{
struct serial_device *s;
s->start();
}
+/**
+ * get_current() - Return pointer to currently selected serial port
+ *
+ * This function returns a pointer to currently selected serial port.
+ * The currently selected serial port is altered by serial_assign()
+ * function.
+ *
+ * In case this function is called before relocation or before any serial
+ * port is configured, this function calls default_serial_console() to
+ * determine the serial port. Otherwise, the configured serial port is
+ * returned.
+ *
+ * Returns pointer to the currently selected serial port on success,
+ * NULL on error.
+ */
static struct serial_device *get_current(void)
{
struct serial_device *dev;
- if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
+ if (!(gd->flags & GD_FLG_RELOC))
+ dev = default_serial_console();
+ else if (!serial_current)
dev = default_serial_console();
+ else
+ dev = serial_current;
- /* We must have a console device */
- if (!dev) {
+ /* We must have a console device */
+ if (!dev) {
#ifdef CONFIG_SPL_BUILD
- puts("Cannot find console\n");
- hang();
+ puts("Cannot find console\n");
+ hang();
#else
- panic("Cannot find console\n");
+ panic("Cannot find console\n");
#endif
- }
- } else
- dev = serial_current;
+ }
+
return dev;
}
+/**
+ * serial_init() - Initialize currently selected serial port
+ *
+ * This function initializes the currently selected serial port. This
+ * usually involves setting up the registers of that particular port,
+ * enabling clock and such. This function uses the get_current() call
+ * to determine which port is selected.
+ *
+ * Returns 0 on success, negative on error.
+ */
int serial_init(void)
{
return get_current()->start();
}
+/**
+ * serial_setbrg() - Configure baud-rate of currently selected serial port
+ *
+ * This function configures the baud-rate of the currently selected
+ * serial port. The baud-rate is retrieved from global data within
+ * the serial port driver. This function uses the get_current() call
+ * to determine which port is selected.
+ *
+ * Returns 0 on success, negative on error.
+ */
void serial_setbrg(void)
{
get_current()->setbrg();
}
+/**
+ * serial_getc() - Read character from currently selected serial port
+ *
+ * This function retrieves a character from currently selected serial
+ * port. In case there is no character waiting on the serial port,
+ * this function will block and wait for the character to appear. This
+ * function uses the get_current() call to determine which port is
+ * selected.
+ *
+ * Returns the character on success, negative on error.
+ */
int serial_getc(void)
{
return get_current()->getc();
}
+/**
+ * serial_tstc() - Test if data is available on currently selected serial port
+ *
+ * This function tests if one or more characters are available on
+ * currently selected serial port. This function never blocks. This
+ * function uses the get_current() call to determine which port is
+ * selected.
+ *
+ * Returns positive if character is available, zero otherwise.
+ */
int serial_tstc(void)
{
return get_current()->tstc();
}
+/**
+ * serial_putc() - Output character via currently selected serial port
+ * @c: Single character to be output from the serial port.
+ *
+ * This function outputs a character via currently selected serial
+ * port. This character is passed to the serial port driver responsible
+ * for controlling the hardware. The hardware may still be in process
+ * of transmitting another character, therefore this function may block
+ * for a short amount of time. This function uses the get_current()
+ * call to determine which port is selected.
+ */
void serial_putc(const char c)
{
get_current()->putc(c);
}
+/**
+ * serial_puts() - Output string via currently selected serial port
+ * @s: Zero-terminated string to be output from the serial port.
+ *
+ * This function outputs a zero-terminated string via currently
+ * selected serial port. This function behaves as an accelerator
+ * in case the hardware can queue multiple characters for transfer.
+ * The whole string that is to be output is available to the function
+ * implementing the hardware manipulation. Transmitting the whole
+ * string may take some time, thus this function may block for some
+ * amount of time. This function uses the get_current() call to
+ * determine which port is selected.
+ */
void serial_puts(const char *s)
{
get_current()->puts(s);
}
+/**
+ * default_serial_puts() - Output string by calling serial_putc() in loop
+ * @s: Zero-terminated string to be output from the serial port.
+ *
+ * This function outputs a zero-terminated string by calling serial_putc()
+ * in a loop. Most drivers do not support queueing more than one byte for
+ * transfer, thus this function precisely implements their serial_puts().
+ *
+ * To optimize the number of get_current() calls, this function only
+ * calls get_current() once and then directly accesses the putc() call
+ * of the &struct serial_device .
+ */
+void default_serial_puts(const char *s)
+{
+ struct serial_device *dev = get_current();
+ while (*s)
+ dev->putc(*s++);
+}
+
#if CONFIG_POST & CONFIG_SYS_POST_UART
static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
+/**
+ * uart_post_test() - Test the currently selected serial port using POST
+ * @flags: POST framework flags
+ *
+ * Do a loopback test of the currently selected serial port. This
+ * function is only useful in the context of the POST testing framwork.
+ * The serial port is firstly configured into loopback mode and then
+ * characters are sent through it.
+ *
+ * Returns 0 on success, value otherwise.
+ */
/* Mark weak until post/cpu/.../uart.c migrate over */
__weak
int uart_post_test(int flags)
return IO_UARTDR1 & 0xff;
}
-static void clps7111_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device clps7111_serial_drv = {
.name = "clps7111_serial",
.start = clps7111_serial_init,
.stop = NULL,
.setbrg = clps7111_serial_setbrg,
.putc = clps7111_serial_putc,
- .puts = clps7111_serial_puts,
+ .puts = default_serial_puts,
.getc = clps7111_serial_getc,
.tstc = clps7111_serial_tstc,
};
return 1;
}
-static void imx_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device imx_serial_drv = {
.name = "imx_serial",
.start = imx_serial_init,
.stop = NULL,
.setbrg = imx_serial_setbrg,
.putc = imx_serial_putc,
- .puts = imx_serial_puts,
+ .puts = default_serial_puts,
.getc = imx_serial_getc,
.tstc = imx_serial_tstc,
};
return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
}
-static void ixp_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device ixp_serial_drv = {
.name = "ixp_serial",
.start = ixp_serial_init,
.stop = NULL,
.setbrg = ixp_serial_setbrg,
.putc = ixp_serial_putc,
- .puts = ixp_serial_puts,
+ .puts = default_serial_puts,
.getc = ixp_serial_getc,
.tstc = ixp_serial_tstc,
};
return 0;
}
-static void ks8695_serial_puts(const char *s)
-{
- char c;
- while ((c = *s++) != 0)
- serial_putc(c);
-}
-
static int ks8695_serial_getc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
.stop = NULL,
.setbrg = ks8695_serial_setbrg,
.putc = ks8695_serial_putc,
- .puts = ks8695_serial_puts,
+ .puts = default_serial_puts,
.getc = ks8695_serial_getc,
.tstc = ks8695_serial_tstc,
};
return GET8(U0RBR);
}
-static void lpc2292_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
/* Test if there is a byte to read */
static int lpc2292_serial_tstc(void)
{
.stop = NULL,
.setbrg = lpc2292_serial_setbrg,
.putc = lpc2292_serial_putc,
- .puts = lpc2292_serial_puts,
+ .puts = default_serial_puts,
.getc = lpc2292_serial_getc,
.tstc = lpc2292_serial_tstc,
};
return 1;
}
-static void mxc_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
.stop = NULL,
.setbrg = mxc_serial_setbrg,
.putc = mxc_serial_putc,
- .puts = mxc_serial_puts,
+ .puts = default_serial_puts,
.getc = mxc_serial_getc,
.tstc = mxc_serial_tstc,
};
return ch_uint & 0xff;
}
-static void netarm_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device netarm_serial_drv = {
.name = "netarm_serial",
.start = netarm_serial_init,
.stop = NULL,
.setbrg = netarm_serial_setbrg,
.putc = netarm_serial_putc,
- .puts = netarm_serial_puts,
+ .puts = default_serial_puts,
.getc = netarm_serial_getc,
.tstc = netarm_serial_tstc,
};
pl01x_putc (CONSOLE_PORT, c);
}
-static void pl01x_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static int pl01x_serial_getc(void)
{
return pl01x_getc (CONSOLE_PORT);
.stop = NULL,
.setbrg = pl01x_serial_setbrg,
.putc = pl01x_serial_putc,
- .puts = pl01x_serial_puts,
+ .puts = default_serial_puts,
.getc = pl01x_serial_getc,
.tstc = pl01x_serial_tstc,
};
}
}
-static void s3c44b0_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device s3c44b0_serial_drv = {
.name = "s3c44b0_serial",
.start = s3c44b0_serial_init,
.stop = NULL,
.setbrg = s3c44b0_serial_setbrg,
.putc = s3c44b0_serial_putc,
- .puts = s3c44b0_serial_puts,
+ .puts = default_serial_puts,
.getc = s3c44b0_serial_getc,
.tstc = s3c44b0_serial_tstc,
};
#endif
}
-static void sa1100_serial_puts(const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
static struct serial_device sa1100_serial_drv = {
.name = "sa1100_serial",
.start = sa1100_serial_init,
.stop = NULL,
.setbrg = sa1100_serial_setbrg,
.putc = sa1100_serial_putc,
- .puts = sa1100_serial_puts,
+ .puts = default_serial_puts,
.getc = sa1100_serial_getc,
.tstc = sa1100_serial_tstc,
};
serial_raw_putc(c);
}
-static void sh_serial_puts(const char *s)
-{
- char c;
- while ((c = *s++) != 0)
- serial_putc(c);
-}
-
static int sh_serial_tstc(void)
{
return serial_rx_fifo_level() ? 1 : 0;
.stop = NULL,
.setbrg = sh_serial_setbrg,
.putc = sh_serial_putc,
- .puts = sh_serial_puts,
+ .puts = default_serial_puts,
.getc = sh_serial_getc,
.tstc = sh_serial_tstc,
};
return 1;
}
memcpy(buffer, cmd_buf, cmd_len);
- if (cmd_len != 1) {
- if (data_in == NULL)
- memcpy(buffer + cmd_len, data_out, data_len);
- }
+ if (data_in == NULL)
+ memcpy(buffer + cmd_len, data_out, data_len);
break;
case SPI_XFER_BEGIN | SPI_XFER_END:
len = data_len;
#include "ehci.h"
+/* Check USB PHY clock valid */
+static int usb_phy_clk_valid(struct usb_ehci *ehci)
+{
+ if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
+ in_be32(&ehci->prictrl))) {
+ printf("USB PHY clock invalid!\n");
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
+ setbits_be32(&ehci->control, USB_EN);
} else {
-#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- clrbits_be32(&ehci->control, UTMI_PHY_EN);
setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
udelay(1000); /* delay required for PHY Clk to appear */
-#endif
+ if (!usb_phy_clk_valid(ehci))
+ return -EINVAL;
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
}
- /* Enable interface. */
- setbits_be32(&ehci->control, USB_EN);
-
out_be32(&ehci->prictrl, 0x0000000c);
out_be32(&ehci->age_cnt_limit, 0x00000040);
out_be32(&ehci->sictrl, 0x00000001);
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
+OUTPUT_ARCH(mips)
+SECTIONS
+{
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ .sdata : { *(.sdata*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
+
+ _end = .;
+}
{
*(.data)
}
+
. = ALIGN(4);
__data_end = .;
#
#
+subdirs-$(CONFIG_CMD_CBFS) += cbfs
subdirs-$(CONFIG_CMD_CRAMFS) := cramfs
subdirs-$(CONFIG_CMD_EXT4) += ext4
ifndef CONFIG_CMD_EXT4
--- /dev/null
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)libcbfs.o
+
+COBJS-$(CONFIG_CMD_CBFS) := cbfs.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+
+all: $(LIB)
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <cbfs.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+
+enum cbfs_result file_cbfs_result;
+
+const char *file_cbfs_error(void)
+{
+ switch (file_cbfs_result) {
+ case CBFS_SUCCESS:
+ return "Success";
+ case CBFS_NOT_INITIALIZED:
+ return "CBFS not initialized";
+ case CBFS_BAD_HEADER:
+ return "Bad CBFS header";
+ case CBFS_BAD_FILE:
+ return "Bad CBFS file";
+ case CBFS_FILE_NOT_FOUND:
+ return "File not found";
+ default:
+ return "Unknown";
+ }
+}
+
+
+static const u32 good_magic = 0x4f524243;
+static const u8 good_file_magic[] = "LARCHIVE";
+
+
+static int initialized;
+static struct cbfs_header cbfs_header;
+static struct cbfs_cachenode *file_cache;
+
+/* Do endian conversion on the CBFS header structure. */
+static void swap_header(struct cbfs_header *dest, struct cbfs_header *src)
+{
+ dest->magic = be32_to_cpu(src->magic);
+ dest->version = be32_to_cpu(src->version);
+ dest->rom_size = be32_to_cpu(src->rom_size);
+ dest->boot_block_size = be32_to_cpu(src->boot_block_size);
+ dest->align = be32_to_cpu(src->align);
+ dest->offset = be32_to_cpu(src->offset);
+}
+
+/* Do endian conversion on a CBFS file header. */
+static void swap_file_header(struct cbfs_fileheader *dest,
+ const struct cbfs_fileheader *src)
+{
+ memcpy(&dest->magic, &src->magic, sizeof(dest->magic));
+ dest->len = be32_to_cpu(src->len);
+ dest->type = be32_to_cpu(src->type);
+ dest->checksum = be32_to_cpu(src->checksum);
+ dest->offset = be32_to_cpu(src->offset);
+}
+
+/*
+ * Given a starting position in memory, scan forward, bounded by a size, and
+ * find the next valid CBFS file. No memory is allocated by this function. The
+ * caller is responsible for allocating space for the new file structure.
+ *
+ * @param start The location in memory to start from.
+ * @param size The size of the memory region to search.
+ * @param align The alignment boundaries to check on.
+ * @param newNode A pointer to the file structure to load.
+ * @param used A pointer to the count of of bytes scanned through,
+ * including the file if one is found.
+ *
+ * @return 1 if a file is found, 0 if one isn't.
+ */
+static int file_cbfs_next_file(u8 *start, u32 size, u32 align,
+ struct cbfs_cachenode *newNode, u32 *used)
+{
+ struct cbfs_fileheader header;
+
+ *used = 0;
+
+ while (size >= align) {
+ const struct cbfs_fileheader *fileHeader =
+ (const struct cbfs_fileheader *)start;
+ u32 name_len;
+ u32 step;
+
+ /* Check if there's a file here. */
+ if (memcmp(good_file_magic, &(fileHeader->magic),
+ sizeof(fileHeader->magic))) {
+ *used += align;
+ size -= align;
+ start += align;
+ continue;
+ }
+
+ swap_file_header(&header, fileHeader);
+ if (header.offset < sizeof(const struct cbfs_cachenode *) ||
+ header.offset > header.len) {
+ file_cbfs_result = CBFS_BAD_FILE;
+ return -1;
+ }
+ newNode->next = NULL;
+ newNode->type = header.type;
+ newNode->data = start + header.offset;
+ newNode->data_length = header.len;
+ name_len = header.offset - sizeof(struct cbfs_cachenode *);
+ newNode->name = (char *)fileHeader +
+ sizeof(struct cbfs_cachenode *);
+ newNode->name_length = name_len;
+ newNode->checksum = header.checksum;
+
+ step = header.len;
+ if (step % align)
+ step = step + align - step % align;
+
+ *used += step;
+ return 1;
+ }
+ return 0;
+}
+
+/* Look through a CBFS instance and copy file metadata into regular memory. */
+static void file_cbfs_fill_cache(u8 *start, u32 size, u32 align)
+{
+ struct cbfs_cachenode *cache_node;
+ struct cbfs_cachenode *newNode;
+ struct cbfs_cachenode **cache_tail = &file_cache;
+
+ /* Clear out old information. */
+ cache_node = file_cache;
+ while (cache_node) {
+ struct cbfs_cachenode *oldNode = cache_node;
+ cache_node = cache_node->next;
+ free(oldNode);
+ }
+ file_cache = NULL;
+
+ while (size >= align) {
+ int result;
+ u32 used;
+
+ newNode = (struct cbfs_cachenode *)
+ malloc(sizeof(struct cbfs_cachenode));
+ result = file_cbfs_next_file(start, size, align,
+ newNode, &used);
+
+ if (result < 0) {
+ free(newNode);
+ return;
+ } else if (result == 0) {
+ free(newNode);
+ break;
+ }
+ *cache_tail = newNode;
+ cache_tail = &newNode->next;
+
+ size -= used;
+ start += used;
+ }
+ file_cbfs_result = CBFS_SUCCESS;
+}
+
+/* Get the CBFS header out of the ROM and do endian conversion. */
+static int file_cbfs_load_header(uintptr_t end_of_rom,
+ struct cbfs_header *header)
+{
+ struct cbfs_header *header_in_rom;
+
+ header_in_rom = (struct cbfs_header *)(uintptr_t)
+ *(u32 *)(end_of_rom - 3);
+ swap_header(header, header_in_rom);
+
+ if (header->magic != good_magic || header->offset >
+ header->rom_size - header->boot_block_size) {
+ file_cbfs_result = CBFS_BAD_HEADER;
+ return 1;
+ }
+ return 0;
+}
+
+void file_cbfs_init(uintptr_t end_of_rom)
+{
+ u8 *start_of_rom;
+ initialized = 0;
+
+ if (file_cbfs_load_header(end_of_rom, &cbfs_header))
+ return;
+
+ start_of_rom = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size);
+
+ file_cbfs_fill_cache(start_of_rom + cbfs_header.offset,
+ cbfs_header.rom_size, cbfs_header.align);
+ if (file_cbfs_result == CBFS_SUCCESS)
+ initialized = 1;
+}
+
+const struct cbfs_header *file_cbfs_get_header(void)
+{
+ if (initialized) {
+ file_cbfs_result = CBFS_SUCCESS;
+ return &cbfs_header;
+ } else {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ return NULL;
+ }
+}
+
+const struct cbfs_cachenode *file_cbfs_get_first(void)
+{
+ if (!initialized) {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ return NULL;
+ } else {
+ file_cbfs_result = CBFS_SUCCESS;
+ return file_cache;
+ }
+}
+
+void file_cbfs_get_next(const struct cbfs_cachenode **file)
+{
+ if (!initialized) {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ file = NULL;
+ return;
+ }
+
+ if (*file)
+ *file = (*file)->next;
+ file_cbfs_result = CBFS_SUCCESS;
+}
+
+const struct cbfs_cachenode *file_cbfs_find(const char *name)
+{
+ struct cbfs_cachenode *cache_node = file_cache;
+
+ if (!initialized) {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ return NULL;
+ }
+
+ while (cache_node) {
+ if (!strcmp(name, cache_node->name))
+ break;
+ cache_node = cache_node->next;
+ }
+ if (!cache_node)
+ file_cbfs_result = CBFS_FILE_NOT_FOUND;
+ else
+ file_cbfs_result = CBFS_SUCCESS;
+
+ return cache_node;
+}
+
+const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
+ const char *name)
+{
+ u8 *start;
+ u32 size;
+ u32 align;
+ static struct cbfs_cachenode node;
+
+ if (file_cbfs_load_header(end_of_rom, &cbfs_header))
+ return NULL;
+
+ start = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size);
+ size = cbfs_header.rom_size;
+ align = cbfs_header.align;
+
+ while (size >= align) {
+ int result;
+ u32 used;
+
+ result = file_cbfs_next_file(start, size, align, &node, &used);
+
+ if (result < 0)
+ return NULL;
+ else if (result == 0)
+ break;
+
+ if (!strcmp(name, node.name))
+ return &node;
+
+ size -= used;
+ start += used;
+ }
+ file_cbfs_result = CBFS_FILE_NOT_FOUND;
+ return NULL;
+}
+
+const char *file_cbfs_name(const struct cbfs_cachenode *file)
+{
+ file_cbfs_result = CBFS_SUCCESS;
+ return file->name;
+}
+
+u32 file_cbfs_size(const struct cbfs_cachenode *file)
+{
+ file_cbfs_result = CBFS_SUCCESS;
+ return file->data_length;
+}
+
+u32 file_cbfs_type(const struct cbfs_cachenode *file)
+{
+ file_cbfs_result = CBFS_SUCCESS;
+ return file->type;
+}
+
+long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer,
+ unsigned long maxsize)
+{
+ u32 size;
+
+ size = file->data_length;
+ if (maxsize && size > maxsize)
+ size = maxsize;
+
+ memcpy(buffer, file->data, size);
+
+ file_cbfs_result = CBFS_SUCCESS;
+ return size;
+}
}
/* Calculate short name checksum */
-static __u8 mkcksum(const char *str)
+static __u8 mkcksum(const char name[8], const char ext[3])
{
int i;
__u8 ret = 0;
- for (i = 0; i < 11; i++) {
- ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + str[i];
- }
+ for (i = 0; i < sizeof(name); i++)
+ ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + name[i];
+ for (i = 0; i < sizeof(ext); i++)
+ ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + ext[i];
return ret;
}
return NULL;
}
#ifdef CONFIG_SUPPORT_VFAT
- if (dols && mkcksum(dentptr->name) == prevcksum) {
+ __u8 csum = mkcksum(dentptr->name, dentptr->ext);
+ if (dols && csum == prevcksum) {
prevcksum = 0xffff;
dentptr++;
continue;
for (i = 0; i < DIRENTSPERBLOCK; i++) {
char s_name[14], l_name[VFAT_MAXLEN_BYTES];
+ __u8 csum;
l_name[0] = '\0';
if (dentptr->name[0] == DELETED_FLAG) {
dentptr++;
continue;
}
- if ((dentptr->attr & ATTR_VOLUME)) {
+
+ csum = mkcksum(dentptr->name, dentptr->ext);
+ if (dentptr->attr & ATTR_VOLUME) {
#ifdef CONFIG_SUPPORT_VFAT
if ((dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
goto exit;
}
#ifdef CONFIG_SUPPORT_VFAT
- else if (dols == LS_ROOT &&
- mkcksum(dentptr->name) == prevcksum) {
+ else if (dols == LS_ROOT && csum == prevcksum) {
prevcksum = 0xffff;
dentptr++;
continue;
/* Get short file name and checksum value */
strncpy(s_name, (*dentptr)->name, 16);
- checksum = mkcksum(s_name);
+ checksum = mkcksum((*dentptr)->name, (*dentptr)->ext);
do {
memset(slotptr, 0x00, sizeof(dir_slot));
--- /dev/null
+#
+# Copyright (C) 2012 Marek Vasut <marex@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+#########################################################################
+
+##
+# make_u_boot_list - Generate contents of u_boot_list section
+# 1: The name of the resulting file (usually u-boot.lst)
+# 2: Files to analyze for possible u_boot_list entries
+#
+# This function generates the contents of the u_boot_list section,
+# including all the border symbols for it's subsections. The operation
+# of this function is as follows, numbering goes per lines:
+#
+# 1) Dump the ELF header sections from all files supplied via $(2)
+# 2) Filter out all other stuff that does not belong into .u_boot_list
+# section.
+# 3) Fix up the lines so that the resulting output is is in format
+# ".u_boot_list.*".
+# 4) Remove the last .something$, since that only contains the name
+# of the variable to be put into a subsection. This name is irelevant
+# for generation of border symbols, thus of no interest, remove it.
+# 5) Take each line and for every dot "." in that line, print the whole
+# line until that dot "." . This is important so that we have all
+# parent border symbols generated as well.
+# 6) Load every line and firstly append "\a" at the end and print the
+# line. Next, append "@" at the end and print the line. Finally,
+# append "~" at the end of line. This will make sense in conjunction
+# with 6) and 7).
+# 7) Sort the lines. It is imperative to use LC_COLLATE=C here because
+# with this, the "\a" symbol is first and "~" symbol is last. Any
+# other symbols fall inbetween. Symbols like "@", which marks the
+# end of current line (representing current section) and ".", which
+# means the line continues and thus represents subsection.
+# 8) With such ordering, all lines ending with "\a" will float at the
+# begining of all lines with the same prefix. Thus it is easy to
+# replace "\a" with __start and make it the __start border symbol.
+# Very similarly for "~", which will be always at the bottom and so
+# can be replaced by "__end" and made into the __end border symbol.
+# Finally, every line ending with "@" symbol will be transformed
+# into " *(SORT(${line}*)); " format, which in the linker parlance
+# will allow it to trap all symbols relevant to the subsection.
+#
+define make_u_boot_list
+$(1): $(2)
+ $(OBJDUMP) -h $(2) | \
+ sed -n -e '/.*\.u_boot_list[^ ]\+/ ! {d;n}' \
+ -e 's/.*\(\.u_boot_list[^ ]\+\).*$$$$/\1/' \
+ -e 's/\.[^\.]\+$$$$//' \
+ -e ':s /^.\+$$$$/ { p;s/^\(.*\)\.[^\.]*$$$$/\1/;b s }' | \
+ sed -n -e 'h;s/$$$$/\a/p;g;s/$$$$/@/p;g;s/$$$$/~/p;' | \
+ LC_COLLATE=C sort -u | \
+ sed -n -e '/\a$$$$/ { s/\./_/g;s/\a$$$$/__start = .;/p; }'\
+ -e '/~$$$$/ { s/\./_/g;s/~$$$$/__end = .;/p; }'\
+ -e '/@$$$$/ { s/\(.*\)@$$$$/*(SORT(\1.*));/p }' > $(1)
+endef
--- /dev/null
+/*
+ * Generic bounce buffer implementation
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __INCLUDE_BOUNCEBUF_H__
+#define __INCLUDE_BOUNCEBUF_H__
+
+/*
+ * GEN_BB_READ -- Data are read from the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the operation
+ * requiring the aligned transfer happens, then the bounce buffer is lost upon
+ * stop() call.
+ */
+#define GEN_BB_READ (1 << 0)
+/*
+ * GEN_BB_WRITE -- Data are written into the buffer eg. by DMA hardware.
+ * The source buffer starts in an undefined state upon start() call, then the
+ * operation requiring the aligned transfer happens, then the bounce buffer is
+ * copied into the destination buffer (if unaligned, otherwise destination
+ * buffer is used directly) upon stop() call.
+ */
+#define GEN_BB_WRITE (1 << 1)
+/*
+ * GEN_BB_RW -- Data are read and written into the buffer eg. by DMA hardware.
+ * The source buffer is copied into the bounce buffer (if unaligned, otherwise
+ * the source buffer is used directly) upon start() call, then the operation
+ * requiring the aligned transfer happens, then the bounce buffer is copied
+ * into the destination buffer (if unaligned, otherwise destination buffer is
+ * used directly) upon stop() call.
+ */
+#define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE)
+
+#ifdef CONFIG_BOUNCE_BUFFER
+/**
+ * bounce_buffer_start() -- Start the bounce buffer session
+ * data: pointer to buffer to be aligned
+ * len: length of the buffer
+ * backup: pointer to backup buffer (the original value is stored here if
+ * needed
+ * flags: flags describing the transaction, see above.
+ */
+int bounce_buffer_start(void **data, size_t len, void **backup, uint8_t flags);
+/**
+ * bounce_buffer_stop() -- Finish the bounce buffer session
+ * data: pointer to buffer that was aligned
+ * len: length of the buffer
+ * backup: pointer to backup buffer (the original value is stored here if
+ * needed
+ * flags: flags describing the transaction, see above.
+ */
+int bounce_buffer_stop(void **data, size_t len, void **backup, uint8_t flags);
+#else
+static inline int bounce_buffer_start(void **data, size_t len, void **backup,
+ uint8_t flags)
+{
+ return 0;
+}
+
+static inline int bounce_buffer_stop(void **data, size_t len, void **backup,
+ uint8_t flags)
+{
+ return 0;
+}
+#endif
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CBFS_H
+#define __CBFS_H
+
+#include <compiler.h>
+#include <linux/compiler.h>
+
+enum cbfs_result {
+ CBFS_SUCCESS = 0,
+ CBFS_NOT_INITIALIZED,
+ CBFS_BAD_HEADER,
+ CBFS_BAD_FILE,
+ CBFS_FILE_NOT_FOUND
+};
+
+enum cbfs_filetype {
+ CBFS_TYPE_STAGE = 0x10,
+ CBFS_TYPE_PAYLOAD = 0x20,
+ CBFS_TYPE_OPTIONROM = 0x30,
+ CBFS_TYPE_BOOTSPLASH = 0x40,
+ CBFS_TYPE_RAW = 0x50,
+ CBFS_TYPE_VSA = 0x51,
+ CBFS_TYPE_MBI = 0x52,
+ CBFS_TYPE_MICROCODE = 0x53,
+ CBFS_COMPONENT_CMOS_DEFAULT = 0xaa,
+ CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa
+};
+
+struct cbfs_header {
+ u32 magic;
+ u32 version;
+ u32 rom_size;
+ u32 boot_block_size;
+ u32 align;
+ u32 offset;
+ u32 pad[2];
+} __packed;
+
+struct cbfs_fileheader {
+ u8 magic[8];
+ u32 len;
+ u32 type;
+ u32 checksum;
+ u32 offset;
+} __packed;
+
+struct cbfs_cachenode {
+ struct cbfs_cachenode *next;
+ u32 type;
+ void *data;
+ u32 data_length;
+ char *name;
+ u32 name_length;
+ u32 checksum;
+} __packed;
+
+extern enum cbfs_result file_cbfs_result;
+
+/*
+ * Return a string describing the most recent error condition.
+ *
+ * @return A pointer to the constant string.
+ */
+const char *file_cbfs_error(void);
+
+/*
+ * Initialize the CBFS driver and load metadata into RAM.
+ *
+ * @param end_of_rom Points to the end of the ROM the CBFS should be read
+ * from.
+ */
+void file_cbfs_init(uintptr_t end_of_rom);
+
+/*
+ * Get the header structure for the current CBFS.
+ *
+ * @return A pointer to the constant structure, or NULL if there is none.
+ */
+const struct cbfs_header *file_cbfs_get_header(void);
+
+/*
+ * Get a handle for the first file in CBFS.
+ *
+ * @return A handle for the first file in CBFS, NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_get_first(void);
+
+/*
+ * Get a handle to the file after this one in CBFS.
+ *
+ * @param file A pointer to the handle to advance.
+ */
+void file_cbfs_get_next(const struct cbfs_cachenode **file);
+
+/*
+ * Find a file with a particular name in CBFS.
+ *
+ * @param name The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find(const char *name);
+
+
+/***************************************************************************/
+/* All of the functions below can be used without first initializing CBFS. */
+/***************************************************************************/
+
+/*
+ * Find a file with a particular name in CBFS without using the heap.
+ *
+ * @param end_of_rom Points to the end of the ROM the CBFS should be read
+ * from.
+ * @param name The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
+ const char *name);
+
+/*
+ * Get the name of a file in CBFS.
+ *
+ * @param file The handle to the file.
+ *
+ * @return The name of the file, NULL on error.
+ */
+const char *file_cbfs_name(const struct cbfs_cachenode *file);
+
+/*
+ * Get the size of a file in CBFS.
+ *
+ * @param file The handle to the file.
+ *
+ * @return The size of the file, zero on error.
+ */
+u32 file_cbfs_size(const struct cbfs_cachenode *file);
+
+/*
+ * Get the type of a file in CBFS.
+ *
+ * @param file The handle to the file.
+ *
+ * @return The type of the file, zero on error.
+ */
+u32 file_cbfs_type(const struct cbfs_cachenode *file);
+
+/*
+ * Read a file from CBFS into RAM
+ *
+ * @param file A handle to the file to read.
+ * @param buffer Where to read it into memory.
+ *
+ * @return If positive or zero, the number of characters read. If negative, an
+ * error occurred.
+ */
+long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer,
+ unsigned long maxsize);
+
+#endif /* __CBFS_H */
#define __COMMAND_H
#include <config.h>
+#include <linker_lists.h>
#ifndef NULL
#define NULL 0
typedef struct cmd_tbl_s cmd_tbl_t;
-extern cmd_tbl_t __u_boot_cmd_start;
-extern cmd_tbl_t __u_boot_cmd_end;
#if defined(CONFIG_CMD_RUN)
extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */
#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */
-#define Struct_Section __attribute__((unused, section(".u_boot_cmd"), \
- aligned(4)))
-
#ifdef CONFIG_AUTO_COMPLETE
# define _CMD_COMPLETE(x) x,
#else
# define _CMD_HELP(x)
#endif
-#define U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
- {#name, maxargs, rep, cmd, usage, _CMD_HELP(help) _CMD_COMPLETE(comp)}
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
+ _usage, _help, _comp) \
+ { #_name, _maxargs, _rep, _cmd, _usage, \
+ _CMD_HELP(_help) _CMD_COMPLETE(_comp) }
-#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
- U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
+#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help) \
+ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
+ _usage, _help, NULL)
-#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
- cmd_tbl_t __u_boot_cmd_##name Struct_Section = \
- U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp)
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
+ ll_entry_declare(cmd_tbl_t, _name, cmd, cmd) = \
+ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
+ _usage, _help, _comp);
-#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
- U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
+#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help) \
+ U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL)
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_LXT
#define CONFIG_PHY_ATHEROS
+#define CONFIG_PHY_SMSC
#ifdef CONFIG_PHYLIB_10G
#define CONFIG_PHY_TERANETICS
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the CU824 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X 1
-#define CONFIG_MPC8245 1
-#define CONFIG_BMW 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
-#define DOC_PASSIVE_PROBE 1
-#define CONFIG_SYS_DOC_SUPPORT_2000 1
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT 1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-
-#if 0
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
-#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM }
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
-
- /* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_SYS_ETH_DEV_FN 0x7800
-#define CONFIG_SYS_ETH_IOBASE 0x00104000
-
- /* Bit-field values for MCCR1.
- */
-#define CONFIG_SYS_ROMNAL 0xf
-#define CONFIG_SYS_ROMFAL 0x1f
-#define CONFIG_SYS_DBUS_SIZE 0x3
-
- /* Bit-field values for MCCR2.
- */
-#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
-#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
-
- /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */
-
- /* Bit-field values for MCCR3.
- */
-#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
-
- /* Bit-field values for MCCR4.
- */
-#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
-#define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-
-#define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_ODCR 0xff
-
-#define CONFIG_PCI 1 /* Include PCI support */
-#undef CONFIG_PCI_PNP
-
-/* PCI Memory space(s) */
-#define PCI_MEM_SPACE1_START 0x80000000
-#define PCI_MEM_SPACE2_START 0xfd000000
-
-/* ROM Spaces */
-#include "../board/bmw/bmw.h"
-
-/* BAT configuration */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*
- * Warining: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
-#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
-#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
-#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#endif /* __CONFIG_H */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
--- /dev/null
+/*
+ * Configuation settings for the Freescale MCF54418 TWR board.
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef _M54418TWR_H
+#define _M54418TWR_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_MCF5441x /* define processor family */
+#define CONFIG_M54418 /* define processor type */
+#define CONFIG_M54418TWR /* M54418TWR board */
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT (0)
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Command line configuration */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_UBI
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_MII
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NAND_YAFFS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+/*
+ * NAND FLASH
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_JFFS2_NAND
+#define CONFIG_NAND_FSL_NFC
+#define CONFIG_SYS_NAND_BASE 0xFC0FC000
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#endif
+
+/* Network configuration */
+#define CONFIG_MCFFEC
+#ifdef CONFIG_MCFFEC
+#define CONFIG_NET_MULTI 1
+#define CONFIG_MII 1
+#define CONFIG_MII_INIT 1
+#define CONFIG_SYS_DISCOVER_PHY
+#define CONFIG_SYS_RX_ETH_BUFFER 2
+#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
+#define CONFIG_SYS_TX_ETH_BUFFER 2
+#define CONFIG_HAS_ETH1
+
+#define CONFIG_SYS_FEC0_PINMUX 0
+#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
+#define CONFIG_SYS_FEC1_PINMUX 0
+#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
+#define MCFFEC_TOUT_LOOP 50000
+#define CONFIG_SYS_FEC0_PHYADDR 0
+#define CONFIG_SYS_FEC1_PHYADDR 1
+
+#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
+ "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
+ "-(jffs2) console=ttyS0,115200"
+#else
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
+ __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
+ __stringify(CONFIG_IPADDR) " ip=" \
+ __stringify(CONFIG_IPADDR) ":" \
+ __stringify(CONFIG_SERVERIP)":" \
+ __stringify(CONFIG_GATEWAYIP)": " \
+ __stringify(CONFIG_NETMASK) \
+ "::eth0:off:rw console=ttyS0,115200"
+#endif
+
+#define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
+#define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
+#define CONFIG_ETHPRIME "FEC0"
+#define CONFIG_IPADDR 192.168.1.2
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_GATEWAYIP 192.168.1.1
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+#define CONFIG_SYS_FEC_BUF_USE_SRAM
+/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
+#ifndef CONFIG_SYS_DISCOVER_PHY
+#define FECDUPLEX FULL
+#define FECSPEED _100BASET
+#define LINKSTATUS 1
+#else
+#define LINKSTATUS 0
+#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif /* CONFIG_SYS_DISCOVER_PHY */
+#endif
+
+#define CONFIG_HOSTNAME M54418TWR
+
+#if defined(CONFIG_CF_SBF)
+/* ST Micro serial flash */
+#define CONFIG_SYS_LOAD_ADDR2 0x40010007
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "loadaddr=0x40010000\0" \
+ "sbfhdr=sbfhdr.bin\0" \
+ "uboot=u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${sbfhdr};" \
+ "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
+ "upd=run load; run prog\0" \
+ "prog=sf probe 0:1 1000000 3;" \
+ "sf erase 0 40000;" \
+ "sf write ${loadaddr} 0 40000;" \
+ "save\0" \
+ ""
+#elif defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "loadaddr=0x40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot};\0" \
+ "upd=run load; run prog\0" \
+ "prog=nand device 0;" \
+ "nand erase 0 40000;" \
+ "nb_update ${loadaddr} ${filesize};" \
+ "save\0" \
+ ""
+#else
+#define CONFIG_SYS_UBOOT_END 0x3FFFF
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "loadaddr=40010000\0" \
+ "u-boot=u-boot.bin\0" \
+ "load=tftp ${loadaddr) ${u-boot}\0" \
+ "upd=run load; run prog\0" \
+ "prog=prot off mram" " ;" \
+ "cp.b ${loadaddr} 0 ${filesize};" \
+ "save\0" \
+ ""
+#endif
+
+/* Realtime clock */
+#undef CONFIG_MCFRTC
+#define CONFIG_RTC_MCFRRTC
+#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* I2c */
+#undef CONFIG_FSL_I2C
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED 80000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x58000
+#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SBFHDR_SIZE 0x7
+#ifdef CONFIG_CMD_SPI
+# define CONFIG_SPI_FLASH
+# define CONFIG_SPI_FLASH_ATMEL
+
+# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
+ DSPI_CTAR_PCSSCK_1CLK | \
+ DSPI_CTAR_PASC(0) | \
+ DSPI_CTAR_PDT(0) | \
+ DSPI_CTAR_CSSCK(0) | \
+ DSPI_CTAR_ASC(0) | \
+ DSPI_CTAR_DT(1))
+# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
+# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
+#endif
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM 2048 /* 2048 KB */
+
+/* HUSH */
+#define CONFIG_SYS_HUSH_PARSER 1
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_SYS_PROMPT "-> "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_MBAR 0xFC000000
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
+/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_INIT_RAM_CTRL 0x221
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 256
+#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
+ CONFIG_SYS_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
+#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_DRAM_TEST
+
+#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_SERIAL_BOOT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN (256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
+ (CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_MRAM 1
+#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
+#define CONFIG_ENV_SIZE 0x1000
+#endif
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_SPI_FLASH 1
+#define CONFIG_ENV_SPI_CS 1
+#define CONFIG_ENV_OFFSET 0x40000
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#endif
+#if defined(CONFIG_SYS_NAND_BOOT)
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND 1
+#define CONFIG_ENV_OFFSET 0x80000
+#define CONFIG_ENV_SIZE 0x20000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#endif
+#undef CONFIG_ENV_OVERWRITE
+
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
+
+#undef CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+
+#define CONFIG_FLASH_CFI_DRIVER 1
+/* Max size that the board might have */
+#define CONFIG_SYS_FLASH_SIZE 0x1000000
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+/* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 270
+/* "Real" (hardware) sectors protection */
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
+#else
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_SECT 270
+/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS 0
+#endif
+
+/*
+ * This is setting for JFFS2 support in u-boot.
+ * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
+ */
+#ifdef CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_DEV "nand0"
+#define CONFIG_JFFS2_PART_OFFSET (0x800000)
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT "nand0=m54418twr.nand"
+
+#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
+ "7m(kernel)," \
+ "-(rootfs)"
+
+#endif
+
+#ifdef CONFIG_CMD_UBI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE /* needed for mtdparts command */
+#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
+#define CONFIG_RBTREE
+#define MTDIDS_DEFAULT "nand0=NAND"
+#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
+ "-(ubi)"
+#endif
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE 16
+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
+ CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+ CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
+ CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
+ CF_CACR_DEC | CF_CACR_DDCM_P | \
+ CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - 12)
+
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+/*
+ * CS0 - NOR Flash 16MB
+ * CS1 - Available
+ * CS2 - Available
+ * CS3 - Available
+ * CS4 - Available
+ * CS5 - Available
+ */
+
+ /* Flash */
+#define CONFIG_SYS_CS0_BASE 0x00000000
+#define CONFIG_SYS_CS0_MASK 0x000F0101
+#define CONFIG_SYS_CS0_CTRL 0x00001D60
+
+#endif /* _M54418TWR_H */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+#define CONFIG_SRIO2 /* SRIO port 2 */
+
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
#define CONFIG_MMC
#define CONFIG_PCIE3
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+#define CONFIG_SRIO2 /* SRIO port 2 */
+
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+#define CONFIG_SRIO2 /* SRIO port 2 */
+
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
*/
#if 1
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+++ /dev/null
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8540 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * sbc8540 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_66
-#define CONFIG_PCI_66
-#endif
-
-#define TSEC_DEBUG
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-
-#define CONFIG_SYS_TEXT_BASE 0xfffc0000
-
-
-#define CONFIG_CPM2 1 /* has CPM2 */
-
-#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
-#define CONFIG_MPC8540 1
-
-#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_PCI /* pci ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-#define CONFIG_ENV_OVERWRITE
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
-
-#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
- #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
-#else
- #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#undef CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
- defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
- defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
-
-/* DDR Setup */
-#define CONFIG_FSL_DDR1
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_SPD
-
-#if defined(CONFIG_MPC85xx_REV1)
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
-#endif
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
-#else /* Boot from real Flash */
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
-#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/* local bus definitions */
-#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
-#define CONFIG_SYS_OR2_PRELIM 0x00000000
-
-#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
-#else
- #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
-#endif
-#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
-
-#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
-#if 1
- #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
-#else
- #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
-#endif
-
-#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
-#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x20000000
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
-#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
-#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-
-/* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
-/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#if 0
-#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
-#else
-#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */
-#endif
-
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#if 0
-#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
-#else
-/* SBC8540 uses internal COMM controller */
-#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
-#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
-#endif
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-
-#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
-#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
-
-# define CONFIG_MPC85xx_TSEC1
-# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
-# define CONFIG_MII 1 /* MII PHY management */
-# define TSEC1_PHY_ADDR 25
-# define TSEC1_PHYIDX 0
-/* Options are: TSEC0 */
-# define CONFIG_ETHPRIME "TSEC0"
-
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
- #undef CONFIG_ETHER_NONE /* define if ether on something else */
- #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
- #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
- #if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
-
- #elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #endif /* CONFIG_ETHER_INDEX */
-
- #define CONFIG_MII /* MII PHY management */
- #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
- /*
- * GPIO pins used for bit-banged MII communications
- */
- #define MDIO_PORT 2 /* Port C */
- #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
- #define MDC_DECLARE MDIO_DECLARE
-
- #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
- #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
- #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
- #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
- #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
- #define MIIDELAY udelay(1)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if 0
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if 0
-/* XXX This doesn't work and I don't want to fix it */
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
- #define CONFIG_SYS_RAMBOOT
-#else
- #undef CONFIG_SYS_RAMBOOT
-#endif
-#endif
-
-/* Environment */
-#if !defined(CONFIG_SYS_RAMBOOT)
- #if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_ENV_IS_NOWHERE
- #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
- #define CONFIG_ENV_SIZE 0x2000
- #else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
- #endif
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
-/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_CMD_MII
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
- #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*Note: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
-# define CONFIG_HAS_ETH1
-# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
-# define CONFIG_HAS_ETH2
-# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
-#endif
-
-#define CONFIG_SERVERIP YourServerIP
-#define CONFIG_IPADDR YourTargetIP
-#define CONFIG_GATEWAYIP YourGatewayIP
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME SBC8560
-#define CONFIG_ROOTPATH "YourRootPath"
-#define CONFIG_BOOTFILE "YourImageName"
-
-#endif /* __CONFIG_H */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_LED 1 /* LED for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
--- /dev/null
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * T4240 QDS board configuration file
+ */
+#define CONFIG_T4240QDS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_T4240
+
+#define CONFIG_FSL_SATA_V2
+#define CONFIG_PCIE4
+
+#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
+
+#include "t4qds.h"
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_BOUNCE_BUFFER
+#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
+#define CONFIG_CMD_CBFS
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
/*-----------------------------------------------------------------------
* Video Configuration
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_SRIO2 /* SRIO port 2 */
-
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
--- /dev/null
+/*
+ * Copyright (C) 2012 Keymile AG
+ * Gerlando Falauto <gerlando.falauto@keymile.com>
+ *
+ * Based on km8321-common.h, see respective copyright notice for credits
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_KM8309_COMMON_H
+#define __CONFIG_KM8309_COMMON_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 family */
+#define CONFIG_QE 1 /* Has QE */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC830x 1 /* MPC830x family */
+#define CONFIG_MPC8309 1 /* MPC8309 CPU specific */
+
+#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
+#define CONFIG_CMD_DIAG 1
+
+/* include common defines/options for all 83xx Keymile boards */
+#include "km83xx-common.h"
+
+/* QE microcode/firmware address */
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+/* at end of uboot partition, before env */
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xF00B0000
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * System IO Config
+ */
+/* 0x14000180 SICR_1 */
+#define CONFIG_SYS_SICRL (0 \
+ | SICR_1_UART1_UART1RTS \
+ | SICR_1_I2C_CKSTOP \
+ | SICR_1_IRQ_A_IRQ \
+ | SICR_1_IRQ_B_IRQ \
+ | SICR_1_GPIO_A_GPIO \
+ | SICR_1_GPIO_B_GPIO \
+ | SICR_1_GPIO_C_GPIO \
+ | SICR_1_GPIO_D_GPIO \
+ | SICR_1_GPIO_E_GPIO \
+ | SICR_1_GPIO_F_GPIO \
+ | SICR_1_USB_A_UART2S \
+ | SICR_1_USB_B_UART2RTS \
+ | SICR_1_FEC1_FEC1 \
+ | SICR_1_FEC2_FEC2 \
+ )
+
+/* 0x00080400 SICR_2 */
+#define CONFIG_SYS_SICRH (0 \
+ | SICR_2_FEC3_FEC3 \
+ | SICR_2_HDLC1_A_HDLC1 \
+ | SICR_2_ELBC_A_LA \
+ | SICR_2_ELBC_B_LCLK \
+ | SICR_2_HDLC2_A_HDLC2 \
+ | SICR_2_USB_D_GPIO \
+ | SICR_2_PCI_PCI \
+ | SICR_2_HDLC1_B_HDLC1 \
+ | SICR_2_HDLC1_C_HDLC1 \
+ | SICR_2_HDLC2_B_GPIO \
+ | SICR_2_HDLC2_C_HDLC2 \
+ | SICR_2_QUIESCE_B \
+ )
+
+/* GPR_1 */
+#define CONFIG_SYS_GPR1 0x50008060
+
+#define CONFIG_SYS_GP1DIR 0x00000000
+#define CONFIG_SYS_GP1ODR 0x00000000
+#define CONFIG_SYS_GP2DIR 0xFF000000
+#define CONFIG_SYS_GP2ODR 0x00000000
+
+/*
+ * Hardware Reset Configuration Word
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+ HRCWL_DDR_TO_SCB_CLK_2X1 | \
+ HRCWL_CSB_TO_CLKIN_2X1 | \
+ HRCWL_CORE_TO_CSB_2X1 | \
+ HRCWL_CE_PLL_VCO_DIV_2 | \
+ HRCWL_CE_TO_PLL_1X3)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+ HRCWH_PCI_AGENT | \
+ HRCWH_PCI_ARBITER_DISABLE | \
+ HRCWH_CORE_ENABLE | \
+ HRCWH_FROM_0X00000100 | \
+ HRCWH_BOOTSEQ_DISABLE | \
+ HRCWH_SW_WATCHDOG_DISABLE | \
+ HRCWH_ROM_LOC_LOCAL_16BIT | \
+ HRCWH_BIG_ENDIAN | \
+ HRCWH_LALE_NORMAL)
+
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
+#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
+ SDRAM_CFG_32_BE | \
+ SDRAM_CFG_SREN | \
+ SDRAM_CFG_HSE)
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
+#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
+#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
+ (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
+
+#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
+ CSCONFIG_ODT_RD_NEVER | \
+ CSCONFIG_ODT_WR_ONLY_CURRENT | \
+ CSCONFIG_ROW_BIT_13 | \
+ CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_MODE 0x47860242
+#define CONFIG_SYS_DDR_MODE2 0x8080c000
+
+#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
+ (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
+ (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
+ (0 << TIMING_CFG0_WWT_SHIFT) | \
+ (0 << TIMING_CFG0_RRT_SHIFT) | \
+ (0 << TIMING_CFG0_WRT_SHIFT) | \
+ (0 << TIMING_CFG0_RWT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
+ (2 << TIMING_CFG1_WRTORD_SHIFT) | \
+ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
+ (3 << TIMING_CFG1_WRREC_SHIFT) | \
+ (7 << TIMING_CFG1_REFREC_SHIFT) | \
+ (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+ (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+ (3 << TIMING_CFG1_PRETOACT_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
+ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
+ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
+ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
+ (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
+ (5 << TIMING_CFG2_CPO_SHIFT))
+
+#define CONFIG_SYS_DDR_TIMING_3 0x00000000
+
+#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+
+/* EEprom support */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP 0x80000000
+#define CONFIG_SYS_LCRR_EADC 0x00010000
+#define CONFIG_SYS_LCRR_CLKDIV 0x00000002
+
+#define CONFIG_SYS_LBC_LBCR 0x00000000
+
+/*
+ * MMU Setup
+ */
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
+
+#endif /* __CONFIG_KM8309_COMMON_H */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
-#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
+#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define UEC_VERBOSE_DEBUG 1
#ifdef CONFIG_UEC_ETH1
+#if defined(CONFIG_MPC8309)
+#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
+#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
+#else
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
+#endif
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SH_I2C 1
+#define CONFIG_SH_I2C_8BIT
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS (2)
+#define CONFIG_SYS_MAX_I2C_BUS (5)
#define CONFIG_SYS_I2C_MODULE
#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE (0x7F)
#define CONFIG_SH_I2C_DATA_HIGH (4)
#define CONFIG_SH_I2C_DATA_LOW (5)
-#define CONFIG_SH_I2C_CLOCK (41666666)
+#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */
#define CONFIG_SH_I2C_BASE0 (0xE6820000)
#define CONFIG_SH_I2C_BASE1 (0xE6822000)
+#define CONFIG_SH_I2C_BASE2 (0xE6824000)
+#define CONFIG_SH_I2C_BASE3 (0xE6826000)
+#define CONFIG_SH_I2C_BASE4 (0xE6828000)
#endif /* __KZM9G_H */
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
-#define CONFIG_MMC_BOUNCE_BUFFER
+#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC830x 1 /* MPC830x family */
#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC_BOUNCE_BUFFER
+#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
-#define CONFIG_PXA_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define RTC 1 /* enable 32KHz osc */
#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
-#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MIPS32 /* MIPS32 CPU core */
+#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
-/*IP address is default used by Qemu*/
-#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
-#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */
-
#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_DHCP
#define CONFIG_DRIVER_NE2000
-#define CONFIG_DRIVER_NE2000_BASE (0xb4000300)
+#define CONFIG_DRIVER_NE2000_BASE 0xb4000300
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
-#define CONFIG_SYS_NS16550_COM1 (0xb40003f8)
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 0xb40003f8
+#define CONFIG_CONS_INDEX 1
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
-#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
-#define CONFIG_SYS_ATA_DATA_OFFSET (0)
-#define CONFIG_SYS_ATA_REG_OFFSET (0)
-#define CONFIG_SYS_ATA_BASE_ADDR (0xb4000000)
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
-#define CONFIG_SYS_IDE_MAXDEVICE (4)
+#define CONFIG_SYS_IDE_MAXDEVICE 4
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
/* Monitor Command Prompt */
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_MALLOC_LEN 128*1024
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x80800000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-
/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_FLASH_BASE 0xbfc00000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Address and size of Primary Environment Sector */
#define MEM_SIZE 128
-#undef CONFIG_MEMSIZE_IN_BYTES
-
#define CONFIG_LZMA
/*-----------------------------------------------------------------------
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 /* MIPS64 CPU core */
+#define CONFIG_QEMU_MIPS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "panic=1\0" \
+ "bootfile=/tftpboot/vmlinux\0" \
+ "load=tftp ffffffff80500000 ${u-boot}\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "bootp;bootelf"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000
+
+#define CONFIG_SYS_IDE_MAXDEVICE 4
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT "qemu-mips64el # "
+#else
+#define CONFIG_SYS_PROMPT "qemu-mips64 # "
+#endif
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_HZ 1000
+
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
+
+#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
+#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (192 << 10)
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE 0x8000
+
+#define CONFIG_ENV_OVERWRITE 1
+
+#define MEM_SIZE 128
+
+#define CONFIG_LZMA
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#endif /* __CONFIG_H */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+++ /dev/null
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * sbc8560 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_66
-#define CONFIG_PCI_66
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-
-#define CONFIG_SYS_TEXT_BASE 0xfffc0000
-
-
-#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
-#define CONFIG_MPC8560 1
-
-/* XXX flagging this as something I might want to delete */
-#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_PCI /* pci ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-#define CONFIG_ENV_OVERWRITE
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
-
-#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
- #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
-#else
- #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#undef CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
- defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
- defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
-
-/* DDR Setup */
-#define CONFIG_FSL_DDR1
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_SPD
-
-#if defined(CONFIG_MPC85xx_REV1)
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
-#endif
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
-#else /* Boot from real Flash */
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
-#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/* local bus definitions */
-#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
-#define CONFIG_SYS_OR2_PRELIM 0x00000000
-
-#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
-#else
- #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
-#endif
-#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
-
-#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
-#if 1
- #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
-#else
- #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
-#endif
-
-#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
-#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x20000000
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
-#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
-#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-
-/* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
-/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-
-#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
-#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#ifdef CONFIG_TSEC_ENET
-
-#ifndef CONFIG_MII
-#define CONFIG_MII 1 /* MII PHY management */
-#endif
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0x19
-#define TSEC2_PHY_ADDR 0x1a
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
- #undef CONFIG_ETHER_NONE /* define if ether on something else */
- #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
- #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
- #if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
-
- #elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #endif /* CONFIG_ETHER_INDEX */
-
- #define CONFIG_MII /* MII PHY management */
- #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
- /*
- * GPIO pins used for bit-banged MII communications
- */
- #define MDIO_PORT 2 /* Port C */
- #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
- #define MDC_DECLARE MDIO_DECLARE
-
- #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
- #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
- #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
- #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
- #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
- #define MIIDELAY udelay(1)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if 0
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if 0
-/* XXX This doesn't work and I don't want to fix it */
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
- #define CONFIG_SYS_RAMBOOT
-#else
- #undef CONFIG_SYS_RAMBOOT
-#endif
-#endif
-
-/* Environment */
-#if !defined(CONFIG_SYS_RAMBOOT)
- #if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_ENV_IS_NOWHERE
- #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
- #define CONFIG_ENV_SIZE 0x2000
- #else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
- #endif
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
-/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_CMD_MII
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-/* You can compile in a MAC address and your custom net settings by using
- * the following syntax. Your board should be marked with the assigned
- * MAC addresses directly on it.
- *
- * #define CONFIG_ETHADDR de:ad:be:ef:00:00
- * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s!
- * #define CONFIG_SERVERIP <server ip>
- * #define CONFIG_IPADDR <board ip>
- * #define CONFIG_GATEWAYIP <gateway ip>
- * #define CONFIG_NETMASK <your netmask>
- */
-
-#define CONFIG_HOSTNAME SBC8560
-#define CONFIG_ROOTPATH "/home/ppc"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=sbc8560.dtb\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
/*
* High Level Configuration Options
*/
-#define CONFIG_SUVD3 /* SUVD3 board specific */
-#define CONFIG_HOSTNAME suvd3
-#define CONFIG_KM_BOARD_NAME "suvd3"
+/* This needs to be set prior to including km/km83xx-common.h */
#define CONFIG_SYS_TEXT_BASE 0xF0000000
+#if defined(CONFIG_SUVD3) /* SUVD3 board specific */
+#define CONFIG_HOSTNAME suvd3
+#define CONFIG_KM_BOARD_NAME "suvd3"
/* include common defines/options for all 8321 Keymile boards */
#include "km/km8321-common.h"
+#elif defined(CONFIG_KMVECT1) /* VECT1 board specific */
+#define CONFIG_HOSTNAME kmvect1
+#define CONFIG_KM_BOARD_NAME "kmvect1"
+/* include common defines/options for all 8309 Keymile boards */
+#include "km/km8309-common.h"
+#else
+#error Supported boards are: SUVD3, KMVECT1
+#endif
#define CONFIG_SYS_APP1_BASE 0xA0000000
-#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
+#define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */
#define CONFIG_SYS_APP2_BASE 0xB0000000
-#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
+#define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
--- /dev/null
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Corenet DS style board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#endif
+
+#define CONFIG_CMD_REGINFO
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E6500
+#define CONFIG_E500 /* BOOKE e500 family */
+#define CONFIG_E500MC /* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
+#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
+#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
+#define CONFIG_MP /* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC /* Enable IFC Support */
+#define CONFIG_PCI /* Enable PCI/PCIE */
+#define CONFIG_PCIE1 /* PCIE controler 1 */
+#define CONFIG_PCIE2 /* PCIE controler 2 */
+#define CONFIG_PCIE3 /* PCIE controler 3 */
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+#define CONFIG_SRIO2 /* SRIO port 2 */
+
+#define CONFIG_FSL_LAW /* Use common FSL init code */
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 10000000
+#define CONFIG_ENV_SPI_MODE 0
+#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
+#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
+
+
+
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#if 0
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
+#endif
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
+
+/*
+ * Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR 0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM 0
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL 4
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+
+#define CONFIG_DDR_SPD
+#define CONFIG_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x51
+#define SPD_EEPROM_ADDRESS2 0x52
+#define SPD_EEPROM_ADDRESS3 0x53
+#define SPD_EEPROM_ADDRESS4 0x54
+#define SPD_EEPROM_ADDRESS5 0x55
+#define SPD_EEPROM_ADDRESS6 0x56
+#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
+#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE 0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
+#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+ CSPR_PORT_SIZE_16 | \
+ CSPR_MSEL_NOR | \
+ CSPR_V)
+#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+
+#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \
+ FTIM0_NOR_TEADC(0x01) | \
+ FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
+ FTIM1_NOR_TRAD_NOR(0x1A) |\
+ FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \
+ FTIM2_NOR_TCH(0x0E) | \
+ FTIM2_NOR_TWPH(0x0E) | \
+ FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3 0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
+ + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS /* use common QIXIS code */
+#define QIXIS_BASE 0xffdf0000
+#define QIXIS_LBMAP_SWITCH 6
+#define QIXIS_LBMAP_MASK 0x0f
+#define QIXIS_LBMAP_SHIFT 0
+#define QIXIS_LBMAP_DFLTBANK 0x00
+#define QIXIS_LBMAP_ALTBANK 0x04
+#define QIXIS_RST_CTL_RESET 0x83
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS QIXIS_BASE
+#endif
+
+#define CONFIG_SYS_CSPR3_EXT (0xf)
+#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 \
+ | CSPR_MSEL_GPCM \
+ | CSPR_V)
+#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3 0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
+ FTIM0_GPCM_TEADC(0x0e) | \
+ FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
+ FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
+ FTIM2_GPCM_TCH(0x0) | \
+ FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3 0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE 0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
+#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+ | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+ | CSPR_MSEL_NAND /* MSEL = NAND */ \
+ | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
+ | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
+ FTIM0_NAND_TWP(0x18) | \
+ FTIM0_NAND_TWCHT(0x07) | \
+ FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
+ FTIM1_NAND_TWBE(0x39) | \
+ FTIM1_NAND_TRR(0x0e) | \
+ FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
+ FTIM2_NAND_TREH(0x0a) | \
+ FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3 0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW 11
+
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+ ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_OFFSET 0x118000
+#define CONFIG_SYS_I2C2_OFFSET 0x118100
+#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define I2C_MUX_CH_DEFAULT 0x8
+#define I2C_MUX_CH_VSC3316_FS 0xc
+#define I2C_MUX_CH_VSC3316_BS 0xd
+#define VSC3316_FSM_TX_ADDR 0x70
+#define VSC3316_FSM_RX_ADDR 0x71
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE 0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS 50
+#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS 50
+#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+#define CONFIG_SYS_INTERLAKEN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
+#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
+#define XFI_CARD_PORT1_PHY_ADDR 0x1 /* tmp, FIXME below addr */
+#define XFI_CARD_PORT2_PHY_ADDR 0x2
+#define XFI_CARD_PORT3_PHY_ADDR 0x3
+#define XFI_CARD_PORT4_PHY_ADDR 0x4
+#define QSGMII_CARD_PHY_ADDR 0x5
+#define FM1_10GEC1_PHY_ADDR 0x6
+#define FM1_10GEC2_PHY_ADDR 0x7
+#define FM2_10GEC1_PHY_ADDR 0x8
+#define FM2_10GEC2_PHY_ADDR 0x9
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif /* CONFIG_PCI */
+
+/* SATA */
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE 2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
+
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_ETHPRIME "FM1@DTSEC1"
+#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#define CONFIG_HAS_FSL_DR_USB
+
+#define CONFIG_MMC
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH "/opt/nfsroot"
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR 1000000
+
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE 115200
+
+#define __USB_PHY_TYPE utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ctlr_intlv=3way_4KB," \
+ "bank_intlv=auto;" \
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot && " \
+ "protect off $ubootaddr +$filesize && " \
+ "erase $ubootaddr +$filesize && " \
+ "cp.b $loadaddr $ubootaddr $filesize && " \
+ "protect on $ubootaddr +$filesize && " \
+ "cmp.b $loadaddr $ubootaddr $filesize\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=t4240qds/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=t4240qds/t4240qds.dtb\0" \
+ "bdev=sda3\0" \
+ "c=ffe\0"
+
+/* For emulation this causes u-boot to jump to the start of the proof point
+ app code automatically */
+#define CONFIG_PROOF_POINTS \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x29000000 - - -;" \
+ "cpu 2 release 0x29000000 - - -;" \
+ "cpu 3 release 0x29000000 - - -;" \
+ "cpu 4 release 0x29000000 - - -;" \
+ "cpu 5 release 0x29000000 - - -;" \
+ "cpu 6 release 0x29000000 - - -;" \
+ "cpu 7 release 0x29000000 - - -;" \
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT \
+ "setenv bootargs config-addr=0x60000000; " \
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "cpu 1 release 0x01000000 - - -;" \
+ "cpu 2 release 0x01000000 - - -;" \
+ "cpu 3 release 0x01000000 - - -;" \
+ "cpu 4 release 0x01000000 - - -;" \
+ "cpu 5 release 0x01000000 - - -;" \
+ "cpu 6 release 0x01000000 - - -;" \
+ "cpu 7 release 0x01000000 - - -;" \
+ "go 0x01000000"
+
+#define CONFIG_LINUX \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "setenv ramdiskaddr 0x02000000;" \
+ "setenv fdtaddr 0x00c00000;" \
+ "setenv loadaddr 0x1000000;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT \
+ "setenv bootargs root=/dev/$bdev rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND \
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
#ifdef CONFIG_MMC
-#define CONFIG_PXA_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_CMD_MMC
#define CONFIG_SYS_MMC_BASE 0xF0000000
#endif
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
--- /dev/null
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __DWMMC_HW_H
+#define __DWMMC_HW_H
+
+#include <asm/io.h>
+#include <mmc.h>
+
+#define DWMCI_CTRL 0x000
+#define DWMCI_PWREN 0x004
+#define DWMCI_CLKDIV 0x008
+#define DWMCI_CLKSRC 0x00C
+#define DWMCI_CLKENA 0x010
+#define DWMCI_TMOUT 0x014
+#define DWMCI_CTYPE 0x018
+#define DWMCI_BLKSIZ 0x01C
+#define DWMCI_BYTCNT 0x020
+#define DWMCI_INTMASK 0x024
+#define DWMCI_CMDARG 0x028
+#define DWMCI_CMD 0x02C
+#define DWMCI_RESP0 0x030
+#define DWMCI_RESP1 0x034
+#define DWMCI_RESP2 0x038
+#define DWMCI_RESP3 0x03C
+#define DWMCI_MINTSTS 0x040
+#define DWMCI_RINTSTS 0x044
+#define DWMCI_STATUS 0x048
+#define DWMCI_FIFOTH 0x04C
+#define DWMCI_CDETECT 0x050
+#define DWMCI_WRTPRT 0x054
+#define DWMCI_GPIO 0x058
+#define DWMCI_TCMCNT 0x05C
+#define DWMCI_TBBCNT 0x060
+#define DWMCI_DEBNCE 0x064
+#define DWMCI_USRID 0x068
+#define DWMCI_VERID 0x06C
+#define DWMCI_HCON 0x070
+#define DWMCI_UHS_REG 0x074
+#define DWMCI_BMOD 0x080
+#define DWMCI_PLDMND 0x084
+#define DWMCI_DBADDR 0x088
+#define DWMCI_IDSTS 0x08C
+#define DWMCI_IDINTEN 0x090
+#define DWMCI_DSCADDR 0x094
+#define DWMCI_BUFADDR 0x098
+#define DWMCI_DATA 0x200
+
+/* Interrupt Mask register */
+#define DWMCI_INTMSK_ALL 0xffffffff
+#define DWMCI_INTMSK_RE (1 << 1)
+#define DWMCI_INTMSK_CDONE (1 << 2)
+#define DWMCI_INTMSK_DTO (1 << 3)
+#define DWMCI_INTMSK_TXDR (1 << 4)
+#define DWMCI_INTMSK_RXDR (1 << 5)
+#define DWMCI_INTMSK_DCRC (1 << 7)
+#define DWMCI_INTMSK_RTO (1 << 8)
+#define DWMCI_INTMSK_DRTO (1 << 9)
+#define DWMCI_INTMSK_HTO (1 << 10)
+#define DWMCI_INTMSK_FRUN (1 << 11)
+#define DWMCI_INTMSK_HLE (1 << 12)
+#define DWMCI_INTMSK_SBE (1 << 13)
+#define DWMCI_INTMSK_ACD (1 << 14)
+#define DWMCI_INTMSK_EBE (1 << 15)
+
+/* Raw interrupt Regsiter */
+#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
+ DWMCI_INTMSK_FRUN | DWMCI_INTMSK_EBE | DWMCI_INTMSK_DCRC)
+#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+/* CTRL register */
+#define DWMCI_CTRL_RESET (1 << 0)
+#define DWMCI_CTRL_FIFO_RESET (1 << 1)
+#define DWMCI_CTRL_DMA_RESET (1 << 2)
+#define DWMCI_DMA_EN (1 << 5)
+#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
+#define DWMCI_IDMAC_EN (1 << 25)
+#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
+ DWMCI_CTRL_DMA_RESET)
+
+/* CMD register */
+#define DWMCI_CMD_RESP_EXP (1 << 6)
+#define DWMCI_CMD_RESP_LENGTH (1 << 7)
+#define DWMCI_CMD_CHECK_CRC (1 << 8)
+#define DWMCI_CMD_DATA_EXP (1 << 9)
+#define DWMCI_CMD_RW (1 << 10)
+#define DWMCI_CMD_SEND_STOP (1 << 12)
+#define DWMCI_CMD_ABORT_STOP (1 << 14)
+#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
+#define DWMCI_CMD_UPD_CLK (1 << 21)
+#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
+#define DWMCI_CMD_START (1 << 31)
+
+/* CLKENA register */
+#define DWMCI_CLKEN_ENABLE (1 << 0)
+#define DWMCI_CLKEN_LOW_PWR (1 << 16)
+
+/* Card-type registe */
+#define DWMCI_CTYPE_1BIT 0
+#define DWMCI_CTYPE_4BIT (1 << 0)
+#define DWMCI_CTYPE_8BIT (1 << 16)
+
+/* Status Register */
+#define DWMCI_BUSY (1 << 9)
+
+/* FIFOTH Register */
+#define MSIZE(x) ((x) << 28)
+#define RX_WMARK(x) ((x) << 16)
+#define TX_WMARK(x) (x)
+
+#define DWMCI_IDMAC_OWN (1 << 31)
+#define DWMCI_IDMAC_CH (1 << 4)
+#define DWMCI_IDMAC_FS (1 << 3)
+#define DWMCI_IDMAC_LD (1 << 2)
+
+/* Bus Mode Register */
+#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
+#define DWMCI_BMOD_IDMAC_FB (1 << 1)
+#define DWMCI_BMOD_IDMAC_EN (1 << 7)
+
+struct dwmci_host {
+ char *name;
+ void *ioaddr;
+ unsigned int quirks;
+ unsigned int caps;
+ unsigned int version;
+ unsigned int clock;
+ unsigned int bus_hz;
+ int dev_index;
+ int buswidth;
+ u32 fifoth_val;
+ struct mmc *mmc;
+
+ void (*clksel)(struct dwmci_host *host);
+ unsigned int (*mmc_clk)(int dev_index);
+};
+
+struct dwmci_idmac {
+ u32 flags;
+ u32 cnt;
+ u32 addr;
+ u32 next_addr;
+};
+
+static inline void dwmci_writel(struct dwmci_host *host, int reg, u32 val)
+{
+ writel(val, host->ioaddr + reg);
+}
+
+static inline void dwmci_writew(struct dwmci_host *host, int reg, u16 val)
+{
+ writew(val, host->ioaddr + reg);
+}
+
+static inline void dwmci_writeb(struct dwmci_host *host, int reg, u8 val)
+{
+ writeb(val, host->ioaddr + reg);
+}
+static inline u32 dwmci_readl(struct dwmci_host *host, int reg)
+{
+ return readl(host->ioaddr + reg);
+}
+
+static inline u16 dwmci_readw(struct dwmci_host *host, int reg)
+{
+ return readw(host->ioaddr + reg);
+}
+
+static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
+{
+ return readb(host->ioaddr + reg);
+}
+
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
+#endif /* __DWMMC_HW_H */
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freqFMan[CONFIG_SYS_NUM_FMAN];
#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ unsigned long freqQMAN;
+#endif
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freqPME;
#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+env_t environment __PPCENV__ = {
+ ENV_CRC, /* CRC Sum */
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+ 1, /* Flags: valid */
+#endif
+ {
+#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
+static char default_environment[] = {
+#else
+const uchar default_environment[] = {
+#endif
+#ifdef CONFIG_BOOTARGS
+ "bootargs=" CONFIG_BOOTARGS "\0"
+#endif
+#ifdef CONFIG_BOOTCOMMAND
+ "bootcmd=" CONFIG_BOOTCOMMAND "\0"
+#endif
+#ifdef CONFIG_RAMBOOTCOMMAND
+ "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
+#endif
+#ifdef CONFIG_NFSBOOTCOMMAND
+ "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
+#endif
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+ "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
+#endif
+#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
+#endif
+#ifdef CONFIG_LOADS_ECHO
+ "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
+#endif
+#ifdef CONFIG_ETHADDR
+ "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
+#endif
+#ifdef CONFIG_ETH1ADDR
+ "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH2ADDR
+ "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH3ADDR
+ "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH4ADDR
+ "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH5ADDR
+ "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
+#endif
+#ifdef CONFIG_ETHPRIME
+ "ethprime=" CONFIG_ETHPRIME "\0"
+#endif
+#ifdef CONFIG_IPADDR
+ "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
+#endif
+#ifdef CONFIG_SERVERIP
+ "serverip=" __stringify(CONFIG_SERVERIP) "\0"
+#endif
+#ifdef CONFIG_SYS_AUTOLOAD
+ "autoload=" CONFIG_SYS_AUTOLOAD "\0"
+#endif
+#ifdef CONFIG_PREBOOT
+ "preboot=" CONFIG_PREBOOT "\0"
+#endif
+#ifdef CONFIG_ROOTPATH
+ "rootpath=" CONFIG_ROOTPATH "\0"
+#endif
+#ifdef CONFIG_GATEWAYIP
+ "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
+#endif
+#ifdef CONFIG_NETMASK
+ "netmask=" __stringify(CONFIG_NETMASK) "\0"
+#endif
+#ifdef CONFIG_HOSTNAME
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
+#endif
+#ifdef CONFIG_BOOTFILE
+ "bootfile=" CONFIG_BOOTFILE "\0"
+#endif
+#ifdef CONFIG_LOADADDR
+ "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
+#endif
+#ifdef CONFIG_CLOCKS_IN_MHZ
+ "clocks_in_mhz=1\0"
+#endif
+#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
+ "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
+#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
+ "arch=" CONFIG_SYS_ARCH "\0"
+ "cpu=" CONFIG_SYS_CPU "\0"
+ "board=" CONFIG_SYS_BOARD "\0"
+#ifdef CONFIG_SYS_VENDOR
+ "vendor=" CONFIG_SYS_VENDOR "\0"
+#endif
+#ifdef CONFIG_SYS_SOC
+ "soc=" CONFIG_SYS_SOC "\0"
+#endif
+#endif
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
+ CONFIG_EXTRA_ENV_SETTINGS
+#endif
+ "\0"
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+ }
+#endif
+};
/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
FM1_DTSEC3,
FM1_DTSEC4,
FM1_DTSEC5,
+ FM1_DTSEC6,
+ FM1_DTSEC9,
+ FM1_DTSEC10,
FM1_10GEC1,
+ FM1_10GEC2,
FM2_DTSEC1,
FM2_DTSEC2,
FM2_DTSEC3,
FM2_DTSEC4,
FM2_DTSEC5,
+ FM2_DTSEC6,
+ FM2_DTSEC9,
+ FM2_DTSEC10,
FM2_10GEC1,
+ FM2_10GEC2,
NUM_FM_PORTS,
};
FM_ETH_10G_E,
};
+#ifdef CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
+#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
+#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#else
#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
+#endif
#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
.phy_regs = (void *)pregs, \
.enet_if = PHY_INTERFACE_MODE_NONE, \
+#ifdef CONFIG_SYS_FMAN_V3
+#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
+{ \
+ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
+ .index = idx, \
+ .num = n - 1, \
+ .type = FM_ETH_1G_E, \
+ .port = FM##idx##_DTSEC##n, \
+ .rx_port_id = RX_PORT_1G_BASE + n - 1, \
+ .tx_port_id = TX_PORT_1G_BASE + n - 1, \
+ .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ offsetof(struct ccsr_fman, memac[n-1]),\
+}
+
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{ \
+ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ .index = idx, \
+ .num = n - 1, \
+ .type = FM_ETH_10G_E, \
+ .port = FM##idx##_10GEC##n, \
+ .rx_port_id = RX_PORT_10G_BASE + n - 1, \
+ .tx_port_id = TX_PORT_10G_BASE + n - 1, \
+ .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ offsetof(struct ccsr_fman, memac[n-1]),\
+}
+#else
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, mac_10g[n-1]),\
}
-
+#endif
struct fm_eth_info {
u8 enabled;
u8 fm;
char *name;
};
+struct memac_mdio_info {
+ struct memac_mdio_controller *regs;
+ char *name;
+};
+
int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
+int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
+
int fm_standard_init(bd_t *bis);
void fman_enet_init(void);
void fdt_fixup_fman_ethernet(void *fdt);
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
* Jun-jie Zhang <b18070@freescale.com>
* Mingkai Hu <Mingkai.hu@freescale.com>
*
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
u16 value);
+int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum, u16 value);
+int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+ int regnum);
struct fsl_pq_mdio_info {
struct tsec_mii_mng *regs;
#define I8042_STATUS_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard status read */
#define I8042_COMMAND_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard ctrl write */
+enum {
+ /* Output register (I8042_DATA_REG) has data for system */
+ I8042_STATUS_OUT_DATA = 1 << 0,
+ I8042_STATUS_IN_DATA = 1 << 1,
+};
+
#define KBD_US 0 /* default US layout */
#define KBD_GER 1 /* german layout */
/* exports */
+/**
+ * Flush all buffer from keyboard controller to host.
+ */
+void i8042_flush(void);
+
+/**
+ * Disables the keyboard so that key strokes no longer generate scancodes to
+ * the host.
+ *
+ * @return 0 if ok, -1 if keyboard input was found while disabling
+ */
+int i8042_disable(void);
+
int i8042_kbd_init(void);
int i8042_tstc(void);
int i8042_getc(void);
#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
#define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+extern ulong ide_bus_offset[];
#ifdef CONFIG_IDE_LED
#ifdef CONFIG_SYS_64BIT_LBA
typedef uint64_t lbaint_t;
+#define LBAF "%llx"
#else
typedef ulong lbaint_t;
+#define LBAF "%lx"
#endif
/*
ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer);
ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer);
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit(void);
+#endif
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+int ide_init_postreset(void);
+#endif
+
#if defined(CONFIG_OF_IDE_FIXUP)
int ide_device_present(int dev);
#endif
void ide_read_data(int dev, ulong *sect_buf, int words);
void ide_write_data(int dev, ulong *sect_buf, int words);
#endif
+
+/*
+ * I/O function overrides
+ */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words);
+void ide_input_data(int dev, ulong *sect_buf, int words);
+void ide_output_data(int dev, const ulong *sect_buf, int words);
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
+
#endif /* _IDE_H */
#define FIT_HASH_NODENAME "hash"
#define FIT_ALGO_PROP "algo"
#define FIT_VALUE_PROP "value"
+#define FIT_IGNORE_PROP "uboot-ignore"
/* image node */
#define FIT_DATA_PROP "data"
int fit_image_hash_get_algo(const void *fit, int noffset, char **algo);
int fit_image_hash_get_value(const void *fit, int noffset, uint8_t **value,
int *value_len);
+#ifndef USE_HOSTCC
+int fit_image_hash_get_ignore(const void *fit, int noffset, int *ignore);
+#endif
int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
int fit_set_hashes(void *fit);
* @param config Input state
* @param keycode List of key codes to examine
* @param num_keycodes Number of key codes
+ * @return number of ascii characters sent, or 0 if none, or -1 for an
+ * internal error
*/
int input_send_keycodes(struct input_config *config, int keycode[], int count);
const void *val, int len);
/**
- * fdt_setprop_inplace_cell - change the value of a single-cell property
+ * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
- * @val: cell (32-bit integer) value to replace the property with
+ * @val: 32-bit integer value to replace the property with
*
- * fdt_setprop_inplace_cell() replaces the value of a given property
- * with the 32-bit integer cell value in val, converting val to
- * big-endian if necessary. This function cannot change the size of a
- * property, and so will only work if the property already exists and
- * has length 4.
+ * fdt_setprop_inplace_u32() replaces the value of a given property
+ * with the 32-bit integer value in val, converting val to big-endian
+ * if necessary. This function cannot change the size of a property,
+ * and so will only work if the property already exists and has length
+ * 4.
*
* This function will alter only the bytes in the blob which contain
* the given property value, and will not alter or move any other part
* returns:
* 0, on success
* -FDT_ERR_NOSPACE, if the property's length is not equal to 4
- * -FDT_ERR_NOTFOUND, node does not have the named property
+ * -FDT_ERR_NOTFOUND, node does not have the named property
* -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
* -FDT_ERR_BADMAGIC,
* -FDT_ERR_BADVERSION,
* -FDT_ERR_BADSTRUCTURE,
* -FDT_ERR_TRUNCATED, standard meanings
*/
-static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
- const char *name, uint32_t val)
+static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
+ const char *name, uint32_t val)
{
val = cpu_to_fdt32(val);
return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
}
+/**
+ * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 64-bit integer value to replace the property with
+ *
+ * fdt_setprop_inplace_u64() replaces the value of a given property
+ * with the 64-bit integer value in val, converting val to big-endian
+ * if necessary. This function cannot change the size of a property,
+ * and so will only work if the property already exists and has length
+ * 8.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, if the property's length is not equal to 8
+ * -FDT_ERR_NOTFOUND, node does not have the named property
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
+ const char *name, uint64_t val)
+{
+ val = cpu_to_fdt64(val);
+ return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_setprop_inplace_cell - change the value of a single-cell property
+ *
+ * This is an alternative name for fdt_setprop_inplace_u32()
+ */
+static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
+ const char *name, uint32_t val)
+{
+ return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val);
+}
+
/**
* fdt_nop_property - replace a property with nop tags
* @fdt: pointer to the device tree blob
int fdt_finish_reservemap(void *fdt);
int fdt_begin_node(void *fdt, const char *name);
int fdt_property(void *fdt, const char *name, const void *val, int len);
-static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
+static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
{
val = cpu_to_fdt32(val);
return fdt_property(fdt, name, &val, sizeof(val));
}
+static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
+{
+ val = cpu_to_fdt64(val);
+ return fdt_property(fdt, name, &val, sizeof(val));
+}
+static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
+{
+ return fdt_property_u32(fdt, name, val);
+}
#define fdt_property_string(fdt, name, str) \
fdt_property(fdt, name, str, strlen(str)+1)
int fdt_end_node(void *fdt);
/* Read-write functions */
/**********************************************************************/
+int fdt_create_empty_tree(void *buf, int bufsize);
int fdt_open_into(const void *fdt, void *buf, int bufsize);
int fdt_pack(void *fdt);
const void *val, int len);
/**
- * fdt_setprop_cell - set a property to a single cell value
+ * fdt_setprop_u32 - set a property to a 32-bit integer
* @fdt: pointer to the device tree blob
* @nodeoffset: offset of the node whose property to change
* @name: name of the property to change
* @val: 32-bit integer value for the property (native endian)
*
- * fdt_setprop_cell() sets the value of the named property in the
- * given node to the given cell value (converting to big-endian if
+ * fdt_setprop_u32() sets the value of the named property in the given
+ * node to the given 32-bit integer value (converting to big-endian if
* necessary), or creates a new property with that value if it does
* not already exist.
*
* -FDT_ERR_BADLAYOUT,
* -FDT_ERR_TRUNCATED, standard meanings
*/
-static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
- uint32_t val)
+static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
+ uint32_t val)
{
val = cpu_to_fdt32(val);
return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
}
+/**
+ * fdt_setprop_u64 - set a property to a 64-bit integer
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 64-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_u64() sets the value of the named property in the given
+ * node to the given 64-bit integer value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ * contain the new property value
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
+ uint64_t val)
+{
+ val = cpu_to_fdt64(val);
+ return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_setprop_cell - set a property to a single cell value
+ *
+ * This is an alternative name for fdt_setprop_u32()
+ */
+static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
+ uint32_t val)
+{
+ return fdt_setprop_u32(fdt, nodeoffset, name, val);
+}
+
/**
* fdt_setprop_string - set a property to a string value
* @fdt: pointer to the device tree blob
#define fdt_setprop_string(fdt, nodeoffset, name, str) \
fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+/**
+ * fdt_appendprop - append to or create a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to append to
+ * @val: pointer to data to append to the property value
+ * @len: length of the data to append to the property value
+ *
+ * fdt_appendprop() appends the value to the named property in the
+ * given node, creating the property if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ * contain the new property value
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
+ const void *val, int len);
+
+/**
+ * fdt_appendprop_u32 - append a 32-bit integer value to a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value to append to the property (native endian)
+ *
+ * fdt_appendprop_u32() appends the given 32-bit integer value
+ * (converting to big-endian if necessary) to the value of the named
+ * property in the given node, or creates a new property with that
+ * value if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ * contain the new property value
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
+ const char *name, uint32_t val)
+{
+ val = cpu_to_fdt32(val);
+ return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_appendprop_u64 - append a 64-bit integer value to a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 64-bit integer value to append to the property (native endian)
+ *
+ * fdt_appendprop_u64() appends the given 64-bit integer value
+ * (converting to big-endian if necessary) to the value of the named
+ * property in the given node, or creates a new property with that
+ * value if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ * contain the new property value
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
+ const char *name, uint64_t val)
+{
+ val = cpu_to_fdt64(val);
+ return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_appendprop_cell - append a single cell value to a property
+ *
+ * This is an alternative name for fdt_appendprop_u32()
+ */
+static inline int fdt_appendprop_cell(void *fdt, int nodeoffset,
+ const char *name, uint32_t val)
+{
+ return fdt_appendprop_u32(fdt, nodeoffset, name, val);
+}
+
+/**
+ * fdt_appendprop_string - append a string to a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value to append to the property
+ *
+ * fdt_appendprop_string() appends the given string to the value of
+ * the named property in the given node, or creates a new property
+ * with that value if it does not already exist.
+ *
+ * This function may insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ * 0, on success
+ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ * contain the new property value
+ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_BADMAGIC,
+ * -FDT_ERR_BADVERSION,
+ * -FDT_ERR_BADSTATE,
+ * -FDT_ERR_BADSTRUCTURE,
+ * -FDT_ERR_BADLAYOUT,
+ * -FDT_ERR_TRUNCATED, standard meanings
+ */
+#define fdt_appendprop_string(fdt, nodeoffset, name, str) \
+ fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
/**
* fdt_delprop - delete a property
* @fdt: pointer to the device tree blob
--- /dev/null
+/*
+ * include/linker_lists.h
+ *
+ * Implementation of linker-generated arrays
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#ifndef __LINKER_LISTS_H__
+#define __LINKER_LISTS_H__
+
+/**
+ * ll_entry_declare() - Declare linker-generated array entry
+ * @_type: Data type of the entry
+ * @_name: Name of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots, for name concatenation)
+ * @_section_d: Subsection of u_boot_list in which this entry is placed
+ * (with dots, for section concatenation)
+ *
+ * This macro declares a variable that is placed into a linker-generated
+ * array. This is a basic building block for more advanced use of linker-
+ * generated arrays. The user is expected to build their own macro wrapper
+ * around this one.
+ *
+ * A variable declared using this macro must be compile-time initialized
+ * and is as such placed into subsection of special section, .u_boot_list.
+ * The subsection is specified by the _section_[u,d] parameter, see below.
+ * The base name of the variable is _name, yet the actual variable is
+ * declared as concatenation of
+ *
+ * %_u_boot_list_ + @_section_u + _ + @_name
+ *
+ * which ensures name uniqueness. This variable shall never be refered
+ * directly though.
+ *
+ * Special precaution must be made when using this macro:
+ * 1) The _type must not contain the "static" keyword, otherwise the entry
+ * is not generated.
+ *
+ * 2) The @_section_u and @_section_d variables must match, the only difference
+ * is that in @_section_u is every dot "." character present in @_section_d
+ * replaced by a single underscore "_" character in @_section_u. The actual
+ * purpose of these parameters is to select proper subsection in the global
+ * .u_boot_list section.
+ *
+ * 3) In case a section is declared that contains some array elements AND a
+ * subsection of this section is declared and contains some elements, it is
+ * imperative that the elements are of the same type.
+ *
+ * 4) In case an outer section is declared that contains some array elements
+ * AND am inner subsection of this section is declared and contains some
+ * elements, then when traversing the outer section, even the elements of
+ * the inner sections are present in the array.
+ *
+ * Example:
+ * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = {
+ * .x = 3,
+ * .y = 4,
+ * };
+ */
+#define ll_entry_declare(_type, _name, _section_u, _section_d) \
+ _type _u_boot_list_##_section_u##_##_name __attribute__(( \
+ unused, aligned(4), \
+ section(".u_boot_list."#_section_d"."#_name)))
+
+/**
+ * ll_entry_start() - Point to first entry of linker-generated array
+ * @_type: Data type of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots)
+ *
+ * This function returns (_type *) pointer to the very first entry of a
+ * linker-generated array placed into subsection of .u_boot_list section
+ * specified by _section_u argument.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_start(_type, _section_u) \
+ ({ \
+ extern _type _u_boot_list_##_section_u##__start; \
+ _type *_ll_result = &_u_boot_list_##_section_u##__start;\
+ _ll_result; \
+ })
+
+/**
+ * ll_entry_count() - Return the number of elements in linker-generated array
+ * @_type: Data type of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots)
+ *
+ * This function returns the number of elements of a linker-generated array
+ * placed into subsection of .u_boot_list section specified by _section_u
+ * argument. The result is of an unsigned int type.
+ *
+ * Example:
+ * int i;
+ * const unsigned int count = ll_entry_count(struct my_sub_cmd, cmd_sub);
+ * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ * for (i = 0; i < count; i++, msc++)
+ * printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y);
+ */
+#define ll_entry_count(_type, _section_u) \
+ ({ \
+ extern _type _u_boot_list_##_section_u##__start; \
+ extern _type _u_boot_list_##_section_u##__end; \
+ unsigned int _ll_result = \
+ &_u_boot_list_##_section_u##__end - \
+ &_u_boot_list_##_section_u##__start; \
+ _ll_result; \
+ })
+
+
+/**
+ * ll_entry_get() - Retrieve entry from linker-generated array by name
+ * @_type: Data type of the entry
+ * @_name: Name of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots)
+ *
+ * This function returns a pointer to a particular entry in LG-array
+ * identified by the subsection of u_boot_list where the entry resides
+ * and it's name.
+ *
+ * Example:
+ * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = {
+ * .x = 3,
+ * .y = 4,
+ * };
+ * ...
+ * struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_get(_type, _name, _section_u) \
+ ({ \
+ extern _type _u_boot_list_##_section_u##_##_name; \
+ _type *_ll_result = &_u_boot_list_##_section_u##_##_name;\
+ _ll_result; \
+ })
+
+#endif /* __LINKER_LISTS_H__ */
#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
#define SPR_8308 0x8100
+#define SPR_8309 0x8110
#define SPR_831X_FAMILY 0x80B
#define SPR_8311 0x80B2
#define SPR_8313 0x80B0
#define SICRH_TSOBI1_V2P5 (1 << 1)
#define SICRH_TSOBI2_V3P3 (0 << 0)
#define SICRH_TSOBI2_V2P5 (1 << 0)
+
+#elif defined(CONFIG_MPC8309)
+/* SICR_1 */
+#define SICR_1_UART1_UART1S (0 << (30-2))
+#define SICR_1_UART1_UART1RTS (1 << (30-2))
+#define SICR_1_I2C_I2C (0 << (30-4))
+#define SICR_1_I2C_CKSTOP (1 << (30-4))
+#define SICR_1_IRQ_A_IRQ (0 << (30-6))
+#define SICR_1_IRQ_A_MCP (1 << (30-6))
+#define SICR_1_IRQ_B_IRQ (0 << (30-8))
+#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
+#define SICR_1_GPIO_A_GPIO (0 << (30-10))
+#define SICR_1_GPIO_A_SD (2 << (30-10))
+#define SICR_1_GPIO_A_DDR (3 << (30-10))
+#define SICR_1_GPIO_B_GPIO (0 << (30-12))
+#define SICR_1_GPIO_B_SD (2 << (30-12))
+#define SICR_1_GPIO_B_QE (3 << (30-12))
+#define SICR_1_GPIO_C_GPIO (0 << (30-14))
+#define SICR_1_GPIO_C_CAN (1 << (30-14))
+#define SICR_1_GPIO_C_DDR (2 << (30-14))
+#define SICR_1_GPIO_C_LCS (3 << (30-14))
+#define SICR_1_GPIO_D_GPIO (0 << (30-16))
+#define SICR_1_GPIO_D_CAN (1 << (30-16))
+#define SICR_1_GPIO_D_DDR (2 << (30-16))
+#define SICR_1_GPIO_D_LCS (3 << (30-16))
+#define SICR_1_GPIO_E_GPIO (0 << (30-18))
+#define SICR_1_GPIO_E_CAN (1 << (30-18))
+#define SICR_1_GPIO_E_DDR (2 << (30-18))
+#define SICR_1_GPIO_E_LCS (3 << (30-18))
+#define SICR_1_GPIO_F_GPIO (0 << (30-20))
+#define SICR_1_GPIO_F_CAN (1 << (30-20))
+#define SICR_1_GPIO_F_CK (2 << (30-20))
+#define SICR_1_USB_A_USBDR (0 << (30-22))
+#define SICR_1_USB_A_UART2S (1 << (30-22))
+#define SICR_1_USB_B_USBDR (0 << (30-24))
+#define SICR_1_USB_B_UART2S (1 << (30-24))
+#define SICR_1_USB_B_UART2RTS (2 << (30-24))
+#define SICR_1_USB_C_USBDR (0 << (30-26))
+#define SICR_1_USB_C_QE_EXT (3 << (30-26))
+#define SICR_1_FEC1_FEC1 (0 << (30-28))
+#define SICR_1_FEC1_GTM (1 << (30-28))
+#define SICR_1_FEC1_GPIO (2 << (30-28))
+#define SICR_1_FEC2_FEC2 (0 << (30-30))
+#define SICR_1_FEC2_GTM (1 << (30-30))
+#define SICR_1_FEC2_GPIO (2 << (30-30))
+/* SICR_2 */
+#define SICR_2_FEC3_FEC3 (0 << (30-0))
+#define SICR_2_FEC3_TMR (1 << (30-0))
+#define SICR_2_FEC3_GPIO (2 << (30-0))
+#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
+#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
+#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
+#define SICR_2_ELBC_A_LA (0 << (30-4))
+#define SICR_2_ELBC_B_LCLK (0 << (30-6))
+#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
+#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
+#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
+/* bits 10-11 unused */
+#define SICR_2_USB_D_USBDR (0 << (30-12))
+#define SICR_2_USB_D_GPIO (2 << (30-12))
+#define SICR_2_USB_D_QE_BRG (3 << (30-12))
+#define SICR_2_PCI_PCI (0 << (30-14))
+#define SICR_2_PCI_CPCI_HS (2 << (30-14))
+#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
+#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
+#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
+#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
+#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
+#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
+#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
+#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
+#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
+#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
+#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
+#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
+#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
+#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
+#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
+#define SICR_2_QUIESCE_B (0 << (30-24))
+
#endif
/*
#define HRCWL_SVCOD_DIV_8 0x10000000
#define HRCWL_SVCOD_DIV_2 0x20000000
#define HRCWL_SVCOD_DIV_1 0x30000000
+#elif defined(CONFIG_MPC8309)
+
+#define HRCWL_CEVCOD 0x000000C0
+#define HRCWL_CEVCOD_SHIFT 6
+/*
+ * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
+ * these are different than with 8360, 832x
+ */
+#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
+#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
+#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
+
+#define HRCWL_CEPDF 0x00000020
+#define HRCWL_CEPDF_SHIFT 5
+#define HRCWL_CE_PLL_DIV_1X1 0x00000000
+#define HRCWL_CE_PLL_DIV_2X1 0x00000020
+
+#define HRCWL_CEPMF 0x0000001F
+#define HRCWL_CEPMF_SHIFT 0
+#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
+#define HRCWL_CE_TO_PLL_1X2 0x00000002
+#define HRCWL_CE_TO_PLL_1X3 0x00000003
+#define HRCWL_CE_TO_PLL_1X4 0x00000004
+#define HRCWL_CE_TO_PLL_1X5 0x00000005
+#define HRCWL_CE_TO_PLL_1X6 0x00000006
+#define HRCWL_CE_TO_PLL_1X7 0x00000007
+#define HRCWL_CE_TO_PLL_1X8 0x00000008
+#define HRCWL_CE_TO_PLL_1X9 0x00000009
+#define HRCWL_CE_TO_PLL_1X10 0x0000000A
+#define HRCWL_CE_TO_PLL_1X11 0x0000000B
+#define HRCWL_CE_TO_PLL_1X12 0x0000000C
+#define HRCWL_CE_TO_PLL_1X13 0x0000000D
+#define HRCWL_CE_TO_PLL_1X14 0x0000000E
+#define HRCWL_CE_TO_PLL_1X15 0x0000000F
+#define HRCWL_CE_TO_PLL_1X16 0x00000010
+#define HRCWL_CE_TO_PLL_1X17 0x00000011
+#define HRCWL_CE_TO_PLL_1X18 0x00000012
+#define HRCWL_CE_TO_PLL_1X19 0x00000013
+#define HRCWL_CE_TO_PLL_1X20 0x00000014
+#define HRCWL_CE_TO_PLL_1X21 0x00000015
+#define HRCWL_CE_TO_PLL_1X22 0x00000016
+#define HRCWL_CE_TO_PLL_1X23 0x00000017
+#define HRCWL_CE_TO_PLL_1X24 0x00000018
+#define HRCWL_CE_TO_PLL_1X25 0x00000019
+#define HRCWL_CE_TO_PLL_1X26 0x0000001A
+#define HRCWL_CE_TO_PLL_1X27 0x0000001B
+#define HRCWL_CE_TO_PLL_1X28 0x0000001C
+#define HRCWL_CE_TO_PLL_1X29 0x0000001D
+#define HRCWL_CE_TO_PLL_1X30 0x0000001E
+#define HRCWL_CE_TO_PLL_1X31 0x0000001F
+
+#define HRCWL_SVCOD 0x30000000
+#define HRCWL_SVCOD_SHIFT 28
+#define HRCWL_SVCOD_DIV_2 0x00000000
+#define HRCWL_SVCOD_DIV_4 0x10000000
+#define HRCWL_SVCOD_DIV_8 0x20000000
+#define HRCWL_SVCOD_DIV_1 0x30000000
#endif
/*
#define SCCR_SATACM_1 0x00000055
#define SCCR_SATACM_2 0x000000aa
#define SCCR_SATACM_3 0x000000ff
+#elif defined(CONFIG_MPC8309)
+/* SCCR bits - MPC8309 specific */
+#define SCCR_SDHCCM 0x0c000000
+#define SCCR_SDHCCM_SHIFT 26
+#define SCCR_SDHCCM_0 0x00000000
+#define SCCR_SDHCCM_1 0x04000000
+#define SCCR_SDHCCM_2 0x08000000
+#define SCCR_SDHCCM_3 0x0c000000
+
+#define SCCR_USBDRCM 0x00c00000
+#define SCCR_USBDRCM_SHIFT 22
+#define SCCR_USBDRCM_0 0x00000000
+#define SCCR_USBDRCM_1 0x00400000
+#define SCCR_USBDRCM_2 0x00800000
+#define SCCR_USBDRCM_3 0x00c00000
#endif
#define SCCR_PCIEXP1CM 0x00300000
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
-#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
#define SDHCI_QUIRK_NO_CD (1 << 5)
+#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
/* to make gcc happy */
struct sdhci_host;
struct serial_device *next;
};
+void default_serial_puts(const char *s);
+
extern struct serial_device serial_smc_device;
extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
SOBJS =
-COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o
+COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o fdt_empty_tree.o
COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
COBJS-$(CONFIG_FIT) += $(COBJS-libfdt)
--- /dev/null
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2012 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this library; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ * b) Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+int fdt_create_empty_tree(void *buf, int bufsize)
+{
+ int err;
+
+ err = fdt_create(buf, bufsize);
+ if (err)
+ return err;
+
+ err = fdt_finish_reservemap(buf);
+ if (err)
+ return err;
+
+ err = fdt_begin_node(buf, "");
+ if (err)
+ return err;
+
+ err = fdt_end_node(buf);
+ if (err)
+ return err;
+
+ err = fdt_finish(buf);
+ if (err)
+ return err;
+
+ return fdt_open_into(buf, buf, bufsize);
+}
+
return 0;
}
+int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
+ const void *val, int len)
+{
+ struct fdt_property *prop;
+ int err, oldlen, newlen;
+
+ FDT_RW_CHECK_HEADER(fdt);
+
+ prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
+ if (prop) {
+ newlen = len + oldlen;
+ err = _fdt_splice_struct(fdt, prop->data,
+ FDT_TAGALIGN(oldlen),
+ FDT_TAGALIGN(newlen));
+ if (err)
+ return err;
+ prop->len = cpu_to_fdt32(newlen);
+ memcpy(prop->data + oldlen, val, len);
+ } else {
+ err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
+ if (err)
+ return err;
+ memcpy(prop->data, val, len);
+ }
+ return 0;
+}
+
int fdt_delprop(void *fdt, int nodeoffset, const char *name)
{
struct fdt_property *prop;
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $@
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
#########################################################################
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $@
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
#########################################################################
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
. = ALIGN(4);
.got : { *(.got) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
u-boot-spl.bin
u-boot-spl.lds
u-boot-spl.map
+u-boot.lst
$(LIBS): depend
$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
-$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - < $< > $@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)u-boot.lst, $(LIBS)))
+$(obj)u-boot-spl.lds: $(LDSCRIPT) $(obj)u-boot.lst depend
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
depend: $(obj).depend
.PHONY: depend
/* obsolete_flag must be 0 to efficiently set it on NOR flash without erasing */
static unsigned char obsolete_flag = 0;
-
-static char default_environment[] = {
-#if defined(CONFIG_BOOTARGS)
- "bootargs=" CONFIG_BOOTARGS "\0"
-#endif
-#if defined(CONFIG_BOOTCOMMAND)
- "bootcmd=" CONFIG_BOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_RAMBOOTCOMMAND)
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_NFSBOOTCOMMAND)
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
-#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
-#endif
-#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
-#endif
-#ifdef CONFIG_ETHADDR
- "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
-#endif
-#ifdef CONFIG_ETH1ADDR
- "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH2ADDR
- "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH4ADDR
- "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH5ADDR
- "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
-#endif
-#ifdef CONFIG_ETHPRIME
- "ethprime=" CONFIG_ETHPRIME "\0"
-#endif
-#ifdef CONFIG_IPADDR
- "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
-#endif
-#ifdef CONFIG_SERVERIP
- "serverip=" __stringify(CONFIG_SERVERIP) "\0"
-#endif
-#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
-#endif
-#ifdef CONFIG_ROOTPATH
- "rootpath=" CONFIG_ROOTPATH "\0"
-#endif
-#ifdef CONFIG_GATEWAYIP
- "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
-#endif
-#ifdef CONFIG_NETMASK
- "netmask=" __stringify(CONFIG_NETMASK) "\0"
-#endif
-#ifdef CONFIG_HOSTNAME
- "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
-#endif
-#ifdef CONFIG_BOOTFILE
- "bootfile=" CONFIG_BOOTFILE "\0"
-#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
-#endif
-#ifdef CONFIG_PREBOOT
- "preboot=" CONFIG_PREBOOT "\0"
-#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=" "1" "\0"
-#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY) "\0"
-#endif
-#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
- "arch=" CONFIG_SYS_ARCH "\0"
- "cpu=" CONFIG_SYS_CPU "\0"
- "board=" CONFIG_SYS_BOARD "\0"
-#ifdef CONFIG_SYS_VENDOR
- "vendor=" CONFIG_SYS_VENDOR "\0"
-#endif
-#ifdef CONFIG_SYS_SOC
- "soc=" CONFIG_SYS_SOC "\0"
-#endif
-#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
- CONFIG_EXTRA_ENV_SETTINGS
-#endif
- "\0" /* Termimate struct environment data with 2 NULs */
-};
+#define DEFAULT_ENV_INSTANCE_STATIC
+#include <env_default.h>
static int flash_io (int mode);
static char *envmatch (char * s1, char * s2);
char *val = argv[i];
size_t val_len = strlen(val);
+ if (value)
+ value[len - 1] = ' ';
value = realloc(value, len + val_len + 1);
if (!value) {
fprintf(stderr,
memcpy(value + len, val, val_len);
len += val_len;
- value[len++] = ' ';
+ value[len++] = '\0';
}
- value[len - 1] = '\0';
fw_env_write(name, value);
return -1;
}
#ifdef DEBUG
- fprintf (stderr, "Read 0x%x bytes at 0x%llx\n",
- rc, blockstart + block_seek);
+ fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
+ rc, blockstart + block_seek, DEVNAME(dev));
#endif
processed += readlen;
readlen = min (blocklen, count - processed);
if (write_total != rc)
return -1;
+#ifdef DEBUG
+ fprintf(stderr, "Preserving data ");
+ if (block_seek != 0)
+ fprintf(stderr, "0x%x - 0x%lx", 0, block_seek - 1);
+ if (block_seek + count != write_total) {
+ if (block_seek != 0)
+ fprintf(stderr, " and ");
+ fprintf(stderr, "0x%lx - 0x%x",
+ block_seek + count, write_total - 1);
+ }
+ fprintf(stderr, "\n");
+#endif
/* Overwrite the old environment */
memcpy (data + block_seek, buf, count);
} else {
}
#ifdef DEBUG
- printf ("Write 0x%x bytes at 0x%llx\n", erasesize, blockstart);
+ fprintf(stderr, "Write 0x%x bytes at 0x%llx\n", erasesize,
+ blockstart);
#endif
if (write (fd, data + processed, erasesize) != erasesize) {
fprintf (stderr, "Write error on %s: %s\n",
}
#ifdef DEBUG
- printf ("Writing new environment at 0x%lx on %s\n",
+ fprintf(stderr, "Writing new environment at 0x%lx on %s\n",
DEVOFFSET (dev_target), DEVNAME (dev_target));
#endif
rc = flash_write_buf(dev_target, fd_target, environment.image,
off_t offset = DEVOFFSET (dev_current) +
offsetof (struct env_image_redundant, flags);
#ifdef DEBUG
- printf ("Setting obsolete flag in environment at 0x%lx on %s\n",
+ fprintf(stderr,
+ "Setting obsolete flag in environment at 0x%lx on %s\n",
DEVOFFSET (dev_current), DEVNAME (dev_current));
#endif
flash_flag_obsolete (dev_current, fd_current, offset);
/* Other pointers are already set */
free (addr1);
}
+#ifdef DEBUG
+ fprintf(stderr, "Selected env in %s\n", DEVNAME(dev_current));
+#endif
}
return 0;
}
Return:
Number of patches that exist on top of the branch
"""
- pipe = [['git', 'log', '--oneline', '@{upstream}..'],
+ pipe = [['git', 'log', '--no-color', '--oneline', '@{upstream}..'],
['wc', '-l']]
stdout = command.RunPipe(pipe, capture=True, oneline=True)
patch_count = int(stdout)
start: Commit to start from: 0=HEAD, 1=next one, etc.
count: Number of commits to list
"""
- pipe = [['git', 'log', '--reverse', 'HEAD~%d' % start, '-n%d' % count]]
+ pipe = [['git', 'log', '--no-color', '--reverse', 'HEAD~%d' % start,
+ '-n%d' % count]]
stdout = command.RunPipe(pipe, capture=True)
series = Series()
ps = PatchStream(series, is_log=True)
projects / karo-tx-uboot.git / commitdiff