*/
#include <common.h>
+#include <asm/io.h>
-#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
+#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
-#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
+#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+8) \
+ / (TIMER_CLOCK / CONFIG_SYS_HZ)
DECLARE_GLOBAL_DATA_PTR;
* (TLV-now) amount of time after passing though -1
* nts = new "advancing time stamp"...it could also roll and cause problems.
*/
- timestamp += lastdec + TIMER_LOAD_VAL - now;
+ timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK /
+ CONFIG_SYS_HZ)) - now;
}
lastdec = now;
*/
ulong get_tbclk (void)
{
- ulong tbclk;
-
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
+ return CONFIG_SYS_HZ;
}
struct pmic_data twl6030_4430es1 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
- .step = 12660, /* 10 mV represented in uV */
+ .step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
struct pmic_data twl6030 = {
.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
- .step = 12660, /* 10 mV represented in uV */
+ .step = 12660, /* 12.66 mV represented in uV */
/* The code starts at 1 not 0 */
.start_code = 1,
};
.core.value = 1200,
.core.addr = SMPS_REG_ADDR_VCORE1,
- .core.pmic = &tps62361,
+ .core.pmic = &twl6030,
.mm.value = 1200,
.mm.addr = SMPS_REG_ADDR_VCORE2,
- .mm.pmic = &tps62361,
+ .mm.pmic = &twl6030,
};
/*
#define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
/* Micron MT41K256M16HA-125E */
-#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100006
-#define MT41K256M16HA125E_EMIF_TIM1 0x0888A39B
-#define MT41K256M16HA125E_EMIF_TIM2 0x26517FDA
-#define MT41K256M16HA125E_EMIF_TIM3 0x501F84EF
-#define MT41K256M16HA125E_EMIF_SDCFG 0x61C04BB2
-#define MT41K256M16HA125E_EMIF_SDREF 0x0000093B
+#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
+#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2 0x26437FDA
+#define MT41K256M16HA125E_EMIF_TIM3 0x501F83FF
+#define MT41K256M16HA125E_EMIF_SDCFG 0x61C052B2
+#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
-#define MT41K256M16HA125E_RATIO 0x40
+#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
-#define MT41K256M16HA125E_RD_DQS 0x3C
-#define MT41K256M16HA125E_WR_DQS 0x45
-#define MT41K256M16HA125E_PHY_WR_DATA 0x7F
+#define MT41K256M16HA125E_RD_DQS 0x3A
+#define MT41K256M16HA125E_WR_DQS 0x42
+#define MT41K256M16HA125E_PHY_WR_DATA 0x7E
#define MT41K256M16HA125E_PHY_FIFO_WE 0x9B
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
#define BOOT_DEVICE_CPGMAC 70
#define BOOT_DEVICE_MMC2_2 0xFF
+#ifdef CONFIG_AM33XX
#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2
+#elif defined(CONFIG_TI814X)
+#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
+#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
+#endif
#endif
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt())
- config_ddr(303, MT41K256M16HA125E_IOCTRL_VALUE,
+ config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
# TI OSK board with OMAP5912 (ARM925EJS) cpu
# see http://www.ti.com/ for more information on Texas Instruments
#
-# OSK has 1 bank of 256 MB SDRAM
+# OSK has 1 bank of 32 MB SDRAM
# Physical Address:
-# 1000'0000 to 2000'0000
+# 1000'0000 to 1200'0000
#
#
# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
# (mem base + reserved)
#
-# we load ourself to 1108'0000
+# When running from RAM use address 1108'0000, otherwise when
+# booting from NOR flash link to address 0000'0000.
#
-#
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
+CONFIG_SYS_TEXT_BASE = 0x00000000
+#CONFIG_SYS_TEXT_BASE = 0x11080000
ldr r1, VAL_MPU_CNTL_TIMER
str r1, [r0]
+ /*
+ * Setup a temporary stack
+ */
+ ldr sp, SRAM_STACK
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+
+ /*
+ * Save the old lr(passed in ip) and the current lr to stack
+ */
+ push {ip, lr}
+
+ /*
+ * go setup pll, mux, memory
+ */
+ bl s_init
+ pop {ip, pc}
+
/* back to arch calling code */
mov pc, lr
VAL_ARM_IDLECT3:
.word 0x00000015
+SRAM_STACK:
+ .word CONFIG_SYS_INIT_SP_ADDR
+
/* command values */
.equ CMD_SDRAM_NOP, 0x00000000
.equ CMD_SDRAM_PRECHARGE, 0x00000001
/* adress of boot parameters */
gd->bd->bi_boot_params = 0x10000100;
+ flash__init();
+ ether__init();
+
+ return 0;
+}
+
+void s_init(void)
+{
/* Configure MUX settings */
set_muxconf_regs ();
peripheral_power_enable ();
* ... rkw ...
*/
icache_enable ();
-
- flash__init ();
- ether__init ();
- return 0;
}
/******************************
Routine:
Description:
******************************/
-int dram_init (void)
+int dram_init(void)
{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
return 0;
}
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+}
+
/******************************************************
Routine: set_muxconf_regs
Description: Setting up the configuration Mux registers
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
+#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_ENV_IS_IN_FLASH 1
/* addr of environment */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
+#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM
+#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE)
#endif /* __CONFIG_H */
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
- "name=u-boot,size=1792KiB,uuid=${uuid_gpt_u-boot};" \
- "name=rootfs,size=-,uuid=${uuid_gpt_rootfs}"
+ "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
#include <configs/omap5_common.h>