#
/MLO
+/SPL
/System.map
/u-boot
/u-boot.hex
/u-boot.imx
+/u-boot-with-spl.imx
+/u-boot-with-nand-spl.imx
/u-boot.map
/u-boot.srec
/u-boot.ldr
devkit3250 lpc32xx
-Zhong Hongbo <bocui107@gmail.com>
-
- SMDK6400 ARM1176 (S3C6400 SoC)
-
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Tetsuyuki Kobayashi <koba@kmckk.co.jp>
HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
sed -e 's/\(cygwin\).*/cygwin/')
-# Set shell to bash if possible, otherwise fall back to sh
-SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
- else if [ -x /bin/bash ]; then echo /bin/bash; \
- else echo sh; fi; fi)
-
-export HOSTARCH HOSTOS SHELL
+export HOSTARCH HOSTOS
# Deal with colliding definitions from tcsh etc.
VENDOR=
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(or $(CONFIG_SPL_PAD_TO),0) \
- -O binary $(obj)spl/u-boot-spl \
- $(obj)spl/u-boot-spl-pad.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
+$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
+ $(OBJTREE)/u-boot-with-spl.imx
+
+$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
+ $(OBJTREE)/u-boot-with-nand-spl.imx
+
$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin
$(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl
lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/')
ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/')
-#########################################################################
-## ARM1176 Systems
-#########################################################################
-smdk6400_noUSB_config \
-smdk6400_config : unconfig
- @mkdir -p $(obj)include $(obj)board/samsung/smdk6400
- @mkdir -p $(obj)nand_spl/board/samsung/smdk6400
- @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
- @if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then \
- echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
- else \
- echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\
- fi
- @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx
- @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
-
#########################################################################
#########################################################################
@rm -f $(obj)u-boot.kwb
@rm -f $(obj)u-boot.pbl
@rm -f $(obj)u-boot.imx
+ @rm -f $(obj)u-boot-with-spl.imx
+ @rm -f $(obj)u-boot-with-nand-spl.imx
@rm -f $(obj)u-boot.ubl
@rm -f $(obj)u-boot.ais
@rm -f $(obj)u-boot.dtb
Support for lib/libgeneric.o in SPL binary
CONFIG_SPL_PAD_TO
- Linker address to which the SPL should be padded before
- appending the SPL payload.
+ Image offset to which the SPL should be padded before appending
+ the SPL payload. By default, this is defined as
+ CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined.
+ CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL
+ payload without any padding, or >= CONFIG_SPL_MAX_SIZE.
CONFIG_SPL_TARGET
Final target image containing SPL and payload. Some SPLs
- CONFIG_SYS_SRIOn_MEM_SIZE:
Size of SRIO port 'n' memory region
-- CONFIG_SYS_NDFC_16
- Defined to tell the NDFC that the NAND chip is using a
- 16 bit bus.
+- CONFIG_SYS_NAND_BUSWIDTH_16BIT
+ Defined to tell the NAND controller that the NAND chip is using
+ a 16 bit bus.
+ Not all NAND drivers use this symbol.
+ Example of drivers that use it:
+ - drivers/mtd/nand/ndfc.c
+ - drivers/mtd/nand/mxc_nand.c
- CONFIG_SYS_NDFC_EBC0_CFG
Sets the EBC0_CFG register for the NDFC. If not defined
endif
# needed for relocation
-ifndef CONFIG_NAND_SPL
LDFLAGS_u-boot += -pie
-endif
#
# FIXME: binutils versions < 2.22 have a bug in the assembler where
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_SPL
ifdef CONFIG_SPL_BUILD
ALL-y += $(OBJTREE)/SPL
endif
+else
+ALL-y += $(obj)u-boot.imx
+endif
+endif
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
-.global _image_copy_end_ofs
+.globl _image_copy_end_ofs
_image_copy_end_ofs:
- .word __image_copy_end - _start
+ .word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
- bx lr
-
#endif
relocate_done:
.text :
{
__start = .;
- arch/arm/cpu/arm1136/start.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text*)
*(.text*)
} >.sram
+++ /dev/null
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).o
-
-SOBJS = reset.o
-
-COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o
-COBJS-y += timer.o init.o
-
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all: $(obj).depend $(START) $(LIB)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\
- $(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+++ /dev/null
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/s3c6400.h>
-
- .globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
- /* DMC1 base address 0x7e001000 */
- ldr r0, =ELFIN_DMC1_BASE
-
- ldr r1, =0x4
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
- ldr r1, =DMC_DDR_REFRESH_PRD
- str r1, [r0, #INDEX_DMC_REFRESH_PRD]
-
- ldr r1, =DMC_DDR_CAS_LATENCY
- str r1, [r0, #INDEX_DMC_CAS_LATENCY]
-
- ldr r1, =DMC_DDR_t_DQSS
- str r1, [r0, #INDEX_DMC_T_DQSS]
-
- ldr r1, =DMC_DDR_t_MRD
- str r1, [r0, #INDEX_DMC_T_MRD]
-
- ldr r1, =DMC_DDR_t_RAS
- str r1, [r0, #INDEX_DMC_T_RAS]
-
- ldr r1, =DMC_DDR_t_RC
- str r1, [r0, #INDEX_DMC_T_RC]
-
- ldr r1, =DMC_DDR_t_RCD
- ldr r2, =DMC_DDR_schedule_RCD
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RCD]
-
- ldr r1, =DMC_DDR_t_RFC
- ldr r2, =DMC_DDR_schedule_RFC
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RFC]
-
- ldr r1, =DMC_DDR_t_RP
- ldr r2, =DMC_DDR_schedule_RP
- orr r1, r1, r2
- str r1, [r0, #INDEX_DMC_T_RP]
-
- ldr r1, =DMC_DDR_t_RRD
- str r1, [r0, #INDEX_DMC_T_RRD]
-
- ldr r1, =DMC_DDR_t_WR
- str r1, [r0, #INDEX_DMC_T_WR]
-
- ldr r1, =DMC_DDR_t_WTR
- str r1, [r0, #INDEX_DMC_T_WTR]
-
- ldr r1, =DMC_DDR_t_XP
- str r1, [r0, #INDEX_DMC_T_XP]
-
- ldr r1, =DMC_DDR_t_XSR
- str r1, [r0, #INDEX_DMC_T_XSR]
-
- ldr r1, =DMC_DDR_t_ESR
- str r1, [r0, #INDEX_DMC_T_ESR]
-
- ldr r1, =DMC1_MEM_CFG
- str r1, [r0, #INDEX_DMC_MEMORY_CFG]
-
- ldr r1, =DMC1_MEM_CFG2
- str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
-
- ldr r1, =DMC1_CHIP0_CFG
- str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
-
- ldr r1, =DMC_DDR_32_CFG
- str r1, [r0, #INDEX_DMC_USER_CONFIG]
-
- /* DMC0 DDR Chip 0 configuration direct command reg */
- ldr r1, =DMC_NOP0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Precharge All */
- ldr r1, =DMC_PA0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Auto Refresh 2 time */
- ldr r1, =DMC_AR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* MRS */
- ldr r1, =DMC_mDDR_EMR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Mode Reg */
- ldr r1, =DMC_mDDR_MR0
- str r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
- /* Enable DMC1 */
- mov r1, #0x0
- str r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-check_dmc1_ready:
- ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
- mov r2, #0x3
- and r1, r1, r2
- cmp r1, #0x1
- bne check_dmc1_ready
- nop
-
- mov pc, lr
-
- .ltorg
+++ /dev/null
-/*
- * (C) Copyright 2012 Ashok Kumar Reddy Kourla
- * ashokkourla2000@gmail.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include<common.h>
-
-int arch_cpu_init(void)
-{
- icache_enable();
-
- return 0;
-}
+++ /dev/null
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/s3c6400.h>
-
-.globl reset_cpu
-reset_cpu:
- ldr r1, =ELFIN_CLOCK_POWER_BASE
- ldr r2, [r1, #SYS_ID_OFFSET]
- ldr r3, =0xffff
- and r2, r3, r2, lsr #12
- str r2, [r1, #SW_RST_OFFSET]
-_loop_forever:
- b _loop_forever
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code should work for both the S3C2400 and the S3C2410
- * as they seem to have the same PLL and clock machinery inside.
- * The different address mapping is handled by the s3c24xx.h files below.
- */
-
-#include <common.h>
-#include <asm/arch/s3c6400.h>
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-
-/* ------------------------------------------------------------------------- */
-/*
- * NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-static ulong get_PLLCLK(int pllreg)
-{
- ulong r, m, p, s;
-
- switch (pllreg) {
- case APLL:
- r = APLL_CON_REG;
- break;
- case MPLL:
- r = MPLL_CON_REG;
- break;
- case EPLL:
- r = EPLL_CON0_REG;
- break;
- default:
- hang();
- }
-
- m = (r >> 16) & 0x3ff;
- p = (r >> 8) & 0x3f;
- s = r & 0x7;
-
- return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
-}
-
-/* return ARMCORE frequency */
-ulong get_ARMCLK(void)
-{
- ulong div;
-
- div = CLK_DIV0_REG;
-
- return get_PLLCLK(APLL) / ((div & 0x7) + 1);
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
- return get_PLLCLK(APLL);
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
- ulong fclk;
-
- uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
- uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
-
- /*
- * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
- * s3c6400 and is always 0, and it is indeed running in ASYNC mode
- */
- if (OTHERS_REG & 0x80)
- fclk = get_FCLK(); /* SYNC Mode */
- else
- fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
-
- return fclk / (hclk_div * hclkx2_div);
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
- ulong fclk;
- uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
- uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
-
- if (OTHERS_REG & 0x80)
- fclk = get_FCLK(); /* SYNC Mode */
- else
- fclk = get_PLLCLK(MPLL); /* ASYNC Mode */
-
- return fclk / (hclkx2_div * pre_div);
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
- return get_PLLCLK(EPLL);
-}
-
-int print_cpuinfo(void)
-{
- printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
- printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
- get_FCLK() / 1000000, get_HCLK() / 1000000,
- get_PCLK() / 1000000);
-
- if (OTHERS_REG & 0x80)
- printf("(SYNC Mode) \n");
- else
- printf("(ASYNC Mode) \n");
- return 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/arch/s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
-
-#define PRESCALER 167
-
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
- return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
-
-/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
-{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- return timers->TCNTO4;
-}
-
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
-int timer_init(void)
-{
- s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
- /* use PWM Timer 4 because it has no output */
- /*
- * We use the following scheme for the timer:
- * Prescaler is hard fixed at 167, divider at 1/4.
- * This gives at PCLK frequency 66MHz approx. 10us ticks
- * The timer is set to wrap after 100s, at 66MHz this obviously
- * happens after 10,000,000 ticks. A long variable can thus
- * keep values up to 40,000s, i.e., 11 hours. This should be
- * enough for most uses:-) Possible optimizations: select a
- * binary-friendly frequency, e.g., 1ms / 128. Also calculate
- * the prescaler automatically for other PCLK frequencies.
- */
- timers->TCFG0 = PRESCALER << 8;
- if (timer_load_val == 0) {
- timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
- timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
- }
-
- /* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
- /* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
- TCON_4_UPDATE;
-
- /* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
- timestamp = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- ulong now = read_timer();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- /* We overrun in 100s */
- return (ulong)(timer_load_val / 100);
-}
-
-ulong get_timer_masked(void)
-{
- unsigned long long res = get_ticks();
- do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
- return res;
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-void __udelay(unsigned long usec)
-{
- unsigned long long tmp;
- ulong tmo;
-
- tmo = (usec + 9) / 10;
- tmp = get_ticks() + tmo; /* get current timestamp */
-
- while (get_ticks() < tmp)/* loop till event */
- /*NOP*/;
-}
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
-#ifdef CONFIG_ENABLE_MMU
-#include <asm/proc/domain.h>
-#endif
-#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
+#ifndef CONFIG_SYS_PHY_UBOOT_BASE
#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
#endif
.globl _start
_start: b reset
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
-
-/*
- * Below variable is very important because we use MMU in U-Boot.
- * Without it, we cannot run code correctly before MMU is ON.
- * by scsuh.
- */
-_TEXT_PHY_BASE:
- .word CONFIG_SYS_PHY_UBOOT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
-#ifndef CONFIG_NAND_SPL
+#ifndef CONFIG_SPL_BUILD
/*
* flush v4 I/D caches
*/
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
blo fixloop
#endif
-#ifdef CONFIG_ENABLE_MMU
-enable_mmu:
- /* enable domain access */
- ldr r5, =0x0000ffff
- mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
-
- /* Set the TTB register */
- ldr r0, _mmu_table_base
- ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
- ldr r2, =0xfff00000
- bic r0, r0, r2
- orr r1, r0, r1
- mcr p15, 0, r1, c2, c0, 0
-
- /* Enable the MMU */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #1 /* Set CR_M to enable MMU */
-
- /* Prepare to enable the MMU */
- adr r1, skip_hw_init
- and r1, r1, #0x3fc
- ldr r2, _TEXT_BASE
- ldr r3, =0xfff00000
- and r2, r2, r3
- orr r2, r2, r1
- b mmu_enable
-
- .align 5
- /* Run in a single cache-line */
-mmu_enable:
-
- mcr p15, 0, r0, c1, c0, 0
- nop
- nop
- mov pc, r2
-skip_hw_init:
-#endif
-
relocate_done:
bx lr
_dynsym_start_ofs:
.word __dynsym_start - _start
-#ifdef CONFIG_ENABLE_MMU
-_mmu_table_base:
- .word mmu_table
-#endif
-
.globl c_runtime_cpu_setup
c_runtime_cpu_setup:
mov pc, lr
-#ifndef CONFIG_NAND_SPL
-/*
- * we assume that cache operation is done before. (eg. cleanup_before_linux())
- * actually, we don't need to do anything about cache if not use d-cache in
- * U-Boot. So, in this function we clean only MMU. by scsuh
- *
- * void theLastJump(void *kernel, int arch_num, uint boot_params);
- */
-#ifdef CONFIG_ENABLE_MMU
- .globl theLastJump
-theLastJump:
- mov r9, r0
- ldr r3, =0xfff00000
- ldr r4, _TEXT_PHY_BASE
- adr r5, phy_last_jump
- bic r5, r5, r3
- orr r5, r5, r4
- mov pc, r5
-phy_last_jump:
- /*
- * disable MMU stuff
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
- bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
- orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
- orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
- mcr p15, 0, r0, c1, c0, 0
-
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- mov r0, #0
- mov pc, r9
-#endif
-
-
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
get_bad_stack
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_NAND_SPL */
+#endif /* CONFIG_SPL_BUILD */
.globl _TEXT_BASE
_TEXT_BASE:
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm920t/start.o (.text)
+ arch/arm/cpu/arm920t/start.o (.text*)
/* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */
. = 0x1000;
LONG(0x53555243)
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
- .data : { *(.data) }
+ .data : { *(.data*) }
. = ALIGN(4);
.got : { *(.got) }
}
. = ALIGN(4);
+
+ __image_copy_end = .;
+
__bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss*) }
__bss_end = .;
_end = .;
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
-
+ifdef CONFIG_SPL
+ifdef CONFIG_SPL_BUILD
+ALL-y += $(OBJTREE)/SPL
+endif
+else
ALL-y += $(obj)u-boot.imx
-
+endif
endif
.globl _TEXT_BASE
_TEXT_BASE:
+#ifdef CONFIG_SPL_TEXT_BASE
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/mxs/start.o (.text)
- *(.text)
+ arch/arm/cpu/arm926ejs/mxs/start.o (.text*)
+ *(.text*)
}
. = ALIGN(4);
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/spear/start.o (.text)
- *(.text)
+ arch/arm/cpu/arm926ejs/spear/start.o (.text*)
+ *(.text*)
}
. = ALIGN(4);
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
.globl _TEXT_BASE
_TEXT_BASE:
-#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
- .word CONFIG_SYS_TEXT_BASE
-#else
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
#endif
-#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
_end_ofs:
.word _end - _start
-#ifdef CONFIG_NAND_U_BOOT
-.globl _end
-_end:
- .word __bss_end
-#endif
-
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
/*------------------------------------------------------------------------------*/
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- sub r9, r6, r0 /* r9 <- relocation offset */
- cmp r0, r6
- moveq r9, #0 /* no relocation. offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
bx lr
+#ifndef CONFIG_SPL_BUILD
+
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
+ .word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
+ifdef CONFIG_SPL
+ifdef CONFIG_SPL_BUILD
+ALL-y += $(OBJTREE)/SPL
+endif
+else
ALL-y += $(obj)u-boot.imx
endif
+endif
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
- ldr r1, =0x02888945
- orr r1, r1, #(1 << 16)
+ ldr r1, =0x02898945
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x00808145
- orr r1, r1, #(2 << 10)
- orr r1, r1, #(0 << 16)
- orr r1, r1, #(1 << 19)
+ ldr r1, =0x00888945
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
.text :
{
__start = .;
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
.text :
{
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sdram
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
-.global _image_copy_end_ofs
+.globl _image_copy_end_ofs
_image_copy_end_ofs:
- .word __image_copy_end - _start
+ .word __image_copy_end - _start
.globl _bss_end_ofs
_bss_end_ofs:
#ifndef CONFIG_SPL_BUILD
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
ENTRY(relocate_code)
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
. = ALIGN(4);
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
.globl _TEXT_BASE
_TEXT_BASE:
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_SYS_TEXT_BASE
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
#ifndef CONFIG_SPL_BUILD
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
/* Disable the Dcache RAM lock for stack now */
#ifdef CONFIG_CPU_PXA25X
#endif
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
.globl _TEXT_BASE
_TEXT_BASE:
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
+ .word CONFIG_SPL_TEXT_BASE
+#else
.word CONFIG_SYS_TEXT_BASE
+#endif
/*
* These are defined in the board-specific linker script.
_bss_start_ofs:
.word __bss_start - _start
+.globl _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
.word __bss_end - _start
/*------------------------------------------------------------------------------*/
/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
+ * void relocate_code(addr_moni)
*
+ * This function relocates the monitor code.
*/
.globl relocate_code
relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
+ mov r6, r0 /* save addr of destination */
adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ subs r9, r6, r0 /* r9 <- relocation offset */
beq relocate_done /* skip relocation */
mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
+ ldr r3, _image_copy_end_ofs
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
+ ldmia r0!, {r10-r11} /* copy from source address [r0] */
+ stmia r1!, {r10-r11} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
+$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx
+ cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
+ rm $(OBJTREE)/spl/u-boot-spl-pad.imx
+
+$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin
+ (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \
+ dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \
+ cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \
+ $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+ rm $(OBJTREE)/spl/u-boot-nand-spl.imx
+ cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@
+ rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx
+
#########################################################################
+++ /dev/null
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _ARCH_HARDWARE_H_
-#define _ARCH_HARDWARE_H_
-
-#include <asm/sizes.h>
-
-#ifndef __ASSEMBLY__
-#define UData(Data) ((unsigned long) (Data))
-
-#define __REG(x) (*(vu_long *)(x))
-#define __REGl(x) (*(vu_long *)(x))
-#define __REGw(x) (*(vu_short *)(x))
-#define __REGb(x) (*(vu_char *)(x))
-#define __REG2(x, y) (*(vu_long *)((x) + (y)))
-#else
-#define UData(Data) (Data)
-
-#define __REG(x) (x)
-#define __REGl(x) (x)
-#define __REGw(x) (x)
-#define __REGb(x) (x)
-#define __REG2(x, y) ((x) + (y))
-#endif
-
-#define Fld(Size, Shft) (((Size) << 16) + (Shft))
-
-#define FSize(Field) ((Field) >> 16)
-#define FShft(Field) ((Field) & 0x0000FFFF)
-#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field) (UData (1) << FShft (Field))
-
-#define FClrBit(Data, Bit) (Data = (Data & ~(Bit)))
-#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field)))
-
-#define FInsrt(Value, Field) \
- (UData (Value) << FShft (Field))
-
-#define FExtr(Data, Field) \
- ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-#endif /* _ARCH_HARDWARE_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2007
- * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
- * - only support for S3C6400
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c6400.h
- *
- * Based on S3C6400 User's manual Rev 0.0
- ************************************************/
-
-#ifndef __S3C6400_H__
-#define __S3C6400_H__
-
-#define S3C64XX_UART_CHANNELS 3
-#define S3C64XX_SPI_CHANNELS 2
-
-#include <asm/hardware.h>
-
-#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
-
-/* Clock & Power Controller for mDirac3*/
-#define APLL_LOCK_OFFSET 0x00
-#define MPLL_LOCK_OFFSET 0x04
-#define EPLL_LOCK_OFFSET 0x08
-#define APLL_CON_OFFSET 0x0C
-#define MPLL_CON_OFFSET 0x10
-#define EPLL_CON0_OFFSET 0x14
-#define EPLL_CON1_OFFSET 0x18
-#define CLK_SRC_OFFSET 0x1C
-#define CLK_DIV0_OFFSET 0x20
-#define CLK_DIV1_OFFSET 0x24
-#define CLK_DIV2_OFFSET 0x28
-#define CLK_OUT_OFFSET 0x2C
-#define HCLK_GATE_OFFSET 0x30
-#define PCLK_GATE_OFFSET 0x34
-#define SCLK_GATE_OFFSET 0x38
-#define AHB_CON0_OFFSET 0x100
-#define AHB_CON1_OFFSET 0x104
-#define AHB_CON2_OFFSET 0x108
-#define SELECT_DMA_OFFSET 0x110
-#define SW_RST_OFFSET 0x114
-#define SYS_ID_OFFSET 0x118
-#define MEM_SYS_CFG_OFFSET 0x120
-#define QOS_OVERRIDE0_OFFSET 0x124
-#define QOS_OVERRIDE1_OFFSET 0x128
-#define MEM_CFG_STAT_OFFSET 0x12C
-#define PWR_CFG_OFFSET 0x804
-#define EINT_MASK_OFFSET 0x808
-#define NOR_CFG_OFFSET 0x810
-#define STOP_CFG_OFFSET 0x814
-#define SLEEP_CFG_OFFSET 0x818
-#define OSC_FREQ_OFFSET 0x820
-#define OSC_STABLE_OFFSET 0x824
-#define PWR_STABLE_OFFSET 0x828
-#define FPC_STABLE_OFFSET 0x82C
-#define MTC_STABLE_OFFSET 0x830
-#define OTHERS_OFFSET 0x900
-#define RST_STAT_OFFSET 0x904
-#define WAKEUP_STAT_OFFSET 0x908
-#define BLK_PWR_STAT_OFFSET 0x90C
-#define INF_REG0_OFFSET 0xA00
-#define INF_REG1_OFFSET 0xA04
-#define INF_REG2_OFFSET 0xA08
-#define INF_REG3_OFFSET 0xA0C
-#define INF_REG4_OFFSET 0xA10
-#define INF_REG5_OFFSET 0xA14
-#define INF_REG6_OFFSET 0xA18
-#define INF_REG7_OFFSET 0xA1C
-
-#define OSC_CNT_VAL_OFFSET 0x824
-#define PWR_CNT_VAL_OFFSET 0x828
-#define FPC_CNT_VAL_OFFSET 0x82C
-#define MTC_CNT_VAL_OFFSET 0x830
-
-#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- SELECT_DMA_OFFSET)
-#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MEM_CFG_STAT_OFFSET)
-#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- MTC_CNT_VAL_OFFSET)
-#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \
- BLK_PWR_STAT_OFFSET)
-#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET)
-#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET)
-#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET)
-#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET)
-#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET)
-#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET)
-#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET)
-#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET)
-#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET)
-#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET)
-#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET)
-#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET)
-#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET)
-#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET)
-#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET)
-#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET)
-#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET)
-#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET)
-#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET)
-#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET)
-#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET)
-#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET)
-#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET)
-#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET)
-#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET)
-#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET)
-#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET)
-#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET)
-#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET)
-#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET)
-#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET)
-#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET)
-#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET)
-#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET)
-#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET)
-#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET)
-#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
-#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
-#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET)
-#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
-#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET)
-#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET)
-#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET)
-#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET)
-#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET)
-#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET)
-#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET)
-
-
-/*
- * GPIO
- */
-#define ELFIN_GPIO_BASE 0x7f008000
-
-#define GPACON_OFFSET 0x00
-#define GPADAT_OFFSET 0x04
-#define GPAPUD_OFFSET 0x08
-#define GPACONSLP_OFFSET 0x0C
-#define GPAPUDSLP_OFFSET 0x10
-#define GPBCON_OFFSET 0x20
-#define GPBDAT_OFFSET 0x24
-#define GPBPUD_OFFSET 0x28
-#define GPBCONSLP_OFFSET 0x2C
-#define GPBPUDSLP_OFFSET 0x30
-#define GPCCON_OFFSET 0x40
-#define GPCDAT_OFFSET 0x44
-#define GPCPUD_OFFSET 0x48
-#define GPCCONSLP_OFFSET 0x4C
-#define GPCPUDSLP_OFFSET 0x50
-#define GPDCON_OFFSET 0x60
-#define GPDDAT_OFFSET 0x64
-#define GPDPUD_OFFSET 0x68
-#define GPDCONSLP_OFFSET 0x6C
-#define GPDPUDSLP_OFFSET 0x70
-#define GPECON_OFFSET 0x80
-#define GPEDAT_OFFSET 0x84
-#define GPEPUD_OFFSET 0x88
-#define GPECONSLP_OFFSET 0x8C
-#define GPEPUDSLP_OFFSET 0x90
-#define GPFCON_OFFSET 0xA0
-#define GPFDAT_OFFSET 0xA4
-#define GPFPUD_OFFSET 0xA8
-#define GPFCONSLP_OFFSET 0xAC
-#define GPFPUDSLP_OFFSET 0xB0
-#define GPGCON_OFFSET 0xC0
-#define GPGDAT_OFFSET 0xC4
-#define GPGPUD_OFFSET 0xC8
-#define GPGCONSLP_OFFSET 0xCC
-#define GPGPUDSLP_OFFSET 0xD0
-#define GPHCON0_OFFSET 0xE0
-#define GPHCON1_OFFSET 0xE4
-#define GPHDAT_OFFSET 0xE8
-#define GPHPUD_OFFSET 0xEC
-#define GPHCONSLP_OFFSET 0xF0
-#define GPHPUDSLP_OFFSET 0xF4
-#define GPICON_OFFSET 0x100
-#define GPIDAT_OFFSET 0x104
-#define GPIPUD_OFFSET 0x108
-#define GPICONSLP_OFFSET 0x10C
-#define GPIPUDSLP_OFFSET 0x110
-#define GPJCON_OFFSET 0x120
-#define GPJDAT_OFFSET 0x124
-#define GPJPUD_OFFSET 0x128
-#define GPJCONSLP_OFFSET 0x12C
-#define GPJPUDSLP_OFFSET 0x130
-#define MEM0DRVCON_OFFSET 0x1D0
-#define MEM1DRVCON_OFFSET 0x1D4
-#define GPKCON0_OFFSET 0x800
-#define GPKCON1_OFFSET 0x804
-#define GPKDAT_OFFSET 0x808
-#define GPKPUD_OFFSET 0x80C
-#define GPLCON0_OFFSET 0x810
-#define GPLCON1_OFFSET 0x814
-#define GPLDAT_OFFSET 0x818
-#define GPLPUD_OFFSET 0x81C
-#define GPMCON_OFFSET 0x820
-#define GPMDAT_OFFSET 0x824
-#define GPMPUD_OFFSET 0x828
-#define GPNCON_OFFSET 0x830
-#define GPNDAT_OFFSET 0x834
-#define GPNPUD_OFFSET 0x838
-#define GPOCON_OFFSET 0x140
-#define GPODAT_OFFSET 0x144
-#define GPOPUD_OFFSET 0x148
-#define GPOCONSLP_OFFSET 0x14C
-#define GPOPUDSLP_OFFSET 0x150
-#define GPPCON_OFFSET 0x160
-#define GPPDAT_OFFSET 0x164
-#define GPPPUD_OFFSET 0x168
-#define GPPCONSLP_OFFSET 0x16C
-#define GPPPUDSLP_OFFSET 0x170
-#define GPQCON_OFFSET 0x180
-#define GPQDAT_OFFSET 0x184
-#define GPQPUD_OFFSET 0x188
-#define GPQCONSLP_OFFSET 0x18C
-#define GPQPUDSLP_OFFSET 0x190
-
-#define EINTPEND_OFFSET 0x924
-
-#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Bus Matrix
- */
-#define ELFIN_MEM_SYS_CFG 0x7e00f120
-
-#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12)
-
-#define S3C64XX_MEM_SYS_CFG_NAND 0x0008
-#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT
-
-#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET)
-#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET)
-#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET)
-#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET)
-#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET)
-#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET)
-#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET)
-#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET)
-#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET)
-#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET)
-#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET)
-#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET)
-#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET)
-#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET)
-#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET)
-#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET)
-#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET)
-#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET)
-#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET)
-#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET)
-#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET)
-#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET)
-#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET)
-#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET)
-#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET)
-#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET)
-#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET)
-#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET)
-#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET)
-#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET)
-#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET)
-#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET)
-#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET)
-#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET)
-#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET)
-#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET)
-#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET)
-#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET)
-#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET)
-#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET)
-#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET)
-#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET)
-#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET)
-#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET)
-#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET)
-#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET)
-#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET)
-#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET)
-#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET)
-#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET)
-#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET)
-#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET)
-#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET)
-#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET)
-#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET)
-#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET)
-#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET)
-#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET)
-#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET)
-#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET)
-#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET)
-#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET)
-#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET)
-#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET)
-#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET)
-#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET)
-#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET)
-#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET)
-#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET)
-#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET)
-#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET)
-#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET)
-#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET)
-#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET)
-#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET)
-#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET)
-#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET)
-#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET)
-#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET)
-#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET)
-
-/*
- * Memory controller
- */
-#define ELFIN_SROM_BASE 0x70000000
-
-#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0)
-#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4)
-#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8)
-#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC)
-#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10)
-#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14)
-#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18)
-
-/*
- * SDRAM Controller
- */
-#define ELFIN_DMC0_BASE 0x7e000000
-#define ELFIN_DMC1_BASE 0x7e001000
-
-#define INDEX_DMC_MEMC_STATUS 0x00
-#define INDEX_DMC_MEMC_CMD 0x04
-#define INDEX_DMC_DIRECT_CMD 0x08
-#define INDEX_DMC_MEMORY_CFG 0x0C
-#define INDEX_DMC_REFRESH_PRD 0x10
-#define INDEX_DMC_CAS_LATENCY 0x14
-#define INDEX_DMC_T_DQSS 0x18
-#define INDEX_DMC_T_MRD 0x1C
-#define INDEX_DMC_T_RAS 0x20
-#define INDEX_DMC_T_RC 0x24
-#define INDEX_DMC_T_RCD 0x28
-#define INDEX_DMC_T_RFC 0x2C
-#define INDEX_DMC_T_RP 0x30
-#define INDEX_DMC_T_RRD 0x34
-#define INDEX_DMC_T_WR 0x38
-#define INDEX_DMC_T_WTR 0x3C
-#define INDEX_DMC_T_XP 0x40
-#define INDEX_DMC_T_XSR 0x44
-#define INDEX_DMC_T_ESR 0x48
-#define INDEX_DMC_MEMORY_CFG2 0x4C
-#define INDEX_DMC_CHIP_0_CFG 0x200
-#define INDEX_DMC_CHIP_1_CFG 0x204
-#define INDEX_DMC_CHIP_2_CFG 0x208
-#define INDEX_DMC_CHIP_3_CFG 0x20C
-#define INDEX_DMC_USER_STATUS 0x300
-#define INDEX_DMC_USER_CONFIG 0x304
-
-/*
- * Memory Chip direct command
- */
-#define DMC_NOP0 0x0c0000
-#define DMC_NOP1 0x1c0000
-#define DMC_PA0 0x000000 /* Precharge all */
-#define DMC_PA1 0x100000
-#define DMC_AR0 0x040000 /* Autorefresh */
-#define DMC_AR1 0x140000
-#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */
-#define DMC_SDR_MR1 0x180032
-#define DMC_DDR_MR0 0x080162
-#define DMC_DDR_MR1 0x180162
-#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */
-#define DMC_mDDR_MR1 0x180032
-#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */
-#define DMC_mSDR_EMR1 0x1a0000
-#define DMC_DDR_EMR0 0x090000
-#define DMC_DDR_EMR1 0x190000
-#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */
-#define DMC_mDDR_EMR1 0x1a0000
-
-/*
- * Definitions for memory configuration
- * Set memory configuration
- * active_chips = 1'b0 (1 chip)
- * qos_master_chip = 3'b000(ARID[3:0])
- * memory burst = 3'b010(burst 4)
- * stop_mem_clock = 1'b0(disable dynamical stop)
- * auto_power_down = 1'b0(disable auto power-down mode)
- * power_down_prd = 6'b00_0000(0 cycle for auto power-down)
- * ap_bit = 1'b0 (bit position of auto-precharge is 10)
- * row_bits = 3'b010(# row address 13)
- * column_bits = 3'b010(# column address 10 )
- *
- * Set user configuration
- * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
- *
- * Set chip select for chip [n]
- * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
- * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
- */
-
-/*
- * Nand flash controller
- */
-#define ELFIN_NAND_BASE 0x70200000
-
-#define NFCONF_OFFSET 0x00
-#define NFCONT_OFFSET 0x04
-#define NFCMMD_OFFSET 0x08
-#define NFADDR_OFFSET 0x0c
-#define NFDATA_OFFSET 0x10
-#define NFMECCDATA0_OFFSET 0x14
-#define NFMECCDATA1_OFFSET 0x18
-#define NFSECCDATA0_OFFSET 0x1c
-#define NFSBLK_OFFSET 0x20
-#define NFEBLK_OFFSET 0x24
-#define NFSTAT_OFFSET 0x28
-#define NFESTAT0_OFFSET 0x2c
-#define NFESTAT1_OFFSET 0x30
-#define NFMECC0_OFFSET 0x34
-#define NFMECC1_OFFSET 0x38
-#define NFSECC_OFFSET 0x3c
-#define NFMLCBITPT_OFFSET 0x40
-
-#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET)
-#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET)
-#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET)
-#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET)
-#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET)
-#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET)
-#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET)
-#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET)
-#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET)
-#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET)
-#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET)
-#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET)
-#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET)
-#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET)
-#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET)
-#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET)
-#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET)
-
-#define NFCONF_ECC_4BIT (1<<24)
-
-#define NFCONT_ECC_ENC (1<<18)
-#define NFCONT_WP (1<<16)
-#define NFCONT_MECCLOCK (1<<7)
-#define NFCONT_SECCLOCK (1<<6)
-#define NFCONT_INITMECC (1<<5)
-#define NFCONT_INITSECC (1<<4)
-#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
-#define NFCONT_CS_ALT (1<<2)
-#define NFCONT_CS (1<<1)
-#define NFCONT_ENABLE (1<<0)
-
-#define NFSTAT_ECCENCDONE (1<<7)
-#define NFSTAT_ECCDECDONE (1<<6)
-#define NFSTAT_RnB (1<<0)
-
-#define NFESTAT0_ECCBUSY (1<<31)
-
-/*
- * Interrupt
- */
-#define ELFIN_VIC0_BASE_ADDR 0x71200000
-#define ELFIN_VIC1_BASE_ADDR 0x71300000
-#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */
-#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */
-#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */
-#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */
-#define oVECTADDR 0xF00 /* VIC ADDRESS */
-
-/*
- * Watchdog timer
- */
-#define ELFIN_WATCHDOG_BASE 0x7E004000
-
-#define WTCON_REG __REG(0x7E004004)
-#define WTDAT_REG __REG(0x7E004008)
-#define WTCNT_REG __REG(0x7E00400C)
-
-
-/*
- * UART
- */
-#define ELFIN_UART_BASE 0x7F005000
-
-#define ELFIN_UART0_OFFSET 0x0000
-#define ELFIN_UART1_OFFSET 0x0400
-#define ELFIN_UART2_OFFSET 0x0800
-
-#define ULCON_OFFSET 0x00
-#define UCON_OFFSET 0x04
-#define UFCON_OFFSET 0x08
-#define UMCON_OFFSET 0x0C
-#define UTRSTAT_OFFSET 0x10
-#define UERSTAT_OFFSET 0x14
-#define UFSTAT_OFFSET 0x18
-#define UMSTAT_OFFSET 0x1C
-#define UTXH_OFFSET 0x20
-#define URXH_OFFSET 0x24
-#define UBRDIV_OFFSET 0x28
-#define UDIVSLOT_OFFSET 0x2C
-#define UINTP_OFFSET 0x30
-#define UINTSP_OFFSET 0x34
-#define UINTM_OFFSET 0x38
-
-#define ULCON0_REG __REG(0x7F005000)
-#define UCON0_REG __REG(0x7F005004)
-#define UFCON0_REG __REG(0x7F005008)
-#define UMCON0_REG __REG(0x7F00500C)
-#define UTRSTAT0_REG __REG(0x7F005010)
-#define UERSTAT0_REG __REG(0x7F005014)
-#define UFSTAT0_REG __REG(0x7F005018)
-#define UMSTAT0_REG __REG(0x7F00501c)
-#define UTXH0_REG __REG(0x7F005020)
-#define URXH0_REG __REG(0x7F005024)
-#define UBRDIV0_REG __REG(0x7F005028)
-#define UDIVSLOT0_REG __REG(0x7F00502c)
-#define UINTP0_REG __REG(0x7F005030)
-#define UINTSP0_REG __REG(0x7F005034)
-#define UINTM0_REG __REG(0x7F005038)
-
-#define ULCON1_REG __REG(0x7F005400)
-#define UCON1_REG __REG(0x7F005404)
-#define UFCON1_REG __REG(0x7F005408)
-#define UMCON1_REG __REG(0x7F00540C)
-#define UTRSTAT1_REG __REG(0x7F005410)
-#define UERSTAT1_REG __REG(0x7F005414)
-#define UFSTAT1_REG __REG(0x7F005418)
-#define UMSTAT1_REG __REG(0x7F00541c)
-#define UTXH1_REG __REG(0x7F005420)
-#define URXH1_REG __REG(0x7F005424)
-#define UBRDIV1_REG __REG(0x7F005428)
-#define UDIVSLOT1_REG __REG(0x7F00542c)
-#define UINTP1_REG __REG(0x7F005430)
-#define UINTSP1_REG __REG(0x7F005434)
-#define UINTM1_REG __REG(0x7F005438)
-
-#define UTRSTAT_TX_EMPTY (1 << 2)
-#define UTRSTAT_RX_READY (1 << 0)
-#define UART_ERR_MASK 0xF
-
-/*
- * PWM timer
- */
-#define ELFIN_TIMER_BASE 0x7F006000
-
-#define TCFG0_REG __REG(0x7F006000)
-#define TCFG1_REG __REG(0x7F006004)
-#define TCON_REG __REG(0x7F006008)
-#define TCNTB0_REG __REG(0x7F00600c)
-#define TCMPB0_REG __REG(0x7F006010)
-#define TCNTO0_REG __REG(0x7F006014)
-#define TCNTB1_REG __REG(0x7F006018)
-#define TCMPB1_REG __REG(0x7F00601c)
-#define TCNTO1_REG __REG(0x7F006020)
-#define TCNTB2_REG __REG(0x7F006024)
-#define TCMPB2_REG __REG(0x7F006028)
-#define TCNTO2_REG __REG(0x7F00602c)
-#define TCNTB3_REG __REG(0x7F006030)
-#define TCMPB3_REG __REG(0x7F006034)
-#define TCNTO3_REG __REG(0x7F006038)
-#define TCNTB4_REG __REG(0x7F00603c)
-#define TCNTO4_REG __REG(0x7F006040)
-
-/* Fields */
-#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */
-#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */
-#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */
-#define fTCFG1_MUX4 Fld(4, 16)
-/* bits */
-#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
-#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
-#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
-#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
-#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
-#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
-#define COUNT_4_ON (TCON_4_ONOFF * 1)
-#define COUNT_4_OFF (TCON_4_ONOFF * 0)
-#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
-#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1)
-#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
-#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
-#define TIMER3_IVT_ON (TCON_3_INVERT * 1)
-#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
-#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
-#define TIMER3_MANUP (TCON_3_MAN*1)
-#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
-#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
-#define TIMER3_ON (TCON_3_ONOFF * 1)
-#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
-
-#if defined(CONFIG_CLK_400_100_50)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 400
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_400_133_66)
-#define STARTUP_AMDIV 400
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_533_133_66)
-#define STARTUP_AMDIV 533
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#elif defined(CONFIG_CLK_667_133_66)
-#define STARTUP_AMDIV 667
-#define STARTUP_MDIV 533
-#define STARTUP_PDIV 6
-#define STARTUP_SDIV 1
-#endif
-
-#define STARTUP_PCLKDIV 3
-#define STARTUP_HCLKX2DIV 1
-#define STARTUP_HCLKDIV 1
-#define STARTUP_MPLLDIV 1
-#define STARTUP_APLLDIV 0
-
-#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
- (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-
-#if defined(CONFIG_SYNC_MODE)
-#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_MDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#else
-#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \
- (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
- STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
- (STARTUP_HCLKDIV + 1))
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */
-#define DMC1_MEM_CFG2 0xB45
-#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */
-#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH 7800 /* ns */
-#define DDR_tRAS 45 /* ns (min: 45ns)*/
-#define DDR_tRC 68 /* ns (min: 67.5ns)*/
-#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
-#define DDR_tRFC 80 /* ns (min: 80ns)*/
-#define DDR_tRP 23 /* ns (min: 22.5ns)*/
-#define DDR_tRRD 15 /* ns (min: 15ns)*/
-#define DDR_tWR 15 /* ns (min: 15ns)*/
-#define DDR_tXSR 120 /* ns (min: 120ns)*/
-#define DDR_CASL 3 /* CAS Latency 3 */
-
-/*
- * mDDR memory configuration
- */
-
-#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000)
-
-#define DMC_DDR_BA_EMRS 2
-#define DMC_DDR_MEM_CASLAT 3
-/* 6 Set Cas Latency to 3 */
-#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1)
-/* Min 0.75 ~ 1.25 */
-#define DMC_DDR_t_DQSS 1
-/* Min 2 tck */
-#define DMC_DDR_t_MRD 2
-/* 7, Min 45ns */
-#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1)
-/* 10, Min 67.5ns */
-#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1)
-/* 4,5(TRM), Min 22.5ns */
-#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1)
-#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
-/* 11,18(TRM) Min 80ns */
-#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1)
-#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
-/* 4, 5(TRM) Min 22.5ns */
-#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1)
-#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
-/* 3, Min 15ns */
-#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1)
-/* Min 15ns */
-#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1)
-#define DMC_DDR_t_WTR 2
-/* 1tck + tIS(1.5ns) */
-#define DMC_DDR_t_XP 2
-/* 17, Min 120ns */
-#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1)
-#define DMC_DDR_t_ESR DMC_DDR_t_XSR
-/* TRM 2656 */
-#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH))
-/* 2b01 : mDDR */
-#define DMC_DDR_USER_CONFIG 1
-
-#ifndef __ASSEMBLY__
-enum s3c64xx_uarts_nr {
- S3C64XX_UART0,
- S3C64XX_UART1,
- S3C64XX_UART2,
-};
-
-#include "s3c64x0.h"
-
-static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr)
-{
- return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400));
-}
-#endif
-
-#endif /*__S3C6400_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : S3C64XX.h
- * Version : 31.3.2003
- *
- * common stuff for SAMSUNG S3C64XX SoC
- ************************************************/
-
-#ifndef __S3C64XX_H__
-#define __S3C64XX_H__
-
-#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400)
-#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration!
-#endif
-
-#include <asm/types.h>
-
-/* UART (see manual chapter 11) */
-typedef struct {
- volatile u32 ULCON;
- volatile u32 UCON;
- volatile u32 UFCON;
- volatile u32 UMCON;
- volatile u32 UTRSTAT;
- volatile u32 UERSTAT;
- volatile u32 UFSTAT;
- volatile u32 UMSTAT;
-#ifdef __BIG_ENDIAN
- volatile u8 res1[3];
- volatile u8 UTXH;
- volatile u8 res2[3];
- volatile u8 URXH;
-#else /* Little Endian */
- volatile u8 UTXH;
- volatile u8 res1[3];
- volatile u8 URXH;
- volatile u8 res2[3];
-#endif
- volatile u32 UBRDIV;
-#ifdef __BIG_ENDIAN
- volatile u8 res3[2];
- volatile u16 UDIVSLOT;
-#else
- volatile u16 UDIVSLOT;
- volatile u8 res3[2];
-#endif
-} s3c64xx_uart;
-
-/* PWM TIMER (see manual chapter 10) */
-typedef struct {
- volatile u32 TCNTB;
- volatile u32 TCMPB;
- volatile u32 TCNTO;
-} s3c64xx_timer;
-
-typedef struct {
- volatile u32 TCFG0;
- volatile u32 TCFG1;
- volatile u32 TCON;
- s3c64xx_timer ch[4];
- volatile u32 TCNTB4;
- volatile u32 TCNTO4;
-} s3c64xx_timers;
-
-#endif /*__S3C64XX_H__*/
#define MACH_TYPE_MIOA701 1257
#define MACH_TYPE_ARMADILLO5X0 1260
#define MACH_TYPE_CC9P9360JS 1264
-#define MACH_TYPE_SMDK6400 1270
#define MACH_TYPE_NOKIA_N800 1271
#define MACH_TYPE_EP80219 1281
#define MACH_TYPE_GORAMO_MLR 1292
# define machine_is_cc9p9360js() (0)
#endif
-#ifdef CONFIG_MACH_SMDK6400
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SMDK6400
-# endif
-# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400)
-#else
-# define machine_is_smdk6400() (0)
-#endif
-
#ifdef CONFIG_MACH_NOKIA_N800
# ifdef machine_arch_type
# undef machine_arch_type
#include <config.h>
#include <asm-offsets.h>
+#include <linux/linkage.h>
/*
* This file handles the target-independent stages of the U-Boot
* have some work left to do at this point regarding memory, so
* call c_runtime_cpu_setup.
*
- * 6. Branch to either nand_boot() or board_init_r().
+ * 6. Branch to board_init_r().
*/
-/*
- * declare nand_boot() or board_init_r() to jump to at end of crt0
- */
-
-#if defined(CONFIG_NAND_SPL)
-
-.globl nand_boot
-
-#elif ! defined(CONFIG_SPL_BUILD)
-
-.globl board_init_r
-
-#endif
-
-/*
- * start and end of BSS
- */
-
-.globl __bss_start
-.globl __bss_end
-
/*
* entry point of crt0 sequence
*/
-.global _main
-
-_main:
+ENTRY(_main)
/*
* Set up initial C runtime environment and call board_init_f(0).
*/
-#if defined(CONFIG_NAND_SPL)
- /* deprecated, use instead CONFIG_SPL_BUILD */
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
-#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =(CONFIG_SPL_STACK)
#else
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
/*
* Set up intermediate environment (new sp and gd) and call
- * relocate_code(addr_sp, gd, addr_moni). Trick here is that
- * we'll return 'here' but relocated.
+ * relocate_code(addr_moni). Trick here is that we'll return
+ * 'here' but relocated.
*/
ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */
adr lr, here
ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */
add lr, lr, r0
- ldr r0, [r8, #GD_START_ADDR_SP] /* r0 = gd->start_addr_sp */
- mov r1, r8 /* r1 = gd */
- ldr r2, [r8, #GD_RELOCADDR] /* r2 = gd->relocaddr */
+ ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
here:
bl coloured_LED_init
bl red_led_on
-#if defined(CONFIG_NAND_SPL)
-
- /* call _nand_boot() */
- ldr pc, =nand_boot
-
-#else
-
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov r0, r8 /* gd_t */
ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */
/* call board_init_r */
ldr pc, =board_init_r /* this is auto-relocated! */
-#endif
-
/* we should not return here. */
#endif
+
+ENDPROC(_main)
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
.text :
{
__start = .;
- arch/arm/cpu/arm926ejs/start.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
.text :
{
__start = .;
- arch/arm/cpu/arm926ejs/start.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
.text :
{
- arch/arm/cpu/arm926ejs/start.o (.text)
- arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text)
- drivers/mtd/nand/libnand.o (.text)
+ arch/arm/cpu/arm926ejs/start.o (.text*)
+ arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*)
+ drivers/mtd/nand/libnand.o (.text*)
*(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
.data : {
}
. = ALIGN(4);
+ __image_copy_end = .;
__rel_dyn_start = .;
__rel_dyn_end = .;
__dynsym_start = .;
}
. = ALIGN (4);
+
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/arm/cpu/arm1136/start.o (.text)
- board/freescale/mx31ads/libmx31ads.o (.text)
- arch/arm/lib/libarm.o (.text)
- net/libnet.o (.text)
- drivers/mtd/libmtd.o (.text)
+ arch/arm/cpu/arm1136/start.o (.text*)
+ board/freescale/mx31ads/libmx31ads.o (.text*)
+ arch/arm/lib/libarm.o (.text*)
+ net/libnet.o (.text*)
+ drivers/mtd/libmtd.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o(.text)
+ common/env_embedded.o(.text*)
- *(.text)
+ *(.text*)
}
. = ALIGN(4);
- .rodata : { *(.rodata) }
+ .rodata : { *(.rodata*) }
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
LIB = $(obj)lib$(BOARD).o
+ifdef CONFIG_SPL_BUILD
+SOBJS := lowlevel_init.o
+endif
COBJS := mx31pdk.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+++ /dev/null
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x87ec0000
-else
-CONFIG_SYS_TEXT_BASE = 0x87f00000
-endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ relocate_code(CONFIG_SPL_TEXT_BASE);
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
}
+#ifdef CONFIG_NAND_MXC
+static void setup_iomux_nand(void)
+{
+ u32 i, reg;
+ #define M4IF_GENP_WEIM_MM_MASK 0x00000001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
+
+ reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
+ reg &= ~M4IF_GENP_WEIM_MM_MASK;
+ __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
+ for (i = 0x4; i < 0x94; i += 0x18) {
+ reg = __raw_readl(WEIM_BASE_ADDR + i);
+ reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
+ __raw_writel(reg, WEIM_BASE_ADDR + i);
+ }
+
+ mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
+ mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+ mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
+ PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
+}
+#else
+static void setup_iomux_nand(void)
+{
+}
+#endif
+
static void setup_iomux_uart(void)
{
/* UART1 RXD */
int board_early_init_f(void)
{
+ setup_iomux_nand();
setup_iomux_uart();
return 0;
}
LIB = $(obj)lib$(BOARD).o
-COBJS := tx25.o
+ifdef CONFIG_SPL_BUILD
SOBJS := lowlevel_init.o
+endif
+COBJS := tx25.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
+++ /dev/null
-ifdef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = 0x810c0000
-else
-CONFIG_SYS_TEXT_BASE = 0x81200000
-endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong bootflag)
+{
+ relocate_code(CONFIG_SPL_TEXT_BASE);
+ asm volatile("ldr pc, =nand_boot");
+}
+#endif
+
#ifdef CONFIG_FEC_MXC
#define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7)
#define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9)
.text :
{
__start = .;
- arch/arm/cpu/armv7/start.o (.text)
+ arch/arm/cpu/armv7/start.o (.text*)
*(.text*)
} >.sram
. = ALIGN(4);
+++ /dev/null
-#
-# Generated files
-#
-
-/config.tmp
+++ /dev/null
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS-y := smdk6400.o
-SOBJS := lowlevel_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(SOBJS) $(OBJS)
- $(call cmd_link_o_target, $(SOBJS) $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-
-# On SMDK6400 we use the 64 MB SDRAM bank at
-#
-# 0x50000000 to 0x58000000
-#
-# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000
-#
-# we load ourselves to 0x57e00000 without MMU
-# with MMU, load address is changed to 0xc7e00000
-#
-# download area is 0x5000c000
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-ifndef CONFIG_NAND_SPL
-CONFIG_SYS_TEXT_BASE = $(RAM_TEXT)
-else
-CONFIG_SYS_TEXT_BASE = 0
-endif
+++ /dev/null
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <config.h>
-#include <version.h>
-
-#include <asm/arch/s3c6400.h>
-
-#ifdef CONFIG_SERIAL1
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
-#elif defined(CONFIG_SERIAL2)
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
-#else
-#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
-#endif
-
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
- .globl lowlevel_init
-lowlevel_init:
- mov r12, lr
-
- /* LED on only #8 */
- ldr r0, =ELFIN_GPIO_BASE
- ldr r1, =0x55540000
- str r1, [r0, #GPNCON_OFFSET]
-
- ldr r1, =0x55555555
- str r1, [r0, #GPNPUD_OFFSET]
-
- ldr r1, =0xf000
- str r1, [r0, #GPNDAT_OFFSET]
-
- /* Disable Watchdog */
- ldr r0, =0x7e000000 @0x7e004000
- orr r0, r0, #0x4000
- mov r1, #0
- str r1, [r0]
-
- /* External interrupt pending clear */
- ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
- ldr r1, [r0]
- str r1, [r0]
-
- ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
- ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
-
- /* Disable all interrupts (VIC0 and VIC1) */
- mvn r3, #0x0
- str r3, [r0, #oINTMSK]
- str r3, [r1, #oINTMSK]
-
- /* Set all interrupts as IRQ */
- mov r3, #0x0
- str r3, [r0, #oINTMOD]
- str r3, [r1, #oINTMOD]
-
- /* Pending Interrupt Clear */
- mov r3, #0x0
- str r3, [r0, #oVECTADDR]
- str r3, [r1, #oVECTADDR]
-
- /* init system clock */
- bl system_clock_init
-
-#ifndef CONFIG_NAND_SPL
- /* for UART */
- bl uart_asm_init
-#endif
-
-#ifdef CONFIG_BOOT_NAND
- /* simple init for NAND */
- bl nand_asm_init
-#endif
-
- /* Memory subsystem address 0x7e00f120 */
- ldr r0, =ELFIN_MEM_SYS_CFG
-
- /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */
- mov r1, #S3C64XX_MEM_SYS_CFG_NAND
- str r1, [r0]
-
- bl mem_ctrl_asm_init
-
-/* Wakeup support. Don't know if it's going to be used, untested. */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
- ldr r1, [r0]
- bic r1, r1, #0xfffffff7
- cmp r1, #0x8
- beq wakeup_reset
-
-1:
- mov lr, r12
- mov pc, lr
-
-wakeup_reset:
-
- /* Clear wakeup status register */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
- ldr r1, [r0]
- str r1, [r0]
-
- /* LED test */
- ldr r0, =ELFIN_GPIO_BASE
- ldr r1, =0x3000
- str r1, [r0, #GPNDAT_OFFSET]
-
- /* Load return address and jump to kernel */
- ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
- /* r1 = physical address of s3c6400_cpu_resume function */
- ldr r1, [r0]
- /* Jump to kernel (sleep-s3c6400.S) */
- mov pc, r1
- nop
- nop
-/*
- * system_clock_init: Initialize core clock and bus clock.
- * void system_clock_init(void)
- */
-system_clock_init:
- ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
-
-#ifdef CONFIG_SYNC_MODE
- ldr r1, [r0, #OTHERS_OFFSET]
- mov r2, #0x40
- orr r1, r1, r2
- str r1, [r0, #OTHERS_OFFSET]
-
- nop
- nop
- nop
- nop
- nop
-
- ldr r2, =0x80
- orr r1, r1, r2
- str r1, [r0, #OTHERS_OFFSET]
-
-check_syncack:
- ldr r1, [r0, #OTHERS_OFFSET]
- ldr r2, =0xf00
- and r1, r1, r2
- cmp r1, #0xf00
- bne check_syncack
-#else /* ASYNC Mode */
- nop
- nop
- nop
- nop
- nop
-
- /*
- * This was unconditional in original Samsung sources, but it doesn't
- * seem to make much sense on S3C6400.
- */
-#ifndef CONFIG_S3C6400
- ldr r1, [r0, #OTHERS_OFFSET]
- bic r1, r1, #0xC0
- orr r1, r1, #0x40
- str r1, [r0, #OTHERS_OFFSET]
-
-wait_for_async:
- ldr r1, [r0, #OTHERS_OFFSET]
- and r1, r1, #0xf00
- cmp r1, #0x0
- bne wait_for_async
-#endif
-
- ldr r1, [r0, #OTHERS_OFFSET]
- bic r1, r1, #0x40
- str r1, [r0, #OTHERS_OFFSET]
-#endif
-
- mov r1, #0xff00
- orr r1, r1, #0xff
- str r1, [r0, #APLL_LOCK_OFFSET]
- str r1, [r0, #MPLL_LOCK_OFFSET]
-
- /* Set Clock Divider */
- ldr r1, [r0, #CLK_DIV0_OFFSET]
- bic r1, r1, #0x30000
- bic r1, r1, #0xff00
- bic r1, r1, #0xff
- ldr r2, =CLK_DIV_VAL
- orr r1, r1, r2
- str r1, [r0, #CLK_DIV0_OFFSET]
-
- ldr r1, =APLL_VAL
- str r1, [r0, #APLL_CON_OFFSET]
- ldr r1, =MPLL_VAL
- str r1, [r0, #MPLL_CON_OFFSET]
-
- /* FOUT of EPLL is 96MHz */
- ldr r1, =0x200203
- str r1, [r0, #EPLL_CON0_OFFSET]
- ldr r1, =0x0
- str r1, [r0, #EPLL_CON1_OFFSET]
-
- /* APLL, MPLL, EPLL select to Fout */
- ldr r1, [r0, #CLK_SRC_OFFSET]
- orr r1, r1, #0x7
- str r1, [r0, #CLK_SRC_OFFSET]
-
- /* wait at least 200us to stablize all clock */
- mov r1, #0x10000
-1: subs r1, r1, #1
- bne 1b
-
- /* Synchronization for VIC port */
-#if defined(CONFIG_SYNC_MODE)
- ldr r1, [r0, #OTHERS_OFFSET]
- orr r1, r1, #0x20
- str r1, [r0, #OTHERS_OFFSET]
-#elif !defined(CONFIG_S3C6400)
- /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
- ldr r1, [r0, #OTHERS_OFFSET]
- bic r1, r1, #0x20
- str r1, [r0, #OTHERS_OFFSET]
-#endif
- mov pc, lr
-
-
-#ifndef CONFIG_NAND_SPL
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
- /* set GPIO to enable UART */
- ldr r0, =ELFIN_GPIO_BASE
- ldr r1, =0x220022
- str r1, [r0, #GPACON_OFFSET]
- mov pc, lr
-#endif
-
-#ifdef CONFIG_BOOT_NAND
-/*
- * NAND Interface init for SMDK6400
- */
-nand_asm_init:
- ldr r0, =ELFIN_NAND_BASE
- ldr r1, [r0, #NFCONF_OFFSET]
- orr r1, r1, #0x70
- orr r1, r1, #0x7700
- str r1, [r0, #NFCONF_OFFSET]
-
- ldr r1, [r0, #NFCONT_OFFSET]
- orr r1, r1, #0x07
- str r1, [r0, #NFCONT_OFFSET]
-
- mov pc, lr
-#endif
-
-#ifdef CONFIG_ENABLE_MMU
-/*
- * MMU Table for SMDK6400
- */
-
- /* form a first-level section entry */
-.macro FL_SECTION_ENTRY base,ap,d,c,b
- .word (\base << 20) | (\ap << 10) | \
- (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
-.endm
-
-.section .mmudata, "a"
- .align 14
- /* the following alignment creates the mmu table at address 0x4000. */
- .globl mmu_table
-mmu_table:
- .set __base, 0
- /* 1:1 mapping for debugging */
- .rept 0xA00
- FL_SECTION_ENTRY __base, 3, 0, 0, 0
- .set __base, __base + 1
- .endr
-
- /* access is not allowed. */
- .rept 0xC00 - 0xA00
- .word 0x00000000
- .endr
-
- /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
- .set __base, 0x500
- .rept 0xC80 - 0xC00
- FL_SECTION_ENTRY __base, 3, 0, 1, 1
- .set __base, __base + 1
- .endr
-
- /* access is not allowed. */
- .rept 0x1000 - 0xc80
- .word 0x00000000
- .endr
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/s3c6400.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-#define CS8900_Tacs 0x0 /* 0clk address set-up */
-#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */
-#define CS8900_Tacc 0xE /* 14clk access cycle */
-#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */
-#define CS8900_Tah 0x4 /* 4clk address holding time */
-#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */
-#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */
-
-static inline void delay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b"
- : "=r" (loops) : "0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-static void cs8900_pre_init(void)
-{
- SROM_BW_REG &= ~(0xf << 4);
- SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4);
- SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) +
- (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) +
- (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC);
-}
-
-int board_init(void)
-{
- cs8900_pre_init();
-
- /* NOR-flash in SROM0 */
-
- /* Enable WAIT */
- SROM_BW_REG |= 4 | 8 | 1;
-
- gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
- return 0;
-}
-
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-}
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
- PHYS_SDRAM_1_SIZE);
-
- return 0;
-}
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- printf("Board: SMDK6400\n");
- return 0;
-}
-#endif
-
-#ifdef CONFIG_ENABLE_MMU
-ulong virt_to_phy_smdk6400(ulong addr)
-{
- if ((0xc0000000 <= addr) && (addr < 0xc8000000))
- return addr - 0xc0000000 + 0x50000000;
- else
- printf("do not support this address : %08lx\n", addr);
-
- return addr;
-}
-#endif
-
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = FLASH_CFI_16BIT;
- info->chipwidth = FLASH_CFI_BY16;
- info->interface = FLASH_CFI_X16;
- return 1;
- } else
- return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_CS8900
- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
- return rc;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-void board_init_f(unsigned long bootflag)
-{
- relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
- CONFIG_SYS_TEXT_BASE);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- arch/arm/cpu/arm1176/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
-
- . = align(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = align(4);
- .mmudata : { *(.mmudata) }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
. = ALIGN(4);
.data : {
- *(.data)
+ *(.data*)
}
. = ALIGN(4);
+ __image_copy_end = .;
+
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
.bss __rel_dyn_start (OVERLAY) : {
__bss_start = .;
- *(.bss)
+ *(.bss*)
. = ALIGN(4);
__bss_end = .;
}
imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
qong arm arm1136 - davedenx mx31
mx31ads arm arm1136 - freescale mx31
-mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT
+mx31pdk arm arm1136 - freescale mx31
tt01 arm arm1136 - hale mx31
imx31_litekit arm arm1136 - logicpd mx31
flea3 arm arm1136 - CarMediaLab mx35
#########################################################################
+# Set shell to bash if possible, otherwise fall back to sh
+SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
+ else if [ -x /bin/bash ]; then echo /bin/bash; \
+ else echo sh; fi; fi)
+
+export SHELL
+
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
-----------------------------------------------------------------------------
-For boards which boot from nand_spl, it is possible to save one copy
+For boards which boot from spl, it is possible to save one copy
if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
is copied again in relocate_code().
-example for the tx25 board:
+example for the tx25 board booting from NAND Flash:
a) cpu starts
b) it copies the first page in nand to internal ram
- (nand_spl_code)
+ (spl code)
c) end executes this code
d) this initialize CPU, RAM, ... and copy itself to RAM
(this bin must fit in one page, so board_init_f()
-----------------------------------------------------------------------------
-Relocation with NAND_SPL (example for the tx25):
+Relocation with SPL (example for the tx25 booting from NAND Flash):
- cpu copies the first page from NAND to 0xbb000000 (IMX_NFC_BASE)
and start with code execution on this address.
-- The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c
- which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads
+- The First page contains u-boot code from drivers/mtd/nand/mxc_nand_spl.c
+ which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads
the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
@CONFIG_SYS_NAND_U_BOOT_START
- This u-boot does no RAM init, nor CPU register setup. Just look
where it has to copy and relocate itself to this address. If
relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the
- CONFIG_SYS_TEXT_BASE from the nand_spl code), then there is no need
+ CONFIG_SPL_TEXT_BASE from the spl code), then there is no need
to copy, just go on with bss clear and jump to board_init_r.
-----------------------------------------------------------------------------
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+smdk6400 arm arm1176 - - Zhong Hongbo <bocui107@gmail.com>
ns9750dev arm arm926ejs - - Markus Pietrek <mpietrek@fsforth.de>
AMX860 powerpc mpc860 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
c2mon powerpc mpc855 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de>
------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 10) s3c64xx.c
+ 10) sandbox.c
-------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 11) sandbox.c
- -------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- 12) serial.c
+ 11) serial.c
------------
This is a complementary part of NS16550 UART driver, see above.
- 13) serial_clps7111.c
+ 12) serial_clps7111.c
---------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 14) serial_imx.c
+ 13) serial_imx.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver
might be removed in favor of serial_mxc.c .
- 15) serial_ixp.c
+ 14) serial_ixp.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 16) serial_ks8695.c
+ 15) serial_ks8695.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 17) serial_max3100.c
+ 16) serial_max3100.c
--------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 18) serial_mxc.c
+ 17) serial_mxc.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 19) serial_netarm.c
+ 18) serial_netarm.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 20) serial_pl01x.c
+ 19) serial_pl01x.c
------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this
driver in fact contains two drivers in total.
- 21) serial_pxa.c
+ 20) serial_pxa.c
----------------
This driver is a bit complicated, but due to clean support for
CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the
conversion process.
- 22) serial_s3c24x0.c
+ 21) serial_s3c24x0.c
--------------------
This driver, being quite ad-hoc might need some work to bring back to shape.
- 23) serial_s3c44b0.c
+ 22) serial_s3c44b0.c
--------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 24) serial_s5p.c
+ 23) serial_s5p.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 25) serial_sa1100.c
+ 24) serial_sa1100.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 26) serial_sh.c
+ 25) serial_sh.c
---------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 27) serial_xuartlite.c
+ 26) serial_xuartlite.c
----------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 28) usbtty.c
+ 27) usbtty.c
------------
This driver seems very complicated and entangled with USB framework. The
conversion might be complicated here.
- 29) arch/powerpc/cpu/mpc512x/serial.c
+ 28) arch/powerpc/cpu/mpc512x/serial.c
-------------------------------------
This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
proper place.
---------------------------
-What: boards with xxx_config targets in top level Makefile
-When: Release v2012.03
-
-Why: We have a boards.cfg file which the vast majority of boards have
- converted over to. Boards that still manually run mkconfig in the
- top level Makefile are either dead, or the maintainer doesn't care,
- or they are doing something weird/wrong that should be fixed in a
- different way, or they need to extend boards.cfg syntax (unlikely).
-
- In any case, if no one cares about these boards to figure out how
- to make boards.cfg work, then we'll just punt them.
-
-Who: Mike Frysinger <vapier@gentoo.org>
-
----------------------------
-
What: GPL cleanup
When: August 2009
Why: Over time, a couple of files have sneaked in into the U-Boot
COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
-COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o
COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
else # minimal SPL drivers
COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
+COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
endif # drivers
endif # nand
#include <nand.h>
#include <linux/err.h>
#include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
+ defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
-#include <fsl_nfc.h>
+#include "mxc_nand.h"
#define DRIVER_NAME "mxc_nand"
struct mtd_info mtd;
struct nand_chip *nand;
- struct fsl_nfc_regs __iomem *regs;
+ struct mxc_nand_regs __iomem *regs;
+#ifdef MXC_NFC_V3_2
+ struct mxc_nand_ip_regs __iomem *ip_regs;
+#endif
int spare_only;
int status_request;
int pagesize_2k;
.oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
};
#endif
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
#ifndef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout nand_hw_eccoob = {
.eccbytes = 9,
#endif
#endif
-#ifdef CONFIG_MX27
static int is_16bit_nand(void)
{
- struct system_control_regs *sc_regs =
- (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
-
- if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
- return 1;
- else
- return 0;
-}
-#elif defined(CONFIG_MX31)
-static int is_16bit_nand(void)
-{
- struct clock_control_regs *sc_regs =
- (struct clock_control_regs *)CCM_BASE;
-
- if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
- return 1;
- else
- return 0;
-}
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-static int is_16bit_nand(void)
-{
- struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
- if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
- return 1;
- else
- return 0;
-}
+#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
+ return 1;
#else
-#warning "8/16 bit NAND autodetection not supported"
-static int is_16bit_nand(void)
-{
return 0;
-}
#endif
+}
static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
{
/*
* This function polls the NANDFC to wait for the basic operation to
- * complete by checking the INT bit of config2 register.
+ * complete by checking the INT bit.
*/
static void wait_op_done(struct mxc_nand_host *host, int max_retries,
uint16_t param)
uint32_t tmp;
while (max_retries-- > 0) {
- if (readw(&host->regs->config2) & NFC_INT) {
- tmp = readw(&host->regs->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &host->regs->config2);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ tmp = readnfc(&host->regs->config2);
+ if (tmp & NFC_V1_V2_CONFIG2_INT) {
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &host->regs->config2);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(&host->ip_regs->ipc);
+ if (tmp & NFC_V3_IPC_INT) {
+ tmp &= ~NFC_V3_IPC_INT;
+ writenfc(tmp, &host->ip_regs->ipc);
+#endif
break;
}
udelay(1);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
- writew(cmd, &host->regs->flash_cmd);
- writew(NFC_CMD, &host->regs->config2);
+ writenfc(cmd, &host->regs->flash_cmd);
+ writenfc(NFC_CMD, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, cmd);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
- writew(addr, &host->regs->flash_addr);
- writew(NFC_ADDR, &host->regs->config2);
+ writenfc(addr, &host->regs->flash_addr);
+ writenfc(NFC_ADDR, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, addr);
if (spare_only)
MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
* The controller copies the 64 bytes of spare data from
}
}
- writew(buf_id, &host->regs->buf_addr);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(buf_id, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint16_t config1 = readw(&host->regs->config1);
+ uint32_t config1 = readnfc(&host->regs->config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
+ config1 &= ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, &host->regs->config1);
}
- writew(NFC_INPUT, &host->regs->config2);
+ writenfc(NFC_INPUT, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
{
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
- writew(buf_id, &host->regs->buf_addr);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(buf_id, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ tmp |= NFC_V3_CONFIG1_RBA(buf_id);
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Configure spare or page+spare access */
if (!host->pagesize_2k) {
- uint32_t config1 = readw(&host->regs->config1);
+ uint32_t config1 = readnfc(&host->regs->config1);
if (spare_only)
- config1 |= NFC_SP_EN;
+ config1 |= NFC_CONFIG1_SP_EN;
else
- config1 &= ~NFC_SP_EN;
- writew(config1, &host->regs->config1);
+ config1 &= ~NFC_CONFIG1_SP_EN;
+ writenfc(config1, &host->regs->config1);
}
- writew(NFC_OUTPUT, &host->regs->config2);
+ writenfc(NFC_OUTPUT, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, spare_only);
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
int i;
/*
/* Request the NANDFC to perform a read of the NAND device ID. */
static void send_read_id(struct mxc_nand_host *host)
{
- uint16_t tmp;
+ uint32_t tmp;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/* NANDFC buffer 0 is used for device ID output */
- writew(0x0, &host->regs->buf_addr);
+ writenfc(0x0, &host->regs->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(tmp, &host->regs->config1);
+#endif
/* Read ID into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_CONFIG1_SP_EN;
+ writenfc(tmp, &host->regs->config1);
- writew(NFC_ID, &host->regs->config2);
+ writenfc(NFC_ID, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
*/
static uint16_t get_dev_status(struct mxc_nand_host *host)
{
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
void __iomem *main_buf = host->regs->main_area[1];
uint32_t store;
- uint16_t ret, tmp;
+#endif
+ uint32_t ret, tmp;
/* Issue status request to NAND device */
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/* store the main area1 first word, later do recovery */
store = readl(main_buf);
/* NANDFC buffer 1 is used for device status */
- writew(1, &host->regs->buf_addr);
+ writenfc(1, &host->regs->buf_addr);
+#endif
/* Read status into main buffer */
- tmp = readw(&host->regs->config1);
- tmp &= ~NFC_SP_EN;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp &= ~NFC_CONFIG1_SP_EN;
+ writenfc(tmp, &host->regs->config1);
- writew(NFC_STATUS, &host->regs->config2);
+ writenfc(NFC_STATUS, &host->regs->operation);
/* Wait for operation to complete */
wait_op_done(host, TROP_US_DELAY, 0);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
/*
* Status is placed in first word of main buffer
* get status, then recovery area 1 data
*/
ret = readw(main_buf);
writel(store, main_buf);
+#elif defined(MXC_NFC_V3_2)
+ ret = readnfc(&host->regs->config1) >> 16;
+#endif
return ret;
}
{
struct nand_chip *nand_chip = mtd->priv;
struct mxc_nand_host *host = nand_chip->priv;
- uint16_t tmp = readw(&host->regs->config1);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ uint16_t tmp = readnfc(&host->regs->config1);
if (on)
- tmp |= NFC_ECC_EN;
+ tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
else
- tmp &= ~NFC_ECC_EN;
- writew(tmp, &host->regs->config1);
+ tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
+ writenfc(tmp, &host->regs->config1);
+#elif defined(MXC_NFC_V3_2)
+ uint32_t tmp = readnfc(&host->ip_regs->config2);
+
+ if (on)
+ tmp |= NFC_V3_CONFIG2_ECC_EN;
+ else
+ tmp &= ~NFC_V3_CONFIG2_ECC_EN;
+ writenfc(tmp, &host->ip_regs->config2);
+#endif
}
#ifdef CONFIG_MXC_NAND_HWECC
*/
}
-#ifdef MXC_NFC_V2_1
+#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
struct nand_chip *chip,
int page, int sndcmd)
MTDDEBUG(MTD_DEBUG_LEVEL0,
"%s: Reading OOB area of page %u to oob %p\n",
- __FUNCTION__, host->page_addr, buf);
+ __func__, page, buf);
chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
for (i = 0; i < chip->ecc.steps; i++) {
int n;
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
host->col_addr = n * eccsize;
uint8_t *oob = chip->oob_poi;
MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
- host->page_addr, buf, oob);
+ page, buf, oob);
/* first read the data area and the available portion of OOB */
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
/* Then switch ECC off and read the OOB area to get the ECC code */
_mxc_nand_enable_hwecc(mtd, 0);
- chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
eccsteps = chip->ecc.steps;
oob = chip->oob_poi + chip->ecc.prepad;
for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
* additional correction. 2-Bit errors cannot be corrected by
* HW ECC, so we need to return failure
*/
- uint16_t ecc_status = readw(&host->regs->ecc_status_result);
+ uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
MTDDEBUG(MTD_DEBUG_LEVEL0,
int board_nand_init(struct nand_chip *this)
{
struct mtd_info *mtd;
-#ifdef MXC_NFC_V2_1
- uint16_t tmp;
+#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
+ uint32_t tmp;
#endif
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
this->read_buf = mxc_nand_read_buf;
this->verify_buf = mxc_nand_verify_buf;
- host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+ host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
+#ifdef MXC_NFC_V3_2
+ host->ip_regs =
+ (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
+#endif
host->clk_act = 1;
#ifdef CONFIG_MXC_NAND_HWECC
this->ecc.calculate = mxc_nand_calculate_ecc;
this->ecc.hwctl = mxc_nand_enable_hwecc;
this->ecc.correct = mxc_nand_correct_data;
- if (is_mxc_nfc_21()) {
+ if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
this->ecc.mode = NAND_ECC_HW_SYNDROME;
this->ecc.read_page = mxc_nand_read_page_syndrome;
this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
this->ecc.layout = &nand_hw_eccoob;
#endif
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
#ifdef MXC_NFC_V2_1
- tmp = readw(&host->regs->config1);
- tmp |= NFC_ONE_CYCLE;
- tmp |= NFC_4_8N_ECC;
- writew(tmp, &host->regs->config1);
+ tmp = readnfc(&host->regs->config1);
+ tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
+ tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
+ writenfc(tmp, &host->regs->config1);
if (host->pagesize_2k)
- writew(64/2, &host->regs->spare_area_size);
+ writenfc(64/2, &host->regs->spare_area_size);
else
- writew(16/2, &host->regs->spare_area_size);
+ writenfc(16/2, &host->regs->spare_area_size);
#endif
/*
* preset operation
* Unlock the internal RAM Buffer
*/
- writew(0x2, &host->regs->config);
+ writenfc(0x2, &host->regs->config);
/* Blocks to be unlocked */
- writew(0x0, &host->regs->unlockstart_blkaddr);
+ writenfc(0x0, &host->regs->unlockstart_blkaddr);
/* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
* unlockend_blkaddr, but the magic 0x4000 does not always work
* when writing more than some 32 megabytes (on 2k page nands)
* This might be NAND chip specific and the i.MX31 datasheet is
* extremely vague about the semantics of this register.
*/
- writew(0xFFFF, &host->regs->unlockend_blkaddr);
+ writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
/* Unlock Block Command for given address range */
- writew(0x4, &host->regs->wrprot);
+ writenfc(0x4, &host->regs->wrprot);
+#elif defined(MXC_NFC_V3_2)
+ writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
+ writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
+
+ /* Unlock the internal RAM Buffer */
+ writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
+ &host->ip_regs->wrprot);
+
+ /* Blocks to be unlocked */
+ for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
+ writenfc(0x0 | 0xFFFF << 16,
+ &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
+
+ writenfc(0, &host->ip_regs->ipc);
+
+ tmp = readnfc(&host->ip_regs->config2);
+ tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
+ NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
+ tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
+
+ if (host->pagesize_2k) {
+ tmp |= NFC_V3_CONFIG2_SPAS(64/2);
+ tmp |= NFC_V3_CONFIG2_PS_2048;
+ } else {
+ tmp |= NFC_V3_CONFIG2_SPAS(16/2);
+ tmp |= NFC_V3_CONFIG2_PS_512;
+ }
+
+ writenfc(tmp, &host->ip_regs->config2);
+
+ tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
+ NFC_V3_CONFIG3_NO_SDMA |
+ NFC_V3_CONFIG3_RBB_MODE |
+ NFC_V3_CONFIG3_SBB(6) | /* Reset default */
+ NFC_V3_CONFIG3_ADD_OP(0);
+
+ if (!(this->options & NAND_BUSWIDTH_16))
+ tmp |= NFC_V3_CONFIG3_FW8;
+
+ writenfc(tmp, &host->ip_regs->config3);
+
+ writenfc(0, &host->ip_regs->delay_line);
+#endif
return 0;
}
--- /dev/null
+/*
+ * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MXC_NAND_H
+#define __MXC_NAND_H
+
+/*
+ * Register map and bit definitions for the Freescale NAND Flash Controller
+ * present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1, which has:
+ * 4 512-byte main buffers and
+ * 4 16-byte spare buffers
+ * to support up to 2K byte pagesize nand.
+ * Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which
+ * have:
+ * 8 512-byte main buffers and
+ * 8 64-byte spare buffers
+ * to support up to 4K byte pagesize nand.
+ * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ * Also some of registers are moved and/or changed meaning as seen below.
+ */
+#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
+#define MXC_NFC_V1
+#define is_mxc_nfc_1() 1
+#define is_mxc_nfc_21() 0
+#define is_mxc_nfc_32() 0
+#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#define MXC_NFC_V2_1
+#define is_mxc_nfc_1() 0
+#define is_mxc_nfc_21() 1
+#define is_mxc_nfc_32() 0
+#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#define MXC_NFC_V3
+#define MXC_NFC_V3_2
+#define is_mxc_nfc_1() 0
+#define is_mxc_nfc_21() 0
+#define is_mxc_nfc_32() 1
+#else
+#error "MXC NFC implementation not supported"
+#endif
+#define is_mxc_nfc_3() is_mxc_nfc_32()
+
+#if defined(MXC_NFC_V1)
+#define NAND_MXC_NR_BUFS 4
+#define NAND_MXC_SPARE_BUF_SIZE 16
+#define NAND_MXC_REG_OFFSET 0xe00
+#define NAND_MXC_2K_MULTI_CYCLE
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
+#define NAND_MXC_NR_BUFS 8
+#define NAND_MXC_SPARE_BUF_SIZE 64
+#define NAND_MXC_REG_OFFSET 0x1e00
+#endif
+
+struct mxc_nand_regs {
+ u8 main_area[NAND_MXC_NR_BUFS][0x200];
+ u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
+ /*
+ * reserved size is offset of nfc registers
+ * minus total main and spare sizes
+ */
+ u8 reserved1[NAND_MXC_REG_OFFSET
+ - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(MXC_NFC_V1)
+ u16 buf_size;
+ u16 reserved2;
+ u16 buf_addr;
+ u16 flash_addr;
+ u16 flash_cmd;
+ u16 config;
+ u16 ecc_status_result;
+ u16 rsltmain_area;
+ u16 rsltspare_area;
+ u16 wrprot;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
+#elif defined(MXC_NFC_V2_1)
+ u16 reserved2[2];
+ u16 buf_addr;
+ u16 flash_addr;
+ u16 flash_cmd;
+ u16 config;
+ u32 ecc_status_result;
+ u16 spare_area_size;
+ u16 wrprot;
+ u16 reserved3[2];
+ u16 nf_wrprst;
+ u16 config1;
+ u16 config2;
+ u16 reserved4;
+ u16 unlockstart_blkaddr;
+ u16 unlockend_blkaddr;
+ u16 unlockstart_blkaddr1;
+ u16 unlockend_blkaddr1;
+ u16 unlockstart_blkaddr2;
+ u16 unlockend_blkaddr2;
+ u16 unlockstart_blkaddr3;
+ u16 unlockend_blkaddr3;
+#elif defined(MXC_NFC_V3_2)
+ u32 flash_cmd;
+ u32 flash_addr[12];
+ u32 config1;
+ u32 ecc_status_result;
+ u32 status_sum;
+ u32 launch;
+#endif
+};
+
+#ifdef MXC_NFC_V3_2
+struct mxc_nand_ip_regs {
+ u32 wrprot;
+ u32 wrprot_unlock_blkaddr[8];
+ u32 config2;
+ u32 config3;
+ u32 ipc;
+ u32 err_addr;
+ u32 delay_line;
+};
+#endif
+
+/* Set FCMD to 1, rest to 0 for Command operation */
+#define NFC_CMD 0x1
+
+/* Set FADD to 1, rest to 0 for Address operation */
+#define NFC_ADDR 0x2
+
+/* Set FDI to 1, rest to 0 for Input operation */
+#define NFC_INPUT 0x4
+
+/* Set FDO to 001, rest to 0 for Data Output operation */
+#define NFC_OUTPUT 0x8
+
+/* Set FDO to 010, rest to 0 for Read ID operation */
+#define NFC_ID 0x10
+
+/* Set FDO to 100, rest to 0 for Read Status operation */
+#define NFC_STATUS 0x20
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+#define NFC_CONFIG1_SP_EN (1 << 2)
+#define NFC_CONFIG1_RST (1 << 6)
+#define NFC_CONFIG1_CE (1 << 7)
+#elif defined(MXC_NFC_V3_2)
+#define NFC_CONFIG1_SP_EN (1 << 0)
+#define NFC_CONFIG1_CE (1 << 1)
+#define NFC_CONFIG1_RST (1 << 2)
+#endif
+#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
+#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
+#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
+#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
+#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
+#define NFC_V2_CONFIG1_FP_INT (1 << 11)
+#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4)
+#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4)
+
+#define NFC_V1_V2_CONFIG2_INT (1 << 15)
+#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0)
+#define NFC_V3_CONFIG2_PS_512 (0 << 0)
+#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
+#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
+#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
+#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
+#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
+#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5)
+#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
+#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7)
+#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
+#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9)
+#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9)
+#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12)
+#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
+#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16)
+#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
+#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24)
+#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
+
+#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
+#define NFC_V3_CONFIG3_FW8 (1 << 3)
+#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
+#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12)
+#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
+#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
+
+#define NFC_V3_WRPROT_UNLOCK (1 << 2)
+#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
+
+#define NFC_V3_IPC_CREQ (1 << 0)
+#define NFC_V3_IPC_INT (1 << 31)
+
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+#define operation config2
+#define readnfc readw
+#define writenfc writew
+#elif defined(MXC_NFC_V3_2)
+#define operation launch
+#define readnfc readl
+#define writenfc writel
+#endif
+
+#endif /* __MXC_NAND_H */
#include <nand.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
-#include <fsl_nfc.h>
+#include "mxc_nand.h"
-static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR;
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR;
+#elif defined(MXC_NFC_V3_2)
+static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI;
+static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR;
+#endif
static void nfc_wait_ready(void)
{
uint32_t tmp;
- while (!(readw(&nfc->config2) & NFC_INT))
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT))
+ ;
+
+ /* Reset interrupt flag */
+ tmp = readnfc(&nfc->config2);
+ tmp &= ~NFC_V1_V2_CONFIG2_INT;
+ writenfc(tmp, &nfc->config2);
+#elif defined(MXC_NFC_V3_2)
+ while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT))
;
/* Reset interrupt flag */
- tmp = readw(&nfc->config2);
- tmp &= ~NFC_INT;
- writew(tmp, &nfc->config2);
+ tmp = readnfc(&nfc_ip->ipc);
+ tmp &= ~NFC_V3_IPC_INT;
+ writenfc(tmp, &nfc_ip->ipc);
+#endif
}
static void nfc_nand_init(void)
{
-#if defined(MXC_NFC_V2_1)
+#if defined(MXC_NFC_V3_2)
+ int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+ int tmp;
+
+ tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK |
+ NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) |
+ NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) |
+ NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN |
+ NFC_V3_CONFIG2_ONE_CYCLE;
+ if (CONFIG_SYS_NAND_PAGE_SIZE == 4096)
+ tmp |= NFC_V3_CONFIG2_PS_4096;
+ else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048)
+ tmp |= NFC_V3_CONFIG2_PS_2048;
+ else if (CONFIG_SYS_NAND_PAGE_SIZE == 512)
+ tmp |= NFC_V3_CONFIG2_PS_512;
+ /*
+ * if spare size is larger that 16 bytes per 512 byte hunk
+ * then use 8 symbol correction instead of 4
+ */
+ if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
+ tmp |= NFC_V3_CONFIG2_ECC_MODE_8;
+ else
+ tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8;
+ writenfc(tmp, &nfc_ip->config2);
+
+ tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
+ NFC_V3_CONFIG3_NO_SDMA |
+ NFC_V3_CONFIG3_RBB_MODE |
+ NFC_V3_CONFIG3_SBB(6) | /* Reset default */
+ NFC_V3_CONFIG3_ADD_OP(0);
+#ifndef CONFIG_SYS_NAND_BUSWIDTH_16
+ tmp |= NFC_V3_CONFIG3_FW8;
+#endif
+ writenfc(tmp, &nfc_ip->config3);
+
+ writenfc(0, &nfc_ip->delay_line);
+#elif defined(MXC_NFC_V2_1)
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
int config1;
- writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
+ writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */
- writew(0x2, &nfc->config);
+ writenfc(0x2, &nfc->config);
/* hardware ECC checking and correct */
- config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK |
- NFC_ONE_CYCLE | NFC_FP_INT;
+ config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN |
+ NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE |
+ NFC_V2_CONFIG1_FP_INT;
/*
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
*/
- if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16)
- config1 &= ~NFC_4_8N_ECC;
+ if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16)
+ config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4;
else
- config1 |= NFC_4_8N_ECC;
- writew(config1, &nfc->config1);
+ config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
+ writenfc(config1, &nfc->config1);
#elif defined(MXC_NFC_V1)
/* unlocking RAM Buff */
- writew(0x2, &nfc->config);
+ writenfc(0x2, &nfc->config);
/* hardware ECC checking and correct */
- writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1);
+ writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK,
+ &nfc->config1);
#endif
}
static void nfc_nand_command(unsigned short command)
{
- writew(command, &nfc->flash_cmd);
- writew(NFC_CMD, &nfc->config2);
+ writenfc(command, &nfc->flash_cmd);
+ writenfc(NFC_CMD, &nfc->operation);
nfc_wait_ready();
}
static void nfc_nand_address(unsigned short address)
{
- writew(address, &nfc->flash_addr);
- writew(NFC_ADDR, &nfc->config2);
+ writenfc(address, &nfc->flash_addr);
+ writenfc(NFC_ADDR, &nfc->operation);
nfc_wait_ready();
}
int i;
#endif
- writew(0, &nfc->buf_addr);
- writew(NFC_OUTPUT, &nfc->config2);
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(0, &nfc->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ int config1 = readnfc(&nfc->config1);
+ config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(config1, &nfc->config1);
+#endif
+ writenfc(NFC_OUTPUT, &nfc->operation);
nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
/*
* for pages larger than 512 bytes.
*/
for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) {
- writew(i, &nfc->buf_addr);
- writew(NFC_OUTPUT, &nfc->config2);
+ writenfc(i, &nfc->buf_addr);
+ writenfc(NFC_OUTPUT, &nfc->operation);
nfc_wait_ready();
}
#endif
#if defined(MXC_NFC_V1)
u16 ecc_status = readw(&nfc->ecc_status_result);
return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2;
-#elif defined(MXC_NFC_V2_1)
+#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
u32 ecc_status = readl(&nfc->ecc_status_result);
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
- int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4;
+ int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4;
int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512;
do {
static void nfc_nand_read_page(unsigned int page_address)
{
- writew(0, &nfc->buf_addr); /* read in first 0 buffer */
+ /* read in first 0 buffer */
+#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
+ writenfc(0, &nfc->buf_addr);
+#elif defined(MXC_NFC_V3_2)
+ int config1 = readnfc(&nfc->config1);
+ config1 &= ~NFC_V3_CONFIG1_RBA_MASK;
+ writenfc(config1, &nfc->config1);
+#endif
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page_address);
return 0;
}
-#if defined(CONFIG_ARM)
-void board_init_f (ulong bootflag)
-{
- relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
- CONFIG_SYS_TEXT_BASE);
-}
-#endif
-
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
struct nand_chip *chip = mtd->priv;
-#ifdef CONFIG_SYS_NDFC_16BIT
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
return (uint8_t) readw(chip->IO_ADDR_R);
#else
return readb(chip->IO_ADDR_R);
nand->ecc.bytes = 3;
nand->select_chip = ndfc_select_chip;
-#ifdef CONFIG_SYS_NDFC_16BIT
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
nand->options |= NAND_BUSWIDTH_16;
#endif
+++ /dev/null
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * Implementation for U-Boot 1.1.6 by Samsung
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#include <nand.h>
-#include <linux/mtd/nand.h>
-
-#include <asm/arch/s3c6400.h>
-
-#include <asm/io.h>
-#include <asm/errno.h>
-
-#define MAX_CHIPS 2
-static int nand_cs[MAX_CHIPS] = {0, 1};
-
-#ifdef CONFIG_NAND_SPL
-#define printf(arg...) do {} while (0)
-#endif
-
-/* Nand flash definition values by jsgood */
-#ifdef S3C_NAND_DEBUG
-/*
- * Function to print out oob buffer for debugging
- * Written by jsgood
- */
-static void print_oob(const char *header, struct mtd_info *mtd)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- printf("%s:\t", header);
-
- for (i = 0; i < 64; i++)
- printf("%02x ", chip->oob_poi[i]);
-
- printf("\n");
-}
-#endif /* S3C_NAND_DEBUG */
-
-static void s3c_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- int ctrl = readl(NFCONT);
-
- switch (chip) {
- case -1:
- ctrl |= 6;
- break;
- case 0:
- ctrl &= ~2;
- break;
- case 1:
- ctrl &= ~4;
- break;
- default:
- return;
- }
-
- writel(ctrl, NFCONT);
-}
-
-/*
- * Hardware specific access to control-lines function
- * Written by jsgood
- */
-static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if (ctrl & NAND_CLE)
- this->IO_ADDR_W = (void __iomem *)NFCMMD;
- else if (ctrl & NAND_ALE)
- this->IO_ADDR_W = (void __iomem *)NFADDR;
- else
- this->IO_ADDR_W = (void __iomem *)NFDATA;
- if (ctrl & NAND_NCE)
- s3c_nand_select_chip(mtd, *(int *)this->priv);
- else
- s3c_nand_select_chip(mtd, -1);
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-/*
- * Function for checking device ready pin
- * Written by jsgood
- */
-static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
-{
- return !!(readl(NFSTAT) & NFSTAT_RnB);
-}
-
-#ifdef CONFIG_SYS_S3C_NAND_HWECC
-/*
- * This function is called before encoding ecc codes to ready ecc engine.
- * Written by jsgood
- */
-static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
-{
- u_long nfcont, nfconf;
-
- /*
- * The original driver used 4-bit ECC for "new" MLC chips, i.e., for
- * those with non-zero ID[3][3:2], which anyway only holds for ST
- * (Numonyx) chips
- */
- nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT;
-
- writel(nfconf, NFCONF);
-
- /* Initialize & unlock */
- nfcont = readl(NFCONT);
- nfcont |= NFCONT_INITECC;
- nfcont &= ~NFCONT_MECCLOCK;
-
- if (mode == NAND_ECC_WRITE)
- nfcont |= NFCONT_ECC_ENC;
- else if (mode == NAND_ECC_READ)
- nfcont &= ~NFCONT_ECC_ENC;
-
- writel(nfcont, NFCONT);
-}
-
-/*
- * This function is called immediately after encoding ecc codes.
- * This function returns encoded ecc codes.
- * Written by jsgood
- */
-static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
- u_char *ecc_code)
-{
- u_long nfcont, nfmecc0;
-
- /* Lock */
- nfcont = readl(NFCONT);
- nfcont |= NFCONT_MECCLOCK;
- writel(nfcont, NFCONT);
-
- nfmecc0 = readl(NFMECC0);
-
- ecc_code[0] = nfmecc0 & 0xff;
- ecc_code[1] = (nfmecc0 >> 8) & 0xff;
- ecc_code[2] = (nfmecc0 >> 16) & 0xff;
- ecc_code[3] = (nfmecc0 >> 24) & 0xff;
-
- return 0;
-}
-
-/*
- * This function determines whether read data is good or not.
- * If SLC, must write ecc codes to controller before reading status bit.
- * If MLC, status bit is already set, so only reading is needed.
- * If status bit is good, return 0.
- * If correctable errors occured, do that.
- * If uncorrectable errors occured, return -1.
- * Written by jsgood
- */
-static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat,
- u_char *read_ecc, u_char *calc_ecc)
-{
- int ret = -1;
- u_long nfestat0, nfmeccdata0, nfmeccdata1, err_byte_addr;
- u_char err_type, repaired;
-
- /* SLC: Write ecc to compare */
- nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0];
- nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2];
- writel(nfmeccdata0, NFMECCDATA0);
- writel(nfmeccdata1, NFMECCDATA1);
-
- /* Read ecc status */
- nfestat0 = readl(NFESTAT0);
- err_type = nfestat0 & 0x3;
-
- switch (err_type) {
- case 0: /* No error */
- ret = 0;
- break;
-
- case 1:
- /*
- * 1 bit error (Correctable)
- * (nfestat0 >> 7) & 0x7ff :error byte number
- * (nfestat0 >> 4) & 0x7 :error bit number
- */
- err_byte_addr = (nfestat0 >> 7) & 0x7ff;
- repaired = dat[err_byte_addr] ^ (1 << ((nfestat0 >> 4) & 0x7));
-
- printf("S3C NAND: 1 bit error detected at byte %ld. "
- "Correcting from 0x%02x to 0x%02x...OK\n",
- err_byte_addr, dat[err_byte_addr], repaired);
-
- dat[err_byte_addr] = repaired;
-
- ret = 1;
- break;
-
- case 2: /* Multiple error */
- case 3: /* ECC area error */
- printf("S3C NAND: ECC uncorrectable error detected. "
- "Not correctable.\n");
- ret = -1;
- break;
- }
-
- return ret;
-}
-#endif /* CONFIG_SYS_S3C_NAND_HWECC */
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - hwcontrol: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
- * only be provided if a hardware ECC is available
- * - eccmode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- * read regs (tR)
- * - options: various chip options. They can partly be set to inform
- * nand_scan about special functionality. See the defines for further
- * explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
- static int chip_n;
-
- if (chip_n >= MAX_CHIPS)
- return -ENODEV;
-
- NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6;
-
- nand->IO_ADDR_R = (void __iomem *)NFDATA;
- nand->IO_ADDR_W = (void __iomem *)NFDATA;
- nand->cmd_ctrl = s3c_nand_hwcontrol;
- nand->dev_ready = s3c_nand_device_ready;
- nand->select_chip = s3c_nand_select_chip;
- nand->options = 0;
-#ifdef CONFIG_NAND_SPL
- nand->read_byte = nand_read_byte;
- nand->write_buf = nand_write_buf;
- nand->read_buf = nand_read_buf;
-#endif
-
-#ifdef CONFIG_SYS_S3C_NAND_HWECC
- nand->ecc.hwctl = s3c_nand_enable_hwecc;
- nand->ecc.calculate = s3c_nand_calculate_ecc;
- nand->ecc.correct = s3c_nand_correct_data;
-
- /*
- * If you get more than 1 NAND-chip with different page-sizes on the
- * board one day, it will get more complicated...
- */
- nand->ecc.mode = NAND_ECC_HW;
- nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
- nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
-#else
- nand->ecc.mode = NAND_ECC_SOFT;
-#endif /* ! CONFIG_SYS_S3C_NAND_HWECC */
-
- nand->priv = nand_cs + chip_n++;
-
- return 0;
-}
int blockpage, found = 0;
unsigned int i;
-#ifdef CONFIG_S3C64XX
- return 0;
-#endif
-
if (ONENAND_IS_2PLANE(this))
blockpage = onenand_get_2x_blockpage(mtd, addr);
else
/*
- * S3C64XX/S5PC100 OneNAND driver at U-Boot
+ * S5PC100 OneNAND driver at U-Boot
*
* Copyright (C) 2008-2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
#define ONENAND_MAIN_SPARE_ACCESS 0x16
#define ONENAND_PIPELINE_READ 0x4000
-#if defined(CONFIG_S3C64XX)
-#define MAP_00 (0x0 << 24)
-#define MAP_01 (0x1 << 24)
-#define MAP_10 (0x2 << 24)
-#define MAP_11 (0x3 << 24)
-#elif defined(CONFIG_S5P)
+#if defined(CONFIG_S5P)
#define MAP_00 (0x0 << 26)
#define MAP_01 (0x1 << 26)
#define MAP_10 (0x2 << 26)
* return the buffer address on the memory device
* It will be combined with CMD_MAP_XX
*/
-#if defined(CONFIG_S3C64XX)
-static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
-{
- return (fba << 12) | (fpa << 6) | (fsa << 4);
-}
-#elif defined(CONFIG_S5P)
+#if defined(CONFIG_S5P)
static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
{
return (fba << 13) | (fpa << 7) | (fsa << 5);
s3c_onenand_check_lock_status(mtd);
}
-#ifdef CONFIG_S3C64XX
-static void s3c_set_width_regs(struct onenand_chip *this)
-{
- int dev_id, density;
- int fba, fpa, fsa;
- int dbs_dfs;
-
- dev_id = DEVICE_ID0_REG;
-
- density = (dev_id >> ONENAND_DEVICE_DENSITY_SHIFT) & 0xf;
- dbs_dfs = !!(dev_id & ONENAND_DEVICE_IS_DDP);
-
- fba = density + 7;
- if (dbs_dfs)
- fba--; /* Decrease the fba */
- fpa = 6;
- if (density >= ONENAND_DEVICE_DENSITY_512Mb)
- fsa = 2;
- else
- fsa = 1;
-
- DPRINTK("FBA %lu, FPA %lu, FSA %lu, DDP %lu",
- FBA_WIDTH0_REG, FPA_WIDTH0_REG, FSA_WIDTH0_REG,
- DDP_DEVICE_REG);
-
- DPRINTK("mem_cfg0 0x%lx, sync mode %lu, "
- "dev_page_size %lu, BURST LEN %lu",
- MEM_CFG0_REG, SYNC_MODE_REG,
- DEV_PAGE_SIZE_REG, BURST_LEN0_REG);
-
- DEV_PAGE_SIZE_REG = 0x1;
-
- FBA_WIDTH0_REG = fba;
- FPA_WIDTH0_REG = fpa;
- FSA_WIDTH0_REG = fsa;
- DBS_DFS_WIDTH0_REG = dbs_dfs;
-}
-#endif
-
int s5pc110_chip_probe(struct mtd_info *mtd)
{
return 0;
onenand->mtd = mtd;
-#if defined(CONFIG_S3C64XX)
- onenand->base = (void *)0x70100000;
- onenand->ahb_addr = (void *)0x20000000;
-#elif defined(CONFIG_S5P)
+#if defined(CONFIG_S5P)
onenand->base = (void *)0xE7100000;
onenand->ahb_addr = (void *)0xB0000000;
#endif
COBJS-$(CONFIG_MCFUART) += mcfuart.o
COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
-COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_S5P) += serial_s5p.o
COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <linux/compiler.h>
-#include <serial.h>
-#include <asm/arch/s3c6400.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SERIAL1
-#define UART_NR S3C64XX_UART0
-
-#elif defined(CONFIG_SERIAL2)
-#define UART_NR S3C64XX_UART1
-
-#elif defined(CONFIG_SERIAL3)
-#define UART_NR S3C64XX_UART2
-
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-
-/*
- * The coefficient, used to calculate the baudrate on S3C6400 UARTs is
- * calculated as
- * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
- * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
- * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
- */
-static const int udivslot[] = {
- 0,
- 0x0080,
- 0x0808,
- 0x0888,
- 0x2222,
- 0x4924,
- 0x4a52,
- 0x54aa,
- 0x5555,
- 0xd555,
- 0xd5d5,
- 0xddd5,
- 0xdddd,
- 0xdfdd,
- 0xdfdf,
- 0xffdf,
-};
-
-static void s3c64xx_serial_setbrg(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
- u32 pclk = get_PCLK();
- u32 baudrate = gd->baudrate;
- int i;
-
- i = (pclk / baudrate) % 16;
-
- uart->UBRDIV = pclk / baudrate / 16 - 1;
- uart->UDIVSLOT = udivslot[i];
-
- for (i = 0; i < 100; i++)
- barrier();
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-static int s3c64xx_serial_init(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
- /* reset and enable FIFOs, set triggers to the maximum */
- uart->UFCON = 0xff;
- uart->UMCON = 0;
- /* 8N1 */
- uart->ULCON = 3;
- /* No interrupts, no DMA, pure polling */
- uart->UCON = 5;
-
- serial_setbrg();
-
- return 0;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int s3c64xx_serial_getc(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
- /* wait for character to arrive */
- while (!(uart->UTRSTAT & 0x1));
-
- return uart->URXH & 0xff;
-}
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int be_quiet;
-void disable_putc(void)
-{
- be_quiet = 1;
-}
-
-void enable_putc(void)
-{
- be_quiet = 0;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void s3c64xx_serial_putc(const char c)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
-#ifdef CONFIG_MODEM_SUPPORT
- if (be_quiet)
- return;
-#endif
-
- /* wait for room in the tx FIFO */
- while (!(uart->UTRSTAT & 0x2));
-
- uart->UTXH = c;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-static int s3c64xx_serial_tstc(void)
-{
- s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
-
- return uart->UTRSTAT & 0x1;
-}
-
-static struct serial_device s3c64xx_serial_drv = {
- .name = "s3c64xx_serial",
- .start = s3c64xx_serial_init,
- .stop = NULL,
- .setbrg = s3c64xx_serial_setbrg,
- .putc = s3c64xx_serial_putc,
- .puts = default_serial_puts,
- .getc = s3c64xx_serial_getc,
- .tstc = s3c64xx_serial_tstc,
-};
-
-void s3c64xx_serial_initialize(void)
-{
- serial_register(&s3c64xx_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
- return &s3c64xx_serial_drv;
-}
serial_initfunc(lpc32xx_serial_initialize);
serial_initfunc(mcf_serial_initialize);
serial_initfunc(oc_serial_initialize);
-serial_initfunc(s3c64xx_serial_initialize);
serial_initfunc(sandbox_serial_initialize);
serial_initfunc(clps7111_serial_initialize);
serial_initfunc(imx_serial_initialize);
lpc32xx_serial_initialize();
mcf_serial_initialize();
oc_serial_initialize();
- s3c64xx_serial_initialize();
sandbox_serial_initialize();
clps7111_serial_initialize();
imx_serial_initialize();
COBJS-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o
COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
-COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o
COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
#if defined(CONFIG_ARM920T) || \
defined(CONFIG_S3C24X0) || \
- defined(CONFIG_S3C6400) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
defined(CONFIG_MPC5200) || \
+++ /dev/null
-/*
- * URB OHCI HCD (Host Controller Driver) initialization for USB on the S3C64XX.
- *
- * Copyright (C) 2008,
- * Guennadi Liakhovetski, DENX Software Engineering <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/arch/s3c6400.h>
-
-int usb_cpu_init(void)
-{
- OTHERS_REG |= 0x10000;
- return 0;
-}
-
-int usb_cpu_stop(void)
-{
- OTHERS_REG &= ~0x10000;
- return 0;
-}
-
-void usb_cpu_init_fail(void)
-{
- OTHERS_REG &= ~0x10000;
-}
void dcache_enable (void);
void dcache_disable(void);
void mmu_disable(void);
-void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn));
+#if defined(CONFIG_ARM)
+void relocate_code(ulong);
+#else
+void relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn));
+#endif
ulong get_endaddr (void);
void trap_init (ulong);
#if defined (CONFIG_4xx) || \
#endif
#if defined(CONFIG_S3C24X0) || \
defined(CONFIG_LH7A40X) || \
- defined(CONFIG_S3C6400) || \
defined(CONFIG_EP93XX)
ulong get_FCLK (void);
ulong get_HCLK (void);
#ifndef __CONFIG_FALLBACKS_H
#define __CONFIG_FALLBACKS_H
+#ifdef CONFIG_SPL
+#ifdef CONFIG_SPL_PAD_TO
+#ifdef CONFIG_SPL_MAX_SIZE
+#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE
+#endif
+#endif
+#else
+#ifdef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
+#else
+#define CONFIG_SPL_PAD_TO 0
+#endif
+#endif
+#endif
+
#ifndef CONFIG_SYS_BAUDRATE_TABLE
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#endif
#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SPL_MAX_SIZE (4 * 1024)
-#define CONFIG_SPL_PAD_TO 0xfff04000
+#define CONFIG_SPL_PAD_TO 0x4000
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x87dc0000
+#define CONFIG_SYS_TEXT_BASE 0x87e00000
+
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
#define CONFIG_MXC_GPIO
#define CONFIG_HARD_SPI
"bootcmd=run bootcmd_net\0" \
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0" \
- "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
+ "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
"nand erase 0x0 0x40000; " \
"nand write 0x81000000 0x0 0x40000\0"
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_GBL_DATA_OFFSET)
+ CONFIG_SYS_INIT_RAM_SIZE)
/*-----------------------------------------------------------------------
* FLASH and environment organization
/* NAND configuration for the NAND_SPL */
/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
-#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
/* Load U-Boot to this address */
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MXC_GPIO
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
+#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_CMD_NAND
+
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_TEXT_BASE 0xfffff000
-#define CONFIG_SPL_MAX_SIZE (4 * 1024)
+#define CONFIG_SPL_MAX_SIZE 4096
#ifdef CONFIG_SYS_INIT_L2_ADDR
/* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <garyj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */
-#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
-#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
-
-#define CONFIG_PERIPORT_REMAP
-#define CONFIG_PERIPORT_BASE 0x70000000
-#define CONFIG_PERIPORT_SIZE 0x13
-
-#define CONFIG_SYS_IRAM_BASE 0x0c000000 /* Internal SRAM base address */
-#define CONFIG_SYS_IRAM_SIZE 0x2000 /* 8 KB of internal SRAM memory */
-#define CONFIG_SYS_IRAM_END (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IRAM_END - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE 0x50000000
-
-/* input clock of PLL: SMDK6400 has 12MHz input clock */
-#define CONFIG_SYS_CLK_FREQ 12000000
-
-#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
-#define CONFIG_ENABLE_MMU
-#endif
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-
-/*
- * Architecture magic and machine type
- */
-#define CONFIG_MACH_TYPE 1270
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_CS8900 /* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE 0x18800300
-#define CONFIG_CS8900_BUS16 /* follow the Linux driver */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
-
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#define CONFIG_CMDLINE_EDITING
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE 115200
-
-/***********************************************************
- * Command definition
- ***********************************************************/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_NAND
-#if defined(CONFIG_BOOT_ONENAND)
-#define CONFIG_CMD_ONENAND
-#endif
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */
-
-#define CONFIG_SYS_HZ 1000
-
-/**********************************
- Support Clock Settings
- **********************************
- Setting SYNC ASYNC
- ----------------------------------
- 667_133_66 X O
- 533_133_66 O O
- 400_133_66 X O
- 400_100_50 O O
- **********************************/
-
-/*#define CONFIG_CLK_667_133_66*/
-#define CONFIG_CLK_533_133_66
-/*
-#define CONFIG_CLK_400_100_50
-#define CONFIG_CLK_400_133_66
-#define CONFIG_SYNC_MODE
-*/
-
-/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE 0x10000000
-#define CONFIG_SYS_MONITOR_BASE 0x00000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
-#define CONFIG_SYS_MAX_FLASH_SECT 40
-
-#define CONFIG_AMD_LV800
-#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */
-/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_LEGACY_512Kx16
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-
-/*
- * SMDK6400 board specific data
- */
-
-#define CONFIG_IDENT_STRING " for SMDK6400"
-
-/* base address for uboot */
-#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000)
-/* total memory available to uboot */
-#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
-
-/* Put environment copies after the end of U-Boot owned RAM */
-#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)
-
-#ifdef CONFIG_ENABLE_MMU
-#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
-#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
- "bootm 0xc0018000"
-#else
-#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
-#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
- "bootm 0x50018000"
-#endif
-
-/* NAND U-Boot load and start address */
-#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)
-
-#define CONFIG_ENV_OFFSET 0x0040000
-
-/* NAND configuration */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x70200010
-#define CONFIG_SYS_S3C_NAND_HWECC
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_WP 1
-#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */
-#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
-
-#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
-
-/* NAND chip page size */
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-/* NAND chip block size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-/* NAND chip page per block count */
-#define CONFIG_SYS_NAND_PAGE_COUNT 64
-/* Location of the bad-block label */
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* Extra address cycle for > 128MiB */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-
-/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
-#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
-/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
-#define CONFIG_SYS_NAND_ECCBYTES 4
-/* Size of a single OOB region */
-#define CONFIG_SYS_NAND_OOBSIZE 64
-/* ECC byte positions */
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63}
-
-/* Boot configuration (define only one of next 3) */
-#define CONFIG_BOOT_NAND
-/* None of these are currently implemented. Left from the original Samsung
- * version for reference
-#define CONFIG_BOOT_NOR
-#define CONFIG_BOOT_MOVINAND
-#define CONFIG_BOOT_ONENAND
-*/
-
-#define CONFIG_NAND
-#define CONFIG_NAND_S3C64XX
-/* Unimplemented or unsupported. See comment above.
-#define CONFIG_ONENAND
-#define CONFIG_MOVINAND
-*/
-
-/* Settings as above boot configuration */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_BOOTARGS "console=ttySAC,115200"
-
-#if !defined(CONFIG_ENABLE_MMU)
-#define CONFIG_CMD_USB 1
-#define CONFIG_USB_S3C64XX
-#define CONFIG_USB_OHCI_NEW 1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400"
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
-#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
-
-#define CONFIG_USB_STORAGE 1
-#endif
-#define CONFIG_DOS_PARTITION 1
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
-# error "usb_ohci.c is currently broken with MMU enabled."
-#endif
-
-#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
+#include <asm/arch/imx-regs.h>
/*
* KARO TX25 board - SoC Configuration
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
-/* NAND BOOT is the only boot method */
-#define CONFIG_NAND_U_BOOT
+#define CONFIG_SPL
+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_MAX_SIZE 2048
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0x810c0000
+#define CONFIG_SYS_TEXT_BASE 0x81200000
#ifndef MACH_TYPE_TX25
#define MACH_TYPE_TX25 2177
#define CONFIG_MACH_TYPE MACH_TYPE_TX25
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
/* Start copying real U-boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
-#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000)
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_SPARE_SIZE 64
+#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE)
#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __FSL_NFC_H
-#define __FSL_NFC_H
-
-/*
- * Register map and bit definitions for the Freescale NAND Flash Controller
- * present in various i.MX devices.
- *
- * MX31 and MX27 have version 1, which has:
- * 4 512-byte main buffers and
- * 4 16-byte spare buffers
- * to support up to 2K byte pagesize nand.
- * Reading or writing a 2K page requires 4 FDI/FDO cycles.
- *
- * MX25 and MX35 have version 2.1, which has:
- * 8 512-byte main buffers and
- * 8 64-byte spare buffers
- * to support up to 4K byte pagesize nand.
- * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
- * Also some of registers are moved and/or changed meaning as seen below.
- */
-#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
-#define MXC_NFC_V1
-#define is_mxc_nfc_1() 1
-#define is_mxc_nfc_21() 0
-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
-#define MXC_NFC_V2_1
-#define is_mxc_nfc_1() 0
-#define is_mxc_nfc_21() 1
-#else
-#error "MXC NFC implementation not supported"
-#endif
-
-#if defined(MXC_NFC_V1)
-#define NAND_MXC_NR_BUFS 4
-#define NAND_MXC_SPARE_BUF_SIZE 16
-#define NAND_MXC_REG_OFFSET 0xe00
-#define NAND_MXC_2K_MULTI_CYCLE
-#elif defined(MXC_NFC_V2_1)
-#define NAND_MXC_NR_BUFS 8
-#define NAND_MXC_SPARE_BUF_SIZE 64
-#define NAND_MXC_REG_OFFSET 0x1e00
-#endif
-
-struct fsl_nfc_regs {
- u8 main_area[NAND_MXC_NR_BUFS][0x200];
- u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
- /*
- * reserved size is offset of nfc registers
- * minus total main and spare sizes
- */
- u8 reserved1[NAND_MXC_REG_OFFSET
- - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
-#if defined(MXC_NFC_V1)
- u16 buf_size;
- u16 reserved2;
- u16 buf_addr;
- u16 flash_addr;
- u16 flash_cmd;
- u16 config;
- u16 ecc_status_result;
- u16 rsltmain_area;
- u16 rsltspare_area;
- u16 wrprot;
- u16 unlockstart_blkaddr;
- u16 unlockend_blkaddr;
- u16 nf_wrprst;
- u16 config1;
- u16 config2;
-#elif defined(MXC_NFC_V2_1)
- u16 reserved2[2];
- u16 buf_addr;
- u16 flash_addr;
- u16 flash_cmd;
- u16 config;
- u32 ecc_status_result;
- u16 spare_area_size;
- u16 wrprot;
- u16 reserved3[2];
- u16 nf_wrprst;
- u16 config1;
- u16 config2;
- u16 reserved4;
- u16 unlockstart_blkaddr;
- u16 unlockend_blkaddr;
- u16 unlockstart_blkaddr1;
- u16 unlockend_blkaddr1;
- u16 unlockstart_blkaddr2;
- u16 unlockend_blkaddr2;
- u16 unlockstart_blkaddr3;
- u16 unlockend_blkaddr3;
-#endif
-};
-
-/*
- * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
- * operation
- */
-#define NFC_CMD 0x1
-
-/*
- * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
- * operation
- */
-#define NFC_ADDR 0x2
-
-/*
- * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
- * operation
- */
-#define NFC_INPUT 0x4
-
-/*
- * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
- * Output operation
- */
-#define NFC_OUTPUT 0x8
-
-/*
- * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
- * operation
- */
-#define NFC_ID 0x10
-
-/*
- * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
- * Status operation
- */
-#define NFC_STATUS 0x20
-
-/*
- * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
- * operation
- */
-#define NFC_INT 0x8000
-
-#ifdef MXC_NFC_V2_1
-#define NFC_4_8N_ECC (1 << 0)
-#endif
-#define NFC_SP_EN (1 << 2)
-#define NFC_ECC_EN (1 << 3)
-#define NFC_INT_MSK (1 << 4)
-#define NFC_BIG (1 << 5)
-#define NFC_RST (1 << 6)
-#define NFC_CE (1 << 7)
-#define NFC_ONE_CYCLE (1 << 8)
-#define NFC_FP_INT (1 << 11)
-
-#endif /* __FSL_NFC_H */
extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
int boundary, int lock);
-/* S3C64xx */
-extern void s3c64xx_onenand_init(struct mtd_info *);
-extern void s3c64xx_set_width_regs(struct onenand_chip *);
-
/* SPL */
void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
set ${line}
# add default board name if needed
[ $# = 3 ] && set ${line} ${1}
-elif [ "${MAKEFLAGS+set}${MAKELEVEL+set}" = "setset" ] ; then
- # only warn when using a config target in the Makefile
- cat <<-EOF
-
- warning: Please migrate to boards.cfg. Failure to do so will
- mean removal of your board in the next release.
-
- EOF
- sleep 5
fi
while [ $# -gt 0 ] ; do
+++ /dev/null
-CONFIG_NAND_SPL = y
-PAD_TO := 2048
-
-include $(TOPDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-
-SOBJS = start.o crt0.o lowlevel_init.o
-COBJS = nand_boot_fsl_nfc.o
-
-SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S
-SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
-SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-#########################################################################
-
-$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/nand_spl/%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- lowlevel_init.o (.text)
- nand_boot_fsl_nfc.o (.text)
- *(.text)
- . = 2K;
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = ALIGN(4);
- .u_boot_list : {
- *(SORT(.u_boot_list*));
- }
-
- . = ALIGN(4);
-
- __image_copy_end = .;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-#
-# (C) Copyright 2009 DENX Software Engineering
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundatio; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-CONFIG_NAND_SPL = y
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL)
-AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-
-SOBJS = start.o crt0.o lowlevel_init.o
-COBJS = nand_boot_fsl_nfc.o
-
-SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c
-SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S
-SRCS += $(SRCTREE)/arch/arm/lib/crt0.S
-SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-#########################################################################
-
-$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(SRCTREE)/nand_spl/%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-PAD_TO := 2048
+++ /dev/null
-/*
- * (C) Copyright 2009
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- lowlevel_init.o (.text)
- nand_boot_fsl_nfc.o (.text)
- *(.text)
- . = 2K;
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : {
- *(.data)
- }
-
- . = ALIGN(4);
-
- . = ALIGN(4);
- .u_boot_list : {
- *(SORT(.u_boot_list*));
- }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-#
-# (C) Copyright 2006-2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-CONFIG_NAND_SPL = y
-
-include $(TOPDIR)/config.mk
-include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-
-nandobj := $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
- $(LDFLAGS_FINAL) -gc-sections
-AFLAGS += -DCONFIG_NAND_SPL
-CFLAGS += -DCONFIG_NAND_SPL -ffunction-sections
-
-SOBJS = start.o cpu_init.o lowlevel_init.o
-COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o nand_base.o
-
-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all: $(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
- -Map $(nandobj)u-boot-spl.map \
- -o $(nandobj)u-boot-spl
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-# from cpu directory
-$(obj)start.S:
- @rm -f $@
- @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@
-
-# from SoC directory
-$(obj)cpu_init.S:
- @rm -f $@
- @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@
-
-# from board directory
-$(obj)lowlevel_init.S:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@
-
-# from nand_spl directory
-$(obj)nand_boot.c:
- @rm -f $@
- @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
-
-# from drivers/mtd/nand directory
-$(obj)nand_ecc.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@
-
-$(obj)s3c64xx.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
-
-$(obj)smdk6400_nand_spl.c:
- @rm -f $@
- @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@
-
-$(obj)nand_base.c:
- @rm -f $@
- @ln -s $(TOPDIR)/drivers/mtd/nand/nand_base.c $@
-#########################################################################
-
-$(obj)%.o: $(obj)%.S
- $(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o: $(obj)%.c
- $(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-#
-# (C) Copyright 2006
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-#
-# Samsung S3C64xx Reference Platform (smdk6400) board
-
-# CONFIG_SYS_TEXT_BASE for SPL:
-#
-# On S3C64xx platforms the SPL is located in SRAM at 0.
-#
-# CONFIG_SYS_TEXT_BASE = 0
-
-include $(TOPDIR)/board/$(BOARDDIR)/config.mk
-
-# PAD_TO used to generate a 4kByte binary needed for the combined image
-# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096
-PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096])
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- start.o (.text)
- cpu_init.o (.text)
- nand_boot.o (.text)
-
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
-
- . = ALIGN(4);
- .u_boot_list : {
- *(SORT(.u_boot_list*));
- }
-
- . = ALIGN(4);
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- .dynsym : {
- __dynsym_start = .;
- *(.dynsym)
- }
-
- _end = .;
-
- .bss __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-}
s/="\([0-9][0-9]*\)"/=\1/;
# ... and from hex numbers
s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/;
+ # ... and from configs defined from other configs
+ s/="\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)"/=$(\1)/;
# Change '1' and empty values to "y" (not perfect, but
# supports conditional compilation in the makefiles
s/=$/=y/;
projects / karo-tx-uboot.git / commitdiff