Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 2 Jun 2014 06:43:48 +0000 (08:43 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 2 Jun 2014 06:43:48 +0000 (08:43 +0200)
496 files changed:
.gitignore
Makefile
README
arch/arc/include/asm/config.h
arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/am33xx/Makefile
arch/arm/cpu/armv7/am33xx/mem.c [deleted file]
arch/arm/cpu/armv7/am33xx/sys_info.c
arch/arm/cpu/armv7/at91/config.mk [new file with mode: 0644]
arch/arm/cpu/armv7/omap-common/Makefile
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/mem-common.c
arch/arm/cpu/armv7/omap3/Makefile
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/cpu/armv7/rmobile/Makefile
arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c [deleted file]
arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c [moved from arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c with 50% similarity]
arch/arm/cpu/armv7/rmobile/cpu_info.c
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
arch/arm/cpu/armv7/sunxi/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/board.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/clock.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/clock_sun4i.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/config.mk [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/cpu_info.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/dram.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/pinmux.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/start.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/timer.c [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds [new file with mode: 0644]
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds [new file with mode: 0644]
arch/arm/cpu/armv7/zynq/cpu.c
arch/arm/cpu/armv7/zynq/ddrc.c
arch/arm/cpu/armv7/zynq/slcr.c
arch/arm/cpu/armv7/zynq/spl.c
arch/arm/cpu/armv8/start.S
arch/arm/cpu/at91-common/spl.c
arch/arm/dts/imx6q-sabreauto.dts
arch/arm/dts/zynq-7000.dtsi
arch/arm/dts/zynq-microzed.dts
arch/arm/dts/zynq-zc702.dts
arch/arm/dts/zynq-zc706.dts
arch/arm/dts/zynq-zc770-xm010.dts
arch/arm/dts/zynq-zc770-xm012.dts
arch/arm/dts/zynq-zc770-xm013.dts
arch/arm/dts/zynq-zed.dts
arch/arm/imx-common/Makefile
arch/arm/imx-common/iomux-v3.c
arch/arm/imx-common/video.c [new file with mode: 0644]
arch/arm/include/asm/arch-am33xx/clock.h
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-at91/at91_pmc.h
arch/arm/include/asm/arch-at91/at91sam9x5.h
arch/arm/include/asm/arch-at91/hardware.h
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6sl_pins.h
arch/arm/include/asm/arch-omap3/mem.h
arch/arm/include/asm/arch-omap4/cpu.h
arch/arm/include/asm/arch-omap4/hardware.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap4/mem.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/clock.h
arch/arm/include/asm/arch-omap5/cpu.h
arch/arm/include/asm/arch-omap5/hardware.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/mem.h [new file with mode: 0644]
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/arch-omap5/sys_proto.h
arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
arch/arm/include/asm/arch-rmobile/r8a7790.h
arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
arch/arm/include/asm/arch-rmobile/r8a7791.h
arch/arm/include/asm/arch-rmobile/rcar-base.h [new file with mode: 0644]
arch/arm/include/asm/arch-rmobile/rmobile.h
arch/arm/include/asm/arch-sunxi/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/clock_sun4i.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/cpu.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/dram.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/mmc.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/sys_proto.h [new file with mode: 0644]
arch/arm/include/asm/arch-sunxi/timer.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra/usb.h
arch/arm/include/asm/arch-vf610/imx-regs.h
arch/arm/include/asm/arch-zynq/hardware.h
arch/arm/include/asm/arch-zynq/sys_proto.h
arch/arm/include/asm/config.h
arch/arm/include/asm/imx-common/iomux-v3.h
arch/arm/include/asm/imx-common/video.h [new file with mode: 0644]
arch/arm/include/asm/omap_common.h
arch/arm/include/asm/ti-common/sys_proto.h [new file with mode: 0644]
arch/arm/include/asm/u-boot.h
arch/arm/lib/board.c
arch/avr32/include/asm/u-boot.h
arch/avr32/lib/board.c
arch/blackfin/include/asm/net.h [deleted file]
arch/blackfin/include/asm/u-boot.h
arch/blackfin/lib/board.c
arch/m68k/include/asm/u-boot.h
arch/m68k/lib/board.c
arch/microblaze/include/asm/u-boot.h
arch/microblaze/lib/board.c
arch/mips/include/asm/config.h
arch/mips/include/asm/u-boot.h
arch/mips/lib/board.c
arch/nds32/include/asm/u-boot.h
arch/nds32/lib/board.c
arch/nios2/include/asm/u-boot.h
arch/nios2/lib/board.c
arch/openrisc/include/asm/u-boot.h
arch/openrisc/lib/board.c
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/speed.c
arch/powerpc/cpu/mpc85xx/spl_minimal.c
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc85xx/t4240_ids.c
arch/powerpc/cpu/mpc85xx/t4240_serdes.c
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
arch/powerpc/cpu/mpc85xx/u-boot.lds
arch/powerpc/cpu/mpc86xx/start.S
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_errata.h
arch/powerpc/include/asm/fsl_secure_boot.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/processor.h
arch/powerpc/include/asm/u-boot.h
arch/powerpc/lib/board.c
arch/sandbox/config.mk
arch/sandbox/dts/.gitignore [new file with mode: 0644]
arch/sandbox/include/asm/config.h
arch/sh/include/asm/u-boot.h
arch/sh/lib/board.c
arch/sparc/cpu/leon2/cpu_init.c
arch/sparc/cpu/leon3/cpu_init.c
arch/sparc/include/asm/u-boot.h
arch/sparc/lib/board.c
board/BuR/common/common.c
board/amcc/acadia/acadia.c
board/amcc/acadia/u-boot-nand.lds [deleted file]
board/amcc/bamboo/u-boot-nand.lds [deleted file]
board/amcc/canyonlands/u-boot-nand.lds [deleted file]
board/amcc/kilauea/u-boot-nand.lds [deleted file]
board/amcc/sequoia/u-boot-nand.lds [deleted file]
board/armadeus/apf27/fpga.c
board/astro/mcf5373l/fpga.c
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
board/atmel/sama5d3_xplained/sama5d3_xplained.c
board/balloon3/balloon3.c
board/bct-brettl2/bct-brettl2.c
board/bf518f-ezbrd/bf518f-ezbrd.c
board/bf526-ezbrd/bf526-ezbrd.c
board/bf527-ezkit/bf527-ezkit.c
board/bf537-minotaur/bf537-minotaur.c
board/bf537-pnav/bf537-pnav.c
board/bf537-srv1/bf537-srv1.c
board/bf537-stamp/bf537-stamp.c
board/boundary/nitrogen6x/nitrogen6x.c
board/buffalo/lsxl/lsxl.c
board/cm-bf527/cm-bf527.c
board/cm-bf537e/cm-bf537e.c
board/cm-bf537u/cm-bf537u.c
board/compulab/cm_t54/Makefile [new file with mode: 0644]
board/compulab/cm_t54/cm_t54.c [new file with mode: 0644]
board/compulab/cm_t54/mux.c [new file with mode: 0644]
board/compulab/cm_t54/spl.c [new file with mode: 0644]
board/compulab/common/Makefile
board/compulab/common/eeprom.c
board/compulab/common/eeprom.h
board/dave/PPChameleonEVB/u-boot.lds
board/dnp5370/dnp5370.c
board/embest/mx6boards/Makefile [new file with mode: 0644]
board/embest/mx6boards/mx6boards.c [new file with mode: 0644]
board/esd/pmc440/fpga.c
board/esd/pmc440/u-boot-nand.lds [deleted file]
board/freescale/b4860qds/b4860qds.c
board/freescale/common/Makefile
board/freescale/common/sys_eeprom.c
board/freescale/common/zm7300.c [new file with mode: 0644]
board/freescale/common/zm7300.h [new file with mode: 0644]
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/mx6slevk/mx6slevk.c
board/freescale/p1_p2_rdb/Makefile
board/freescale/p1_p2_rdb/ddr.c
board/freescale/p1_p2_rdb/spl.c [new file with mode: 0644]
board/freescale/p1_p2_rdb/spl_minimal.c [new file with mode: 0644]
board/freescale/p1_p2_rdb/tlb.c
board/freescale/qemu-ppce500/qemu-ppce500.c
board/freescale/t104xrdb/t104xrdb.c
board/freescale/t4rdb/Makefile [new file with mode: 0644]
board/freescale/t4rdb/ddr.c [new file with mode: 0644]
board/freescale/t4rdb/ddr.h [new file with mode: 0644]
board/freescale/t4rdb/eth.c [new file with mode: 0644]
board/freescale/t4rdb/law.c [new file with mode: 0644]
board/freescale/t4rdb/pci.c [new file with mode: 0644]
board/freescale/t4rdb/t4240rdb.c [new file with mode: 0644]
board/freescale/t4rdb/t4_pbi.cfg [new file with mode: 0644]
board/freescale/t4rdb/t4_rcw.cfg [new file with mode: 0644]
board/freescale/t4rdb/t4rdb.h [new file with mode: 0644]
board/freescale/t4rdb/tlb.c [new file with mode: 0644]
board/freescale/vf610twr/vf610twr.c
board/gateworks/gw_ventana/gw_ventana.c
board/gateworks/gw_ventana/ventana_eeprom.h
board/gen860t/fpga.c
board/gumstix/duovero/Makefile [new file with mode: 0644]
board/gumstix/duovero/duovero.c [new file with mode: 0644]
board/gumstix/duovero/duovero_mux_data.h [new file with mode: 0644]
board/gumstix/pepper/Makefile [new file with mode: 0644]
board/gumstix/pepper/board.c [new file with mode: 0644]
board/gumstix/pepper/board.h [new file with mode: 0644]
board/gumstix/pepper/mux.c [new file with mode: 0644]
board/ip04/ip04.c
board/keymile/kmp204x/kmp204x.c
board/keymile/kmp204x/kmp204x.h
board/keymile/kmp204x/pbi.cfg
board/keymile/kmp204x/pci.c
board/keymile/kmp204x/qrio.c
board/keymile/kmp204x/rcw_kmp204x.cfg
board/matrix_vision/common/mv_common.c
board/matrix_vision/mvsmr/fpga.c
board/muas3001/muas3001.c
board/mvblue/mvblue.c
board/overo/overo.c
board/overo/overo.h
board/renesas/koelsch/koelsch.c
board/renesas/koelsch/qos.c
board/renesas/lager/lager.c
board/renesas/lager/qos.c
board/samsung/common/Makefile
board/samsung/common/ums.c [deleted file]
board/sandbox/Makefile [moved from board/sandbox/sandbox/Makefile with 100% similarity]
board/sandbox/README.sandbox [new file with mode: 0644]
board/sandbox/sandbox.c [moved from board/sandbox/sandbox/sandbox.c with 100% similarity]
board/sandbox/sandbox/README.sandbox [deleted file]
board/siemens/common/board.c
board/siemens/draco/Makefile [moved from board/siemens/dxr2/Makefile with 100% similarity]
board/siemens/draco/board.c [moved from board/siemens/dxr2/board.c with 63% similarity]
board/siemens/draco/board.h [moved from board/siemens/dxr2/board.h with 71% similarity]
board/siemens/draco/mux.c [moved from board/siemens/dxr2/mux.c with 99% similarity]
board/siemens/pxm2/board.c
board/siemens/rut/board.c
board/spear/x600/fpga.c
board/sunxi/Makefile [new file with mode: 0644]
board/sunxi/board.c [new file with mode: 0644]
board/sunxi/dram_cubietruck.c [new file with mode: 0644]
board/sunxi/gmac.c [new file with mode: 0644]
board/tcm-bf518/tcm-bf518.c
board/tcm-bf537/tcm-bf537.c
board/teejet/mt_ventoux/mt_ventoux.c
board/wandboard/wandboard.c
board/xilinx/zynq/.gitignore [new file with mode: 0644]
board/xilinx/zynq/Makefile
board/xilinx/zynq/board.c
board/xilinx/zynq/ps7_init.c [deleted file]
board/xilinx/zynq/xil_io.h [new file with mode: 0644]
boards.cfg
common/Makefile
common/board_f.c
common/cmd_bdinfo.c
common/cmd_bootm.c
common/cmd_fastboot.c [new file with mode: 0644]
common/cmd_fpga.c
common/cmd_fuse.c
common/cmd_mmc.c
common/cmd_nand.c
common/cmd_nvedit.c
common/cmd_otp.c
common/cmd_part.c
common/cmd_time.c
common/cmd_usb_mass_storage.c
common/console.c
common/hush.c
common/image-android.c [new file with mode: 0644]
common/image.c
common/main.c
common/spl/spl_nand.c
disk/part.c
disk/part_efi.c
doc/README.android-fastboot [new file with mode: 0644]
doc/README.android-fastboot-protocol [new file with mode: 0644]
doc/README.atmel_pmecc
doc/README.generic-board
doc/README.gpt
doc/git-mailrc
drivers/dfu/dfu.c
drivers/dfu/dfu_mmc.c
drivers/dfu/dfu_nand.c
drivers/fpga/fpga.c
drivers/fpga/spartan2.c
drivers/fpga/spartan3.c
drivers/fpga/virtex2.c
drivers/fpga/xilinx.c
drivers/fpga/zynqpl.c
drivers/gpio/at91_gpio.c
drivers/i2c/mvtwsi.c
drivers/i2c/zynq_i2c.c
drivers/mmc/Makefile
drivers/mmc/fsl_esdhc.c
drivers/mmc/gen_atmel_mci.c
drivers/mmc/mmc.c
drivers/mmc/rpmb.c [new file with mode: 0644]
drivers/mmc/sunxi_mmc.c [new file with mode: 0644]
drivers/mtd/nand/omap_gpmc.c
drivers/net/designware.c
drivers/net/designware.h
drivers/net/dm9000x.c
drivers/net/fm/Makefile
drivers/net/fm/memac_phy.c
drivers/net/ftmac110.c
drivers/net/phy/atheros.c
drivers/net/phy/phy.c
drivers/net/phy/vitesse.c
drivers/pci/fsl_pci_init.c
drivers/power/pmic/Makefile
drivers/power/pmic/pmic_ltc3676.c [new file with mode: 0644]
drivers/power/pmic/pmic_pfuze100.c
drivers/power/tps6586x.c
drivers/qe/qe.c
drivers/serial/ns16550.c
drivers/serial/serial.c
drivers/usb/gadget/Makefile
drivers/usb/gadget/ci_udc.c
drivers/usb/gadget/ci_udc.h
drivers/usb/gadget/f_dfu.c
drivers/usb/gadget/f_fastboot.c [new file with mode: 0644]
drivers/usb/gadget/f_thor.c
drivers/usb/gadget/storage_common.c
drivers/usb/host/Makefile
drivers/usb/host/ehci-fsl.c
drivers/usb/host/ehci-tegra.c
drivers/usb/host/ehci-zynq.c [new file with mode: 0644]
drivers/usb/musb-new/musb_gadget_ep0.c
drivers/video/Makefile
drivers/video/atmel_hlcdfb.c
drivers/video/imx25lcdc.c [new file with mode: 0644]
drivers/video/mxc_ipuv3_fb.c
examples/standalone/Makefile
fs/ext4/ext4_common.c
fs/ext4/ext4_write.c
fs/fat/fat_write.c
fs/ubifs/super.c
include/android_image.h [new file with mode: 0644]
include/asm-generic/u-boot.h
include/common.h
include/config_fallbacks.h
include/configs/B4860QDS.h
include/configs/BSC9132QDS.h
include/configs/GEN860T.h
include/configs/MPC8536DS.h
include/configs/MPC8572DS.h
include/configs/MPC8641HPCN.h
include/configs/MVBC_P.h
include/configs/MVBLM7.h
include/configs/MVSMR.h
include/configs/P1_P2_RDB.h
include/configs/P2041RDB.h
include/configs/T1040QDS.h
include/configs/T104xRDB.h
include/configs/T208xQDS.h
include/configs/T208xRDB.h
include/configs/T4240EMU.h
include/configs/T4240QDS.h
include/configs/T4240RDB.h [new file with mode: 0644]
include/configs/alpr.h
include/configs/armadillo-800eva.h
include/configs/astro_mcf5373l.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9n12ek.h
include/configs/at91sam9x5ek.h
include/configs/balloon3.h
include/configs/bct-brettl2.h
include/configs/bf518f-ezbrd.h
include/configs/bf526-ezbrd.h
include/configs/bf527-ezkit.h
include/configs/bf537-minotaur.h
include/configs/bf537-pnav.h
include/configs/bf537-srv1.h
include/configs/bf537-stamp.h
include/configs/cm-bf527.h
include/configs/cm-bf537e.h
include/configs/cm-bf537u.h
include/configs/cm_t54.h [new file with mode: 0644]
include/configs/coreboot.h
include/configs/corenet_ds.h
include/configs/corvus.h
include/configs/cpu9260.h
include/configs/da850evm.h
include/configs/dnp5370.h
include/configs/draco.h [new file with mode: 0644]
include/configs/duovero.h [new file with mode: 0644]
include/configs/dxr2.h
include/configs/embestmx6boards.h [new file with mode: 0644]
include/configs/ethernut5.h
include/configs/grsim.h
include/configs/grsim_leon2.h
include/configs/gw_ventana.h
include/configs/highbank.h
include/configs/hummingboard.h
include/configs/ids8313.h
include/configs/iocon.h
include/configs/ip04.h
include/configs/k2hk_evm.h
include/configs/km/kmp204x-common.h
include/configs/koelsch.h
include/configs/kwb.h
include/configs/lager.h
include/configs/lsxl.h
include/configs/m28evk.h
include/configs/mt_ventoux.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/mx6sabre_common.h
include/configs/mx6sabresd.h
include/configs/mx6slevk.h
include/configs/mxs.h
include/configs/nitrogen6x.h
include/configs/omap3_beagle.h
include/configs/omap3_mvblx.h
include/configs/omap3_overo.h
include/configs/p1_p2_rdb_pc.h
include/configs/pepper.h [new file with mode: 0644]
include/configs/pxm2.h
include/configs/qemu-ppce500.h
include/configs/sama5d3_xplained.h
include/configs/sama5d3xek.h
include/configs/sandbox.h
include/configs/siemens-am33x-common.h
include/configs/sun7i.h [new file with mode: 0644]
include/configs/sunxi-common.h [new file with mode: 0644]
include/configs/t4qds.h
include/configs/tcm-bf518.h
include/configs/tcm-bf537.h
include/configs/ti_omap4_common.h
include/configs/tseries.h
include/configs/udoo.h
include/configs/vl_ma2sc.h
include/configs/wandboard.h
include/configs/x600.h
include/configs/zynq-common.h
include/configs/zynq_zc70x.h
include/configs/zynq_zed.h
include/dfu.h
include/ext4fs.h
include/fat.h
include/fpga.h
include/image.h
include/mmc.h
include/net.h
include/netdev.h
include/ns16550.h
include/palmas.h
include/part.h
include/power/ltc3676_pmic.h [new file with mode: 0644]
include/power/pfuze100_pmic.h
include/spartan2.h
include/spartan3.h
include/usb/ehci-fsl.h
include/usb_mass_storage.h
include/virtex2.h
include/xilinx.h
include/zynqpl.h
lib/Makefile
lib/sha256.c
nand_spl/board/freescale/p1_p2_rdb/Makefile [deleted file]
nand_spl/board/freescale/p1_p2_rdb/nand_boot.c [deleted file]
net/eth.c
spl/Makefile
tools/.gitignore
tools/Makefile
tools/atmel_pmecc_params.c [new file with mode: 0644]
tools/atmelimage.c [new file with mode: 0644]
tools/env/aes.c [new file with mode: 0644]
tools/imagetool.c
tools/imagetool.h
tools/logos/syteco.bmp
tools/mksunxiboot.c [new file with mode: 0644]
tools/patman/README
tools/patman/commit.py
tools/patman/gitutil.py
tools/patman/patchstream.py

index cba5eac..a6b2d1c 100644 (file)
@@ -47,8 +47,8 @@
 /errlog
 /reloc_off
 
-!/spl/Makefile
 /spl/*
+!/spl/Makefile
 /tpl/
 
 #
index 840c39b..966fd14 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -6,9 +6,9 @@
 #
 
 VERSION = 2014
-PATCHLEVEL = 04
+PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
@@ -285,7 +285,7 @@ export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
 #         cmd_cc_o_c       = $(CC) $(c_flags) -c -o $@ $<
 #
 # If $(quiet) is empty, the whole command will be printed.
-# If it is set to "quiet_", only the short version will be printed. 
+# If it is set to "quiet_", only the short version will be printed.
 # If it is set to "silent_", nothing will be printed at all, since
 # the variable $(silent_cmd_cc_o_c) doesn't exist.
 #
@@ -578,6 +578,9 @@ KBUILD_AFLAGS += -Wa,-gstabs,-S
 endif
 endif
 
+# Prohibit date/time macros, which would make the build non-deterministic
+KBUILD_CFLAGS   += $(call cc-option,-Werror=date-time)
+
 ifneq ($(CONFIG_SYS_TEXT_BASE),)
 KBUILD_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
 endif
@@ -696,6 +699,7 @@ PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`
 endif
 PLATFORM_LIBS += $(PLATFORM_LIBGCC)
 export PLATFORM_LIBS
+export PLATFORM_LIBGCC
 
 # Special flags for CPP when processing the linker script.
 # Pass the version down so we can handle backwards compatibility
@@ -749,6 +753,9 @@ ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
 ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
 ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin
+ifeq ($(CONFIG_SPL_FRAMEWORK),y)
+ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
+endif
 ALL-$(CONFIG_OF_HOSTFILE) += u-boot.dtb
 ifneq ($(CONFIG_SPL_TARGET),)
 ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
@@ -851,6 +858,11 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
 u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
        $(call if_changed,mkimage)
 
+MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
+
+u-boot-dtb.img: u-boot-dtb.bin FORCE
+       $(call if_changed,mkimage)
+
 u-boot.sha1:   u-boot.bin
                tools/ubsha1 u-boot.bin
 
@@ -890,7 +902,7 @@ MKIMAGEFLAGS_u-boot-spl.ais = -s -n $(if $(CONFIG_AIS_CONFIG_FILE), \
 spl/u-boot-spl.ais: spl/u-boot-spl.bin FORCE
        $(call if_changed,mkimage)
 
-OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_MAX_SIZE)
+OBJCOPYFLAGS_u-boot.ais = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
 u-boot.ais: spl/u-boot-spl.ais u-boot.img FORCE
        $(call if_changed,pad_cat)
 
@@ -925,6 +937,13 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO)
 u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
        $(call if_changed,pad_cat)
 
+ifneq ($(CONFIG_SUNXI),)
+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
+                                  --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+       $(call if_changed,pad_cat)
+endif
+
 ifneq ($(CONFIG_TEGRA),)
 OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
 u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
@@ -995,7 +1014,7 @@ ifeq ($(CONFIG_KALLSYMS),y)
        $(call cmd,u-boot__) common/system_map.o
 endif
 
-# The actual objects are generated when descending, 
+# The actual objects are generated when descending,
 # make sure no implicit rule kicks in
 $(sort $(u-boot-init) $(u-boot-main)): $(u-boot-dirs) ;
 
@@ -1151,6 +1170,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl
 spl/u-boot-spl: tools prepare
        $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
 
+spl/sunxi-spl.bin: spl/u-boot-spl
+       @:
+
 tpl/u-boot-tpl.bin: tools prepare
        $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
 
@@ -1434,7 +1456,7 @@ endif
        $(build)=$(build-dir) $(@:.ko=.o)
        $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost
 
-# FIXME Should go into a make.lib or something 
+# FIXME Should go into a make.lib or something
 # ===========================================================================
 
 quiet_cmd_rmdirs = $(if $(wildcard $(rm-dirs)),CLEAN   $(wildcard $(rm-dirs)))
diff --git a/README b/README
index 61851b3..a280435 100644 (file)
--- a/README
+++ b/README
@@ -264,6 +264,17 @@ e.g. "make cogent_mpc8xx_config". And also configure the cogent
 directory according to the instructions in cogent/README.
 
 
+Sandbox Environment:
+--------------------
+
+U-Boot can be built natively to run on a Linux host using the 'sandbox'
+board. This allows feature development which is not board- or architecture-
+specific to be undertaken on a native platform. The sandbox is also used to
+run some of U-Boot's tests.
+
+See board/sandbox/sandbox/README.sandbox for more details.
+
+
 Configuration Options:
 ----------------------
 
@@ -440,6 +451,12 @@ The following options need to be configured:
                supported, core will start to execute uboot when wakes up.
 
 - Generic CPU options:
+               CONFIG_SYS_GENERIC_GLOBAL_DATA
+               Defines global data is initialized in generic board board_init_f().
+               If this macro is defined, global data is created and cleared in
+               generic board board_init_f(). Without this macro, architecture/board
+               should initialize global data before calling board_init_f().
+
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
                Defines the endianess of the CPU. Implementation of those
@@ -740,6 +757,10 @@ The following options need to be configured:
                boot loader that has already initialized the UART.  Define this
                variable to flush the UART at init time.
 
+               CONFIG_SERIAL_HW_FLOW_CONTROL
+
+               Define this variable to enable hw flow control in serial driver.
+               Current user of this option is drivers/serial/nsl16550.c driver
 
 - Console Interface:
                Depending on board, define exactly one serial port
@@ -1513,6 +1534,16 @@ The following options need to be configured:
                        CONFIG_SH_MMCIF_CLK
                        Define the clock frequency for MMCIF
 
+               CONFIG_GENERIC_MMC
+               Enable the generic MMC driver
+
+               CONFIG_SUPPORT_EMMC_BOOT
+               Enable some additional features of the eMMC boot partitions.
+
+               CONFIG_SUPPORT_EMMC_RPMB
+               Enable the commands for reading, writing and programming the
+               key for the Replay Protection Memory Block partition in eMMC.
+
 - USB Device Firmware Update (DFU) class support:
                CONFIG_DFU_FUNCTION
                This enables the USB portion of the DFU USB class
@@ -1558,6 +1589,28 @@ The following options need to be configured:
                entering dfuMANIFEST state. Host waits this timeout, before
                sending again an USB request to the device.
 
+- USB Device Android Fastboot support:
+               CONFIG_CMD_FASTBOOT
+               This enables the command "fastboot" which enables the Android
+               fastboot mode for the platform's USB device. Fastboot is a USB
+               protocol for downloading images, flashing and device control
+               used on Android devices.
+               See doc/README.android-fastboot for more information.
+
+               CONFIG_ANDROID_BOOT_IMAGE
+               This enables support for booting images which use the Android
+               image format header.
+
+               CONFIG_USB_FASTBOOT_BUF_ADDR
+               The fastboot protocol requires a large memory buffer for
+               downloads. Define this to the starting RAM address to use for
+               downloaded images.
+
+               CONFIG_USB_FASTBOOT_BUF_SIZE
+               The fastboot protocol requires a large memory buffer for
+               downloads. This buffer should be as large as possible for a
+               platform. Define this to the size available RAM for fastboot.
+
 - Journaling Flash filesystem support:
                CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
                CONFIG_JFFS2_NAND_DEV
@@ -2529,6 +2582,19 @@ CBFS (Coreboot Filesystem) support
 
                Specify the number of FPGA devices to support.
 
+               CONFIG_CMD_FPGA_LOADMK
+
+               Enable support for fpga loadmk command
+
+               CONFIG_CMD_FPGA_LOADP
+
+               Enable support for fpga loadp command - load partial bitstream
+
+               CONFIG_CMD_FPGA_LOADBP
+
+               Enable support for fpga loadbp command - load partial bitstream
+               (Xilinx only)
+
                CONFIG_SYS_FPGA_PROG_FEEDBACK
 
                Enable printing of hash marks during FPGA configuration.
index 5761def..3d331cc 100644 (file)
@@ -7,6 +7,8 @@
 #ifndef __ASM_ARC_CONFIG_H_
 #define __ASM_ARC_CONFIG_H_
 
+#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+
 #define CONFIG_LMB
 
 #endif /*__ASM_ARC_CONFIG_H_ */
index 7d7725c..0e6c0da 100644 (file)
@@ -165,3 +165,20 @@ void at91_macb_hw_init(void)
 #endif
 }
 #endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void at91_mci_hw_init(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+       at91_set_a_periph(AT91_PIO_PORTA, 0, 0);        /* MCI0 CLK */
+       at91_set_a_periph(AT91_PIO_PORTA, 1, 0);        /* MCI0 CDA */
+       at91_set_a_periph(AT91_PIO_PORTA, 2, 0);        /* MCI0 DA0 */
+       at91_set_a_periph(AT91_PIO_PORTA, 3, 0);        /* MCI0 DA1 */
+       at91_set_a_periph(AT91_PIO_PORTA, 4, 0);        /* MCI0 DA2 */
+       at91_set_a_periph(AT91_PIO_PORTA, 5, 0);        /* MCI0 DA3 */
+
+       /* Enable clock */
+       writel(1 << ATMEL_ID_MCI0, &pmc->pcer);
+}
+#endif
index ab869b1..232118d 100644 (file)
@@ -12,7 +12,7 @@ obj-y += cache_v7.o
 obj-y  += cpu.o
 obj-y  += syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y  += lowlevel_init.o
 endif
index 5566310..aae3f09 100644 (file)
@@ -14,7 +14,6 @@ endif
 
 obj-$(CONFIG_TI816X)   += clock_ti816x.o
 obj-y  += sys_info.o
-obj-y  += mem.o
 obj-y  += ddr.o
 obj-y  += emif4.o
 obj-y  += board.o
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
deleted file mode 100644 (file)
index 56c9e7d..0000000
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- *     Mansoor Ahamed <mansoor.ahamed@ti.com>
- *
- * Initial Code from:
- *     Manikandan Pillai <mani.pillai@ti.com>
- *     Richard Woodruff <r-woodruff2@ti.com>
- *     Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <command.h>
-
-struct gpmc *gpmc_cfg;
-
-
-void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
-                       u32 size)
-{
-       writel(0, &cs->config7);
-       sdelay(1000);
-       /* Delay for settling */
-       writel(gpmc_config[0], &cs->config1);
-       writel(gpmc_config[1], &cs->config2);
-       writel(gpmc_config[2], &cs->config3);
-       writel(gpmc_config[3], &cs->config4);
-       writel(gpmc_config[4], &cs->config5);
-       writel(gpmc_config[5], &cs->config6);
-       /* Enable the config */
-       writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
-               (1 << 6)), &cs->config7);
-       sdelay(2000);
-}
-
-/*****************************************************
- * gpmc_init(): init gpmc bus
- * Init GPMC for x16, MuxMode (SDRAM in x32).
- * This code can only be executed from SRAM or SDRAM.
- *****************************************************/
-void gpmc_init(void)
-{
-       /* putting a blanket check on GPMC based on ZeBu for now */
-       gpmc_cfg = (struct gpmc *)GPMC_BASE;
-#if defined(CONFIG_NOR)
-/* configure GPMC for NOR */
-       const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
-                                               STNOR_GPMC_CONFIG2,
-                                               STNOR_GPMC_CONFIG3,
-                                               STNOR_GPMC_CONFIG4,
-                                               STNOR_GPMC_CONFIG5,
-                                               STNOR_GPMC_CONFIG6,
-                                               STNOR_GPMC_CONFIG7
-                                               };
-       u32 size = GPMC_SIZE_16M;
-       u32 base = CONFIG_SYS_FLASH_BASE;
-#elif defined(CONFIG_NAND)
-/* configure GPMC for NAND */
-       const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
-                                               M_NAND_GPMC_CONFIG2,
-                                               M_NAND_GPMC_CONFIG3,
-                                               M_NAND_GPMC_CONFIG4,
-                                               M_NAND_GPMC_CONFIG5,
-                                               M_NAND_GPMC_CONFIG6,
-                                               0
-                                               };
-       u32 size = GPMC_SIZE_256M;
-       u32 base = CONFIG_SYS_NAND_BASE;
-#else
-       const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
-       u32 size = 0;
-       u32 base = 0;
-#endif
-       /* global settings */
-       writel(0x00000008, &gpmc_cfg->sysconfig);
-       writel(0x00000000, &gpmc_cfg->irqstatus);
-       writel(0x00000000, &gpmc_cfg->irqenable);
-#ifdef CONFIG_NOR
-       writel(0x00000200, &gpmc_cfg->config);
-#else
-       writel(0x00000012, &gpmc_cfg->config);
-#endif
-       /*
-        * Disable the GPMC0 config set by ROM code
-        */
-       writel(0, &gpmc_cfg->cs[0].config7);
-       sdelay(1000);
-       /* enable chip-select specific configurations */
-       enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
-}
index 50eb598..2ce682f 100644 (file)
@@ -79,12 +79,24 @@ u32 get_sysboot_value(void)
 }
 
 #ifdef CONFIG_DISPLAY_CPUINFO
+static char *cpu_revs[] = {
+               "1.0",
+               "2.0",
+               "2.1"};
+
+
+static char *dev_types[] = {
+               "TST",
+               "EMU",
+               "HS",
+               "GP"};
+
 /**
  * Print CPU information
  */
 int print_cpuinfo(void)
 {
-       char *cpu_s, *sec_s;
+       char *cpu_s, *sec_s, *rev_s;
 
        switch (get_cpu_type()) {
        case AM335X:
@@ -94,28 +106,21 @@ int print_cpuinfo(void)
                cpu_s = "TI81XX";
                break;
        default:
-               cpu_s = "Unknown cpu type";
+               cpu_s = "Unknown CPU type";
                break;
        }
 
-       switch (get_device_type()) {
-       case TST_DEVICE:
-               sec_s = "TST";
-               break;
-       case EMU_DEVICE:
-               sec_s = "EMU";
-               break;
-       case HS_DEVICE:
-               sec_s = "HS";
-               break;
-       case GP_DEVICE:
-               sec_s = "GP";
-               break;
-       default:
+       if (get_cpu_rev() < ARRAY_SIZE(cpu_revs))
+               rev_s = cpu_revs[get_cpu_rev()];
+       else
+               rev_s = "?";
+
+       if (get_device_type() < ARRAY_SIZE(dev_types))
+               sec_s = dev_types[get_device_type()];
+       else
                sec_s = "?";
-       }
 
-       printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev());
+       printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s);
 
        return 0;
 }
diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk
new file mode 100644 (file)
index 0000000..09eab70
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2014, Andreas BieƟmann <andreas.devel@googlemail.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+ifdef CONFIG_SPL_BUILD
+ALL-y  += boot.bin
+else
+ALL-y  += u-boot.img
+endif
index 59f5352..5f5132f 100644 (file)
@@ -27,8 +27,4 @@ obj-y += boot-common.o
 obj-y  += lowlevel_init.o
 endif
 
-ifndef CONFIG_SPL_BUILD
-ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 obj-y  += mem-common.o
-endif
-endif
index 429c4be..71c0cc8 100644 (file)
@@ -1384,8 +1384,10 @@ void sdram_init(void)
 
        if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
            (!in_sdram && !warm_reset())) {
-               do_bug0039_workaround(EMIF1_BASE);
-               do_bug0039_workaround(EMIF2_BASE);
+               if (emif1_enabled)
+                       do_bug0039_workaround(EMIF1_BASE);
+               if (emif2_enabled)
+                       do_bug0039_workaround(EMIF2_BASE);
        }
 
        debug("<<sdram_init()\n");
index 8ebc0ce..ba97d9e 100644 (file)
@@ -185,7 +185,7 @@ u32 omap_sdram_size(void)
 {
        u32 section, i, valid;
        u64 sdram_start = 0, sdram_end = 0, addr,
-           size, total_size = 0, trap_size = 0;
+           size, total_size = 0, trap_size = 0, trap_start = 0;
 
        for (i = 0; i < 4; i++) {
                section = __raw_readl(DMM_BASE + i*4);
@@ -194,8 +194,8 @@ u32 omap_sdram_size(void)
                addr = section & EMIF_SYS_ADDR_MASK;
 
                /* See if the address is valid */
-               if ((addr >= DRAM_ADDR_SPACE_START) &&
-                   (addr < DRAM_ADDR_SPACE_END)) {
+               if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) &&
+                   (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) {
                        size = ((section & EMIF_SYS_SIZE_MASK) >>
                                   EMIF_SYS_SIZE_SHIFT);
                        size = 1 << size;
@@ -208,12 +208,15 @@ u32 omap_sdram_size(void)
                                        sdram_end = addr + size;
                        } else {
                                trap_size = size;
+                               trap_start = addr;
                        }
-
                }
-
        }
-       total_size = (sdram_end - sdram_start) - (trap_size);
+
+       if ((trap_start >= sdram_start) && (trap_start < sdram_end))
+               total_size = (sdram_end - sdram_start) - (trap_size);
+       else
+               total_size = sdram_end - sdram_start;
 
        return total_size;
 }
index afc1bc1..944ef84 100644 (file)
  * (C) Copyright 2010
  * Texas Instruments, <www.ti.com>
  *
- * Steve Sakoman <steve@sakoman.com>
+ * Author :
+ *     Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *     Manikandan Pillai <mani.pillai@ti.com>
+ *     Richard Woodruff <r-woodruff2@ti.com>
+ *     Syed Mohammed Khasim <khasim@ti.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#include <common.h>
+#include <asm/io.h>
 #include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
+#include <command.h>
+#include <linux/mtd/omap_gpmc.h>
 
 struct gpmc *gpmc_cfg;
 
+#if defined(CONFIG_OMAP34XX)
+/********************************************************
+ *  mem_ok() - test used to see if timings are correct
+ *             for a part. Helps in guessing which part
+ *             we are currently using.
+ *******************************************************/
+u32 mem_ok(u32 cs)
+{
+       u32 val1, val2, addr;
+       u32 pattern = 0x12345678;
+
+       addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
+
+       writel(0x0, addr + 0x400);      /* clear pos A */
+       writel(pattern, addr);          /* pattern to pos B */
+       writel(0x0, addr + 4);          /* remove pattern off the bus */
+       val1 = readl(addr + 0x400);     /* get pos A value */
+       val2 = readl(addr);             /* get val2 */
+       writel(0x0, addr + 0x400);      /* clear pos A */
+
+       if ((val1 != 0) || (val2 != pattern))   /* see if pos A val changed */
+               return 0;
+       else
+               return 1;
+}
+#endif
+
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+                       u32 size)
+{
+       writel(0, &cs->config7);
+       sdelay(1000);
+       /* Delay for settling */
+       writel(gpmc_config[0], &cs->config1);
+       writel(gpmc_config[1], &cs->config2);
+       writel(gpmc_config[2], &cs->config3);
+       writel(gpmc_config[3], &cs->config4);
+       writel(gpmc_config[4], &cs->config5);
+       writel(gpmc_config[5], &cs->config6);
+       /* Enable the config */
+       writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
+               (1 << 6)), &cs->config7);
+       sdelay(2000);
+}
+
 /*****************************************************
  * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
  * This code can only be executed from SRAM or SDRAM.
  *****************************************************/
 void gpmc_init(void)
 {
+       /* putting a blanket check on GPMC based on ZeBu for now */
        gpmc_cfg = (struct gpmc *)GPMC_BASE;
-
+#if defined(CONFIG_NOR)
+/* configure GPMC for NOR */
+       const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
+                                               STNOR_GPMC_CONFIG2,
+                                               STNOR_GPMC_CONFIG3,
+                                               STNOR_GPMC_CONFIG4,
+                                               STNOR_GPMC_CONFIG5,
+                                               STNOR_GPMC_CONFIG6,
+                                               STNOR_GPMC_CONFIG7
+                                               };
+       u32 size = GPMC_SIZE_16M;
+       u32 base = CONFIG_SYS_FLASH_BASE;
+#elif defined(CONFIG_NAND)
+/* configure GPMC for NAND */
+       const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
+                                               M_NAND_GPMC_CONFIG2,
+                                               M_NAND_GPMC_CONFIG3,
+                                               M_NAND_GPMC_CONFIG4,
+                                               M_NAND_GPMC_CONFIG5,
+                                               M_NAND_GPMC_CONFIG6,
+                                               0
+                                               };
+       u32 size = GPMC_SIZE_256M;
+       u32 base = CONFIG_SYS_NAND_BASE;
+#elif defined(CONFIG_CMD_ONENAND)
+       const u32 gpmc_regs[GPMC_MAX_REG] = {   ONENAND_GPMC_CONFIG1,
+                                               ONENAND_GPMC_CONFIG2,
+                                               ONENAND_GPMC_CONFIG3,
+                                               ONENAND_GPMC_CONFIG4,
+                                               ONENAND_GPMC_CONFIG5,
+                                               ONENAND_GPMC_CONFIG6,
+                                               0
+                                               };
+       u32 base = PISMO1_ONEN_BASE;
+       u32 size = PISMO1_ONEN_SIZE;
+#else
+       const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
+       u32 size = 0;
+       u32 base = 0;
+#endif
        /* global settings */
-       writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
-       writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
-
+       writel(0x00000008, &gpmc_cfg->sysconfig);
+       writel(0x00000000, &gpmc_cfg->irqstatus);
+       writel(0x00000000, &gpmc_cfg->irqenable);
+       writel(0x00000000, &gpmc_cfg->timeout_control);
+#ifdef CONFIG_NOR
+       writel(0x00000200, &gpmc_cfg->config);
+#else
+       writel(0x00000012, &gpmc_cfg->config);
+#endif
        /*
         * Disable the GPMC0 config set by ROM code
-        * It conflicts with our MPDB (both at 0x08000000)
         */
        writel(0, &gpmc_cfg->cs[0].config7);
+       sdelay(1000);
+       /* enable chip-select specific configurations */
+       enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 }
index 39ff257..cf86046 100644 (file)
@@ -9,7 +9,6 @@ obj-y   := lowlevel_init.o
 
 obj-y  += board.o
 obj-y  += clock.o
-obj-y  += mem.o
 obj-y  += sys_info.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_OMAP3_ID_NAND)        += spl_id_nand.o
index ad97132..4baca11 100644 (file)
@@ -372,6 +372,38 @@ struct vcores_data dra752_volts = {
        .iva.pmic       = &tps659038,
 };
 
+struct vcores_data dra722_volts = {
+       .mpu.value      = 1000,
+       .mpu.efuse.reg  = STD_FUSE_OPP_VMIN_MPU_NOM,
+       .mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .mpu.addr       = 0x23,
+       .mpu.pmic       = &tps659038,
+
+       .eve.value      = 1000,
+       .eve.efuse.reg  = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+       .eve.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .eve.addr       = 0x2f,
+       .eve.pmic       = &tps659038,
+
+       .gpu.value      = 1000,
+       .gpu.efuse.reg  = STD_FUSE_OPP_VMIN_GPU_NOM,
+       .gpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .gpu.addr       = 0x2f,
+       .gpu.pmic       = &tps659038,
+
+       .core.value     = 1000,
+       .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
+       .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
+       .core.addr      = 0x27,
+       .core.pmic      = &tps659038,
+
+       .iva.value      = 1000,
+       .iva.efuse.reg  = STD_FUSE_OPP_VMIN_IVA_NOM,
+       .iva.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+       .iva.addr       = 0x2f,
+       .iva.pmic       = &tps659038,
+};
+
 /*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
@@ -558,6 +590,13 @@ void hw_data_init(void)
        *ctrl = &dra7xx_ctrl;
        break;
 
+       case DRA722_ES1_0:
+       *prcm = &dra7xx_prcm;
+       *dplls_data = &dra7xx_dplls;
+       *omap_vcores = &dra722_volts;
+       *ctrl = &dra7xx_ctrl;
+       break;
+
        default:
                printf("\n INVALID OMAP REVISION ");
        }
@@ -580,6 +619,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA722_ES1_0:
                *regs = &ioregs_dra7xx_es1;
                break;
 
index 93feb16..a8a474a 100644 (file)
@@ -336,6 +336,9 @@ void init_omap_revision(void)
        case DRA752_CONTROL_ID_CODE_ES1_1:
                *omap_si_rev = DRA752_ES1_1;
                break;
+       case DRA722_CONTROL_ID_CODE_ES1_0:
+               *omap_si_rev = DRA722_ES1_0;
+               break;
        default:
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
        }
index 7292161..ff08ef4 100644 (file)
@@ -447,10 +447,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_wkup_control_spare_r           = 0x4AE0C5B4,
        .control_wkup_control_spare_r_c0        = 0x4AE0C5B8,
        .control_srcomp_east_side_wkup          = 0x4AE0C5BC,
-       .control_efuse_1                        = 0x4AE0C5C0,
-       .control_efuse_2                        = 0x4AE0C5C4,
-       .control_efuse_3                        = 0x4AE0C5C8,
-       .control_efuse_4                        = 0x4AE0C5CC,
+       .control_efuse_1                        = 0x4AE0C5C8,
+       .control_efuse_2                        = 0x4AE0C5CC,
+       .control_efuse_3                        = 0x4AE0C5D0,
+       .control_efuse_4                        = 0x4AE0C5D4,
        .control_efuse_13                       = 0x4AE0C5F0,
 };
 
index 16a91f9..e2ebab8 100644 (file)
@@ -229,6 +229,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
        .is_ma_present  = 0x1
 };
 
+/*
+ * DRA722 EVM EMIF1 CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
+       .dmm_lisa_map_0 = 0x0,
+       .dmm_lisa_map_1 = 0x0,
+       .dmm_lisa_map_2 = 0x80600100,
+       .dmm_lisa_map_3 = 0xFF020100,
+       .is_ma_present  = 0x1
+};
+
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
        switch (omap_revision()) {
@@ -255,6 +266,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                        break;
                }
                break;
+       case DRA722_ES1_0:
        default:
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }
@@ -275,8 +287,11 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
-       default:
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
+               break;
+       case DRA722_ES1_0:
+       default:
+               *dmm_lisa_regs = &lisa_map_2G_x_2;
        }
 
 }
@@ -463,6 +478,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA722_ES1_0:
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
@@ -630,6 +646,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA722_ES1_0:
                bug_00339_regs_ptr = dra_bug_00339_regs;
                *iterations = sizeof(dra_bug_00339_regs)/
                             sizeof(dra_bug_00339_regs[0]);
index 2221999..fad004c 100644 (file)
@@ -11,7 +11,7 @@ obj-y += emac.o
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
-obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
-obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
deleted file mode 100644 (file)
index 2de58ed..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
- *
- * Copyright (C) 2013 Renesas Electronics Corporation
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-#include <common.h>
-#include <asm/io.h>
-
-#define PRR 0xFF000044
-
-u32 rmobile_get_cpu_type(void)
-{
-       u32 product;
-
-       product = readl(PRR);
-
-       return (u32)((product & 0x00007F00) >> 8);
-}
-
-u32 rmobile_get_cpu_rev_integer(void)
-{
-       u32 product;
-
-       product = readl(PRR);
-
-       return (u32)((product & 0x000000F0) >> 4);
-}
similarity index 50%
rename from arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
rename to arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
index 7232e23..42ee30f 100644 (file)
@@ -1,8 +1,7 @@
 /*
- * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
- *     This file is r8a7790 processor support.
+ * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
  *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
  */
@@ -18,5 +17,10 @@ u32 rmobile_get_cpu_type(void)
 
 u32 rmobile_get_cpu_rev_integer(void)
 {
-       return (readl(PRR) & 0x000000F0) >> 4;
+       return ((readl(PRR) & 0x000000F0) >> 4) + 1;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+       return readl(PRR) & 0x0000000F;
 }
index 83d5282..7a7c97d 100644 (file)
@@ -44,35 +44,30 @@ static u32 __rmobile_get_cpu_rev_fraction(void)
 u32 rmobile_get_cpu_rev_fraction(void)
                __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
 
+/* CPU infomation table */
+static const struct {
+       u16 cpu_type;
+       u8 cpu_name[10];
+} rmobile_cpuinfo[] = {
+       { 0x37, "SH73A0" },
+       { 0x40, "R8A7740" },
+       { 0x45, "R8A7790" },
+       { 0x47, "R8A7791" },
+       { 0x0, "CPU" },
+};
+
 int print_cpuinfo(void)
 {
-       switch (rmobile_get_cpu_type()) {
-       case 0x37:
-               printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n",
-                      rmobile_get_cpu_rev_integer(),
-                      rmobile_get_cpu_rev_fraction());
-               break;
-       case 0x40:
-               printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n",
-                      rmobile_get_cpu_rev_integer(),
-                      rmobile_get_cpu_rev_fraction());
-               break;
-
-       case 0x45:
-               printf("CPU: Renesas Electronics R8A7790 rev %d\n",
-                      rmobile_get_cpu_rev_integer());
-               break;
-
-       case 0x47:
-               printf("CPU: Renesas Electronics R8A7791 rev %d\n",
-                       rmobile_get_cpu_rev_integer());
-               break;
-
-       default:
-               printf("CPU: Renesas Electronics CPU rev %d.%d\n",
-                      rmobile_get_cpu_rev_integer(),
-                      rmobile_get_cpu_rev_fraction());
-               break;
+       int i = 0;
+       u32 cpu_type = rmobile_get_cpu_type();
+       for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++) {
+               if (rmobile_cpuinfo[i].cpu_type == cpu_type) {
+                       printf("CPU: Renesas Electronics %s rev %d.%d\n",
+                              rmobile_cpuinfo[i].cpu_name,
+                              rmobile_get_cpu_rev_integer(),
+                              rmobile_get_cpu_rev_fraction());
+                       break;
+               }
        }
        return 0;
 }
index e07cc80..287f8d7 100644 (file)
@@ -2,7 +2,7 @@
  * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
  *     This file is lager low level initialize.
  *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
  */
@@ -36,16 +36,32 @@ do_cpu_waiting:
        .align  4
 do_lowlevel_init:
        /* surpress wfe if ca15 */
-       tst     r4, #4
+       tst r4, #4
        mrceq p15, 0, r0, c1, c0, 1     /* actlr */
        orreq r0, r0, #(1<<7)
        mcreq p15, 0, r0, c1, c0, 1
+
        /* and set l2 latency */
        mrceq p15, 1, r0, c9, c0, 2     /* l2ctlr */
        orreq r0, r0, #0x00000800
        orreq r0, r0, #0x00000003
        mcreq p15, 1, r0, c9, c0, 2
 
+       mrc p15, 0, r0, c0, c0, 5       /* r0 = MPIDR */
+       and r0, r0, #0xf00
+       lsr r0, r0, #8
+       tst r0, #1                      /* only need for cluster 0 */
+       bne _exit_init_l2_a15
+
+       mrc p15, 1, r0, c9, c0, 2       /* r0 = L2CTLR */
+       and r1, r0, #7
+       cmp r1, #3                      /* has already been set up */
+       bicne r0, r0, #0xe7
+       orrne r0, r0, #0x83             /* L2CTLR[7:6] + L2CTLR[2:0] */
+       orrne r0, r0, #0x20             /* L2CTLR[5] */
+       mcrne p15, 1, r0, c9, c0, 2
+
+_exit_init_l2_a15:
        ldr     r3, =(CONFIG_SYS_INIT_SP_ADDR)
        sub     sp, r3, #4
        str     lr, [sp]
index f49f990..46d6e60 100644 (file)
@@ -913,7 +913,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* SEL_SCIF3 [2] */
                FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
                /* SEL_IEB [2] */
-               FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+               FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
                /* SEL_MMC [1] */
                FN_SEL_MMC_0, FN_SEL_MMC_1,
                /* SEL_SCIF5 [1] */
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
new file mode 100644 (file)
index 0000000..a64bfa1
--- /dev/null
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+#
+# Based on some other Makefile
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+obj-y  += timer.o
+obj-y  += board.o
+obj-y  += clock.o
+obj-y  += pinmux.o
+obj-$(CONFIG_SUN7I)    += clock_sun4i.o
+
+ifndef CONFIG_SPL_BUILD
+obj-y  += cpu_info.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SUN7I)    += dram.o
+ifdef CONFIG_SPL_FEL
+obj-y  += start.o
+endif
+endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
new file mode 100644 (file)
index 0000000..49c9448
--- /dev/null
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Some init for sunxi platform.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <serial.h>
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/timer.h>
+
+#ifdef CONFIG_SPL_BUILD
+/* Pointer to the global data structure for SPL */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The sunxi internal brom will try to loader external bootloader
+ * from mmc0, nand flash, mmc2.
+ * Unfortunately we can't check how SPL was loaded so assume
+ * it's always the first SD/MMC controller
+ */
+u32 spl_boot_device(void)
+{
+       return BOOT_DEVICE_MMC1;
+}
+
+/* No confirmation data available in SPL yet. Hardcode bootmode */
+u32 spl_boot_mode(void)
+{
+       return MMCSD_MODE_RAW;
+}
+#endif
+
+int gpio_init(void)
+{
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
+       sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
+       sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
+
+       return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
+/* do some early init */
+void s_init(void)
+{
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
+       /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+       asm volatile(
+               "mrc p15, 0, r0, c1, c0, 1\n"
+               "orr r0, r0, #1 << 6\n"
+               "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+
+       clock_init();
+       timer_init();
+       gpio_init();
+
+#ifdef CONFIG_SPL_BUILD
+       gd = &gdata;
+       preloader_console_init();
+
+       sunxi_board_init();
+#endif
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+int cpu_eth_init(bd_t *bis)
+{
+       int rc;
+
+#ifdef CONFIG_SUNXI_GMAC
+       rc = sunxi_gmac_initialize(bis);
+       if (rc < 0) {
+               printf("sunxi: failed to initialize gmac\n");
+               return rc;
+       }
+#endif
+
+       return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
new file mode 100644 (file)
index 0000000..47fb70f
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+
+int clock_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+       clock_init_safe();
+#endif
+       clock_init_uart();
+
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
new file mode 100644 (file)
index 0000000..5a7da3c
--- /dev/null
@@ -0,0 +1,188 @@
+/*
+ * sun4i, sun5i and sun7i specific clock code
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sys_proto.h>
+
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       /* Set safe defaults until PMU is configured */
+       writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+              AHB_DIV_2 << AHB_DIV_SHIFT |
+              APB0_DIV_1 << APB0_DIV_SHIFT |
+              CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+              &ccm->cpu_ahb_apb0_cfg);
+       writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
+       sdelay(200);
+       writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+              AHB_DIV_2 << AHB_DIV_SHIFT |
+              APB0_DIV_1 << APB0_DIV_SHIFT |
+              CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+              &ccm->cpu_ahb_apb0_cfg);
+#ifdef CONFIG_SUN7I
+       writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
+              &ccm->ahb_gate0);
+#endif
+       writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+}
+#endif
+
+void clock_init_uart(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       /* uart clock source is apb1 */
+       writel(APB1_CLK_SRC_OSC24M|
+              APB1_CLK_RATE_N_1|
+              APB1_CLK_RATE_M(1),
+              &ccm->apb1_clk_div_cfg);
+
+       /* open the clock for uart */
+       setbits_le32(&ccm->apb1_gate,
+               CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
+}
+
+int clock_twi_onoff(int port, int state)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       if (port > 2)
+               return -1;
+
+       /* set the apb clock gate for twi */
+       if (state)
+               setbits_le32(&ccm->apb1_gate,
+                            CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
+       else
+               clrbits_le32(&ccm->apb1_gate,
+                            CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
+
+       return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#define PLL1_CFG(N, K, M, P)   ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
+                                 0 << CCM_PLL1_CFG_VCO_RST_SHIFT |  \
+                                 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
+                                 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
+                                16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
+                                (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
+                                 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
+                                (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
+                                (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
+                                 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
+                                 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
+                                (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
+
+static struct {
+       u32 pll1_cfg;
+       unsigned int freq;
+} pll1_para[] = {
+       /* This array must be ordered by frequency. */
+       { PLL1_CFG(16, 0, 0, 0), 384000000 },
+       { PLL1_CFG(16, 1, 0, 0), 768000000 },
+       { PLL1_CFG(20, 1, 0, 0), 960000000 },
+       { PLL1_CFG(21, 1, 0, 0), 1008000000},
+       { PLL1_CFG(22, 1, 0, 0), 1056000000},
+       { PLL1_CFG(23, 1, 0, 0), 1104000000},
+       { PLL1_CFG(24, 1, 0, 0), 1152000000},
+       { PLL1_CFG(25, 1, 0, 0), 1200000000},
+       { PLL1_CFG(26, 1, 0, 0), 1248000000},
+       { PLL1_CFG(27, 1, 0, 0), 1296000000},
+       { PLL1_CFG(28, 1, 0, 0), 1344000000},
+       { PLL1_CFG(29, 1, 0, 0), 1392000000},
+       { PLL1_CFG(30, 1, 0, 0), 1440000000},
+       { PLL1_CFG(31, 1, 0, 0), 1488000000},
+       /* Final catchall entry */
+       { PLL1_CFG(31, 1, 0, 0), ~0},
+};
+
+void clock_set_pll1(unsigned int hz)
+{
+       int i = 0;
+       int axi, ahb, apb0;
+       struct sunxi_ccm_reg * const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       /* Find target frequency */
+       while (pll1_para[i].freq < hz)
+               i++;
+
+       hz = pll1_para[i].freq;
+
+       /* Calculate system clock divisors */
+       axi = DIV_ROUND_UP(hz, 432000000);      /* Max 450MHz */
+       ahb = DIV_ROUND_UP(hz/axi, 204000000);  /* Max 250MHz */
+       apb0 = 2;                               /* Max 150MHz */
+
+       printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
+
+       /* Map divisors to register values */
+       axi = axi - 1;
+       if (ahb > 4)
+               ahb = 3;
+       else if (ahb > 2)
+               ahb = 2;
+       else if (ahb > 1)
+               ahb = 1;
+       else
+               ahb = 0;
+
+       apb0 = apb0 - 1;
+
+       /* Switch to 24MHz clock while changing PLL1 */
+       writel(AXI_DIV_1 << AXI_DIV_SHIFT |
+              AHB_DIV_2 << AHB_DIV_SHIFT |
+              APB0_DIV_1 << APB0_DIV_SHIFT |
+              CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+              &ccm->cpu_ahb_apb0_cfg);
+       sdelay(20);
+
+       /* Configure sys clock divisors */
+       writel(axi << AXI_DIV_SHIFT |
+              ahb << AHB_DIV_SHIFT |
+              apb0 << APB0_DIV_SHIFT |
+              CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+              &ccm->cpu_ahb_apb0_cfg);
+
+       /* Configure PLL1 at the desired frequency */
+       writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
+       sdelay(200);
+
+       /* Switch CPU to PLL1 */
+       writel(axi << AXI_DIV_SHIFT |
+              ahb << AHB_DIV_SHIFT |
+              apb0 << APB0_DIV_SHIFT |
+              CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+              &ccm->cpu_ahb_apb0_cfg);
+       sdelay(20);
+}
+#endif
+
+unsigned int clock_get_pll6(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       uint32_t rval = readl(&ccm->pll6_cfg);
+       int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
+       int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
+       return 24000000 * n * k / 2;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk
new file mode 100644 (file)
index 0000000..00f5ffc
--- /dev/null
@@ -0,0 +1,8 @@
+# Build a combined spl + u-boot image
+ifdef CONFIG_SPL
+ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_SPL_FEL
+ALL-y += u-boot-sunxi-with-spl.bin
+endif
+endif
+endif
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
new file mode 100644 (file)
index 0000000..b4c3d5c
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+       puts("CPU:   Allwinner A20 (SUN7I)\n");
+       return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c
new file mode 100644 (file)
index 0000000..b43c4b4
--- /dev/null
@@ -0,0 +1,593 @@
+/*
+ * sunxi DRAM controller initialization
+ * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
+ * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+ *
+ * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
+ * and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * Unfortunately the only documentation we have on the sun7i DRAM
+ * controller is Allwinner boot0 + boot1 code, and that code uses
+ * magic numbers & shifts with no explanations. Hence this code is
+ * rather undocumented and full of magic.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/sys_proto.h>
+
+#define CPU_CFG_CHIP_VER(n) ((n) << 6)
+#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
+#define CPU_CFG_CHIP_REV_A 0x0
+#define CPU_CFG_CHIP_REV_C1 0x1
+#define CPU_CFG_CHIP_REV_C2 0x2
+#define CPU_CFG_CHIP_REV_B 0x3
+
+/*
+ * Wait up to 1s for mask to be clear in given reg.
+ */
+static void await_completion(u32 *reg, u32 mask)
+{
+       unsigned long tmo = timer_get_us() + 1000000;
+
+       while (readl(reg) & mask) {
+               if (timer_get_us() > tmo)
+                       panic("Timeout initialising DRAM\n");
+       }
+}
+
+static void mctl_ddr3_reset(void)
+{
+       struct sunxi_dram_reg *dram =
+                       (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
+       udelay(2);
+       setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+}
+
+static void mctl_set_drive(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
+                       DRAM_MCR_MODE_EN(0x3) |
+                       0xffc);
+}
+
+static void mctl_itm_disable(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
+}
+
+static void mctl_itm_enable(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
+}
+
+static void mctl_enable_dll0(u32 phase)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
+                       ((phase >> 16) & 0x3f) << 6);
+       clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
+       udelay(2);
+
+       clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
+       udelay(22);
+
+       clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
+       udelay(22);
+}
+
+/*
+ * Note: This differs from pm/standby in that it checks the bus width
+ */
+static void mctl_enable_dllx(u32 phase)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 i, n, bus_width;
+
+       bus_width = readl(&dram->dcr);
+
+       if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
+           DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
+               n = DRAM_DCR_NR_DLLCR_32BIT;
+       else
+               n = DRAM_DCR_NR_DLLCR_16BIT;
+
+       for (i = 1; i < n; i++) {
+               clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
+                               (phase & 0xf) << 14);
+               clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
+                               DRAM_DLLCR_DISABLE);
+               phase >>= 4;
+       }
+       udelay(2);
+
+       for (i = 1; i < n; i++)
+               clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
+                            DRAM_DLLCR_DISABLE);
+       udelay(22);
+
+       for (i = 1; i < n; i++)
+               clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
+                               DRAM_DLLCR_NRESET);
+       udelay(22);
+}
+
+static u32 hpcr_value[32] = {
+#ifdef CONFIG_SUN7I
+       0x0301, 0x0301, 0x0301, 0x0301,
+       0x0301, 0x0301, 0x0301, 0x0301,
+       0, 0, 0, 0,
+       0, 0, 0, 0,
+       0x1031, 0x1031, 0x0735, 0x1035,
+       0x1035, 0x0731, 0x1031, 0x0735,
+       0x1035, 0x1031, 0x0731, 0x1035,
+       0x0001, 0x1031, 0, 0x1031
+       /* last row differs from boot0 source table
+        * 0x1031, 0x0301, 0x0301, 0x0731
+        * but boot0 code skips #28 and #30, and sets #29 and #31 to the
+        * value from #28 entry (0x1031)
+        */
+#endif
+};
+
+static void mctl_configure_hostport(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 i;
+
+       for (i = 0; i < 32; i++)
+               writel(hpcr_value[i], &dram->hpcr[i]);
+}
+
+static void mctl_setup_dram_clock(u32 clk)
+{
+       u32 reg_val;
+       struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+       /* setup DRAM PLL */
+       reg_val = readl(&ccm->pll5_cfg);
+       reg_val &= ~CCM_PLL5_CTRL_M_MASK;               /* set M to 0 (x1) */
+       reg_val &= ~CCM_PLL5_CTRL_K_MASK;               /* set K to 0 (x1) */
+       reg_val &= ~CCM_PLL5_CTRL_N_MASK;               /* set N to 0 (x0) */
+       reg_val &= ~CCM_PLL5_CTRL_P_MASK;               /* set P to 0 (x1) */
+       if (clk >= 540 && clk < 552) {
+               /* dram = 540MHz, pll5p = 540MHz */
+               reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+               reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
+               reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
+               reg_val |= CCM_PLL5_CTRL_P(1);
+       } else if (clk >= 512 && clk < 528) {
+               /* dram = 512MHz, pll5p = 384MHz */
+               reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
+               reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
+               reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
+               reg_val |= CCM_PLL5_CTRL_P(2);
+       } else if (clk >= 496 && clk < 504) {
+               /* dram = 496MHz, pll5p = 372MHz */
+               reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
+               reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
+               reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
+               reg_val |= CCM_PLL5_CTRL_P(2);
+       } else if (clk >= 468 && clk < 480) {
+               /* dram = 468MHz, pll5p = 468MHz */
+               reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+               reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
+               reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
+               reg_val |= CCM_PLL5_CTRL_P(1);
+       } else if (clk >= 396 && clk < 408) {
+               /* dram = 396MHz, pll5p = 396MHz */
+               reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+               reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
+               reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
+               reg_val |= CCM_PLL5_CTRL_P(1);
+       } else  {
+               /* any other frequency that is a multiple of 24 */
+               reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
+               reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
+               reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
+               reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
+       }
+       reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN;             /* PLL VCO Gain off */
+       reg_val |= CCM_PLL5_CTRL_EN;                    /* PLL On */
+       writel(reg_val, &ccm->pll5_cfg);
+       udelay(5500);
+
+       setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
+
+#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+       /* reset GPS */
+       clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
+       setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+       udelay(1);
+       clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
+#endif
+
+       /* setup MBUS clock */
+       reg_val = CCM_MBUS_CTRL_GATE |
+                 CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
+                 CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
+                 CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
+       writel(reg_val, &ccm->mbus_clk_cfg);
+
+       /*
+        * open DRAMC AHB & DLL register clock
+        * close it first
+        */
+       clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+       udelay(22);
+
+       /* then open it */
+       setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
+       udelay(22);
+}
+
+static int dramc_scan_readpipe(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 reg_val;
+
+       /* data training trigger */
+#ifdef CONFIG_SUN7I
+       clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
+#endif
+       setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+
+       /* check whether data training process has completed */
+       await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
+
+       /* check data training result */
+       reg_val = readl(&dram->csr);
+       if (reg_val & DRAM_CSR_FAILED)
+               return -1;
+
+       return 0;
+}
+
+static int dramc_scan_dll_para(void)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
+       const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
+                                0x02, 0x01, 0x00, 0x08, 0x10,
+                                0x18, 0x20, 0x28, 0x30, 0x38};
+       u32 clk_dqs_count[15];
+       u32 dqs_i, clk_i, cr_i;
+       u32 max_val, min_val;
+       u32 dqs_index, clk_index;
+
+       /* Find DQS_DLY Pass Count for every CLK_DLY */
+       for (clk_i = 0; clk_i < 15; clk_i++) {
+               clk_dqs_count[clk_i] = 0;
+               clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
+                               (clk_dly[clk_i] & 0x3f) << 6);
+               for (dqs_i = 0; dqs_i < 7; dqs_i++) {
+                       for (cr_i = 1; cr_i < 5; cr_i++) {
+                               clrsetbits_le32(&dram->dllcr[cr_i],
+                                               0x4f << 14,
+                                               (dqs_dly[dqs_i] & 0x4f) << 14);
+                       }
+                       udelay(2);
+                       if (dramc_scan_readpipe() == 0)
+                               clk_dqs_count[clk_i]++;
+               }
+       }
+       /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
+       for (dqs_i = 15; dqs_i > 0; dqs_i--) {
+               max_val = 15;
+               min_val = 15;
+               for (clk_i = 0; clk_i < 15; clk_i++) {
+                       if (clk_dqs_count[clk_i] == dqs_i) {
+                               max_val = clk_i;
+                               if (min_val == 15)
+                                       min_val = clk_i;
+                       }
+               }
+               if (max_val < 15)
+                       break;
+       }
+
+       /* Check if Find a CLK_DLY failed */
+       if (!dqs_i)
+               goto fail;
+
+       /* Find the middle index of CLK_DLY */
+       clk_index = (max_val + min_val) >> 1;
+       if ((max_val == (15 - 1)) && (min_val > 0))
+               /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
+                * value can be more close to the max_val
+                */
+               clk_index = (15 + clk_index) >> 1;
+       else if ((max_val < (15 - 1)) && (min_val == 0))
+               /* if CLK_DLY[0] is very good, then the middle value can be more
+                * close to the min_val
+                */
+               clk_index >>= 1;
+       if (clk_dqs_count[clk_index] < dqs_i)
+               clk_index = min_val;
+
+       /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
+        * read pipe again
+        */
+       clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
+                       (clk_dly[clk_index] & 0x3f) << 6);
+       max_val = 7;
+       min_val = 7;
+       for (dqs_i = 0; dqs_i < 7; dqs_i++) {
+               clk_dqs_count[dqs_i] = 0;
+               for (cr_i = 1; cr_i < 5; cr_i++) {
+                       clrsetbits_le32(&dram->dllcr[cr_i],
+                                       0x4f << 14,
+                                       (dqs_dly[dqs_i] & 0x4f) << 14);
+               }
+               udelay(2);
+               if (dramc_scan_readpipe() == 0) {
+                       clk_dqs_count[dqs_i] = 1;
+                       max_val = dqs_i;
+                       if (min_val == 7)
+                               min_val = dqs_i;
+               }
+       }
+
+       if (max_val < 7) {
+               dqs_index = (max_val + min_val) >> 1;
+               if ((max_val == (7-1)) && (min_val > 0))
+                       dqs_index = (7 + dqs_index) >> 1;
+               else if ((max_val < (7-1)) && (min_val == 0))
+                       dqs_index >>= 1;
+               if (!clk_dqs_count[dqs_index])
+                       dqs_index = min_val;
+               for (cr_i = 1; cr_i < 5; cr_i++) {
+                       clrsetbits_le32(&dram->dllcr[cr_i],
+                                       0x4f << 14,
+                                       (dqs_dly[dqs_index] & 0x4f) << 14);
+               }
+               udelay(2);
+               return dramc_scan_readpipe();
+       }
+
+fail:
+       clrbits_le32(&dram->dllcr[0], 0x3f << 6);
+       for (cr_i = 1; cr_i < 5; cr_i++)
+               clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
+       udelay(2);
+
+       return dramc_scan_readpipe();
+}
+
+static void dramc_clock_output_en(u32 on)
+{
+#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+
+       if (on)
+               setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+       else
+               clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
+#endif
+}
+
+static const u16 tRFC_table[2][6] = {
+       /*       256Mb    512Mb    1Gb      2Gb      4Gb      8Gb      */
+       /* DDR2  75ns     105ns    127.5ns  195ns    327.5ns  invalid  */
+       {        77,      108,     131,     200,     336,     336 },
+       /* DDR3  invalid  90ns     110ns    160ns    300ns    350ns    */
+       {        93,      93,      113,     164,     308,     359 }
+};
+
+static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 tRFC, tREFI;
+
+       tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
+       tREFI = (7987 * clk) >> 10;     /* <= 7.8us */
+
+       writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
+}
+
+unsigned long dramc_init(struct dram_para *para)
+{
+       struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
+       u32 reg_val;
+       u32 density;
+       int ret_val;
+
+       /* check input dram parameter structure */
+       if (!para)
+               return 0;
+
+       /* setup DRAM relative clock */
+       mctl_setup_dram_clock(para->clock);
+
+       /* reset external DRAM */
+       mctl_set_drive();
+
+       /* dram clock off */
+       dramc_clock_output_en(0);
+
+       mctl_itm_disable();
+       mctl_enable_dll0(para->tpr3);
+
+       /* configure external DRAM */
+       reg_val = 0x0;
+       if (para->type == DRAM_MEMORY_TYPE_DDR3)
+               reg_val |= DRAM_DCR_TYPE_DDR3;
+       reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
+
+       if (para->density == 256)
+               density = DRAM_DCR_CHIP_DENSITY_256M;
+       else if (para->density == 512)
+               density = DRAM_DCR_CHIP_DENSITY_512M;
+       else if (para->density == 1024)
+               density = DRAM_DCR_CHIP_DENSITY_1024M;
+       else if (para->density == 2048)
+               density = DRAM_DCR_CHIP_DENSITY_2048M;
+       else if (para->density == 4096)
+               density = DRAM_DCR_CHIP_DENSITY_4096M;
+       else if (para->density == 8192)
+               density = DRAM_DCR_CHIP_DENSITY_8192M;
+       else
+               density = DRAM_DCR_CHIP_DENSITY_256M;
+
+       reg_val |= DRAM_DCR_CHIP_DENSITY(density);
+       reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
+       reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
+       reg_val |= DRAM_DCR_CMD_RANK_ALL;
+       reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
+       writel(reg_val, &dram->dcr);
+
+#ifdef CONFIG_SUN7I
+       setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
+       if (para->tpr4 & 0x2)
+               clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
+       dramc_clock_output_en(1);
+#endif
+
+#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
+       /* set odt impendance divide ratio */
+       reg_val = ((para->zq) >> 8) & 0xfffff;
+       reg_val |= ((para->zq) & 0xff) << 20;
+       reg_val |= (para->zq) & 0xf0000000;
+       writel(reg_val, &dram->zqcr0);
+#endif
+
+#ifdef CONFIG_SUN7I
+       /* Set CKE Delay to about 1ms */
+       setbits_le32(&dram->idcr, 0x1ffff);
+#endif
+
+#ifdef CONFIG_SUN7I
+       if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
+               mctl_ddr3_reset();
+       else
+               setbits_le32(&dram->mcr, DRAM_MCR_RESET);
+#endif
+
+       udelay(1);
+
+       await_completion(&dram->ccr, DRAM_CCR_INIT);
+
+       mctl_enable_dllx(para->tpr3);
+
+       /* set refresh period */
+       dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
+
+       /* set timing parameters */
+       writel(para->tpr0, &dram->tpr0);
+       writel(para->tpr1, &dram->tpr1);
+       writel(para->tpr2, &dram->tpr2);
+
+       if (para->type == DRAM_MEMORY_TYPE_DDR3) {
+               reg_val = DRAM_MR_BURST_LENGTH(0x0);
+#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
+               reg_val |= DRAM_MR_POWER_DOWN;
+#endif
+               reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
+               reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
+       } else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
+               reg_val = DRAM_MR_BURST_LENGTH(0x2);
+               reg_val |= DRAM_MR_CAS_LAT(para->cas);
+               reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
+       }
+       writel(reg_val, &dram->mr);
+
+       writel(para->emr1, &dram->emr);
+       writel(para->emr2, &dram->emr2);
+       writel(para->emr3, &dram->emr3);
+
+       /* set DQS window mode */
+       clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
+
+#ifdef CONFIG_SUN7I
+       /* Command rate timing mode 2T & 1T */
+       if (para->tpr4 & 0x1)
+               setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
+#endif
+       /* reset external DRAM */
+       setbits_le32(&dram->ccr, DRAM_CCR_INIT);
+       await_completion(&dram->ccr, DRAM_CCR_INIT);
+
+#ifdef CONFIG_SUN7I
+       /* setup zq calibration manual */
+       reg_val = readl(&dram->ppwrsctl);
+       if ((reg_val & 0x1) == 1) {
+               /* super_standby_flag = 1 */
+
+               reg_val = readl(0x01c20c00 + 0x120); /* rtc */
+               reg_val &= 0x000fffff;
+               reg_val |= 0x17b00000;
+               writel(reg_val, &dram->zqcr0);
+
+               /* exit self-refresh state */
+               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
+               /* check whether command has been executed */
+               await_completion(&dram->dcr, 0x1 << 31);
+
+               udelay(2);
+
+               /* dram pad hold off */
+               setbits_le32(&dram->ppwrsctl, 0x16510000);
+
+               await_completion(&dram->ppwrsctl, 0x1);
+
+               /* exit self-refresh state */
+               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
+
+               /* check whether command has been executed */
+               await_completion(&dram->dcr, 0x1 << 31);
+
+               udelay(2);
+
+               /* issue a refresh command */
+               clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
+               await_completion(&dram->dcr, 0x1 << 31);
+
+               udelay(2);
+       }
+#endif
+
+       /* scan read pipe value */
+       mctl_itm_enable();
+       if (para->tpr3 & (0x1 << 31)) {
+               ret_val = dramc_scan_dll_para();
+               if (ret_val == 0)
+                       para->tpr3 =
+                               (((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
+                               (((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
+                               (((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
+                               (((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
+                               (((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
+                               );
+       } else {
+               ret_val = dramc_scan_readpipe();
+       }
+
+       if (ret_val < 0)
+               return 0;
+
+       /* configure all host port */
+       mctl_configure_hostport();
+
+       return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c
new file mode 100644 (file)
index 0000000..1f2843f
--- /dev/null
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+{
+       u32 bank = GPIO_BANK(pin);
+       u32 index = GPIO_CFG_INDEX(pin);
+       u32 offset = GPIO_CFG_OFFSET(pin);
+       struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+       clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
+
+       return 0;
+}
+
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+       u32 cfg;
+       u32 bank = GPIO_BANK(pin);
+       u32 index = GPIO_CFG_INDEX(pin);
+       u32 offset = GPIO_CFG_OFFSET(pin);
+       struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+       cfg = readl(&pio->cfg[0] + index);
+       cfg >>= offset;
+
+       return cfg & 0xf;
+}
+
+int sunxi_gpio_set_drv(u32 pin, u32 val)
+{
+       u32 bank = GPIO_BANK(pin);
+       u32 index = GPIO_DRV_INDEX(pin);
+       u32 offset = GPIO_DRV_OFFSET(pin);
+       struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+       clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
+
+       return 0;
+}
+
+int sunxi_gpio_set_pull(u32 pin, u32 val)
+{
+       u32 bank = GPIO_BANK(pin);
+       u32 index = GPIO_PULL_INDEX(pin);
+       u32 offset = GPIO_PULL_OFFSET(pin);
+       struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+       clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
+
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/start.c b/arch/arm/cpu/armv7/sunxi/start.c
new file mode 100644 (file)
index 0000000..6b392fa
--- /dev/null
@@ -0,0 +1 @@
+/* Intentionally empty. Only needed to get FEL SPL link line right */
diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c
new file mode 100644 (file)
index 0000000..3626389
--- /dev/null
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define TIMER_MODE   (0x0 << 7)        /* continuous mode */
+#define TIMER_DIV    (0x0 << 4)        /* pre scale 1 */
+#define TIMER_SRC    (0x1 << 2)        /* osc24m */
+#define TIMER_RELOAD (0x1 << 1)        /* reload internal value */
+#define TIMER_EN     (0x1 << 0)        /* enable timer */
+
+#define TIMER_CLOCK            (24 * 1000 * 1000)
+#define COUNT_TO_USEC(x)       ((x) / 24)
+#define USEC_TO_COUNT(x)       ((x) * 24)
+#define TICKS_PER_HZ           (TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x)         ((x) / TICKS_PER_HZ)
+
+#define TIMER_LOAD_VAL         0xffffffff
+
+#define TIMER_NUM              0       /* we use timer 0 */
+
+/* read the 32-bit timer */
+static ulong read_timer(void)
+{
+       struct sunxi_timer_reg *timers =
+               (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+       struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
+
+       /*
+        * The hardware timer counts down, therefore we invert to
+        * produce an incrementing timer.
+        */
+       return ~readl(&timer->val);
+}
+
+/* init timer register */
+int timer_init(void)
+{
+       struct sunxi_timer_reg *timers =
+               (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
+       struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
+       writel(TIMER_LOAD_VAL, &timer->inter);
+       writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
+              &timer->ctl);
+
+       return 0;
+}
+
+/* timer without interrupts */
+ulong get_timer(ulong base)
+{
+       return get_timer_masked() - base;
+}
+
+ulong get_timer_masked(void)
+{
+       /* current tick value */
+       ulong now = TICKS_TO_HZ(read_timer());
+
+       if (now >= gd->arch.lastinc)    /* normal (non rollover) */
+               gd->arch.tbl += (now - gd->arch.lastinc);
+       else {
+               /* rollover */
+               gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
+                               - gd->arch.lastinc) + now;
+       }
+       gd->arch.lastinc = now;
+
+       return gd->arch.tbl;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+       long tmo = USEC_TO_COUNT(usec);
+       ulong now, last = read_timer();
+
+       while (tmo > 0) {
+               now = read_timer();
+               if (now > last) /* normal (non rollover) */
+                       tmo -= now - last;
+               else            /* rollover */
+                       tmo -= TIMER_LOAD_VAL - last + now;
+               last = now;
+       }
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+       return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+       return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
new file mode 100644 (file)
index 0000000..364e35c
--- /dev/null
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2013
+ * Henrik Nordstrom <henrik@henriknordstrom.net>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(s_init)
+SECTIONS
+{
+       . = 0x00002000;
+
+       . = ALIGN(4);
+       .text :
+       {
+               *(.text.s_init)
+               *(.text*)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+       . = ALIGN(4);
+       .data : {
+               *(.data*)
+       }
+
+       . = ALIGN(4);
+       . = .;
+
+       . = ALIGN(4);
+       .rel.dyn : {
+               __rel_dyn_start = .;
+               *(.rel*)
+               __rel_dyn_end = .;
+       }
+
+       .dynsym : {
+               __dynsym_start = .;
+               *(.dynsym)
+       }
+
+       . = ALIGN(4);
+       .note.gnu.build-id :
+       {
+               *(.note.gnu.build-id)
+       }
+       _end = .;
+
+       . = ALIGN(4096);
+       .mmutable : {
+               *(.mmutable)
+       }
+
+       .bss_start __rel_dyn_start (OVERLAY) : {
+               KEEP(*(.__bss_start));
+               __bss_base = .;
+       }
+
+       .bss __bss_base (OVERLAY) : {
+               *(.bss*)
+               . = ALIGN(4);
+               __bss_limit = .;
+       }
+
+       .bss_end __bss_limit (OVERLAY) : {
+               KEEP(*(.__bss_end));
+       }
+
+       /DISCARD/ : { *(.dynstr*) }
+       /DISCARD/ : { *(.dynamic*) }
+       /DISCARD/ : { *(.plt*) }
+       /DISCARD/ : { *(.interp*) }
+       /DISCARD/ : { *(.gnu*) }
+       /DISCARD/ : { *(.note*) }
+}
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
new file mode 100644 (file)
index 0000000..5008028
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Based on omap-common/u-boot-spl.lds:
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *     Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+               LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+               LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       .text      :
+       {
+               __start = .;
+               arch/arm/cpu/armv7/start.o      (.text)
+               *(.text*)
+       } > .sram
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+       . = ALIGN(4);
+       .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+       . = ALIGN(4);
+       __image_copy_end = .;
+       _end = .;
+
+       .bss :
+       {
+               . = ALIGN(4);
+               __bss_start = .;
+               *(.bss*)
+               . = ALIGN(4);
+               __bss_end = .;
+       } > .sdram
+}
index 7626b5c..816d0c5 100644 (file)
@@ -14,6 +14,9 @@ void lowlevel_init(void)
 {
 }
 
+#define ZYNQ_SILICON_VER_MASK  0xF0000000
+#define ZYNQ_SILICON_VER_SHIFT 28
+
 int arch_cpu_init(void)
 {
        zynq_slcr_unlock();
@@ -42,6 +45,16 @@ int arch_cpu_init(void)
        return 0;
 }
 
+unsigned int zynq_get_silicon_version(void)
+{
+       unsigned int ver;
+
+       ver = (readl(&devcfg_base->mctrl) &
+              ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT;
+
+       return ver;
+}
+
 void reset_cpu(ulong addr)
 {
        zynq_slcr_cpu_reset();
index ba6a6ae..e0ed3bf 100644 (file)
@@ -40,11 +40,8 @@ void zynq_ddrc_init(void)
                 * first stage bootloader. To get ECC to work all memory has
                 * been initialized by writing any value.
                 */
-               memset(0, 0, 1 * 1024 * 1024);
+               memset((void *)0, 0, 1 * 1024 * 1024);
        } else {
                puts("Memory: ECC disabled\n");
        }
-
-       if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)
-               gd->ram_size /= 2;
 }
index d7c1882..934ccc3 100644 (file)
@@ -8,26 +8,75 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/arch/clk.h>
 
 #define SLCR_LOCK_MAGIC                0x767B
 #define SLCR_UNLOCK_MAGIC      0xDF0D
 
+#define SLCR_USB_L1_SEL                        0x04
+
 #define SLCR_IDCODE_MASK       0x1F000
 #define SLCR_IDCODE_SHIFT      12
 
+/*
+ * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
+ *
+ * @peri_name: Name of the peripheral for checking MIO status
+ * @get_pins: Pointer to array of get pin for this peripheral
+ * @num_pins: Number of pins for this peripheral
+ * @mask: Mask value
+ * @check_val: Required check value to get the status of  periph
+ */
+struct zynq_slcr_mio_get_status {
+       const char *peri_name;
+       const int *get_pins;
+       int num_pins;
+       u32 mask;
+       u32 check_val;
+};
+
+static const int usb0_pins[] = {
+       28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
+};
+
+static const int usb1_pins[] = {
+       40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
+};
+
+static const struct zynq_slcr_mio_get_status mio_periphs[] = {
+       {
+               "usb0",
+               usb0_pins,
+               ARRAY_SIZE(usb0_pins),
+               SLCR_USB_L1_SEL,
+               SLCR_USB_L1_SEL,
+       },
+       {
+               "usb1",
+               usb1_pins,
+               ARRAY_SIZE(usb1_pins),
+               SLCR_USB_L1_SEL,
+               SLCR_USB_L1_SEL,
+       },
+};
+
 static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */
 
 void zynq_slcr_lock(void)
 {
-       if (!slcr_lock)
+       if (!slcr_lock) {
                writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock);
+               slcr_lock = 1;
+       }
 }
 
 void zynq_slcr_unlock(void)
 {
-       if (slcr_lock)
+       if (slcr_lock) {
                writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock);
+               slcr_lock = 0;
+       }
 }
 
 /* Reset the entire system */
@@ -82,7 +131,7 @@ void zynq_slcr_devcfg_disable(void)
 {
        zynq_slcr_unlock();
 
-       /* Disable AXI interface */
+       /* Disable AXI interface by asserting FPGA resets */
        writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
 
        /* Set Level Shifters DT618760 */
@@ -98,7 +147,7 @@ void zynq_slcr_devcfg_enable(void)
        /* Set Level Shifters DT618760 */
        writel(0xF, &slcr_base->lvl_shftr_en);
 
-       /* Disable AXI interface */
+       /* Enable AXI interface by de-asserting FPGA resets */
        writel(0x0, &slcr_base->fpga_rst_ctrl);
 
        zynq_slcr_lock();
@@ -115,3 +164,33 @@ u32 zynq_slcr_get_idcode(void)
        return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >>
                                                        SLCR_IDCODE_SHIFT;
 }
+
+/*
+ * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
+ *
+ * @periph: Name of the peripheral
+ *
+ * Returns count to indicate the number of pins configured for the
+ * given @periph.
+ */
+int zynq_slcr_get_mio_pin_status(const char *periph)
+{
+       const struct zynq_slcr_mio_get_status *mio_ptr;
+       int val, i, j;
+       int mio = 0;
+
+       for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
+               if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
+                       mio_ptr = &mio_periphs[i];
+                       for (j = 0; j < mio_ptr->num_pins; j++) {
+                               val = readl(&slcr_base->mio_pin
+                                               [mio_ptr->get_pins[j]]);
+                               if ((val & mio_ptr->mask) == mio_ptr->check_val)
+                                       mio++;
+                       }
+                       break;
+               }
+       }
+
+       return mio;
+}
index fcad762..d73e5cb 100644 (file)
@@ -28,6 +28,13 @@ void board_init_f(ulong dummy)
        board_init_r(NULL, 0);
 }
 
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+       board_init();
+}
+#endif
+
 u32 spl_boot_device(void)
 {
        u32 mode;
@@ -67,3 +74,11 @@ int spl_start_uboot(void)
        return 0;
 }
 #endif
+
+__weak void ps7_init(void)
+{
+       /*
+        * This function is overridden by the one in
+        * board/xilinx/zynq/ps7_init.c, if it exists.
+        */
+}
index 33d3f36..4b11aa4 100644 (file)
@@ -50,10 +50,10 @@ reset:
         */
        adr     x0, vectors
        switch_el x1, 3f, 2f, 1f
-3:     mrs     x0, scr_el3
+3:     msr     vbar_el3, x0
+       mrs     x0, scr_el3
        orr     x0, x0, #0xf                    /* SCR_EL3.NS|IRQ|FIQ|EA */
        msr     scr_el3, x0
-       msr     vbar_el3, x0
        msr     cptr_el3, xzr                   /* Enable FP/SIMD */
        ldr     x0, =COUNTER_FREQUENCY
        msr     cntfrq_el0, x0                  /* Initialize CNTFRQ */
index 7f4debb..cbb5a52 100644 (file)
@@ -20,6 +20,43 @@ static void at91_disable_wdt(void)
        writel(AT91_WDT_MR_WDDIS, &wdt->mr);
 }
 
+static void switch_to_main_crystal_osc(void)
+{
+       struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+       u32 tmp;
+
+       tmp = readl(&pmc->mor);
+       tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff);
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_MOSCEN;
+       tmp |= AT91_PMC_MOR_OSCOUNT(8);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+       while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS))
+               ;
+
+       tmp = readl(&pmc->mor);
+       tmp &= ~AT91_PMC_MOR_OSCBYPASS;
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+
+       tmp = readl(&pmc->mor);
+       tmp |= AT91_PMC_MOR_MOSCSEL;
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+
+       while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS))
+               ;
+
+       tmp = readl(&pmc->mor);
+       tmp &= ~AT91_PMC_MOR_MOSCRCEN;
+       tmp &= ~AT91_PMC_MOR_KEY(0xff);
+       tmp |= AT91_PMC_MOR_KEY(0x37);
+       writel(tmp, &pmc->mor);
+}
+
 void at91_plla_init(u32 pllar)
 {
        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
@@ -76,6 +113,8 @@ u32 spl_boot_mode(void)
 
 void s_init(void)
 {
+       switch_to_main_crystal_osc();
+
        /* disable watchdog */
        at91_disable_wdt();
 
index a3c9c91..7af2a88 100644 (file)
@@ -1,9 +1,9 @@
 /*
   + * Copyright 2012 Freescale Semiconductor, Inc.
   + * Copyright 2011 Linaro Ltd.
   + *
   + * SPDX-License-Identifier:     GPL-2.0+
   + */
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
 
 /dts-v1/;
 
index f20b8bd..2d076f1 100644 (file)
 
 / {
        compatible = "xlnx,zynq-7000";
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <0>;
+                       clocks = <&clkc 3>;
+                       clock-latency = <1000>;
+                       operating-points = <
+                               /* kHz    uV */
+                               666667  1000000
+                               333334  1000000
+                               222223  1000000
+                       >;
+               };
+
+               cpu@1 {
+                       compatible = "arm,cortex-a9";
+                       device_type = "cpu";
+                       reg = <1>;
+                       clocks = <&clkc 3>;
+               };
+       };
+
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts = <0 5 4>, <0 6 4>;
+               interrupt-parent = <&intc>;
+               reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+       };
+
+       amba {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               interrupt-parent = <&intc>;
+               ranges;
+
+               i2c0: zynq-i2c@e0004000 {
+                       compatible = "cdns,i2c-r1p10";
+                       status = "disabled";
+                       clocks = <&clkc 38>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 25 4>;
+                       reg = <0xe0004000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               i2c1: zynq-i2c@e0005000 {
+                       compatible = "cdns,i2c-r1p10";
+                       status = "disabled";
+                       clocks = <&clkc 39>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 48 4>;
+                       reg = <0xe0005000 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               intc: interrupt-controller@f8f01000 {
+                       compatible = "arm,cortex-a9-gic";
+                       #interrupt-cells = <3>;
+                       #address-cells = <1>;
+                       interrupt-controller;
+                       reg = <0xF8F01000 0x1000>,
+                             <0xF8F00100 0x100>;
+               };
+
+               L2: cache-controller {
+                       compatible = "arm,pl310-cache";
+                       reg = <0xF8F02000 0x1000>;
+                       arm,data-latency = <3 2 2>;
+                       arm,tag-latency = <2 2 2>;
+                       cache-unified;
+                       cache-level = <2>;
+               };
+
+               uart0: uart@e0000000 {
+                       compatible = "xlnx,xuartps";
+                       status = "disabled";
+                       clocks = <&clkc 23>, <&clkc 40>;
+                       clock-names = "ref_clk", "aper_clk";
+                       reg = <0xE0000000 0x1000>;
+                       interrupts = <0 27 4>;
+               };
+
+               uart1: uart@e0001000 {
+                       compatible = "xlnx,xuartps";
+                       status = "disabled";
+                       clocks = <&clkc 24>, <&clkc 41>;
+                       clock-names = "ref_clk", "aper_clk";
+                       reg = <0xE0001000 0x1000>;
+                       interrupts = <0 50 4>;
+               };
+
+               gem0: ethernet@e000b000 {
+                       compatible = "cdns,gem";
+                       reg = <0xe000b000 0x4000>;
+                       status = "disabled";
+                       interrupts = <0 22 4>;
+                       clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
+                       clock-names = "pclk", "hclk", "tx_clk";
+               };
+
+               gem1: ethernet@e000c000 {
+                       compatible = "cdns,gem";
+                       reg = <0xe000c000 0x4000>;
+                       status = "disabled";
+                       interrupts = <0 45 4>;
+                       clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
+                       clock-names = "pclk", "hclk", "tx_clk";
+               };
+
+               sdhci0: ps7-sdhci@e0100000 {
+                       compatible = "arasan,sdhci-8.9a";
+                       status = "disabled";
+                       clock-names = "clk_xin", "clk_ahb";
+                       clocks = <&clkc 21>, <&clkc 32>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 24 4>;
+                       reg = <0xe0100000 0x1000>;
+               } ;
+
+               sdhci1: ps7-sdhci@e0101000 {
+                       compatible = "arasan,sdhci-8.9a";
+                       status = "disabled";
+                       clock-names = "clk_xin", "clk_ahb";
+                       clocks = <&clkc 22>, <&clkc 33>;
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 47 4>;
+                       reg = <0xe0101000 0x1000>;
+               } ;
+
+               slcr: slcr@f8000000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "xlnx,zynq-slcr", "syscon";
+                       reg = <0xF8000000 0x1000>;
+                       ranges;
+                       clkc: clkc@100 {
+                               #clock-cells = <1>;
+                               compatible = "xlnx,ps7-clkc";
+                               ps-clk-frequency = <33333333>;
+                               fclk-enable = <0>;
+                               clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                               "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                               "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                               "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                               "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                               "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                               "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                               "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                               "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                               "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                               "dbg_trc", "dbg_apb";
+                               reg = <0x100 0x100>;
+                       };
+               };
+
+               global_timer: timer@f8f00200 {
+                       compatible = "arm,cortex-a9-global-timer";
+                       reg = <0xf8f00200 0x20>;
+                       interrupts = <1 11 0x301>;
+                       interrupt-parent = <&intc>;
+                       clocks = <&clkc 4>;
+               };
+
+               ttc0: ttc0@f8001000 {
+                       interrupt-parent = <&intc>;
+                       interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                       compatible = "cdns,ttc";
+                       clocks = <&clkc 6>;
+                       reg = <0xF8001000 0x1000>;
+               };
+
+               ttc1: ttc1@f8002000 {
+                       interrupt-parent = <&intc>;
+                       interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                       compatible = "cdns,ttc";
+                       clocks = <&clkc 6>;
+                       reg = <0xF8002000 0x1000>;
+               };
+               scutimer: scutimer@f8f00600 {
+                       interrupt-parent = <&intc>;
+                       interrupts = < 1 13 0x301 >;
+                       compatible = "arm,cortex-a9-twd-timer";
+                       reg = < 0xf8f00600 0x20 >;
+                       clocks = <&clkc 4>;
+               } ;
+       };
 };
index 6da71c1..c373a2c 100644 (file)
 / {
        model = "Zynq MicroZED Board";
        compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 667dc28..4fa0b00 100644 (file)
 / {
        model = "Zynq ZC702 Board";
        compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 526fc88..2a80195 100644 (file)
 / {
        model = "Zynq ZC706 Board";
        compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 8b542a1..5e66174 100644 (file)
 / {
        model = "Zynq ZC770 XM010 Board";
        compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 0379a07..127a661 100644 (file)
 / {
        model = "Zynq ZC770 XM012 Board";
        compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index a4f9e05..c61c7e7 100644 (file)
 / {
        model = "Zynq ZC770 XM013 Board";
        compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x40000000>;
+       };
 };
index 91a5deb..70cc8a6 100644 (file)
 / {
        model = "Zynq ZED Board";
        compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+
+       aliases {
+               serial0 = &uart1;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0 0x20000000>;
+       };
 };
index b04dfbb..0e71395 100644 (file)
@@ -19,6 +19,7 @@ obj-y += misc.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx6))
 obj-$(CONFIG_CMD_SATA) += sata.o
+obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
index b59b802..6e46ea8 100644 (file)
@@ -30,6 +30,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
                (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
+#if defined CONFIG_MX6SL
+       /* Check whether LVE bit needs to be set */
+       if (pad_ctrl & PAD_CTL_LVE) {
+               pad_ctrl &= ~PAD_CTL_LVE;
+               pad_ctrl |= PAD_CTL_LVE_BIT;
+       }
+#endif
+
        if (mux_ctrl_ofs)
                __raw_writel(mux_mode, base + mux_ctrl_ofs);
 
diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c
new file mode 100644 (file)
index 0000000..0121cd7
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/imx-common/video.h>
+
+extern struct display_info_t const displays[];
+extern size_t display_count;
+
+int board_video_skip(void)
+{
+       int i;
+       int ret;
+       char const *panel = getenv("panel");
+       if (!panel) {
+               for (i = 0; i < display_count; i++) {
+                       struct display_info_t const *dev = displays+i;
+                       if (dev->detect && dev->detect(dev)) {
+                               panel = dev->mode.name;
+                               printf("auto-detected panel %s\n", panel);
+                               break;
+                       }
+               }
+               if (!panel) {
+                       panel = displays[0].mode.name;
+                       printf("No panel detected: default to %s\n", panel);
+                       i = 0;
+               }
+       } else {
+               for (i = 0; i < display_count; i++) {
+                       if (!strcmp(panel, displays[i].mode.name))
+                               break;
+               }
+       }
+       if (i < display_count) {
+               ret = ipuv3_fb_init(&displays[i].mode, 0,
+                                   displays[i].pixfmt);
+               if (!ret) {
+                       displays[i].enable(displays+i);
+                       printf("Display: %s (%ux%u)\n",
+                              displays[i].mode.name,
+                              displays[i].mode.xres,
+                              displays[i].mode.yres);
+               } else
+                       printf("LCD %s cannot be configured: %d\n",
+                              displays[i].mode.name, ret);
+       } else {
+               printf("unsupported panel %s\n", panel);
+               return -EINVAL;
+       }
+
+       return 0;
+}
+
+#ifdef CONFIG_IMX_HDMI
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/io.h>
+int detect_hdmi(struct display_info_t const *dev)
+{
+       struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+       return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
+}
+#endif
index 7637457..f00fad3 100644 (file)
@@ -42,6 +42,8 @@
 #define MODULE_CLKCTRL_IDLEST_DISABLED         3
 
 /* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_SSC_EN_SHIFT           12
+#define CM_CLKMODE_DPLL_SSC_EN_MASK            (1 << 12)
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT         11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK          (1 << 11)
 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT                10
index 91ff2ad..33a82fc 100644 (file)
@@ -11,6 +11,7 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 #include <linux/mtd/omap_gpmc.h>
+#include <asm/ti-common/sys_proto.h>
 #include <asm/arch/cpu.h>
 
 #define BOARD_REV_ID   0x0
index 4535608..04f6239 100644 (file)
@@ -70,7 +70,10 @@ typedef struct at91_pmc {
 
 #define AT91_PMC_MOR_MOSCEN            0x01
 #define AT91_PMC_MOR_OSCBYPASS         0x02
+#define AT91_PMC_MOR_MOSCRCEN          0x08
 #define AT91_PMC_MOR_OSCOUNT(x)                ((x & 0xff) << 8)
+#define AT91_PMC_MOR_KEY(x)            ((x & 0xff) << 16)
+#define AT91_PMC_MOR_MOSCSEL           (1 << 24)
 
 #define AT91_PMC_PLLXR_DIV(x)          (x & 0xFF)
 #define AT91_PMC_PLLXR_PLLCOUNT(x)     ((x & 0x3F) << 8)
@@ -142,6 +145,7 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_PCKRDY1           0x00000200
 #define AT91_PMC_IXR_PCKRDY2           0x00000400
 #define AT91_PMC_IXR_PCKRDY3           0x00000800
+#define AT91_PMC_IXR_MOSCSELS          0x00010000
 
 #define                AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define                AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
index a471038..d49c184 100644 (file)
@@ -12,6 +12,9 @@
 #ifndef __AT91SAM9X5_H__
 #define __AT91SAM9X5_H__
 
+#define CONFIG_ARM926EJS       /* ARM926EJS Core */
+#define CONFIG_AT91FAMILY      /* it's a member of AT91 family */
+
 /*
  * Peripheral identifiers/interrupts.
  */
index a63f974..d712a0d 100644 (file)
@@ -25,8 +25,6 @@
 # include <asm/arch/at91sam9x5.h>
 #elif defined(CONFIG_AT91CAP9)
 # include <asm/arch/at91cap9.h>
-#elif defined(CONFIG_AT91X40)
-# include <asm/arch/at91x40.h>
 #elif defined(CONFIG_SAMA5D3)
 # include <asm/arch/sama5d3.h>
 #else
index a17f828..3dffa4a 100644 (file)
@@ -161,6 +161,126 @@ struct aips_regs {
        u32 mpr_0_7;
        u32 mpr_8_15;
 };
+/* LCD controller registers */
+struct lcdc_regs {
+       u32 lssar;      /* Screen Start Address */
+       u32 lsr;        /* Size */
+       u32 lvpwr;      /* Virtual Page Width */
+       u32 lcpr;       /* Cursor Position */
+       u32 lcwhb;      /* Cursor Width Height and Blink */
+       u32 lccmr;      /* Color Cursor Mapping */
+       u32 lpcr;       /* Panel Configuration */
+       u32 lhcr;       /* Horizontal Configuration */
+       u32 lvcr;       /* Vertical Configuration */
+       u32 lpor;       /* Panning Offset */
+       u32 lscr;       /* Sharp Configuration */
+       u32 lpccr;      /* PWM Contrast Control */
+       u32 ldcr;       /* DMA Control */
+       u32 lrmcr;      /* Refresh Mode Control */
+       u32 licr;       /* Interrupt Configuration */
+       u32 lier;       /* Interrupt Enable */
+       u32 lisr;       /* Interrupt Status */
+       u32 res0[3];
+       u32 lgwsar;     /* Graphic Window Start Address */
+       u32 lgwsr;      /* Graphic Window Size */
+       u32 lgwvpwr;    /* Graphic Window Virtual Page Width Regist */
+       u32 lgwpor;     /* Graphic Window Panning Offset */
+       u32 lgwpr;      /* Graphic Window Position */
+       u32 lgwcr;      /* Graphic Window Control */
+       u32 lgwdcr;     /* Graphic Window DMA Control */
+       u32 res1[5];
+       u32 lauscr;     /* AUS Mode Control */
+       u32 lausccr;    /* AUS mode Cursor Control */
+       u32 res2[31 + 64*7];
+       u32 bglut;      /* Background Lookup Table */
+       u32 gwlut;      /* Graphic Window Lookup Table */
+};
+
+/* Wireless External Interface Module Registers */
+struct weim_regs {
+       u32 cscr0u;     /* Chip Select 0 Upper Register */
+       u32 cscr0l;     /* Chip Select 0 Lower Register */
+       u32 cscr0a;     /* Chip Select 0 Addition Register */
+       u32 pad0;
+       u32 cscr1u;     /* Chip Select 1 Upper Register */
+       u32 cscr1l;     /* Chip Select 1 Lower Register */
+       u32 cscr1a;     /* Chip Select 1 Addition Register */
+       u32 pad1;
+       u32 cscr2u;     /* Chip Select 2 Upper Register */
+       u32 cscr2l;     /* Chip Select 2 Lower Register */
+       u32 cscr2a;     /* Chip Select 2 Addition Register */
+       u32 pad2;
+       u32 cscr3u;     /* Chip Select 3 Upper Register */
+       u32 cscr3l;     /* Chip Select 3 Lower Register */
+       u32 cscr3a;     /* Chip Select 3 Addition Register */
+       u32 pad3;
+       u32 cscr4u;     /* Chip Select 4 Upper Register */
+       u32 cscr4l;     /* Chip Select 4 Lower Register */
+       u32 cscr4a;     /* Chip Select 4 Addition Register */
+       u32 pad4;
+       u32 cscr5u;     /* Chip Select 5 Upper Register */
+       u32 cscr5l;     /* Chip Select 5 Lower Register */
+       u32 cscr5a;     /* Chip Select 5 Addition Register */
+       u32 pad5;
+       u32 wcr;        /* WEIM Configuration Register */
+};
+
+/* Multi-Master Memory Interface */
+struct m3if_regs {
+       u32 ctl;        /* Control Register */
+       u32 wcfg0;      /* Watermark Configuration Register 0 */
+       u32 wcfg1;      /* Watermark Configuration Register1 */
+       u32 wcfg2;      /* Watermark Configuration Register2 */
+       u32 wcfg3;      /* Watermark Configuration Register 3 */
+       u32 wcfg4;      /* Watermark Configuration Register 4 */
+       u32 wcfg5;      /* Watermark Configuration Register 5 */
+       u32 wcfg6;      /* Watermark Configuration Register 6 */
+       u32 wcfg7;      /* Watermark Configuration Register 7 */
+       u32 wcsr;       /* Watermark Control and Status Register */
+       u32 scfg0;      /* Snooping Configuration Register 0 */
+       u32 scfg1;      /* Snooping Configuration Register 1 */
+       u32 scfg2;      /* Snooping Configuration Register 2 */
+       u32 ssr0;       /* Snooping Status Register 0 */
+       u32 ssr1;       /* Snooping Status Register 1 */
+       u32 res0;
+       u32 mlwe0;      /* Master Lock WEIM CS0 Register */
+       u32 mlwe1;      /* Master Lock WEIM CS1 Register */
+       u32 mlwe2;      /* Master Lock WEIM CS2 Register */
+       u32 mlwe3;      /* Master Lock WEIM CS3 Register */
+       u32 mlwe4;      /* Master Lock WEIM CS4 Register */
+       u32 mlwe5;      /* Master Lock WEIM CS5 Register */
+};
+
+/* Pulse width modulation */
+struct pwm_regs {
+       u32 cr; /* Control Register */
+       u32 sr; /* Status Register */
+       u32 ir; /* Interrupt Register */
+       u32 sar;        /* Sample Register */
+       u32 pr; /* Period Register */
+       u32 cnr;        /* Counter Register */
+};
+
+/* Enhanced Periodic Interrupt Timer */
+struct epit_regs {
+       u32 cr; /* Control register */
+       u32 sr; /* Status register */
+       u32 lr; /* Load register */
+       u32 cmpr;       /* Compare register */
+       u32 cnr;        /* Counter register */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+       u32 rxdata;
+       u32 txdata;
+       u32 ctrl;
+       u32 intr;
+       u32 dma;
+       u32 stat;
+       u32 period;
+       u32 test;
+};
 
 #endif
 
@@ -289,6 +409,8 @@ struct aips_regs {
 #define CCM_PERCLK_MASK                0x3f
 #define CCM_RCSR_NF_16BIT_SEL  (1 << 14)
 #define CCM_RCSR_NF_PS(v)      ((v >> 26) & 3)
+#define CCM_CRDR_BT_UART_SRC_SHIFT     29
+#define CCM_CRDR_BT_UART_SRC_MASK      7
 
 /* ESDRAM Controller register bitfields */
 #define ESDCTL_PRCT(x)         (((x) & 0x3f) << 0)
@@ -345,12 +467,65 @@ struct aips_regs {
 #define WSR_UNLOCK1            0x5555
 #define WSR_UNLOCK2            0xAAAA
 
+/* MAX bits */
+#define MAX_MGPCR_AULB(x)      (((x) & 0x7) << 0)
+
+/* M3IF bits */
+#define M3IF_CTL_MRRP(x)       (((x) & 0xff) << 0)
+
+/* WEIM bits */
+/* 13 fields of the upper CS control register */
+#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
+               cnc, wsc, ew, wws, edc) \
+               ((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
+               (psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
+               (cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
+/* 12 fields of the lower CS control register */
+#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
+               csa, ebc, dsz, csn, psr, cre, wrap, csen) \
+               ((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
+               (csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
+               (psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
+/* 14 fields of the additional CS control register */
+#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
+               wwu, age, cnc2, fce) \
+               ((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
+               (mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
+               (dww) << 6 | (dct) << 4 | (wwu) << 3 |\
+               (age) << 2 | (cnc2) << 1 | (fce) << 0)
+
 /* Names used in GPIO driver */
 #define GPIO1_BASE_ADDR                IMX_GPIO1_BASE
 #define GPIO2_BASE_ADDR                IMX_GPIO2_BASE
 #define GPIO3_BASE_ADDR                IMX_GPIO3_BASE
 #define GPIO4_BASE_ADDR                IMX_GPIO4_BASE
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN                (1 << 0)
+#define MXC_CSPICTRL_MODE      (1 << 1)
+#define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_SMC       (1 << 3)
+#define MXC_CSPICTRL_POL       (1 << 4)
+#define MXC_CSPICTRL_PHA       (1 << 5)
+#define MXC_CSPICTRL_SSCTL     (1 << 6)
+#define MXC_CSPICTRL_SSPOL     (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)       (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC                (1 << 7)
+#define MXC_CSPICTRL_RXOVF     (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+       IMX_CSPI1_BASE, \
+       IMX_CSPI2_BASE, \
+       IMX_CSPI3_BASE
+
 #define CHIP_REV_1_0           0x10
 #define CHIP_REV_1_1           0x11
 #define CHIP_REV_1_2           0x12
index 5f9c90a..045ccc4 100644 (file)
 #include <asm/imx-common/iomux-v3.h>
 
 enum {
+       MX6_PAD_ECSPI1_MISO__ECSPI_MISO                         = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
+       MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI                         = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
+       MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK                         = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
+       MX6_PAD_ECSPI1_SS0__GPIO4_IO11                          = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
        MX6_PAD_SD2_CLK__USDHC2_CLK                             = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
        MX6_PAD_SD2_CMD__USDHC2_CMD                             = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
        MX6_PAD_SD2_DAT0__USDHC2_DAT0                           = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
index 1804191..bdb1435 100644 (file)
@@ -344,6 +344,7 @@ enum {
  * MAP  - Map this CS to which address(GPMC address space)- Absolute address
  *   >>24 before being used.
  */
+#define GPMC_SIZE_256M 0x0
 #define GPMC_SIZE_128M 0x8
 #define GPMC_SIZE_64M  0xC
 #define GPMC_SIZE_32M  0xE
index c21fb54..f7595ae 100644 (file)
@@ -12,6 +12,8 @@
 #include <asm/types.h>
 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
 
+#include <asm/arch/hardware.h>
+
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct gptimer {
@@ -57,9 +59,6 @@ struct watchdog {
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
-/* GPMC BASE */
-#define GPMC_BASE              (OMAP44XX_GPMC_BASE)
-
 /* I2C base */
 #define I2C_BASE1              (OMAP44XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2              (OMAP44XX_L4_PER_BASE + 0x72000)
diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h
new file mode 100644 (file)
index 0000000..f7011b4
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __OMAP_HARDWARE_H
+#define __OMAP_HARDWARE_H
+
+#include <asm/arch/omap.h>
+
+/*
+ * Common hardware definitions
+ */
+
+/* BCH Error Location Module */
+#define ELM_BASE                       0x48078000
+
+/* GPMC Base address */
+#define GPMC_BASE                      0x50000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h
new file mode 100644 (file)
index 0000000..d2e708b
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *             Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *             Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
+ */
+#define GPMC_SIZE_256M         0x0
+#define GPMC_SIZE_128M         0x8
+#define GPMC_SIZE_64M          0xC
+#define GPMC_SIZE_32M          0xE
+#define GPMC_SIZE_16M          0xF
+
+#define M_NAND_GPMC_CONFIG1    0x00000800
+#define M_NAND_GPMC_CONFIG2    0x001e1e00
+#define M_NAND_GPMC_CONFIG3    0x001e1e00
+#define M_NAND_GPMC_CONFIG4    0x16051807
+#define M_NAND_GPMC_CONFIG5    0x00151e1e
+#define M_NAND_GPMC_CONFIG6    0x16000f80
+#define M_NAND_GPMC_CONFIG7    0x00000008
+
+#define STNOR_GPMC_CONFIG1     0x00001200
+#define STNOR_GPMC_CONFIG2     0x00101000
+#define STNOR_GPMC_CONFIG3     0x00030301
+#define STNOR_GPMC_CONFIG4     0x10041004
+#define STNOR_GPMC_CONFIG5     0x000C1010
+#define STNOR_GPMC_CONFIG6     0x08070280
+#define STNOR_GPMC_CONFIG7     0x00000F48
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS            8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG           7
+
+#endif /* endif _MEM_H_ */
index f66da0d..d43dc26 100644 (file)
@@ -60,9 +60,6 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE              (OMAP44XX_L4_WKUP_BASE + 0x14000)
 
-/* GPMC */
-#define OMAP44XX_GPMC_BASE     0x50000000
-
 /*
  * Hardware Register Details
  */
index 80172f3..83d858f 100644 (file)
@@ -14,6 +14,7 @@
 #include <asm/omap_common.h>
 #include <linux/mtd/omap_gpmc.h>
 #include <asm/arch/mux_omap4.h>
+#include <asm/ti-common/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -53,54 +54,4 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
 void setup_warmreset_time(void);
-
-static inline u32 running_from_sdram(void)
-{
-       u32 pc;
-       asm volatile ("mov %0, pc" : "=r" (pc));
-       return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
-           (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
-}
-
-static inline u8 uboot_loaded_by_spl(void)
-{
-       /*
-        * u-boot can be running from sdram either because of configuration
-        * Header or by SPL. If because of CH, then the romcode sets the
-        * CHSETTINGS executed bit to true in the boot parameter structure that
-        * it passes to the bootloader.This parameter is stored in the ch_flags
-        * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
-        * mandatory section if CH is present.
-        */
-       if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
-               return 0;
-       else
-               return running_from_sdram();
-}
-/*
- * The basic hardware init of OMAP(s_init()) can happen in 4
- * different contexts:
- *  1. SPL running from SRAM
- *  2. U-Boot running from FLASH
- *  3. Non-XIP U-Boot loaded to SDRAM by SPL
- *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
- *     Configuration Header feature
- *
- * This function finds this context.
- * Defining as inline may help in compiling out unused functions in SPL
- */
-static inline u32 omap_hw_init_context(void)
-{
-#ifdef CONFIG_SPL_BUILD
-       return OMAP_INIT_CONTEXT_SPL;
-#else
-       if (uboot_loaded_by_spl())
-               return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
-       else if (running_from_sdram())
-               return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
-       else
-               return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
-#endif
-}
-
 #endif
index 2dfe4ef..30d9de2 100644 (file)
 
 #define V_SCLK V_OSCK
 
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK      (1 << 28)
+
 /* AUXCLKx reg fields */
 #define AUXCLK_ENABLE_MASK             (1 << 8)
 #define AUXCLK_SRCSELECT_SHIFT         1
index 5f1d745..6109b92 100644 (file)
@@ -14,6 +14,8 @@
 #include <asm/types.h>
 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
 
+#include <asm/arch/hardware.h>
+
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct gptimer {
@@ -63,9 +65,6 @@ struct watchdog {
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
-/* GPMC BASE */
-#define GPMC_BASE              (OMAP54XX_GPMC_BASE)
-
 /* I2C base */
 #define I2C_BASE1              (OMAP54XX_L4_PER_BASE + 0x70000)
 #define I2C_BASE2              (OMAP54XX_L4_PER_BASE + 0x72000)
diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h
new file mode 100644 (file)
index 0000000..f7011b4
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * hardware.h
+ *
+ * hardware specific header
+ *
+ * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __OMAP_HARDWARE_H
+#define __OMAP_HARDWARE_H
+
+#include <asm/arch/omap.h>
+
+/*
+ * Common hardware definitions
+ */
+
+/* BCH Error Location Module */
+#define ELM_BASE                       0x48078000
+
+/* GPMC Base address */
+#define GPMC_BASE                      0x50000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h
new file mode 100644 (file)
index 0000000..d2e708b
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author
+ *             Mansoor Ahamed <mansoor.ahamed@ti.com>
+ *
+ * Initial Code from:
+ *             Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _MEM_H_
+#define _MEM_H_
+
+/*
+ * GPMC settings -
+ * Definitions is as per the following format
+ * #define <PART>_GPMC_CONFIG<x> <value>
+ * Where:
+ * PART is the part name e.g. STNOR - Intel Strata Flash
+ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
+ * Value is corresponding value
+ *
+ * For every valid PRCM configuration there should be only one definition of
+ * the same. if values are independent of the board, this definition will be
+ * present in this file if values are dependent on the board, then this should
+ * go into corresponding mem-boardName.h file
+ *
+ * Currently valid part Names are (PART):
+ * M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
+ */
+#define GPMC_SIZE_256M         0x0
+#define GPMC_SIZE_128M         0x8
+#define GPMC_SIZE_64M          0xC
+#define GPMC_SIZE_32M          0xE
+#define GPMC_SIZE_16M          0xF
+
+#define M_NAND_GPMC_CONFIG1    0x00000800
+#define M_NAND_GPMC_CONFIG2    0x001e1e00
+#define M_NAND_GPMC_CONFIG3    0x001e1e00
+#define M_NAND_GPMC_CONFIG4    0x16051807
+#define M_NAND_GPMC_CONFIG5    0x00151e1e
+#define M_NAND_GPMC_CONFIG6    0x16000f80
+#define M_NAND_GPMC_CONFIG7    0x00000008
+
+#define STNOR_GPMC_CONFIG1     0x00001200
+#define STNOR_GPMC_CONFIG2     0x00101000
+#define STNOR_GPMC_CONFIG3     0x00030301
+#define STNOR_GPMC_CONFIG4     0x10041004
+#define STNOR_GPMC_CONFIG5     0x000C1010
+#define STNOR_GPMC_CONFIG6     0x08070280
+#define STNOR_GPMC_CONFIG7     0x00000F48
+
+/* max number of GPMC Chip Selects */
+#define GPMC_MAX_CS            8
+/* max number of GPMC regs */
+#define GPMC_MAX_REG           7
+
+#endif /* endif _MEM_H_ */
index 19fdece..b9600cf 100644 (file)
 #define OMAP54XX_L4_WKUP_BASE  0x4Ae00000
 #define OMAP54XX_L4_PER_BASE   0x48000000
 
-#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
-#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
-#define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
-#define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
-
 /* CONTROL ID CODE */
 #define CONTROL_CORE_ID_CODE   0x4A002204
 #define CONTROL_WKUP_ID_CODE   0x4AE0C204
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0           0x0B99002F
 #define DRA752_CONTROL_ID_CODE_ES1_1           0x1B99002F
+#define DRA722_CONTROL_ID_CODE_ES1_0           0x0B9BC02F
 
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE             (OMAP54XX_L4_PER_BASE + 0x6c000)
 #define UART3_BASE             (OMAP54XX_L4_PER_BASE + 0x20000)
+#define UART4_BASE             (OMAP54XX_L4_PER_BASE + 0x6e000)
 
 /* General Purpose Timers */
 #define GPT1_BASE              (OMAP54XX_L4_WKUP_BASE + 0x18000)
@@ -59,9 +56,6 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE              (OMAP54XX_L4_WKUP_BASE + 0x14000)
 
-/* GPMC */
-#define OMAP54XX_GPMC_BASE     0x50000000
-
 /* QSPI */
 #define QSPI_BASE              0x4B300000
 
index bf12c73..1038303 100644 (file)
@@ -14,6 +14,7 @@
 #include <asm/omap_common.h>
 #include <linux/mtd/omap_gpmc.h>
 #include <asm/arch/clock.h>
+#include <asm/ti-common/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -56,55 +57,6 @@ void get_ioregs(const struct ctrl_ioregs **regs);
 void srcomp_enable(void);
 void setup_warmreset_time(void);
 
-static inline u32 running_from_sdram(void)
-{
-       u32 pc;
-       asm volatile ("mov %0, pc" : "=r" (pc));
-       return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) &&
-           (pc < OMAP54XX_DRAM_ADDR_SPACE_END));
-}
-
-static inline u8 uboot_loaded_by_spl(void)
-{
-       /*
-        * u-boot can be running from sdram either because of configuration
-        * Header or by SPL. If because of CH, then the romcode sets the
-        * CHSETTINGS executed bit to true in the boot parameter structure that
-        * it passes to the bootloader.This parameter is stored in the ch_flags
-        * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a
-        * mandatory section if CH is present.
-        */
-       if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS))
-               return 0;
-       else
-               return running_from_sdram();
-}
-/*
- * The basic hardware init of OMAP(s_init()) can happen in 4
- * different contexts:
- *  1. SPL running from SRAM
- *  2. U-Boot running from FLASH
- *  3. Non-XIP U-Boot loaded to SDRAM by SPL
- *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
- *     Configuration Header feature
- *
- * This function finds this context.
- * Defining as inline may help in compiling out unused functions in SPL
- */
-static inline u32 omap_hw_init_context(void)
-{
-#ifdef CONFIG_SPL_BUILD
-       return OMAP_INIT_CONTEXT_SPL;
-#else
-       if (uboot_loaded_by_spl())
-               return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL;
-       else if (running_from_sdram())
-               return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH;
-       else
-               return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR;
-#endif
-}
-
 static inline u32 div_round_up(u32 num, u32 den)
 {
        return (num + den - 1)/den;
index 444e361..74b5f1d 100644 (file)
@@ -1,5 +1,5 @@
-#ifndef __ASM_R8A7790_H__
-#define __ASM_R8A7790_H__
+#ifndef __ASM_R8A7790_GPIO_H__
+#define __ASM_R8A7790_GPIO_H__
 
 /* Pin Function Controller:
  * GPIO_FN_xx - GPIO used to select pin function
@@ -384,4 +384,4 @@ enum {
        GPIO_FN_TCLK1_B,
 };
 
-#endif /* __ASM_R8A7790_H__ */
+#endif /* __ASM_R8A7790_GPIO_H__ */
index d9ea71f..6ef665d 100644 (file)
 /*
  * arch/arm/include/asm/arch-rmobile/r8a7790.h
  *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
- */
+*/
 
 #ifndef __ASM_ARCH_R8A7790_H
 #define __ASM_ARCH_R8A7790_H
 
-/*
- * R8A7790 I/O Addresses
- */
-#define        RWDT_BASE               0xE6020000
-#define        SWDT_BASE               0xE6030000
-#define        LBSC_BASE               0xFEC00200
-#define DBSC3_0_BASE           0xE6790000
-#define DBSC3_1_BASE           0xE67A0000
-#define TMU_BASE               0xE61E0000
-#define        GPIO5_BASE              0xE6055000
-#define SH_QSPI_BASE   0xE6B10000
-
-#define S3C_BASE               0xE6784000
-#define S3C_INT_BASE           0xE6784A00
-#define S3C_MEDIA_BASE         0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE    0xE6784BDC
-#define S3C_QOS_CCI0_BASE      0xE6784C00
-#define S3C_QOS_CCI1_BASE      0xE6784C24
-#define S3C_QOS_MXI_BASE       0xE6784C48
-#define S3C_QOS_AXI_BASE       0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE    0xE6791000
-#define DBSC3_0_QOS_R1_BASE    0xE6791100
-#define DBSC3_0_QOS_R2_BASE    0xE6791200
-#define DBSC3_0_QOS_R3_BASE    0xE6791300
-#define DBSC3_0_QOS_R4_BASE    0xE6791400
-#define DBSC3_0_QOS_R5_BASE    0xE6791500
-#define DBSC3_0_QOS_R6_BASE    0xE6791600
-#define DBSC3_0_QOS_R7_BASE    0xE6791700
-#define DBSC3_0_QOS_R8_BASE    0xE6791800
-#define DBSC3_0_QOS_R9_BASE    0xE6791900
-#define DBSC3_0_QOS_R10_BASE   0xE6791A00
-#define DBSC3_0_QOS_R11_BASE   0xE6791B00
-#define DBSC3_0_QOS_R12_BASE   0xE6791C00
-#define DBSC3_0_QOS_R13_BASE   0xE6791D00
-#define DBSC3_0_QOS_R14_BASE   0xE6791E00
-#define DBSC3_0_QOS_R15_BASE   0xE6791F00
-#define DBSC3_0_QOS_W0_BASE    0xE6792000
-#define DBSC3_0_QOS_W1_BASE    0xE6792100
-#define DBSC3_0_QOS_W2_BASE    0xE6792200
-#define DBSC3_0_QOS_W3_BASE    0xE6792300
-#define DBSC3_0_QOS_W4_BASE    0xE6792400
-#define DBSC3_0_QOS_W5_BASE    0xE6792500
-#define DBSC3_0_QOS_W6_BASE    0xE6792600
-#define DBSC3_0_QOS_W7_BASE    0xE6792700
-#define DBSC3_0_QOS_W8_BASE    0xE6792800
-#define DBSC3_0_QOS_W9_BASE    0xE6792900
-#define DBSC3_0_QOS_W10_BASE   0xE6792A00
-#define DBSC3_0_QOS_W11_BASE   0xE6792B00
-#define DBSC3_0_QOS_W12_BASE   0xE6792C00
-#define DBSC3_0_QOS_W13_BASE   0xE6792D00
-#define DBSC3_0_QOS_W14_BASE   0xE6792E00
-#define DBSC3_0_QOS_W15_BASE   0xE6792F00
-
-#define DBSC3_0_DBADJ2         0xE67900C8
-
-#define CCI_400_MAXOT_1                0xF0091110
-#define CCI_400_MAXOT_2                0xF0092110
-#define CCI_400_QOSCNTL_1      0xF009110C
-#define CCI_400_QOSCNTL_2      0xF009210C
-
-#define        MXI_BASE                0xFE960000
-#define        MXI_QOS_BASE            0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE        0xFF800300
-#define SYS_AXI_AVB_BASE       0xFF800340
-#define SYS_AXI_G2D_BASE       0xFF800540
-#define SYS_AXI_IMP0_BASE      0xFF800580
-#define SYS_AXI_IMP1_BASE      0xFF8005C0
-#define SYS_AXI_IMUX0_BASE     0xFF800600
-#define SYS_AXI_IMUX1_BASE     0xFF800640
-#define SYS_AXI_IMUX2_BASE     0xFF800680
-#define SYS_AXI_LBS_BASE       0xFF8006C0
-#define SYS_AXI_MMUDS_BASE     0xFF800700
-#define SYS_AXI_MMUM_BASE      0xFF800740
-#define SYS_AXI_MMUR_BASE      0xFF800780
-#define SYS_AXI_MMUS0_BASE     0xFF8007C0
-#define SYS_AXI_MMUS1_BASE     0xFF800800
-#define SYS_AXI_MTSB0_BASE     0xFF800880
-#define SYS_AXI_MTSB1_BASE     0xFF8008C0
-#define SYS_AXI_PCI_BASE       0xFF800900
-#define SYS_AXI_RTX_BASE       0xFF800940
-#define SYS_AXI_SDS0_BASE      0xFF800A80
-#define SYS_AXI_SDS1_BASE      0xFF800AC0
-#define SYS_AXI_USB20_BASE     0xFF800C00
-#define SYS_AXI_USB21_BASE     0xFF800C40
-#define SYS_AXI_USB22_BASE     0xFF800C80
-#define SYS_AXI_USB30_BASE     0xFF800CC0
-
-#define RT_AXI_SHX_BASE                0xFF810100
-#define RT_AXI_RDS_BASE                0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE 0xFF810200
-#define RT_AXI_STPRO_BASE      0xFF810240
-
-#define MP_AXI_ADSP_BASE       0xFF820100
-#define MP_AXI_ASDS0_BASE      0xFF8201C0
-#define MP_AXI_ASDS1_BASE      0xFF820200
-#define MP_AXI_MLP_BASE                0xFF820240
-#define MP_AXI_MMUMP_BASE      0xFF820280
-#define MP_AXI_SPU_BASE                0xFF8202C0
-#define MP_AXI_SPUC_BASE       0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE    0xFF860100
-#define SYS_AXI256_SYX_BASE    0xFF860140
-#define SYS_AXI256_MPX_BASE    0xFF860180
-#define SYS_AXI256_MXI_BASE    0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE     0xFF880100
-#define CCI_AXI_SYX2_BASE      0xFF880140
-#define CCI_AXI_MMUR_BASE      0xFF880180
-#define CCI_AXI_MMUDS_BASE     0xFF8801C0
-#define CCI_AXI_MMUM_BASE      0xFF880200
-#define CCI_AXI_MXI_BASE       0xFF880240
-#define CCI_AXI_MMUS1_BASE     0xFF880280
-#define CCI_AXI_MMUMP_BASE     0xFF8802C0
-
-#define MEDIA_AXI_JPR_BASE     0xFE964100
-#define MEDIA_AXI_JPW_BASE     0xFE966100
-#define MEDIA_AXI_GCU0R_BASE   0xFE964140
-#define MEDIA_AXI_GCU0W_BASE   0xFE966140
-#define MEDIA_AXI_GCU1R_BASE   0xFE964180
-#define MEDIA_AXI_GCU1W_BASE   0xFE966180
-#define MEDIA_AXI_TDMR_BASE    0xFE964500
-#define MEDIA_AXI_TDMW_BASE    0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE  0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE  0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE  0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE  0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE        0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE        0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE        0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE        0xFE966600
-#define MEDIA_AXI_VIN0W_BASE   0xFE966900
-#define MEDIA_AXI_VSP0R_BASE   0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE   0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE   0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE   0xFE966D40
-#define MEDIA_AXI_IMSR_BASE    0xFE964D80
-#define MEDIA_AXI_IMSW_BASE    0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE   0xFE965100
-#define MEDIA_AXI_VSP1W_BASE   0xFE967100
-#define MEDIA_AXI_FDP1R_BASE   0xFE965140
-#define MEDIA_AXI_FDP1W_BASE   0xFE967140
-#define MEDIA_AXI_IMRR_BASE    0xFE965180
-#define MEDIA_AXI_IMRW_BASE    0xFE967180
-#define MEDIA_AXI_FDP2R_BASE   0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE   0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE  0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE  0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE  0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE  0xFE967540
-#define MEDIA_AXI_DU0R_BASE    0xFE965580
-#define MEDIA_AXI_DU0W_BASE    0xFE967580
-#define MEDIA_AXI_DU1R_BASE    0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE    0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE  0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE  0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE  0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE  0xFE967940
-#define MEDIA_AXI_VPC0R_BASE   0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE  0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE  0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE  0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE  0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE   0xFE965D80
-
-#define SYS_AXI_AVBDMSCR       0xFF802000
-#define SYS_AXI_SYX2DMSCR      0xFF802004
-#define SYS_AXI_CC50DMSCR      0xFF802008
-#define SYS_AXI_CC51DMSCR      0xFF80200C
-#define SYS_AXI_CCIDMSCR       0xFF802010
-#define SYS_AXI_CSDMSCR                0xFF802014
-#define SYS_AXI_DDMDMSCR       0xFF802018
-#define SYS_AXI_ETHDMSCR       0xFF80201C
-#define SYS_AXI_G2DDMSCR       0xFF802020
-#define SYS_AXI_IMP0DMSCR      0xFF802024
-#define SYS_AXI_IMP1DMSCR      0xFF802028
-#define SYS_AXI_LBSDMSCR       0xFF80202C
-#define SYS_AXI_MMUDSDMSCR     0xFF802030
-#define SYS_AXI_MMUMXDMSCR     0xFF802034
-#define SYS_AXI_MMURDDMSCR     0xFF802038
-#define SYS_AXI_MMUS0DMSCR     0xFF80203C
-#define SYS_AXI_MMUS1DMSCR     0xFF802040
-#define SYS_AXI_MPXDMSCR       0xFF802044
-#define SYS_AXI_MTSB0DMSCR     0xFF802048
-#define SYS_AXI_MTSB1DMSCR     0xFF80204C
-#define SYS_AXI_PCIDMSCR       0xFF802050
-#define SYS_AXI_RTXDMSCR       0xFF802054
-#define SYS_AXI_SAT0DMSCR      0xFF802058
-#define SYS_AXI_SAT1DMSCR      0xFF80205C
-#define SYS_AXI_SDM0DMSCR      0xFF802060
-#define SYS_AXI_SDM1DMSCR      0xFF802064
-#define SYS_AXI_SDS0DMSCR      0xFF802068
-#define SYS_AXI_SDS1DMSCR      0xFF80206C
-#define SYS_AXI_ETRABDMSCR     0xFF802070
-#define SYS_AXI_ETRKFDMSCR     0xFF802074
-#define SYS_AXI_UDM0DMSCR      0xFF802078
-#define SYS_AXI_UDM1DMSCR      0xFF80207C
-#define SYS_AXI_USB20DMSCR     0xFF802080
-#define SYS_AXI_USB21DMSCR     0xFF802084
-#define SYS_AXI_USB22DMSCR     0xFF802088
-#define SYS_AXI_USB30DMSCR     0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR       0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR       0xFF802104
-#define SYS_AXI_AVBSLVDMSCR    0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR   0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR    0xFF802110
-#define SYS_AXI_GICSLVDMSCR    0xFF802114
-#define SYS_AXI_IMPSLVDMSCR    0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR   0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR   0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR   0xFF802124
-#define SYS_AXI_LBSSLVDMSCR    0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR   0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR   0xFF802130
-#define SYS_AXI_MPXSLVDMSCR    0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR  0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR  0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR    0xFF802140
-#define SYS_AXI_PCISLVDMSCR    0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR  0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR  0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR    0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR   0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR   0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR  0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR  0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR  0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR  0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR    0xFF802180
-#define SYS_AXI_STBSLVDMSCR    0xFF802188
-#define SYS_AXI_STMSLVDMSCR    0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR  0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR  0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR  0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR  0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR  0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR  0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR  0xFF8021AC
-
-#define RT_AXI_CBMDMSCR                0xFF812000
-#define RT_AXI_DBDMSCR         0xFF812004
-#define RT_AXI_RDMDMSCR                0xFF812008
-#define RT_AXI_RDSDMSCR                0xFF81200C
-#define RT_AXI_STRDMSCR                0xFF812010
-#define RT_AXI_SY2RTDMSCR      0xFF812014
-#define RT_AXI_CBSSLVDMSCR     0xFF812100
-#define RT_AXI_DBSSLVDMSCR     0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR   0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR   0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR   0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR   0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR        0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR        0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR       0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR   0xFF812128
-
-#define MP_AXI_ADSPDMSCR       0xFF822000
-#define MP_AXI_ASDM0DMSCR      0xFF822004
-#define MP_AXI_ASDM1DMSCR      0xFF822008
-#define MP_AXI_ASDS0DMSCR      0xFF82200C
-#define MP_AXI_ASDS1DMSCR      0xFF822010
-#define MP_AXI_MLPDMSCR                0xFF822014
-#define MP_AXI_MMUMPDMSCR      0xFF822018
-#define MP_AXI_SPUDMSCR                0xFF82201C
-#define MP_AXI_SPUCDMSCR       0xFF822020
-#define MP_AXI_SY2MPDMSCR      0xFF822024
-#define MP_AXI_ADSPSLVDMSCR    0xFF822100
-#define MP_AXI_MLMSLVDMSCR     0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR   0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR   0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR   0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR   0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR   0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR  0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR   0xFF822124
-#define MP_AXI_SPUSLVDMSCR     0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR  0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR     0xFF842000
-#define ADM_AXI_ASDM1DMSCR     0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR  0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR  0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR  0xFF84210C
-
-#define DM_AXI_RDMDMSCR                0xFF852000
-#define DM_AXI_SDM0DMSCR       0xFF852004
-#define DM_AXI_SDM1DMSCR       0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR   0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR   0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR   0xFF852108
-#define DM_AXI_RAP4SLVDMSCR    0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR    0xFF852110
-#define DM_AXI_SAP4SLVDMSCR    0xFF852114
-#define DM_AXI_SAP5SLVDMSCR    0xFF852118
-#define DM_AXI_SAP6SLVDMSCR    0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR   0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR   0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR   0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR   0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR   0xFF852130
-
-#define SYS_AXI256_SYXDMSCR    0xFF862000
-#define SYS_AXI256_MPXDMSCR    0xFF862004
-#define SYS_AXI256_MXIDMSCR    0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR   0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR   0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
-
-#define MXT_SYXDMSCR           0xFF872000
-#define MXT_CMM0SLVDMSCR       0xFF872100
-#define MXT_CMM1SLVDMSCR       0xFF872104
-#define MXT_CMM2SLVDMSCR       0xFF872108
-#define MXT_FDPSLVDMSCR                0xFF87210C
-#define MXT_IMRSLVDMSCR                0xFF872110
-#define MXT_VINSLVDMSCR                0xFF872114
-#define MXT_VPC0SLVDMSCR       0xFF872118
-#define MXT_VPC1SLVDMSCR       0xFF87211C
-#define MXT_VSP0SLVDMSCR       0xFF872120
-#define MXT_VSP1SLVDMSCR       0xFF872124
-#define MXT_VSPD0SLVDMSCR      0xFF872128
-#define MXT_VSPD1SLVDMSCR      0xFF87212C
-#define MXT_MAP1SLVDMSCR       0xFF872130
-#define MXT_MAP2SLVDMSCR       0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR     0xFF882000
-#define CCI_AXI_SYX2DMSCR      0xFF882004
-#define CCI_AXI_MMURDMSCR      0xFF882008
-#define CCI_AXI_MMUDSDMSCR     0xFF88200C
-#define CCI_AXI_MMUMDMSCR      0xFF882010
-#define CCI_AXI_MXIDMSCR       0xFF882014
-#define CCI_AXI_MMUS1DMSCR     0xFF882018
-#define CCI_AXI_MMUMPDMSCR     0xFF88201C
-#define CCI_AXI_DVMDMSCR       0xFF882020
-#define CCI_AXI_CCISLVDMSCR    0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR    0xFF880400
-#define CCI_AXI_IPMMURDVMCR    0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR   0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR   0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR   0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR   0xFF880414
-#define CCI_AXI_AX2ADDRMASK    0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7790_rwdt {
-       u32 rwtcnt;     /* 0x00 */
-       u32 rwtcsra;    /* 0x04 */
-       u16 rwtcsrb;    /* 0x08 */
-};
-
-/* SWDT */
-struct r8a7790_swdt {
-       u32 swtcnt;     /* 0x00 */
-       u32 swtcsra;    /* 0x04 */
-       u16 swtcsrb;    /* 0x08 */
-};
-
-/* LBSC */
-struct r8a7790_lbsc {
-       u32 cs0ctrl;
-       u32 cs1ctrl;
-       u32 ecs0ctrl;
-       u32 ecs1ctrl;
-       u32 ecs2ctrl;
-       u32 ecs3ctrl;
-       u32 ecs4ctrl;
-       u32 ecs5ctrl;
-       u32 dummy0[4];  /* 0x20 .. 0x2C */
-       u32 cswcr0;
-       u32 cswcr1;
-       u32 ecswcr0;
-       u32 ecswcr1;
-       u32 ecswcr2;
-       u32 ecswcr3;
-       u32 ecswcr4;
-       u32 ecswcr5;
-       u32 exdmawcr0;
-       u32 exdmawcr1;
-       u32 exdmawcr2;
-       u32 dummy1[9];  /* 0x5C .. 0x7C */
-       u32 cspwcr0;
-       u32 cspwcr1;
-       u32 ecspwcr0;
-       u32 ecspwcr1;
-       u32 ecspwcr2;
-       u32 ecspwcr3;
-       u32 ecspwcr4;
-       u32 ecspwcr5;
-       u32 exwtsync;
-       u32 dummy2[3];  /* 0xA4 .. 0xAC */
-       u32 cs0bstctl;
-       u32 cs0btph;
-       u32 dummy3[2];  /* 0xB8 .. 0xBC */
-       u32 cs1gdst;
-       u32 ecs0gdst;
-       u32 ecs1gdst;
-       u32 ecs2gdst;
-       u32 ecs3gdst;
-       u32 ecs4gdst;
-       u32 ecs5gdst;
-       u32 dummy4[5];  /* 0xDC .. 0xEC */
-       u32 exdmaset0;
-       u32 exdmaset1;
-       u32 exdmaset2;
-       u32 dummy5[5];  /* 0xFC .. 0x10C */
-       u32 exdmcr0;
-       u32 exdmcr1;
-       u32 exdmcr2;
-       u32 dummy6[5];  /* 0x11C .. 0x12C */
-       u32 bcintsr;
-       u32 bcintcr;
-       u32 bcintmr;
-       u32 dummy7;     /* 0x13C */
-       u32 exbatlv;
-       u32 exwtsts;
-       u32 dummy8[14]; /* 0x148 .. 0x17C */
-       u32 atacsctrl;
-       u32 dummy9[15]; /* 0x184 .. 0x1BC */
-       u32 exbct;
-       u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7790_dbsc3 {
-       u32 dummy0[3];  /* 0x00 .. 0x08 */
-       u32 dbstate1;
-       u32 dbacen;
-       u32 dbrfen;
-       u32 dbcmd;
-       u32 dbwait;
-       u32 dbkind;
-       u32 dbconf0;
-       u32 dummy1[2];  /* 0x28 .. 0x2C */
-       u32 dbphytype;
-       u32 dummy2[3];  /* 0x34 .. 0x3C */
-       u32 dbtr0;
-       u32 dbtr1;
-       u32 dbtr2;
-       u32 dummy3;     /* 0x4C */
-       u32 dbtr3;
-       u32 dbtr4;
-       u32 dbtr5;
-       u32 dbtr6;
-       u32 dbtr7;
-       u32 dbtr8;
-       u32 dbtr9;
-       u32 dbtr10;
-       u32 dbtr11;
-       u32 dbtr12;
-       u32 dbtr13;
-       u32 dbtr14;
-       u32 dbtr15;
-       u32 dbtr16;
-       u32 dbtr17;
-       u32 dbtr18;
-       u32 dbtr19;
-       u32 dummy4[7];  /* 0x94 .. 0xAC */
-       u32 dbbl;
-       u32 dummy5[3];  /* 0xB4 .. 0xBC */
-       u32 dbadj0;
-       u32 dummy6;     /* 0xC4 */
-       u32 dbadj2;
-       u32 dummy7[5];  /* 0xCC .. 0xDC */
-       u32 dbrfcnf0;
-       u32 dbrfcnf1;
-       u32 dbrfcnf2;
-       u32 dummy8[2];  /* 0xEC .. 0xF0 */
-       u32 dbcalcnf;
-       u32 dbcaltr;
-       u32 dummy9;     /* 0xFC */
-       u32 dbrnk0;
-       u32 dummy10[31];        /* 0x104 .. 0x17C */
-       u32 dbpdncnf;
-       u32 dummy11[47];        /* 0x184 ..0x23C */
-       u32 dbdfistat;
-       u32 dbdficnt;
-       u32 dummy12[14];        /* 0x248 .. 0x27C */
-       u32 dbpdlck;
-       u32 dummy13[3]; /* 0x284 .. 0x28C */
-       u32 dbpdrga;
-       u32 dummy14[3]; /* 0x294 .. 0x29C */
-       u32 dbpdrgd;
-       u32 dummy15[24];        /* 0x2A4 .. 0x300 */
-       u32 dbbs0cnt1;
-       u32 dummy16[30];        /* 0x308 .. 0x37C */
-       u32 dbwt0cnf0;
-       u32 dbwt0cnf1;
-       u32 dbwt0cnf2;
-       u32 dbwt0cnf3;
-       u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7790_gpio {
-       u32 iointsel;
-       u32 inoutsel;
-       u32 outdt;
-       u32 indt;
-       u32 intdt;
-       u32 intclr;
-       u32 intmsk;
-       u32 posneg;
-       u32 edglevel;
-       u32 filonoff;
-       u32 intmsks;
-       u32 mskclrs;
-       u32 outdtsel;
-       u32 outdth;
-       u32 outdtl;
-       u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7790_s3c {
-       u32 s3cexcladdmsk;
-       u32 s3cexclidmsk;
-       u32 s3cadsplcr;
-       u32 s3cmaar;
-       u32 s3carcr11;
-       u32 s3crorr;
-       u32 s3cworr;
-       u32 s3carcr22;
-       u32 dummy1[2];  /* 0x20 .. 0x24 */
-       u32 s3cmctr;
-       u32 dummy2;     /* 0x2C */
-       u32 cconf0;
-       u32 cconf1;
-       u32 cconf2;
-       u32 cconf3;
-};
-
-struct r8a7790_s3c_qos {
-       u32 s3cqos0;
-       u32 s3cqos1;
-       u32 s3cqos2;
-       u32 s3cqos3;
-       u32 s3cqos4;
-       u32 s3cqos5;
-       u32 s3cqos6;
-       u32 s3cqos7;
-       u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7790_dbsc3_qos {
-       u32 dblgcnt;
-       u32 dbtmval0;
-       u32 dbtmval1;
-       u32 dbtmval2;
-       u32 dbtmval3;
-       u32 dbrqctr;
-       u32 dbthres0;
-       u32 dbthres1;
-       u32 dbthres2;
-       u32 dummy0;     /* 0x24 */
-       u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7790_mxi {
-       u32 mxsaar0;
-       u32 mxsaar1;
-       u32 dummy0[7];  /* 0x08 .. 0x20 */
-       u32 mxaxiracr;
-       u32 mxs3cracr;
-       u32 dummy1[2];  /* 0x2C .. 0x30 */
-       u32 mxaxiwacr;
-       u32 mxs3cwacr;
-       u32 dummy2;     /* 0x3C */
-       u32 mxrtcr;
-       u32 mxwtcr;
-};
-
-struct r8a7790_mxi_qos {
-       u32 vspdu0;
-       u32 vspdu1;
-       u32 du0;
-       u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7790_axi_qos {
-       u32 qosconf;
-       u32 qosctset0;
-       u32 qosctset1;
-       u32 qosctset2;
-       u32 qosctset3;
-       u32 qosreqctr;
-       u32 qosthres0;
-       u32 qosthres1;
-       u32 qosthres2;
-       u32 qosqon;
-};
+#include "rcar-base.h"
 
-#endif
+#define R8A7790_CUT_ES2X       2
+#define IS_R8A7790_ES2()       \
+       (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
 
 #endif /* __ASM_ARCH_R8A7790_H */
index d3cf0c1..42e8259 100644 (file)
@@ -1,5 +1,5 @@
-#ifndef __ASM_R8A7791_H__
-#define __ASM_R8A7791_H__
+#ifndef __ASM_R8A7791_GPIO_H__
+#define __ASM_R8A7791_GPIO_H__
 
 /* Pin Function Controller:
  * GPIO_FN_xx - GPIO used to select pin function
@@ -435,4 +435,4 @@ enum {
        GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
 };
 
-#endif /* __ASM_R8A7791_H__ */
+#endif /* __ASM_R8A7791_GPIO_H__ */
index ff30180..592c524 100644 (file)
@@ -1,69 +1,18 @@
 /*
  * arch/arm/include/asm/arch-rmobile/r8a7791.h
  *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
- */
+*/
 
 #ifndef __ASM_ARCH_R8A7791_H
 #define __ASM_ARCH_R8A7791_H
 
+#include "rcar-base.h"
 /*
- * R8A7791 I/O Addresses
+ * R-Car (R8A7791) I/O Addresses
  */
-#define        RWDT_BASE       0xE6020000
-#define        SWDT_BASE       0xE6030000
-#define        LBSC_BASE       0xFEC00200
-#define DBSC3_0_BASE   0xE6790000
-#define DBSC3_1_BASE   0xE67A0000
-#define TMU_BASE       0xE61E0000
-#define        GPIO5_BASE      0xE6055000
-#define SH_QSPI_BASE   0xE6B10000
-
-#define S3C_BASE       0xE6784000
-#define S3C_INT_BASE   0xE6784A00
-#define S3C_MEDIA_BASE 0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE    0xE6784BDC
-#define S3C_QOS_CCI0_BASE      0xE6784C00
-#define S3C_QOS_CCI1_BASE      0xE6784C24
-#define S3C_QOS_MXI_BASE       0xE6784C48
-#define S3C_QOS_AXI_BASE       0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE    0xE6791000
-#define DBSC3_0_QOS_R1_BASE    0xE6791100
-#define DBSC3_0_QOS_R2_BASE    0xE6791200
-#define DBSC3_0_QOS_R3_BASE    0xE6791300
-#define DBSC3_0_QOS_R4_BASE    0xE6791400
-#define DBSC3_0_QOS_R5_BASE    0xE6791500
-#define DBSC3_0_QOS_R6_BASE    0xE6791600
-#define DBSC3_0_QOS_R7_BASE    0xE6791700
-#define DBSC3_0_QOS_R8_BASE    0xE6791800
-#define DBSC3_0_QOS_R9_BASE    0xE6791900
-#define DBSC3_0_QOS_R10_BASE   0xE6791A00
-#define DBSC3_0_QOS_R11_BASE   0xE6791B00
-#define DBSC3_0_QOS_R12_BASE   0xE6791C00
-#define DBSC3_0_QOS_R13_BASE   0xE6791D00
-#define DBSC3_0_QOS_R14_BASE   0xE6791E00
-#define DBSC3_0_QOS_R15_BASE   0xE6791F00
-#define DBSC3_0_QOS_W0_BASE    0xE6792000
-#define DBSC3_0_QOS_W1_BASE    0xE6792100
-#define DBSC3_0_QOS_W2_BASE    0xE6792200
-#define DBSC3_0_QOS_W3_BASE    0xE6792300
-#define DBSC3_0_QOS_W4_BASE    0xE6792400
-#define DBSC3_0_QOS_W5_BASE    0xE6792500
-#define DBSC3_0_QOS_W6_BASE    0xE6792600
-#define DBSC3_0_QOS_W7_BASE    0xE6792700
-#define DBSC3_0_QOS_W8_BASE    0xE6792800
-#define DBSC3_0_QOS_W9_BASE    0xE6792900
-#define DBSC3_0_QOS_W10_BASE   0xE6792A00
-#define DBSC3_0_QOS_W11_BASE   0xE6792B00
-#define DBSC3_0_QOS_W12_BASE   0xE6792C00
-#define DBSC3_0_QOS_W13_BASE   0xE6792D00
-#define DBSC3_0_QOS_W14_BASE   0xE6792E00
-#define DBSC3_0_QOS_W15_BASE   0xE6792F00
-
 #define DBSC3_1_QOS_R0_BASE    0xE67A1000
 #define DBSC3_1_QOS_R1_BASE    0xE67A1100
 #define DBSC3_1_QOS_R2_BASE    0xE67A1200
 #define DBSC3_1_QOS_W13_BASE   0xE67A2D00
 #define DBSC3_1_QOS_W14_BASE   0xE67A2E00
 #define DBSC3_1_QOS_W15_BASE   0xE67A2F00
+#define DBSC3_1_DBADJ2         0xE67A00C8
 
-#define DBSC3_0_DBADJ2         0xE67900C8
-
-#define CCI_400_MAXOT_1                0xF0091110
-#define CCI_400_MAXOT_2                0xF0092110
-#define CCI_400_QOSCNTL_1      0xF009110C
-#define CCI_400_QOSCNTL_2      0xF009210C
-
-#define        MXI_BASE                0xFE960000
-#define        MXI_QOS_BASE            0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE        0xFF800300
-#define SYS_AXI_AVB_BASE       0xFF800340
-#define SYS_AXI_G2D_BASE       0xFF800540
-#define SYS_AXI_IMP0_BASE      0xFF800580
-#define SYS_AXI_IMP1_BASE      0xFF8005C0
-#define SYS_AXI_IMUX0_BASE     0xFF800600
-#define SYS_AXI_IMUX1_BASE     0xFF800640
-#define SYS_AXI_IMUX2_BASE     0xFF800680
-#define SYS_AXI_LBS_BASE       0xFF8006C0
-#define SYS_AXI_MMUDS_BASE     0xFF800700
-#define SYS_AXI_MMUM_BASE      0xFF800740
-#define SYS_AXI_MMUR_BASE      0xFF800780
-#define SYS_AXI_MMUS0_BASE     0xFF8007C0
-#define SYS_AXI_MMUS1_BASE     0xFF800800
-#define SYS_AXI_MTSB0_BASE     0xFF800880
-#define SYS_AXI_MTSB1_BASE     0xFF8008C0
-#define SYS_AXI_PCI_BASE       0xFF800900
-#define SYS_AXI_RTX_BASE       0xFF800940
-#define SYS_AXI_SDS0_BASE      0xFF800A80
-#define SYS_AXI_SDS1_BASE      0xFF800AC0
-#define SYS_AXI_USB20_BASE     0xFF800C00
-#define SYS_AXI_USB21_BASE     0xFF800C40
-#define SYS_AXI_USB22_BASE     0xFF800C80
-#define SYS_AXI_USB30_BASE     0xFF800CC0
-#define SYS_AXI_AX2M_BASE      0xFF800380
-#define SYS_AXI_CC50_BASE      0xFF8003C0
-#define SYS_AXI_CCI_BASE       0xFF800440
-#define SYS_AXI_CS_BASE                0xFF800480
-#define SYS_AXI_DDM_BASE       0xFF8004C0
-#define SYS_AXI_ETH_BASE       0xFF800500
-#define SYS_AXI_MPXM_BASE      0xFF800840
-#define SYS_AXI_SAT0_BASE      0xFF800980
-#define SYS_AXI_SAT1_BASE      0xFF8009C0
-#define SYS_AXI_SDM0_BASE      0xFF800A00
-#define SYS_AXI_SDM1_BASE      0xFF800A40
-#define SYS_AXI_TRAB_BASE      0xFF800B00
-#define SYS_AXI_UDM0_BASE      0xFF800B80
-#define SYS_AXI_UDM1_BASE      0xFF800BC0
-
-#define RT_AXI_SHX_BASE                0xFF810100
-#define RT_AXI_DBG_BASE                0xFF810140
-#define RT_AXI_RDM_BASE                0xFF810180
-#define RT_AXI_RDS_BASE                0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE 0xFF810200
-#define RT_AXI_STPRO_BASE      0xFF810240
-#define RT_AXI_SY2RT_BASE      0xFF810280
-
-#define MP_AXI_ADSP_BASE       0xFF820100
-#define MP_AXI_ASDS0_BASE      0xFF8201C0
-#define MP_AXI_ASDS1_BASE      0xFF820200
-#define MP_AXI_MLP_BASE                0xFF820240
-#define MP_AXI_MMUMP_BASE      0xFF820280
-#define MP_AXI_SPU_BASE                0xFF8202C0
-#define MP_AXI_SPUC_BASE       0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE    0xFF860100
-#define SYS_AXI256_SYX_BASE    0xFF860140
-#define SYS_AXI256_MPX_BASE    0xFF860180
-#define SYS_AXI256_MXI_BASE    0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE     0xFF880100
-#define CCI_AXI_SYX2_BASE      0xFF880140
-#define CCI_AXI_MMUR_BASE      0xFF880180
-#define CCI_AXI_MMUDS_BASE     0xFF8801C0
-#define CCI_AXI_MMUM_BASE      0xFF880200
-#define CCI_AXI_MXI_BASE       0xFF880240
-#define CCI_AXI_MMUS1_BASE     0xFF880280
-#define CCI_AXI_MMUMP_BASE     0xFF8802C0
-
-#define MEDIA_AXI_MXR_BASE     0xFE960080
-#define MEDIA_AXI_MXW_BASE     0xFE9600C0
-#define MEDIA_AXI_JPR_BASE     0xFE964100
-#define MEDIA_AXI_JPW_BASE     0xFE966100
-#define MEDIA_AXI_GCU0R_BASE   0xFE964140
-#define MEDIA_AXI_GCU0W_BASE   0xFE966140
-#define MEDIA_AXI_GCU1R_BASE   0xFE964180
-#define MEDIA_AXI_GCU1W_BASE   0xFE966180
-#define MEDIA_AXI_TDMR_BASE    0xFE964500
-#define MEDIA_AXI_TDMW_BASE    0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE  0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE  0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE  0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE  0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE        0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE        0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE        0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE        0xFE966600
-#define MEDIA_AXI_VIN0W_BASE   0xFE966900
-#define MEDIA_AXI_VSP0R_BASE   0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE   0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE   0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE   0xFE966D40
-#define MEDIA_AXI_IMSR_BASE    0xFE964D80
-#define MEDIA_AXI_IMSW_BASE    0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE   0xFE965100
-#define MEDIA_AXI_VSP1W_BASE   0xFE967100
-#define MEDIA_AXI_FDP1R_BASE   0xFE965140
-#define MEDIA_AXI_FDP1W_BASE   0xFE967140
-#define MEDIA_AXI_IMRR_BASE    0xFE965180
-#define MEDIA_AXI_IMRW_BASE    0xFE967180
-#define MEDIA_AXI_FDP2R_BASE   0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE   0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE  0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE  0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE  0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE  0xFE967540
-#define MEDIA_AXI_DU0R_BASE    0xFE965580
-#define MEDIA_AXI_DU0W_BASE    0xFE967580
-#define MEDIA_AXI_DU1R_BASE    0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE    0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE  0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE  0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE  0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE  0xFE967940
-#define MEDIA_AXI_VPC0R_BASE   0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE  0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE  0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE  0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE  0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE   0xFE965D80
-
-#define SYS_AXI_AVBDMSCR       0xFF802000
-#define SYS_AXI_SYX2DMSCR      0xFF802004
-#define SYS_AXI_CC50DMSCR      0xFF802008
-#define SYS_AXI_CC51DMSCR      0xFF80200C
-#define SYS_AXI_CCIDMSCR       0xFF802010
-#define SYS_AXI_CSDMSCR                0xFF802014
-#define SYS_AXI_DDMDMSCR       0xFF802018
-#define SYS_AXI_ETHDMSCR       0xFF80201C
-#define SYS_AXI_G2DDMSCR       0xFF802020
-#define SYS_AXI_IMP0DMSCR      0xFF802024
-#define SYS_AXI_IMP1DMSCR      0xFF802028
-#define SYS_AXI_LBSDMSCR       0xFF80202C
-#define SYS_AXI_MMUDSDMSCR     0xFF802030
-#define SYS_AXI_MMUMXDMSCR     0xFF802034
-#define SYS_AXI_MMURDDMSCR     0xFF802038
-#define SYS_AXI_MMUS0DMSCR     0xFF80203C
-#define SYS_AXI_MMUS1DMSCR     0xFF802040
-#define SYS_AXI_MPXDMSCR       0xFF802044
-#define SYS_AXI_MTSB0DMSCR     0xFF802048
-#define SYS_AXI_MTSB1DMSCR     0xFF80204C
-#define SYS_AXI_PCIDMSCR       0xFF802050
-#define SYS_AXI_RTXDMSCR       0xFF802054
-#define SYS_AXI_SAT0DMSCR      0xFF802058
-#define SYS_AXI_SAT1DMSCR      0xFF80205C
-#define SYS_AXI_SDM0DMSCR      0xFF802060
-#define SYS_AXI_SDM1DMSCR      0xFF802064
-#define SYS_AXI_SDS0DMSCR      0xFF802068
-#define SYS_AXI_SDS1DMSCR      0xFF80206C
-#define SYS_AXI_ETRABDMSCR     0xFF802070
-#define SYS_AXI_ETRKFDMSCR     0xFF802074
-#define SYS_AXI_UDM0DMSCR      0xFF802078
-#define SYS_AXI_UDM1DMSCR      0xFF80207C
-#define SYS_AXI_USB20DMSCR     0xFF802080
-#define SYS_AXI_USB21DMSCR     0xFF802084
-#define SYS_AXI_USB22DMSCR     0xFF802088
-#define SYS_AXI_USB30DMSCR     0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR       0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR       0xFF802104
-#define SYS_AXI_AVBSLVDMSCR    0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR   0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR    0xFF802110
-#define SYS_AXI_GICSLVDMSCR    0xFF802114
-#define SYS_AXI_IMPSLVDMSCR    0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR   0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR   0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR   0xFF802124
-#define SYS_AXI_LBSSLVDMSCR    0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR   0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR   0xFF802130
-#define SYS_AXI_MPXSLVDMSCR    0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR  0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR  0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR    0xFF802140
-#define SYS_AXI_PCISLVDMSCR    0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR  0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR  0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR    0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR   0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR   0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR  0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR  0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR  0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR  0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR    0xFF802180
-#define SYS_AXI_STBSLVDMSCR    0xFF802188
-#define SYS_AXI_STMSLVDMSCR    0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR  0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR  0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR  0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR  0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR  0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR  0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR  0xFF8021AC
-
-#define RT_AXI_CBMDMSCR                0xFF812000
-#define RT_AXI_DBDMSCR         0xFF812004
-#define RT_AXI_RDMDMSCR                0xFF812008
-#define RT_AXI_RDSDMSCR                0xFF81200C
-#define RT_AXI_STRDMSCR                0xFF812010
-#define RT_AXI_SY2RTDMSCR      0xFF812014
-#define RT_AXI_CBSSLVDMSCR     0xFF812100
-#define RT_AXI_DBSSLVDMSCR     0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR   0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR   0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR   0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR   0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR        0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR        0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR       0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR   0xFF812128
-
-#define MP_AXI_ADSPDMSCR       0xFF822000
-#define MP_AXI_ASDM0DMSCR      0xFF822004
-#define MP_AXI_ASDM1DMSCR      0xFF822008
-#define MP_AXI_ASDS0DMSCR      0xFF82200C
-#define MP_AXI_ASDS1DMSCR      0xFF822010
-#define MP_AXI_MLPDMSCR                0xFF822014
-#define MP_AXI_MMUMPDMSCR      0xFF822018
-#define MP_AXI_SPUDMSCR                0xFF82201C
-#define MP_AXI_SPUCDMSCR       0xFF822020
-#define MP_AXI_SY2MPDMSCR      0xFF822024
-#define MP_AXI_ADSPSLVDMSCR    0xFF822100
-#define MP_AXI_MLMSLVDMSCR     0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR   0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR   0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR   0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR   0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR   0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR  0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR   0xFF822124
-#define MP_AXI_SPUSLVDMSCR     0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR  0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR     0xFF842000
-#define ADM_AXI_ASDM1DMSCR     0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR  0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR  0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR  0xFF84210C
-
-#define DM_AXI_RDMDMSCR                0xFF852000
-#define DM_AXI_SDM0DMSCR       0xFF852004
-#define DM_AXI_SDM1DMSCR       0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR   0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR   0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR   0xFF852108
-#define DM_AXI_RAP4SLVDMSCR    0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR    0xFF852110
-#define DM_AXI_SAP4SLVDMSCR    0xFF852114
-#define DM_AXI_SAP5SLVDMSCR    0xFF852118
-#define DM_AXI_SAP6SLVDMSCR    0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR   0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR   0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR   0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR   0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR   0xFF852130
-
-#define SYS_AXI256_SYXDMSCR    0xFF862000
-#define SYS_AXI256_MPXDMSCR    0xFF862004
-#define SYS_AXI256_MXIDMSCR    0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR   0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR   0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
-
-#define MXT_SYXDMSCR           0xFF872000
-#define MXT_CMM0SLVDMSCR       0xFF872100
-#define MXT_CMM1SLVDMSCR       0xFF872104
-#define MXT_CMM2SLVDMSCR       0xFF872108
-#define MXT_FDPSLVDMSCR                0xFF87210C
-#define MXT_IMRSLVDMSCR                0xFF872110
-#define MXT_VINSLVDMSCR                0xFF872114
-#define MXT_VPC0SLVDMSCR       0xFF872118
-#define MXT_VPC1SLVDMSCR       0xFF87211C
-#define MXT_VSP0SLVDMSCR       0xFF872120
-#define MXT_VSP1SLVDMSCR       0xFF872124
-#define MXT_VSPD0SLVDMSCR      0xFF872128
-#define MXT_VSPD1SLVDMSCR      0xFF87212C
-#define MXT_MAP1SLVDMSCR       0xFF872130
-#define MXT_MAP2SLVDMSCR       0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR     0xFF882000
-#define CCI_AXI_SYX2DMSCR      0xFF882004
-#define CCI_AXI_MMURDMSCR      0xFF882008
-#define CCI_AXI_MMUDSDMSCR     0xFF88200C
-#define CCI_AXI_MMUMDMSCR      0xFF882010
-#define CCI_AXI_MXIDMSCR       0xFF882014
-#define CCI_AXI_MMUS1DMSCR     0xFF882018
-#define CCI_AXI_MMUMPDMSCR     0xFF88201C
-#define CCI_AXI_DVMDMSCR       0xFF882020
-#define CCI_AXI_CCISLVDMSCR    0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR    0xFF880400
-#define CCI_AXI_IPMMURDVMCR    0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR   0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR   0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR   0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR   0xFF880414
-#define CCI_AXI_AX2ADDRMASK    0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7791_rwdt {
-       u32 rwtcnt;     /* 0x00 */
-       u32 rwtcsra;    /* 0x04 */
-       u16 rwtcsrb;    /* 0x08 */
-};
-
-/* SWDT */
-struct r8a7791_swdt {
-       u32 swtcnt;     /* 0x00 */
-       u32 swtcsra;    /* 0x04 */
-       u16 swtcsrb;    /* 0x08 */
-};
-
-/* LBSC */
-struct r8a7791_lbsc {
-       u32 cs0ctrl;
-       u32 cs1ctrl;
-       u32 ecs0ctrl;
-       u32 ecs1ctrl;
-       u32 ecs2ctrl;
-       u32 ecs3ctrl;
-       u32 ecs4ctrl;
-       u32 ecs5ctrl;
-       u32 dummy0[4];  /* 0x20 .. 0x2C */
-       u32 cswcr0;
-       u32 cswcr1;
-       u32 ecswcr0;
-       u32 ecswcr1;
-       u32 ecswcr2;
-       u32 ecswcr3;
-       u32 ecswcr4;
-       u32 ecswcr5;
-       u32 exdmawcr0;
-       u32 exdmawcr1;
-       u32 exdmawcr2;
-       u32 dummy1[9];  /* 0x5C .. 0x7C */
-       u32 cspwcr0;
-       u32 cspwcr1;
-       u32 ecspwcr0;
-       u32 ecspwcr1;
-       u32 ecspwcr2;
-       u32 ecspwcr3;
-       u32 ecspwcr4;
-       u32 ecspwcr5;
-       u32 exwtsync;
-       u32 dummy2[3];  /* 0xA4 .. 0xAC */
-       u32 cs0bstctl;
-       u32 cs0btph;
-       u32 dummy3[2];  /* 0xB8 .. 0xBC */
-       u32 cs1gdst;
-       u32 ecs0gdst;
-       u32 ecs1gdst;
-       u32 ecs2gdst;
-       u32 ecs3gdst;
-       u32 ecs4gdst;
-       u32 ecs5gdst;
-       u32 dummy4[5];  /* 0xDC .. 0xEC */
-       u32 exdmaset0;
-       u32 exdmaset1;
-       u32 exdmaset2;
-       u32 dummy5[5];  /* 0xFC .. 0x10C */
-       u32 exdmcr0;
-       u32 exdmcr1;
-       u32 exdmcr2;
-       u32 dummy6[5];  /* 0x11C .. 0x12C */
-       u32 bcintsr;
-       u32 bcintcr;
-       u32 bcintmr;
-       u32 dummy7;     /* 0x13C */
-       u32 exbatlv;
-       u32 exwtsts;
-       u32 dummy8[14]; /* 0x148 .. 0x17C */
-       u32 atacsctrl;
-       u32 dummy9[15]; /* 0x184 .. 0x1BC */
-       u32 exbct;
-       u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7791_dbsc3 {
-       u32 dummy0[3];  /* 0x00 .. 0x08 */
-       u32 dbstate1;
-       u32 dbacen;
-       u32 dbrfen;
-       u32 dbcmd;
-       u32 dbwait;
-       u32 dbkind;
-       u32 dbconf0;
-       u32 dummy1[2];  /* 0x28 .. 0x2C */
-       u32 dbphytype;
-       u32 dummy2[3];  /* 0x34 .. 0x3C */
-       u32 dbtr0;
-       u32 dbtr1;
-       u32 dbtr2;
-       u32 dummy3;     /* 0x4C */
-       u32 dbtr3;
-       u32 dbtr4;
-       u32 dbtr5;
-       u32 dbtr6;
-       u32 dbtr7;
-       u32 dbtr8;
-       u32 dbtr9;
-       u32 dbtr10;
-       u32 dbtr11;
-       u32 dbtr12;
-       u32 dbtr13;
-       u32 dbtr14;
-       u32 dbtr15;
-       u32 dbtr16;
-       u32 dbtr17;
-       u32 dbtr18;
-       u32 dbtr19;
-       u32 dummy4[7];  /* 0x94 .. 0xAC */
-       u32 dbbl;
-       u32 dummy5[3];  /* 0xB4 .. 0xBC */
-       u32 dbadj0;
-       u32 dummy6;     /* 0xC4 */
-       u32 dbadj2;
-       u32 dummy7[5];  /* 0xCC .. 0xDC */
-       u32 dbrfcnf0;
-       u32 dbrfcnf1;
-       u32 dbrfcnf2;
-       u32 dummy8[2];  /* 0xEC .. 0xF0 */
-       u32 dbcalcnf;
-       u32 dbcaltr;
-       u32 dummy9;     /* 0xFC */
-       u32 dbrnk0;
-       u32 dummy10[31];        /* 0x104 .. 0x17C */
-       u32 dbpdncnf;
-       u32 dummy11[47];        /* 0x184 ..0x23C */
-       u32 dbdfistat;
-       u32 dbdficnt;
-       u32 dummy12[14];        /* 0x248 .. 0x27C */
-       u32 dbpdlck;
-       u32 dummy13[3]; /* 0x284 .. 0x28C */
-       u32 dbpdrga;
-       u32 dummy14[3]; /* 0x294 .. 0x29C */
-       u32 dbpdrgd;
-       u32 dummy15[24];        /* 0x2A4 .. 0x300 */
-       u32 dbbs0cnt1;
-       u32 dummy16[30];        /* 0x308 .. 0x37C */
-       u32 dbwt0cnf0;
-       u32 dbwt0cnf1;
-       u32 dbwt0cnf2;
-       u32 dbwt0cnf3;
-       u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7791_gpio {
-       u32 iointsel;
-       u32 inoutsel;
-       u32 outdt;
-       u32 indt;
-       u32 intdt;
-       u32 intclr;
-       u32 intmsk;
-       u32 posneg;
-       u32 edglevel;
-       u32 filonoff;
-       u32 intmsks;
-       u32 mskclrs;
-       u32 outdtsel;
-       u32 outdth;
-       u32 outdtl;
-       u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7791_s3c {
-       u32 s3cexcladdmsk;
-       u32 s3cexclidmsk;
-       u32 s3cadsplcr;
-       u32 s3cmaar;
-       u32 dummy0;     /* 0x10 */
-       u32 s3crorr;
-       u32 s3cworr;
-       u32 s3carcr22;
-       u32 dummy1[2];  /* 0x20 .. 0x24 */
-       u32 s3cmctr;
-       u32 dummy2;     /* 0x2C */
-       u32 cconf0;
-       u32 cconf1;
-       u32 cconf2;
-       u32 cconf3;
-};
-
-struct r8a7791_s3c_qos {
-       u32 s3cqos0;
-       u32 s3cqos1;
-       u32 s3cqos2;
-       u32 s3cqos3;
-       u32 s3cqos4;
-       u32 s3cqos5;
-       u32 s3cqos6;
-       u32 s3cqos7;
-       u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7791_dbsc3_qos {
-       u32 dblgcnt;
-       u32 dbtmval0;
-       u32 dbtmval1;
-       u32 dbtmval2;
-       u32 dbtmval3;
-       u32 dbrqctr;
-       u32 dbthres0;
-       u32 dbthres1;
-       u32 dbthres2;
-       u32 dummy0;     /* 0x24 */
-       u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7791_mxi {
-       u32 mxsaar0;
-       u32 mxsaar1;
-       u32 dummy0[8];  /* 0x08 .. 0x24 */
-       u32 mxs3cracr;
-       u32 dummy1[3];  /* 0x2C .. 0x34 */
-       u32 mxs3cwacr;
-       u32 dummy2;     /* 0x3C */
-       u32 mxrtcr;
-       u32 mxwtcr;
-};
-
-struct r8a7791_mxi_qos {
-       u32 vspdu0;
-       u32 vspdu1;
-       u32 du0;
-       u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7791_axi_qos {
-       u32 qosconf;
-       u32 qosctset0;
-       u32 qosctset1;
-       u32 qosctset2;
-       u32 qosctset3;
-       u32 qosreqctr;
-       u32 qosthres0;
-       u32 qosthres1;
-       u32 qosthres2;
-       u32 qosqon;
-};
-
-#endif
+#define R8A7791_CUT_ES2X       2
+#define IS_R8A7791_ES2()       \
+       (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
 
 #endif /* __ASM_ARCH_R8A7791_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
new file mode 100644 (file)
index 0000000..41240f3
--- /dev/null
@@ -0,0 +1,645 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/rcar-base.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_RCAR_BASE_H
+#define __ASM_ARCH_RCAR_BASE_H
+
+/*
+ * R-Car (R8A7790/R8A7791) I/O Addresses
+ */
+#define RWDT_BASE              0xE6020000
+#define SWDT_BASE              0xE6030000
+#define LBSC_BASE              0xFEC00200
+#define DBSC3_0_BASE           0xE6790000
+#define DBSC3_1_BASE           0xE67A0000
+#define TMU_BASE               0xE61E0000
+#define GPIO5_BASE             0xE6055000
+#define SH_QSPI_BASE           0xE6B10000
+
+/* SCIF */
+#define SCIF0_BASE             0xE6E60000
+#define SCIF1_BASE             0xE6E68000
+#define SCIF2_BASE             0xE6E58000
+#define SCIF3_BASE             0xE6EA8000
+#define SCIF4_BASE             0xE6EE0000
+#define SCIF5_BASE             0xE6EE8000
+
+#define S3C_BASE               0xE6784000
+#define S3C_INT_BASE           0xE6784A00
+#define S3C_MEDIA_BASE         0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE    0xE6784BDC
+#define S3C_QOS_CCI0_BASE      0xE6784C00
+#define S3C_QOS_CCI1_BASE      0xE6784C24
+#define S3C_QOS_MXI_BASE       0xE6784C48
+#define S3C_QOS_AXI_BASE       0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE    0xE6791000
+#define DBSC3_0_QOS_R1_BASE    0xE6791100
+#define DBSC3_0_QOS_R2_BASE    0xE6791200
+#define DBSC3_0_QOS_R3_BASE    0xE6791300
+#define DBSC3_0_QOS_R4_BASE    0xE6791400
+#define DBSC3_0_QOS_R5_BASE    0xE6791500
+#define DBSC3_0_QOS_R6_BASE    0xE6791600
+#define DBSC3_0_QOS_R7_BASE    0xE6791700
+#define DBSC3_0_QOS_R8_BASE    0xE6791800
+#define DBSC3_0_QOS_R9_BASE    0xE6791900
+#define DBSC3_0_QOS_R10_BASE   0xE6791A00
+#define DBSC3_0_QOS_R11_BASE   0xE6791B00
+#define DBSC3_0_QOS_R12_BASE   0xE6791C00
+#define DBSC3_0_QOS_R13_BASE   0xE6791D00
+#define DBSC3_0_QOS_R14_BASE   0xE6791E00
+#define DBSC3_0_QOS_R15_BASE   0xE6791F00
+#define DBSC3_0_QOS_W0_BASE    0xE6792000
+#define DBSC3_0_QOS_W1_BASE    0xE6792100
+#define DBSC3_0_QOS_W2_BASE    0xE6792200
+#define DBSC3_0_QOS_W3_BASE    0xE6792300
+#define DBSC3_0_QOS_W4_BASE    0xE6792400
+#define DBSC3_0_QOS_W5_BASE    0xE6792500
+#define DBSC3_0_QOS_W6_BASE    0xE6792600
+#define DBSC3_0_QOS_W7_BASE    0xE6792700
+#define DBSC3_0_QOS_W8_BASE    0xE6792800
+#define DBSC3_0_QOS_W9_BASE    0xE6792900
+#define DBSC3_0_QOS_W10_BASE   0xE6792A00
+#define DBSC3_0_QOS_W11_BASE   0xE6792B00
+#define DBSC3_0_QOS_W12_BASE   0xE6792C00
+#define DBSC3_0_QOS_W13_BASE   0xE6792D00
+#define DBSC3_0_QOS_W14_BASE   0xE6792E00
+#define DBSC3_0_QOS_W15_BASE   0xE6792F00
+#define DBSC3_0_DBADJ2         0xE67900C8
+
+#define CCI_400_MAXOT_1                0xF0091110
+#define CCI_400_MAXOT_2                0xF0092110
+#define CCI_400_QOSCNTL_1      0xF009110C
+#define CCI_400_QOSCNTL_2      0xF009210C
+
+#define        MXI_BASE                0xFE960000
+#define        MXI_QOS_BASE            0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE        0xFF800300
+#define SYS_AXI_AVB_BASE       0xFF800340
+#define SYS_AXI_G2D_BASE       0xFF800540
+#define SYS_AXI_IMP0_BASE      0xFF800580
+#define SYS_AXI_IMP1_BASE      0xFF8005C0
+#define SYS_AXI_IMUX0_BASE     0xFF800600
+#define SYS_AXI_IMUX1_BASE     0xFF800640
+#define SYS_AXI_IMUX2_BASE     0xFF800680
+#define SYS_AXI_LBS_BASE       0xFF8006C0
+#define SYS_AXI_MMUDS_BASE     0xFF800700
+#define SYS_AXI_MMUM_BASE      0xFF800740
+#define SYS_AXI_MMUR_BASE      0xFF800780
+#define SYS_AXI_MMUS0_BASE     0xFF8007C0
+#define SYS_AXI_MMUS1_BASE     0xFF800800
+#define SYS_AXI_MTSB0_BASE     0xFF800880
+#define SYS_AXI_MTSB1_BASE     0xFF8008C0
+#define SYS_AXI_PCI_BASE       0xFF800900
+#define SYS_AXI_RTX_BASE       0xFF800940
+#define SYS_AXI_SDS0_BASE      0xFF800A80
+#define SYS_AXI_SDS1_BASE      0xFF800AC0
+#define SYS_AXI_USB20_BASE     0xFF800C00
+#define SYS_AXI_USB21_BASE     0xFF800C40
+#define SYS_AXI_USB22_BASE     0xFF800C80
+#define SYS_AXI_USB30_BASE     0xFF800CC0
+#define SYS_AXI_AX2M_BASE     &nbs