KBUILD_OUTPUT := $(shell mkdir -p $(KBUILD_OUTPUT) && cd $(KBUILD_OUTPUT) \
&& /bin/pwd)
$(if $(KBUILD_OUTPUT),, \
- $(error output directory "$(saved-output)" does not exist))
+ $(error failed to create output directory "$(saved-output)"))
PHONY += $(MAKECMDGOALS) sub-make
else echo sh; fi ; fi)
HOSTCC = gcc
+ HOSTCXX = g++
HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
+ HOSTCXXFLAGS = -O2
+
+ ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1)
+ HOSTCFLAGS += -Wno-unused-value -Wno-unused-parameter \
+ -Wno-missing-field-initializers -fno-delete-null-pointer-checks
+ endif
ifeq ($(HOSTOS),cygwin)
HOSTCFLAGS += -ansi
# If the user is running make -s (silent mode), suppress echoing of
# commands
+ ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
+ ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
+ quiet=silent_
+ endif
+ else # make-3.8x
ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
quiet=silent_
endif
+ endif
export quiet Q KBUILD_VERBOSE
+ ifneq ($(CC),)
+ ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
+ COMPILER := clang
+ else
+ COMPILER := gcc
+ endif
+ export COMPILER
+ endif
# Look for make include files relative to root of kernel src
MAKEFLAGS += --include-dir=$(srctree)
# Files to ignore in find ... statements
- RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \
- -o -name .pc -o -name .hg -o -name .git \) -prune -o
+ export RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o \
+ -name CVS -o -name .pc -o -name .hg -o -name .git \) \
+ -prune -o
export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \
--exclude CVS --exclude .pc --exclude .hg --exclude .git
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
+ ifeq ($(COMPILER),clang)
+ KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
+ KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
+ KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
+ KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
+ KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
+ # Quiet clang warning: comparison of unsigned expression < 0 is always false
+ KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
+ # CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
+ # source of a reference will be _MergedGlobals and not on of the whitelisted names.
+ # See modpost pattern 2
+ KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
+ endif
+
KBUILD_CFLAGS += -g
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
export CONFIG_SYS_TEXT_BASE
+ # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments
+ KBUILD_CPPFLAGS += $(KCPPFLAGS)
+ KBUILD_AFLAGS += $(KAFLAGS)
+ KBUILD_CFLAGS += $(KCFLAGS)
+
# Use UBOOTINCLUDE when you must reference the include/ directory.
# Needed to be compatible with the O= option
UBOOTINCLUDE := \
ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
+ ifeq ($(CONFIG_SPL_FSL_PBL),y)
+ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
+ else
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
+ endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
+MKIMAGEFLAGS_u-boot-spl.gph = -A $(ARCH) -T gpimage -C none \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n SPL
+spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
+OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+ --gap-fill=0
+u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
+ $(call if_changed,pad_cat)
+
ifneq ($(CONFIG_TEGRA),)
OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
$(call if_changed,cat)
+ #Add a target to create boot binary having SPL binary in PBI format
+ #concatenated with u-boot binary. It is need by PowerPC SoC having
+ #internal SRAM <= 512KB.
+ MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
+ -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
+
+ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
+ OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
+ --gap-fill=0xff
+
+ u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
+ $(call if_changed,pad_cat)
+
# PPC4xx needs the SPL at the end of the image, since the reset vector
# is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target
# and need to introduce a new build target with the full blown U-Boot
CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
# Directories & files removed with 'make mrproper'
- MRPROPER_DIRS += include/config include/generated
+ MRPROPER_DIRS += include/config include/generated \
+ .tmp_objdiff
MRPROPER_FILES += .config .config.old \
tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
include/config.h include/config.mk
@find $(srctree) $(RCS_FIND_IGNORE) \
\( -name '*.orig' -o -name '*.rej' -o -name '*~' \
-o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
- -o -name '.*.rej' -o -name '*.pyc' \
- -o -name '*%' -o -name '.*.cmd' -o -name 'core' \) \
+ -o -name '.*.rej' -o -name '*%' -o -name 'core' \
+ -o -name '*.pyc' \) \
-type f -print | xargs rm -f
backup:
====================
/arch Architecture specific files
+ /arc Files generic to ARC architecture
+ /cpu CPU specific files
+ /arc700 Files specific to ARC 700 CPUs
+ /lib Architecture specific library files
/arm Files generic to ARM architecture
/cpu CPU specific files
/arm720t Files specific to ARM 720 CPUs
/mips Files generic to MIPS architecture
/cpu CPU specific files
/mips32 Files specific to MIPS32 CPUs
- /xburst Files specific to Ingenic XBurst CPUs
+ /mips64 Files specific to MIPS64 CPUs
/lib Architecture specific library files
/nds32 Files generic to NDS32 architecture
/cpu CPU specific files
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
+ CONFIG_SYS_CPC_REINIT_F
+ This CONFIG is defined when the CPC is configured as SRAM at the
+ time of U-boot entry and is required to be re-initialized.
+
+ CONFIG_DEEP_SLEEP
+ Inidcates this SoC supports deep sleep feature. If deep sleep is
+ supported, core will start to execute uboot when wakes up.
+
- Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
CONFIG_SYS_FSL_DDRC_GEN3
Freescale DDR3 controller.
+ CONFIG_SYS_FSL_DDRC_GEN4
+ Freescale DDR4 controller.
+
CONFIG_SYS_FSL_DDRC_ARM_GEN3
Freescale DDR3 controller for ARM-based SoCs.
CONFIG_SYS_FSL_DDR3
Board config to use DDR3. It can be enabled for SoCs with
- Freescale DDR3 controllers.
+ Freescale DDR3 or DDR3L controllers.
+
+ CONFIG_SYS_FSL_DDR3L
+ Board config to use DDR3L. It can be enabled for SoCs with
+ DDR3L controllers.
+
+ CONFIG_SYS_FSL_DDR4
+ Board config to use DDR4. It can be enabled for SoCs with
+ DDR4 controllers.
CONFIG_SYS_FSL_IFC_BE
Defines the IFC controller register space as Big Endian
PBI commands can be used to configure SoC before it starts the execution.
Please refer doc/README.pblimage for more details
+ CONFIG_SPL_FSL_PBL
+ It adds a target to create boot binary having SPL binary in PBI format
+ concatenated with u-boot binary.
+
CONFIG_SYS_FSL_DDR_BE
Defines the DDR controller register space as Big Endian
The default command configuration includes all commands
except those marked below with a "*".
+ CONFIG_CMD_AES AES 128 CBC encrypt/decrypt
CONFIG_CMD_ASKENV * ask for env variable
CONFIG_CMD_BDI bdinfo
CONFIG_CMD_BEDBUG * Include BedBug Debugger
for your device
- CONFIG_USBD_PRODUCTID 0xFFFF
- Some USB device drivers may need to check USB cable attachment.
- In this case you can enable following config in BoardName.h:
- CONFIG_USB_CABLE_CHECK
- This enables function definition:
- - usb_cable_connected() in include/usb.h
- Implementation of this function is board-specific.
-
- ULPI Layer Support:
The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via
the generic ULPI layer. The generic layer accesses the ULPI PHY
supports MMC, NAND and YMODEM loading of U-Boot and NAND
NAND loading of the Linux Kernel.
+ CONFIG_SPL_OS_BOOT
+ Enable booting directly to an OS from SPL.
+ See also: doc/README.falcon
+
CONFIG_SPL_DISPLAY_PRINT
For ARM, enable an optional function to print more information
about the running system.
continuing (the hardware starts execution after just
loading the first page rather than the full 4K).
+ CONFIG_SPL_SKIP_RELOCATE
+ Avoid SPL relocation
+
CONFIG_SPL_NAND_BASE
Include nand_base.c in the SPL. Requires
CONFIG_SPL_NAND_DRIVERS.
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
+ CONFIG_SPL_MTD_SUPPORT
+ Support for the MTD subsystem within SPL. Useful for
+ environment on NAND support within SPL.
+
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
drivers/ddr/fsl/libddr.o in SPL binary.
- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
Enables the RTC32K OSC on AM33xx based plattforms
+- CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
+ Option to disable subpage write in NAND driver
+ driver that uses this:
+ drivers/mtd/nand/davinci_nand.c
+
Freescale QE/FMAN Firmware Support:
-----------------------------------
are used to identify the storage device (NOR flash, SPI, etc) and the address
within that device.
- - CONFIG_SYS_QE_FMAN_FW_ADDR
- The address in the storage device where the firmware is located. The
+ - CONFIG_SYS_FMAN_FW_ADDR
+ The address in the storage device where the FMAN microcode is located. The
+ meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+ is also specified.
+
+ - CONFIG_SYS_QE_FW_ADDR
+ The address in the storage device where the QE microcode is located. The
meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
is also specified.
Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com>
+Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <vitalya@ti.com>
Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de>
Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de>
Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com>
-Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini <trini@ti.com>
+Active arm armv7 omap3 ti beagle omap3_beagle omap3_beagle:NAND Tom Rini <trini@ti.com>
Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com>
Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - -
Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>
+Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
+Active arm armv7:arm720t tegra124 nvidia jetson-tk1 jetson-tk1 jetson-tk1:BOARD_JETSON_TK1= Stephen Warren <swarren@nvidia.com>
Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
- Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
- Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
- Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
- Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Active powerpc 74xx_7xx - - - ppmc7xx - -
Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de>
- Active powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
Active powerpc 74xx_7xx - eltec elppc ELPPC - -
Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com>
Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
- Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Active powerpc mpc824x - - mvblue MVBLUE - -
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
- Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
Active powerpc mpc8260 - - - ep82xxm - -
Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
- Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu87 CPU87 - -
Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
- Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
+ Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
+ Active powerpc mpc8260 - ids ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
+ Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc85xx - - socrates socrates - -
Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
- Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
- Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale b4860qds B4860QDS_SECURE_BOOT B4860QDS:PPC_B4860,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND
Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133_SECURE BSC9132QDS:BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
- Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
- Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Active powerpc mpc85xx - freescale t1040qds T1040QDS_D4 T1040QDS:PPC_T1040,SYS_FSL_DDR4 Poonam Aggrwal <poonam.aggrwal@freescale.com>
+ Active powerpc mpc85xx - freescale t1040qds T1040QDS_SECURE_BOOT T1040QDS:PPC_T1040,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <Priyanka.Jain@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+ Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SECURE_BOOT T104xRDB:PPC_T1040,SECURE_BOOT,T1040RDB Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <Priyanka.Jain@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <Priyanka.Jain@freescale.com>
+ Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+ Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <Priyanka.Jain@freescale.com>
Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 -
- Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
- Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
- Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale t208xqds T2080QDS_SECURE_BOOT T208xQDS:PPC_T2080,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+ Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+ Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 -
- Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
- Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
- Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+ Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
+ Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
- Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
- Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
- Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+ Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+ Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
- Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale t4qds T4160QDS_NAND T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+ Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
- Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
- Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
+ Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
+ Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
+ Active powerpc mpc85xx - freescale qemu-ppce500 qemu-ppce500 - Alexander Graf <agraf@suse.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
Active sparc leon3 - gaisler - gr_xc3s_1500 - -
Active sparc leon3 - gaisler - grsim - -
Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
+ # The following were moved to "Orphan" in April, 2014
+ Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
+ Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
+ Orphan powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
+ Orphan powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
# The following were moved to "Orphan" in March, 2014
Orphan blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Orphan blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
# The following were move to "Orphan" in September, 2013
Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
- Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net>
- Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - -
- Orphan powerpc mpc824x - - mousse MOUSSE - -
- Orphan powerpc mpc8260 - - - rsdproto - -
- Orphan powerpc mpc8260 - - rpxsuper RPXsuper - -
- Orphan powerpc mpc8xx - - - RPXClassic - -
- Orphan powerpc mpc8xx - - - RPXlite - -
- Orphan powerpc mpc8xx - - fads ADS860 - -
- Orphan powerpc mpc8xx - - fads FADS823 - -
- Orphan powerpc mpc8xx - - fads FADS850SAR - -
- Orphan powerpc mpc8xx - - fads FADS860T - -
- Orphan powerpc mpc8xx - - genietv GENIETV - -
- Orphan powerpc mpc8xx - - mbx8xx MBX - -
- Orphan powerpc mpc8xx - - mbx8xx MBX860T - -
- Orphan powerpc mpc8xx - - nx823 NX823 - -
static int init_mmc_for_env(struct mmc *mmc)
{
+#ifdef CONFIG_SYS_MMC_ENV_PART
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
+#endif
+
if (!mmc) {
puts("No MMC card found\n");
return -1;
#ifdef CONFIG_SYS_MMC_ENV_PART
if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num) {
- if (mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
- CONFIG_SYS_MMC_ENV_PART)) {
+ if (mmc_switch_part(dev, CONFIG_SYS_MMC_ENV_PART)) {
puts("MMC partition switch failed\n");
return -1;
}
static void fini_mmc_for_env(struct mmc *mmc)
{
#ifdef CONFIG_SYS_MMC_ENV_PART
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
if (CONFIG_SYS_MMC_ENV_PART != mmc->part_num)
- mmc_switch_part(CONFIG_SYS_MMC_ENV_DEV,
- mmc->part_num);
+ mmc_switch_part(dev, mmc->part_num);
#endif
}
int saveenv(void)
{
ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
- ssize_t len;
- char *res;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
u32 offset;
int ret, copy = 0;
if (init_mmc_for_env(mmc))
return 1;
- res = (char *)&env_new->data;
- len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
- if (len < 0) {
- error("Cannot export environment: errno = %d\n", errno);
- ret = 1;
+ ret = env_export(env_new);
+ if (ret)
goto fini;
- }
-
- env_new->crc = crc32(0, &env_new->data[0], ENV_SIZE);
#ifdef CONFIG_ENV_OFFSET_REDUND
env_new->flags = ++env_flags; /* increase the serial */
unsigned long offset, const void *buffer)
{
uint blk_start, blk_cnt, n;
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
- n = mmc->block_dev.block_read(CONFIG_SYS_MMC_ENV_DEV, blk_start,
- blk_cnt, (uchar *)buffer);
+ n = mmc->block_dev.block_read(dev, blk_start, blk_cnt, (uchar *)buffer);
return (n == blk_cnt) ? 0 : -1;
}
void env_relocate_spec(void)
{
#if !defined(ENV_IS_EMBEDDED)
- struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ struct mmc *mmc;
u32 offset1, offset2;
int read1_fail = 0, read2_fail = 0;
int crc1_ok = 0, crc2_ok = 0;
env_t *ep;
int ret;
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env1, 1);
ALLOC_CACHE_ALIGN_BUFFER(env_t, tmp_env2, 1);
- if (tmp_env1 == NULL || tmp_env2 == NULL) {
- puts("Can't allocate buffers for environment\n");
- ret = 1;
- goto err;
- }
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
+
+ mmc = find_mmc_device(dev);
if (init_mmc_for_env(mmc)) {
ret = 1;
{
#if !defined(ENV_IS_EMBEDDED)
ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
- struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
+ struct mmc *mmc;
u32 offset;
int ret;
+ int dev = CONFIG_SYS_MMC_ENV_DEV;
+
+#ifdef CONFIG_SPL_BUILD
+ dev = 0;
+#endif
+
+ mmc = find_mmc_device(dev);
if (init_mmc_for_env(mmc)) {
ret = 1;
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "fdt_high=0xffffffff\0" \
+ DEFAULT_LINUX_BOOT_ENV \
"boot_fdt=try\0" \
- "rdaddr=0x81000000\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"nfsopts=nolock\0" \
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
"::off\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+ "ramroot=/dev/ram0 rw\0" \
"ramrootfstype=ext2\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
-/* SPI flash. */
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
-#define CONFIG_SPL_SPI_LOAD
-#define CONFIG_SPL_SPI_BUS 0
-#define CONFIG_SPL_SPI_CS 0
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
-
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#ifdef CONFIG_NAND
#endif
/* USB Device Firmware Update support */
+ #ifndef CONFIG_SPL_BUILD
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
#define CONFIG_CMD_DFU
"boot part 0 1;" \
"rootfs part 0 2;" \
"MLO fat 0 1;" \
- "MLO.raw mmc 100 100;" \
- "u-boot.img.raw mmc 300 400;" \
- "spl-os-args.raw mmc 80 80;" \
- "spl-os-image.raw mmc 900 2000;" \
+ "MLO.raw mmc 0x100 0x100;" \
+ "u-boot.img.raw mmc 0x300 0x400;" \
+ "spl-os-args.raw mmc 0x80 0x80;" \
+ "spl-os-image.raw mmc 0x900 0x2000;" \
"spl-os-args fat 0 1;" \
"spl-os-image fat 0 1;" \
"u-boot.img fat 0 1;" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_NAND
+ #endif
/*
* Default to using SPI for environment, etc.
* 0x442000 - 0x800000 : Userland
*/
#if defined(CONFIG_SPI_BOOT)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
+
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
-#undef CONFIG_SPL_SPI_SUPPORT
#ifdef CONFIG_NOR_BOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#include <libfdt.h>
+ u32 fdt_getprop_u32_default_node(const void *fdt, int off, int cell,
+ const char *prop, const u32 dflt);
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt);
int fdt_chosen(void *fdt, int force);
#endif
void ft_board_setup(void *blob, bd_t *bd);
+/*
+ * The keystone2 SOC requires all 32 bit aliased addresses to be converted
+ * to their 36 physical format. This has to happen after all fdt nodes
+ * are added or modified by the image_setup_libfdt(). The ft_board_setup_ex()
+ * called at the end of the image_setup_libfdt() is to do that convertion.
+ */
+void ft_board_setup_ex(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
void ft_pci_setup(void *blob, bd_t *bd);
int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
u64 addr);
u64 fdt_get_base_address(void *fdt, int node);
+ int fdt_read_range(void *fdt, int node, int n, uint64_t *child_addr,
+ uint64_t *addr, uint64_t *len);
enum fdt_status {
FDT_STATUS_OKAY,
}
#endif /* ifdef CONFIG_OF_LIBFDT */
+
+ #ifdef USE_HOSTCC
+ int fdtdec_get_int(const void *blob, int node, const char *prop_name,
+ int default_val);
+ #endif
#endif /* ifndef __FDT_SUPPORT_H */
# ifdef CONFIG_SPL_SHA1_SUPPORT
# define IMAGE_ENABLE_SHA1 1
# endif
+ # ifdef CONFIG_SPL_SHA256_SUPPORT
+ # define IMAGE_ENABLE_SHA256 1
+ # endif
# else
# define CONFIG_CRC32 /* FIT images need CRC32 support */
# define CONFIG_MD5 /* and MD5 */
# define CONFIG_SHA1 /* and SHA1 */
+ # define CONFIG_SHA256 /* and SHA256 */
# define IMAGE_ENABLE_CRC32 1
# define IMAGE_ENABLE_MD5 1
# define IMAGE_ENABLE_SHA1 1
+ # define IMAGE_ENABLE_SHA256 1
# endif
#ifndef IMAGE_ENABLE_CRC32
#define IMAGE_ENABLE_SHA1 0
#endif
+ #ifndef IMAGE_ENABLE_SHA256
+ #define IMAGE_ENABLE_SHA256 0
+ #endif
+
#endif /* CONFIG_FIT */
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */
#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */
#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */
+#define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */
/*
* Compression Types
#if defined(CONFIG_FIT_SIGNATURE)
# ifdef USE_HOSTCC
# define IMAGE_ENABLE_SIGN 1
- # define IMAGE_ENABLE_VERIFY 0
+ # define IMAGE_ENABLE_VERIFY 1
+ # include <openssl/evp.h>
#else
# define IMAGE_ENABLE_SIGN 0
# define IMAGE_ENABLE_VERIFY 1
#endif
#ifdef USE_HOSTCC
- # define gd_fdt_blob() NULL
+ void *image_get_host_blob(void);
+ void image_set_host_blob(void *host_blob);
+ # define gd_fdt_blob() image_get_host_blob()
#else
# define gd_fdt_blob() (gd->fdt_blob)
#endif
int size;
};
+ #if IMAGE_ENABLE_VERIFY
+ # include <rsa-checksum.h>
+ #endif
+ struct checksum_algo {
+ const char *name;
+ const int checksum_len;
+ const int pad_len;
+ #if IMAGE_ENABLE_SIGN
+ const EVP_MD *(*calculate_sign)(void);
+ #endif
+ void (*calculate)(const struct image_region region[],
+ int region_count, uint8_t *checksum);
+ const uint8_t *rsa_padding;
+ };
+
struct image_sig_algo {
const char *name; /* Name of algorithm */
int (*verify)(struct image_sign_info *info,
const struct image_region region[], int region_count,
uint8_t *sig, uint sig_len);
+
+ /* pointer to checksum algorithm */
+ struct checksum_algo *checksum;
};
/**
static inline int fit_image_check_target_arch(const void *fdt, int node)
{
+ #ifndef USE_HOSTCC
return fit_image_check_arch(fdt, node, IH_ARCH_DEFAULT);
+ #else
+ return 0;
+ #endif
}
#ifdef CONFIG_FIT_VERBOSE
# TODO: CONFIG_CMD_LICENSE does not work
hostprogs-$(CONFIG_CMD_LICENSE) += bin2header$(SFX)
-
hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
HOSTCFLAGS_bmp_logo$(SFX).o := -pedantic
mkenvimage$(SFX)-objs := crc32.o mkenvimage.o os_support.o
hostprogs-y += dumpimage$(SFX) mkimage$(SFX)
+ hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info$(SFX) fit_check_sign$(SFX)
FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := image-sig.o
# Flattened device tree objects
LIBFDT_OBJS := fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o
- RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o
+ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o rsa-verify.o rsa-checksum.o
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
$(FIT_SIG_OBJS-y) \
crc32.o \
default_image.o \
+ fdtdec.o \
+ fit_common.o \
fit_image.o \
+ gpimage.o \
+ gpimage-common.o \
image-fit.o \
image-host.o \
image.o \
os_support.o \
pblimage.o \
sha1.o \
+ sha256.o \
ublimage.o \
$(LIBFDT_OBJS) \
$(RSA_OBJS-y)
dumpimage$(SFX)-objs := $(dumpimage-mkimage-objs) dumpimage.o
mkimage$(SFX)-objs := $(dumpimage-mkimage-objs) mkimage.o
+ fit_info$(SFX)-objs := $(dumpimage-mkimage-objs) fit_info.o
+ fit_check_sign$(SFX)-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
# TODO(sjg@chromium.org): Is this correct on Mac OS?
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
+ HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto
+ HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
ifdef CONFIG_FIT_SIGNATURE
HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
+ HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto
+ HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto
# This affects include/image.h, but including the board config file
# is tricky, so manually define this options here.
HOSTCFLAGS_crc32.o := -pedantic
HOSTCFLAGS_md5.o := -pedantic
HOSTCFLAGS_sha1.o := -pedantic
+ HOSTCFLAGS_sha256.o := -pedantic
# Don't build by default
#hostprogs-$(CONFIG_PPC) += mpc86x_clk$(SFX)
#include "fw_env.h"
+ #include <aes.h>
+
+ #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
+
#define WHITESPACE(c) ((c == '\t') || (c == ' '))
#define min(x, y) ({ \
_min1 < _min2 ? _min1 : _min2; })
struct envdev_s {
- char devname[16]; /* Device name */
+ const char *devname; /* Device name */
ulong devoff; /* Device offset */
ulong env_size; /* environment size */
ulong erase_size; /* device erase size */
.flag_scheme = FLAG_NONE,
};
+ /* Is AES encryption used? */
+ static int aes_flag;
+ static uint8_t aes_key[AES_KEY_LENGTH] = { 0 };
+ static int env_aes_cbc_crypt(char *data, const int enc);
+
static int HaveRedundEnv = 0;
static unsigned char active_flag = 1;
if (HaveRedundEnv)
rc -= sizeof (char);
+
+ if (aes_flag)
+ rc &= ~(AES_KEY_LENGTH - 1);
+
return rc;
}
return NULL;
}
+ static int parse_aes_key(char *key)
+ {
+ char tmp[5] = { '0', 'x', 0, 0, 0 };
+ unsigned long ul;
+ int i;
+
+ if (strnlen(key, 64) != 32) {
+ fprintf(stderr,
+ "## Error: '-a' option requires 16-byte AES key\n");
+ return -1;
+ }
+
+ for (i = 0; i < 16; i++) {
+ tmp[2] = key[0];
+ tmp[3] = key[1];
+ errno = 0;
+ ul = strtoul(tmp, NULL, 16);
+ if (errno) {
+ fprintf(stderr,
+ "## Error: '-a' option requires valid AES key\n");
+ return -1;
+ }
+ aes_key[i] = ul & 0xff;
+ key += 2;
+ }
+ aes_flag = 1;
+
+ return 0;
+ }
+
/*
* Print the current definition of one, or more, or all
* environment variables
int i, n_flag;
int rc = 0;
+ if (argc >= 2 && strcmp(argv[1], "-a") == 0) {
+ if (argc < 3) {
+ fprintf(stderr,
+ "## Error: '-a' option requires AES key\n");
+ return -1;
+ }
+ rc = parse_aes_key(argv[2]);
+ if (rc)
+ return rc;
+ argv += 2;
+ argc -= 2;
+ }
+
if (fw_env_open())
return -1;
int fw_env_close(void)
{
+ int ret;
+ if (aes_flag) {
+ ret = env_aes_cbc_crypt(environment.data, 1);
+ if (ret) {
+ fprintf(stderr,
+ "Error: can't encrypt env for flash\n");
+ return ret;
+ }
+ }
+
/*
* Update CRC
*/
*/
int fw_setenv(int argc, char *argv[])
{
- int i;
+ int i, rc;
size_t len;
char *name;
char *value = NULL;
return -1;
}
+ if (strcmp(argv[1], "-a") == 0) {
+ if (argc < 3) {
+ fprintf(stderr,
+ "## Error: '-a' option requires AES key\n");
+ return -1;
+ }
+ rc = parse_aes_key(argv[2]);
+ if (rc)
+ return rc;
+ argv += 2;
+ argc -= 2;
+ }
+
+ if (argc < 2) {
+ errno = EINVAL;
+ return -1;
+ }
+
if (fw_env_open()) {
fprintf(stderr, "Error: environment not initialized\n");
return -1;
return rc;
}
+ /* Encrypt or decrypt the environment before writing or reading it. */
+ static int env_aes_cbc_crypt(char *payload, const int enc)
+ {
+ uint8_t *data = (uint8_t *)payload;
+ const int len = getenvsize();
+ uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
+ uint32_t aes_blocks;
+
+ /* First we expand the key. */
+ aes_expand_key(aes_key, key_exp);
+
+ /* Calculate the number of AES blocks to encrypt. */
+ aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
+
+ if (enc)
+ aes_cbc_encrypt_blocks(key_exp, data, data, aes_blocks);
+ else
+ aes_cbc_decrypt_blocks(key_exp, data, data, aes_blocks);
+
+ return 0;
+ }
+
static int flash_write (int fd_current, int fd_target, int dev_target)
{
int rc;
fprintf(stderr, "Writing new environment at 0x%lx on %s\n",
DEVOFFSET (dev_target), DEVNAME (dev_target));
#endif
+
rc = flash_write_buf(dev_target, fd_target, environment.image,
CUR_ENVSIZE, DEVOFFSET(dev_target),
DEVTYPE(dev_target));
rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
DEVOFFSET (dev_current), mtdinfo.type);
+ if (rc != CUR_ENVSIZE)
+ return -1;
- return (rc != CUR_ENVSIZE) ? -1 : 0;
+ return 0;
}
static int flash_io (int mode)
unsigned char flag1;
void *addr1;
+ int ret;
+
struct env_image_single *single;
struct env_image_redundant *redundant;
return -1;
crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
+
+ if (aes_flag) {
+ ret = env_aes_cbc_crypt(environment.data, 0);
+ if (ret)
+ return ret;
+ }
+
crc0_ok = (crc0 == *environment.crc);
if (!HaveRedundEnv) {
if (!crc0_ok) {
}
crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
+
+ if (aes_flag) {
+ ret = env_aes_cbc_crypt(redundant->data, 0);
+ if (ret)
+ return ret;
+ }
+
crc1_ok = (crc1 == redundant->crc);
flag1 = redundant->flags;
return -1;
}
#else
- strcpy (DEVNAME (0), DEVICE1_NAME);
+ DEVNAME (0) = DEVICE1_NAME;
DEVOFFSET (0) = DEVICE1_OFFSET;
ENVSIZE (0) = ENV1_SIZE;
/* Default values are: erase-size=env-size */
#endif
#ifdef HAVE_REDUND
- strcpy (DEVNAME (1), DEVICE2_NAME);
+ DEVNAME (1) = DEVICE2_NAME;
DEVOFFSET (1) = DEVICE2_OFFSET;
ENVSIZE (1) = ENV2_SIZE;
/* Default values are: erase-size=env-size */
int i = 0;
int rc;
char dump[128];
+ char *devname;
fp = fopen (fname, "r");
if (fp == NULL)
if (dump[0] == '#')
continue;
- rc = sscanf (dump, "%s %lx %lx %lx %lx",
- DEVNAME (i),
+ rc = sscanf (dump, "%ms %lx %lx %lx %lx",
+ &devname,
&DEVOFFSET (i),
&ENVSIZE (i),
&DEVESIZE (i),
if (rc < 3)
continue;
+ DEVNAME(i) = devname;
+
if (rc < 4)
/* Assume the erase size is the same as the env-size */
DEVESIZE(i) = ENVSIZE(i);
projects / karo-tx-uboot.git / commitdiff