]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 18 Dec 2013 21:19:02 +0000 (22:19 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 18 Dec 2013 21:19:02 +0000 (22:19 +0100)
arch/arm/cpu/pxa/pxa2xx.c
board/icpdas/lp8x4x/lp8x4x.c
include/configs/balloon3.h
include/configs/lp8x4x.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/scb9328.h
include/configs/zipitz2.h

index c9a7d45392f3cb92f299a6d3cb6f62261d308656..7e861e26dba7e1baa009e0bf85459ae068eb47b1 100644 (file)
@@ -279,6 +279,7 @@ void reset_cpu(ulong ignored)
        tmp = readl(OSCR);
        tmp += 0x1000;
        writel(tmp, OSMR3);
+       writel(MDREFR_SLFRSH, MDREFR);
 
        for (;;)
                ;
index 92dd4ff97a7e27b09504de0ac2774c326415fcd8..a136dc4c37ab611bbcbd82a7379f90251b0b3a96 100644 (file)
@@ -61,15 +61,24 @@ int board_mmc_init(bd_t *bis)
 #ifdef CONFIG_CMD_USB
 int board_usb_init(int index, enum usb_init_type init)
 {
-       writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
-               ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
-               UHCHR);
+       if (index !=0 || init != USB_INIT_HOST)
+               return -1;
+
+       writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
+
+       writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
+       udelay(11);
+       writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 
        writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
 
        while (readl(UHCHR) & UHCHR_FSBIR)
                continue; /* required by checkpath.pl */
 
+       writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
+       writel(readl(UHCRHDA) & ~(0x1000), UHCRHDA);
+       writel(readl(UHCRHDA) | 0x800, UHCRHDA);
+
        writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
        writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
 
@@ -83,19 +92,10 @@ int board_usb_init(int index, enum usb_init_type init)
        /* Set port power control mask bits, only 3 ports. */
        writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
 
-       /* enable port 2 */
-       writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
-               UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
-
-       return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
        return 0;
 }
 
-void usb_board_stop(void)
+int usb_board_stop(void)
 {
        writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
        udelay(11);
@@ -104,32 +104,25 @@ void usb_board_stop(void)
        writel(readl(UHCCOMS) | 1, UHCCOMS);
        udelay(10);
 
+       writel(readl(UHCHR) | UHCHR_SSEP0 | UHCHR_SSE, UHCHR);
+
        writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 
-       return;
+       return 0;
 }
-#endif
 
-#ifdef CONFIG_DRIVER_DM9000
-void lp8x4x_eth1_mac_init(void)
+int board_usb_cleanup(int index, enum usb_init_type init)
 {
-       u8 eth1addr[8];
-       int i;
-       u8 reg;
-
-       eth_getenv_enetaddr_by_index("eth", 1, eth1addr);
-       if (!is_valid_ether_addr(eth1addr))
-               return;
-
-       for (i = 0, reg = 0x10; i < 6; i++, reg++) {
-               writeb(reg, (u8 *)(DM9000_IO_2));
-               writeb(eth1addr[i], (u8 *)(DM9000_DATA_2));
-       }
+       if (index !=0 || init != USB_INIT_HOST)
+               return -1;
+
+       return usb_board_stop();
 }
+#endif
 
+#ifdef CONFIG_DRIVER_DM9000
 int board_eth_init(bd_t *bis)
 {
-       lp8x4x_eth1_mac_init();
        return dm9000_initialize(bis);
 }
 #endif
index 12df45b0facce65bdf7e931fcc5b09960279767b..d3d62744fa04a827492890f3a5252137d41cc27d 100644 (file)
@@ -85,7 +85,7 @@
  * Clock Configuration
  */
 #undef CONFIG_SYS_CLKS_IN_HZ
-#define        CONFIG_SYS_HZ                   3250000         /* Timer @ 3250000 Hz */
+#define        CONFIG_SYS_HZ                   1000
 #define        CONFIG_SYS_CPUSPEED             0x290           /* 520MHz */
 
 /*
 
 #define        CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 
-#define        CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_LOCK_TOUT      (2*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_UNLOCK_TOUT    (2*CONFIG_SYS_HZ)
+#define        CONFIG_SYS_FLASH_ERASE_TOUT     240000
+#define        CONFIG_SYS_FLASH_WRITE_TOUT     240000
+#define        CONFIG_SYS_FLASH_LOCK_TOUT      240000
+#define        CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
 #define        CONFIG_SYS_FLASH_PROTECTION
 #define        CONFIG_ENV_IS_IN_FLASH
 #else
index 68e1a974dd0d03bb6db93d7062a5f8bd79abb9d3..8e58fea3b378980637f7ea37324cfcc31db9550b 100644 (file)
 #define        CONFIG_SYS_MALLOC_LEN           (128*1024)
 #define        CONFIG_ARCH_CPU_INIT
 #define        CONFIG_BOOTCOMMAND              \
-       "bootm 80000;"
+       "bootm 80000 - 240000;"
 
 #define        CONFIG_BOOTARGS                 \
-       "console=ttySA0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
-       "init=/sbin/init rootfstype=ext3"
+       "console=ttyS0,115200 mem=128M root=/dev/mmcblk0p1 rw" \
+       "init=/sbin/init rootfstype=ext4 rootwait"
 
 #define        CONFIG_TIMESTAMP
 #define        CONFIG_BOOTDELAY                2       /* Autoboot delay */
 #define        CONFIG_CMDLINE_TAG
 #define        CONFIG_SETUP_MEMORY_TAGS
 #define        CONFIG_LZMA                     /* LZMA compression support */
-#undef CONFIG_OF_LIBFDT
+#define        CONFIG_OF_LIBFDT
 
 /*
  * Serial Console Configuration
  */
 #define        CONFIG_SYS_HUSH_PARSER          1
 
-#undef CONFIG_SYS_LONGHELP
+#define        CONFIG_SYS_LONGHELP
 #ifdef CONFIG_SYS_HUSH_PARSER
 #define        CONFIG_SYS_PROMPT               "$ "
 #else
 #define        CONFIG_ENV_SECT_SIZE            0x40000
 
 #define        PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
-#define        PHYS_FLASH_2                    0x02000000      /* Flash Bank #2 */
+#define        PHYS_FLASH_2                    0x04000000      /* Flash Bank #2 */
 
 #define        CONFIG_SYS_FLASH_CFI
 #define        CONFIG_FLASH_CFI_DRIVER         1
 #define        CONFIG_SYS_GAFR1_L_VAL  0x999a955a
 #define        CONFIG_SYS_GAFR1_U_VAL  0xaaa5a00a
 #define        CONFIG_SYS_GAFR2_L_VAL  0xaaaaaaaa
-#define        CONFIG_SYS_GAFR2_U_VAL  0x55f0a402
+#define        CONFIG_SYS_GAFR2_U_VAL  0x55f9a402
 #define        CONFIG_SYS_GAFR3_L_VAL  0x540a950c
 #define        CONFIG_SYS_GAFR3_U_VAL  0x00001599
 
  */
 #ifdef CONFIG_CMD_USB
 #define        CONFIG_USB_OHCI_NEW
-#define        CONFIG_SYS_USB_OHCI_CPU_INIT
 #define        CONFIG_SYS_USB_OHCI_BOARD_INIT
 #define        CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 #define        CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
index 84bc9ed81361d258e6f3fcb965d16e38fcce4789..a5b6e3aa95db5bb4c24ad959afc90949901da628 100644 (file)
  * Clock Configuration
  */
 #undef CONFIG_SYS_CLKS_IN_HZ
-#define        CONFIG_SYS_HZ                   3250000         /* Timer @ 3250000 Hz */
+#define        CONFIG_SYS_HZ                   1000
 #define        CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
 
 /*
 
 #define        CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 
-#define        CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_LOCK_TOUT      (25*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_UNLOCK_TOUT    (25*CONFIG_SYS_HZ)
+#define        CONFIG_SYS_FLASH_ERASE_TOUT     240000
+#define        CONFIG_SYS_FLASH_WRITE_TOUT     240000
+#define        CONFIG_SYS_FLASH_LOCK_TOUT      240000
+#define        CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
 #define        CONFIG_SYS_FLASH_PROTECTION
 
 #define        CONFIG_ENV_IS_IN_FLASH          1
index 661101ccb689acc20c6876d6b88231f92a746c9f..7303e1c31f0a837c746e58b8ec8683d8f5c4599a 100644 (file)
  * Clock Configuration
  */
 #undef CONFIG_SYS_CLKS_IN_HZ
-#define        CONFIG_SYS_HZ                   3686400         /* Timer @ 3686400 Hz */
+#define        CONFIG_SYS_HZ                   1000
 #define        CONFIG_SYS_CPUSPEED             0x161           /* 400MHz;L=1 M=3 T=1 */
 
 /*
 
 #define        CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 
-#define        CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_LOCK_TOUT      (2*CONFIG_SYS_HZ)
-#define        CONFIG_SYS_FLASH_UNLOCK_TOUT    (2*CONFIG_SYS_HZ)
+#define        CONFIG_SYS_FLASH_ERASE_TOUT     240000
+#define        CONFIG_SYS_FLASH_WRITE_TOUT     240000
+#define        CONFIG_SYS_FLASH_LOCK_TOUT      240000
+#define        CONFIG_SYS_FLASH_UNLOCK_TOUT    240000
 #define        CONFIG_SYS_FLASH_PROTECTION
 
 #define        CONFIG_ENV_IS_IN_FLASH          1
index a09310c889626d4d2789fb46ca21c45e287d3864..c0048aca78a5ff263b85a97a2dd21f41a5c5ce69 100644 (file)
@@ -69,7 +69,7 @@
 #define CONFIG_SYS_MEMTEST_START       0x08100000            /* memtest test area   */
 #define CONFIG_SYS_MEMTEST_END         0x08F00000
 
-#define CONFIG_SYS_HZ                  3686400      /* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ                  1000
 #define CONFIG_SYS_CPUSPEED            0x141        /* core clock - register value  */
 
 #define CONFIG_BAUDRATE 115200
    now.*/
 #undef CONFIG_SYS_FLASH_CFI
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Erase operation */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ)    /* timeout for Write operation */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    240000    /* timeout for Erase operation */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    240000    /* timeout for Write operation */
 
 #define CONFIG_SYS_FLASH_BASE          SCB9328_FLASH_BASE
 
index 52a745e6049ef2211e70dc668ba02bd17809c497..904f3b0fb15ea425f9d4dd733cc61ac2039ac099 100644 (file)
@@ -139,7 +139,7 @@ unsigned char zipitz2_spi_read(void);
  * Clock Configuration
  */
 #undef CONFIG_SYS_CLKS_IN_HZ
-#define        CONFIG_SYS_HZ                   3250000         /* Timer @ 3250000 Hz */
+#define        CONFIG_SYS_HZ                   1000
 #define CONFIG_SYS_CPUSPEED            0x190           /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
 
 /*
@@ -186,10 +186,10 @@ unsigned char zipitz2_spi_read(void);
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE      1
 
-#define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_LOCK_TOUT     (2*CONFIG_SYS_HZ)
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT   (2*CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_ERASE_TOUT    240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT    240000
+#define CONFIG_SYS_FLASH_LOCK_TOUT     240000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT   240000
 #define CONFIG_SYS_FLASH_PROTECTION
 
 /*