Merge branch 'master' of git://git.denx.de/u-boot-microblaze
authorWolfgang Denk <wd@denx.de>
Tue, 31 Jul 2012 20:01:08 +0000 (22:01 +0200)
committerWolfgang Denk <wd@denx.de>
Tue, 31 Jul 2012 20:01:08 +0000 (22:01 +0200)
* 'master' of git://git.denx.de/u-boot-microblaze:
  microblaze: Wire up SPI driver
  spi: microblaze: Adds driver for Xilinx SPI controller
  microblaze: intc: Clear interrupt code
  microblaze: Call serial multi initialization
  microblaze: Move __udelay implementation
  microblaze: Remove extern from board.c
  microblaze: Wire up dts configuration
  fdt: Add board specific dts inclusion
  microblaze: Move individual board linker scripts to common script in cpu tree.
  microblaze: Add gpio.h
  microblaze: Add missing undefs for UBI and UBIFS
  microblaze: Expand and correct configuration comments
  microblaze: Enable ubi support
  microblaze: Avoid compile error on systems without cfi flash
  microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION

Conflicts:
drivers/spi/Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>
514 files changed:
MAINTAINERS
Makefile
README
arch/arm/cpu/arm1136/cpu.c
arch/arm/cpu/arm1136/start.S
arch/arm/cpu/arm1176/start.S
arch/arm/cpu/arm720t/start.S
arch/arm/cpu/arm920t/start.S
arch/arm/cpu/arm925t/start.S
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S
arch/arm/cpu/arm926ejs/kirkwood/mpp.c
arch/arm/cpu/arm926ejs/mx28/mx28.c
arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
arch/arm/cpu/arm926ejs/spear/Makefile
arch/arm/cpu/arm926ejs/spear/cpu.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spear600.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spl.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spl_boot.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/start.S [new file with mode: 0644]
arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds [new file with mode: 0644]
arch/arm/cpu/arm946es/start.S
arch/arm/cpu/arm_intcm/start.S
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/config.mk
arch/arm/cpu/armv7/exynos/Makefile
arch/arm/cpu/armv7/exynos/pinmux.c [new file with mode: 0644]
arch/arm/cpu/armv7/exynos/power.c
arch/arm/cpu/armv7/exynos/system.c
arch/arm/cpu/armv7/imx-common/speed.c
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap-common/hwinit-common.c
arch/arm/cpu/armv7/omap-common/reset.c
arch/arm/cpu/armv7/omap4/clocks.c
arch/arm/cpu/armv7/omap4/hwinit.c
arch/arm/cpu/armv7/omap4/sdram_elpida.c
arch/arm/cpu/armv7/omap5/clocks.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/cpu/armv7/s5p-common/cpu_info.c
arch/arm/cpu/armv7/start.S
arch/arm/cpu/armv7/tegra2/Makefile
arch/arm/cpu/armv7/tegra2/ap20.c
arch/arm/cpu/armv7/tegra2/board.c
arch/arm/cpu/armv7/tegra2/clock.c
arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c [new file with mode: 0644]
arch/arm/cpu/armv7/tegra2/config.mk
arch/arm/cpu/armv7/tegra2/funcmux.c
arch/arm/cpu/armv7/tegra2/usb.c
arch/arm/cpu/ixp/start.S
arch/arm/cpu/lh7a40x/start.S
arch/arm/cpu/pxa/start.S
arch/arm/cpu/s3c44b0/start.S
arch/arm/cpu/sa1100/start.S
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/i2c.h
arch/arm/include/asm/arch-at91/at91_pio.h
arch/arm/include/asm/arch-exynos/cpu.h
arch/arm/include/asm/arch-exynos/ehci.h [moved from arch/arm/include/asm/arch-exynos/ehci-s5p.h with 90% similarity]
arch/arm/include/asm/arch-exynos/periph.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/pinmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/power.h
arch/arm/include/asm/arch-exynos/system.h
arch/arm/include/asm/arch-kirkwood/config.h
arch/arm/include/asm/arch-kirkwood/mpp.h
arch/arm/include/asm/arch-kirkwood/spi.h
arch/arm/include/asm/arch-mx28/regs-common.h
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
arch/arm/include/asm/arch-mx5/imx-regs.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6x_pins.h
arch/arm/include/asm/arch-omap3/cpu.h
arch/arm/include/asm/arch-omap3/sys_proto.h
arch/arm/include/asm/arch-omap4/clocks.h
arch/arm/include/asm/arch-omap4/cpu.h
arch/arm/include/asm/arch-omap4/omap.h
arch/arm/include/asm/arch-omap4/sys_proto.h
arch/arm/include/asm/arch-omap5/clocks.h
arch/arm/include/asm/arch-omap5/cpu.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/arch-omap5/sys_proto.h
arch/arm/include/asm/arch-s5pc1xx/cpu.h
arch/arm/include/asm/arch-spear/clk.h [moved from board/avionic-design/common/tamonten.h with 69% similarity]
arch/arm/include/asm/arch-spear/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-spear/hardware.h
arch/arm/include/asm/arch-spear/spr_defs.h
arch/arm/include/asm/arch-spear/spr_gpt.h
arch/arm/include/asm/arch-spear/spr_misc.h
arch/arm/include/asm/arch-spear/spr_nand.h [deleted file]
arch/arm/include/asm/arch-spear/spr_ssp.h [moved from board/avionic-design/plutux/plutux.c with 60% similarity]
arch/arm/include/asm/arch-spear/spr_syscntl.h
arch/arm/include/asm/arch-spear/spr_xloader_table.h [deleted file]
arch/arm/include/asm/arch-tegra2/clock.h
arch/arm/include/asm/arch-tegra2/funcmux.h
arch/arm/include/asm/arch-tegra2/gpio.h
arch/arm/include/asm/arch-tegra2/pinmux.h
arch/arm/include/asm/arch-tegra2/tegra2.h
arch/arm/include/asm/arch-tegra2/tegra_spi.h [moved from arch/arm/include/asm/arch-tegra2/tegra2_spi.h with 95% similarity]
arch/arm/include/asm/arch-tegra2/uart-spi-switch.h
arch/arm/include/asm/emif.h
arch/arm/include/asm/omap_common.h
arch/arm/include/asm/u-boot-arm.h
arch/arm/lib/board.c
arch/arm/lib/cache-cp15.c
arch/arm/lib/eabi_compat.c
arch/blackfin/include/asm/bfin_logo_230x230_gzip.h [moved from arch/blackfin/include/asm/bfin_logo_230x230.h with 100% similarity]
arch/blackfin/include/asm/bfin_logo_230x230_lzma.h [new file with mode: 0644]
arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h [moved from arch/blackfin/include/asm/bfin_logo_rgb565_230x230.h with 100% similarity]
arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h [new file with mode: 0644]
arch/nds32/cpu/n1213/ag101/cpu.c
arch/nds32/cpu/n1213/ag102/cpu.c
arch/nds32/lib/Makefile
arch/nds32/lib/cache.c [new file with mode: 0644]
arch/nios2/lib/board.c
arch/powerpc/cpu/mpc83xx/Makefile
arch/powerpc/cpu/mpc83xx/serdes.c
arch/powerpc/cpu/mpc85xx/Makefile
arch/powerpc/cpu/mpc85xx/cmd_errata.c
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/cpu_init_early.c
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/p2041_serdes.c
arch/powerpc/cpu/mpc85xx/release.S
arch/powerpc/cpu/mpc85xx/start.S
arch/powerpc/cpu/mpc8xx/cpu.c
arch/powerpc/cpu/mpc8xxx/cpu.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
arch/powerpc/include/asm/io.h
arch/powerpc/include/asm/processor.h
board/AndesTech/adp-ag101/README [moved from doc/README.ag101 with 100% similarity]
board/BuS/vl_ma2sc/Makefile [moved from board/spear/spear310/config.mk with 54% similarity]
board/BuS/vl_ma2sc/vl_ma2sc.c [new file with mode: 0644]
board/LaCie/common/common.c
board/LaCie/common/common.h
board/LaCie/edminiv2/edminiv2.c
board/LaCie/net2big_v2/net2big_v2.c
board/LaCie/netspace_v2/netspace_v2.c
board/Marvell/db64360/README [moved from doc/README.db64360 with 100% similarity]
board/Marvell/db64460/README [moved from doc/README.db64460 with 100% similarity]
board/Marvell/dreamplug/dreamplug.c
board/Marvell/guruplug/guruplug.c
board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
board/Marvell/openrd/openrd.c
board/Marvell/rd6281a/rd6281a.c
board/Marvell/sheevaplug/sheevaplug.c
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board/Seagate/dockstar/dockstar.c
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board/alphaproject/ap_sh4a_4a/ap_sh4a_4a.c
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board/amcc/ocotea/README.ocotea [moved from doc/README.ocotea with 100% similarity]
board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot [moved from doc/README.ocotea-PIBS-to-U-Boot with 100% similarity]
board/armltd/integrator/README [moved from doc/README-integrator with 100% similarity]
board/atmel/at91sam9260ek/partition.c
board/atmel/at91sam9261ek/partition.c
board/atmel/at91sam9263ek/at91sam9263ek.c
board/atmel/at91sam9263ek/partition.c
board/atmel/at91sam9rlek/partition.c
board/avionic-design/common/tamonten.c
board/avionic-design/dts/tegra2-medcom.dts [new file with mode: 0644]
board/avionic-design/dts/tegra2-plutux.dts [new file with mode: 0644]
board/avionic-design/dts/tegra2-tec.dts [new file with mode: 0644]
board/avionic-design/medcom/Makefile
board/avionic-design/plutux/Makefile
board/avionic-design/tec/Makefile [new file with mode: 0644]
board/bc3450/cmd_bc3450.c
board/bf527-ezkit/video.c
board/bf548-ezkit/video.c
board/buffalo/lsxl/Makefile [moved from board/spear/spear320/config.mk with 52% similarity]
board/buffalo/lsxl/kwbimage-lschl.cfg [new file with mode: 0644]
board/buffalo/lsxl/kwbimage-lsxhl.cfg [new file with mode: 0644]
board/buffalo/lsxl/lsxl.c [new file with mode: 0644]
board/buffalo/lsxl/lsxl.h [new file with mode: 0644]
board/cloudengines/pogo_e02/pogo_e02.c
board/cm-bf548/video.c
board/cm_t35/cm_t35.c
board/cm_t35/eeprom.c
board/cm_t35/eeprom.h
board/cmi/README [moved from doc/README.cmi with 100% similarity]
board/cobra5272/README [moved from doc/README.COBRA5272 with 100% similarity]
board/compal/dts/tegra2-paz00.dts [new file with mode: 0644]
board/compal/paz00/paz00.c
board/compulab/dts/tegra2-trimslice.dts [new file with mode: 0644]
board/compulab/trimslice/Makefile [new file with mode: 0644]
board/compulab/trimslice/trimslice.c [new file with mode: 0644]
board/d-link/dns325/dns325.c
board/davinci/da8xxevm/README.hawkboard [moved from doc/README.hawkboard with 100% similarity]
board/dnp5370/README [moved from doc/README.dnp5370 with 100% similarity]
board/efikamx/Makefile
board/enbw/enbw_cmc/enbw_cmc.c
board/esg/ima3-mx53/Makefile
board/evb64260/README [moved from doc/README.evb64260 with 100% similarity]
board/evb64260/README.EVB-64260-750CX [moved from doc/README.EVB-64260-750CX with 100% similarity]
board/fads/README [moved from doc/README.fads with 100% similarity]
board/freescale/bsc9131rdb/Makefile [moved from board/spear/spear600/config.mk with 51% similarity]
board/freescale/bsc9131rdb/README [new file with mode: 0644]
board/freescale/bsc9131rdb/bsc9131rdb.c [new file with mode: 0644]
board/freescale/bsc9131rdb/ddr.c [new file with mode: 0644]
board/freescale/bsc9131rdb/law.c [new file with mode: 0644]
board/freescale/bsc9131rdb/tlb.c [new file with mode: 0644]
board/freescale/common/fman.c
board/freescale/common/fman.h
board/freescale/m52277evb/README [moved from doc/README.m52277evb with 100% similarity]
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board/freescale/mpc7448hpc2/README [moved from doc/README.mpc7448hpc2 with 100% similarity]
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board/freescale/mx51evk/Makefile
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board/freescale/mx53smd/Makefile
board/freescale/mx6qarm2/Makefile
board/freescale/mx6qarm2/imximage.cfg
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board/freescale/mx6qsabrelite/imximage.cfg
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board/freescale/p1010rdb/README [new file with mode: 0644]
board/freescale/p1010rdb/ddr.c
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board/ti/am335x/evm.c
board/ti/beagle/beagle.c
board/ti/omap5_evm/mux_data.h
board/ti/omap730p2/README.omap730p2 [moved from doc/README.omap730p2 with 100% similarity]
board/ti/panda/panda_mux_data.h
board/ti/sdp4430/sdp4430_mux_data.h
board/timll/devkit8000/README [moved from doc/README.timll with 100% similarity]
board/tqc/tqm8260/README [moved from doc/README.TQM8260 with 100% similarity]
board/ttcontrol/vision2/Makefile
board/xes/xpedite1000/README [moved from doc/README.xpedite1k with 100% similarity]
board/zeus/README [moved from doc/README.zeus with 100% similarity]
boards.cfg
common/Makefile
common/cmd_pxe.c
common/cmd_sf.c
common/env_common.c
common/env_embedded.c
common/env_mmc.c
common/lcd.c
common/usb.c
common/usb_storage.c
config.mk
doc/README.OXC [deleted file]
doc/README.Sandpoint8240 [deleted file]
doc/README.amigaone [deleted file]
doc/README.enetaddr
doc/README.link-local
doc/README.mpc85xx [new file with mode: 0644]
doc/README.mx28_common
doc/README.mx28evk
doc/README.p4080ds [deleted file]
doc/README.qemu_mips [deleted file]
doc/README.spear
doc/README.switch_config [new file with mode: 0644]
doc/kwboot.1 [new file with mode: 0644]
drivers/block/sata_sil.c
drivers/gpio/Makefile
drivers/gpio/at91_gpio.c
drivers/gpio/spear_gpio.c [new file with mode: 0644]
drivers/gpio/tegra_gpio.c [moved from drivers/gpio/tegra2_gpio.c with 99% similarity]
drivers/i2c/designware_i2c.c
drivers/i2c/mxc_i2c.c
drivers/i2c/mxs_i2c.c
drivers/i2c/omap24xx_i2c.c
drivers/mmc/Makefile
drivers/mmc/fsl_esdhc.c
drivers/mmc/mmc.c
drivers/mmc/tegra_mmc.c [moved from drivers/mmc/tegra2_mmc.c with 99% similarity]
drivers/mmc/tegra_mmc.h [moved from drivers/mmc/tegra2_mmc.h with 97% similarity]
drivers/mtd/Makefile
drivers/mtd/nand/Makefile
drivers/mtd/nand/fsmc_nand.c [new file with mode: 0644]
drivers/mtd/nand/spr_nand.c [deleted file]
drivers/mtd/spi/eon.c
drivers/mtd/spi/macronix.c
drivers/mtd/spi/ramtron.c
drivers/mtd/spi/spansion.c
drivers/mtd/spi/spi_flash.c
drivers/mtd/spi/spi_flash_internal.h
drivers/mtd/spi/sst.c
drivers/mtd/spi/stmicro.c
drivers/mtd/spi/winbond.c
drivers/mtd/st_smi.c [moved from drivers/mtd/spr_smi.c with 62% similarity]
drivers/net/bfin_mac.c
drivers/net/davinci_emac.c
drivers/net/designware.c
drivers/net/designware.h
drivers/net/fec_mxc.c
drivers/net/fm/eth.c
drivers/net/phy/micrel.c
drivers/net/phy/phy.c
drivers/net/sh_eth.c
drivers/net/sh_eth.h
drivers/net/tsec.c
drivers/net/xilinx_axi_emac.c
drivers/net/xilinx_ll_temac.c
drivers/rtc/m41t62.c
drivers/spi/Makefile
drivers/spi/kirkwood_spi.c
drivers/spi/tegra_spi.c [moved from drivers/spi/tegra2_spi.c with 95% similarity]
drivers/usb/eth/asix.c
drivers/usb/eth/smsc95xx.c
drivers/usb/host/Makefile
drivers/usb/host/ehci-atmel.c [new file with mode: 0644]
drivers/usb/host/ehci-exynos.c [moved from drivers/usb/host/ehci-s5p.c with 79% similarity]
drivers/usb/host/ehci-hcd.c
drivers/usb/host/ehci-omap.c
drivers/usb/host/ehci-tegra.c
drivers/usb/musb/musb_core.h
drivers/video/Makefile
drivers/video/cfb_console.c
drivers/video/da8xx-fb.c
drivers/video/exynos_fb.c
drivers/video/ipu_common.c
drivers/video/ipu_disp.c
drivers/video/ipu_regs.h
dts/Makefile
fs/ext2/ext2fs.c
include/addr_map.h
include/common.h
include/configs/BSC9131RDB.h [new file with mode: 0644]
include/configs/MPC8323ERDB.h
include/configs/MPC8349EMDS.h
include/configs/MPC8349ITX.h
include/configs/MPC8360EMDS.h
include/configs/MPC8360ERDK.h
include/configs/MPC8536DS.h
include/configs/P1022DS.h
include/configs/P1023RDS.h
include/configs/P2020COME.h
include/configs/P2020DS.h
include/configs/P2041RDB.h
include/configs/at91sam9260ek.h
include/configs/at91sam9261ek.h
include/configs/at91sam9263ek.h
include/configs/at91sam9m10g45ek.h
include/configs/at91sam9rlek.h
include/configs/bf527-ezkit.h
include/configs/bf548-ezkit.h
include/configs/cm-bf548.h
include/configs/cm_t35.h
include/configs/corenet_ds.h
include/configs/enbw_cmc.h
include/configs/flea3.h
include/configs/harmony.h
include/configs/hawkboard.h
include/configs/imx31_phycore.h
include/configs/km/km_arm.h
include/configs/km_kirkwood.h
include/configs/lacie_kw.h
include/configs/lsxl.h [new file with mode: 0644]
include/configs/m28evk.h
include/configs/medcom.h
include/configs/mgcoge3un.h [deleted file]
include/configs/mx28evk.h
include/configs/mx35pdk.h
include/configs/mx51evk.h
include/configs/mx53ard.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx53smd.h
include/configs/mx6qarm2.h
include/configs/mx6qsabrelite.h
include/configs/nios2-generic.h
include/configs/omap3_beagle.h
include/configs/omap3_evm.h
include/configs/omap4_common.h
include/configs/omap5_evm.h
include/configs/paz00.h
include/configs/plutux.h
include/configs/portl2.h [deleted file]
include/configs/sbc8349.h
include/configs/seaboard.h
include/configs/smdk5250.h
include/configs/spear-common.h
include/configs/spear3xx_evb.h [moved from include/configs/spear3xx.h with 72% similarity]
include/configs/spear6xx_evb.h [moved from include/configs/spear6xx.h with 74% similarity]
include/configs/tec.h [new file with mode: 0644]
include/configs/tegra2-common-post.h [new file with mode: 0644]
include/configs/tegra2-common.h
include/configs/tk71.h [new file with mode: 0644]
include/configs/trimslice.h [new file with mode: 0644]
include/configs/ventana.h
include/configs/vision2.h
include/configs/vl_ma2sc.h [new file with mode: 0644]
include/configs/vme8349.h
include/configs/whistler.h [new file with mode: 0644]
include/configs/zipitz2.h
include/linux/mtd/fsmc_nand.h [new file with mode: 0644]
include/linux/mtd/st_smi.h [moved from arch/arm/include/asm/arch-spear/spr_smi.h with 95% similarity]
include/net.h
include/netdev.h
include/usb.h
lib/Makefile
lib/addr_map.c
lib/rand.c [moved from board/avionic-design/medcom/medcom.c with 62% similarity]
mkconfig
net/Makefile
net/arp.c
net/bootp.c
net/eth.c
net/link_local.c
net/net.c
net/net_rand.c [deleted file]
net/net_rand.h
net/nfs.c
net/tftp.c
tools/.gitignore
tools/Makefile
tools/kwboot.c [new file with mode: 0644]
tools/mingw_support.h
tools/mkenvimage.c

index e55893b..fd0c65c 100644 (file)
@@ -21,6 +21,8 @@ Poonam Aggrwal <poonam.aggrwal@freescale.com>
 
        P2020RDB        P2020
 
+       BSC9131RDB      BSC9131
+
 Greg Allen <gallen@arlut.utexas.edu>
 
        UTX8245         MPC8245
@@ -740,6 +742,9 @@ Sergey Lapin <slapin@ossfans.org>
 Valentin Longchamp <valentin.longchamp@keymile.com>
 
        km_kirkwood     ARM926EJS (Kirkwood SoC)
+       kmnusa          ARM926EJS (Kirkwood SoC)
+       mgcoge3un       ARM926EJS (Kirkwood SoC)
+       kmcoge5un       ARM926EJS (Kirkwood SoC)
        portl2          ARM926EJS (Kirkwood SoC)
 
 Nishanth Menon <nm@ti.com>
@@ -808,6 +813,7 @@ Thierry Reding <thierry.reding@avionic-design.de>
 
        plutux          Tegra2 (ARM7 & A9 Dual Core)
        medcom          Tegra2 (ARM7 & A9 Dual Core)
+       tec             Tegra2 (ARM7 & A9 Dual Core)
 
 Christian Riesch <christian.riesch@omicron.at>
 Manfred Rudigier <manfred.rudigier@omicron.at>
@@ -845,12 +851,12 @@ Steve Sakoman <sakoman@gmail.com>
 Jens Scharsig <esw@bus-elektronik.de>
 
        eb_cpux9k2      ARM920T (AT91RM9200 SoC)
+       vl_ma2sc        ARM926EJS (AT91SAM9263 SoC)
 
 Heiko Schocher <hs@denx.de>
 
        enbw_cmc        ARM926EJS (AM1808 SoC)
        magnesium       i.MX27
-       mgcoge3un       ARM926EJS (Kirkwood SoC)
 
 Michael Schwingen <michael@schwingen.org>
 
@@ -904,6 +910,11 @@ Prafulla Wadaskar <prafulla@marvell.com>
        rd6281a         ARM926EJS (Kirkwood SoC)
        sheevaplug      ARM926EJS (Kirkwood SoC)
 
+Michael Walle <michael@walle.cc>
+
+       lschlv2         ARM926EJS (Kirkwood SoC)
+       lsxhl           ARM926EJS (Kirkwood SoC)
+
 Tom Warren <twarren@nvidia.com>
 
        harmony         Tegra2 (ARM7 & A9 Dual Core)
@@ -914,6 +925,8 @@ Stephen Warren <swarren@nvidia.com>
 
        ventana         Tegra2 (ARM7 & A9 Dual Core)
        paz00           Tegra2 (ARM7 & A9 Dual Core)
+       trimslice       Tegra2 (ARM7 & A9 Dual Core)
+       whistler        Tegra2 (ARM7 & A9 Dual Core)
 
 Thomas Weber <weber@corscience.de>
 
index 0197239..eb37ea1 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -22,8 +22,8 @@
 #
 
 VERSION = 2012
-PATCHLEVEL = 04
-SUBLEVEL = 01
+PATCHLEVEL = 07
+SUBLEVEL =
 EXTRAVERSION =
 ifneq "$(SUBLEVEL)" ""
 U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
@@ -456,6 +456,22 @@ $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
                elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
                        -o $(obj)u-boot.sb
 
+# On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
+# Both images are created using mkimage (crc etc), so that the ROM
+# bootloader can check its integrity. Padding needs to be done to the
+# SPL image (with mkimage header) and not the binary. Otherwise the resulting image
+# which is loaded/copied by the ROM bootloader to SRAM doesn't fit.
+# The resulting image containing both U-Boot images is called u-boot.spr
+$(obj)u-boot.spr:      $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
+               $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
+               -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \
+               -d $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl.img
+               tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \
+                       of=$(obj)spl/u-boot-spl-pad.img 2>/dev/null
+               dd if=$(obj)spl/u-boot-spl.img of=$(obj)spl/u-boot-spl-pad.img \
+                       conv=notrunc 2>/dev/null
+               cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@
+
 ifeq ($(CONFIG_SANDBOX),y)
 GEN_UBOOT = \
                cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
@@ -601,7 +617,7 @@ $(obj)lib/asm-offsets.s:    $(obj)include/autoconf.mk.dep \
 
 $(obj)include/generated/asm-offsets.h: $(obj)include/autoconf.mk.dep \
        $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
-       @echo Generating $@
+       @$(XECHO) Generating $@
        tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@
 
 $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s:  $(obj)include/autoconf.mk.dep
@@ -775,7 +791,8 @@ clobber:    tidy
        @rm -f $(obj)u-boot.ais
        @rm -f $(obj)u-boot.dtb
        @rm -f $(obj)u-boot.sb
-       @rm -f $(obj)tools/inca-swap-bytes
+       @rm -f $(obj)u-boot.spr
+       @rm -f $(obj)tools/xway-swap-bytes
        @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
        @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
        @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
diff --git a/README b/README
index 67dc444..fb9d904 100644 (file)
--- a/README
+++ b/README
@@ -374,6 +374,15 @@ The following options need to be configured:
                Defines the string to utilize when trying to match PCIe device
                tree nodes for the given platform.
 
+               CONFIG_SYS_PPC_E500_DEBUG_TLB
+
+               Enables a temporary TLB entry to be used during boot to work
+               around limitations in e500v1 and e500v2 external debugger
+               support. This reduces the portions of the boot code where
+               breakpoints and single stepping do not work.  The value of this
+               symbol should be set to the TLB1 entry to be used for this
+               purpose.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -2140,6 +2149,13 @@ The following options need to be configured:
 
                Timeout waiting for an ARP reply in milliseconds.
 
+               CONFIG_NFS_TIMEOUT
+
+               Timeout in milliseconds used in NFS protocol.
+               If you encounter "ERROR: Cannot umount" in nfs command,
+               try longer timeout such as
+               #define CONFIG_NFS_TIMEOUT 10000UL
+
 - Command Interpreter:
                CONFIG_AUTO_COMPLETE
 
@@ -2220,6 +2236,20 @@ The following options need to be configured:
                the environment like the "source" command or the
                boot command first.
 
+               CONFIG_ENV_VARS_UBOOT_CONFIG
+
+               Define this in order to add variables describing the
+               U-Boot build configuration to the default environment.
+               These will be named arch, cpu, board, vendor, and soc.
+
+               Enabling this option will cause the following to be defined:
+
+               - CONFIG_SYS_ARCH
+               - CONFIG_SYS_CPU
+               - CONFIG_SYS_BOARD
+               - CONFIG_SYS_VENDOR
+               - CONFIG_SYS_SOC
+
 - DataFlash Support:
                CONFIG_HAS_DATAFLASH
 
index f72bab6..b98e3d9 100644 (file)
@@ -95,7 +95,7 @@ void flush_dcache_all(void)
        asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-static inline int bad_cache_range(unsigned long start, unsigned long stop)
+static int check_cache_range(unsigned long start, unsigned long stop)
 {
        int ok = 1;
 
@@ -114,7 +114,7 @@ static inline int bad_cache_range(unsigned long start, unsigned long stop)
 
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-       if (bad_cache_range(start, stop))
+       if (!check_cache_range(start, stop))
                return;
 
        while (start < stop) {
@@ -125,7 +125,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
 
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-       if (bad_cache_range(start, stop))
+       if (!check_cache_range(start, stop))
                return;
 
        while (start < stop) {
index c0db96c..2483c63 100644 (file)
@@ -251,10 +251,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 #endif /* #ifndef CONFIG_SPL_BUILD */
 
 /*
index 848144a..d613641 100644 (file)
@@ -351,11 +351,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
-
+       b       clbss_l
+clbss_e:
 #ifndef CONFIG_NAND_SPL
        bl coloured_LED_init
        bl red_led_on
index 540e3c2..3b97e80 100644 (file)
@@ -228,10 +228,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
        bl coloured_LED_init
        bl red_led_on
index 8c5612c..9b8604e 100644 (file)
@@ -271,10 +271,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
        bl coloured_LED_init
        bl red_led_on
index dbb93ef..1a54416 100644 (file)
@@ -265,10 +265,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
        bl coloured_LED_init
        bl red_led_on
index 5b39484..0e45426 100644 (file)
@@ -523,9 +523,8 @@ VTPLock:
 
        ldr     r6, DDRVTPR
        ldr     r7, [r6]
-       and     r7, r7, $0x1f
-       and     r8, r7, $0x3e0
-       orr     r8, r7, r8
+       mov     r8, r7, LSL #32-10
+       mov     r8, r8, LSR #32-10        /* grab low 10 bits  */
        ldr     r7, VTP_RECAL
        orr     r8, r7, r8
        ldr     r7, VTP_EN
@@ -644,7 +643,7 @@ VTP_LOCK_COUNT:
 VTP_MASK:
        .word   0xffffdfff
 VTP_RECAL:
-       .word   0x40000
+       .word   0x08000
 VTP_EN:
        .word   0x02000
 CFGTEST:
index 3da6c98..03eb2de 100644 (file)
@@ -31,7 +31,7 @@ static u32 kirkwood_variant(void)
 #define MPP_CTRL(i)    (KW_MPP_BASE + (i* 4))
 #define MPP_NR_REGS    (1 + MPP_MAX/8)
 
-void kirkwood_mpp_conf(u32 *mpp_list)
+void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save)
 {
        u32 mpp_ctrl[MPP_NR_REGS];
        unsigned int variant_mask;
@@ -52,6 +52,7 @@ void kirkwood_mpp_conf(u32 *mpp_list)
        while (*mpp_list) {
                unsigned int num = MPP_NUM(*mpp_list);
                unsigned int sel = MPP_SEL(*mpp_list);
+               unsigned int sel_save;
                int shift;
 
                if (num > MPP_MAX) {
@@ -66,6 +67,13 @@ void kirkwood_mpp_conf(u32 *mpp_list)
                }
 
                shift = (num & 7) << 2;
+
+               if (mpp_save) {
+                       sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf;
+                       *mpp_save = num | (sel_save << 8) | variant_mask;
+                       mpp_save++;
+               }
+
                mpp_ctrl[num / 8] &= ~(0xf << shift);
                mpp_ctrl[num / 8] |= sel << shift;
 
index a82ff25..ff25772 100644 (file)
@@ -153,7 +153,6 @@ int arch_misc_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_CPU_INIT
 int arch_cpu_init(void)
 {
        struct mx28_clkctrl_regs *clkctrl_regs =
@@ -187,7 +186,6 @@ int arch_cpu_init(void)
 
        return 0;
 }
-#endif
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
index 9fa5d29..e17a4d7 100644 (file)
@@ -82,10 +82,18 @@ uint32_t dram_vals[] = {
        0x00000000, 0x00010001
 };
 
+void __mx28_adjust_memory_params(uint32_t *dram_vals)
+{
+}
+void mx28_adjust_memory_params(uint32_t *dram_vals)
+       __attribute__((weak, alias("__mx28_adjust_memory_params")));
+
 void init_m28_200mhz_ddr2(void)
 {
        int i;
 
+       mx28_adjust_memory_params(dram_vals);
+
        for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
                writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
index f32ec4c..d06f03d 100644 (file)
@@ -25,16 +25,27 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS  := reset.o \
+COBJS-y        := cpu.o \
+          reset.o \
           timer.o
-SOBJS  :=
 
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(COBJS))
-SOBJS  := $(addprefix $(obj),$(SOBJS))
+ifdef CONFIG_SPL_BUILD
+COBJS-y        += spl.o spl_boot.o
+COBJS-$(CONFIG_SPEAR600) += spear600.o
+COBJS-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o
+COBJS-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o
+COBJS-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o
+endif
 
-$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
-       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+SRCS   := $(START:.o=.S) $(COBJS-y:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS-y))
+START  := $(addprefix $(obj),$(START))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):        $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
 
 #########################################################################
 
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
new file mode 100644 (file)
index 0000000..e299de3
--- /dev/null
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+
+int arch_cpu_init(void)
+{
+       struct misc_regs *const misc_p =
+           (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       u32 periph1_clken, periph_clk_cfg;
+
+       periph1_clken = readl(&misc_p->periph1_clken);
+
+#if defined(CONFIG_SPEAR3XX)
+       periph1_clken |= MISC_GPT2ENB;
+#elif defined(CONFIG_SPEAR600)
+       periph1_clken |= MISC_GPT3ENB;
+#endif
+
+#if defined(CONFIG_PL011_SERIAL)
+       periph1_clken |= MISC_UART0ENB;
+
+       periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
+       periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
+       periph_clk_cfg |= CONFIG_SPEAR_UART48M;
+       writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
+#endif
+#if defined(CONFIG_DESIGNWARE_ETH)
+       periph1_clken |= MISC_ETHENB;
+#endif
+#if defined(CONFIG_DW_UDC)
+       periph1_clken |= MISC_USBDENB;
+#endif
+#if defined(CONFIG_DW_I2C)
+       periph1_clken |= MISC_I2CENB;
+#endif
+#if defined(CONFIG_ST_SMI)
+       periph1_clken |= MISC_SMIENB;
+#endif
+#if defined(CONFIG_NAND_FSMC)
+       periph1_clken |= MISC_FSMCENB;
+#endif
+
+       writel(periph1_clken, &misc_p->periph1_clken);
+       return 0;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+#ifdef CONFIG_SPEAR300
+       printf("CPU:   SPEAr300\n");
+#elif defined(CONFIG_SPEAR310)
+       printf("CPU:   SPEAr310\n");
+#elif defined(CONFIG_SPEAR320)
+       printf("CPU:   SPEAr320\n");
+#elif defined(CONFIG_SPEAR600)
+       printf("CPU:   SPEAr600\n");
+#else
+#error CPU not supported in spear platform
+#endif
+       return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c
new file mode 100644 (file)
index 0000000..ff52131
--- /dev/null
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2000-2009
+ * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_defs.h>
+
+#define FALSE                          0
+#define TRUE                           (!FALSE)
+
+static void sel_1v8(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       u32 ddr1v8, ddr2v5;
+
+       ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+       ddr2v5 &= 0x8080ffc0;
+       ddr2v5 |= 0x78000003;
+       writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+       ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+       ddr1v8 &= 0x8080ffc0;
+       ddr1v8 |= 0x78000010;
+       writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+       while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
+               ;
+}
+
+static void sel_2v5(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       u32 ddr1v8, ddr2v5;
+
+       ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+       ddr1v8 &= 0x8080ffc0;
+       ddr1v8 |= 0x78000003;
+       writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+       ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+       ddr2v5 &= 0x8080ffc0;
+       ddr2v5 |= 0x78000010;
+       writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+       while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
+               ;
+}
+
+/*
+ * plat_ddr_init:
+ */
+void plat_ddr_init(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       u32 ddrpad;
+       u32 core3v3, ddr1v8, ddr2v5;
+
+       /* DDR pad register configurations */
+       ddrpad = readl(&misc_p->ddr_pad);
+       ddrpad &= ~DDR_PAD_CNF_MSK;
+
+#if (CONFIG_DDR_HCLK)
+       ddrpad |= 0xEAAB;
+#elif (CONFIG_DDR_2HCLK)
+       ddrpad |= 0xEAAD;
+#elif (CONFIG_DDR_PLL2)
+       ddrpad |= 0xEAAD;
+#endif
+       writel(ddrpad, &misc_p->ddr_pad);
+
+       /* Compensation register configurations */
+       core3v3 = readl(&misc_p->core_3v3_compensation);
+       core3v3 &= 0x8080ffe0;
+       core3v3 |= 0x78000002;
+       writel(core3v3, &misc_p->core_3v3_compensation);
+
+       ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
+       ddr1v8 &= 0x8080ffc0;
+       ddr1v8 |= 0x78000004;
+       writel(ddr1v8, &misc_p->ddr_1v8_compensation);
+
+       ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
+       ddr2v5 &= 0x8080ffc0;
+       ddr2v5 |= 0x78000004;
+       writel(ddr2v5, &misc_p->ddr_2v5_compensation);
+
+       if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
+               /* Software memory configuration */
+               if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
+                       sel_1v8();
+               else
+                       sel_2v5();
+       } else {
+               /* Hardware memory configuration */
+               if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
+                       sel_1v8();
+               else
+                       sel_2v5();
+       }
+}
+
+/*
+ * soc_init:
+ */
+void soc_init(void)
+{
+       /* Nothing to be done for SPEAr600 */
+}
+
+/*
+ * xxx_boot_selected:
+ *
+ * return TRUE if the particular booting option is selected
+ * return FALSE otherwise
+ */
+static u32 read_bootstrap(void)
+{
+       return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
+               & CONFIG_SPEAR_BOOTSTRAPMASK;
+}
+
+int snor_boot_selected(void)
+{
+       u32 bootstrap = read_bootstrap();
+
+       if (SNOR_BOOT_SUPPORTED) {
+               /* Check whether SNOR boot is selected */
+               if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
+                       CONFIG_SPEAR_ONLYSNORBOOT)
+                       return TRUE;
+
+               if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+                       CONFIG_SPEAR_NORNAND8BOOT)
+                       return TRUE;
+
+               if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+                       CONFIG_SPEAR_NORNAND16BOOT)
+                       return TRUE;
+       }
+
+       return FALSE;
+}
+
+int nand_boot_selected(void)
+{
+       u32 bootstrap = read_bootstrap();
+
+       if (NAND_BOOT_SUPPORTED) {
+               /* Check whether NAND boot is selected */
+               if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+                       CONFIG_SPEAR_NORNAND8BOOT)
+                       return TRUE;
+
+               if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
+                       CONFIG_SPEAR_NORNAND16BOOT)
+                       return TRUE;
+       }
+
+       return FALSE;
+}
+
+int pnor_boot_selected(void)
+{
+       /* Parallel NOR boot is not selected in any SPEAr600 revision */
+       return FALSE;
+}
+
+int usb_boot_selected(void)
+{
+       u32 bootstrap = read_bootstrap();
+
+       if (USB_BOOT_SUPPORTED) {
+               /* Check whether USB boot is selected */
+               if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
+                       return TRUE;
+       }
+
+       return FALSE;
+}
+
+int tftp_boot_selected(void)
+{
+       /* TFTP boot is not selected in any SPEAr600 revision */
+       return FALSE;
+}
+
+int uart_boot_selected(void)
+{
+       /* UART boot is not selected in any SPEAr600 revision */
+       return FALSE;
+}
+
+int spi_boot_selected(void)
+{
+       /* SPI boot is not selected in any SPEAr600 revision */
+       return FALSE;
+}
+
+int i2c_boot_selected(void)
+{
+       /* I2C boot is not selected in any SPEAr600 revision */
+       return FALSE;
+}
+
+int mmc_boot_selected(void)
+{
+       return FALSE;
+}
+
+void plat_late_init(void)
+{
+       spear_late_init();
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
new file mode 100644 (file)
index 0000000..48e6efb
--- /dev/null
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_syscntl.h>
+
+inline void hang(void)
+{
+       serial_puts("### ERROR ### Please RESET the board ###\n");
+       for (;;)
+               ;
+}
+
+static void ddr_clock_init(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       u32 clkenb, ddrpll;
+
+       clkenb = readl(&misc_p->periph1_clken);
+       clkenb &= ~PERIPH_MPMCMSK;
+       clkenb |= PERIPH_MPMC_WE;
+
+       /* Intentionally done twice */
+       writel(clkenb, &misc_p->periph1_clken);
+       writel(clkenb, &misc_p->periph1_clken);
+
+       ddrpll = readl(&misc_p->pll_ctr_reg);
+       ddrpll &= ~MEM_CLK_SEL_MSK;
+#if (CONFIG_DDR_HCLK)
+       ddrpll |= MEM_CLK_HCLK;
+#elif (CONFIG_DDR_2HCLK)
+       ddrpll |= MEM_CLK_2HCLK;
+#elif (CONFIG_DDR_PLL2)
+       ddrpll |= MEM_CLK_PLL2;
+#else
+#error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
+#endif
+       writel(ddrpll, &misc_p->pll_ctr_reg);
+
+       writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
+                       &misc_p->periph1_clken);
+}
+
+static void mpmc_init_values(void)
+{
+       u32 i;
+       u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+       u32 *mpmc_val_p = &mpmc_conf_vals[0];
+
+       for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
+               writel(*mpmc_val_p, mpmc_reg_p);
+
+       mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
+
+       /*
+        * MPMC controller start
+        * MPMC waiting for DLLLOCKREG high
+        */
+       writel(0x01000100, &mpmc_reg_p[7]);
+
+       while (!(readl(&mpmc_reg_p[3]) & 0x10000))
+               ;
+}
+
+static void mpmc_init(void)
+{
+       /* Clock related settings for DDR */
+       ddr_clock_init();
+
+       /*
+        * DDR pad register bits are different for different SoCs
+        * Compensation values are also handled separately
+        */
+       plat_ddr_init();
+
+       /* Initialize mpmc register values */
+       mpmc_init_values();
+}
+
+static void pll_init(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+       /* Initialize PLLs */
+       writel(FREQ_332, &misc_p->pll1_frq);
+       writel(0x1C0A, &misc_p->pll1_cntl);
+       writel(0x1C0E, &misc_p->pll1_cntl);
+       writel(0x1C06, &misc_p->pll1_cntl);
+       writel(0x1C0E, &misc_p->pll1_cntl);
+
+       writel(FREQ_332, &misc_p->pll2_frq);
+       writel(0x1C0A, &misc_p->pll2_cntl);
+       writel(0x1C0E, &misc_p->pll2_cntl);
+       writel(0x1C06, &misc_p->pll2_cntl);
+       writel(0x1C0E, &misc_p->pll2_cntl);
+
+       /* wait for pll locks */
+       while (!(readl(&misc_p->pll1_cntl) & 0x1))
+               ;
+       while (!(readl(&misc_p->pll2_cntl) & 0x1))
+               ;
+}
+
+static void mac_init(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+       writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
+                       &misc_p->periph1_clken);
+
+       writel(SYNTH23, &misc_p->gmac_synth_clk);
+
+       switch (get_socrev()) {
+       case SOC_SPEAR600_AA:
+       case SOC_SPEAR600_AB:
+       case SOC_SPEAR600_BA:
+       case SOC_SPEAR600_BB:
+       case SOC_SPEAR600_BC:
+       case SOC_SPEAR600_BD:
+               writel(0x0, &misc_p->gmac_ctr_reg);
+               break;
+
+       case SOC_SPEAR300:
+       case SOC_SPEAR310:
+       case SOC_SPEAR320:
+               writel(0x4, &misc_p->gmac_ctr_reg);
+               break;
+       }
+
+       writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
+                       &misc_p->periph1_clken);
+
+       writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
+                       &misc_p->periph1_rst);
+       writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
+                       &misc_p->periph1_rst);
+}
+
+static void sys_init(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       struct syscntl_regs *syscntl_p =
+               (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+       /* Set system state to SLOW */
+       writel(SLOW, &syscntl_p->scctrl);
+       writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
+
+       /* Initialize PLLs */
+       pll_init();
+
+       /*
+        * Ethernet configuration
+        * To be done only if the tftp boot is not selected already
+        * Boot code ensures the correct configuration in tftp booting
+        */
+       if (!tftp_boot_selected())
+               mac_init();
+
+       writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
+       writel(0x555, &misc_p->amba_clk_cfg);
+
+       writel(NORMAL, &syscntl_p->scctrl);
+
+       /* Wait for system to switch to normal mode */
+       while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
+               != NORMAL)
+               ;
+}
+
+/*
+ * get_socrev
+ *
+ * Get SoC Revision.
+ * @return SOC_SPEARXXX
+ */
+int get_socrev(void)
+{
+#if defined(CONFIG_SPEAR600)
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       u32 soc_id = readl(&misc_p->soc_core_id);
+       u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
+       u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
+
+       if ((pri_socid == 'B') && (sec_socid == 'B'))
+               return SOC_SPEAR600_BB;
+       else if ((pri_socid == 'B') && (sec_socid == 'C'))
+               return SOC_SPEAR600_BC;
+       else if ((pri_socid == 'B') && (sec_socid == 'D'))
+               return SOC_SPEAR600_BD;
+       else if (soc_id == 0)
+               return SOC_SPEAR600_BA;
+       else
+               return SOC_SPEAR_NA;
+#elif defined(CONFIG_SPEAR300)
+       return SOC_SPEAR300;
+#elif defined(CONFIG_SPEAR310)
+       return SOC_SPEAR310;
+#elif defined(CONFIG_SPEAR320)
+       return SOC_SPEAR320;
+#endif
+}
+
+void lowlevel_init(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+       const char *u_boot_rev = U_BOOT_VERSION;
+
+       /* Initialize PLLs */
+       sys_init();
+
+       /* Initialize UART */
+       serial_init();
+
+       /* Print U-Boot SPL version string */
+       serial_puts("\nU-Boot SPL ");
+       /* Avoid a second "U-Boot" coming from this string */
+       u_boot_rev = &u_boot_rev[7];
+       serial_puts(u_boot_rev);
+       serial_puts(" (");
+       serial_puts(U_BOOT_DATE);
+       serial_puts(" - ");
+       serial_puts(U_BOOT_TIME);
+       serial_puts(")\n");
+
+#if defined(CONFIG_OS_BOOT)
+       writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
+                       &misc_p->periph1_clken);
+#endif
+
+       /* Enable IPs (release reset) */
+       writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
+
+       /* Initialize MPMC */
+       serial_puts("Configure DDR\n");
+       mpmc_init();
+
+       /* SoC specific initialization */
+       soc_init();
+}
+
+void spear_late_init(void)
+{
+       struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+       writel(0x80000007, &misc_p->arb_icm_ml1);
+       writel(0x80000007, &misc_p->arb_icm_ml2);
+       writel(0x80000007, &misc_p->arb_icm_ml3);
+       writel(0x80000007, &misc_p->arb_icm_ml4);
+       writel(0x80000007, &misc_p->arb_icm_ml5);
+       writel(0x80000007, &misc_p->arb_icm_ml6);
+       writel(0x80000007, &misc_p->arb_icm_ml7);
+       writel(0x80000007, &misc_p->arb_icm_ml8);
+       writel(0x80000007, &misc_p->arb_icm_ml9);
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c
new file mode 100644 (file)
index 0000000..f2f9a49
--- /dev/null
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <image.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/arch/spr_defs.h>
+#include <linux/mtd/st_smi.h>
+
+static const char kernel_name[] = "Linux";
+static const char loader_name[] = "U-Boot";
+
+int image_check_header(image_header_t *hdr, const char *name)
+{
+       if (image_check_magic(hdr) &&
+           (!strncmp(image_get_name(hdr), name, strlen(name))) &&
+           image_check_hcrc(hdr)) {
+               return 1;
+       }
+       return 0;
+}
+
+int image_check_data(image_header_t *hdr)
+{
+       if (image_check_dcrc(hdr))
+               return 1;
+
+       return 0;
+}
+
+/*
+ * SNOR (Serial NOR flash) related functions
+ */
+void snor_init(void)
+{
+       struct smi_regs *const smicntl =
+               (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+
+       /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
+       writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+              &smicntl->smi_cr1);
+}
+
+static int snor_image_load(u8 *load_addr, void (**image_p)(void),
+                          const char *image_name)
+{
+       image_header_t *header;
+
+       /*
+        * Since calculating the crc in the SNOR flash does not
+        * work, we copy the image to the destination address
+        * minus the header size. And point the header to this
+        * new destination. This will not work for address 0
+        * of course.
+        */
+       header = (image_header_t *)load_addr;
+       memcpy((ulong *)(image_get_load(header) - sizeof(image_header_t)),
+              (const ulong *)load_addr,
+              image_get_data_size(header) + sizeof(image_header_t));
+       header = (image_header_t *)(image_get_load(header) -
+                                   sizeof(image_header_t));
+
+       if (image_check_header(header, image_name)) {
+               if (image_check_data(header)) {
+                       /* Jump to boot image */
+                       *image_p = (void *)image_get_load(header);
+                       return 1;
+               }
+       }
+
+       return 0;
+}
+
+static void boot_image(void (*image)(void))
+{
+       void (*funcp)(void) __noreturn = (void *)image;
+
+       (*funcp)();
+}
+
+/*
+ * spl_boot:
+ *
+ * All supported booting types of all supported SoCs are listed here.
+ * Generic readback APIs are provided for each supported booting type
+ * eg. nand_read_skip_bad
+ */
+u32 spl_boot(void)
+{
+       void (*image)(void);
+
+#ifdef CONFIG_SPEAR_USBTTY
+       plat_late_init();
+       return 1;
+#endif
+
+       /*
+        * All the supported booting devices are listed here. Each of
+        * the booting type supported by the platform would define the
+        * macro xxx_BOOT_SUPPORTED to TRUE.
+        */
+
+       if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
+               /* SNOR-SMI initialization */
+               snor_init();
+
+               serial_puts("Booting via SNOR\n");
+               /* Serial NOR booting */
+               if (1 == snor_image_load((u8 *)CONFIG_SYS_UBOOT_BASE,
+                                           &image, loader_name)) {
+                       /* Platform related late initialasations */
+                       plat_late_init();
+
+                       /* Jump to boot image */
+                       serial_puts("Jumping to U-Boot\n");
+                       boot_image(image);
+                       return 1;
+               }
+       }
+
+       if (NAND_BOOT_SUPPORTED && nand_boot_selected()) {
+               /* NAND booting */
+               /* Not ported from XLoader to SPL yet */
+               return 0;
+       }
+
+       if (PNOR_BOOT_SUPPORTED && pnor_boot_selected()) {
+               /* PNOR booting */
+               /* Not ported from XLoader to SPL yet */
+               return 0;
+       }
+
+       if (MMC_BOOT_SUPPORTED && mmc_boot_selected()) {
+               /* MMC booting */
+               /* Not ported from XLoader to SPL yet */
+               return 0;
+       }
+
+       if (SPI_BOOT_SUPPORTED && spi_boot_selected()) {
+               /* SPI booting */
+               /* Not supported for any platform as of now */
+               return 0;
+       }
+
+       if (I2C_BOOT_SUPPORTED && i2c_boot_selected()) {
+               /* I2C booting */
+               /* Not supported for any platform as of now */
+               return 0;
+       }
+
+       /*
+        * All booting types without memory are listed as below
+        * Control has to be returned to BootROM in case of all
+        * the following booting scenarios
+        */
+
+       if (USB_BOOT_SUPPORTED && usb_boot_selected()) {
+               plat_late_init();
+               return 1;
+       }
+
+       if (TFTP_BOOT_SUPPORTED && tftp_boot_selected()) {
+               plat_late_init();
+               return 1;
+       }
+
+       if (UART_BOOT_SUPPORTED && uart_boot_selected()) {
+               plat_late_init();
+               return 1;
+       }
+
+       /* Ideally, the control should not reach here. */
+       hang();
+}
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h128m8_3_266_cl5_async.c
new file mode 100644 (file)
index 0000000..5edc115
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+       0x00000001,
+       0x00000000,
+       0x01000000,
+       0x00000101,
+       0x00000001,
+       0x01000000,
+       0x00010001,
+       0x00000100,
+       0x00010001,
+       0x00000003,
+       0x01000201,
+       0x06000202,
+       0x06060106,
+       0x03050502,
+       0x03040404,
+       0x02020503,
+       0x02010106,
+       0x03000404,
+       0x02030202,
+       0x03000204,
+       0x0707073f,
+       0x07070707,
+       0x06060607,
+       0x06060606,
+       0x05050506,
+       0x05050505,
+       0x04040405,
+       0x04040404,
+       0x03030304,
+       0x03030303,
+       0x02020203,
+       0x02020202,
+       0x01010102,
+       0x01010101,
+       0x08080a01,
+       0x0000023f,
+       0x00040800,
+       0x00000000,
+       0x00000f02,
+       0x00001b1b,
+       0x7f000000,
+       0x005f0000,
+       0x1c040b6a,
+       0x00640064,
+       0x00640064,
+       0x00640064,
+       0x00000064,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x000007ff,
+       0x00000000,
+       0x47ec00c8,
+       0x00c8001f,
+       0x00000000,
+       0x0000cd98,
+       0x00000000,
+       0x03030100,
+       0x03030303,
+       0x03030303,
+       0x03030303,
+       0x00270000,
+       0x00250027,
+       0x00300000,
+       0x008900b7,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_333_cl5_psync.c
new file mode 100644 (file)
index 0000000..616b861
--- /dev/null
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+       0x00000001,
+       0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+       0x02020201,
+       0x02020202,
+#endif
+       0x01000000,
+       0x00000101,
+       0x00000101,
+       0x01000000,
+       0x00010001,
+       0x00000100,
+       0x01010001,
+       0x00000201,
+       0x01000101,
+       0x06000002,
+       0x06060106,
+       0x03050502,
+       0x03040404,
+       0x02020503,
+       0x02010106,
+       0x03000405,
+       0x03040202,
+       0x04000305,
+       0x0707073f,
+       0x07070707,
+       0x06060607,
+       0x06060606,
+       0x05050506,
+       0x05050505,
+       0x04040405,
+       0x04040404,
+       0x03030304,
+       0x03030303,
+       0x02020203,
+       0x02020202,
+       0x01010102,
+       0x01010101,
+       0x0a0a0a01,
+       0x0000023f,
+       0x00050a00,
+       0x11000000,
+       0x00001302,
+       0x00000A0A,
+       0x72000000,
+       0x00550000,
+       0x2b050e86,
+       0x00640064,
+       0x00640064,
+       0x00640064,
+       0x00000064,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00000a24,
+       0x43C20000,
+       0x5b1c00c8,
+       0x00c8002e,
+       0x00000000,
+       0x0001046b,
+       0x00000000,
+       0x03030100,
+       0x03030303,
+       0x03030303,
+       0x03030303,
+       0x00210000,
+       0x00010021,
+       0x00200000,
+       0x006c0090,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h32m16_37e_166_cl4_sync.c
new file mode 100644 (file)
index 0000000..b89f77d
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+       0x03030301,
+       0x03030303,
+       0x01000000,
+       0x00000101,
+       0x00000001,
+       0x01000000,
+       0x00010001,
+       0x00000100,
+       0x00010001,
+       0x00000003,
+       0x01000201,
+       0x06000202,
+       0x06060106,
+       0x03050502,
+       0x03040404,
+       0x02020503,
+       0x02010106,
+       0x03000404,
+       0x02020202,
+       0x03000203,
+       0x0707073f,
+       0x07070707,
+       0x06060607,
+       0x06060606,
+       0x05050506,
+       0x05050505,
+       0x04040405,
+       0x04040404,
+       0x03030304,
+       0x03030303,
+       0x02020203,
+       0x02020202,
+       0x01010102,
+       0x01010101,
+       0x08080a01,
+       0x0000023f,
+       0x00030600,
+       0x00000000,
+       0x00000a02,
+       0x00001c1c,
+       0x7f000000,
+       0x005f0000,
+       0x12030743,
+       0x00640064,
+       0x00640064,
+       0x00640064,
+       0x00000064,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x0000050e,
+       0x00000000,
+       0x2d8900c8,
+       0x00c80014,
+       0x00000000,
+       0x00008236,
+       0x00000000,
+       0x03030100,
+       0x03030303,
+       0x03030303,
+       0x03030303,
+       0x00400000,
+       0x003a0040,
+       0x00680000,
+       0x00d80120,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c b/arch/arm/cpu/arm926ejs/spear/spr600_mt47h64m16_3_333_cl5_psync.c
new file mode 100644 (file)
index 0000000..0c39cd1
--- /dev/null
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2000-2009
+ * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
+
+const u32 mpmc_conf_vals[CONFIG_SPEAR_MPMCREGS] = {
+#if (CONFIG_DDR_PLL2)
+       0x00000001,
+       0x00000000,
+#elif (CONFIG_DDR_2HCLK)
+       0x02020201,
+       0x02020202,
+#endif
+       0x01000000,
+       0x00000101,
+       0x00000101,
+       0x01000000,
+       0x00010001,
+       0x00000100,
+       0x01010001,
+       0x00000201,
+       0x01000101,
+       0x06000002,
+       0x06060106,
+       0x03050502,
+       0x03040404,
+       0x02020503,
+#ifdef CONFIG_X600
+       0x02030206,
+#else
+       0x02010106,
+#endif
+       0x03000405,
+       0x03040202,
+       0x04000305,
+       0x0707073f,
+       0x07070707,
+       0x06060607,
+       0x06060606,
+       0x05050506,
+       0x05050505,
+       0x04040405,
+       0x04040404,
+       0x03030304,
+       0x03030303,
+       0x02020203,
+       0x02020202,
+       0x01010102,
+       0x01010101,
+       0x0a0a0a01,
+       0x0000023f,
+       0x00050a00,
+       0x11000000,
+       0x00001302,
+       0x00000A0A,
+#ifdef CONFIG_X600
+       0x7f000000,
+       0x005c0000,
+#else
+       0x72000000,
+       0x00550000,
+#endif
+       0x2b050e86,
+       0x00640064,
+       0x00640064,
+       0x00640064,
+       0x00000064,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00200020,
+       0x00000a24,
+       0x43C20000,
+       0x5b1c00c8,
+       0x00c8002e,
+       0x00000000,
+       0x0001046b,
+       0x00000000,
+       0x03030100,
+       0x03030303,
+       0x03030303,
+       0x03030303,
+       0x00210000,
+       0x00010021,
+       0x00200000,
+       0x006c0090,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x003fffff,
+       0x003fffff,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000
+};
+#endif
diff --git a/arch/arm/cpu/arm926ejs/spear/start.S b/arch/arm/cpu/arm926ejs/spear/start.S
new file mode 100644 (file)
index 0000000..a103c0f
--- /dev/null
@@ -0,0 +1,122 @@
+/*
+ *  armboot - Startup Code for ARM926EJS CPU-core
+ *
+ *  Copyright (c) 2003  Texas Instruments
+ *
+ *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
+ *
+ *  Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ *  Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ *  Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ *  Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ *  Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+
+.globl _start
+_start:
+       b       reset
+       ldr     pc, _undefined_instruction
+       ldr     pc, _software_interrupt
+       ldr     pc, _prefetch_abort
+       ldr     pc, _data_abort
+       ldr     pc, _not_used
+       ldr     pc, _irq
+       ldr     pc, _fiq
+
+_undefined_instruction:
+_software_interrupt:
+_prefetch_abort:
+_data_abort:
+_not_used:
+_irq:
+_fiq:
+       .word infinite_loop
+
+infinite_loop:
+       b       infinite_loop
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * Below are the critical initializations already taken place in BootROM.
+ * So, these are not taken care in Xloader
+ * 1. Relocation to RAM
+ * 2. Initializing stacks
+ *
+ *************************************************************************
+ */
+
+/*
+ * the actual reset code
+ */
+
+reset:
+/*
+ * Xloader has to return back to BootROM in a few cases.
+ * eg. Ethernet boot, UART boot, USB boot
+ * Saving registers for returning back
+ */
+       stmdb   sp!, {r0-r12,r14}
+       bl      cpu_init_crit
+/*
+ * Clearing bss area is not done in Xloader.
+ * BSS area lies in the DDR location which is not yet initialized
+ * bss is assumed to be uninitialized.
+ */
+       bl      spl_boot
+       ldmia   sp!, {r0-r12,pc}
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+cpu_init_crit:
+       /*
+        * flush v4 I/D caches
+        */
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c7, 0   /* flush v3/v4 cache */
+       mcr     p15, 0, r0, c8, c7, 0   /* flush v4 TLB */
+
+       /*
+        * enable instruction cache
+        */
+       mrc     p15, 0, r0, c1, c0, 0
+       orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
+       mcr     p15, 0, r0, c1, c0, 0
+
+       /*
+        * Go setup Memory and board specific bits prior to relocation.
+        */
+       stmdb   sp!, {lr}
+       bl      lowlevel_init   /* go setup pll,mux,memory */
+       ldmia   sp!, {pc}
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
new file mode 100644 (file)
index 0000000..afd3381
--- /dev/null
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text   :
+       {
+               arch/arm/cpu/arm926ejs/spear/start.o    (.text)
+               *(.text)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+       . = ALIGN(4);
+       .data : {
+               *(.data)
+       }
+
+       . = ALIGN(4);
+       __u_boot_cmd_start = .;
+       .u_boot_cmd : { *(.u_boot_cmd) }
+       __u_boot_cmd_end = .;
+
+       . = ALIGN(4);
+
+       .rel.dyn : {
+               __rel_dyn_start = .;
+               *(.rel*)
+               __rel_dyn_end = .;
+       }
+
+       .dynsym : {
+               __dynsym_start = .;
+               *(.dynsym)
+       }
+
+       .bss : {
+               . = ALIGN(4);
+               __bss_start = .;
+               *(.bss*)
+               . = ALIGN(4);
+               __bss_end__ = .;
+       }
+
+       _end = .;
+
+       /DISCARD/ : { *(.dynstr*) }
+       /DISCARD/ : { *(.dynsym*) }
+       /DISCARD/ : { *(.dynamic*) }
+       /DISCARD/ : { *(.hash*) }
+       /DISCARD/ : { *(.plt*) }
+       /DISCARD/ : { *(.interp*) }
+       /DISCARD/ : { *(.gnu*) }
+}
index 89ba558..b4d1d2d 100644 (file)
@@ -236,10 +236,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       blo     clbss_l
+       b       clbss_l
+clbss_e:
 #endif
 
 /*
index 2033b36..b85e7d4 100644 (file)
@@ -232,10 +232,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
        bl coloured_LED_init
        bl red_led_on
index 6b7a494..71309a7 100644 (file)
@@ -40,6 +40,22 @@ struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 #define UART_SMART_IDLE_EN     (0x1 << 0x3)
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+/* Initialize timer */
+static void init_timer(void)
+{
+       /* Reset the Timer */
+       writel(0x2, (&timer_base->tscir));
+
+       /* Wait until the reset is done */
+       while (readl(&timer_base->tiocp_cfg) & 1)
+               ;
+
+       /* Start the Timer */
+       writel(0x1, (&timer_base->tclr));
+}
+#endif
+
 /*
  * early system init of muxing and clocks.
  */
@@ -88,20 +104,6 @@ void s_init(void)
        enable_mmc0_pin_mux();
 }
 
-/* Initialize timer */
-void init_timer(void)
-{
-       /* Reset the Timer */
-       writel(0x2, (&timer_base->tscir));
-
-       /* Wait until the reset is done */
-       while (readl(&timer_base->tiocp_cfg) & 1)
-               ;
-
-       /* Start the Timer */
-       writel(0x1, (&timer_base->tclr));
-}
-
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
index 5407cb6..560c084 100644 (file)
@@ -26,6 +26,8 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 # supported by more tool-chains
 PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
 PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
+PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
+PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED)
 
 # =========================================================================
 #
index 90ec2bd..9119961 100644 (file)
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(SOC).o
 
-COBJS  += clock.o power.o soc.o system.o
+COBJS  += clock.o power.o soc.o system.o pinmux.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
new file mode 100644 (file)
index 0000000..d2b7d2c
--- /dev/null
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/sromc.h>
+
+static void exynos5_uart_config(int peripheral)
+{
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+       struct s5p_gpio_bank *bank;
+       int i, start, count;
+
+       switch (peripheral) {
+       case PERIPH_ID_UART0:
+               bank = &gpio1->a0;
+               start = 0;
+               count = 4;
+               break;
+       case PERIPH_ID_UART1:
+               bank = &gpio1->a0;
+               start = 4;
+               count = 4;
+               break;
+       case PERIPH_ID_UART2:
+               bank = &gpio1->a1;
+               start = 0;
+               count = 4;
+               break;
+       case PERIPH_ID_UART3:
+               bank = &gpio1->a1;
+               start = 4;
+               count = 2;
+               break;
+       }
+       for (i = start; i < start + count; i++) {
+               s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+               s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+       }
+}
+
+static int exynos5_mmc_config(int peripheral, int flags)
+{
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+       struct s5p_gpio_bank *bank, *bank_ext;
+       int i;
+
+       switch (peripheral) {
+       case PERIPH_ID_SDMMC0:
+               bank = &gpio1->c0;
+               bank_ext = &gpio1->c1;
+               break;
+       case PERIPH_ID_SDMMC1:
+               bank = &gpio1->c1;
+               bank_ext = NULL;
+               break;
+       case PERIPH_ID_SDMMC2:
+               bank = &gpio1->c2;
+               bank_ext = &gpio1->c3;
+               break;
+       case PERIPH_ID_SDMMC3:
+               bank = &gpio1->c3;
+               bank_ext = NULL;
+               break;
+       }
+       if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
+               debug("SDMMC device %d does not support 8bit mode",
+                               peripheral);
+               return -1;
+       }
+       if (flags & PINMUX_FLAG_8BIT_MODE) {
+               for (i = 3; i <= 6; i++) {
+                       s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+                       s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
+                       s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
+               }
+       }
+       for (i = 0; i < 2; i++) {
+               s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+               s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
+               s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+       }
+       for (i = 3; i <= 6; i++) {
+               s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
+               s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
+               s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
+       }
+       return 0;
+}
+
+static void exynos5_sromc_config(int flags)
+{
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+       int i;
+
+       /*
+        * SROM:CS1 and EBI
+        *
+        * GPY0[0]      SROM_CSn[0]
+        * GPY0[1]      SROM_CSn[1](2)
+        * GPY0[2]      SROM_CSn[2]
+        * GPY0[3]      SROM_CSn[3]
+        * GPY0[4]      EBI_OEn(2)
+        * GPY0[5]      EBI_EEn(2)
+        *
+        * GPY1[0]      EBI_BEn[0](2)
+        * GPY1[1]      EBI_BEn[1](2)
+        * GPY1[2]      SROM_WAIT(2)
+        * GPY1[3]      EBI_DATA_RDn(2)
+        */
+       s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK),
+                               GPIO_FUNC(2));
+       s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
+       s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
+
+       for (i = 0; i < 4; i++)
+               s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
+
+       /*
+        * EBI: 8 Addrss Lines
+        *
+        * GPY3[0]      EBI_ADDR[0](2)
+        * GPY3[1]      EBI_ADDR[1](2)
+        * GPY3[2]      EBI_ADDR[2](2)
+        * GPY3[3]      EBI_ADDR[3](2)
+        * GPY3[4]      EBI_ADDR[4](2)
+        * GPY3[5]      EBI_ADDR[5](2)
+        * GPY3[6]      EBI_ADDR[6](2)
+        * GPY3[7]      EBI_ADDR[7](2)
+        *
+        * EBI: 16 Data Lines
+        *
+        * GPY5[0]      EBI_DATA[0](2)
+        * GPY5[1]      EBI_DATA[1](2)
+        * GPY5[2]      EBI_DATA[2](2)
+        * GPY5[3]      EBI_DATA[3](2)
+        * GPY5[4]      EBI_DATA[4](2)
+        * GPY5[5]      EBI_DATA[5](2)
+        * GPY5[6]      EBI_DATA[6](2)
+        * GPY5[7]      EBI_DATA[7](2)
+        *
+        * GPY6[0]      EBI_DATA[8](2)
+        * GPY6[1]      EBI_DATA[9](2)
+        * GPY6[2]      EBI_DATA[10](2)
+        * GPY6[3]      EBI_DATA[11](2)
+        * GPY6[4]      EBI_DATA[12](2)
+        * GPY6[5]      EBI_DATA[13](2)
+        * GPY6[6]      EBI_DATA[14](2)
+        * GPY6[7]      EBI_DATA[15](2)
+        */
+       for (i = 0; i < 8; i++) {
+               s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
+               s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
+
+               s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
+               s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
+
+               s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
+               s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
+       }
+}
+
+static int exynos5_pinmux_config(int peripheral, int flags)
+{
+       switch (peripheral) {
+       case PERIPH_ID_UART0:
+       case PERIPH_ID_UART1:
+       case PERIPH_ID_UART2:
+       case PERIPH_ID_UART3:
+               exynos5_uart_config(peripheral);
+               break;
+       case PERIPH_ID_SDMMC0:
+       case PERIPH_ID_SDMMC1:
+       case PERIPH_ID_SDMMC2:
+       case PERIPH_ID_SDMMC3:
+               return exynos5_mmc_config(peripheral, flags);
+       case PERIPH_ID_SROMC:
+               exynos5_sromc_config(flags);
+               break;
+       default:
+               debug("%s: invalid peripheral %d", __func__, peripheral);
+               return -1;
+       }
+
+       return 0;
+}
+
+int exynos_pinmux_config(int peripheral, int flags)
+{
+       if (cpu_is_exynos5())
+               return exynos5_pinmux_config(peripheral, flags);
+       else {
+               debug("pinmux functionality not supported\n");
+               return -1;
+       }
+}
index c765304..4116781 100644 (file)
@@ -52,3 +52,25 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
        if (cpu_is_exynos4())
                exynos4_mipi_phy_control(dev_index, enable);
 }
+
+void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
+{
+       struct exynos5_power *power =
+               (struct exynos5_power *)samsung_get_base_power();
+
+       if (enable) {
+               /* Enabling USBHOST_PHY */
+               setbits_le32(&power->usbhost_phy_control,
+                               POWER_USB_HOST_PHY_CTRL_EN);
+       } else {
+               /* Disabling USBHOST_PHY */
+               clrbits_le32(&power->usbhost_phy_control,
+                               POWER_USB_HOST_PHY_CTRL_EN);
+       }
+}
+
+void set_usbhost_phy_ctrl(unsigned int enable)
+{
+       if (cpu_is_exynos5())
+               exynos5_set_usbhost_phy_ctrl(enable);
+}
index 6c34730..4426611 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/system.h>
 
+static void exynos5_set_usbhost_mode(unsigned int mode)
+{
+       struct exynos5_sysreg *sysreg =
+               (struct exynos5_sysreg *)samsung_get_base_sysreg();
+
+       /* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
+       if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
+               setbits_le32(&sysreg->usb20phy_cfg,
+                               USB20_PHY_CFG_HOST_LINK_EN);
+       } else {
+               clrbits_le32(&sysreg->usb20phy_cfg,
+                               USB20_PHY_CFG_HOST_LINK_EN);
+       }
+}
+
+void set_usbhost_mode(unsigned int mode)
+{
+       if (cpu_is_exynos5())
+               exynos5_set_usbhost_mode(mode);
+}
+
 static void exynos4_set_system_display(void)
 {
        struct exynos4_sysreg *sysreg =
index 2187e8e..80989c4 100644 (file)
@@ -35,7 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
 int get_clocks(void)
 {
 #ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_USDHC
+       gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#else
        gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+#endif
 #endif
        return 0;
 }
index fc2406b..64862b3 100644 (file)
@@ -843,7 +843,7 @@ void mxc_set_sata_internal_clock(void)
 
        set_usb_phy1_clk();
 
-       writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+       writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
 }
 #endif
 
index 90f2088..84b458c 100644 (file)
@@ -43,7 +43,6 @@ u32 get_cpu_rev(void)
        return system_rev;
 }
 
-#ifdef CONFIG_ARCH_CPU_INIT
 void init_aips(void)
 {
        struct aipstz_regs *aips1, *aips2;
@@ -113,7 +112,6 @@ int arch_cpu_init(void)
 
        return 0;
 }
-#endif
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
index 10d286a..b1fd277 100644 (file)
@@ -299,8 +299,12 @@ static void setup_dplls(void)
         * Core DPLL will be locked after setting up EMIF
         * using the FREQ_UPDATE method(freq_update_core())
         */
-       do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK,
-                                                               "core");
+       if (omap_revision() != OMAP5432_ES1_0)
+               do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+                                                       DPLL_NO_LOCK, "core");
+       else
+               do_setup_dpll(&prcm->cm_clkmode_dpll_core, params,
+                                                       DPLL_LOCK, "core");
        /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
        temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
            (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
index db509c9..30dcf1b 100644 (file)
 #include <asm/arch/sys_proto.h>
 #include <asm/omap_common.h>
 #include <asm/utils.h>
+#include <linux/compiler.h>
+
+void set_lpmode_selfrefresh(u32 base)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+       u32 reg;
+
+       reg = readl(&emif->emif_pwr_mgmt_ctrl);
+       reg &= ~EMIF_REG_LP_MODE_MASK;
+       reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
+       reg &= ~EMIF_REG_SR_TIM_MASK;
+       writel(reg, &emif->emif_pwr_mgmt_ctrl);
+
+       /* dummy read for the new SR_TIM to be loaded */
+       readl(&emif->emif_pwr_mgmt_ctrl);
+}
+
+void force_emif_self_refresh()
+{
+       set_lpmode_selfrefresh(EMIF1_BASE);
+       set_lpmode_selfrefresh(EMIF2_BASE);
+}
 
 inline u32 emif_num(u32 base)
 {
@@ -56,7 +78,12 @@ static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
                mr = readl(&emif->emif_lpddr2_mode_reg_data);
        debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
              cs, mr_addr, mr);
-       return mr;
+       if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
+           ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
+           ((mr & 0xff000000) >> 24) == (mr & 0xff))
+               return mr & 0xff;
+       else
+               return mr;
 }
 
 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
@@ -114,9 +141,6 @@ static void do_lpddr2_init(u32 base, u32 cs)
 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-       u32 *ext_phy_ctrl_base = 0;
-       u32 *emif_ext_phy_ctrl_base = 0;
-       u32 i = 0;
 
        /* Not NVM */
        clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
@@ -134,29 +158,7 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
        writel(regs->sdram_config_init, &emif->emif_sdram_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 
-       ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
-       emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
-       if (omap_revision() >= OMAP5430_ES1_0) {
-               /* Configure external phy control timing registers */
-               for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
-                       writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
-                       /* Update shadow registers */
-                       writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
-               }
-
-               /*
-                * external phy 6-24 registers do not change with
-                * ddr frequency
-                */
-               for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
-                       writel(ext_phy_ctrl_const_base[i],
-                                               emif_ext_phy_ctrl_base++);
-                       /* Update shadow registers */
-                       writel(ext_phy_ctrl_const_base[i],
-                                               emif_ext_phy_ctrl_base++);
-               }
-       }
+       do_ext_phy_settings(base, regs);
 
        do_lpddr2_init(base, CS0);
        if (regs->sdram_config & EMIF_REG_EBANK_MASK)
@@ -168,6 +170,10 @@ static void lpddr2_init(u32 base, const struct emif_regs *regs)
        /* Enable refresh now */
        clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 
+       }
+
+__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
 }
 
 void emif_update_timings(u32 base, const struct emif_regs *regs)
@@ -190,7 +196,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
        writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-       if (omap_revision() == OMAP5430_ES1_0) {
+       if (omap_revision() >= OMAP5430_ES1_0) {
                writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
                        &emif->emif_l3_config);
        } else if (omap_revision() >= OMAP4460_ES1_0) {
@@ -202,6 +208,101 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
        }
 }
 
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+       /* keep sdram in self-refresh */
+       writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
+               & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+       __udelay(130);
+
+       /*
+        * Set invert_clkout (if activated)--DDR_PHYCTRL_1
+        * Invert clock adds an additional half cycle delay on the command
+        * interface.  The additional half cycle, is usually meant to enable
+        * leveling in the situation that DQS is later than CK on the board.It
+        * also helps provide some additional margin for leveling.
+        */
+       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+       writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+       __udelay(130);
+
+       writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
+               & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+
+       /* Launch Full leveling */
+       writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+       /* Wait till full leveling is complete */
+       readl(&emif->emif_rd_wr_lvl_ctl);
+       __udelay(130);
+
+       /* Read data eye leveling no of samples */
+       config_data_eye_leveling_samples(base);
+
+       /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
+       writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
+       __udelay(130);
+
+       /* Launch Incremental leveling */
+       writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
+       __udelay(130);
+}
+
+static void ddr3_init(u32 base, const struct emif_regs *regs)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+       u32 *ext_phy_ctrl_base = 0;
+       u32 *emif_ext_phy_ctrl_base = 0;
+       u32 i = 0;
+
+       /*
+        * Set SDRAM_CONFIG and PHY control registers to locked frequency
+        * and RL =7. As the default values of the Mode Registers are not
+        * defined, contents of mode Registers must be fully initialized.
+        * H/W takes care of this initialization
+        */
+       writel(regs->sdram_config_init, &emif->emif_sdram_config);
+
+       writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
+
+       /* Update timing registers */
+       writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
+       writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
+       writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
+
+       writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+       writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
+
+       ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+       emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+       /* Configure external phy control timing registers */
+       for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+               writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+               /* Update shadow registers */
+               writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+       }
+
+       /*
+        * external phy 6-24 registers do not change with
+        * ddr frequency
+        */
+       for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+               writel(ddr3_ext_phy_ctrl_const_base[i],
+                                       emif_ext_phy_ctrl_base++);
+               /* Update shadow registers */
+               writel(ddr3_ext_phy_ctrl_const_base[i],
+                                       emif_ext_phy_ctrl_base++);
+       }
+
+       /* enable leveling */
+       writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
+
+       ddr3_leveling(base, regs);
+}
+
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 
@@ -826,7 +927,7 @@ static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
        }
 
        mr = get_mr(base, cs, LPDDR2_MR5);
-       if (mr >= 0xFF) {
+       if (mr > 0xFF) {
                /* Mode register value bigger than 8 bit */
                return 0;
        }
@@ -895,7 +996,7 @@ struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
                return NULL;
 
        /* Do the minimum init for mode register accesses */
-       if (!running_from_sdram()) {
+       if (!(running_from_sdram() || warm_reset())) {
                phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
                writel(phy, &emif->emif_ddr_phy_ctrl_1);
        }
@@ -975,8 +1076,12 @@ static void do_sdram_init(u32 base)
         * Changing the timing registers in EMIF can happen(going from one
         * OPP to another)
         */
-       if (!in_sdram)
-               lpddr2_init(base, regs);
+       if (!(in_sdram || warm_reset())) {
+               if (omap_revision() != OMAP5432_ES1_0)
+                       lpddr2_init(base, regs);
+               else
+                       ddr3_init(base, regs);
+       }
 
        /* Write to the shadow registers */
        emif_update_timings(base, regs);
@@ -1133,6 +1238,7 @@ void dmm_init(u32 base)
 void sdram_init(void)
 {
        u32 in_sdram, size_prog, size_detect;
+       u32 omap_rev = omap_revision();
 
        debug(">>sdram_init()\n");
 
@@ -1142,25 +1248,34 @@ void sdram_init(void)
        in_sdram = running_from_sdram();
        debug("in_sdram = %d\n", in_sdram);
 
-       if (!in_sdram)
-               bypass_dpll(&prcm->cm_clkmode_dpll_core);
-
+       if (!(in_sdram || warm_reset())) {
+               if (omap_rev != OMAP5432_ES1_0)
+                       bypass_dpll(&prcm->cm_clkmode_dpll_core);
+               else
+                       writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
+       }
 
        do_sdram_init(EMIF1_BASE);
        do_sdram_init(EMIF2_BASE);
 
-       if (!in_sdram) {
+       if (!in_sdram)
                dmm_init(DMM_BASE);
+
+       if (!(in_sdram || warm_reset())) {
                emif_post_init_config(EMIF1_BASE);
                emif_post_init_config(EMIF2_BASE);
        }
 
        /* for the shadow registers to take effect */
-       freq_update_core();
+       if (omap_rev != OMAP5432_ES1_0)
+               freq_update_core();
 
        /* Do some testing after the init */
        if (!in_sdram) {
                size_prog = omap_sdram_size();
+               size_prog = log_2_n_round_down(size_prog);
+               size_prog = (1 << size_prog);
+
                size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                                                size_prog);
                /* Compare with the size programmed */
index cf71ab4..459ebb5 100644 (file)
@@ -111,6 +111,10 @@ static void init_boot_params(void)
 void s_init(void)
 {
        init_omap_revision();
+#ifdef CONFIG_SPL_BUILD
+       if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
+               force_emif_self_refresh();
+#endif
        watchdog_init();
        set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
@@ -162,11 +166,16 @@ void watchdog_init(void)
  */
 u32 omap_sdram_size(void)
 {
-       u32 section, i, total_size = 0, size, addr;
+       u32 section, i, valid;
+       u64 sdram_start = 0, sdram_end = 0, addr,
+           size, total_size = 0, trap_size = 0;
 
        for (i = 0; i < 4; i++) {
                section = __raw_readl(DMM_BASE + i*4);
+               valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
+                       (EMIF_SDRC_ADDRSPC_SHIFT);
                addr = section & EMIF_SYS_ADDR_MASK;
+
                /* See if the address is valid */
                if ((addr >= DRAM_ADDR_SPACE_START) &&
                    (addr < DRAM_ADDR_SPACE_END)) {
@@ -174,9 +183,20 @@ u32 omap_sdram_size(void)
                                   EMIF_SYS_SIZE_SHIFT);
                        size = 1 << size;
                        size *= SZ_16M;
-                       total_size += size;
+
+                       if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
+                               if (!sdram_start || (addr < sdram_start))
+                                       sdram_start = addr;
+                               if (!sdram_end || ((addr + size) > sdram_end))
+                                       sdram_end = addr + size;
+                       } else {
+                               trap_size = size;
+                       }
+
                }
+
        }
+       total_size = (sdram_end - sdram_start) - (trap_size);
 
        return total_size;
 }
index 234e90a..587bb47 100644 (file)
@@ -34,3 +34,8 @@ void __weak reset_cpu(unsigned long ignored)
 {
        writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
 }
+
+u32 __weak warm_reset(void)
+{
+       return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK);
+}
index c568951..5bd0a88 100644 (file)
@@ -146,7 +146,7 @@ static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
        {727, 14, -1, -1, 4, 7, -1, -1},        /* 19.2 MHz */
        {931, 25, -1, -1, 4, 7, -1, -1},        /* 26 MHz   */
        {931, 26, -1, -1, 4, 7, -1, -1},        /* 27 MHz   */
-       {412, 16, -1, -1, 4, 7, -1, -1}         /* 38.4 MHz */
+       {291, 11, -1, -1, 4, 7, -1, -1}         /* 38.4 MHz */
 };
 
 /* ABE M & N values with sys_clk as source */
@@ -354,6 +354,7 @@ void enable_basic_clocks(void)
        };
 
        u32 *const clk_modules_hw_auto_essential[] = {
+               &prcm->cm_l3_2_gpmc_clkctrl,
                &prcm->cm_memif_emif_1_clkctrl,
                &prcm->cm_memif_emif_2_clkctrl,
                &prcm->cm_l4cfg_l4_cfg_clkctrl,
@@ -363,9 +364,6 @@ void enable_basic_clocks(void)
                &prcm->cm_l4per_gpio4_clkctrl,
                &prcm->cm_l4per_gpio5_clkctrl,
                &prcm->cm_l4per_gpio6_clkctrl,
-               &prcm->cm_l3init_usbphy_clkctrl,
-               &prcm->cm_clksel_usb_60mhz,
-               &prcm->cm_l3init_hsusbtll_clkctrl,
                0
        };
 
@@ -376,7 +374,6 @@ void enable_basic_clocks(void)
                &prcm->cm_l4per_gptimer2_clkctrl,
                &prcm->cm_wkup_wdtimer2_clkctrl,
                &prcm->cm_l4per_uart3_clkctrl,
-               &prcm->cm_l3init_hsusbhost_clkctrl,
                0
        };
 
@@ -413,6 +410,9 @@ void enable_basic_uboot_clocks(void)
        u32 *const clk_modules_hw_auto_essential[] = {
                &prcm->cm_l3init_hsusbotg_clkctrl,
                &prcm->cm_l3init_usbphy_clkctrl,
+               &prcm->cm_l3init_usbphy_clkctrl,
+               &prcm->cm_clksel_usb_60mhz,
+               &prcm->cm_l3init_hsusbtll_clkctrl,
                0
        };
 
@@ -422,6 +422,7 @@ void enable_basic_uboot_clocks(void)
                &prcm->cm_l4per_i2c2_clkctrl,
                &prcm->cm_l4per_i2c3_clkctrl,
                &prcm->cm_l4per_i2c4_clkctrl,
+               &prcm->cm_l3init_hsusbhost_clkctrl,
                0
        };
 
@@ -452,12 +453,10 @@ void enable_non_essential_clocks(void)
        };
 
        u32 *const clk_modules_hw_auto_non_essential[] = {
-               &prcm->cm_l3_2_gpmc_clkctrl,
                &prcm->cm_l3instr_l3_3_clkctrl,
                &prcm->cm_l3instr_l3_instr_clkctrl,
                &prcm->cm_l3instr_intrconn_wp1_clkctrl,
                &prcm->cm_l3init_hsi_clkctrl,
-               &prcm->cm_l3init_hsusbtll_clkctrl,
                0
        };
 
@@ -497,7 +496,6 @@ void enable_non_essential_clocks(void)
                &prcm->cm_cam_fdif_clkctrl,
                &prcm->cm_dss_dss_clkctrl,
                &prcm->cm_sgx_sgx_clkctrl,
-               &prcm->cm_l3init_hsusbhost_clkctrl,
                0
        };
 
index 187e938..2c34e48 100644 (file)
@@ -118,6 +118,11 @@ void do_io_settings(void)
 }
 #endif
 
+/* dummy fuction for omap4 */
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+}
+
 void init_omap_revision(void)
 {
        /*
index b538960..b9128fa 100644 (file)
@@ -91,7 +91,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
 };
 
 /* Dummy registers for OMAP44xx */
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
 
 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
        .dmm_lisa_map_0 = 0xFF020100,
index 1a59f26..eecfbad 100644 (file)
@@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void)
  */
 void scale_vcores(void)
 {
-       u32 volt;
+       u32 volt_core, volt_mpu, volt_mm;
 
        omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
 
        /* Palmas settings */
-       volt = VDD_CORE;
-       do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt);
-
-       volt = VDD_MPU;
-       do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt);
-
-       volt = VDD_MM;
-       do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt);
-
+       if (omap_revision() != OMAP5432_ES1_0) {
+               volt_core = VDD_CORE;
+               volt_mpu = VDD_MPU;
+               volt_mm = VDD_MM;
+       } else {
+               volt_core = VDD_CORE_5432;
+               volt_mpu = VDD_MPU_5432;
+               volt_mm = VDD_MM_5432;
+       }
+
+       do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
+       do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
+       do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
+
+       if (omap_revision() == OMAP5432_ES1_0) {
+               /* Configure LDO SRAM "magic" bits */
+               writel(2, &prcm->prm_sldo_core_setup);
+               writel(2, &prcm->prm_sldo_mpu_setup);
+               writel(2, &prcm->prm_sldo_mm_setup);
+       }
 }
 
 u32 get_offset_code(u32 volt_offset)
@@ -306,6 +317,7 @@ void enable_basic_clocks(void)
        };
 
        u32 *const clk_modules_hw_auto_essential[] = {
+               &prcm->cm_l3_2_gpmc_clkctrl,
                &prcm->cm_memif_emif_1_clkctrl,
                &prcm->cm_memif_emif_2_clkctrl,
                &prcm->cm_l4cfg_l4_cfg_clkctrl,
@@ -382,6 +394,9 @@ void enable_basic_uboot_clocks(void)
                &prcm->cm_l4per_i2c2_clkctrl,
                &prcm->cm_l4per_i2c3_clkctrl,
                &prcm->cm_l4per_i2c4_clkctrl,
+               &prcm->cm_l3init_hsusbtll_clkctrl,
+               &prcm->cm_l3init_hsusbhost_clkctrl,
+               &prcm->cm_l3init_fsusb_clkctrl,
                0
        };
 
@@ -416,12 +431,10 @@ void enable_non_essential_clocks(void)
                &prcm->cm_ivahd_ivahd_clkctrl,
                &prcm->cm_ivahd_sl2_clkctrl,
                &prcm->cm_dsp_dsp_clkctrl,
-               &prcm->cm_l3_2_gpmc_clkctrl,
                &prcm->cm_l3instr_l3_3_clkctrl,
                &prcm->cm_l3instr_l3_instr_clkctrl,
                &prcm->cm_l3instr_intrconn_wp1_clkctrl,
                &prcm->cm_l3init_hsi_clkctrl,
-               &prcm->cm_l3init_hsusbtll_clkctrl,
                &prcm->cm_l4per_hdq1w_clkctrl,
                0
        };
@@ -460,8 +473,6 @@ void enable_non_essential_clocks(void)
                &prcm->cm_cam_fdif_clkctrl,
                &prcm->cm_dss_dss_clkctrl,
                &prcm->cm_sgx_sgx_clkctrl,
-               &prcm->cm_l3init_hsusbhost_clkctrl,
-               &prcm->cm_l3init_fsusb_clkctrl,
                0
        };
 
index d01cc81..d0c3ff7 100644 (file)
@@ -35,6 +35,7 @@
 #include <asm/sizes.h>
 #include <asm/utils.h>
 #include <asm/arch/gpio.h>
+#include <asm/emif.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,6 +53,81 @@ static struct gpio_bank gpio_bank_54xx[6] = {
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
 
 #ifdef CONFIG_SPL_BUILD
+/* LPDDR2 specific IO settings */
+static void io_settings_lpddr2(void)
+{
+       struct omap_sys_ctrl_regs *ioregs_base =
+                     (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch1_0));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch1_1));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch2_0));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
+                               &(ioregs_base->control_ddrch2_1));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+                               &(ioregs_base->control_lpddr2ch1_0));
+       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
+                               &(ioregs_base->control_lpddr2ch1_1));
+       writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
+                               &(ioregs_base->control_ddrio_0));
+       writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
+                               &(ioregs_base->control_ddrio_1));
+       writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
+                               &(ioregs_base->control_ddrio_2));
+}
+
+/* DDR3 specific IO settings */
+static void io_settings_ddr3(void)
+{
+       u32 io_settings = 0;
+       struct omap_sys_ctrl_regs *ioregs_base =
+                     (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+       writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddr3ch1_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch1_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch1_1));
+
+       writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddr3ch2_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch2_0));
+       writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
+                               &(ioregs_base->control_ddrch2_1));
+
+       writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
+                               &(ioregs_base->control_ddrio_0));
+       writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
+                               &(ioregs_base->control_ddrio_1));
+       writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
+                               &(ioregs_base->control_ddrio_2));
+
+       /* omap5432 does not use lpddr2 */
+       writel(0x0, &(ioregs_base->control_lpddr2ch1_0));
+       writel(0x0, &(ioregs_base->control_lpddr2ch1_1));
+
+       writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+                       &(ioregs_base->control_emif1_sdram_config_ext));
+       writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+                       &(ioregs_base->control_emif2_sdram_config_ext));
+
+       /* Disable DLL select */
+       io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config))
+                                                       & 0xFFEFFFFF);
+       writel(io_settings,
+               &(ioregs_base->control_port_emif1_sdram_config));
+
+       io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config))
+                                                       & 0xFFEFFFFF);
+       writel(io_settings,
+               &(ioregs_base->control_port_emif2_sdram_config));
+}
+
 /*
  * Some tuning of IOs for optimal power and performance
  */
@@ -115,25 +191,10 @@ void do_io_settings(void)
                       (sc_fast << 17) | (sc_fast << 14);
        writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
 
-       /* LPDDR2 io settings */
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch1_0));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch1_1));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch2_0));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
-                                       &(ioregs_base->control_ddrch2_1));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
-                                       &(ioregs_base->control_lpddr2ch1_0));
-       writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
-                                       &(ioregs_base->control_lpddr2ch1_1));
-       writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
-                                       &(ioregs_base->control_ddrio_0));
-       writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
-                                       &(ioregs_base->control_ddrio_1));
-       writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
-                                       &(ioregs_base->control_ddrio_2));
+       if (omap_revision() <= OMAP5430_ES1_0)
+               io_settings_lpddr2();
+       else
+               io_settings_ddr3();
 
        /* Efuse settings */
        writel(EFUSE_1, &(ioregs_base->control_efuse_1));
@@ -143,6 +204,20 @@ void do_io_settings(void)
 }
 #endif
 
+void config_data_eye_leveling_samples(u32 emif_base)
+{
+       struct omap_sys_ctrl_regs *ioregs_base =
+               (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+       /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
+       if (emif_base == EMIF1_BASE)
+               writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+                       &(ioregs_base->control_emif1_sdram_config_ext));
+       else if (emif_base == EMIF2_BASE)
+               writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
+                       &(ioregs_base->control_emif2_sdram_config_ext));
+}
+
 void init_omap_revision(void)
 {
        /*
@@ -154,7 +229,15 @@ void init_omap_revision(void)
 
        switch (rev) {
        case MIDR_CORTEX_A15_R0P0:
-               *omap_si_rev = OMAP5430_ES1_0;
+               switch (readl(CONTROL_ID_CODE)) {
+               case OMAP5430_CONTROL_ID_CODE_ES1_0:
+                       *omap_si_rev = OMAP5430_ES1_0;
+                       break;
+               case OMAP5432_CONTROL_ID_CODE_ES1_0:
+               default:
+                       *omap_si_rev = OMAP5432_ES1_0;
+                       break;
+               }
                break;
        default:
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
index b2b5753..6ebdf5f 100644 (file)
@@ -86,11 +86,34 @@ const struct emif_regs emif_regs_266_mhz_2cs = {
        .emif_ddr_ext_phy_ctrl_5        = 0x04010040
 };
 
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
+       .sdram_config_init              = 0x61851B32,
+       .sdram_config                   = 0x61851B32,
+       .ref_ctrl                       = 0x00001035,
+       .sdram_tim1                     = 0xCCCF36B3,
+       .sdram_tim2                     = 0x308F7FDA,
+       .sdram_tim3                     = 0x027F88A8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x0007190B,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
+       .emif_ddr_phy_ctlr_1            = 0x0024420A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
+       .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
+};
+
 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
        .dmm_lisa_map_0 = 0x0,
-       .dmm_lisa_map_1 = 0,
-       .dmm_lisa_map_2 = 0,
-       .dmm_lisa_map_3 = 0x80740300
+       .dmm_lisa_map_1 = 0x0,
+       .dmm_lisa_map_2 = 0x80740300,
+       .dmm_lisa_map_3 = 0xFF020100
 };
 
 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
@@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
        0x00000077
 };
 
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+       0x01004010,
+       0x00001004,
+       0x04010040,
+       0x01004010,
+       0x00001004,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x80080080,
+       0x00800800,
+       0x08102040,
+       0x00000002,
+       0x0,
+       0x0,
+       0x0,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000057
+};
+
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
-       *regs = &emif_regs_532_mhz_2cs;
+       if (omap_revision() == OMAP5432_ES1_0)
+               *regs = &emif_regs_ddr3_532_mhz_1cs;
+       else
+               *regs = &emif_regs_532_mhz_2cs;
 }
 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
        __attribute__((weak, alias("emif_get_reg_dump_sdp")));
@@ -156,6 +204,37 @@ void emif_get_device_details(u32 emif_nr,
 
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+       u32 *ext_phy_ctrl_base = 0;
+       u32 *emif_ext_phy_ctrl_base = 0;
+       u32 i = 0;
+
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+       ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
+       emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
+
+       /* Configure external phy control timing registers */
+       for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
+               writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
+               /* Update shadow registers */
+               writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
+       }
+
+       /*
+        * external phy 6-24 registers do not change with
+        * ddr frequency
+        */
+       for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+               writel(ext_phy_ctrl_const_base[i],
+                                       emif_ext_phy_ctrl_base++);
+               /* Update shadow registers */
+               writel(ext_phy_ctrl_const_base[i],
+                                       emif_ext_phy_ctrl_base++);
+       }
+}
+
 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
        .max_freq       = 532000000,
index 527f32d..1642733 100644 (file)
@@ -48,8 +48,9 @@ int print_cpuinfo(void)
 {
        char buf[32];
 
-       printf("CPU:\tS5P%X@%sMHz\n",
-                       s5p_cpu_id, strmhz(buf, get_arm_clk()));
+       printf("CPU:\t%s%X@%sMHz\n",
+                       s5p_get_cpu_name(), s5p_cpu_id,
+                       strmhz(buf, get_arm_clk()));
 
        return 0;
 }
index 261835b..aee27fd 100644 (file)
@@ -259,10 +259,12 @@ clear_bss:
 #endif
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -277,6 +279,18 @@ jump_2_ram:
        mcr     p15, 0, r0, c7, c10, 4  @ DSB
        mcr     p15, 0, r0, c7, c5, 4   @ ISB
 #endif
+/*
+ * Move vector table
+ */
+#if !defined(CONFIG_TEGRA2)
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
+       /* Set vector address in CP15 VBAR register */
+       ldr     r0, =_start
+       add     r0, r0, r9
+       mcr     p15, 0, r0, c12, c0, 0  @Set VBAR
+#endif
+#endif /* !Tegra2 */
+
        ldr     r0, _board_init_r_ofs
        adr     r1, _start
        add     lr, r0, r1
index 08c4137..80da453 100644 (file)
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
+COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
index 698bfd0..1aad387 100644 (file)
@@ -77,8 +77,10 @@ static int ap20_cpu_is_cortexa9(void)
 
 void init_pllx(void)
 {
-       struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-       struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
+       struct clk_rst_ctlr *clkrst =
+                       (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       struct clk_pll_simple *pll =
+               &clkrst->crc_pll_simple[CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE];
        u32 reg;
 
        /* If PLLX is already enabled, just return */
@@ -312,9 +314,28 @@ void enable_scu(void)
        writel(reg, &scu->scu_ctrl);
 }
 
+static u32 get_odmdata(void)
+{
+       /*
+        * ODMDATA is stored in the BCT in IRAM by the BootROM.
+        * The BCT start and size are stored in the BIT in IRAM.
+        * Read the data @ bct_start + (bct_size - 12). This works
+        * on T20 and T30 BCTs, which are locked down. If this changes
+        * in new chips (T114, etc.), we can revisit this algorithm.
+        */
+
+       u32 bct_start, odmdata;
+
+       bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+       odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
+
+       return odmdata;
+}
+
 void init_pmc_scratch(void)
 {
        struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+       u32 odmdata;
        int i;
 
        /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
@@ -322,7 +343,8 @@ void init_pmc_scratch(void)
                writel(0, &pmc->pmc_scratch1+i);
 
        /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
-       writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
+       odmdata = get_odmdata();
+       writel(odmdata, &pmc->pmc_scratch20);
 
 #ifdef CONFIG_TEGRA2_LP0
        /* save Sdram params to PMC 2, 4, and 24 for WB0 */
index a50b1b9..923678d 100644 (file)
@@ -101,6 +101,22 @@ int arch_cpu_init(void)
 }
 #endif
 
+static int uart_configs[] = {
+#if defined(CONFIG_TEGRA2_UARTA_UAA_UAB)
+       FUNCMUX_UART1_UAA_UAB,
+#elif defined(CONFIG_TEGRA2_UARTA_GPU)
+       FUNCMUX_UART1_GPU,
+#elif defined(CONFIG_TEGRA2_UARTA_SDIO1)
+       FUNCMUX_UART1_SDIO1,
+#else
+       FUNCMUX_UART1_IRRX_IRTX,
+#endif
+       FUNCMUX_UART2_IRDA,
+       -1,
+       FUNCMUX_UART4_GMC,
+       -1,
+};
+
 /**
  * Set up the specified uarts
  *
@@ -120,7 +136,7 @@ static void setup_uarts(int uart_ids)
                if (uart_ids & (1 << i)) {
                        enum periph_id id = id_for_uart[i];
 
-                       funcmux_select(id, FUNCMUX_DEFAULT);
+                       funcmux_select(id, uart_configs[i]);
                        clock_ll_start_uart(id);
                }
        }
index ccad351..602589c 100644 (file)
@@ -426,7 +426,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
        struct clk_rst_ctlr *clkrst =
                        (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
-       assert(clock_id_isvalid(clkid));
+       assert(clock_id_is_pll(clkid));
        return &clkrst->crc_pll[clkid];
 }
 
@@ -439,7 +439,7 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
        assert(clkid != CLOCK_ID_USB);
 
        /* Safety check, adds to code size but is small */
-       if (!clock_id_isvalid(clkid) || clkid == CLOCK_ID_USB)
+       if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
                return -1;
        data = readl(&pll->pll_base);
        *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
diff --git a/arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra2/cmd_enterrcm.c
new file mode 100644 (file)
index 0000000..2fcd107
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Derived from code (arch/arm/lib/reset.c) that is:
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/pmc.h>
+
+static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
+                      char * const argv[])
+{
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE;
+
+       puts("Entering RCM...\n");
+       udelay(50000);
+
+       pmc->pmc_scratch0 = 2;
+       disable_interrupts();
+       reset_cpu(0);
+
+       return 0;
+}
+
+U_BOOT_CMD(
+       enterrcm, 1, 0, do_enterrcm,
+       "reset Tegra and enter USB Recovery Mode",
+       ""
+);
index fe9ef5b..4dd8cb8 100644 (file)
 # MA 02111-1307 USA
 #
 
-# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this
-# file with compatible flags
+# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build these
+# files with compatible flags
 ifdef CONFIG_TEGRA2
 CFLAGS_arch/arm/lib/board.o += -march=armv4t
+CFLAGS_arch/arm/lib/memset.o += -march=armv4t
+CFLAGS_lib/string.o += -march=armv4t
+CFLAGS_common/cmd_nvedit.o += -march=armv4t
 endif
 
 USE_PRIVATE_LIBGCC = yes
index 0ef7753..4a31a4c 100644 (file)
@@ -31,11 +31,32 @@ int funcmux_select(enum periph_id id, int config)
 
        switch (id) {
        case PERIPH_ID_UART1:
-               if (config == FUNCMUX_UART1_IRRX_IRTX) {
+               switch (config) {
+               case FUNCMUX_UART1_IRRX_IRTX:
                        pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
                        pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
                        pinmux_tristate_disable(PINGRP_IRRX);
                        pinmux_tristate_disable(PINGRP_IRTX);
+                       break;
+               case FUNCMUX_UART1_UAA_UAB:
+                       pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
+                       pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PINGRP_UAA);
+                       pinmux_tristate_disable(PINGRP_UAB);
+                       bad_config = 0;
+                       break;
+               case FUNCMUX_UART1_GPU:
+                       pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PINGRP_GPU);
+                       bad_config = 0;
+                       break;
+               case FUNCMUX_UART1_SDIO1:
+                       pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
+                       pinmux_tristate_disable(PINGRP_SDIO1);
+                       bad_config = 0;
+                       break;
+               }
+               if (!bad_config) {
                        /*
                         * Tegra appears to boot with function UARTA pre-
                         * selected on mux group SDB. If two mux groups are
@@ -106,6 +127,13 @@ int funcmux_select(enum periph_id id, int config)
                }
                break;
 
+       case PERIPH_ID_SDMMC1:
+               if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
+                       pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
+                       pinmux_tristate_disable(PINGRP_SDIO1);
+               }
+               break;
+
        case PERIPH_ID_SDMMC2:
                if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
                        pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
@@ -181,9 +209,30 @@ int funcmux_select(enum periph_id id, int config)
                                pinmux_set_func(grp[i], PMUX_FUNC_KBC);
                                pinmux_set_pullupdown(grp[i], PMUX_PULL_UP);
                        }
+               }
+               break;
 
-                       break;
+       case PERIPH_ID_USB2:
+               if (config == FUNCMUX_USB2_ULPI) {
+                       pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI);
+                       pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI);
+                       pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI);
+
+                       pinmux_tristate_disable(PINGRP_UAA);
+                       pinmux_tristate_disable(PINGRP_UAB);
+                       pinmux_tristate_disable(PINGRP_UDA);
                }
+               break;
+
+       case PERIPH_ID_SPI1:
+               if (config == FUNCMUX_SPI1_GMC_GMD) {
+                       pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
+                       pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+
+                       pinmux_tristate_disable(PINGRP_GMC);
+                       pinmux_tristate_disable(PINGRP_GMD);
+               }
+               break;
 
        default:
                debug("%s: invalid periph_id %d", __func__, id);
index c80de7f..5f2b243 100644 (file)
@@ -290,7 +290,7 @@ static int init_usb_controller(struct fdt_usb *config,
                        break;
                udelay(1);
        }
-       if (loop_count == 100000)
+       if (!loop_count)
                return -1;
 
        return 0;
index cb32121..59c359a 100644 (file)
@@ -334,10 +334,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
        bl coloured_LED_init
        bl red_led_on
index 62de8b8..bd68cd4 100644 (file)
@@ -245,10 +245,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 #endif
 
 /*
index ba0de8f..33c73f6 100644 (file)
@@ -258,10 +258,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 #endif /* #ifndef CONFIG_SPL_BUILD */
 
 /*
index a29d5b4..8daf26c 100644 (file)
@@ -217,10 +217,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 
        bl coloured_LED_init
        bl red_led_on
index 92546d8..bcea2a8 100644 (file)
@@ -221,10 +221,12 @@ clear_bss:
        add     r1, r1, r4
        mov     r2, #0x00000000         /* clear                            */
 
-clbss_l:str    r2, [r0]                /* clear loop...                    */
+clbss_l:cmp    r0, r1                  /* clear loop... */
+       bhs     clbss_e                 /* if reached end of bss, exit */
+       str     r2, [r0]
        add     r0, r0, #4
-       cmp     r0, r1
-       bne     clbss_l
+       b       clbss_l
+clbss_e:
 #endif
 
 /*
index abc5b6b..d748dd2 100644 (file)
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
-#define OSC    24
+#define OSC    (V_OSCK/1000000)
 
 /* MAIN PLL Fdll = 550 MHZ, */
 #define MPUPLL_M       550
-#define MPUPLL_N       23
+#define MPUPLL_N       (OSC-1)
 #define MPUPLL_M2      1
 
 /* Core PLL Fdll = 1 GHZ, */
 #define COREPLL_M      1000
-#define COREPLL_N      23
+#define COREPLL_N      (OSC-1)
 
 #define COREPLL_M4     10      /* CORE_CLKOUTM4 = 200 MHZ */
 #define COREPLL_M5     8       /* CORE_CLKOUTM5 = 250 MHZ */
  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
  */
 #define PERPLL_M       960
-#define PERPLL_N       23
+#define PERPLL_N       (OSC-1)
 #define PERPLL_M2      5
 
 /* DDR Freq is 266 MHZ for now */
 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
 #define DDRPLL_M       266
-#define DDRPLL_N       23
+#define DDRPLL_N       (OSC-1)
 #define DDRPLL_M2      1
 
 extern void pll_init(void);
index cd002e6..a027e31 100644 (file)
 /* Reset control */
 #ifdef CONFIG_AM33XX
 #define PRM_RSTCTRL                    0x44E00F00
+#define PRM_RSTST                      0x44E00F08
 #endif
 #define PRM_RSTCTRL_RESET              0x01
+#define PRM_RSTST_WARM_RESET_MASK      0x232
 
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
@@ -62,7 +64,7 @@
 struct cm_wkuppll {
        unsigned int wkclkstctrl;       /* offset 0x00 */
        unsigned int wkctrlclkctrl;     /* offset 0x04 */
-       unsigned int resv1[1];
+       unsigned int wkgpio0clkctrl;    /* offset 0x08 */
        unsigned int wkl4wkclkctrl;     /* offset 0x0c */
        unsigned int resv2[4];
        unsigned int idlestdpllmpu;     /* offset 0x20 */
@@ -111,34 +113,54 @@ struct cm_perpll {
        unsigned int l3clkstctrl;       /* offset 0x0c */
        unsigned int resv1;
        unsigned int cpgmac0clkctrl;    /* offset 0x14 */
-       unsigned int resv2[4];
+       unsigned int lcdclkctrl;        /* offset 0x18 */
+       unsigned int usb0clkctrl;       /* offset 0x1C */
+       unsigned int resv2;
+       unsigned int tptc0clkctrl;      /* offset 0x24 */
        unsigned int emifclkctrl;       /* offset 0x28 */
        unsigned int ocmcramclkctrl;    /* offset 0x2c */
        unsigned int gpmcclkctrl;       /* offset 0x30 */
-       unsigned int resv3[2];
+       unsigned int mcasp0clkctrl;     /* offset 0x34 */
+       unsigned int uart5clkctrl;      /* offset 0x38 */
        unsigned int mmc0clkctrl;       /* offset 0x3C */
        unsigned int elmclkctrl;        /* offset 0x40 */
        unsigned int i2c2clkctrl;       /* offset 0x44 */
        unsigned int i2c1clkctrl;       /* offset 0x48 */
        unsigned int spi0clkctrl;       /* offset 0x4C */
        unsigned int spi1clkctrl;       /* offset 0x50 */
-       unsigned int resv4[3];
+       unsigned int resv3[3];
        unsigned int l4lsclkctrl;       /* offset 0x60 */
        unsigned int l4fwclkctrl;       /* offset 0x64 */
-       unsigned int resv5[6];
+       unsigned int mcasp1clkctrl;     /* offset 0x68 */
+       unsigned int uart1clkctrl;      /* offset 0x6C */
+       unsigned int uart2clkctrl;      /* offset 0x70 */
+       unsigned int uart3clkctrl;      /* offset 0x74 */
+       unsigned int uart4clkctrl;      /* offset 0x78 */
+       unsigned int timer7clkctrl;     /* offset 0x7C */
        unsigned int timer2clkctrl;     /* offset 0x80 */
-       unsigned int resv6[11];
+       unsigned int timer3clkctrl;     /* offset 0x84 */
+       unsigned int timer4clkctrl;     /* offset 0x88 */
+       unsigned int resv4[8];
+       unsigned int gpio1clkctrl;      /* offset 0xAC */
        unsigned int gpio2clkctrl;      /* offset 0xB0 */
-       unsigned int resv7[7];
+       unsigned int gpio3clkctrl;      /* offset 0xB4 */
+       unsigned int resv5;
+       unsigned int tpccclkctrl;       /* offset 0xBC */
+       unsigned int dcan0clkctrl;      /* offset 0xC0 */
+       unsigned int dcan1clkctrl;      /* offset 0xC4 */
+       unsigned int resv6[2];
        unsigned int emiffwclkctrl;     /* offset 0xD0 */
-       unsigned int resv8[2];
+       unsigned int resv7[2];
        unsigned int l3instrclkctrl;    /* offset 0xDC */
        unsigned int l3clkctrl;         /* Offset 0xE0 */
-       unsigned int resv9[14];
+       unsigned int resv8[4];
+       unsigned int mmc1clkctrl;       /* offset 0xF4 */
+       unsigned int mmc2clkctrl;       /* offset 0xF8 */
+       unsigned int resv9[8];
        unsigned int l4hsclkstctrl;     /* offset 0x11C */
        unsigned int l4hsclkctrl;       /* offset 0x120 */
        unsigned int resv10[8];
-       unsigned int cpswclkctrl;       /* offset 0x144 */
+       unsigned int cpswclkstctrl;     /* offset 0x144 */
 };
 
 /* Encapsulating Display pll registers */
@@ -213,8 +235,6 @@ struct ctrl_stat {
        unsigned int resv1[16];
        unsigned int statusreg;         /* ofset 0x40 */
 };
-
-void init_timer(void);
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
index 366e2bb..32b2258 100644 (file)
@@ -34,9 +34,9 @@ struct i2c {
        unsigned short revnb_lo;        /* 0x00 */
        unsigned short res1;
        unsigned short revnb_hi;        /* 0x04 */
-       unsigned short res2[13];
-       unsigned short sysc;            /* 0x20 */
-       unsigned short res3;
+       unsigned short res2[5];
+       unsigned short sysc;            /* 0x10 */
+       unsigned short res3[9];
        unsigned short irqstatus_raw;   /* 0x24 */
        unsigned short res4;
        unsigned short stat;            /* 0x28 */
@@ -76,6 +76,6 @@ struct i2c {
 };
 
 #define I2C_IP_CLK                     48000000
-#define I2C_INTERNAL_SAMLPING_CLK      12000000
+#define I2C_INTERNAL_SAMPLING_CLK      12000000
 
 #endif /* _I2C_H_ */
index 416cabf..0483c98 100644 (file)
@@ -66,14 +66,50 @@ typedef struct at91_port {
        u32     puer;           /* 0x64 Pull-up Enable Register */
        u32     pusr;           /* 0x68 Pad Pull-up Status Register */
        u32     reserved4;
+#if defined(CPU_HAS_PIO3)
+       u32     abcdsr1;        /* 0x70 Peripheral ABCD Select Register 1 */
+       u32     abcdsr2;        /* 0x74 Peripheral ABCD Select Register 2 */
+       u32     reserved5[2];
+       u32     ifscdr;         /* 0x80 Input Filter SCLK Disable Register */
+       u32     ifscer;         /* 0x84 Input Filter SCLK Enable Register */
+       u32     ifscsr;         /* 0x88 Input Filter SCLK Status Register */
+       u32     scdr;           /* 0x8C SCLK Divider Debouncing Register */
+       u32     ppddr;          /* 0x90 Pad Pull-down Disable Register */
+       u32     ppder;          /* 0x94 Pad Pull-down Enable Register */
+       u32     ppdsr;          /* 0x98 Pad Pull-down Status Register */
+       u32     reserved6;      /*  */
+#else
        u32     asr;            /* 0x70 Select A Register */
        u32     bsr;            /* 0x74 Select B Register */
        u32     absr;           /* 0x78 AB Select Status Register */
        u32     reserved5[9];   /*  */
+#endif
        u32     ower;           /* 0xA0 Output Write Enable Register */
        u32     owdr;           /* 0xA4 Output Write Disable Register */
-       u32     owsr;           /* OxA8 utput Write Status Register */
+       u32     owsr;           /* OxA8 Output Write Status Register */
+#if defined(CPU_HAS_PIO3)
+       u32     reserved7;      /*  */
+       u32     aimer;          /* 0xB0 Additional INT Modes Enable Register */
+       u32     aimdr;          /* 0xB4 Additional INT Modes Disable Register */
+       u32     aimmr;          /* 0xB8 Additional INT Modes Mask Register */
+       u32     reserved8;      /* */
+       u32     esr;            /* 0xC0 Edge Select Register */
+       u32     lsr;            /* 0xC4 Level Select Register */
+       u32     elsr;           /* 0xC8 Edge/Level Status Register */
+       u32     reserved9;      /* 0xCC */
+       u32     fellsr;         /* 0xD0 Falling /Low Level Select Register */
+       u32     rehlsr;         /* 0xD4 Rising /High Level Select Register */
+       u32     frlhsr;         /* 0xD8 Fall/Rise - Low/High Status Register */
+       u32     reserved10;     /* */
+       u32     locksr;         /* 0xE0 Lock Status */
+       u32     wpmr;           /* 0xE4 Write Protect Mode Register */
+       u32     wpsr;           /* 0xE8 Write Protect Status Register */
+       u32     reserved11[5];  /* */
+       u32     schmitt;        /* 0x100 Schmitt Trigger Register */
+       u32     reserved12[63];
+#else
        u32     reserved6[85];
+#endif
 } at91_port_t;
 
 typedef union at91_pio {
@@ -94,6 +130,13 @@ typedef union at91_pio {
 #ifdef CONFIG_AT91_GPIO
 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup);
 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup);
+#if defined(CPU_HAS_PIO3)
+int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup);
+int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div);
+int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on);
+int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin);
+#endif
 int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup);
 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on);
 int at91_set_pio_output(unsigned port, unsigned pin, int value);
index ac4ddc7..0c341d4 100644 (file)
@@ -24,6 +24,7 @@
 
 #define DEVICE_NOT_AVAILABLE           0
 
+#define EXYNOS_CPU_NAME                        "Exynos"
 #define EXYNOS4_ADDR_BASE              0x10000000
 
 /* EXYNOS4 */
@@ -45,6 +46,7 @@
 #define EXYNOS4_USBOTG_BASE            0x12480000
 #define EXYNOS4_MMC_BASE               0x12510000
 #define EXYNOS4_SROMC_BASE             0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE     0x12580000
 #define EXYNOS4_USBPHY_BASE            0x125B0000
 #define EXYNOS4_UART_BASE              0x13800000
 #define EXYNOS4_ADC_BASE               0x13910000
 #define EXYNOS5_DMC_CTRL_BASE          0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE                0x11400000
 #define EXYNOS5_MIPI_DSIM_BASE         0x11D00000
+#define EXYNOS5_USB_HOST_EHCI_BASE     0x12110000
+#define EXYNOS5_USBPHY_BASE            0x12130000
+#define EXYNOS5_USBOTG_BASE            0x12140000
 #define EXYNOS5_MMC_BASE               0x12200000
 #define EXYNOS5_SROMC_BASE             0x12250000
-#define EXYNOS5_USBOTG_BASE            0x12480000
-#define EXYNOS5_USBPHY_BASE            0x12480000
 #define EXYNOS5_UART_BASE              0x12C00000
 #define EXYNOS5_PWMTIMER_BASE          0x12DD0000
 #define EXYNOS5_GPIO_PART2_BASE                0x13400000
@@ -93,29 +96,42 @@ static inline int s5p_get_cpu_rev(void)
 
 static inline void s5p_set_cpu_id(void)
 {
-       s5p_cpu_id = readl(EXYNOS4_PRO_ID);
-       s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
-
-       /*
-        * 0xC200: EXYNOS4210 EVT0
-        * 0xC210: EXYNOS4210 EVT1
-        */
-       if (s5p_cpu_id == 0xC200) {
-               s5p_cpu_id |= 0x10;
+       unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
+
+       switch (pro_id) {
+       case 0x200:
+               /* Exynos4210 EVT0 */
+               s5p_cpu_id = 0x4210;
                s5p_cpu_rev = 0;
-       } else if (s5p_cpu_id == 0xC210) {
-               s5p_cpu_rev = 1;
+               break;
+       case 0x210:
+               /* Exynos4210 EVT1 */
+               s5p_cpu_id = 0x4210;
+               break;
+       case 0x412:
+               /* Exynos4412 */
+               s5p_cpu_id = 0x4412;
+               break;
+       case 0x520:
+               /* Exynos5250 */
+               s5p_cpu_id = 0x5250;
+               break;
        }
 }
 
+static inline char *s5p_get_cpu_name(void)
+{
+       return EXYNOS_CPU_NAME;
+}
+
 #define IS_SAMSUNG_TYPE(type, id)                      \
 static inline int cpu_is_##type(void)                  \
 {                                                      \
-       return s5p_cpu_id == id ? 1 : 0;                \
+       return (s5p_cpu_id >> 12) == id;                \
 }
 
-IS_SAMSUNG_TYPE(exynos4, 0xc210)
-IS_SAMSUNG_TYPE(exynos5, 0xc520)
+IS_SAMSUNG_TYPE(exynos4, 0x4)
+IS_SAMSUNG_TYPE(exynos5, 0x5)
 
 #define SAMSUNG_BASE(device, base)                             \
 static inline unsigned int samsung_get_base_##device(void)     \
@@ -145,6 +161,7 @@ SAMSUNG_BASE(swreset, SWRESET)
 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 SAMSUNG_BASE(uart, UART_BASE)
 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
similarity index 90%
rename from arch/arm/include/asm/arch-exynos/ehci-s5p.h
rename to arch/arm/include/asm/arch-exynos/ehci.h
index 68feb85..8aeff8a 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * SAMSUNG S5P USB HOST EHCI Controller
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
  *
  * Copyright (C) 2012 Samsung Electronics Co.Ltd
  *     Vivek Gautam <gautam.vivek@samsung.com>
@@ -20,8 +20,8 @@
  * MA 02110-1301 USA
  */
 
-#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
 
 #define CLK_24MHZ              5
 
@@ -43,7 +43,7 @@
 #define EHCICTRL_ENAINCR16                     (1 << 26)
 
 /* Register map for PHY control */
-struct s5p_usb_phy {
+struct exynos_usb_phy {
        unsigned int usbphyctrl0;
        unsigned int usbphytune0;
        unsigned int reserved1[2];
@@ -63,4 +63,4 @@ struct s5p_usb_phy {
 /* Switch on the VBUS power. */
 int board_usb_vbus_init(void);
 
-#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
new file mode 100644 (file)
index 0000000..5db25aa
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PERIPH_H
+#define __ASM_ARM_ARCH_PERIPH_H
+
+/*
+ * Peripherals requiring clock/pinmux configuration. List will
+ * grow with support for more devices getting added.
+ *
+ */
+enum periph_id {
+       PERIPH_ID_SDMMC0,
+       PERIPH_ID_SDMMC1,
+       PERIPH_ID_SDMMC2,
+       PERIPH_ID_SDMMC3,
+       PERIPH_ID_SROMC,
+       PERIPH_ID_UART0,
+       PERIPH_ID_UART1,
+       PERIPH_ID_UART2,
+       PERIPH_ID_UART3,
+
+       PERIPH_ID_COUNT,
+       PERIPH_ID_NONE = -1,
+};
+
+#endif /* __ASM_ARM_ARCH_PERIPH_H */
diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h
new file mode 100644 (file)
index 0000000..10ea736
--- /dev/null
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Abhilash Kesavan <a.kesavan@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PINMUX_H
+#define __ASM_ARM_ARCH_PINMUX_H
+
+#include "periph.h"
+
+/*
+ * Flags for setting specific configarations of peripherals.
+ * List will grow with support for more devices getting added.
+ */
+enum {
+       PINMUX_FLAG_NONE        = 0x00000000,
+
+       /* Flags for eMMC */
+       PINMUX_FLAG_8BIT_MODE   = 1 << 0,       /* SDMMC 8-bit mode */
+
+       /* Flags for SROM controller */
+       PINMUX_FLAG_BANK        = 3 << 0,       /* bank number (0-3) */
+       PINMUX_FLAG_16BIT       = 1 << 2,       /* 16-bit width */
+};
+
+/**
+ * Configures the pinmux for a particular peripheral.
+ *
+ * Each gpio can be configured in many different ways (4 bits on exynos)
+ * such as "input", "output", "special function", "external interrupt"
+ * etc. This function will configure the peripheral pinmux along with
+ * pull-up/down and drive strength.
+ *
+ * @param peripheral   peripheral to be configured
+ * @param flags                configure flags
+ * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
+ */
+int exynos_pinmux_config(int peripheral, int flags);
+
+#endif
index 6444fd0..e5467e2 100644 (file)
@@ -225,6 +225,628 @@ struct exynos4_power {
        unsigned int    gps_alive_status;
        unsigned int    gps_alive_option;
 };
+
+struct exynos5_power {
+       unsigned int    om_stat;
+       unsigned char   res1[0x18];
+       unsigned int    rtc_clko_sel;
+       unsigned int    gnss_rtc_out_ctrl;
+       unsigned char   res2[0x1dc];
+       unsigned int    central_seq_configuration;
+       unsigned int    central_seq_status;
+       unsigned int    central_seq_option;
+       unsigned char   res3[0x14];
+       unsigned int    seq_transition0;
+       unsigned int    seq_transition1;
+       unsigned int    seq_transition2;
+       unsigned int    seq_transition3;
+       unsigned int    seq_transition4;
+       unsigned int    seq_transition5;
+       unsigned int    seq_transition6;
+       unsigned int    seq_transition7;
+       unsigned int    central_seq_dmc_configuration;
+       unsigned int    central_seq_dmc_status;
+       unsigned int    central_seq_dmc_option;
+       unsigned char   res4[0x14];
+       unsigned int    seq_dmc_transition0;
+       unsigned int    seq_dmc_transition1;
+       unsigned int    seq_dmc_transition2;
+       unsigned int    seq_dmc_transition3;
+       unsigned int    seq_dmc_transition4;
+       unsigned int    seq_dmc_transition5;
+       unsigned int    seq_dmc_transition6;
+       unsigned int    seq_dmc_transition7;
+       unsigned char   res5[0x180];
+       unsigned int    swreset;
+       unsigned int    rst_stat;
+       unsigned int    automatic_wdt_reset_disable;
+       unsigned int    mask_wdt_reset_request;
+       unsigned int    mask_wreset_request;
+       unsigned char   res6[0xec];
+       unsigned int    reset_sequencer_configuration;
+       unsigned int    reset_sequencer_status;
+       unsigned int    reset_sequencer_option;
+       unsigned char   res7[0xf4];
+       unsigned int    wakeup_stat;
+       unsigned int    eint_wakeup_mask;
+       unsigned int    wakeup_mask;
+       unsigned int    wakeup_interrupt;
+       unsigned char   res8[0x10];
+       unsigned int    wakeup_stat_dmc;
+       unsigned int    eint_wakeup_mask_dmc;
+       unsigned int    wakeup_mask_dmc;
+       unsigned int    wakeup_interrupt_dmc;
+       unsigned char   res9[0xd0];
+       unsigned int    hdmi_phy_control;
+       unsigned int    usbdrd_phy_control;
+       unsigned int    usbhost_phy_control;
+       unsigned int    efnand_phy_control;
+       unsigned int    mipi_phy0_control;
+       unsigned int    mipi_phy1_control;
+       unsigned int    adc_phy_control;
+       unsigned int    mtcadc_phy_control;
+       unsigned int    dptx_phy_control;
+       unsigned int    sata_phy_control;
+       unsigned char   res10[0xd8];
+       unsigned int    inform0;
+       unsigned int    inform1;
+       unsigned int    inform2;
+       unsigned int    inform3;
+       unsigned int    sysip_dat0;
+       unsigned int    sysip_dat1;
+       unsigned int    sysip_dat2;
+       unsigned int    sysip_dat3;
+       unsigned char   res11[0xe0];
+       unsigned int    pmu_spare0;
+       unsigned int    pmu_spare1;
+       unsigned int    pmu_spare2;
+       unsigned int    pmu_spare3;
+       unsigned char   res12[0x70];
+       unsigned int    irom_data_reg0;
+       unsigned int    irom_data_reg1;
+       unsigned int    irom_data_reg2;
+       unsigned int    irom_data_reg3;
+       unsigned char   res13[0x70];
+       unsigned int    pmu_debug;
+       unsigned char   res14[0x5fc];
+       unsigned int    arm_core0_sys_pwr_reg;
+       unsigned int    dis_irq_arm_core0_local_sys_pwr_reg;
+       unsigned int    dis_irq_arm_core0_central_sys_pwr_reg;
+       unsigned char   res15[0x4];
+       unsigned int    arm_core1_sys_pwr_reg;
+       unsigned int    dis_irq_arm_core1_local_sys_pwr_reg;
+       unsigned int    dis_irq_arm_core1_central_sys_pwr_reg;
+       unsigned char   res16[0x24];
+       unsigned int    fsys_arm_sys_pwr_reg;
+       unsigned int    dis_irq_fsys_arm_local_sys_pwr_reg;
+       unsigned int    dis_irq_fsys_arm_central_sys_pwr_reg;
+       unsigned char   res17[0x4];
+       unsigned int    isp_arm_sys_pwr_reg;
+       unsigned int    dis_irq_isp_arm_local_sys_pwr_reg;
+       unsigned int    dis_irq_isp_arm_central_sys_pwr_reg;
+       unsigned char   res18[0x24];
+       unsigned int    arm_common_sys_pwr_reg;
+       unsigned char   res19[0x3c];
+       unsigned int    arm_l2_sys_pwr_reg;
+       unsigned char   res20[0x3c];
+       unsigned int    cmu_aclkstop_sys_pwr_reg;
+       unsigned int    cmu_sclkstop_sys_pwr_reg;
+       unsigned char   res21[0x4];
+       unsigned int    cmu_reset_sys_pwr_reg;
+       unsigned char   res22[0x10];
+       unsigned int    cmu_aclkstop_dmc_sys_pwr_reg;
+       unsigned int    cmu_sclkstop_dmc_sys_pwr_reg;
+       unsigned char   res23[0x4];
+       unsigned int    cmu_reset_dmc_sys_pwr_reg;
+       unsigned char   res24[0x8];
+       unsigned int    ddrphy_dlllock_sys_pwr_reg;
+       unsigned char   res25[0x4];
+       unsigned int    apll_sysclk_sys_pwr_reg;
+       unsigned int    mpll_sysclk_sys_pwr_reg;
+       unsigned int    vpll_sysclk_sys_pwr_reg;
+       unsigned int    epll_sysclk_sys_pwr_reg;
+       unsigned int    bpll_sysclk_sys_pwr_reg;
+       unsigned int    cpll_sysclk_sys_pwr_reg;
+       unsigned int    gpll_sysclk_sys_pwr_reg;
+       unsigned char   res26[0x8];
+       unsigned int    mplluser_sysclk_sys_pwr_reg;
+       unsigned char   res27[0x8];
+       unsigned int    bplluser_sysclk_sys_pwr_reg;
+       unsigned char   res28[0xc];
+       unsigned int    top_bus_sys_pwr_reg;
+       unsigned int    top_retention_sys_pwr_reg;
+       unsigned int    top_pwr_sys_pwr_reg;
+       unsigned char   res29[0x4];
+       unsigned int    top_bus_dmc_sys_pwr_reg;
+       unsigned int    top_retention_dmc_sys_pwr_reg;
+       unsigned int    top_pwr_dmc_sys_pwr_reg;
+       unsigned char   res30[0x4];
+       unsigned int    logic_reset_sys_pwr_reg;
+       unsigned int    oscclk_gate_sys_pwr_reg;
+       unsigned char   res31[0x8];
+       unsigned int    logic_reset_dmc_sys_pwr_reg;
+       unsigned int    oscclk_gate_dmc_sys_pwr_reg;
+       unsigned char   res32[0x8];
+       unsigned int    usbotg_mem_sys_pwr_reg;
+       unsigned char   res33[0x4];
+       unsigned int    g2d_mem_sys_pwr_reg;
+       unsigned int    usbdrd_mem_sys_pwr_reg;
+       unsigned int    efnand_mem_sys_pwr_reg;
+       unsigned int    cssys_mem_sys_pwr_reg;
+       unsigned int    secss_mem_sys_pwr_reg;
+       unsigned int    rotator_mem_sys_pwr_reg;
+       unsigned int    intram_mem_sys_pwr_reg;
+       unsigned int    introm_mem_sys_pwr_reg;
+       unsigned int    jpeg_mem_sys_pwr_reg;
+       unsigned int    hsi_mem_sys_pwr_reg;
+       unsigned char   res34[0x4];
+       unsigned int    mcuiop_mem_sys_pwr_reg;
+       unsigned char   res35[0x4];
+       unsigned int    sata_mem_sys_pwr_reg;
+       unsigned int    pad_retention_dram_sys_pwr_reg;
+       unsigned int    pad_retention_mau_sys_pwr_reg;
+       unsigned int    pad_retention_jtag_sys_pwr_reg;
+       unsigned char   res36[0xc];
+       unsigned int    pad_retention_mmc2_sys_pwr_reg;
+       unsigned int    pad_retention_mmc3_sys_pwr_reg;
+       unsigned int    pad_retention_gpio_sys_pwr_reg;
+       unsigned int    pad_retention_uart_sys_pwr_reg;
+       unsigned int    pad_retention_mmc0_sys_pwr_reg;
+       unsigned int    pad_retention_mmc1_sys_pwr_reg;
+       unsigned int    pad_retention_ebia_sys_pwr_reg;
+       unsigned int    pad_retention_ebib_sys_pwr_reg;
+       unsigned int    pad_retention_spi_sys_pwr_reg;
+       unsigned int    pad_retention_gpio_dmc_sys_pwr_reg;
+       unsigned int    pad_isolation_sys_pwr_reg;
+       unsigned char   res37[0xc];
+       unsigned int    pad_isolation_dmc_sys_pwr_reg;
+       unsigned char   res38[0xc];
+       unsigned int    pad_alv_sel_sys_pwr_reg;
+       unsigned char   res39[0x20];
+       unsigned int    xxti_sys_pwr_reg;
+       unsigned char   res40[0x38];
+       unsigned int    ext_regulator_sys_pwr_reg;
+       unsigned char   res41[0x3c];
+       unsigned int    gpio_mode_sys_pwr_reg;
+       unsigned char   res42[0x1c];
+       unsigned int    gpio_mode_dmc_sys_pwr_reg;
+       unsigned char   res43[0x1c];
+       unsigned int    gpio_mode_mau_sys_pwr_reg;
+       unsigned int    top_asb_reset_sys_pwr_reg;
+       unsigned int    top_asb_isolation_sys_pwr_reg;
+       unsigned char   res44[0xb4];
+       unsigned int    gscl_sys_pwr_reg;
+       unsigned int    isp_sys_pwr_reg;
+       unsigned int    mfc_sys_pwr_reg;
+       unsigned int    g3d_sys_pwr_reg;
+       unsigned char   res45[0x4];
+       unsigned int    disp1_sys_pwr_reg;
+       unsigned int    mau_sys_pwr_reg;
+       unsigned char   res46[0x64];
+       unsigned int    cmu_clkstop_gscl_sys_pwr_reg;
+       unsigned int    cmu_clkstop_isp_sys_pwr_reg;
+       unsigned int    cmu_clkstop_mfc_sys_pwr_reg;
+       unsigned int    cmu_clkstop_g3d_sys_pwr_reg;
+       unsigned char   res47[0x4];
+       unsigned int    cmu_clkstop_disp1_sys_pwr_reg;
+       unsigned int    cmu_clkstop_mau_sys_pwr_reg;
+       unsigned char   res48[0x24];
+       unsigned int    cmu_sysclk_gscl_sys_pwr_reg;
+       unsigned int    cmu_sysclk_isp_sys_pwr_reg;
+       unsigned int    cmu_sysclk_mfc_sys_pwr_reg;
+       unsigned int    cmu_sysclk_g3d_sys_pwr_reg;
+       unsigned char   res49[0x4];
+       unsigned int    cmu_sysclk_disp1_sys_pwr_reg;
+       unsigned int    cmu_sysclk_mau_sys_pwr_reg;
+       unsigned char   res50[0xa4];
+       unsigned int    cmu_reset_gscl_sys_pwr_reg;
+       unsigned int    cmu_reset_isp_sys_pwr_reg;
+       unsigned int    cmu_reset_mfc_sys_pwr_reg;
+       unsigned int    cmu_reset_g3d_sys_pwr_reg;
+       unsigned char   res51[0x4];
+       unsigned int    cmu_reset_disp1_sys_pwr_reg;
+       unsigned int    cmu_reset_mau_sys_pwr_reg;
+       unsigned char   res52[0xa64];
+       unsigned int    arm_core0_configuration;
+       unsigned int    arm_core0_status;
+       unsigned int    arm_core0_option;
+       unsigned char   res53[0x14];
+       unsigned int    dis_irq_arm_core0_local_configuration;
+       unsigned int    dis_irq_arm_core0_local_status;
+       unsigned int    dis_irq_arm_core0_local_option;
+       unsigned char   res54[0x14];
+       unsigned int    dis_irq_arm_core0_central_configuration;
+       unsigned int    dis_irq_arm_core0_central_status;
+       unsigned int    dis_irq_arm_core0_central_option;
+       unsigned char   res55[0x34];
+       unsigned int    arm_core1_configuration;
+       unsigned int    arm_core1_status;
+       unsigned int    arm_core1_option;
+       unsigned char   res56[0x14];
+       unsigned int    dis_irq_arm_core1_local_configuration;
+       unsigned int    dis_irq_arm_core1_local_status;
+       unsigned int    dis_irq_arm_core1_local_option;
+       unsigned char   res57[0x14];
+       unsigned int    dis_irq_arm_core1_central_configuration;
+       unsigned int    dis_irq_arm_core1_central_status;
+       unsigned int    dis_irq_arm_core1_central_option;
+       unsigned char   res58[0x134];
+       unsigned int    fsys_arm_configuration;
+       unsigned int    fsys_arm_status;
+       unsigned int    fsys_arm_option;
+       unsigned char   res59[0x14];
+       unsigned int    dis_irq_fsys_arm_local_configuration;
+       unsigned int    dis_irq_fsys_arm_local_status;
+       unsigned int    dis_irq_fsys_arm_local_option;
+       unsigned char   res60[0x14];
+       unsigned int    dis_irq_fsys_arm_central_configuration;
+       unsigned int    dis_irq_fsys_arm_central_status;
+       unsigned int    dis_irq_fsys_arm_central_option;
+       unsigned char   res61[0x34];
+       unsigned int    isp_arm_configuration;
+       unsigned int    isp_arm_status;
+       unsigned int    isp_arm_option;
+       unsigned char   res62[0x14];
+       unsigned int    dis_irq_isp_arm_local_configuration;
+       unsigned int    dis_irq_isp_arm_local_status;
+       unsigned int    dis_irq_isp_arm_local_option;
+       unsigned char   res63[0x14];
+       unsigned int    dis_irq_isp_arm_central_configuration;
+       unsigned int    dis_irq_isp_arm_central_status;
+       unsigned int    dis_irq_isp_arm_central_option;
+       unsigned char   res64[0x134];
+       unsigned int    arm_common_configuration;
+       unsigned int    arm_common_status;
+       unsigned int    arm_common_option;
+       unsigned char   res65[0x1f4];
+       unsigned int    arm_l2_configuration;
+       unsigned int    arm_l2_status;
+       unsigned int    arm_l2_option;
+       unsigned char   res66[0x1f4];
+       unsigned int    cmu_aclkstop_configuration;
+       unsigned int    cmu_aclkstop_status;
+       unsigned int    cmu_aclkstop_option;
+       unsigned char   res67[0x14];
+       unsigned int    cmu_sclkstop_configuration;
+       unsigned int    cmu_sclkstop_status;
+       unsigned int    cmu_sclkstop_option;
+       unsigned char   res68[0x34];
+       unsigned int    cmu_reset_configuration;
+       unsigned int    cmu_reset_status;
+       unsigned int    cmu_reset_option;
+       unsigned char   res69[0x94];
+       unsigned int    cmu_aclkstop_dmc_configuration;
+       unsigned int    cmu_aclkstop_dmc_status;
+       unsigned int    cmu_aclkstop_dmc_option;
+       unsigned char   res70[0x14];
+       unsigned int    cmu_sclkstop_dmc_configuration;
+       unsigned int    cmu_sclkstop_dmc_status;
+       unsigned int    cmu_sclkstop_dmc_option;
+       unsigned char   res71[0x34];
+       unsigned int    cmu_reset_dmc_configuration;
+       unsigned int    cmu_reset_dmc_status;
+       unsigned int    cmu_reset_dmc_option;
+       unsigned char   res72[0x54];
+       unsigned int    ddrphy_dlllock_configuration;
+       unsigned int    ddrphy_dlllock_status;
+       unsigned int    ddrphy_dlllock_option;
+       unsigned char   res73[0x34];
+       unsigned int    apll_sysclk_configuration;
+       unsigned int    apll_sysclk_status;
+       unsigned int    apll_sysclk_option;
+       unsigned char   res74[0x18];
+       unsigned int    mpll_sysclk_status;
+       unsigned int    mpll_sysclk_option;
+       unsigned char   res75[0x14];
+       unsigned int    vpll_sysclk_configuration;
+       unsigned int    vpll_sysclk_status;
+       unsigned int    vpll_sysclk_option;
+       unsigned char   res76[0x14];
+       unsigned int    epll_sysclk_configuration;
+       unsigned int    epll_sysclk_status;
+       unsigned int    epll_sysclk_option;
+       unsigned char   res77[0x14];
+       unsigned int    bpll_sysclk_configuration;
+       unsigned int    bpll_sysclk_status;
+       unsigned int    bpll_sysclk_option;
+       unsigned char   res78[0x14];
+       unsigned int    cpll_sysclk_configuration;
+       unsigned int    cpll_sysclk_status;
+       unsigned int    cpll_sysclk_option;
+       unsigned char   res79[0x14];
+       unsigned int    gpll_sysclk_configuration;
+       unsigned int    gpll_sysclk_status;
+       unsigned int    gpll_sysclk_option;
+       unsigned char   res80[0x54];
+       unsigned int    mplluser_sysclk_configuration;
+       unsigned int    mplluser_sysclk_status;
+       unsigned int    mplluser_sysclk_option;
+       unsigned char   res81[0x54];
+       unsigned int    bplluser_sysclk_configuration;
+       unsigned int    bplluser_sysclk_status;
+       unsigned int    bplluser_sysclk_option;
+       unsigned char   res82[0x74];
+       unsigned int    top_bus_configuration;
+       unsigned int    top_bus_status;
+       unsigned int    top_bus_option;
+       unsigned char   res83[0x14];
+       unsigned int    top_retention_configuration;
+       unsigned int    top_retention_status;
+       unsigned int    top_retention_option;
+       unsigned char   res84[0x14];
+       unsigned int    top_pwr_configuration;
+       unsigned int    top_pwr_status;
+       unsigned int    top_pwr_option;
+       unsigned char   res85[0x34];
+       unsigned int    top_bus_dmc_configuration;
+       unsigned int    top_bus_dmc_status;
+       unsigned int    top_bus_dmc_option;
+       unsigned char   res86[0x14];
+       unsigned int    top_retention_dmc_configuration;
+       unsigned int    top_retention_dmc_status;
+       unsigned int    top_retention_dmc_option;
+       unsigned char   res87[0x14];
+       unsigned int    top_pwr_dmc_configuration;
+       unsigned int    top_pwr_dmc_status;
+       unsigned int    top_pwr_dmc_option;
+       unsigned char   res88[0x34];
+       unsigned int    logic_reset_configuration;
+       unsigned int    logic_reset_status;
+       unsigned int    logic_reset_option;
+       unsigned char   res89[0x14];
+       unsigned int    oscclk_gate_configuration;
+       unsigned int    oscclk_gate_status;
+       unsigned int    oscclk_gate_option;
+       unsigned char   res90[0x54];
+       unsigned int    logic_reset_dmc_configuration;
+       unsigned int    logic_reset_dmc_status;
+       unsigned int    logic_reset_dmc_option;
+       unsigned char   res91[0x14];
+       unsigned int    oscclk_gate_dmc_configuration;
+       unsigned int    oscclk_gate_dmc_status;
+       unsigned int    oscclk_gate_dmc_option;
+       unsigned char   res92[0x54];
+       unsigned int    usbotg_mem_configuration;
+       unsigned int    usbotg_mem_status;
+       unsigned int    usbotg_mem_option;
+       unsigned char   res93[0x34];
+       unsigned int    g2d_mem_configuration;
+       unsigned int    g2d_mem_status;
+       unsigned int    g2d_mem_option;
+       unsigned char   res94[0x14];
+       unsigned int    usbdrd_mem_configuration;
+       unsigned int    usbdrd_mem_status;
+       unsigned int    usbdrd_mem_option;
+       unsigned char   res95[0x14];
+       unsigned int    efnand_mem_configuration;
+       unsigned int    efnand_mem_status;
+       unsigned int    efnand_mem_option;
+       unsigned char   res96[0x14];
+       unsigned int    cssys_mem_configuration;
+       unsigned int    cssys_mem_status;
+       unsigned int    cssys_mem_option;
+       unsigned char   res97[0x14];
+       unsigned int    secss_mem_configuration;
+       unsigned int    secss_mem_status;
+       unsigned int    secss_mem_option;
+       unsigned char   res98[0x14];
+       unsigned int    rotator_mem_configuration;
+       unsigned int    rotator_mem_status;
+       unsigned int    rotator_mem_option;
+       unsigned char   res99[0x14];
+       unsigned int    intram_mem_configuration;
+       unsigned int    intram_mem_status;
+       unsigned int    intram_mem_option;
+       unsigned char   res100[0x14];
+       unsigned int    introm_mem_configuration;
+       unsigned int    introm_mem_status;
+       unsigned int    introm_mem_option;
+       unsigned char   res101[0x14];
+       unsigned int    jpeg_mem_configuration;
+       unsigned int    jpeg_mem_status;
+       unsigned int    jpeg_mem_option;
+       unsigned char   res102[0x14];
+       unsigned int    hsi_mem_configuration;
+       unsigned int    hsi_mem_status;
+       unsigned int    hsi_mem_option;
+       unsigned char   res103[0x34];
+       unsigned int    mcuiop_mem_configuration;
+       unsigned int    mcuiop_mem_status;
+       unsigned int    mcuiop_mem_option;
+       unsigned char   res104[0x14];
+       unsigned int    sata_mem_configuration;
+       unsigned int    sata_mem_status;
+       unsigned int    sata_mem_option;
+       unsigned char   res105[0x34];
+       unsigned int    pad_retention_dram_configuration;
+       unsigned int    pad_retention_dram_status;
+       unsigned int    pad_retention_dram_option;
+       unsigned char   res106[0x14];
+       unsigned int    pad_retention_mau_configuration;
+       unsigned int    pad_retention_mau_status;
+       unsigned int    pad_retention_mau_option;
+       unsigned char   res107[0x14];
+       unsigned int    pad_retention_jtag_configuration;
+       unsigned int    pad_retention_jtag_status;
+       unsigned int    pad_retention_jtag_option;
+       unsigned char   res108[0x74];
+       unsigned int    pad_retention_mmc2_configuration;
+       unsigned int    pad_retention_mmc2_status;
+       unsigned int    pad_retention_mmc2_option;
+       unsigned char   res109[0x14];
+       unsigned int    pad_retention_mmc3_configuration;
+       unsigned int    pad_retention_mmc3_status;
+       unsigned int    pad_retention_mmc3_option;
+       unsigned char   res110[0x14];
+       unsigned int    pad_retention_gpio_configuration;
+       unsigned int    pad_retention_gpio_status;
+       unsigned int    pad_retention_gpio_option;
+       unsigned char   res111[0x14];
+       unsigned int    pad_retention_uart_configuration;
+       unsigned int    pad_retention_uart_status;
+       unsigned int    pad_retention_uart_option;
+       unsigned char   res112[0x14];
+       unsigned int    pad_retention_mmc0_configuration;
+       unsigned int    pad_retention_mmc0_status;
+       unsigned int    pad_retention_mmc0_option;
+       unsigned char   res113[0x14];
+       unsigned int    pad_retention_mmc1_configuration;
+       unsigned int    pad_retention_mmc1_status;
+       unsigned int    pad_retention_mmc1_option;
+       unsigned char   res114[0x14];
+       unsigned int    pad_retention_ebia_configuration;
+       unsigned int    pad_retention_ebia_status;
+       unsigned int    pad_retention_ebia_option;
+       unsigned char   res115[0x14];
+       unsigned int    pad_retention_eb