Merge branch 'master' of git://git.denx.de/u-boot-arm
authorTom Rini <trini@ti.com>
Sat, 22 Dec 2012 12:55:19 +0000 (05:55 -0700)
committerTom Rini <trini@ti.com>
Sat, 22 Dec 2012 12:55:19 +0000 (05:55 -0700)
163 files changed:
MAINTAINERS
Makefile
README
arch/arm/cpu/arm1136/config.mk
arch/arm/cpu/arm1136/cpu.c
arch/arm/cpu/arm1136/mx35/Makefile
arch/arm/cpu/arm1136/mx35/generic.c
arch/arm/cpu/arm1136/mx35/mx35_sdram.c [new file with mode: 0644]
arch/arm/cpu/arm1136/start.S
arch/arm/cpu/arm1136/u-boot-spl.lds [new file with mode: 0644]
arch/arm/cpu/arm1176/s3c64xx/Makefile
arch/arm/cpu/arm1176/s3c64xx/init.c [new file with mode: 0644]
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
arch/arm/cpu/armv7/cache_v7.c
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/mx5/clock.c
arch/arm/cpu/armv7/mx5/lowlevel_init.S
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/s5p-common/Makefile
arch/arm/cpu/armv7/tegra20/Makefile
arch/arm/cpu/armv7/tegra20/display.c [new file with mode: 0644]
arch/arm/cpu/armv7/tegra20/pwm.c [new file with mode: 0644]
arch/arm/cpu/tegra20-common/funcmux.c
arch/arm/cpu/tegra20-common/pinmux.c
arch/arm/dts/tegra20.dtsi
arch/arm/imx-common/cpu.c
arch/arm/include/asm/arch-exynos/clk.h
arch/arm/include/asm/arch-exynos/clock.h
arch/arm/include/asm/arch-exynos/cpu.h
arch/arm/include/asm/arch-exynos/gpio.h
arch/arm/include/asm/arch-exynos/i2s-regs.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/periph.h
arch/arm/include/asm/arch-exynos/sound.h [new file with mode: 0644]
arch/arm/include/asm/arch-exynos/spi.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx25/imx-regs.h
arch/arm/include/asm/arch-mx25/sys_proto.h
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
arch/arm/include/asm/arch-mx35/mmc_host_def.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx35/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx35/sys_proto.h
arch/arm/include/asm/arch-mx5/mx5x_pins.h
arch/arm/include/asm/arch-mx5/sys_proto.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-mx6/mx6dl_pins.h [new file with mode: 0644]
arch/arm/include/asm/arch-mx6/sys_proto.h
arch/arm/include/asm/arch-mxs/imx-regs.h
arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
arch/arm/include/asm/arch-mxs/regs-power-mx28.h [moved from arch/arm/include/asm/arch-mxs/regs-power.h with 99% similarity]
arch/arm/include/asm/arch-s5pc1xx/gpio.h
arch/arm/include/asm/arch-tegra20/dc.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/display.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra20/pinmux.h
arch/arm/include/asm/arch-tegra20/pwm.h [new file with mode: 0644]
arch/arm/include/asm/system.h
arch/arm/lib/cache-cp15.c
board/compal/paz00/paz00.c
board/compulab/dts/tegra20-trimslice.dts
board/compulab/trimslice/trimslice.c
board/freescale/mx25pdk/mx25pdk.c
board/freescale/mx31ads/u-boot.lds
board/freescale/mx35pdk/lowlevel_init.S
board/freescale/mx35pdk/mx35pdk.c
board/freescale/mx53loco/mx53loco.c
board/nvidia/common/board.c
board/nvidia/dts/tegra20-seaboard.dts
board/nvidia/harmony/harmony.c
board/nvidia/seaboard/seaboard.c
board/samsung/smdk5250/Makefile
board/samsung/smdk5250/smdk5250.c
board/samsung/smdk5250/spl_boot.c [moved from board/samsung/smdk5250/mmc_boot.c with 66% similarity]
board/samsung/trats/trats.c
board/samsung/universal_c210/Makefile
board/samsung/universal_c210/lowlevel_init.S [deleted file]
board/samsung/universal_c210/universal.c
board/syteco/zmx25/zmx25.c
board/woodburn/Makefile [new file with mode: 0644]
board/woodburn/imximage.cfg [new file with mode: 0644]
board/woodburn/lowlevel_init.S [new file with mode: 0644]
board/woodburn/woodburn.c [new file with mode: 0644]
boards.cfg
common/Makefile
common/cmd_sound.c [new file with mode: 0644]
common/lcd.c
common/main.c
doc/README.imx5
doc/device-tree-bindings/pwm/tegra20-pwm.txt [new file with mode: 0644]
doc/device-tree-bindings/video/displaymode.txt [new file with mode: 0644]
doc/device-tree-bindings/video/tegra20-dc.txt [new file with mode: 0644]
drivers/gpio/mxc_gpio.c
drivers/gpio/s5p_gpio.c
drivers/input/tegra-kbc.c
drivers/mmc/tegra_mmc.c
drivers/power/pmic/Makefile
drivers/power/pmic/pmic_max77686.c [new file with mode: 0644]
drivers/power/power_fsl.c
drivers/serial/s3c64xx.c
drivers/sound/Makefile [new file with mode: 0644]
drivers/sound/samsung-i2s.c [new file with mode: 0644]
drivers/sound/sound.c [new file with mode: 0644]
drivers/sound/wm8994.c [new file with mode: 0644]
drivers/sound/wm8994.h [new file with mode: 0644]
drivers/sound/wm8994_registers.h [new file with mode: 0644]
drivers/spi/Makefile
drivers/spi/exynos_spi.c [new file with mode: 0644]
drivers/spi/mxc_spi.c
drivers/usb/host/ehci-mx5.c
drivers/usb/host/ehci-mx6.c
drivers/usb/host/ehci-mxc.c
drivers/video/Makefile
drivers/video/exynos_fb.c
drivers/video/ipu_regs.h
drivers/video/ld9040.c [new file with mode: 0644]
drivers/video/tegra.c [new file with mode: 0644]
drivers/watchdog/Makefile
drivers/watchdog/s5p_wdt.c [moved from arch/arm/cpu/armv7/s5p-common/wdt.c with 100% similarity]
include/configs/harmony.h
include/configs/mx25pdk.h
include/configs/mx28evk.h
include/configs/mx31pdk.h
include/configs/mx35pdk.h
include/configs/mx51_efikamx.h
include/configs/mx51evk.h
include/configs/mx53evk.h
include/configs/mx53loco.h
include/configs/mx6qarm2.h
include/configs/mx6qsabre_common.h
include/configs/mx6qsabrelite.h
include/configs/palmld.h
include/configs/palmtc.h
include/configs/paz00.h
include/configs/s5pc210_universal.h
include/configs/seaboard.h
include/configs/smdk5250.h
include/configs/tec.h
include/configs/tegra-common-post.h
include/configs/tegra20-common.h
include/configs/trats.h
include/configs/trimslice.h
include/configs/ventana.h
include/configs/vision2.h
include/configs/whistler.h
include/configs/woodburn.h [new file with mode: 0644]
include/configs/woodburn_common.h [new file with mode: 0644]
include/configs/woodburn_sd.h [new file with mode: 0644]
include/configs/zipitz2.h
include/configs/zmx25.h
include/fdtdec.h
include/i2s.h [new file with mode: 0644]
include/lcd.h
include/ld9040.h [new file with mode: 0644]
include/mc34704.h [new file with mode: 0644]
include/power/max77686_pmic.h [new file with mode: 0644]
include/power/max8998_pmic.h
include/sound.h [new file with mode: 0644]
include/usb/ehci-fsl.h
lib/fdtdec.c
nand_spl/board/freescale/mx31pdk/u-boot.lds
spl/Makefile

index 2fc81cf..28c052d 100644 (file)
@@ -586,6 +586,7 @@ Stefano Babic <sbabic@denx.de>
        trizepsiv       xscale/pxa
        twister         omap3
        vision2         i.MX51
+       woodburn        i.MX35
 
 Lukasz Dalek <luk0104@gmail.com>
 
index 9d43499..a7b6cd1 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -316,6 +316,7 @@ LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
 endif
 LIBS-y += drivers/rtc/librtc.o
 LIBS-y += drivers/serial/libserial.o
+LIBS-y += drivers/sound/libsound.o
 LIBS-$(CONFIG_GENERIC_LPC_TPM) += drivers/tpm/libtpm.o
 LIBS-y += drivers/twserial/libtws.o
 LIBS-y += drivers/usb/eth/libusb_eth.o
@@ -510,7 +511,7 @@ $(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
 ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
 
 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
-               elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
+               elftosb -zf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \
                        -o $(obj)u-boot.sb
 
 # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL.
@@ -869,6 +870,7 @@ clobber:    tidy
        @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
        @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
        @rm -f $(obj)MLO
+       @rm -f $(obj)SPL
        @rm -f $(obj)tools/xway-swap-bytes
        @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
        @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c
diff --git a/README b/README
index 1d2e129..78f40df 100644 (file)
--- a/README
+++ b/README
@@ -1486,6 +1486,21 @@ CBFS (Coreboot Filesystem) support
                Normally display is black on white background; define
                CONFIG_SYS_WHITE_ON_BLACK to get it inverted.
 
+               CONFIG_LCD_ALIGNMENT
+
+               Normally the LCD is page-aligned (tyically 4KB). If this is
+               defined then the LCD will be aligned to this value instead.
+               For ARM it is sometimes useful to use MMU_SECTION_SIZE
+               here, since it is cheaper to change data cache settings on
+               a per-section basis.
+
+               CONFIG_CONSOLE_SCROLL_LINES
+
+               When the console need to be scrolled, this is the number of
+               lines to scroll by. It defaults to 1. Increasing this makes
+               the console jump but can help speed up operation when scrolling
+               is slow.
+
                CONFIG_LCD_BMP_RLE8
 
                Support drawing of RLE8-compressed bitmaps on the LCD.
@@ -1495,7 +1510,6 @@ CBFS (Coreboot Filesystem) support
                Enables an 'i2c edid' command which can read EDID
                information over I2C from an attached LCD display.
 
-
 - Splash Screen Support: CONFIG_SPLASH_SCREEN
 
                If this option is set, the environment is checked for
index efee0d1..9092d91 100644 (file)
@@ -31,3 +31,6 @@ PLATFORM_CPPFLAGS += -march=armv5
 # =========================================================================
 PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
 PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+ifdef CONFIG_SPL_BUILD
+ALL-y  += $(OBJTREE)/SPL
+endif
index b98e3d9..32a4c24 100644 (file)
@@ -141,16 +141,6 @@ void flush_cache(unsigned long start, unsigned long size)
        flush_dcache_range(start, start + size);
 }
 
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
-       icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-       dcache_enable();
-#endif
-}
-
 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
 void invalidate_dcache_all(void)
 {
@@ -172,3 +162,15 @@ void flush_cache(unsigned long start, unsigned long size)
 {
 }
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       dcache_enable();
+#endif
+}
+#endif
index 469397c..f4ababb 100644 (file)
@@ -30,6 +30,7 @@ LIB   = $(obj)lib$(SOC).o
 COBJS  += generic.o
 COBJS  += timer.o
 COBJS  += iomux.o
+COBJS  += mx35_sdram.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
index 41e9639..98aa4d1 100644 (file)
@@ -35,6 +35,7 @@
 #include <fsl_esdhc.h>
 #endif
 #include <netdev.h>
+#include <spl.h>
 
 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
 #define CLK_CODE_ARM(c)                (((c) >> 16) & 0xFF)
@@ -492,3 +493,77 @@ void reset_cpu(ulong addr)
        struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
        writew(4, &wdog->wcr);
 }
+
+#define RCSR_MEM_CTL_WEIM      0
+#define RCSR_MEM_CTL_NAND      1
+#define RCSR_MEM_CTL_ATA       2
+#define RCSR_MEM_CTL_EXPANSION 3
+#define RCSR_MEM_TYPE_NOR      0
+#define RCSR_MEM_TYPE_ONENAND  2
+#define RCSR_MEM_TYPE_SD       0
+#define RCSR_MEM_TYPE_I2C      2
+#define RCSR_MEM_TYPE_SPI      3
+
+u32 spl_boot_device(void)
+{
+       struct ccm_regs *ccm =
+               (struct ccm_regs *)IMX_CCM_BASE;
+
+       u32 rcsr = readl(&ccm->rcsr);
+       u32 mem_type, mem_ctl;
+
+       /* In external mode, no boot device is returned */
+       if ((rcsr >> 10) & 0x03)
+               return BOOT_DEVICE_NONE;
+
+       mem_ctl = (rcsr >> 25) & 0x03;
+       mem_type = (rcsr >> 23) & 0x03;
+
+       switch (mem_ctl) {
+       case RCSR_MEM_CTL_WEIM:
+               switch (mem_type) {
+               case RCSR_MEM_TYPE_NOR:
+                       return BOOT_DEVICE_NOR;
+               case RCSR_MEM_TYPE_ONENAND:
+                       return BOOT_DEVICE_ONE_NAND;
+               default:
+                       return BOOT_DEVICE_NONE;
+               }
+       case RCSR_MEM_CTL_NAND:
+               return BOOT_DEVICE_NAND;
+       case RCSR_MEM_CTL_EXPANSION:
+               switch (mem_type) {
+               case RCSR_MEM_TYPE_SD:
+                       return BOOT_DEVICE_MMC1;
+               case RCSR_MEM_TYPE_I2C:
+                       return BOOT_DEVICE_I2C;
+               case RCSR_MEM_TYPE_SPI:
+                       return BOOT_DEVICE_SPI;
+               default:
+                       return BOOT_DEVICE_NONE;
+               }
+       }
+
+       return BOOT_DEVICE_NONE;
+}
+
+#ifdef CONFIG_SPL_BUILD
+u32 spl_boot_mode(void)
+{
+       switch (spl_boot_device()) {
+       case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+               return MMCSD_MODE_FAT;
+#else
+               return MMCSD_MODE_RAW;
+#endif
+               break;
+       case BOOT_DEVICE_NAND:
+               return 0;
+               break;
+       default:
+               puts("spl: ERROR:  unsupported device\n");
+               hang();
+       }
+}
+#endif
diff --git a/arch/arm/cpu/arm1136/mx35/mx35_sdram.c b/arch/arm/cpu/arm1136/mx35/mx35_sdram.c
new file mode 100644 (file)
index 0000000..f7e682c
--- /dev/null
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+
+#define ESDCTL_DDR2_EMR2       0x04000000
+#define ESDCTL_DDR2_EMR3       0x06000000
+#define ESDCTL_PRECHARGE       0x00000400
+#define ESDCTL_DDR2_EN_DLL     0x02000400
+#define ESDCTL_DDR2_RESET_DLL  0x00000333
+#define ESDCTL_DDR2_MR         0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+
+enum {
+       SMODE_NORMAL =  0,
+       SMODE_PRECHARGE,
+       SMODE_AUTO_REFRESH,
+       SMODE_LOAD_REG,
+       SMODE_MANUAL_REFRESH
+};
+
+#define set_mode(x, en, m)     (x | (en << 31) | (m << 28))
+
+static inline void dram_wait(unsigned int count)
+{
+       volatile unsigned int wait = count;
+
+       while (wait--)
+               ;
+
+}
+
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+       u32 row, u32 col, u32 dsize, u32 refresh)
+{
+       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+       u32 *cfg_reg, *ctl_reg;
+       u32 val;
+       u32 ctlval;
+
+       switch (start_address) {
+       case CSD0_BASE_ADDR:
+               cfg_reg = &esdc->esdcfg0;
+               ctl_reg = &esdc->esdctl0;
+               break;
+       case CSD1_BASE_ADDR:
+               cfg_reg = &esdc->esdcfg1;
+               ctl_reg = &esdc->esdctl1;
+               break;
+       default:
+               return;
+       }
+
+       /* The MX35 supports 11 up to 14 rows */
+       if (row < 11 || row > 14 || col < 8 || col > 10)
+               return;
+       ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
+
+       /* Initialize MISC register for DDR2 */
+       val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+               ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+       writel(val, &esdc->esdmisc);
+       val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+       writel(val, &esdc->esdmisc);
+
+       /*
+        * according to DDR2 specs, wait a while before
+        * the PRECHARGE_ALL command
+        */
+       dram_wait(0x20000);
+
+       /* Load DDR2 config and timing */
+       writel(ddr2_config, cfg_reg);
+
+       /* Precharge ALL */
+       writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+               ctl_reg);
+       writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+       /* Load mode */
+       writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+               ctl_reg);
+       writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+       writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+       writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+       /* Precharge ALL */
+       writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
+               ctl_reg);
+       writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+       /* Set mode auto refresh : at least two refresh are required */
+       writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
+               ctl_reg);
+       writel(0xda, start_address);
+       writel(0xda, start_address);
+
+       writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
+               ctl_reg);
+       writeb(0xda, start_address + ESDCTL_DDR2_MR);
+       writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+       /* OCD mode exit */
+       writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+       /* Set normal mode */
+       writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
+               ctl_reg);
+
+       dram_wait(0x20000);
+
+       /* Do not set delay lines, only for MDDR */
+}
index 3752af9..5d3b4c2 100644 (file)
@@ -100,6 +100,10 @@ _TEXT_BASE:
 _bss_start_ofs:
        .word __bss_start - _start
 
+.global        _image_copy_end_ofs
+_image_copy_end_ofs:
+       .word   __image_copy_end - _start
+
 .globl _bss_end_ofs
 _bss_end_ofs:
        .word __bss_end__ - _start
@@ -193,7 +197,7 @@ stack_setup:
        moveq   r9, #0          /* no relocation. relocation offset(r9) = 0 */
        beq     clear_bss               /* skip relocation */
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r3, _bss_start_ofs
+       ldr     r3, _image_copy_end_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
 
 copy_loop:
@@ -241,15 +245,28 @@ fixnext:
        add     r2, r2, #8              /* each rel.dyn entry is 8 bytes */
        cmp     r2, r3
        blo     fixloop
+       b       clear_bss
+
+_rel_dyn_start_ofs:
+       .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+       .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+       .word __dynsym_start - _start
 #endif
 
 clear_bss:
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_BUILD
+       /* No relocation for SPL */
+       ldr     r0, =__bss_start
+       ldr     r1, =__bss_end__
+#else
        ldr     r0, _bss_start_ofs
        ldr     r1, _bss_end_ofs
        mov     r4, r6                  /* reloc addr */
        add     r0, r0, r4
        add     r1, r1, r4
+#endif
        mov     r2, #0x00000000         /* clear                            */
 
 clbss_l:cmp    r0, r1                  /* clear loop... */
@@ -258,7 +275,6 @@ clbss_l:cmp r0, r1                  /* clear loop... */
        add     r0, r0, #4
        b       clbss_l
 clbss_e:
-#endif /* #ifndef CONFIG_SPL_BUILD */
 
 /*
  * We are done. Do not return, instead branch to second part of board
@@ -273,7 +289,7 @@ _nand_boot_ofs:
 #else
 jump_2_ram:
        ldr     r0, _board_init_r_ofs
-       ldr     r1, _TEXT_BASE
+       adr     r1, _start
        add     lr, r0, r1
        add     lr, lr, r9
        /* setup parameters for board_init_r */
@@ -286,13 +302,6 @@ _board_init_r_ofs:
        .word board_init_r - _start
 #endif
 
-_rel_dyn_start_ofs:
-       .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-       .word __rel_dyn_end - _start
-_dynsym_start_ofs:
-       .word __dynsym_start - _start
-
 /*
  *************************************************************************
  *
diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds
new file mode 100644 (file)
index 0000000..a0462ab
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *     Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+               LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+               LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       .text      :
+       {
+       __start = .;
+         arch/arm/cpu/arm1136/start.o  (.text)
+         *(.text*)
+       } >.sram
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+       . = ALIGN(4);
+       .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+       . = ALIGN(4);
+       __image_copy_end = .;
+       _end = .;
+
+       .bss :
+       {
+               . = ALIGN(4);
+               __bss_start = .;
+               *(.bss*)
+               . = ALIGN(4);
+               __bss_end__ = .;
+       } >.sdram
+}
index 0785b19..266a073 100644 (file)
@@ -31,7 +31,7 @@ LIB   = $(obj)lib$(SOC).o
 SOBJS  = reset.o
 
 COBJS-$(CONFIG_S3C6400)        += cpu_init.o speed.o
-COBJS-y        += timer.o
+COBJS-y        += timer.o init.o
 
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
 
diff --git a/arch/arm/cpu/arm1176/s3c64xx/init.c b/arch/arm/cpu/arm1176/s3c64xx/init.c
new file mode 100644 (file)
index 0000000..f113d8e
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2012 Ashok Kumar Reddy Kourla
+ * ashokkourla2000@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include<common.h>
+
+int arch_cpu_init(void)
+{
+       icache_enable();
+
+       return 0;
+}
index 8ea7c36..1b8502e 100644 (file)
@@ -50,7 +50,7 @@ void early_delay(int delay)
 }
 
 #define        MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-const iomux_cfg_t iomux_boot[] = {
+static const iomux_cfg_t iomux_boot[] = {
        MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
        MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
        MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
@@ -59,7 +59,7 @@ const iomux_cfg_t iomux_boot[] = {
        MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
 };
 
-uint8_t mxs_get_bootmode_index(void)
+static uint8_t mxs_get_bootmode_index(void)
 {
        uint8_t bootmode = 0;
        int i;
index e693145..401c513 100644 (file)
 
 #include "mxs_init.h"
 
-static uint32_t mx28_dram_vals[] = {
+static uint32_t dram_vals[] = {
+/*
+ * i.MX28 DDR2 at 200MHz
+ */
+#if defined(CONFIG_MX28)
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -79,6 +83,9 @@ static uint32_t mx28_dram_vals[] = {
        0x06120612, 0x04320432, 0x04320432, 0x00040004,
        0x00040004, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00010001
+#else
+#error Unsupported memory initialization
+#endif
 };
 
 void __mxs_adjust_memory_params(uint32_t *dram_vals)
@@ -87,17 +94,17 @@ void __mxs_adjust_memory_params(uint32_t *dram_vals)
 void mxs_adjust_memory_params(uint32_t *dram_vals)
        __attribute__((weak, alias("__mxs_adjust_memory_params")));
 
-void init_mx28_200mhz_ddr2(void)
+static void initialize_dram_values(void)
 {
        int i;
 
-       mxs_adjust_memory_params(mx28_dram_vals);
+       mxs_adjust_memory_params(dram_vals);
 
-       for (i = 0; i < ARRAY_SIZE(mx28_dram_vals); i++)
-               writel(mx28_dram_vals[i], MXS_DRAM_BASE + (4 * i));
+       for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
+               writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
 }
 
-void mxs_mem_init_clock(void)
+static void mxs_mem_init_clock(void)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -128,7 +135,7 @@ void mxs_mem_init_clock(void)
        early_delay(10000);
 }
 
-void mxs_mem_setup_cpu_and_hbus(void)
+static void mxs_mem_setup_cpu_and_hbus(void)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -160,7 +167,7 @@ void mxs_mem_setup_cpu_and_hbus(void)
        early_delay(15000);
 }
 
-void mxs_mem_setup_vdda(void)
+static void mxs_mem_setup_vdda(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -171,17 +178,6 @@ void mxs_mem_setup_vdda(void)
                &power_regs->hw_power_vddactrl);
 }
 
-void mxs_mem_setup_vddd(void)
-{
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
-
-       writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
-               (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
-               POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
-               &power_regs->hw_power_vdddctrl);
-}
-
 uint32_t mxs_mem_get_size(void)
 {
        uint32_t sz, da;
@@ -229,7 +225,7 @@ void mxs_mem_init(void)
        /* Clear START bit from DRAM_CTL16 */
        clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
 
-       init_mx28_200mhz_ddr2();
+       initialize_dram_values();
 
        /* Clear SREFRESH bit from DRAM_CTL17 */
        clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
@@ -241,8 +237,6 @@ void mxs_mem_init(void)
        while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
                ;
 
-       mxs_mem_setup_vddd();
-
        early_delay(10000);
 
        mxs_mem_setup_cpu_and_hbus();
index 4b917bd..be44c22 100644 (file)
@@ -30,7 +30,7 @@
 
 #include "mxs_init.h"
 
-void mxs_power_clock2xtal(void)
+static void mxs_power_clock2xtal(void)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -40,7 +40,7 @@ void mxs_power_clock2xtal(void)
                &clkctrl_regs->hw_clkctrl_clkseq_set);
 }
 
-void mxs_power_clock2pll(void)
+static void mxs_power_clock2pll(void)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@@ -52,7 +52,7 @@ void mxs_power_clock2pll(void)
                        CLKCTRL_CLKSEQ_BYPASS_CPU);
 }
 
-void mxs_power_clear_auto_restart(void)
+static void mxs_power_clear_auto_restart(void)
 {
        struct mxs_rtc_regs *rtc_regs =
                (struct mxs_rtc_regs *)MXS_RTC_BASE;
@@ -85,7 +85,7 @@ void mxs_power_clear_auto_restart(void)
                ;
 }
 
-void mxs_power_set_linreg(void)
+static void mxs_power_set_linreg(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -104,7 +104,7 @@ void mxs_power_set_linreg(void)
                        POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 }
 
-int mxs_get_batt_volt(void)
+static int mxs_get_batt_volt(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -115,12 +115,12 @@ int mxs_get_batt_volt(void)
        return volt;
 }
 
-int mxs_is_batt_ready(void)
+static int mxs_is_batt_ready(void)
 {
        return (mxs_get_batt_volt() >= 3600);
 }
 
-int mxs_is_batt_good(void)
+static int mxs_is_batt_good(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -160,7 +160,7 @@ int mxs_is_batt_good(void)
        return 0;
 }
 
-void mxs_power_setup_5v_detect(void)
+static void mxs_power_setup_5v_detect(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -172,7 +172,7 @@ void mxs_power_setup_5v_detect(void)
                        POWER_5VCTRL_PWRUP_VBUS_CMPS);
 }
 
-void mxs_src_power_init(void)
+static void mxs_src_power_init(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -203,7 +203,7 @@ void mxs_src_power_init(void)
        clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 }
 
-void mxs_power_init_4p2_params(void)
+static void mxs_power_init_4p2_params(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -227,7 +227,7 @@ void mxs_power_init_4p2_params(void)
                0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
-void mxs_enable_4p2_dcdc_input(int xfer)
+static void mxs_enable_4p2_dcdc_input(int xfer)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -323,7 +323,7 @@ void mxs_enable_4p2_dcdc_input(int xfer)
                                POWER_CTRL_ENIRQ_VDD5V_DROOP);
 }
 
-void mxs_power_init_4p2_regulator(void)
+static void mxs_power_init_4p2_regulator(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -407,7 +407,7 @@ void mxs_power_init_4p2_regulator(void)
        writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 }
 
-void mxs_power_init_dcdc_4p2_source(void)
+static void mxs_power_init_dcdc_4p2_source(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -429,7 +429,7 @@ void mxs_power_init_dcdc_4p2_source(void)
        }
 }
 
-void mxs_power_enable_4p2(void)
+static void mxs_power_enable_4p2(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -488,7 +488,7 @@ void mxs_power_enable_4p2(void)
                        &power_regs->hw_power_charge_clr);
 }
 
-void mxs_boot_valid_5v(void)
+static void mxs_boot_valid_5v(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -511,7 +511,7 @@ void mxs_boot_valid_5v(void)
        mxs_power_enable_4p2();
 }
 
-void mxs_powerdown(void)
+static void mxs_powerdown(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -520,7 +520,7 @@ void mxs_powerdown(void)
                &power_regs->hw_power_reset);
 }
 
-void mxs_batt_boot(void)
+static void mxs_batt_boot(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -564,7 +564,7 @@ void mxs_batt_boot(void)
                0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 }
 
-void mxs_handle_5v_conflict(void)
+static void mxs_handle_5v_conflict(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -600,7 +600,7 @@ void mxs_handle_5v_conflict(void)
        }
 }
 
-void mxs_5v_boot(void)
+static void mxs_5v_boot(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -623,7 +623,7 @@ void mxs_5v_boot(void)
        mxs_handle_5v_conflict();
 }
 
-void mxs_init_batt_bo(void)
+static void mxs_init_batt_bo(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -637,7 +637,7 @@ void mxs_init_batt_bo(void)
        writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 }
 
-void mxs_switch_vddd_to_dcdc_source(void)
+static void mxs_switch_vddd_to_dcdc_source(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -651,7 +651,7 @@ void mxs_switch_vddd_to_dcdc_source(void)
                POWER_VDDDCTRL_DISABLE_STEPPING);
 }
 
-void mxs_power_configure_power_source(void)
+static void mxs_power_configure_power_source(void)
 {
        int batt_ready, batt_good;
        struct mxs_power_regs *power_regs =
@@ -689,7 +689,7 @@ void mxs_power_configure_power_source(void)
        mxs_switch_vddd_to_dcdc_source();
 }
 
-void mxs_enable_output_rail_protection(void)
+static void mxs_enable_output_rail_protection(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -707,7 +707,7 @@ void mxs_enable_output_rail_protection(void)
                        POWER_VDDIOCTRL_PWDN_BRNOUT);
 }
 
-int mxs_get_vddio_power_source_off(void)
+static int mxs_get_vddio_power_source_off(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -735,7 +735,7 @@ int mxs_get_vddio_power_source_off(void)
 
 }
 
-int mxs_get_vddd_power_source_off(void)
+static int mxs_get_vddd_power_source_off(void)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
@@ -766,201 +766,115 @@ int mxs_get_vddd_power_source_off(void)
        return 0;
 }
 
-void mxs_power_set_vddio(uint32_t new_target, uint32_t new_brownout)
+struct mxs_vddx_cfg {
+       uint32_t                *reg;
+       uint8_t                 step_mV;
+       uint16_t                lowest_mV;
+       int                     (*powered_by_linreg)(void);
+       uint32_t                trg_mask;
+       uint32_t                bo_irq;
+       uint32_t                bo_enirq;
+       uint32_t                bo_offset_mask;
+       uint32_t                bo_offset_offset;
+};
+
+static const struct mxs_vddx_cfg mxs_vddio_cfg = {
+       .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+                                       hw_power_vddioctrl),
+       .step_mV                = 50,
+       .lowest_mV              = 2800,
+       .powered_by_linreg      = mxs_get_vddio_power_source_off,
+       .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
+       .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
+       .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
+       .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
+       .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
+};
+
+static const struct mxs_vddx_cfg mxs_vddd_cfg = {
+       .reg                    = &(((struct mxs_power_regs *)MXS_POWER_BASE)->
+                                       hw_power_vdddctrl),
+       .step_mV                = 25,
+       .lowest_mV              = 800,
+       .powered_by_linreg      = mxs_get_vddd_power_source_off,
+       .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
+       .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
+       .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
+       .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
+       .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
+};
+
+static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
+                               uint32_t new_target, uint32_t new_brownout)
 {
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
        uint32_t cur_target, diff, bo_int = 0;
        uint32_t powered_by_linreg = 0;
+       int adjust_up, tmp;
 
-       new_brownout = (new_target - new_brownout + 25) / 50;
+       new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV);
 
-       cur_target = readl(&power_regs->hw_power_vddioctrl);
-       cur_target &= POWER_VDDIOCTRL_TRG_MASK;
-       cur_target *= 50;       /* 50 mV step*/
-       cur_target += 2800;     /* 2800 mV lowest */
+       cur_target = readl(cfg->reg);
+       cur_target &= cfg->trg_mask;
+       cur_target *= cfg->step_mV;
+       cur_target += cfg->lowest_mV;
 
-       powered_by_linreg = mxs_get_vddio_power_source_off();
-       if (new_target > cur_target) {
+       adjust_up = new_target > cur_target;
+       powered_by_linreg = cfg->powered_by_linreg();
 
+       if (adjust_up) {
                if (powered_by_linreg) {
-                       bo_int = readl(&power_regs->hw_power_vddioctrl);
-                       clrbits_le32(&power_regs->hw_power_vddioctrl,
-                                       POWER_CTRL_ENIRQ_VDDIO_BO);
+                       bo_int = readl(cfg->reg);
+                       clrbits_le32(cfg->reg, cfg->bo_enirq);
                }
+               setbits_le32(cfg->reg, cfg->bo_offset_mask);
+       }
 
-               setbits_le32(&power_regs->hw_power_vddioctrl,
-                               POWER_VDDIOCTRL_BO_OFFSET_MASK);
-               do {
-                       if (new_target - cur_target > 100)
+       do {
+               if (abs(new_target - cur_target) > 100) {
+                       if (adjust_up)
                                diff = cur_target + 100;
                        else
-                               diff = new_target;
-
-                       diff -= 2800;
-                       diff /= 50;
-
-                       clrsetbits_le32(&power_regs->hw_power_vddioctrl,
-                               POWER_VDDIOCTRL_TRG_MASK, diff);
-
-                       if (powered_by_linreg ||
-                               (readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(500);
-                       else {
-                               while (!(readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_DC_OK))
-                                       ;
-
-                       }
-
-                       cur_target = readl(&power_regs->hw_power_vddioctrl);
-                       cur_target &= POWER_VDDIOCTRL_TRG_MASK;
-                       cur_target *= 50;       /* 50 mV step*/
-                       cur_target += 2800;     /* 2800 mV lowest */
-               } while (new_target > cur_target);
-
-               if (powered_by_linreg) {
-                       writel(POWER_CTRL_VDDIO_BO_IRQ,
-                               &power_regs->hw_power_ctrl_clr);
-                       if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
-                               setbits_le32(&power_regs->hw_power_vddioctrl,
-                                               POWER_CTRL_ENIRQ_VDDIO_BO);
-               }
-       } else {
-               do {
-                       if (cur_target - new_target > 100)
                                diff = cur_target - 100;
-                       else
-                               diff = new_target;
-
-                       diff -= 2800;
-                       diff /= 50;
-
-                       clrsetbits_le32(&power_regs->hw_power_vddioctrl,
-                               POWER_VDDIOCTRL_TRG_MASK, diff);
-
-                       if (powered_by_linreg ||
-                               (readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(500);
-                       else {
-                               while (!(readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_DC_OK))
-                                       ;
-
-                       }
-
-                       cur_target = readl(&power_regs->hw_power_vddioctrl);
-                       cur_target &= POWER_VDDIOCTRL_TRG_MASK;
-                       cur_target *= 50;       /* 50 mV step*/
-                       cur_target += 2800;     /* 2800 mV lowest */
-               } while (new_target < cur_target);
-       }
-
-       clrsetbits_le32(&power_regs->hw_power_vddioctrl,
-                       POWER_VDDIOCTRL_BO_OFFSET_MASK,
-                       new_brownout << POWER_VDDIOCTRL_BO_OFFSET_OFFSET);
-}
-
-void mxs_power_set_vddd(uint32_t new_target, uint32_t new_brownout)
-{
-       struct mxs_power_regs *power_regs =
-               (struct mxs_power_regs *)MXS_POWER_BASE;
-       uint32_t cur_target, diff, bo_int = 0;
-       uint32_t powered_by_linreg = 0;
-
-       new_brownout = (new_target - new_brownout + 12) / 25;
-
-       cur_target = readl(&power_regs->hw_power_vdddctrl);
-       cur_target &= POWER_VDDDCTRL_TRG_MASK;
-       cur_target *= 25;       /* 25 mV step*/
-       cur_target += 800;      /* 800 mV lowest */
-
-       powered_by_linreg = mxs_get_vddd_power_source_off();
-       if (new_target > cur_target) {
-               if (powered_by_linreg) {
-                       bo_int = readl(&power_regs->hw_power_vdddctrl);
-                       clrbits_le32(&power_regs->hw_power_vdddctrl,
-                                       POWER_CTRL_ENIRQ_VDDD_BO);
+               } else {
+                       diff = new_target;
                }
 
-               setbits_le32(&power_regs->hw_power_vdddctrl,
-                               POWER_VDDDCTRL_BO_OFFSET_MASK);
-
-               do {
-                       if (new_target - cur_target > 100)
-                               diff = cur_target + 100;
-                       else
-                               diff = new_target;
-
-                       diff -= 800;
-                       diff /= 25;
-
-                       clrsetbits_le32(&power_regs->hw_power_vdddctrl,
-                               POWER_VDDDCTRL_TRG_MASK, diff);
+               diff -= cfg->lowest_mV;
+               diff /= cfg->step_mV;
 
-                       if (powered_by_linreg ||
-                               (readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(500);
-                       else {
-                               while (!(readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_DC_OK))
-                                       ;
+               clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
 
+               if (powered_by_linreg ||
+                       (readl(&power_regs->hw_power_sts) &
+                               POWER_STS_VDD5V_GT_VDDIO))
+                       early_delay(500);
+               else {
+                       for (;;) {
+                               tmp = readl(&power_regs->hw_power_sts);
+                               if (tmp & POWER_STS_DC_OK)
+                                       break;
                        }
-
-                       cur_target = readl(&power_regs->hw_power_vdddctrl);
-                       cur_target &= POWER_VDDDCTRL_TRG_MASK;
-                       cur_target *= 25;       /* 25 mV step*/
-                       cur_target += 800;      /* 800 mV lowest */
-               } while (new_target > cur_target);
-
-               if (powered_by_linreg) {
-                       writel(POWER_CTRL_VDDD_BO_IRQ,
-                               &power_regs->hw_power_ctrl_clr);
-                       if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
-                               setbits_le32(&power_regs->hw_power_vdddctrl,
-                                               POWER_CTRL_ENIRQ_VDDD_BO);
                }
-       } else {
-               do {
-                       if (cur_target - new_target > 100)
-                               diff = cur_target - 100;
-                       else
-                               diff = new_target;
 
-                       diff -= 800;
-                       diff /= 25;
+               cur_target = readl(cfg->reg);
+               cur_target &= cfg->trg_mask;
+               cur_target *= cfg->step_mV;
+               cur_target += cfg->lowest_mV;
+       } while (new_target > cur_target);
 
-                       clrsetbits_le32(&power_regs->hw_power_vdddctrl,
-                                       POWER_VDDDCTRL_TRG_MASK, diff);
-
-                       if (powered_by_linreg ||
-                               (readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_VDD5V_GT_VDDIO))
-                               early_delay(500);
-                       else {
-                               while (!(readl(&power_regs->hw_power_sts) &
-                                       POWER_STS_DC_OK))
-                                       ;
-
-                       }
-
-                       cur_target = readl(&power_regs->hw_power_vdddctrl);
-                       cur_target &= POWER_VDDDCTRL_TRG_MASK;
-                       cur_target *= 25;       /* 25 mV step*/
-                       cur_target += 800;      /* 800 mV lowest */
-               } while (new_target < cur_target);
+       if (adjust_up && powered_by_linreg) {
+               writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
+               if (bo_int & cfg->bo_enirq)
+                       setbits_le32(cfg->reg, cfg->bo_enirq);
        }
 
-       clrsetbits_le32(&power_regs->hw_power_vdddctrl,
-                       POWER_VDDDCTRL_BO_OFFSET_MASK,
-                       new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET);
+       clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
+                       new_brownout << cfg->bo_offset_offset);
 }
 
-void mxs_setup_batt_detect(void)
+static void mxs_setup_batt_detect(void)
 {
        mxs_lradc_init();
        mxs_lradc_enable_batt_measurement();
@@ -982,9 +896,8 @@ void mxs_power_init(void)
        mxs_power_configure_power_source();
        mxs_enable_output_rail_protection();
 
-       mxs_power_set_vddio(3300, 3150);
-
-       mxs_power_set_vddd(1350, 1200);
+       mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150);
+       mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000);
 
        writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
                POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
index 1b4e808..5f6d039 100644 (file)
@@ -297,6 +297,12 @@ void arm_init_before_mmu(void)
        v7_inval_tlb();
 }
 
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+       flush_dcache_range(start, stop);
+       v7_inval_tlb();
+}
+
 /*
  * Flush range from all levels of d-cache/unified-cache used:
  * Affects the range [start, start + size - 1]
@@ -329,6 +335,11 @@ void arm_init_before_mmu(void)
 void  flush_cache(unsigned long start, unsigned long size)
 {
 }
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF
index 21e45d2..7459979 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
-
-/* exynos4: return pll clock frequency */
-static unsigned long exynos4_get_pll_clk(int pllreg)
+#include <asm/arch/periph.h>
+
+/* Epll Clock division values to achive different frequency output */
+static struct set_epll_con_val exynos5_epll_div[] = {
+       { 192000000, 0, 48, 3, 1, 0 },
+       { 180000000, 0, 45, 3, 1, 0 },
+       {  73728000, 1, 73, 3, 3, 47710 },
+       {  67737600, 1, 90, 4, 3, 20762 },
+       {  49152000, 0, 49, 3, 3, 9961 },
+       {  45158400, 0, 45, 3, 3, 10381 },
+       { 180633600, 0, 45, 3, 1, 10381 }
+};
+
+/* exynos: return pll clock frequency */
+static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 {
-       struct exynos4_clock *clk =
-               (struct exynos4_clock *)samsung_get_base_clock();
-       unsigned long r, m, p, s, k = 0, mask, fout;
+       unsigned long m, p, s = 0, mask, fout;
        unsigned int freq;
-
-       switch (pllreg) {
-       case APLL:
-               r = readl(&clk->apll_con0);
-               break;
-       case MPLL:
-               r = readl(&clk->mpll_con0);
-               break;
-       case EPLL:
-               r = readl(&clk->epll_con0);
-               k = readl(&clk->epll_con1);
-               break;
-       case VPLL:
-               r = readl(&clk->vpll_con0);
-               k = readl(&clk->vpll_con1);
-               break;
-       default:
-               printf("Unsupported PLL (%d)\n", pllreg);
-               return 0;
-       }
-
        /*
         * APLL_CON: MIDV [25:16]
         * MPLL_CON: MIDV [25:16]
         * EPLL_CON: MIDV [24:16]
         * VPLL_CON: MIDV [24:16]
+        * BPLL_CON: MIDV [25:16]: Exynos5
         */
-       if (pllreg == APLL || pllreg == MPLL)
+       if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
                mask = 0x3ff;
        else
                mask = 0x1ff;
@@ -92,13 +82,43 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
        return fout;
 }
 
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+       struct exynos4_clock *clk =
+               (struct exynos4_clock *)samsung_get_base_clock();
+       unsigned long r, k = 0;
+
+       switch (pllreg) {
+       case APLL:
+               r = readl(&clk->apll_con0);
+               break;
+       case MPLL:
+               r = readl(&clk->mpll_con0);
+               break;
+       case EPLL:
+               r = readl(&clk->epll_con0);
+               k = readl(&clk->epll_con1);
+               break;
+       case VPLL:
+               r = readl(&clk->vpll_con0);
+               k = readl(&clk->vpll_con1);
+               break;
+       default:
+               printf("Unsupported PLL (%d)\n", pllreg);
+               return 0;
+       }
+
+       return exynos_get_pll_clk(pllreg, r, k);
+}
+
 /* exynos5: return pll clock frequency */
 static unsigned long exynos5_get_pll_clk(int pllreg)
 {
        struct exynos5_clock *clk =
                (struct exynos5_clock *)samsung_get_base_clock();
-       unsigned long r, m, p, s, k = 0, mask, fout;
-       unsigned int freq, pll_div2_sel, fout_sel;
+       unsigned long r, k = 0, fout;
+       unsigned int pll_div2_sel, fout_sel;
 
        switch (pllreg) {
        case APLL:
@@ -123,41 +143,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
                return 0;
        }
 
-       /*
-        * APLL_CON: MIDV [25:16]
-        * MPLL_CON: MIDV [25:16]
-        * EPLL_CON: MIDV [24:16]
-        * VPLL_CON: MIDV [24:16]
-        * BPLL_CON: MIDV [25:16]
-        */
-       if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
-               mask = 0x3ff;
-       else
-               mask = 0x1ff;
-
-       m = (r >> 16) & mask;
-
-       /* PDIV [13:8] */
-       p = (r >> 8) & 0x3f;
-       /* SDIV [2:0] */
-       s = r & 0x7;
-
-       freq = CONFIG_SYS_CLK_FREQ;
-
-       if (pllreg == EPLL) {
-               k = k & 0xffff;
-               /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 65536) * (freq / (p * (1 << s)));
-       } else if (pllreg == VPLL) {
-               k = k & 0xfff;
-               /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
-               fout = (m + k / 1024) * (freq / (p * (1 << s)));
-       } else {
-               if (s < 1)
-                       s = 1;
-               /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
-               fout = m * (freq / (p * (1 << (s - 1))));
-       }
+       fout = exynos_get_pll_clk(pllreg, r, k);
 
        /* According to the user manual, in EVT1 MPLL and BPLL always gives
         * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
@@ -732,6 +718,209 @@ static unsigned long exynos5_get_i2c_clk(void)
        return aclk_66;
 }
 
+int exynos5_set_epll_clk(unsigned long rate)
+{
+       unsigned int epll_con, epll_con_k;
+       unsigned int i;
+       unsigned int lockcnt;
+       unsigned int start;
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+
+       epll_con = readl(&clk->epll_con0);
+       epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
+                       EPLL_CON0_LOCK_DET_EN_SHIFT) |
+               EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
+               EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
+               EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
+
+       for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
+               if (exynos5_epll_div[i].freq_out == rate)
+                       break;
+       }
+
+       if (i == ARRAY_SIZE(exynos5_epll_div))
+               return -1;
+
+       epll_con_k = exynos5_epll_div[i].k_dsm << 0;
+       epll_con |= exynos5_epll_div[i].en_lock_det <<
+                               EPLL_CON0_LOCK_DET_EN_SHIFT;
+       epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
+       epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
+       epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
+
+       /*
+        * Required period ( in cycles) to genarate a stable clock output.
+        * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
+        * frequency input (as per spec)
+        */
+       lockcnt = 3000 * exynos5_epll_div[i].p_div;
+
+       writel(lockcnt, &clk->epll_lock);
+       writel(epll_con, &clk->epll_con0);
+       writel(epll_con_k, &clk->epll_con1);
+
+       start = get_timer(0);
+
+        while (!(readl(&clk->epll_con0) &
+                       (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
+               if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
+                       debug("%s: Timeout waiting for EPLL lock\n", __func__);
+                       return -1;
+               }
+       }
+       return 0;
+}
+
+void exynos5_set_i2s_clk_source(void)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+
+       clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+                       (CLK_SRC_SCLK_EPLL));
+}
+
+int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
+                                       unsigned int dst_frq)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       unsigned int div;
+
+       if ((dst_frq == 0) || (src_frq == 0)) {
+               debug("%s: Invalid requency input for prescaler\n", __func__);
+               debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+               return -1;
+       }
+
+       div = (src_frq / dst_frq);
+       if (div > AUDIO_1_RATIO_MASK) {
+               debug("%s: Frequency ratio is out of range\n", __func__);
+               debug("src frq = %d des frq = %d ", src_frq, dst_frq);
+               return -1;
+       }
+       clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+                               (div & AUDIO_1_RATIO_MASK));
+       return 0;
+}
+
+/**
+ * Linearly searches for the most accurate main and fine stage clock scalars
+ * (divisors) for a specified target frequency and scalar bit sizes by checking
+ * all multiples of main_scalar_bits values. Will always return scalars up to or
+ * slower than target.
+ *
+ * @param main_scalar_bits     Number of main scalar bits, must be > 0 and < 32
+ * @param fine_scalar_bits     Number of fine scalar bits, must be > 0 and < 32
+ * @param input_freq           Clock frequency to be scaled in Hz
+ * @param target_freq          Desired clock frequency in Hz
+ * @param best_fine_scalar     Pointer to store the fine stage divisor
+ *
+ * @return best_main_scalar    Main scalar for desired frequency or -1 if none
+ * found
+ */
+static int clock_calc_best_scalar(unsigned int main_scaler_bits,
+       unsigned int fine_scalar_bits, unsigned int input_rate,
+       unsigned int target_rate, unsigned int *best_fine_scalar)
+{
+       int i;
+       int best_main_scalar = -1;
+       unsigned int best_error = target_rate;
+       const unsigned int cap = (1 << fine_scalar_bits) - 1;
+       const unsigned int loops = 1 << main_scaler_bits;
+
+       debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
+                       target_rate, cap);
+
+       assert(best_fine_scalar != NULL);
+       assert(main_scaler_bits <= fine_scalar_bits);
+
+       *best_fine_scalar = 1;
+
+       if (input_rate == 0 || target_rate == 0)
+               return -1;
+
+       if (target_rate >= input_rate)
+               return 1;
+
+       for (i = 1; i <= loops; i++) {
+               const unsigned int effective_div = max(min(input_rate / i /
+                                                       target_rate, cap), 1);
+               const unsigned int effective_rate = input_rate / i /
+                                                       effective_div;
+               const int error = target_rate - effective_rate;
+
+               debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
+                               effective_rate, error);
+
+               if (error >= 0 && error <= best_error) {
+                       best_error = error;
+                       best_main_scalar = i;
+                       *best_fine_scalar = effective_div;
+               }
+       }
+
+       return best_main_scalar;
+}
+
+static int exynos5_set_spi_clk(enum periph_id periph_id,
+                                       unsigned int rate)
+{
+       struct exynos5_clock *clk =
+               (struct exynos5_clock *)samsung_get_base_clock();
+       int main;
+       unsigned int fine;
+       unsigned shift, pre_shift;
+       unsigned mask = 0xff;
+       u32 *reg;
+
+       main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
+       if (main < 0) {
+               debug("%s: Cannot set clock rate for periph %d",
+                               __func__, periph_id);
+               return -1;
+       }
+       main = main - 1;
+       fine = fine - 1;
+
+       switch (periph_id) {
+       case PERIPH_ID_SPI0:
+               reg = &clk->div_peric1;
+               shift = 0;
+               pre_shift = 8;
+               break;
+       case PERIPH_ID_SPI1:
+               reg = &clk->div_peric1;
+               shift = 16;
+               pre_shift = 24;
+               break;
+       case PERIPH_ID_SPI2:
+               reg = &clk->div_peric2;
+               shift = 0;
+               pre_shift = 8;
+               break;
+       case PERIPH_ID_SPI3:
+               reg = &clk->sclk_div_isp;
+               shift = 0;
+               pre_shift = 4;
+               break;
+       case PERIPH_ID_SPI4:
+               reg = &clk->sclk_div_isp;
+               shift = 12;
+               pre_shift = 16;
+               break;
+       default:
+               debug("%s: Unsupported peripheral ID %d\n", __func__,
+                     periph_id);
+               return -1;
+       }
+       clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
+       clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
+
+       return 0;
+}
+
 static unsigned long exynos4_get_i2c_clk(void)
 {
        struct exynos4_clock *clk =
@@ -820,3 +1009,34 @@ void set_mipi_clk(void)
        if (cpu_is_exynos4())
                exynos4_set_mipi_clk();
 }
+
+int set_spi_clk(int periph_id, unsigned int rate)
+{
+       if (cpu_is_exynos5())
+               return exynos5_set_spi_clk(periph_id, rate);
+       else
+               return 0;
+}
+
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
+{
+
+       if (cpu_is_exynos5())
+               return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
+       else
+               return 0;
+}
+
+void set_i2s_clk_source(void)
+{
+       if (cpu_is_exynos5())
+               exynos5_set_i2s_clk_source();
+}
+
+int set_epll_clk(unsigned long rate)
+{
+       if (cpu_is_exynos5())
+               return exynos5_set_epll_clk(rate);
+       else
+               return 0;
+}
index 44ce072..20a4b84 100644 (file)
@@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
                s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
                s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
        }
+
        return 0;
 }
 
@@ -230,6 +231,59 @@ static void exynos5_i2c_config(int peripheral, int flags)
        }
 }
 
+static void exynos5_i2s_config(int peripheral)
+{
+       int i;
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+       for (i = 0; i < 5; i++)
+               s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
+}
+
+void exynos5_spi_config(int peripheral)
+{
+       int cfg = 0, pin = 0, i;
+       struct s5p_gpio_bank *bank = NULL;
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+       struct exynos5_gpio_part2 *gpio2 =
+               (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+       switch (peripheral) {
+       case PERIPH_ID_SPI0:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI1:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 4;
+               break;
+       case PERIPH_ID_SPI2:
+               bank = &gpio1->b1;
+               cfg = GPIO_FUNC(0x5);
+               pin = 1;
+               break;
+       case PERIPH_ID_SPI3:
+               bank = &gpio2->f1;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI4:
+               for (i = 0; i < 2; i++) {
+                       s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
+                       s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+               }
+               break;
+       }
+       if (peripheral != PERIPH_ID_SPI4) {
+               for (i = pin; i < pin + 4; i++)
+                       s5p_gpio_cfg_pin(bank, i, cfg);
+       }
+}
+
 static int exynos5_pinmux_config(int peripheral, int flags)
 {
        switch (peripheral) {
@@ -257,6 +311,16 @@ static int exynos5_pinmux_config(int peripheral, int flags)
        case PERIPH_ID_I2C7:
                exynos5_i2c_config(peripheral, flags);
                break;
+       case PERIPH_ID_I2S1:
+               exynos5_i2s_config(peripheral);
+               break;
+       case PERIPH_ID_SPI0:
+       case PERIPH_ID_SPI1:
+       case PERIPH_ID_SPI2:
+       case PERIPH_ID_SPI3:
+       case PERIPH_ID_SPI4:
+               exynos5_spi_config(peripheral);
+               break;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
                return -1;
index 1c9223f..76c2c52 100644 (file)
@@ -928,7 +928,9 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
        printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
        printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-
+#ifdef CONFIG_MXC_SPI
+       printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
        return 0;
 }
 
index 29ec957..6d9396a 100644 (file)
@@ -396,7 +396,7 @@ ENTRY(lowlevel_init)
        mov r10, lr
        mov r4, #0      /* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
        ldr r0, =GPIO1_BASE_ADDR
        ldr r1, [r0, #0x0]
        orr r1, r1, #1 << 23
index a01d96f..a50db70 100644 (file)
@@ -404,7 +404,9 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        printf("\n");
        printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
        printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
        printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
        printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
        printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
        printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
index bc65767..a8aad5d 100644 (file)
 #include <asm/arch/sys_proto.h>
 #include <asm/imx-common/boot_mode.h>
 
+struct scu_regs {
+       u32     ctrl;
+       u32     config;
+       u32     status;
+       u32     invalidate;
+       u32     fpga_rev;
+};
+
 u32 get_cpu_rev(void)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-       int reg = readl(&anatop->digprog);
-
-       /* Read mx6 variant: quad, dual or solo */
-       int system_rev = (reg >> 4) & 0xFF000;
-       /* Read mx6 silicon revision */
-       system_rev |= (reg & 0xFF) + 0x10;
-
-       return system_rev;
+       u32 reg = readl(&anatop->digprog_sololite);
+       u32 type = ((reg >> 16) & 0xff);
+
+       if (type != MXC_CPU_MX6SL) {
+               reg = readl(&anatop->digprog);
+               type = ((reg >> 16) & 0xff);
+               if (type == MXC_CPU_MX6DL) {
+                       struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
+                       u32 cfg = readl(&scu->config) & 3;
+
+                       if (!cfg)
+                               type = MXC_CPU_MX6SOLO;
+               }
+       }
+       reg &= 0xff;            /* mx6 silicon revision */
+       return (type << 12) | (reg + 0x10);
 }
 
 void init_aips(void)
index f975f3f..1705399 100644 (file)
@@ -28,7 +28,6 @@ LIB   = $(obj)libs5p-common.o
 COBJS-y                += cpu_info.o
 COBJS-y                += timer.o
 COBJS-y                += sromc.o
-COBJS-y                += wdt.o
 COBJS-$(CONFIG_PWM)    += pwm.o
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
index 09a0314..54ed8c4 100644 (file)
@@ -28,6 +28,8 @@ include $(TOPDIR)/config.mk
 LIB    =  $(obj)lib$(SOC).o
 
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
+COBJS-$(CONFIG_PWM_TEGRA) += pwm.o
+COBJS-$(CONFIG_VIDEO_TEGRA) += display.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
new file mode 100644 (file)
index 0000000..031f9a8
--- /dev/null
@@ -0,0 +1,409 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch/display.h>
+#include <asm/arch/dc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+
+static struct fdt_disp_config config;
+
+static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
+{
+       unsigned h_dda, v_dda;
+       unsigned long val;
+
+       val = readl(&dc->cmd.disp_win_header);
+       val |= WINDOW_A_SELECT;
+       writel(val, &dc->cmd.disp_win_header);
+
+       writel(win->fmt, &dc->win.color_depth);
+
+       clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
+                       BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
+
+       val = win->out_x << H_POSITION_SHIFT;
+       val |= win->out_y << V_POSITION_SHIFT;
+       writel(val, &dc->win.pos);
+
+       val = win->out_w << H_SIZE_SHIFT;
+       val |= win->out_h << V_SIZE_SHIFT;
+       writel(val, &dc->win.size);
+
+       val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
+       val |= win->h << V_PRESCALED_SIZE_SHIFT;
+       writel(val, &dc->win.prescaled_size);
+
+       writel(0, &dc->win.h_initial_dda);
+       writel(0, &dc->win.v_initial_dda);
+
+       h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
+       v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
+
+       val = h_dda << H_DDA_INC_SHIFT;
+       val |= v_dda << V_DDA_INC_SHIFT;
+       writel(val, &dc->win.dda_increment);
+
+       writel(win->stride, &dc->win.line_stride);
+       writel(0, &dc->win.buf_stride);
+
+       val = WIN_ENABLE;
+       if (win->bpp < 24)
+               val |= COLOR_EXPAND;
+       writel(val, &dc->win.win_opt);
+
+       writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
+       writel(win->x, &dc->winbuf.addr_h_offset);
+       writel(win->y, &dc->winbuf.addr_v_offset);
+
+       writel(0xff00, &dc->win.blend_nokey);
+       writel(0xff00, &dc->win.blend_1win);
+
+       val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
+       val |= GENERAL_UPDATE | WIN_A_UPDATE;
+       writel(val, &dc->cmd.state_ctrl);
+}
+
+static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
+{
+       writel(config->horiz_timing[item] |
+                       (config->vert_timing[item] << 16), reg);
+}
+
+static int update_display_mode(struct dc_disp_reg *disp,
+               struct fdt_disp_config *config)
+{
+       unsigned long val;
+       unsigned long rate;
+       unsigned long div;
+
+       writel(0x0, &disp->disp_timing_opt);
+       write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
+       write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
+       write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
+       write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
+
+       writel(config->width | (config->height << 16), &disp->disp_active);
+
+       val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
+       val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
+       writel(val, &disp->data_enable_opt);
+
+       val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
+       val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
+       val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
+       writel(val, &disp->disp_interface_ctrl);
+
+       /*
+        * The pixel clock divider is in 7.1 format (where the bottom bit
+        * represents 0.5). Here we calculate the divider needed to get from
+        * the display clock (typically 600MHz) to the pixel clock. We round
+        * up or down as requried.
+        */
+       rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
+       div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
+       debug("Display clock %lu, divider %lu\n", rate, div);
+
+       writel(0x00010001, &disp->shift_clk_opt);
+
+       val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
+       val |= div << SHIFT_CLK_DIVIDER_SHIFT;
+       writel(val, &disp->disp_clk_ctrl);
+
+       return 0;
+}
+
+/* Start up the display and turn on power to PWMs */
+static void basic_init(struct dc_cmd_reg *cmd)
+{
+       u32 val;
+
+       writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
+       writel(0x0000011a, &cmd->cont_syncpt_vsync);
+       writel(0x00000000, &cmd->int_type);
+       writel(0x00000000, &cmd->int_polarity);
+       writel(0x00000000, &cmd->int_mask);
+       writel(0x00000000, &cmd->int_enb);
+
+       val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
+       val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
+       val |= PM1_ENABLE;
+       writel(val, &cmd->disp_pow_ctrl);
+
+       val = readl(&cmd->disp_cmd);
+       val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
+       writel(val, &cmd->disp_cmd);
+}
+
+static void basic_init_timer(struct dc_disp_reg *disp)
+{
+       writel(0x00000020, &disp->mem_high_pri);
+       writel(0x00000001, &disp->mem_high_pri_timer);
+}
+
+static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+};
+
+static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
+       0x00000000,
+       0x01000000,
+       0x00000000,
+       0x00000000,
+};
+
+static const u32 rgb_data_tab[PIN_REG_COUNT] = {
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+};
+
+static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00000000,
+       0x00210222,
+       0x00002200,
+       0x00020000,
+};
+
+static void rgb_enable(struct dc_com_reg *com)
+{
+       int i;
+
+       for (i = 0; i < PIN_REG_COUNT; i++) {
+               writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
+               writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
+               writel(rgb_data_tab[i], &com->pin_output_data[i]);
+       }
+
+       for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
+               writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
+}
+
+int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
+{
+       win->x = 0;
+       win->y = 0;
+       win->w = config->width;
+       win->h = config->height;
+       win->out_x = 0;
+       win->out_y = 0;
+       win->out_w = config->width;
+       win->out_h = config->height;
+       win->phys_addr = config->frame_buffer;
+       win->stride = config->width * (1 << config->log2_bpp) / 8;
+       debug("%s: depth = %d\n", __func__, config->log2_bpp);
+       switch (config->log2_bpp) {
+       case 5:
+       case 24:
+               win->fmt = COLOR_DEPTH_R8G8B8A8;
+               win->bpp = 32;
+               break;
+       case 4:
+               win->fmt = COLOR_DEPTH_B5G6R5;
+               win->bpp = 16;
+               break;
+
+       default:
+               debug("Unsupported LCD bit depth");
+               return -1;
+       }
+
+       return 0;
+}
+
+struct fdt_disp_config *tegra_display_get_config(void)
+{
+       return config.valid ? &config : NULL;
+}
+
+static void debug_timing(const char *name, unsigned int timing[])
+{
+#ifdef DEBUG
+       int i;
+
+       debug("%s timing: ", name);
+       for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
+               debug("%d ", timing[i]);
+       debug("\n");
+#endif
+}
+
+/**
+ * Decode panel information from the fdt, according to a standard binding
+ *
+ * @param blob         fdt blob
+ * @param node         offset of fdt node to read from
+ * @param config       structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_decode_panel(const void *blob, int node,
+                             struct fdt_disp_config *config)
+{
+       int front, back, ref;
+
+       config->width = fdtdec_get_int(blob, node, "xres", -1);
+       config->height = fdtdec_get_int(blob, node, "yres", -1);
+       config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
+       if (!config->pixel_clock || config->width == -1 ||
+                       config->height == -1) {
+               debug("%s: Pixel parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       back = fdtdec_get_int(blob, node, "left-margin", -1);
+       front = fdtdec_get_int(blob, node, "right-margin", -1);
+       ref = fdtdec_get_int(blob, node, "hsync-len", -1);
+       if ((back | front | ref) == -1) {
+               debug("%s: Horizontal parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       /* Use a ref-to-sync of 1 always, and take this from the front porch */
+       config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+       config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+       config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+       config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+               config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+       debug_timing("horiz", config->horiz_timing);
+
+       back = fdtdec_get_int(blob, node, "upper-margin", -1);
+       front = fdtdec_get_int(blob, node, "lower-margin", -1);
+       ref = fdtdec_get_int(blob, node, "vsync-len", -1);
+       if ((back | front | ref) == -1) {
+               debug("%s: Vertical parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+
+       config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
+       config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
+       config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
+       config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
+               config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
+       debug_timing("vert", config->vert_timing);
+
+       return 0;
+}
+
+/**
+ * Decode the display controller information from the fdt.
+ *
+ * @param blob         fdt blob
+ * @param config       structure to store fdt config into
+ * @return 0 if ok, -ve on error
+ */
+static int tegra_display_decode_config(const void *blob,
+                                      struct fdt_disp_config *config)
+{
+       int node, rgb;
+       int bpp, bit;
+
+       /* TODO: Support multiple controllers */
+       node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
+       if (node < 0) {
+               debug("%s: Cannot find display controller node in fdt\n",
+                     __func__);
+               return node;
+       }
+       config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
+       if (!config->disp) {
+               debug("%s: No display controller address\n", __func__);
+               return -1;
+       }
+
+       rgb = fdt_subnode_offset(blob, node, "rgb");
+
+       config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
+       if (!config->panel_node < 0) {
+               debug("%s: Cannot find panel information\n", __func__);
+               return -1;
+       }
+
+       if (tegra_decode_panel(blob, config->panel_node, config)) {
+               debug("%s: Failed to decode panel information\n", __func__);
+               return -1;
+       }
+
+       bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
+                            -1);
+       bit = ffs(bpp) - 1;
+       if (bpp == (1 << bit))
+               config->log2_bpp = bit;
+       else
+               config->log2_bpp = bpp;
+       if (bpp == -1) {
+               debug("%s: Pixel bpp parameters missing\n", __func__);
+               return -FDT_ERR_NOTFOUND;
+       }
+       config->bpp = bpp;
+
+       config->valid = 1;      /* we have a valid configuration */
+
+       return 0;
+}
+
+int tegra_display_probe(const void *blob, void *default_lcd_base)
+{
+       struct disp_ctl_win window;
+       struct dc_ctlr *dc;
+
+       if (tegra_display_decode_config(blob, &config))
+               return -1;
+
+       config.frame_buffer = (u32)default_lcd_base;
+
+       dc = (struct dc_ctlr *)config.disp;
+
+       /*
+        * A header file for clock constants was NAKed upstream.
+        * TODO: Put this into the FDT and fdt_lcd struct when we have clock
+        * support there
+        */
+       clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
+                              144 * 1000000);
+       clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
+                              600 * 1000000);
+       basic_init(&dc->cmd);
+       basic_init_timer(&dc->disp);
+       rgb_enable(&dc->com);
+
+       if (config.pixel_clock)
+               update_display_mode(&dc->disp, &config);
+
+       if (setup_window(&window, &config))
+               return -1;
+
+       update_window(dc, &window);
+
+       return 0;
+}
diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c b/arch/arm/cpu/armv7/tegra20/pwm.c
new file mode 100644 (file)
index 0000000..b655c5c
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * Tegra2 pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+struct pwm_info {
+       struct pwm_ctlr *pwm;           /* Registers for our pwm controller */
+       int pwm_node;                   /* PWM device tree node */
+} local;
+
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
+{
+       u32 reg;
+
+       assert(channel < PWM_NUM_CHANNELS);
+
+       /* TODO: Can we use clock_adjust_periph_pll_div() here? */
+       clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+
+       reg = PWM_ENABLE_MASK;
+       reg |= pulse_width << PWM_WIDTH_SHIFT;
+       reg |= freq_divider << PWM_DIVIDER_SHIFT;
+       writel(reg, &local.pwm[channel].control);
+       debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
+}
+
+int pwm_request(const void *blob, int node, const char *prop_name)
+{
+       int pwm_node;
+       u32 data[3];
+
+       if (fdtdec_get_int_array(blob, node, prop_name, data,
+                       ARRAY_SIZE(data))) {
+               debug("%s: Cannot decode PWM property '%s'\n", __func__,
+                     prop_name);
+               return -1;
+       }
+
+       pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
+       if (pwm_node != local.pwm_node) {
+               debug("%s: PWM property '%s' phandle %d not recognised"
+                     "- expecting %d\n", __func__, prop_name, data[0],
+                     local.pwm_node);
+               return -1;
+       }
+       if (data[1] >= PWM_NUM_CHANNELS) {
+               debug("%s: PWM property '%s': invalid channel %u\n", __func__,
+                     prop_name, data[1]);
+               return -1;
+       }
+
+       /*
+        * TODO: We could maintain a list of requests, but it might not be
+        * worth it for U-Boot.
+        */
+       return data[1];
+}
+
+int pwm_init(const void *blob)
+{
+       local.pwm_node = fdtdec_next_compatible(blob, 0,
+                                               COMPAT_NVIDIA_TEGRA20_PWM);
+       if (local.pwm_node < 0) {
+               debug("%s: Cannot find device tree node\n", __func__);
+               return -1;
+       }
+
+       local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
+                                                      "reg");
+       if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
+               debug("%s: Cannot find pwm reg address\n", __func__);
+               return -1;
+       }
+       debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
+
+       return 0;
+}
index 00b8029..ece7ad9 100644 (file)
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 
+/*
+ * The PINMUX macro is used to set up pinmux tables.
+ */
+#define PINMUX(grp, mux, pupd, tri)                   \
+       {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
+
+static const struct pingroup_config disp1_default[] = {
+       PINMUX(LDI,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHP0,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHP1,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHP2,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LHS,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(LM0,   RSVD4,      NORMAL,    NORMAL),
+       PINMUX(LPP,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(LPW0,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LPW2,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LSC0,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LSPI,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LVP1,  DISPA,      NORMAL,    NORMAL),
+       PINMUX(LVS,   DISPA,      NORMAL,    NORMAL),
+       PINMUX(SLXD,  SPDIF,      NORMAL,    NORMAL),
+};
+
+
 int funcmux_select(enum periph_id id, int config)
 {
        int bad_config = config != FUNCMUX_DEFAULT;
@@ -257,6 +281,19 @@ int funcmux_select(enum periph_id id, int config)
                        break;
                }
                break;
+       case PERIPH_ID_DISP1:
+               if (config == FUNCMUX_DEFAULT) {
+                       int i;
+
+                       for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
+                               pinmux_set_func(i, PMUX_FUNC_DISPA);
+                               pinmux_tristate_disable(i);
+                               pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
+                       }
+                       pinmux_config_table(disp1_default,
+                                           ARRAY_SIZE(disp1_default));
+               }
+               break;
 
        default:
                debug("%s: invalid periph_id %d", __func__, id);
index 08b8305..a2a0916 100644 (file)
@@ -554,7 +554,7 @@ void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
        writel(reg, muxctl);
 }
 
-void pinmux_config_pingroup(struct pingroup_config *config)
+void pinmux_config_pingroup(const struct pingroup_config *config)
 {
        enum pmux_pingrp pin = config->pingroup;
 
@@ -563,7 +563,7 @@ void pinmux_config_pingroup(struct pingroup_config *config)
        pinmux_set_tristate(pin, config->tristate);
 }
 
-void pinmux_config_table(struct pingroup_config *config, int len)
+void pinmux_config_table(const struct pingroup_config *config, int len)
 {
        int i;
 
index d936b1e..636ec2c 100644 (file)
                compatible = "nvidia,tegra20-nand";
                reg = <0x70008000 0x100>;
        };
+
+       pwm: pwm@7000a000 {
+               compatible = "nvidia,tegra20-pwm";
+               reg = <0x7000a000 0x100>;
+               #pwm-cells = <2>;
+       };
+
+       host1x {
+               compatible = "nvidia,tegra20-host1x", "simple-bus";
+               reg = <0x50000000 0x00024000>;
+               interrupts = <0 65 0x04   /* mpcore syncpt */
+                             0 67 0x04>; /* mpcore general */
+               status = "disabled";
+
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               ranges = <0x54000000 0x54000000 0x04000000>;
+
+               /* video-encoding/decoding */
+               mpe {
+                       reg = <0x54040000 0x00040000>;
+                       interrupts = <0 68 0x04>;
+                       status = "disabled";
+               };
+
+               /* video input */
+               vi {
+                       reg = <0x54080000 0x00040000>;
+                       interrupts = <0 69 0x04>;
+                       status = "disabled";
+               };
+
+               /* EPP */
+               epp {
+                       reg = <0x540c0000 0x00040000>;
+                       interrupts = <0 70 0x04>;
+                       status = "disabled";
+               };
+
+               /* ISP */
+               isp {
+                       reg = <0x54100000 0x00040000>;
+                       interrupts = <0 71 0x04>;
+                       status = "disabled";
+               };
+
+               /* 2D engine */
+               gr2d {
+                       reg = <0x54140000 0x00040000>;
+                       interrupts = <0 72 0x04>;
+                       status = "disabled";
+               };
+
+               /* 3D engine */
+               gr3d {
+                       reg = <0x54180000 0x00040000>;
+                       status = "disabled";
+               };
+
+               /* display controllers */
+               dc@54200000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54200000 0x00040000>;
+                       interrupts = <0 73 0x04>;
+                       status = "disabled";
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               dc@54240000 {
+                       compatible = "nvidia,tegra20-dc";
+                       reg = <0x54240000 0x00040000>;
+                       interrupts = <0 74 0x04>;
+                       status = "disabled";
+
+                       rgb {
+                               status = "disabled";
+                       };
+               };
+
+               /* outputs */
+               hdmi {
+                       compatible = "nvidia,tegra20-hdmi";
+                       reg = <0x54280000 0x00040000>;
+                       interrupts = <0 75 0x04>;
+                       status = "disabled";
+               };
+
+               tvo {
+                       compatible = "nvidia,tegra20-tvo";
+                       reg = <0x542c0000 0x00040000>;
+                       interrupts = <0 76 0x04>;
+                       status = "disabled";
+               };
+
+               dsi {
+                       compatible = "nvidia,tegra20-dsi";
+                       reg = <0x54300000 0x00040000>;
+                       status = "disabled";
+               };
+       };
+
 };
index a10d12d..5081908 100644 (file)
@@ -65,20 +65,72 @@ char *get_reset_cause(void)
        }
 }
 
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53)
+#define MEMCTL_BASE    ESDCTL_BASE_ADDR;
+#else
+#define MEMCTL_BASE    MMDC_P0_BASE_ADDR;
+#endif
+static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
+static const unsigned char bank_lookup[] = {3, 2};
+
+struct esd_mmdc_regs {
+       uint32_t        ctl;
+       uint32_t        pdc;
+       uint32_t        otc;
+       uint32_t        cfg0;
+       uint32_t        cfg1;
+       uint32_t        cfg2;
+       uint32_t        misc;
+       uint32_t        scr;
+       uint32_t        ref;
+       uint32_t        rsvd1;
+       uint32_t        rsvd2;
+       uint32_t        rwd;
+       uint32_t        or;
+       uint32_t        mrr;
+       uint32_t        cfg3lp;
+       uint32_t        mr4;
+};
+
+#define ESD_MMDC_CTL_GET_ROW(mdctl)    ((ctl >> 24) & 7)
+#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
+#define ESD_MMDC_CTL_GET_WIDTH(mdctl)  ((ctl >> 16) & 3)
+#define ESD_MMDC_CTL_GET_CS1(mdctl)    ((ctl >> 30) & 1)
+#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
+
+unsigned imx_ddr_size(void)
+{
+       struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
+       unsigned ctl = readl(&mem->ctl);
+       unsigned misc = readl(&mem->misc);
+       int bits = 11 + 0 + 0 + 1;      /* row + col + bank + width */
+
+       bits += ESD_MMDC_CTL_GET_ROW(ctl);
+       bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
+       bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
+       bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
+       bits += ESD_MMDC_CTL_GET_CS1(ctl);
+       return 1 << bits;
+}
+#endif
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 
-static const char *get_imx_type(u32 imxtype)
+const char *get_imx_type(u32 imxtype)
 {
        switch (imxtype) {
-       case 0x63:
+       case MXC_CPU_MX6Q:
                return "6Q";    /* Quad-core version of the mx6 */
-       case 0x61:
-               return "6DS";   /* Dual/Solo version of the mx6 */
-       case 0x60:
+       case MXC_CPU_MX6DL:
+               return "6DL";   /* Dual Lite version of the mx6 */
+       case MXC_CPU_MX6SOLO:
+               return "6SOLO"; /* Solo version of the mx6 */
+       case MXC_CPU_MX6SL:
                return "6SL";   /* Solo-Lite version of the mx6 */
-       case 0x51:
+       case MXC_CPU_MX51:
                return "51";
-       case 0x53:
+       case MXC_CPU_MX53:
                return "53";
        default:
                return "??";
index 5529025..cd12323 100644 (file)
@@ -38,5 +38,9 @@ void set_mmc_clk(int dev_index, unsigned int div);
 unsigned long get_lcd_clk(void);
 void set_lcd_clk(void);
 void set_mipi_clk(void);
+void set_i2s_clk_source(void);
+int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
+int set_epll_clk(unsigned long rate);
+int set_spi_clk(int periph_id, unsigned int rate);
 
 #endif
index fce38ef..ff6781a 100644 (file)
@@ -595,9 +595,38 @@ struct exynos5_clock {
        unsigned int    pll_div2_sel;
        unsigned char   res123[0xf5d8];
 };
+
+/* structure for epll configuration used in audio clock configuration */
+struct set_epll_con_val {
+       unsigned int freq_out;          /* frequency out */
+       unsigned int en_lock_det;       /* enable lock detect */
+       unsigned int m_div;             /* m divider value */
+       unsigned int p_div;             /* p divider value */
+       unsigned int s_div;             /* s divider value */
+       unsigned int k_dsm;             /* k value of delta signal modulator */
+};
 #endif
 
 #define MPLL_FOUT_SEL_SHIFT    4
+#define EXYNOS5_EPLLCON0_LOCKED_SHIFT  29  /* EPLL Locked bit position*/
+#define TIMEOUT_EPLL_LOCK              1000
+
+#define AUDIO_0_RATIO_MASK             0x0f
+#define AUDIO_1_RATIO_MASK             0x0f
+
+#define AUDIO1_SEL_MASK                        0xf
+#define CLK_SRC_SCLK_EPLL              0x7
+
+/* CON0 bit-fields */
+#define EPLL_CON0_MDIV_MASK            0x1ff
+#define EPLL_CON0_PDIV_MASK            0x3f
+#define EPLL_CON0_SDIV_MASK            0x7
+#define EPLL_CON0_MDIV_SHIFT           16
+#define EPLL_CON0_PDIV_SHIFT           8
+#define EPLL_CON0_SDIV_SHIFT           0
+#define EPLL_CON0_LOCK_DET_EN_SHIFT    28
+#define EPLL_CON0_LOCK_DET_EN_MASK     1
+
 #define MPLL_FOUT_SEL_MASK     0x1
 #define BPLL_FOUT_SEL_SHIFT    0
 #define BPLL_FOUT_SEL_MASK     0x1
index 3073ca1..f06af2e 100644 (file)
 #define EXYNOS4_UART_BASE              0x13800000
 #define EXYNOS4_I2C_BASE               0x13860000
 #define EXYNOS4_ADC_BASE               0x13910000
+#define EXYNOS4_SPI_BASE               0x13920000
 #define EXYNOS4_PWMTIMER_BASE          0x139D0000
 #define EXYNOS4_MODEM_BASE             0x13A00000
 #define EXYNOS4_USBPHY_CONTROL         0x10020704
+#define EXYNOS4_I2S_BASE               0xE2100000
 
 #define EXYNOS4_GPIO_PART4_BASE                DEVICE_NOT_AVAILABLE
 #define EXYNOS4_DP_BASE                        DEVICE_NOT_AVAILABLE
+#define EXYNOS4_SPI_ISP_BASE           DEVICE_NOT_AVAILABLE
 
 /* EXYNOS5 */
 #define EXYNOS5_I2C_SPACING            0x10000
 #define EXYNOS5_SROMC_BASE             0x12250000
 #define EXYNOS5_UART_BASE              0x12C00000
 #define EXYNOS5_I2C_BASE               0x12C60000
+#define EXYNOS5_SPI_BASE               0x12D20000
+#define EXYNOS5_I2S_BASE               0x12D60000
 #define EXYNOS5_PWMTIMER_BASE          0x12DD0000
+#define EXYNOS5_SPI_ISP_BASE           0x131A0000
 #define EXYNOS5_GPIO_PART2_BASE                0x13400000
 #define EXYNOS5_FIMD_BASE              0x14400000
 #define EXYNOS5_DP_BASE                        0x145B0000
@@ -141,6 +147,15 @@ static inline int cpu_is_##type(void)                      \
 IS_SAMSUNG_TYPE(exynos4, 0x4)
 IS_SAMSUNG_TYPE(exynos5, 0x5)
 
+#define IS_EXYNOS_TYPE(type, id)                       \
+static inline int proid_is_##type(void)                        \
+{                                                      \
+       return s5p_cpu_id == id;                        \
+}
+
+IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos5250, 0x5250)
+
 #define SAMSUNG_BASE(device, base)                             \
 static inline unsigned int samsung_get_base_##device(void)     \
 {                                                              \
@@ -158,6 +173,7 @@ SAMSUNG_BASE(dp, DP_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 SAMSUNG_BASE(fimd, FIMD_BASE)
 SAMSUNG_BASE(i2c, I2C_BASE)
+SAMSUNG_BASE(i2s, I2S_BASE)
 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
@@ -175,6 +191,8 @@ SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
+SAMSUNG_BASE(spi, SPI_BASE)
+SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 #endif
 
 #endif /* _EXYNOS4_CPU_H */
index 97be4ea..4db8fd6 100644 (file)
@@ -207,6 +207,25 @@ static inline unsigned int s5p_gpio_base(int nr)
        return 0;
 }
 
+static inline unsigned int s5p_gpio_part_max(int nr)
+{
+       if (cpu_is_exynos5()) {
+               if (nr < EXYNOS5_GPIO_PART1_MAX)
+                       return 0;
+               else if (nr < EXYNOS5_GPIO_PART2_MAX)
+                       return EXYNOS5_GPIO_PART1_MAX;
+               else
+                       return EXYNOS5_GPIO_PART2_MAX;
+
+       } else if (cpu_is_exynos4()) {
+               if (nr < EXYNOS4_GPIO_PART1_MAX)
+                       return 0;
+               else
+                       return EXYNOS4_GPIO_PART1_MAX;
+       }
+
+       return 0;
+}
 #endif
 
 /* Pin configurations */
diff --git a/arch/arm/include/asm/arch-exynos/i2s-regs.h b/arch/arm/include/asm/arch-exynos/i2s-regs.h
new file mode 100644 (file)
index 0000000..2326ca0
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * R. Chandrasekar <rcsekar@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __I2S_REGS_H__
+#define __I2S_REGS_H__
+
+#define CON_TXFIFO_FULL                (1 << 8)
+#define CON_TXCH_PAUSE         (1 << 4)
+#define CON_ACTIVE             (1 << 0)
+
+#define MOD_BLCP_SHIFT         24
+#define MOD_BLCP_16BIT         (0 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_8BIT          (1 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_24BIT         (2 << MOD_BLCP_SHIFT)
+#define MOD_BLCP_MASK          (3 << MOD_BLCP_SHIFT)
+
+#define MOD_BLC_16BIT          (0 << 13)
+#define MOD_BLC_8BIT           (1 << 13)
+#define MOD_BLC_24BIT          (2 << 13)
+#define MOD_BLC_MASK           (3 << 13)
+
+#define MOD_SLAVE              (1 << 11)
+#define MOD_MASK               (3 << 8)
+#define MOD_LR_LLOW            (0 << 7)
+#define MOD_LR_RLOW            (1 << 7)
+#define MOD_SDF_IIS            (0 << 5)
+#define MOD_SDF_MSB            (1 << 5)
+#define MOD_SDF_LSB            (2 << 5)
+#define MOD_SDF_MASK           (3 << 5)
+#define MOD_RCLK_256FS         (0 << 3)
+#define MOD_RCLK_512FS         (1 << 3)
+#define MOD_RCLK_384FS         (2 << 3)
+#define MOD_RCLK_768FS         (3 << 3)
+#define MOD_RCLK_MASK          (3 << 3)
+#define MOD_BCLK_32FS          (0 << 1)
+#define MOD_BCLK_48FS          (1 << 1)
+#define MOD_BCLK_16FS          (2 << 1)
+#define MOD_BCLK_24FS          (3 << 1)
+#define MOD_BCLK_MASK          (3 << 1)
+
+#define MOD_CDCLKCON           (1 << 12)
+
+#define FIC_TXFLUSH            (1 << 15)
+#define FIC_RXFLUSH            (1 << 7)
+
+#endif /* __I2S_REGS_H__ */
index b861d7d..13abd2d 100644 (file)
@@ -38,11 +38,18 @@ enum periph_id {
        PERIPH_ID_I2C5,
        PERIPH_ID_I2C6,
        PERIPH_ID_I2C7,
+       PERIPH_ID_I2S1,
        PERIPH_ID_SDMMC0,
        PERIPH_ID_SDMMC1,
        PERIPH_ID_SDMMC2,
        PERIPH_ID_SDMMC3,
+       PERIPH_ID_SDMMC4,
        PERIPH_ID_SROMC,
+       PERIPH_ID_SPI0,
+       PERIPH_ID_SPI1,
+       PERIPH_ID_SPI2,
+       PERIPH_ID_SPI3,
+       PERIPH_ID_SPI4,
        PERIPH_ID_UART0,
        PERIPH_ID_UART1,
        PERIPH_ID_UART2,
diff --git a/arch/arm/include/asm/arch-exynos/sound.h b/arch/arm/include/asm/arch-exynos/sound.h
new file mode 100644 (file)
index 0000000..d1bd2f6
--- /dev/null
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __SOUND_ARCH_H__
+#define __SOUND_ARCH_H__
+
+/* I2S values */
+#define I2S_PLL_CLK            192000000
+#define I2S_SAMPLING_RATE      48000
+#define I2S_BITS_PER_SAMPLE    16
+#define I2S_CHANNELS           2
+#define I2S_RFS                        256
+#define I2S_BFS                        32
+
+/* I2C values */
+#define AUDIO_I2C_BUS          1
+#define AUDIO_I2C_REG          0x1a
+
+/* Audio Codec */
+#define AUDIO_CODEC            "wm8994"
+
+#define AUDIO_COMPAT           1
+#endif
diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h
new file mode 100644 (file)
index 0000000..7cab1e9
--- /dev/null
@@ -0,0 +1,78 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+
+#ifndef __ASSEMBLY__
+
+/* SPI peripheral register map; padded to 64KB */
+struct exynos_spi {
+       unsigned int            ch_cfg;         /* 0x00 */
+       unsigned char           reserved0[4];
+       unsigned int            mode_cfg;       /* 0x08 */
+       unsigned int            cs_reg;         /* 0x0c */
+       unsigned char           reserved1[4];
+       unsigned int            spi_sts;        /* 0x14 */
+       unsigned int            tx_data;        /* 0x18 */
+       unsigned int            rx_data;        /* 0x1c */
+       unsigned int            pkt_cnt;        /* 0x20 */
+       unsigned char           reserved2[4];
+       unsigned char           reserved3[4];
+       unsigned int            fb_clk;         /* 0x2c */
+       unsigned char           padding[0xffd0];
+};
+
+#define EXYNOS_SPI_MAX_FREQ    50000000
+
+#define SPI_TIMEOUT_MS         10
+
+/* SPI_CHCFG */
+#define SPI_CH_HS_EN           (1 << 6)
+#define SPI_CH_RST             (1 << 5)
+#define SPI_SLAVE_MODE         (1 << 4)
+#define SPI_CH_CPOL_L          (1 << 3)
+#define SPI_CH_CPHA_B          (1 << 2)
+#define SPI_RX_CH_ON           (1 << 1)
+#define SPI_TX_CH_ON           (1 << 0)
+
+/* SPI_MODECFG */
+#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
+#define SPI_MODE_BUS_WIDTH_WORD        (0x2 << 17)
+
+/* SPI_CSREG */
+#define SPI_SLAVE_SIG_INACT    (1 << 0)
+
+/* SPI_STS */
+#define SPI_ST_TX_DONE         (1 << 25)
+#define SPI_FIFO_LVL_MASK      0x1ff
+#define SPI_TX_LVL_OFFSET      6
+#define SPI_RX_LVL_OFFSET      15
+
+/* Feedback Delay */
+#define SPI_CLK_BYPASS         (0 << 0)
+#define SPI_FB_DELAY_90                (1 << 0)
+#define SPI_FB_DELAY_180       (2 << 0)
+#define SPI_FB_DELAY_270       (3 << 0)
+
+/* Packet Count */
+#define SPI_PACKET_CNT_EN      (1 << 16)
+
+#endif /* __ASSEMBLY__ */
+#endif
index 53aafe3..5f4b543 100644 (file)
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
-#ifdef CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
-
 /* Clock Control Module (CCM) registers */
 struct ccm_regs {
        u32 mpctl;      /* Core PLL Control */
@@ -245,6 +241,7 @@ struct aips_regs {
 #define IMX_RTIC_BASE          (0x53FEC000)
 #define IMX_IIM_BASE           (0x53FF0000)
 #define IMX_USB_BASE           (0x53FF4000)
+#define IMX_USB_PORT_OFFSET    0x200
 #define IMX_CSI_BASE           (0x53FF8000)
 #define IMX_DRYICE_BASE                (0x53FFC000)
 
index 6a01a7b..46db341 100644 (file)
@@ -25,5 +25,8 @@
 #define _SYS_PROTO_H_
 
 void mx25_uart1_init_pins(void);
+#if defined CONFIG_FEC_MXC
+extern void mx25_fec_init_pins(void);
+#endif
 
 #endif
index 8fd3d08..ae3658b 100644 (file)
@@ -895,32 +895,7 @@ struct esdc_regs {
 
 #define MX31_AIPS1_BASE_ADDR   0x43f00000
 #define IMX_USB_BASE           (MX31_AIPS1_BASE_ADDR + 0x88000)
-
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23)
-#define MXC_EHCI_FORCE_FS              (1 << 24)
-#define MXC_EHCI_UTMI_8BIT             (0 << 28)
-#define MXC_EHCI_UTMI_16BIT            (1 << 28)
-#define MXC_EHCI_SERIAL                        (1 << 29)
-#define MXC_EHCI_MODE_UTMI             (0 << 30)
-#define MXC_EHCI_MODE_PHILIPS          (1 << 30)
-#define MXC_EHCI_MODE_ULPI             (2 << 30)
-#define MXC_EHCI_MODE_SERIAL           (3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI    (0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI     (1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI  (2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI   (3 << 0)
-#define MXC_EHCI_INTERFACE_MASK                (0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED    (1 << 5)
-#define MXC_EHCI_TTL_ENABLED           (1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY          (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN            (1 << 8)
-#define MXC_EHCI_IPPUE_UP              (1 << 9)
+#define IMX_USB_PORT_OFFSET    0x200
 
 /*
  * CSPI register definitions
index 7b09809..18c6816 100644 (file)
@@ -33,6 +33,8 @@
 #define IRAM_BASE_ADDR         0x10000000      /* internal ram */
 #define IRAM_SIZE              0x00020000      /* 128 KB */
 
+#define LOW_LEVEL_SRAM_STACK   0x1001E000
+
 /*
  * AIPS 1
  */
@@ -82,6 +84,8 @@
 #define PWM_BASE_ADDR          0x53FE0000
 #define RTIC_BASE_ADDR         0x53FEC000
 #define IIM_BASE_ADDR          0x53FF0000
+#define IMX_USB_BASE           0x53FF4000
+#define IMX_USB_PORT_OFFSET    0x400
 
 #define IMX_CCM_BASE           CCM_BASE_ADDR
 
diff --git a/arch/arm/include/asm/arch-mx35/mmc_host_def.h b/arch/arm/include/asm/arch-mx35/mmc_host_def.h
new file mode 100644 (file)
index 0000000..775b955
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation's version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MMC_HOST_DEF_H
+#define MMC_HOST_DEF_H
+
+/* Driver definitions */
+#define MMCSD_SECTOR_SIZE              512
+
+#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-mx35/spl.h b/arch/arm/include/asm/arch-mx35/spl.h
new file mode 100644 (file)
index 0000000..91d11ae
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2012
+ * Texas Instruments, <www.ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef        _ASM_ARCH_SPL_H_
+#define        _ASM_SPL_H_
+
+#define BOOT_DEVICE_NONE       0
+#define BOOT_DEVICE_XIP                1
+#define BOOT_DEVICE_XIPWAIT    2
+#define BOOT_DEVICE_NAND       3
+#define BOOT_DEVICE_ONE_NAND   4
+#define BOOT_DEVICE_MMC1       5
+#define BOOT_DEVICE_MMC2       6
+#define BOOT_DEVICE_MMC2_2     7
+#define BOOT_DEVICE_NOR                8
+#define BOOT_DEVICE_I2C                9
+#define BOOT_DEVICE_SPI                10
+
+#endif
index 9c0d513..aa3549c 100644 (file)
@@ -25,6 +25,8 @@
 #define _SYS_PROTO_H_
 
 u32 get_cpu_rev(void);
+void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
+       u32 row, u32 col, u32 dsize, u32 refresh);
 #define is_soc_rev(rev)        ((get_cpu_rev() & 0xFF) - rev)
 
 #endif
index 122fbee..3457f6a 100644 (file)
@@ -802,22 +802,22 @@ typedef enum iomux_input_select {
        MX53_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
        MX53_CSPI_IPP_IND_MISO_SELECT_INPUT,
        MX53_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+       MX53_CSPI_IPP_IND_SS_B_0_SELECT_INPUT,
        MX53_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
        MX53_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
        MX53_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
-       MX53_CSPI_IPP_IND_SS_B_4_SELECT_INPUT,
        MX53_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT,
        MX53_ECSPI1_IPP_IND_MISO_SELECT_INPUT,
        MX53_ECSPI1_IPP_IND_MOSI_SELECT_INPUT,
+       MX53_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT,
        MX53_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
        MX53_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT,
        MX53_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT,
-       MX53_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT,
        MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT,
        MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT,
        MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT,
+       MX53_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT,
        MX53_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
-       MX53_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT,
        MX53_ESAI1_IPP_IND_FSR_SELECT_INPUT,
        MX53_ESAI1_IPP_IND_FST_SELECT_INPUT,
        MX53_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
index 7b5246e..93ad1c6 100644 (file)
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-u32 get_cpu_rev(void);
+#define MXC_CPU_MX51           0x51
+#define MXC_CPU_MX53           0x53
+#define MXC_CPU_MX6SL          0x60
+#define MXC_CPU_MX6DL          0x61
+#define MXC_CPU_MX6SOLO                0x62
+#define MXC_CPU_MX6Q           0x63
+
 #define is_soc_rev(rev)        ((get_cpu_rev() & 0xFF) - rev)
+u32 get_cpu_rev(void);
+unsigned imx_ddr_size(void);
 void sdelay(unsigned long);
 void set_chipselect_size(int const);
 
index 09ab010..3eb0081 100644 (file)
@@ -564,6 +564,8 @@ struct anatop_regs {
        u32     usb2_misc_clr;          /* 0x258 */
        u32     usb2_misc_tog;          /* 0x25c */
        u32     digprog;                /* 0x260 */
+       u32     reserved1[7];
+       u32     digprog_sololite;       /* 0x280 */
 };
 
 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT         0
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
new file mode 100644 (file)
index 0000000..79e2c4f
--- /dev/null
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6DL_PINS_H__
+#define __ASM_ARCH_MX6_MX6DL_PINS_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS            (1 << 16)
+#define PAD_CTL_PUS_100K_DOWN  (0 << 14)
+#define PAD_CTL_PUS_47K_UP     (1 << 14)
+#define PAD_CTL_PUS_100K_UP    (2 << 14)
+#define PAD_CTL_PUS_22K_UP     (3 << 14)
+
+#define PAD_CTL_PUE            (1 << 13)
+#define PAD_CTL_PKE            (1 << 12)
+#define PAD_CTL_ODE            (1 << 11)
+#define PAD_CTL_SPEED_LOW      (1 << 6)
+#define PAD_CTL_SPEED_MED      (2 << 6)
+#define PAD_CTL_SPEED_HIGH     (3 << 6)
+#define PAD_CTL_DSE_DISABLE    (0 << 3)
+#define PAD_CTL_DSE_240ohm     (1 << 3)
+#define PAD_CTL_DSE_120ohm     (2 << 3)
+#define PAD_CTL_DSE_80ohm      (3 << 3)
+#define PAD_CTL_DSE_60ohm      (4 << 3)
+#define PAD_CTL_DSE_48ohm      (5 << 3)
+#define PAD_CTL_DSE_40ohm      (6 << 3)
+#define PAD_CTL_DSE_34ohm      (7 << 3)
+#define PAD_CTL_SRE_FAST       (1 << 0)
+#define PAD_CTL_SRE_SLOW       (0 << 0)
+
+#define IOMUX_CONFIG_SION 0x10
+#define NO_MUX_I                0
+#define NO_PAD_I                0
+enum {
+       MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK = IOMUX_PAD(0x03B0, 0x009C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15     = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN2       = IOMUX_PAD(0x03B8, 0x00A4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN3       = IOMUX_PAD(0x03BC, 0x00A8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DI0_PIN4__GPIO_4_20           = IOMUX_PAD(0x03C0, 0x00AC, 5, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0  = IOMUX_PAD(0x03C4, 0x00B0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1  = IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2   = IOMUX_PAD(0x03F4, 0x00E0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3  = IOMUX_PAD(0x0408, 0x00F4, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4  = IOMUX_PAD(0x040C, 0x00F8, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5  = IOMUX_PAD(0x0410, 0x00FC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6  = IOMUX_PAD(0x0414, 0x0100, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7  = IOMUX_PAD(0x0418, 0x0104, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8  = IOMUX_PAD(0x041C, 0x0108, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9  = IOMUX_PAD(0x0420, 0x010C, 0, 0x0000, 0, PAD_CTL_DSE_120ohm),
+       MX6DL_PAD_EIM_D16__ECSPI1_SCLK          = IOMUX_PAD(0x0514, 0x0144, 1, 0x07D8, 2, 0),
+       MX6DL_PAD_EIM_D17__ECSPI1_MISO          = IOMUX_PAD(0x0518, 0x0148, 1, 0x07DC, 2, 0),
+       MX6DL_PAD_EIM_D18__ECSPI1_MOSI          = IOMUX_PAD(0x051C, 0x014C, 1, 0x07E0, 2, 0),
+       MX6DL_PAD_EIM_D19__GPIO_3_19            = IOMUX_PAD(0x0520, 0x0150, 5, 0x0000, 0, 0),
+       MX6DL_PAD_EIM_D21__GPIO_3_21            = IOMUX_PAD(0x0528, 0x0158, 5, 0x0000, 0, 0),
+       MX6DL_PAD_EIM_D21__I2C1_SCL             = IOMUX_PAD(0x0528, 0x0158, 6 | IOMUX_CONFIG_SION, 0x0868, 1, 0),
+       MX6DL_PAD_EIM_D23__GPIO_3_23            = IOMUX_PAD(0x0530, 0x0160, 5, 0x0000, 0, 0),
+       MX6DL_PAD_EIM_D26__UART2_TXD            = IOMUX_PAD(0x053C, 0x016C, 4, 0x0000, 0, 0),
+       MX6DL_PAD_EIM_D27__UART2_RXD            = IOMUX_PAD(0x0540, 0x0170, 4, 0x0904, 1, 0),
+       MX6DL_PAD_EIM_D28__I2C1_SDA             = IOMUX_PAD(0x0544, 0x0174, 1 | IOMUX_CONFIG_SION, 0x086C, 1, 0),
+       MX6DL_PAD_EIM_D28__GPIO_3_28            = IOMUX_PAD(0x0544, 0x0174, 5, 0x0000, 0, 0),
+       MX6DL_PAD_ENET_MDC__ENET_MDC            = IOMUX_PAD(0x05B8, 0x01E8, 1, 0x0000, 0,  0),
+       MX6DL_PAD_ENET_MDIO__ENET_MDIO          = IOMUX_PAD(0x05BC, 0x01EC, 1, 0x0810, 0, 0),
+       MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK     = IOMUX_PAD(0x05C0, 0x01F0, 1, 0x0000, 0, 0),
+       MX6DL_PAD_ENET_RXD0__GPIO_1_27          = IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
+       MX6DL_PAD_GPIO_16__GPIO_7_11            = IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0),
+       MX6DL_PAD_GPIO_16__I2C3_SDA             = IOMUX_PAD(0x05E4, 0x0214, 6 | IOMUX_CONFIG_SION, 0x087C, 1, 0),
+       MX6DL_PAD_GPIO_17__GPIO_7_12            = IOMUX_PAD(0x05E8, 0x0218, 5, 0x0000, 0, 0),
+       MX6DL_PAD_GPIO_18__GPIO_7_13            = IOMUX_PAD(0x05EC, 0x021C, 5, 0x0000, 0, 0),
+       MX6DL_PAD_GPIO_19__GPIO_4_5             = IOMUX_PAD(0x05F0, 0x0220, 5, 0x0000, 0, 0),
+       MX6DL_PAD_GPIO_5__GPIO_1_5              = IOMUX_PAD(0x0600, 0x0230, 5, 0x0000, 0, 0),
+       MX6DL_PAD_GPIO_5__I2C3_SCL              = IOMUX_PAD(0x0600, 0x0230, 6 | IOMUX_CONFIG_SION, 0x0878, 2, 0),
+       MX6DL_PAD_KEY_COL3__I2C2_SCL            = IOMUX_PAD(0x0638, 0x0250, 4 | IOMUX_CONFIG_SION, 0x0870, 1, 0),
+       MX6DL_PAD_KEY_COL3__GPIO_4_12           = IOMUX_PAD(0x0638, 0x0250, 5, 0x0000, 0, 0),
+       MX6DL_PAD_KEY_ROW3__I2C2_SDA            = IOMUX_PAD(0x064C, 0x0264, 4 | IOMUX_CONFIG_SION, 0x0874, 1, 0),
+       MX6DL_PAD_KEY_ROW3__GPIO_4_13           = IOMUX_PAD(0x064C, 0x0264, 5, 0x0000, 0, 0),
+       MX6DL_PAD_NANDF_D1__GPIO_2_1            = IOMUX_PAD(0x0670, 0x0288, 5, 0x0000, 0, 0),
+       MX6DL_PAD_NANDF_D2__GPIO_2_2            = IOMUX_PAD(0x0674, 0x028C, 5, 0x0000, 0, 0),
+       MX6DL_PAD_NANDF_D3__GPIO_2_3            = IOMUX_PAD(0x0678, 0x0290, 5, 0x0000, 0, 0),
+       MX6DL_PAD_NANDF_D4__GPIO_2_4            = IOMUX_PAD(0x067C, 0x0294, 5, 0x0000, 0, 0),
+       MX6DL_PAD_NANDF_D6__GPIO_2_6            = IOMUX_PAD(0x0684, 0x029C, 5, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0     = IOMUX_PAD(0x0694, 0x02AC, 1, 0x0818, 1, 0),
+       MX6DL_PAD_RGMII_RD0__GPIO_6_25          = IOMUX_PAD(0x0694, 0x02AC, 5, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1     = IOMUX_PAD(0x0698, 0x02B0, 1, 0x081C, 1, 0),
+       MX6DL_PAD_RGMII_RD1__GPIO_6_27          = IOMUX_PAD(0x0698, 0x02B0, 5, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2     = IOMUX_PAD(0x069C, 0x02B4, 1, 0x0820, 1, 0),
+       MX6DL_PAD_RGMII_RD2__GPIO_6_28          = IOMUX_PAD(0x069C, 0x02B4, 5, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3     = IOMUX_PAD(0x06A0, 0x02B8, 1, 0x0824, 1, 0),
+       MX6DL_PAD_RGMII_RD3__GPIO_6_29          = IOMUX_PAD(0x06A0, 0x02B8, 5, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL    = IOMUX_PAD(0x06A4, 0x02BC, 1, 0x0828, 1, 0),
+       MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24       = IOMUX_PAD(0x06A4, 0x02BC, 5, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC     = IOMUX_PAD(0x06A8, 0x02C0, 1, 0x0814, 1, 0),
+       MX6DL_PAD_RGMII_RXC__GPIO_6_30          = IOMUX_PAD(0x06A8, 0x02C0, 5, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0     = IOMUX_PAD(0x06AC, 0x02C4, 1, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1     = IOMUX_PAD(0x06B0, 0x02C8, 1, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2     = IOMUX_PAD(0x06B4, 0x02CC, 1, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3     = IOMUX_PAD(0x06B8, 0x02D0, 1, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL    = IOMUX_PAD(0x06BC, 0x02D4, 1, 0x0000, 0, 0),
+       MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC     = IOMUX_PAD(0x06C0, 0x02D8, 1, 0x0000, 0, 0),
+       MX6DL_PAD_SD1_CMD__GPIO_1_18            = IOMUX_PAD(0x06C8, 0x02E0, 5, 0x0000, 0, 0),
+       MX6DL_PAD_SD1_DAT3__GPIO_1_21           = IOMUX_PAD(0x06D8, 0x02F0, 5, 0x0000, 0, 0),
+       MX6DL_PAD_SD3_CLK__USDHC3_CLK           = IOMUX_PAD(0x06F4, 0x030C, 0, 0x0934, 1, 0),
+       MX6DL_PAD_SD3_CMD__USDHC3_CMD           = IOMUX_PAD(0x06F8, 0x0310, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6DL_PAD_SD3_DAT0__USDHC3_DAT0         = IOMUX_PAD(0x06FC, 0x0314, 0, 0x0000, 0, 0),
+       MX6DL_PAD_SD3_DAT1__USDHC3_DAT1         = IOMUX_PAD(0x0700, 0x0318, 0, 0x0000, 0, 0),
+       MX6DL_PAD_SD3_DAT2__USDHC3_DAT2         = IOMUX_PAD(0x0704, 0x031C, 0, 0x0000, 0, 0),
+       MX6DL_PAD_SD3_DAT3__USDHC3_DAT3         = IOMUX_PAD(0x0708, 0x0320, 0, 0x0000, 0, 0),
+       MX6DL_PAD_SD3_DAT5__GPIO_7_0            = IOMUX_PAD(0x0710, 0x0328, 5, 0x0000, 0, 0),
+       MX6DL_PAD_SD3_DAT6__UART1_RXD           = IOMUX_PAD(0x0714, 0x032C, 1, 0x08FC, 2, 0),
+       MX6DL_PAD_SD3_DAT7__UART1_TXD           = IOMUX_PAD(0x0718, 0x0330, 1, 0x0000, 0, 0),
+       MX6DL_PAD_SD4_CLK__USDHC4_CLK           = IOMUX_PAD(0x0720, 0x0338, 0, 0x0938, 1, 0),
+       MX6DL_PAD_SD4_CMD__USDHC4_CMD           = IOMUX_PAD(0x0724, 0x033C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+       MX6DL_PAD_SD4_DAT0__USDHC4_DAT0         = IOMUX_PAD(0x0728, 0x0340, 1, 0x0000, 0, 0),
+       MX6DL_PAD_SD4_DAT1__USDHC4_DAT1         = IOMUX_PAD(0x072C, 0x0344, 1, 0x0000, 0, 0),
+       MX6DL_PAD_SD4_DAT2__USDHC4_DAT2         = IOMUX_PAD(0x0730, 0x0348, 1, 0x0000, 0, 0),
+       MX6DL_PAD_SD4_DAT3__USDHC4_DAT3         = IOMUX_PAD(0x0734, 0x034C, 1, 0x0000, 0, 0),
+};
+#endif /* __ASM_ARCH_MX6_MX6DL_PINS_H__ */
index 711b30d..3193297 100644 (file)
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-#define is_soc_rev(rev)        ((get_cpu_rev() & 0xFF) - rev)
+#define MXC_CPU_MX51           0x51
+#define MXC_CPU_MX53           0x53
+#define MXC_CPU_MX6SL          0x60
+#define MXC_CPU_MX6DL          0x61
+#define MXC_CPU_MX6SOLO                0x62
+#define MXC_CPU_MX6Q           0x63
 
+#define is_soc_rev(rev)        ((get_cpu_rev() & 0xFF) - rev)
 u32 get_cpu_rev(void);
+const char *get_imx_type(u32 imxtype);
+unsigned imx_ddr_size(void);
 
 void set_vddsoc(u32 mv);
 
index 5e1901e..9764041 100644 (file)
@@ -26,7 +26,6 @@
 #include <asm/arch/regs-apbh.h>
 #include <asm/arch/regs-base.h>
 #include <asm/arch/regs-bch.h>
-#include <asm/arch/regs-clkctrl-mx28.h>
 #include <asm/arch/regs-digctl.h>
 #include <asm/arch/regs-gpmi.h>
 #include <asm/arch/regs-i2c.h>
 #include <asm/arch/regs-lradc.h>
 #include <asm/arch/regs-ocotp.h>
 #include <asm/arch/regs-pinctrl.h>
-#include <asm/arch/regs-power.h>
 #include <asm/arch/regs-rtc.h>
 #include <asm/arch/regs-ssp.h>
 #include <asm/arch/regs-timrot.h>
 
+#ifdef CONFIG_MX28
+#include <asm/arch/regs-clkctrl-mx28.h>
+#include <asm/arch/regs-power-mx28.h>
+#endif
+
 #endif /* __IMX_REGS_H__ */
index b662fbe..23e9adc 100644 (file)
 #ifndef        __ASSEMBLY__
 struct mxs_clkctrl_regs {
        mxs_reg_32(hw_clkctrl_pll0ctrl0)        /* 0x00 */
-       mxs_reg_32(hw_clkctrl_pll0ctrl1)        /* 0x10 */
+       uint32_t        hw_clkctrl_pll0ctrl1;   /* 0x10 */
+       uint32_t        reserved_pll0ctrl1[3];  /* 0x14-0x1c */
        mxs_reg_32(hw_clkctrl_pll1ctrl0)        /* 0x20 */
-       mxs_reg_32(hw_clkctrl_pll1ctrl1)        /* 0x30 */
+       uint32_t        hw_clkctrl_pll1ctrl1;   /* 0x30 */
+       uint32_t        reserved_pll1ctrl1[3];  /* 0x34-0x3c */
        mxs_reg_32(hw_clkctrl_pll2ctrl0)        /* 0x40 */
        mxs_reg_32(hw_clkctrl_cpu)              /* 0x50 */
        mxs_reg_32(hw_clkctrl_hbus)             /* 0x60 */
similarity index 99%
rename from arch/arm/include/asm/arch-mxs/regs-power.h
rename to arch/arm/include/asm/arch-mxs/regs-power-mx28.h
index a46a372..257ee88 100644 (file)
@@ -128,7 +128,7 @@ struct mxs_power_regs {
 #define        POWER_MINPWR_PWD_ANA_CMPS                       (1 << 10)
 #define        POWER_MINPWR_ENABLE_OSC                         (1 << 9)
 #define        POWER_MINPWR_SELECT_OSC                         (1 << 8)
-#define        POWER_MINPWR_FBG_OFF                            (1 << 7)
+#define        POWER_MINPWR_VBG_OFF                            (1 << 7)
 #define        POWER_MINPWR_DOUBLE_FETS                        (1 << 6)
 #define        POWER_MINPWR_HALFFETS                           (1 << 5)
 #define        POWER_MINPWR_LESSANA_I                          (1 << 4)
@@ -268,7 +268,7 @@ struct mxs_power_regs {
 #define        POWER_DCLIMITS_POSLIMIT_BUCK_MASK               (0x7f << 8)
 #define        POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET             8
 #define        POWER_DCLIMITS_NEGLIMIT_MASK                    0x7f
-#define        POWER_DCLIMITS_NETLIMIT_OFFSET                  0
+#define        POWER_DCLIMITS_NEGLIMIT_OFFSET                  0
 
 #define        POWER_LOOPCTRL_TOGGLE_DIF                       (1 << 20)
 #define        POWER_LOOPCTRL_HYST_SIGN                        (1 << 19)
index 76b901b..00e498d 100644 (file)
@@ -143,7 +143,12 @@ static inline unsigned int s5p_gpio_base(int nr)
        return S5PC110_GPIO_BASE;
 }
 
-#define s5pc110_gpio_get_nr(bank, pin) \
+static inline unsigned int s5p_gpio_part_max(int nr)
+{
+       return 0;
+}
+
+#define s5pc110_gpio_get_nr(bank, pin)   \
        ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
            - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
          * GPIO_PER_BANK) + pin)
diff --git a/arch/arm/include/asm/arch-tegra20/dc.h b/arch/arm/include/asm/arch-tegra20/dc.h
new file mode 100644 (file)
index 0000000..37934e1
--- /dev/null
@@ -0,0 +1,545 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DC_H
+#define __ASM_ARCH_TEGRA_DC_H
+
+/* Register definitions for the Tegra display controller */
+
+/* CMD register 0x000 ~ 0x43 */
+struct dc_cmd_reg {
+       /* Address 0x000 ~ 0x002 */
+       uint gen_incr_syncpt;           /* _CMD_GENERAL_INCR_SYNCPT_0 */
+       uint gen_incr_syncpt_ctrl;      /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
+       uint gen_incr_syncpt_err;       /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved0[5];              /* reserved_0[5] */
+
+       /* Address 0x008 ~ 0x00a */
+       uint win_a_incr_syncpt;         /* _CMD_WIN_A_INCR_SYNCPT_0 */
+       uint win_a_incr_syncpt_ctrl;    /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
+       uint win_a_incr_syncpt_err;     /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved1[5];              /* reserved_1[5] */
+
+       /* Address 0x010 ~ 0x012 */
+       uint win_b_incr_syncpt;         /* _CMD_WIN_B_INCR_SYNCPT_0 */
+       uint win_b_incr_syncpt_ctrl;    /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
+       uint win_b_incr_syncpt_err;     /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved2[5];              /* reserved_2[5] */
+
+       /* Address 0x018 ~ 0x01a */
+       uint win_c_incr_syncpt;         /* _CMD_WIN_C_INCR_SYNCPT_0 */
+       uint win_c_incr_syncpt_ctrl;    /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */
+       uint win_c_incr_syncpt_err;     /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */
+
+       uint reserved3[13];             /* reserved_3[13] */
+
+       /* Address 0x028 */
+       uint cont_syncpt_vsync;         /* _CMD_CONT_SYNCPT_VSYNC_0 */
+
+       uint reserved4[7];              /* reserved_4[7] */
+
+       /* Address 0x030 ~ 0x033 */
+       uint ctxsw;                     /* _CMD_CTXSW_0 */
+       uint disp_cmd_opt0;             /* _CMD_DISPLAY_COMMAND_OPTION0_0 */
+       uint disp_cmd;                  /* _CMD_DISPLAY_COMMAND_0 */
+       uint sig_raise;                 /* _CMD_SIGNAL_RAISE_0 */
+
+       uint reserved5[2];              /* reserved_0[2] */
+
+       /* Address 0x036 ~ 0x03e */
+       uint disp_pow_ctrl;             /* _CMD_DISPLAY_POWER_CONTROL_0 */
+       uint int_stat;                  /* _CMD_INT_STATUS_0 */
+       uint int_mask;                  /* _CMD_INT_MASK_0 */
+       uint int_enb;                   /* _CMD_INT_ENABLE_0 */
+       uint int_type;                  /* _CMD_INT_TYPE_0 */
+       uint int_polarity;              /* _CMD_INT_POLARITY_0 */
+       uint sig_raise1;                /* _CMD_SIGNAL_RAISE1_0 */
+       uint sig_raise2;                /* _CMD_SIGNAL_RAISE2_0 */
+       uint sig_raise3;                /* _CMD_SIGNAL_RAISE3_0 */
+
+       uint reserved6;                 /* reserved_6 */
+
+       /* Address 0x040 ~ 0x043 */
+       uint state_access;              /* _CMD_STATE_ACCESS_0 */
+       uint state_ctrl;                /* _CMD_STATE_CONTROL_0 */
+       uint disp_win_header;           /* _CMD_DISPLAY_WINDOW_HEADER_0 */
+       uint reg_act_ctrl;              /* _CMD_REG_ACT_CONTROL_0 */
+};
+
+enum {
+       PIN_REG_COUNT           = 4,
+       PIN_OUTPUT_SEL_COUNT    = 7,
+};
+
+/* COM register 0x300 ~ 0x329 */
+struct dc_com_reg {
+       /* Address 0x300 ~ 0x301 */
+       uint crc_ctrl;                  /* _COM_CRC_CONTROL_0 */
+       uint crc_checksum;              /* _COM_CRC_CHECKSUM_0 */
+
+       /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */
+       uint pin_output_enb[PIN_REG_COUNT];
+
+       /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */
+       uint pin_output_polarity[PIN_REG_COUNT];
+
+       /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */
+       uint pin_output_data[PIN_REG_COUNT];
+
+       /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */
+       uint pin_input_enb[PIN_REG_COUNT];
+
+       /* Address 0x312 ~ 0x313 */
+       uint pin_input_data0;           /* _COM_PIN_INPUT_DATA0_0 */
+       uint pin_input_data1;           /* _COM_PIN_INPUT_DATA1_0 */
+
+       /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */
+       uint pin_output_sel[PIN_OUTPUT_SEL_COUNT];
+
+       /* Address 0x31b ~ 0x329 */
+       uint pin_misc_ctrl;             /* _COM_PIN_MISC_CONTROL_0 */
+       uint pm0_ctrl;                  /* _COM_PM0_CONTROL_0 */
+       uint pm0_duty_cycle;            /* _COM_PM0_DUTY_CYCLE_0 */
+       uint pm1_ctrl;                  /* _COM_PM1_CONTROL_0 */
+       uint pm1_duty_cycle;            /* _COM_PM1_DUTY_CYCLE_0 */
+       uint spi_ctrl;                  /* _COM_SPI_CONTROL_0 */
+       uint spi_start_byte;            /* _COM_SPI_START_BYTE_0 */
+       uint hspi_wr_data_ab;           /* _COM_HSPI_WRITE_DATA_AB_0 */
+       uint hspi_wr_data_cd;           /* _COM_HSPI_WRITE_DATA_CD */
+       uint hspi_cs_dc;                /* _COM_HSPI_CS_DC_0 */
+       uint scratch_reg_a;             /* _COM_SCRATCH_REGISTER_A_0 */
+       uint scratch_reg_b;             /* _COM_SCRATCH_REGISTER_B_0 */
+       uint gpio_ctrl;                 /* _COM_GPIO_CTRL_0 */
+       uint gpio_debounce_cnt;         /* _COM_GPIO_DEBOUNCE_COUNTER_0 */
+       uint crc_checksum_latched;      /* _COM_CRC_CHECKSUM_LATCHED_0 */
+};
+
+enum dc_disp_h_pulse_pos {
+       H_PULSE0_POSITION_A,
+       H_PULSE0_POSITION_B,
+       H_PULSE0_POSITION_C,
+       H_PULSE0_POSITION_D,
+       H_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_h_pulse {
+       /* _DISP_H_PULSE0/1/2_CONTROL_0 */
+       uint h_pulse_ctrl;
+       /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */
+       uint h_pulse_pos[H_PULSE0_POSITION_COUNT];
+};
+
+enum dc_disp_v_pulse_pos {
+       V_PULSE0_POSITION_A,
+       V_PULSE0_POSITION_B,
+       V_PULSE0_POSITION_C,
+       V_PULSE0_POSITION_COUNT,
+};
+
+struct _disp_v_pulse0 {
+       /* _DISP_H_PULSE0/1_CONTROL_0 */
+       uint v_pulse_ctrl;
+       /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */
+       uint v_pulse_pos[V_PULSE0_POSITION_COUNT];
+};
+
+struct _disp_v_pulse2 {
+       /* _DISP_H_PULSE2/3_CONTROL_0 */
+       uint v_pulse_ctrl;
+       /* _DISP_H_PULSE2/3_POSITION_A_0 */
+       uint v_pulse_pos_a;
+};
+
+enum dc_disp_h_pulse_reg {
+       H_PULSE0,
+       H_PULSE1,
+       H_PULSE2,
+       H_PULSE_COUNT,
+};
+
+enum dc_disp_pp_select {
+       PP_SELECT_A,
+       PP_SELECT_B,
+       PP_SELECT_C,
+       PP_SELECT_D,
+       PP_SELECT_COUNT,
+};
+
+/* DISP register 0x400 ~ 0x4c1 */
+struct dc_disp_reg {
+       /* Address 0x400 ~ 0x40a */
+       uint disp_signal_opt0;          /* _DISP_DISP_SIGNAL_OPTIONS0_0 */
+       uint disp_signal_opt1;          /* _DISP_DISP_SIGNAL_OPTIONS1_0 */
+       uint disp_win_opt;              /* _DISP_DISP_WIN_OPTIONS_0 */
+       uint mem_high_pri;              /* _DISP_MEM_HIGH_PRIORITY_0 */
+       uint mem_high_pri_timer;        /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */
+       uint disp_timing_opt;           /* _DISP_DISP_TIMING_OPTIONS_0 */
+       uint ref_to_sync;               /* _DISP_REF_TO_SYNC_0 */
+       uint sync_width;                /* _DISP_SYNC_WIDTH_0 */
+       uint back_porch;                /* _DISP_BACK_PORCH_0 */
+       uint disp_active;               /* _DISP_DISP_ACTIVE_0 */
+       uint front_porch;               /* _DISP_FRONT_PORCH_0 */
+
+       /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_  */
+       struct _disp_h_pulse h_pulse[H_PULSE_COUNT];
+
+       /* Address 0x41a ~ 0x421 */
+       struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */
+       struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */
+
+       /* Address 0x422 ~ 0x425 */
+       struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */
+       struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */
+
+       /* Address 0x426 ~ 0x429 */
+       uint m0_ctrl;                   /* _DISP_M0_CONTROL_0 */
+       uint m1_ctrl;                   /* _DISP_M1_CONTROL_0 */
+       uint di_ctrl;                   /* _DISP_DI_CONTROL_0 */
+       uint pp_ctrl;                   /* _DISP_PP_CONTROL_0 */
+
+       /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */
+       uint pp_select[PP_SELECT_COUNT];
+
+       /* Address 0x42e ~ 0x435 */
+       uint disp_clk_ctrl;             /* _DISP_DISP_CLOCK_CONTROL_0 */
+       uint disp_interface_ctrl;       /* _DISP_DISP_INTERFACE_CONTROL_0 */
+       uint disp_color_ctrl;           /* _DISP_DISP_COLOR_CONTROL_0 */
+       uint shift_clk_opt;             /* _DISP_SHIFT_CLOCK_OPTIONS_0 */
+       uint data_enable_opt;           /* _DISP_DATA_ENABLE_OPTIONS_0 */
+       uint serial_interface_opt;      /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */
+       uint lcd_spi_opt;               /* _DISP_LCD_SPI_OPTIONS_0 */
+       uint border_color;              /* _DISP_BORDER_COLOR_0 */
+
+       /* Address 0x436 ~ 0x439 */
+       uint color_key0_lower;          /* _DISP_COLOR_KEY0_LOWER_0 */
+       uint color_key0_upper;          /* _DISP_COLOR_KEY0_UPPER_0 */
+       uint color_key1_lower;          /* _DISP_COLOR_KEY1_LOWER_0 */
+       uint color_key1_upper;          /* _DISP_COLOR_KEY1_UPPER_0 */
+
+       uint reserved0[2];              /* reserved_0[2] */
+
+       /* Address 0x43c ~ 0x442 */
+       uint cursor_foreground;         /* _DISP_CURSOR_FOREGROUND_0 */
+       uint cursor_background;         /* _DISP_CURSOR_BACKGROUND_0 */
+       uint cursor_start_addr;         /* _DISP_CURSOR_START_ADDR_0 */
+       uint cursor_start_addr_ns;      /* _DISP_CURSOR_START_ADDR_NS_0 */
+       uint cursor_pos;                /* _DISP_CURSOR_POSITION_0 */
+       uint cursor_pos_ns;             /* _DISP_CURSOR_POSITION_NS_0 */
+       uint seq_ctrl;                  /* _DISP_INIT_SEQ_CONTROL_0 */
+
+       /* Address 0x442 ~ 0x446 */
+       uint spi_init_seq_data_a;       /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
+       uint spi_init_seq_data_b;       /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
+       uint spi_init_seq_data_c;       /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
+       uint spi_init_seq_data_d;       /* _DISP_SPI_INIT_SEQ_DATA_D_0 */
+
+       uint reserved1[0x39];           /* reserved1[0x39], */
+
+       /* Address 0x480 ~ 0x484 */
+       uint dc_mccif_fifoctrl;         /* _DISP_DC_MCCIF_FIFOCTRL_0 */
+       uint mccif_disp0a_hyst;         /* _DISP_MCCIF_DISPLAY0A_HYST_0 */
+       uint mccif_disp0b_hyst;         /* _DISP_MCCIF_DISPLAY0B_HYST_0 */
+       uint mccif_disp0c_hyst;         /* _DISP_MCCIF_DISPLAY0C_HYST_0 */
+       uint mccif_disp1b_hyst;         /* _DISP_MCCIF_DISPLAY1B_HYST_0 */
+
+       uint reserved2[0x3b];           /* reserved2[0x3b] */
+
+       /* Address 0x4c0 ~ 0x4c1 */
+       uint dac_crt_ctrl;              /* _DISP_DAC_CRT_CTRL_0 */
+       uint disp_misc_ctrl;            /* _DISP_DISP_MISC_CONTROL_0 */
+};
+
+enum dc_winc_filter_p {
+       WINC_FILTER_COUNT       = 0x10,
+};
+
+/* Window A/B/C register 0x500 ~ 0x628 */
+struct dc_winc_reg {
+
+       /* Address 0x500 */
+       uint color_palette;             /* _WINC_COLOR_PALETTE_0 */
+
+       uint reserved0[0xff];           /* reserved_0[0xff] */
+
+       /* Address 0x600 */
+       uint palette_color_ext;         /* _WINC_PALETTE_COLOR_EXT_0 */
+
+       /* _WINC_H_FILTER_P00~0F_0 */
+       /* Address 0x601 ~ 0x610 */
+       uint h_filter_p[WINC_FILTER_COUNT];
+
+       /* Address 0x611 ~ 0x618 */
+       uint csc_yof;                   /* _WINC_CSC_YOF_0 */
+       uint csc_kyrgb;                 /* _WINC_CSC_KYRGB_0 */
+       uint csc_kur;                   /* _WINC_CSC_KUR_0 */
+       uint csc_kvr;                   /* _WINC_CSC_KVR_0 */
+       uint csc_kug;                   /* _WINC_CSC_KUG_0 */
+       uint csc_kvg;                   /* _WINC_CSC_KVG_0 */
+       uint csc_kub;                   /* _WINC_CSC_KUB_0 */
+       uint csc_kvb;                   /* _WINC_CSC_KVB_0 */
+
+       /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
+       uint v_filter_p[WINC_FILTER_COUNT];
+};
+
+/* WIN A/B/C Register 0x700 ~ 0x714*/
+struct dc_win_reg {
+       /* Address 0x700 ~ 0x714 */
+       uint win_opt;                   /* _WIN_WIN_OPTIONS_0 */
+       uint byte_swap;                 /* _WIN_BYTE_SWAP_0 */
+       uint buffer_ctrl;               /* _WIN_BUFFER_CONTROL_0 */
+       uint color_depth;               /* _WIN_COLOR_DEPTH_0 */
+       uint pos;                       /* _WIN_POSITION_0 */
+       uint size;                      /* _WIN_SIZE_0 */
+       uint prescaled_size;            /* _WIN_PRESCALED_SIZE_0 */
+       uint h_initial_dda;             /* _WIN_H_INITIAL_DDA_0 */
+       uint v_initial_dda;             /* _WIN_V_INITIAL_DDA_0 */
+       uint dda_increment;             /* _WIN_DDA_INCREMENT_0 */
+       uint line_stride;               /* _WIN_LINE_STRIDE_0 */
+       uint buf_stride;                /* _WIN_BUF_STRIDE_0 */
+       uint uv_buf_stride;             /* _WIN_UV_BUF_STRIDE_0 */
+       uint buffer_addr_mode;          /* _WIN_BUFFER_ADDR_MODE_0 */
+       uint dv_ctrl;                   /* _WIN_DV_CONTROL_0 */
+       uint blend_nokey;               /* _WIN_BLEND_NOKEY_0 */
+       uint blend_1win;                /* _WIN_BLEND_1WIN_0 */
+       uint blend_2win_x;              /* _WIN_BLEND_2WIN_X_0 */
+       uint blend_2win_y;              /* _WIN_BLEND_2WIN_Y_0 */
+       uint blend_3win_xy;             /* _WIN_BLEND_3WIN_XY_0 */
+       uint hp_fetch_ctrl;             /* _WIN_HP_FETCH_CONTROL_0 */
+};
+
+/* WINBUF A/B/C Register 0x800 ~ 0x80a */
+struct dc_winbuf_reg {
+       /* Address 0x800 ~ 0x80a */
+       uint start_addr;                /* _WINBUF_START_ADDR_0 */
+       uint start_addr_ns;             /* _WINBUF_START_ADDR_NS_0 */
+       uint start_addr_u;              /* _WINBUF_START_ADDR_U_0 */
+       uint start_addr_u_ns;           /* _WINBUF_START_ADDR_U_NS_0 */
+       uint start_addr_v;              /* _WINBUF_START_ADDR_V_0 */
+       uint start_addr_v_ns;           /* _WINBUF_START_ADDR_V_NS_0 */
+       uint addr_h_offset;             /* _WINBUF_ADDR_H_OFFSET_0 */
+       uint addr_h_offset_ns;          /* _WINBUF_ADDR_H_OFFSET_NS_0 */
+       uint addr_v_offset;             /* _WINBUF_ADDR_V_OFFSET_0 */
+       uint addr_v_offset_ns;          /* _WINBUF_ADDR_V_OFFSET_NS_0 */
+       uint uflow_status;              /* _WINBUF_UFLOW_STATUS_0 */
+};
+
+/* Display Controller (DC_) regs */
+struct dc_ctlr {
+       struct dc_cmd_reg cmd;          /* CMD register 0x000 ~ 0x43 */
+       uint reserved0[0x2bc];
+
+       struct dc_com_reg com;          /* COM register 0x300 ~ 0x329 */
+       uint reserved1[0xd6];
+
+       struct dc_disp_reg disp;        /* DISP register 0x400 ~ 0x4c1 */
+       uint reserved2[0x3e];
+
+       struct dc_winc_reg winc;        /* Window A/B/C 0x500 ~ 0x628 */
+       uint reserved3[0xd7];
+
+       struct dc_win_reg win;          /* WIN A/B/C 0x700 ~ 0x714*/
+       uint reserved4[0xeb];
+
+       struct dc_winbuf_reg winbuf;    /* WINBUF A/B/C 0x800 ~ 0x80a */
+};
+
+#define BIT(pos)       (1U << pos)
+
+/* DC_CMD_DISPLAY_COMMAND 0x032 */
+#define CTRL_MODE_SHIFT                5
+#define CTRL_MODE_MASK         (0x3 << CTRL_MODE_SHIFT)
+enum {
+       CTRL_MODE_STOP,
+       CTRL_MODE_C_DISPLAY,
+       CTRL_MODE_NC_DISPLAY,
+};
+
+/* _WIN_COLOR_DEPTH_0 */
+enum win_color_depth_id {
+       COLOR_DEPTH_P1,
+       COLOR_DEPTH_P2,
+       COLOR_DEPTH_P4,
+       COLOR_DEPTH_P8,
+       COLOR_DEPTH_B4G4R4A4,
+       COLOR_DEPTH_B5G5R5A,
+       COLOR_DEPTH_B5G6R5,
+       COLOR_DEPTH_AB5G5R5,
+       COLOR_DEPTH_B8G8R8A8 = 12,
+       COLOR_DEPTH_R8G8B8A8,
+       COLOR_DEPTH_B6x2G6x2R6x2A8,
+       COLOR_DEPTH_R6x2G6x2B6x2A8,
+       COLOR_DEPTH_YCbCr422,
+       COLOR_DEPTH_YUV422,
+       COLOR_DEPTH_YCbCr420P,
+       COLOR_DEPTH_YUV420P,
+       COLOR_DEPTH_YCbCr422P,
+       COLOR_DEPTH_YUV422P,
+       COLOR_DEPTH_YCbCr422R,
+       COLOR_DEPTH_YUV422R,
+       COLOR_DEPTH_YCbCr422RA,
+       COLOR_DEPTH_YUV422RA,
+};
+
+/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */
+#define PW0_ENABLE             BIT(0)
+#define PW1_ENABLE             BIT(2)
+#define PW2_ENABLE             BIT(4)
+#define PW3_ENABLE             BIT(6)
+#define PW4_ENABLE             BIT(8)
+#define PM0_ENABLE             BIT(16)
+#define PM1_ENABLE             BIT(18)
+#define SPI_ENABLE             BIT(24)
+#define HSPI_ENABLE            BIT(25)
+
+/* DC_CMD_STATE_CONTROL 0x041 */
+#define GENERAL_ACT_REQ                BIT(0)
+#define WIN_A_ACT_REQ          BIT(1)
+#define WIN_B_ACT_REQ          BIT(2)
+#define WIN_C_ACT_REQ          BIT(3)
+#define GENERAL_UPDATE         BIT(8)
+#define WIN_A_UPDATE           BIT(9)
+#define WIN_B_UPDATE           BIT(10)
+#define WIN_C_UPDATE           BIT(11)
+
+/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
+#define WINDOW_A_SELECT                BIT(4)
+#define WINDOW_B_SELECT                BIT(5)
+#define WINDOW_C_SELECT                BIT(6)
+
+/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
+#define SHIFT_CLK_DIVIDER_SHIFT        0
+#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT)
+#define        PIXEL_CLK_DIVIDER_SHIFT 8
+#define        PIXEL_CLK_DIVIDER_MSK   (0xf << PIXEL_CLK_DIVIDER_SHIFT)
+enum {
+       PIXEL_CLK_DIVIDER_PCD1,
+       PIXEL_CLK_DIVIDER_PCD1H,
+       PIXEL_CLK_DIVIDER_PCD2,
+       PIXEL_CLK_DIVIDER_PCD3,
+       PIXEL_CLK_DIVIDER_PCD4,
+       PIXEL_CLK_DIVIDER_PCD6,
+       PIXEL_CLK_DIVIDER_PCD8,
+       PIXEL_CLK_DIVIDER_PCD9,
+       PIXEL_CLK_DIVIDER_PCD12,
+       PIXEL_CLK_DIVIDER_PCD16,
+       PIXEL_CLK_DIVIDER_PCD18,
+       PIXEL_CLK_DIVIDER_PCD24,
+       PIXEL_CLK_DIVIDER_PCD13,
+};
+
+/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */
+#define DATA_FORMAT_SHIFT      0
+#define DATA_FORMAT_MASK       (0xf << DATA_FORMAT_SHIFT)
+enum {
+       DATA_FORMAT_DF1P1C,
+       DATA_FORMAT_DF1P2C24B,
+       DATA_FORMAT_DF1P2C18B,
+       DATA_FORMAT_DF1P2C16B,
+       DATA_FORMAT_DF2S,
+       DATA_FORMAT_DF3S,
+       DATA_FORMAT_DFSPI,
+       DATA_FORMAT_DF1P3C24B,
+       DATA_FORMAT_DF1P3C18B,
+};
+#define DATA_ALIGNMENT_SHIFT   8
+enum {
+       DATA_ALIGNMENT_MSB,
+       DATA_ALIGNMENT_LSB,
+};
+#define DATA_ORDER_SHIFT       9
+enum {
+       DATA_ORDER_RED_BLUE,
+       DATA_ORDER_BLUE_RED,
+};
+
+/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
+#define DE_SELECT_SHIFT                0
+#define DE_SELECT_MASK         (0x3 << DE_SELECT_SHIFT)
+#define DE_SELECT_ACTIVE_BLANK 0x0
+#define DE_SELECT_ACTIVE       0x1
+#define DE_SELECT_ACTIVE_IS    0x2
+#define DE_CONTROL_SHIFT       2
+#define DE_CONTROL_MASK                (0x7 << DE_CONTROL_SHIFT)
+enum {
+       DE_CONTROL_ONECLK,
+       DE_CONTROL_NORMAL,
+       DE_CONTROL_EARLY_EXT,
+       DE_CONTROL_EARLY,
+       DE_CONTROL_ACTIVE_BLANK,
+};
+
+/* DC_WIN_WIN_OPTIONS 0x700 */
+#define H_DIRECTION            BIT(0)
+enum {
+       H_DIRECTION_INCREMENT,
+       H_DIRECTION_DECREMENT,
+};
+#define V_DIRECTION            BIT(2)
+enum {
+       V_DIRECTION_INCREMENT,
+       V_DIRECTION_DECREMENT,
+};
+#define COLOR_EXPAND           BIT(6)
+#define CP_ENABLE              BIT(16)
+#define DV_ENABLE              BIT(20)
+#define WIN_ENABLE             BIT(30)
+
+/* DC_WIN_BYTE_SWAP 0x701 */
+#define BYTE_SWAP_SHIFT                0
+#define BYTE_SWAP_MASK         (3 << BYTE_SWAP_SHIFT)
+enum {
+       BYTE_SWAP_NOSWAP,
+       BYTE_SWAP_SWAP2,
+       BYTE_SWAP_SWAP4,
+       BYTE_SWAP_SWAP4HW
+};
+
+/* DC_WIN_POSITION 0x704 */
+#define H_POSITION_SHIFT       0
+#define H_POSITION_MASK                (0x1FFF << H_POSITION_SHIFT)
+#define V_POSITION_SHIFT       16
+#define V_POSITION_MASK                (0x1FFF << V_POSITION_SHIFT)
+
+/* DC_WIN_SIZE 0x705 */
+#define H_SIZE_SHIFT           0
+#define H_SIZE_MASK            (0x1FFF << H_SIZE_SHIFT)
+#define V_SIZE_SHIFT           16
+#define V_SIZE_MASK            (0x1FFF << V_SIZE_SHIFT)
+
+/* DC_WIN_PRESCALED_SIZE 0x706 */
+#define H_PRESCALED_SIZE_SHIFT 0
+#define H_PRESCALED_SIZE_MASK  (0x7FFF << H_PRESCALED_SIZE)
+#define V_PRESCALED_SIZE_SHIFT 16
+#define V_PRESCALED_SIZE_MASK  (0x1FFF << V_PRESCALED_SIZE)
+
+/* DC_WIN_DDA_INCREMENT 0x709 */
+#define H_DDA_INC_SHIFT                0
+#define H_DDA_INC_MASK         (0xFFFF << H_DDA_INC_SHIFT)
+#define V_DDA_INC_SHIFT                16
+#define V_DDA_INC_MASK         (0xFFFF << V_DDA_INC_SHIFT)
+
+#endif /* __ASM_ARCH_TEGRA_DC_H */
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h
new file mode 100644 (file)
index 0000000..c870959
--- /dev/null
@@ -0,0 +1,152 @@
+/*
+ *  (C) Copyright 2010
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+#include <asm/arch/dc.h>
+#include <fdtdec.h>
+
+/* This holds information about a window which can be displayed */
+struct disp_ctl_win {
+       enum win_color_depth_id fmt;    /* Color depth/format */
+       unsigned        bpp;            /* Bits per pixel */
+       phys_addr_t     phys_addr;      /* Physical address in memory */
+       unsigned        x;              /* Horizontal address offset (bytes) */
+       unsigned        y;              /* Veritical address offset (bytes) */
+       unsigned        w;              /* Width of source window */
+       unsigned        h;              /* Height of source window */
+       unsigned        stride;         /* Number of bytes per line */
+       unsigned        out_x;          /* Left edge of output window (col) */
+       unsigned        out_y;          /* Top edge of output window (row) */
+       unsigned        out_w;          /* Width of output window in pixels */
+       unsigned        out_h;          /* Height of output window in pixels */
+};
+
+#define FDT_LCD_TIMINGS        4
+
+enum {
+       FDT_LCD_TIMING_REF_TO_SYNC,
+       FDT_LCD_TIMING_SYNC_WIDTH,
+       FDT_LCD_TIMING_BACK_PORCH,
+       FDT_LCD_TIMING_FRONT_PORCH,
+
+       FDT_LCD_TIMING_COUNT,
+};
+
+enum lcd_cache_t {
+       FDT_LCD_CACHE_OFF               = 0,
+       FDT_LCD_CACHE_WRITE_THROUGH     = 1 << 0,
+       FDT_LCD_CACHE_WRITE_BACK        = 1 << 1,
+       FDT_LCD_CACHE_FLUSH             = 1 << 2,
+       FDT_LCD_CACHE_WRITE_BACK_FLUSH  = FDT_LCD_CACHE_WRITE_BACK |
+                                               FDT_LCD_CACHE_FLUSH,
+};
+
+/* Information about the display controller */
+struct fdt_disp_config {
+       int valid;                      /* config is valid */
+       int width;                      /* width in pixels */
+       int height;                     /* height in pixels */
+       int bpp;                        /* number of bits per pixel */
+
+       /*
+        * log2 of number of bpp, in general, unless it bpp is 24 in which
+        * case this field holds 24 also! This is a U-Boot thing.
+        */
+       int log2_bpp;
+       struct disp_ctlr *disp;         /* Display controller to use */
+       fdt_addr_t frame_buffer;        /* Address of frame buffer */
+       unsigned pixel_clock;           /* Pixel clock in Hz */
+       uint horiz_timing[FDT_LCD_TIMING_COUNT];        /* Horizontal timing */
+       uint vert_timing[FDT_LCD_TIMING_COUNT];         /* Vertical timing */
+       int panel_node;                 /* node offset of panel information */
+};
+
+/* Information about the LCD panel */
+struct fdt_panel_config {
+       int pwm_channel;                /* PWM channel to use for backlight */
+       enum lcd_cache_t cache_type;
+
+       struct fdt_gpio_state backlight_en;     /* GPIO for backlight enable */
+       struct fdt_gpio_state lvds_shutdown;    /* GPIO for lvds shutdown */
+       struct fdt_gpio_state backlight_vdd;    /* GPIO for backlight vdd */
+       struct fdt_gpio_state panel_vdd;        /* GPIO for panel vdd */
+       /*
+        * Panel required timings
+        * Timing 1: delay between panel_vdd-rise and data-rise
+        * Timing 2: delay between data-rise and backlight_vdd-rise
+        * Timing 3: delay between backlight_vdd and pwm-rise
+        * Timing 4: delay between pwm-rise and backlight_en-rise
+        */
+       uint panel_timings[FDT_LCD_TIMINGS];
+};
+
+/**
+ * Register a new display based on device tree configuration.
+ *
+ * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * You should pass in the U-Boot address here, and check the contents of
+ * struct fdt_disp_config to see what was actually chosen.
+ *
+ * @param blob                 Device tree blob
+ * @param default_lcd_base     Default address of LCD frame buffer
+ * @return 0 if ok, -1 on error (unsupported bits per pixel)
+ */
+int tegra_display_probe(const void *blob, void *default_lcd_base);
+
+/**
+ * Return the current display configuration
+ *
+ * @return pointer to display configuration, or NULL if there is no valid
+ * config
+ */
+struct fdt_disp_config *tegra_display_get_config(void);
+
+/**
+ * Perform the next stage of the LCD init if it is time to do so.
+ *
+ * LCD init can be time-consuming because of the number of delays we need
+ * while waiting for the backlight power supply, etc. This function can
+ * be called at various times during U-Boot operation to advance the
+ * initialization of the LCD to the next stage if sufficient time has
+ * passed since the last stage. It keeps track of what stage it is up to
+ * and the time that it is permitted to move to the next stage.
+ *
+ * The final call should have wait=1 to complete the init.
+ *
+ * @param blob fdt blob containing LCD information
+ * @param wait 1 to wait until all init is complete, and then return
+ *             0 to return immediately, potentially doing nothing if it is
+ *             not yet time for the next init.
+ */
+int tegra_lcd_check_next_stage(const void *blob, int wait);
+
+/**
+ * Set up the maximum LCD size so we can size the frame buffer.
+ *
+ * @param blob fdt blob containing LCD information
+ */
+void tegra_lcd_early_init(const void *blob);
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
index 03fa7ca..797e158 100644 (file)
@@ -339,7 +339,7 @@ void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
 
 /* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
+void pinmux_config_pingroup(const struct pingroup_config *config);
 
 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
 
@@ -349,6 +349,6 @@ void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
  * @param config       List of config items
  * @param len          Number of config items in list
  */
-void pinmux_config_table(struct pingroup_config *config, int len);
+void pinmux_config_table(const struct pingroup_config *config, int len);
 
 #endif /* PINMUX_H */
diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra20/pwm.h
new file mode 100644 (file)
index 0000000..9e03837
--- /dev/null
@@ -0,0 +1,75 @@
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWM_H
+#define __ASM_ARCH_TEGRA_PWM_H
+
+/* This is a single PWM channel */
+struct pwm_ctlr {
+       uint control;           /* Control register */
+       uint reserved[3];       /* Space space */
+};
+
+#define PWM_NUM_CHANNELS       4
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWM_ENABLE_SHIFT       31
+#define PWM_ENABLE_MASK        (0x1 << PWM_ENABLE_SHIFT)
+
+#define PWM_WIDTH_SHIFT        16
+#define PWM_WIDTH_MASK         (0x7FFF << PWM_WIDTH_SHIFT)
+
+#define PWM_DIVIDER_SHIFT      0
+#define PWM_DIVIDER_MASK       (0x1FFF << PWM_DIVIDER_SHIFT)
+
+/**
+ * Program the PWM with the given parameters.
+ *
+ * @param channel      PWM channel to update
+ * @param rate         Clock rate to use for PWM
+ * @param pulse_width  high pulse width: 0=always low, 1=1/256 pulse high,
+ *                     n = n/256 pulse high
+ * @param freq_divider frequency divider value (1 to use rate as is)
+ */
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
+
+/**
+ * Request a pwm channel as referenced by a device tree node.
+ *
+ * This channel can then be passed to pwm_enable().
+ *
+ * @param blob         Device tree blob
+ * @param node         Node containing reference to pwm
+ * @param prop_name    Property name of pwm reference
+ * @return channel number, if ok, else -1
+ */
+int pwm_request(const void *blob, int node, const char *prop_name);
+
+/**
+ * Set up the pwm controller, by looking it up in the fdt.
+ *
+ * @return 0 if ok, -1 if the device tree node was not found or invalid.
+ */
+int pwm_init(const void *blob);
+
+#endif /* __ASM_ARCH_TEGRA_PWM_H */
index 2b28a26..78ca8e0 100644 (file)
@@ -75,6 +75,37 @@ static inline void set_cr(unsigned int val)
        isb();
 }
 
+/* options available for data cache on each page */
+enum dcache_option {
+       DCACHE_OFF = 0x12,
+       DCACHE_WRITETHROUGH = 0x1a,
+       DCACHE_WRITEBACK = 0x1e,
+};
+
+/* Size of an MMU section */
+enum {
+       MMU_SECTION_SHIFT       = 20,
+       MMU_SECTION_SIZE        = 1 << MMU_SECTION_SHIFT,
+};
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start                start address of memory region to change
+ * \param size         size of memory region to change
+ * \param option       dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+                                    enum dcache_option option);
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start                start address of update in page table
+ * \param stop         stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
index 939de10..6edf815 100644 (file)
 
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
 
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define CACHE_SETUP    0x1a
-#else
-#define CACHE_SETUP    0x1e
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 void __arm_init_before_mmu(void)
@@ -50,9 +44,41 @@ static void cp_delay (void)
        asm volatile("" : : : "memory");
 }
 
-static inline void dram_bank_mmu_setup(int bank)
+void set_section_dcache(int section, enum dcache_option option)
 {
        u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 value;
+
+       value = (section << MMU_SECTION_SHIFT) | (3 << 10);
+       value |= option;
+       page_table[section] = value;
+}
+
+void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+       debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+       __attribute__((weak, alias("__mmu_page_table_flush")));
+
+void mmu_set_region_dcache_behaviour(u32 start, int size,
+                                    enum dcache_option option)
+{
+       u32 *page_table = (u32 *)gd->tlb_addr;
+       u32 upto, end;
+
+       end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
+       start = start >> MMU_SECTION_SHIFT;
+       debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+             option);
+       for (upto = start; upto < end; upto++)
+               set_section_dcache(upto, option);
+       mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+}
+
+static inline void dram_bank_mmu_setup(int bank)
+{
        bd_t *bd = gd->bd;
        int     i;
 
@@ -60,21 +86,24 @@ static inline void dram_bank_mmu_setup(int bank)
        for (i = bd->bi_dram[bank].start >> 20;
             i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
             i++) {
-               page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+               set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+               set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
        }
 }
 
 /* to activate the MMU we need to set up virtual memory: use 1M areas */
 static inline void mmu_setup(void)
 {
-       u32 *page_table = (u32 *)gd->tlb_addr;
        int i;
        u32 reg;
 
        arm_init_before_mmu();
        /* Set up an identity-mapping for all 4GB, rw for everyone */
        for (i = 0; i < 4096; i++)
-               page_table[i] = i << 20 | (3 << 10) | 0x12;
+               set_section_dcache(i, DCACHE_OFF);
 
        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
                dram_bank_mmu_setup(i);
@@ -82,7 +111,7 @@ static inline void mmu_setup(void)
 
        /* Copy the page table address to cp15 */
        asm volatile("mcr p15, 0, %0, c2, c0, 0"
-                    : : "r" (page_table) : "memory");
+                    : : "r" (gd->tlb_addr) : "memory");
        /* Set the access control to all-supervisor */
        asm volatile("mcr p15, 0, %0, c3, c0, 0"
                     : : "r" (~0));
index 0725989..6492d41 100644 (file)
@@ -61,9 +61,8 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        debug("board_mmc_init: init eMMC\n");
-       /* init dev 0, eMMC chip, with 4-bit bus */
-       /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra_mmc_init(0, 4, -1, -1);
+       /* init dev 0, eMMC chip, with 8-bit bus */
+       tegra_mmc_init(0, 8, -1, -1);
 
        debug("board_mmc_init: init SD slot\n");
        /* init dev 3, SD slot, with 4-bit bus */
index db79e77..4450674 100644 (file)
@@ -8,6 +8,7 @@
 
        aliases {
                usb0 = "/usb@c5008000";
+               usb1 = "/usb@c5000000";
        };
 
        memory {
@@ -48,7 +49,7 @@
        };
 
        usb@c5000000 {
-               status = "disabled";
+               nvidia,vbus-gpio = <&gpio 170 0>; /* PV2 */
        };
 
        usb@c5004000 {
index 9ef66fd..8f4dd09 100644 (file)
 #include <mmc.h>
 #endif
 
+void pin_mux_usb(void)
+{
+       /*
+        * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
+        * in the current device tree.
+        */
+       pinmux_tristate_disable(PINGRP_UAC);
+}
 
 void pin_mux_spi(void)
 {
index 4a8352f..d73e27e 100644 (file)
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/imx25-pinmux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
+
+#define FEC_RESET_B            IMX_GPIO_NR(2, 3)
+#define FEC_ENABLE_B           IMX_GPIO_NR(4, 8)
+#define CARD_DETECT            IMX_GPIO_NR(2, 1)
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[1] = {
+       {IMX_MMC_SDHC1_BASE},
+};
+#endif
+
+static void mx25pdk_fec_init(void)
+{
+       struct iomuxc_mux_ctl *muxctl;
+       struct iomuxc_pad_ctl *padctl;
+       u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+       u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+       /* FEC pin init is generic */
+       mx25_fec_init_pins();
+
+       muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+       padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+       /*
+        * Set up FEC_RESET_B and FEC_ENABLE_B
+        *
+        * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
+        * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
+        */
+       writel(gpio_mux_mode, &muxctl->pad_d12);
+       writel(gpio_mux_mode, &muxctl->pad_a17);
+
+       writel(0x0, &padctl->pad_d12);
+       writel(0x0, &padctl->pad_a17);
+
+       /* Assert RESET and ENABLE low */
+       gpio_direction_output(FEC_RESET_B, 0);
+       gpio_direction_output(FEC_ENABLE_B, 0);
+
+       udelay(10);
+
+       /* Deassert RESET and ENABLE */
+       gpio_set_value(FEC_RESET_B, 1);
+       gpio_set_value(FEC_ENABLE_B, 1);
+
+       /* Setup I2C pins so that PMIC can turn on PHY supply */
+       writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
+       writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
+       writel(0x1E8, &padctl->pad_i2c1_clk);
+       writel(0x1E8, &padctl->pad_i2c1_dat);
+}
+
 int dram_init(void)
 {
        /* dram_init must store complete ramsize in gd->ram_size */
@@ -48,6 +107,68 @@ int board_init(void)
        return 0;
 }
 
+int board_late_init(void)
+{
+       struct pmic *p;
+       int ret;
+
+       mx25pdk_fec_init();
+
+       ret = pmic_init(I2C_PMIC);
+       if (ret)
+               return ret;
+
+       p = pmic_get("FSL_PMIC");
+       if (!p)
+               return -ENODEV;
+
+       /* Turn on Ethernet PHY supply */
+       pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+
+       return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_getcd(struct mmc *mmc)
+{
+       struct iomuxc_mux_ctl *muxctl;
+       struct iomuxc_pad_ctl *padctl;
+       u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+
+       /*
+        * Set up the Card Detect pin.
+        *
+        * SD1_GPIO_CD: gpio2_1 is ALT 5 mode of pin A15
+        *
+        */
+       muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+       padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+
+       writel(gpio_mux_mode, &muxctl->pad_a15);
+       writel(0x0, &padctl->pad_a15);
+
+       gpio_direction_input(CARD_DETECT);
+       return !gpio_get_value(CARD_DETECT);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       struct iomuxc_mux_ctl *muxctl;
+       u32 sdhc1_mux_mode = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+       muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+       writel(sdhc1_mux_mode, &muxctl->pad_sd1_cmd);
+       writel(sdhc1_mux_mode, &muxctl->pad_sd1_clk);
+       writel(sdhc1_mux_mode, &muxctl->pad_sd1_data0);
+       writel(sdhc1_mux_mode, &muxctl->pad_sd1_data1);
+       writel(sdhc1_mux_mode, &muxctl->pad_sd1_data2);
+       writel(sdhc1_mux_mode, &muxctl->pad_sd1_data3);
+
+       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+       return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+}
+#endif
+
 int checkboard(void)
 {
        puts("Board: MX25PDK\n");
index 29ad0e6..5267729 100644 (file)
@@ -65,6 +65,8 @@ SECTIONS
 
        . = ALIGN(4);
 
+       __image_copy_end = .;
+
        .rel.dyn : {
                __rel_dyn_start = .;
                *(.rel*)
index 75bb958..da8b6f3 100644 (file)
        orr r1, r1, #0x00000C00
        orr r1, r1, #0x00000003
        str r1, [r0, #CLKCTL_CGR1]
+
+       ldr r1, [r0, #CLKCTL_CGR2]
+       orr r1, r1, #0x00C00000
+       str r1, [r0, #CLKCTL_CGR2]
 .endm
 
 .macro setup_sdram
index c835b0e..2aa000f 100644 (file)
@@ -98,6 +98,26 @@ static void setup_iomux_spi(void)
        mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
 }
 
+static void setup_iomux_usbotg(void)
+{
+       int in_pad, out_pad;
+
+       /* Set up pins for USBOTG. */
+       mxc_request_iomux(MX35_PIN_USBOTG_PWR,
+                         MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_USBOTG_OC,
+                         MUX_CONFIG_SION | MUX_CONFIG_FUNC);
+
+       in_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
+               PAD_CTL_PUE_PUD | PAD_CTL_100K_PD | PAD_CTL_ODE_CMOS |
+               PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+       out_pad = PAD_CTL_DRV_3_3V | PAD_CTL_HYS_CMOS | PAD_CTL_PKE_NONE |
+               PAD_CTL_ODE_CMOS | PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW;
+
+       mxc_iomux_set_pad(MX35_PIN_USBOTG_PWR, out_pad);
+       mxc_iomux_set_pad(MX35_PIN_USBOTG_OC, in_pad);
+}
+
 static void setup_iomux_fec(void)
 {
        int pad;
@@ -189,6 +209,7 @@ int board_early_init_f(void)
        __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
 
        setup_iomux_i2c();
+       setup_iomux_usbotg();
        setup_iomux_fec();
        setup_iomux_spi();
 
index 81c511c..2c8cb7a 100644 (file)
@@ -374,7 +374,7 @@ static int power_init(void)
                if (retval)
                        return retval;
 
-               p = pmic_get("DIALOG_PMIC");
+               p = pmic_get("FSL_PMIC");
                if (!p)
                        return -ENODEV;
 
index 2c7cd0d..76ec687 100644 (file)
 #include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/display.h>
 #include <asm/arch/emc.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
+#include <asm/arch/pwm.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch/usb.h>
 #include <asm/arch-tegra/board.h>
@@ -118,6 +120,13 @@ int board_init(void)
 #ifdef CONFIG_TEGRA_SPI
        pin_mux_spi();
        spi_init();
+#endif
+#ifdef CONFIG_PWM_TEGRA
+       if (pwm_init(gd->fdt_blob))
+               debug("%s: Failed to init pwm\n", __func__);
+#endif
+#ifdef CONFIG_LCD
+       tegra_lcd_check_next_stage(gd->fdt_blob, 0);
 #endif
        /* boot param addr */
        gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
@@ -144,6 +153,9 @@ int board_init(void)
        pin_mux_usb();
        board_usb_init(gd->fdt_blob);
 #endif
+#ifdef CONFIG_LCD
+       tegra_lcd_check_next_stage(gd->fdt_blob, 0);
+#endif
 
 #ifdef CONFIG_TEGRA_NAND
        pin_mux_nand();
@@ -174,7 +186,19 @@ int board_early_init_f(void)
        /* Initialize periph GPIOs */
        gpio_early_init();
        gpio_early_init_uart();
+#ifdef CONFIG_LCD
+       tegra_lcd_early_init(gd->fdt_blob);
+#endif
 
        return 0;
 }
 #endif /* EARLY_INIT */
+
+int board_late_init(void)
+{
+#ifdef CONFIG_LCD
+       /* Make sure we finish initing the LCD */
+       tegra_lcd_check_next_stage(gd->fdt_blob, 1);
+#endif
+       return 0;
+}
index 25a63a0..dd98ca4 100644 (file)
                        compatible = "hynix,hy27uf4g2b", "nand-flash";
                };
        };
+
+       host1x {
+               status = "okay";
+               dc@54200000 {
+                       status = "okay";
+                       rgb {
+                               status = "okay";
+                               nvidia,panel = <&lcd_panel>;
+                       };
+               };
+       };
+
+       lcd_panel: panel {
+               /* Seaboard has 1366x768 */
+               clock = <70600000>;
+               xres = <1366>;
+               yres = <768>;
+               left-margin = <58>;
+               right-margin = <58>;
+               hsync-len = <58>;
+               lower-margin = <4>;
+               upper-margin = <4>;
+               vsync-len = <4>;
+               hsync-active-high;
+               nvidia,bits-per-pixel = <16>;
+               nvidia,pwm = <&pwm 2 0>;
+               nvidia,backlight-enable-gpios = <&gpio 28 0>;   /* PD4 */
+               nvidia,lvds-shutdown-gpios = <&gpio 10 0>;      /* PB2 */
+               nvidia,backlight-vdd-gpios = <&gpio 176 0>;     /* PW0 */
+               nvidia,panel-vdd-gpios = <&gpio 22 0>;          /* PC6 */
+               nvidia,panel-timings = <400 4 203 17 15>;
+       };
+
 };
index c7590ac..93430ed 100644 (file)
@@ -64,9 +64,8 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        debug("board_mmc_init: init SD slot J26\n");
-       /* init dev 0, SD slot J26, with 4-bit bus */
-       /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
+       /* init dev 0, SD slot J26, with 8-bit bus */
+       tegra_mmc_init(0, 8, GPIO_PI6, GPIO_PH2);
 
        debug("board_mmc_init: init SD slot J5\n");
        /* init dev 2, SD slot J5, with 4-bit bus */
index c412c07..3e33da0 100644 (file)
@@ -71,9 +71,8 @@ int board_mmc_init(bd_t *bd)
        pin_mux_mmc();
 
        debug("board_mmc_init: init eMMC\n");
-       /* init dev 0, eMMC chip, with 4-bit bus */
-       /* The board has an 8-bit bus, but 8-bit doesn't work yet */
-       tegra_mmc_init(0, 4, -1, -1);
+       /* init dev 0, eMMC chip, with 8-bit bus */
+       tegra_mmc_init(0, 8, -1, -1);
 
        debug("board_mmc_init: init SD slot\n");
        /* init dev 1, SD slot, with 4-bit bus */
index 1474fa8..47c6a5a 100644 (file)
@@ -36,7 +36,7 @@ COBJS += smdk5250.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS  += mmc_boot.o
+COBJS  += spl_boot.o
 endif
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
index a5816e4..9c926d6 100644 (file)
 #include <asm/io.h>
 #include <i2c.h>
 #include <netdev.h>
+#include <spi.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/sromc.h>
+#include <power/pmic.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -63,6 +65,9 @@ static int smc9115_pre_init(void)
 int board_init(void)
 {
        gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
+#ifdef CONFIG_EXYNOS_SPI
+       spi_init();
+#endif
        return 0;
 }
 
@@ -79,6 +84,16 @@ int dram_init(void)
        return 0;
 }
 
+#if defined(CONFIG_POWER)
+int power_init_board(void)
+{
+       if (pmic_init(I2C_PMIC))
+               return -1;
+       else
+               return 0;
+}
+#endif
+
 void dram_init_banksize(void)
 {
        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
similarity index 66%
rename from board/samsung/smdk5250/mmc_boot.c
rename to board/samsung/smdk5250/spl_boot.c
index 449a919..d8f3c1e 100644 (file)
 #include<common.h>
 #include<config.h>
 
+enum boot_mode {
+       BOOT_MODE_MMC = 4,
+       BOOT_MODE_SERIAL = 20,
+       /* Boot based on Operating Mode pin settings */
+       BOOT_MODE_OM = 32,
+       BOOT_MODE_USB,  /* Boot using USB download */
+};
+
+       typedef u32 (*spi_copy_func_t)(u32 offset, u32 nblock, u32 dst);
+
 /*
 * Copy U-boot from mmc to RAM:
 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
 */
 void copy_uboot_to_ram(void)
 {
-       u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+       spi_copy_func_t spi_copy;
+       enum boot_mode bootmode;
+       u32 (*copy_bl2)(u32, u32, u32);
+
+       bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
 
-       copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE);
+       switch (bootmode) {
+       case BOOT_MODE_SERIAL:
+               spi_copy = *(spi_copy_func_t *)EXYNOS_COPY_SPI_FNPTR_ADDR;
+               spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
+                                               CONFIG_SYS_TEXT_BASE);
+               break;
+       case BOOT_MODE_MMC:
+               copy_bl2 = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR;
+               copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
+                                               CONFIG_SYS_TEXT_BASE);
+               break;
+       default:
+               break;
+       }
 }
 
 void board_init_f(unsigned long bootflag)
index e540190..4724029 100644 (file)
@@ -29,6 +29,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/mipi_dsim.h>
@@ -361,7 +362,9 @@ int power_init_board(void)
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
-               get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
+               get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
+               get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
+               get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE);
 
        return 0;
 }
@@ -372,6 +375,10 @@ void dram_init_banksize(void)
        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
        gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+       gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+       gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+       gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+       gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
 }
 
 static unsigned int get_hw_revision(void)
@@ -419,54 +426,22 @@ int board_mmc_init(bd_t *bis)
 {
        struct exynos4_gpio_part2 *gpio =
                (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
-       int i, err;
+       int err;
 
        /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
        s5p_gpio_direction_output(&gpio->k0, 2, 1);
        s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
 
-       /*
-        * eMMC GPIO:
-        * SDR 8-bit@48MHz at MMC0
-        * GPK0[0]      SD_0_CLK(2)
-        * GPK0[1]      SD_0_CMD(2)
-        * GPK0[2]      SD_0_CDn        -> Not used
-        * GPK0[3:6]    SD_0_DATA[0:3](2)
-        * GPK1[3:6]    SD_0_DATA[0:3](3)
-        *
-        * DDR 4-bit@26MHz at MMC4
-        * GPK0[0]      SD_4_CLK(3)
-        * GPK0[1]      SD_4_CMD(3)
-        * GPK0[2]      SD_4_CDn        -> Not used
-        * GPK0[3:6]    SD_4_DATA[0:3](3)
-        * GPK1[3:6]    SD_4_DATA[4:7](4)
-        */
-       for (i = 0; i < 7; i++) {
-               if (i == 2)
-                       continue;
-               /* GPK0[0:6] special function 2 */
-               s5p_gpio_cfg_pin(&gpio->k0, i, 0x2);
-               /* GPK0[0:6] pull disable */
-               s5p_gpio_set_pull(&gpio->k0, i, GPIO_PULL_NONE);
-               /* GPK0[0:6] drv 4x */
-               s5p_gpio_set_drv(&gpio->k0, i, GPIO_DRV_4X);
-       }
-
-       for (i = 3; i < 7; i++) {
-               /* GPK1[3:6] special function 3 */
-               s5p_gpio_cfg_pin(&gpio->k1, i, 0x3);
-               /* GPK1[3:6] pull disable */
-               s5p_gpio_set_pull(&gpio->k1, i, GPIO_PULL_NONE);
-               /* GPK1[3:6] drv 4x */
-               s5p_gpio_set_drv(&gpio->k1, i, GPIO_DRV_4X);
-       }
-
        /*
         * MMC device init
         * mmc0  : eMMC (8-bit buswidth)
         * mmc2  : SD card (4-bit buswidth)
         */
-       err = s5p_mmc_init(0, 8);
+       err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+       if (err)
+               debug("SDMMC0 not configured\n");
+       else
+               err = s5p_mmc_init(0, 8);
 
        /* T-flash detect */
        s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
@@ -477,24 +452,11 @@ int board_mmc_init(bd_t *bis)
         * GPX3[4] T-flash detect pin
         */
        if (!s5p_gpio_get_value(&gpio->x3, 4)) {
-               /*
-                * SD card GPIO:
-                * GPK2[0]      SD_2_CLK(2)
-                * GPK2[1]      SD_2_CMD(2)
-                * GPK2[2]      SD_2_CDn        -> Not used
-                * GPK2[3:6]    SD_2_DATA[0:3](2)
-                */
-               for (i = 0; i < 7; i++) {
-                       if (i == 2)
-                               continue;
-                       /* GPK2[0:6] special function 2 */
-                       s5p_gpio_cfg_pin(&gpio->k2, i, 0x2);
-                       /* GPK2[0:6] pull disable */
-                       s5p_gpio_set_pull(&gpio->k2, i, GPIO_PULL_NONE);
-                       /* GPK2[0:6] drv 4x */
-                       s5p_gpio_set_drv(&gpio->k2, i, GPIO_DRV_4X);
-               }
-               err = s5p_mmc_init(2, 4);
+               err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+               if (err)
+                       debug("SDMMC2 not configured\n");
+               else
+                       err = s5p_mmc_init(2, 4);
        }
 
        return err;
@@ -629,6 +591,10 @@ static void board_power_init(void)
        writel(0, (unsigned int)&pwr->lcd1_configuration);
        writel(0, (unsigned int)&pwr->gps_configuration);
        writel(0, (unsigned int)&pwr->gps_alive_configuration);
+
+       /* It is necessary to power down core 1 */
+       /* to successfully boot CPU1 in kernel */
+       writel(0, (unsigned int)&pwr->arm_core1_configuration);
 }
 
 static void board_uart_init(void)
index bfec08f..587cc1b 100644 (file)
@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB    = $(obj)lib$(BOARD).o
 
 COBJS-y        := universal.o onenand.o
-SOBJS  := lowlevel_init.o
 
 SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS   := $(addprefix $(obj),$(COBJS-y))
diff --git a/board/samsung/universal_c210/lowlevel_init.S b/board/samsung/universal_c210/lowlevel_init.S
deleted file mode 100644 (file)
index dc7f69e..0000000
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * Lowlevel setup for universal board based on EXYNOS4210
- *
- * Copyright (C) 2010 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-/*
- * Register usages:
- *
- * r5 has zero always
- * r7 has GPIO part1 base 0x11400000
- * r6 has GPIO part2 base 0x11000000
- */
-
-       .globl lowlevel_init
-lowlevel_init:
-       mov     r11, lr
-
-       /* r5 has always zero */
-       mov     r5, #0
-
-       ldr     r7, =EXYNOS4_GPIO_PART1_BASE
-       ldr     r6, =EXYNOS4_GPIO_PART2_BASE
-
-       /* System Timer */
-       ldr     r0, =EXYNOS4_SYSTIMER_BASE
-       ldr     r1, =0x5000
-       str     r1, [r0, #0x0]
-       ldr     r1, =0xffffffff
-       str     r1, [r0, #0x8]
-       ldr     r1, =0x49
-       str     r1, [r0, #0x4]
-
-       /* PMIC manual reset */
-       /* nPOWER: XEINT_23: GPX2[7] */
-       add     r0, r6, #0xC40                  @ EXYNOS4_GPIO_X2_OFFSET
-       ldr     r1, [r0, #0x0]
-       bic     r1, r1, #(0xf << 28)            @ 28 = 7 * 4-bit
-       orr     r1, r1, #(0x1 << 28)            @ Output
-       str     r1, [r0, #0x0]
-
-       ldr     r1, [r0, #0x4]
-       orr     r1, r1, #(1 << 7)               @ 7 = 7 * 1-bit
-       str     r1, [r0, #0x4]
-
-       /* init system clock */
-       bl      system_clock_init
-
-       /* Disable Watchdog */
-       ldr     r0, =EXYNOS4_WATCHDOG_BASE              @0x10060000
-       str     r5, [r0]
-
-       /* UART */
-       bl      uart_asm_init
-
-       /* PMU init */
-       bl      system_power_init
-
-       bl      tzpc_init
-
-       mov     lr, r11
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-/*
- * uart_asm_init: Initialize UART's pins
- */
-uart_asm_init:
-       /*
-        * setup UART0-UART4 GPIOs (part1)
-        * GPA1CON[3] = I2C_3_SCL (3)
-        * GPA1CON[2] = I2C_3_SDA (3)
-        */
-       mov     r0, r7
-       ldr     r1, =0x22222222
-       str     r1, [r0, #0x00]                 @ EXYNOS4_GPIO_A0_OFFSET
-       ldr     r1, =0x00223322
-       str     r1, [r0, #0x20]                 @ EXYNOS4_GPIO_A1_OFFSET
-
-       /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
-       add     r0, r6, #0x1A0                  @ EXYNOS4_GPIO_Y4_OFFSET
-       ldr     r1, [r0, #0x0]
-       bic     r1, r1, #(0xf << 28)            @ 28 = 7 * 4-bit
-       orr     r1, r1, #(0x1 << 28)
-       str     r1, [r0, #0x0]
-
-       ldr     r1, [r0, #0x8]
-       bic     r1, r1, #(0x3 << 14)            @ 14 = 7 * 2-bit
-       orr     r1, r1, #(0x3 << 14)            @ Pull-up enabled
-       str     r1, [r0, #0x8]
-
-       ldr     r1, [r0, #0x4]
-       orr     r1, r1, #(1 << 7)               @ 7 = 7 * 1-bit
-       str     r1, [r0, #0x4]
-
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-system_clock_init:
-       ldr     r0, =EXYNOS4_CLOCK_BASE
-
-       /* APLL(1), MPLL(1), CORE(0), HPM(0) */
-       ldr     r1, =0x0101
-       ldr     r2, =0x14200                    @ CLK_SRC_CPU
-       str     r1, [r0, r2]
-
-       /* wait ?us */
-       mov     r1, #0x10000
-1:     subs    r1, r1, #1
-       bne     1b
-
-       /*
-        * CLK_SRC_TOP0
-        * MUX_ONENAND_SEL[28]  0: DOUT133, 1: DOUT166
-        * MUX_VPLL_SEL[8]      0: FINPLL,  1: FOUTVPLL
-        * MUX_EPLL_SEL[4]      0: FINPLL,  1: FOUTEPLL
-        */
-       ldr     r1, =0x10000110
-       ldr     r2, =0x0C210                    @ CLK_SRC_TOP
-       str     r1, [r0, r2]
-
-       /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
-       ldr     r1, =0x0066666
-       ldr     r2, =0x0C240                    @ CLK_SRC_FSYS
-       str     r1, [r0, r2]
-       /* UART[0:5], PWM: SCLKMPLL(6) */
-       ldr     r1, =0x6666666
-       ldr     r2, =0x0C250                    @ CLK_SRC_PERIL0_OFFSET
-       str     r1, [r0, r2]
-
-       /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */
-       ldr     r1, =0x0133730
-       ldr     r2, =0x14500                    @ CLK_DIV_CPU0
-       str     r1, [r0, r2]
-       /* CPU1: COPY, HPM */
-       ldr     r1, =0x03
-       ldr     r2, =0x14504                    @ CLK_DIV_CPU1
-       str     r1, [r0, r2]
-       /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */
-       ldr     r1, =0x13111113
-       ldr     r2, =0x10500                    @ CLK_DIV_DMC0
-       str     r1, [r0, r2]
-       /* DMC1: PWI, DVSEM, DPM */
-       ldr     r1, =0x01010100
-       ldr     r2, =0x10504                    @ CLK_DIV_DMC1
-       str     r1, [r0, r2]
-       /* LEFTBUS: GDL, GPL */
-       ldr     r1, =0x13
-       ldr     r2, =0x04500                    @ CLK_DIV_LEFTBUS
-       str     r1, [r0, r2]
-       /* RIGHHTBUS: GDR, GPR */
-       ldr     r1, =0x13
-       ldr     r2, =0x08500                    @ CLK_DIV_RIGHTBUS
-       str     r1, [r0, r2]
-       /*
-        * CLK_DIV_TOP
-        * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1)
-        * ACLK_200, ACLK_100, ACLK_160, ACLK_133,
-        */
-       ldr     r1, =0x00005473
-       ldr     r2, =0x0C510                    @ CLK_DIV_TOP
-       str     r1, [r0, r2]
-       /* MMC[0:1] */
-       ldr     r1, =0x000f000f                 /* 800(MPLL) / (15 + 1) */
-       ldr     r2, =0x0C544                    @ CLK_DIV_FSYS1
-       str     r1, [r0, r2]
-       /* MMC[2:3] */
-       ldr     r1, =0x000f000f                 /* 800(MPLL) / (15 + 1) */
-       ldr     r2, =0x0C548                    @ CLK_DIV_FSYS2
-       str     r1, [r0, r2]
-       /* MMC4 */
-       ldr     r1, =0x000f                     /* 800(MPLL) / (15 + 1) */
-       ldr     r2, =0x0C54C                    @ CLK_DIV_FSYS3
-       str     r1, [r0, r2]
-       /* UART[0:5] */
-       ldr     r1, =0x774777
-       ldr     r2, =0x0C550                    @ CLK_DIV_PERIL0
-       str     r1, [r0, r2]
-       /* SLIMBUS: ???, PWM */
-       ldr     r1, =0x8
-       ldr     r2, =0x0C55C                    @ CLK_DIV_PERIL3
-       str     r1, [r0, r2]
-
-       /* PLL Setting */
-       ldr     r1, =0x1C20
-       ldr     r2, =0x14000                    @ APLL_LOCK
-       str     r1, [r0, r2]
-       ldr     r2, =0x14008                    @ MPLL_LOCK
-       str     r1, [r0, r2]
-       ldr     r2, =0x0C010                    @ EPLL_LOCK
-       str     r1, [r0, r2]
-       ldr     r2, =0x0C020                    @ VPLL_LOCK
-       str     r1, [r0, r2]
-
-       /* APLL */
-       ldr     r1, =0x8000001c
-       ldr     r2, =0x14104                    @ APLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80c80601                 @ 800MHz
-       ldr     r2, =0x14100                    @ APLL_CON0
-       str     r1, [r0, r2]
-       /* MPLL */
-       ldr     r1, =0x8000001C
-       ldr     r2, =0x1410C                    @ MPLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80c80601                 @ 800MHz
-       ldr     r2, =0x14108                    @ MPLL_CON0
-       str     r1, [r0, r2]
-       /* EPLL */
-       ldr     r1, =0x0
-       ldr     r2, =0x0C114                    @ EPLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80300302                 @ 96MHz
-       ldr     r2, =0x0C110                    @ EPLL_CON0
-       str     r1, [r0, r2]
-       /* VPLL */
-       ldr     r1, =0x11000400
-       ldr     r2, =0x0C124                    @ VPLL_CON1
-       str     r1, [r0, r2]
-       ldr     r1, =0x80350302                 @ 108MHz
-       ldr     r2, =0x0C120                    @ VPLL_CON0
-       str     r1, [r0, r2]
-
-       /*
-        * SMMUJPEG[11], JPEG[6], CSIS1[5]              : 0111 1001
-        * Turn off all
-        */
-       ldr     r1, =0xFFF80000
-       ldr     r2, =0x0C920                    @ CLK_GATE_IP_CAM
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFC0
-       ldr     r2, =0x0C924                    @ CLK_GATE_IP_VP
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFE0
-       ldr     r2, =0x0C928                    @ CLK_GATE_IP_MFC
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFFC
-       ldr     r2, =0x0C92C                    @ CLK_GATE_IP_G3D
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFC00
-       ldr     r2, =0x0C930                    @ CLK_GATE_IP_IMAGE
-       str     r1, [r0, r2]
-
-       /* DSIM0[3], MDNIE0[2], MIE0[1]                 : 0001 */
-       ldr     r1, =0xFFFFFFF1
-       ldr     r2, =0x0C934                    @ CLK_GATE_IP_LCD0
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFC0
-       ldr     r2, =0x0C938                    @ CLK_GATE_IP_LCD1
-       str     r1, [r0, r2]
-
-       /*
-        * SMMUPCIE[18], NFCON[16]                      : 1111 1010
-        * PCIE[14],  SATA[10], SDMMC43[9:8]            : 1011 1000
-        * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2]    : 1010 0011
-        */
-       ldr     r1, =0xFFFAB8A3
-       ldr     r2, =0x0C940                    @ CLK_GATE_IP_FSYS
-       str     r1, [r0, r2]
-
-       /* Turn off all */
-       ldr     r1, =0xFFFFFFFC
-       ldr     r2, =0x0C94C                    @ CLK_GATE_IP_GPS
-       str     r1, [r0, r2]
-
-       /*
-        * AC97[27], SPDIF[26], SLIMBUS[25]             : 1111 0001
-        * I2C2[8]                                      : 1111 1110
-        */
-       ldr     r1, =0xF1FFFEFF
-       ldr     r2, =0x0C950                    @ CLK_GATE_IP_PERIL
-       str     r1, [r0, r2]
-
-       /*
-        * KEYIF[16]                                    : 1111 1110
-        */
-       ldr     r1, =0xFFFEFFFF
-       ldr     r2, =0x0C960                    @ CLK_GATE_IP_PERIR
-       str     r1, [r0, r2]
-
-       /* LCD1[5], G3D[3], MFC[2], TV[1]               : 1101 0001 */
-       ldr     r1, =0xFFFFFFD1
-       ldr     r2, =0x0C970                    @ CLK_GATE_BLOCK
-       str     r1, [r0, r2]
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-system_power_init:
-       ldr     r0, =EXYNOS4_POWER_BASE         @ 0x10020000
-
-       ldr     r2, =0x330C                     @ PS_HOLD_CONTROL
-       ldr     r1, [r0, r2]
-       orr     r1, r1, #(0x3 << 8)             @ Data High, Output En
-       str     r1, [r0, r2]
-
-       /* Power Down */
-       add     r2, r0, #0x3000
-       str     r5, [r2, #0xC20]                @ TV_CONFIGURATION
-       str     r5, [r2, #0xC40]                @ MFC_CONFIGURATION
-       str     r5, [r2, #0xC60]                @ G3D_CONFIGURATION
-       str     r5, [r2, #0xCA0]                @ LCD1_CONFIGURATION
-       str     r5, [r2, #0xCE0]                @ GPS_CONFIGURATION
-
-       mov     pc, lr
-       nop
-       nop
-       nop
-
-tzpc_init:
-       ldr     r0, =0x10110000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10120000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10130000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10140000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       ldr     r0, =0x10150000
-       mov     r1, #0x0
-       str     r1, [r0]
-       mov     r1, #0xff
-       str     r1, [r0, #0x0804]
-       str     r1, [r0, #0x0810]
-       str     r1, [r0, #0x081C]
-       str     r1, [r0, #0x0828]
-
-       mov     pc, lr
index 36a0472..e742707 100644 (file)
  */
 
 #include <common.h>
+#include <spi.h>
+#include <lcd.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/adc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/watchdog.h>
+#include <libtizen.h>
+#include <ld9040.h>
 #include <power/pmic.h>
 #include <usb/s3c_udc.h>
 #include <asm/arch/cpu.h>
@@ -48,21 +55,7 @@ static int get_hwrev(void)
        return board_rev & 0xFF;
 }
 
-static void check_hw_revision(void);
-
-int board_init(void)
-{
-       gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
-       gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
-
-       gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
-       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-       check_hw_revision();
-       printf("HW Revision:\t0x%x\n", board_rev);
-
-       return 0;
-}
+static void init_pmic_lcd(void);
 
 int power_init_board(void)
 {
@@ -72,6 +65,8 @@ int power_init_board(void)
        if (ret)
                return ret;
 
+       init_pmic_lcd();
+
        return 0;
 }
 
@@ -186,7 +181,7 @@ int checkboard(void)
 #ifdef CONFIG_GENERIC_MMC
 int board_mmc_init(bd_t *bis)
 {
-       int i, err;
+       int err;
 
        switch (get_hwrev()) {
        case 0:
@@ -209,75 +204,30 @@ int board_mmc_init(bd_t *bis)
        }
 
        /*
-        * eMMC GPIO:
-        * SDR 8-bit@48MHz at MMC0
-        * GPK0[0]      SD_0_CLK(2)
-        * GPK0[1]      SD_0_CMD(2)
-        * GPK0[2]      SD_0_CDn        -> Not used
-        * GPK0[3:6]    SD_0_DATA[0:3](2)
-        * GPK1[3:6]    SD_0_DATA[0:3](3)
-        *
-        * DDR 4-bit@26MHz at MMC4
-        * GPK0[0]      SD_4_CLK(3)
-        * GPK0[1]      SD_4_CMD(3)
-        * GPK0[2]      SD_4_CDn        -> Not used
-        * GPK0[3:6]    SD_4_DATA[0:3](3)
-        * GPK1[3:6]    SD_4_DATA[4:7](4)
+        * MMC device init
+        * mmc0  : eMMC (8-bit buswidth)
+        * mmc2  : SD card (4-bit buswidth)
         */
-       for (i = 0; i < 7; i++) {
-               if (i == 2)
-                       continue;
-               /* GPK0[0:6] special function 2 */
-               s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2);
-               /* GPK0[0:6] pull disable */
-               s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE);
-               /* GPK0[0:6] drv 4x */
-               s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X);
-       }
-
-       for (i = 3; i < 7; i++) {
-               /* GPK1[3:6] special function 3 */
-               s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3);
-               /* GPK1[3:6] pull disable */
-               s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE);
-               /* GPK1[3:6] drv 4x */
-               s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X);
-       }
+       err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+       if (err)
+               debug("SDMMC0 not configured\n");
+       else
+               err = s5p_mmc_init(0, 8);
 
        /* T-flash detect */
        s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
        s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
 
-       /*
-        * MMC device init
-        * mmc0  : eMMC (8-bit buswidth)
-        * mmc2  : SD card (4-bit buswidth)
-        */
-       err = s5p_mmc_init(0, 8);
-
        /*
         * Check the T-flash  detect pin
         * GPX3[4] T-flash detect pin
         */
        if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
-               /*
-                * SD card GPIO:
-                * GPK2[0]      SD_2_CLK(2)
-                * GPK2[1]      SD_2_CMD(2)
-                * GPK2[2]      SD_2_CDn        -> Not used
-                * GPK2[3:6]    SD_2_DATA[0:3](2)
-                */
-               for (i = 0; i < 7; i++) {
-                       if (i == 2)
-                               continue;
-                       /* GPK2[0:6] special function 2 */
-                       s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2);
-                       /* GPK2[0:6] pull disable */
-                       s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE);
-                       /* GPK2[0:6] drv 4x */
-                       s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X);
-               }
-               err = s5p_mmc_init(2, 4);
+               err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+               if (err)
+                       debug("SDMMC2 not configured\n");
+               else
+                       err = s5p_mmc_init(2, 4);
        }
 
        return err;
@@ -331,3 +281,242 @@ struct s3c_plat_otg_data s5pc210_otg_data = {
        .usb_flags = PHY0_SLEEP,
 };
 #endif
+
+int board_early_init_f(void)
+{
+       wdt_stop();
+
+       return 0;
+}
+
+#ifdef CONFIG_SOFT_SPI
+static void soft_spi_init(void)
+{
+       gpio_direction_output(CONFIG_SOFT_SPI_GPIO_SCLK,
+               CONFIG_SOFT_SPI_MODE & SPI_CPOL);
+       gpio_direction_output(CONFIG_SOFT_SPI_GPIO_MOSI, 1);
+       gpio_direction_input(CONFIG_SOFT_SPI_GPIO_MISO);
+       gpio_direction_output(CONFIG_SOFT_SPI_GPIO_CS,
+               !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+               !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+       SPI_SCL(1);
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+               CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_CS,
+               !(CONFIG_SOFT_SPI_MODE & SPI_CS_HIGH));
+}
+
+int  spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && cs == 0;
+}
+
+void universal_spi_scl(int bit)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_SCLK, bit);
+}
+
+void universal_spi_sda(int bit)
+{
+       gpio_set_value(CONFIG_SOFT_SPI_GPIO_MOSI, bit);
+}
+
+int universal_spi_read(void)
+{
+       return gpio_get_value(CONFIG_SOFT_SPI_GPIO_MISO);
+}
+#endif
+
+static void init_pmic_lcd(void)
+{
+       unsigned char val;
+       int ret = 0;
+
+       struct pmic *p = pmic_get("MAX8998_PMIC");
+
+       if (!p)
+               return;
+
+       if (pmic_probe(p))
+               return;
+
+       /* LDO7 1.8V */
+       val = 0x02; /* (1800 - 1600) / 100; */
+       ret |= pmic_reg_write(p,  MAX8998_REG_LDO7, val);
+
+       /* LDO17 3.0V */
+       val = 0xe; /* (3000 - 1600) / 100; */
+       ret |= pmic_reg_write(p,  MAX8998_REG_LDO17, val);
+
+       /* Disable unneeded regulators */
+       /*
+        * ONOFF1
+        * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
+        * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
+        */
+       val = 0xB9;
+       ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF1, val);
+
+       /* ONOFF2
+        * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
+        * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
+        */
+       val = 0x50;
+       ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF2, val);
+
+       /* ONOFF3
+        * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
+        * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
+        */
+       val = 0x00;
+       ret |= pmic_reg_write(p,  MAX8998_REG_ONOFF3, val);
+
+       if (ret)
+               puts("LCD pmic initialisation error!\n");
+}
+
+static void lcd_cfg_gpio(void)
+{
+       unsigned int i, f3_end = 4;
+
+       for (i = 0; i < 8; i++) {
+               /* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
+               s5p_gpio_cfg_pin(&gpio1->f0, i, GPIO_FUNC(2));
+               s5p_gpio_cfg_pin(&gpio1->f1, i, GPIO_FUNC(2));
+               s5p_gpio_cfg_pin(&gpio1->f2, i, GPIO_FUNC(2));
+               /* pull-up/down disable */
+               s5p_gpio_set_pull(&gpio1->f0, i, GPIO_PULL_NONE);
+               s5p_gpio_set_pull(&gpio1->f1, i, GPIO_PULL_NONE);
+               s5p_gpio_set_pull(&gpio1->f2, i, GPIO_PULL_NONE);
+
+               /* drive strength to max (24bit) */
+               s5p_gpio_set_drv(&gpio1->f0, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+               s5p_gpio_set_drv(&gpio1->f1, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f1, i, GPIO_DRV_SLOW);
+               s5p_gpio_set_drv(&gpio1->f2, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f0, i, GPIO_DRV_SLOW);
+       }
+
+       for (i = 0; i < f3_end; i++) {
+               /* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
+               s5p_gpio_cfg_pin(&gpio1->f3, i, GPIO_FUNC(2));
+               /* pull-up/down disable */
+               s5p_gpio_set_pull(&gpio1->f3, i, GPIO_PULL_NONE);
+               /* drive strength to max (24bit) */
+               s5p_gpio_set_drv(&gpio1->f3, i, GPIO_DRV_4X);
+               s5p_gpio_set_rate(&gpio1->f3, i, GPIO_DRV_SLOW);
+       }
+
+       /* gpio pad configuration for LCD reset. */
+       s5p_gpio_cfg_pin(&gpio2->y4, 5, GPIO_OUTPUT);
+
+       spi_init();
+}
+
+static void reset_lcd(void)
+{
+       s5p_gpio_set_value(&gpio2->y4, 5, 1);
+       udelay(10000);
+       s5p_gpio_set_value(&gpio2->y4, 5, 0);
+       udelay(10000);
+       s5p_gpio_set_value(&gpio2->y4, 5, 1);
+       udelay(100);
+}
+
+static void lcd_power_on(void)
+{
+       struct pmic *p = pmic_get("MAX8998_PMIC");
+
+       if (!p)
+               return;
+
+       if (pmic_probe(p))
+               return;
+
+       pmic_set_output(p, MAX8998_REG_ONOFF3, MAX8998_LDO17, LDO_ON);
+       pmic_set_output(p, MAX8998_REG_ONOFF2, MAX8998_LDO7, LDO_ON);
+}
+
+vidinfo_t panel_info = {
+       .vl_freq        = 60,
+       .vl_col         = 480,
+       .vl_row         = 800,
+       .vl_width       = 480,
+       .vl_height      = 800,
+       .vl_clkp        = CONFIG_SYS_HIGH,
+       .vl_hsp         = CONFIG_SYS_HIGH,
+       .vl_vsp         = CONFIG_SYS_HIGH,
+       .vl_dp          = CONFIG_SYS_HIGH,
+
+       .vl_bpix        = 5,    /* Bits per pixel */
+
+       /* LD9040 LCD Panel */
+       .vl_hspw        = 2,
+       .vl_hbpd        = 16,
+       .vl_hfpd        = 16,
+
+       .vl_vspw        = 2,
+       .vl_vbpd        = 8,
+       .vl_vfpd        = 8,
+       .vl_cmd_allow_len = 0xf,
+
+       .win_id         = 0,
+       .cfg_gpio       = lcd_cfg_gpio,
+       .backlight_on   = NULL,
+       .lcd_power_on   = lcd_power_on,
+       .reset_lcd      = reset_lcd,
+       .dual_lcd_enabled = 0,
+
+       .init_delay     = 0,
+       .power_on_delay = 10000,
+       .reset_delay    = 10000,
+       .interface_mode = FIMD_RGB_INTERFACE,
+       .mipi_enabled   = 0,
+};
+
+void init_panel_info(vidinfo_t *vid)
+{
+       vid->logo_on    = 1;
+       vid->resolution = HD_RESOLUTION;
+       vid->rgb_mode   = MODE_RGB_P;
+
+#ifdef CONFIG_TIZEN
+       get_tizen_logo_info(vid);
+#endif
+
+       /* for LD9040. */
+       vid->pclk_name = 1;     /* MPLL */
+       vid->sclk_div = 1;
+
+       vid->cfg_ldo = ld9040_cfg_ldo;
+       vid->enable_ldo = ld9040_enable_ldo;
+
+       setenv("lcdinfo", "lcd=ld9040");
+}
+
+int board_init(void)
+{
+       gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+       gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
+
+       gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+#ifdef CONFIG_SOFT_SPI
+       soft_spi_init();
+#endif
+       check_hw_revision();
+       printf("HW Revision:\t0x%x\n", board_rev);
+
+       return 0;
+}
index fe5589d..4f37c59 100644 (file)
@@ -33,6 +33,7 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile
new file mode 100644 (file)
index 0000000..b60163f
--- /dev/null
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := woodburn.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/woodburn/imximage.cfg b/board/woodburn/imximage.cfg
new file mode 100644 (file)
index 0000000..b4cc8ec
--- /dev/null
@@ -0,0 +1,4 @@
+BOOT_FROM      sd
+
+# DDR2 init
+DATA 4 0xB8001010 0x00000304
diff --git a/board/woodburn/lowlevel_init.S b/board/woodburn/lowlevel_init.S
new file mode 100644 (file)
index 0000000..57fb1b1
--- /dev/null
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+       core_init
+
+       init_aips
+
+       init_max
+
+       init_m3if
+
+       mov pc, lr
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
new file mode 100644 (file)
index 0000000..d74f360
--- /dev/null
@@ -0,0 +1,264 @@
+/*
+ * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
+ *
+ * Based on flea3.c and mx35pdk.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+#include <spl.h>
+
+#define CCM_CCMR_CONFIG                0x003F4208
+
+#define ESDCTL_DDR2_CONFIG     0x007FFC3F
+
+/* For MMC */
+#define GPIO_MMC_CD    7
+#define GPIO_MMC_WP    8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+               PHYS_SDRAM_1_SIZE);
+
+       return 0;
+}
+
+static void board_setup_sdram(void)
+{
+       struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+       /* Initialize with default values both CSD0/1 */
+       writel(0x2000, &esdc->esdctl0);
+       writel(0x2000, &esdc->esdctl1);
+
+       mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+                13, 10, 2, 0x8080);
+}
+
+static void setup_iomux_fec(void)
+{
+       /* setup pins for FEC */
+       mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+}
+
+int woodburn_init(void)
+{
+       struct ccm_regs *ccm =
+               (struct ccm_regs *)IMX_CCM_BASE;
+
+       /* initialize PLL and clock configuration */
+       writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+       /* Set-up RAM */
+       board_setup_sdram();
+
+       /* enable clocks */
+       writel(readl(&ccm->cgr0) |
+               MXC_CCM_CGR0_EMI_MASK |
+               MXC_CCM_CGR0_EDIO_MASK |
+               MXC_CCM_CGR0_EPIT1_MASK,
+               &ccm->cgr0);
+
+       writel(readl(&ccm->cgr1) |
+               MXC_CCM_CGR1_FEC_MASK |
+               MXC_CCM_CGR1_GPIO1_MASK |
+               MXC_CCM_CGR1_GPIO2_MASK |
+               MXC_CCM_CGR1_GPIO3_MASK |
+               MXC_CCM_CGR1_I2C1_MASK |
+               MXC_CCM_CGR1_I2C2_MASK |
+               MXC_CCM_CGR1_I2C3_MASK,
+               &ccm->cgr1);
+
+       /* Set-up NAND */
+       __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+       /* Set pinmux for the required peripherals */
+       setup_iomux_fec();
+
+       /* setup GPIO1_4 FEC_ENABLE signal */
+       mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5);
+       gpio_direction_output(4, 1);
+       mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5);
+       gpio_direction_output(9, 1);
+
+       return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD)
+void board_init_f(ulong dummy)
+{
+       /* Set the stack pointer. */
+       asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
+
+       /* Initialize MUX and SDRAM */
+       woodburn_init();
+
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end__ - __bss_start);
+
+       /* Set global data pointer. */
+       gd = &gdata;
+
+       preloader_console_init();
+       timer_init();
+
+       board_init_r(NULL, 0);
+}
+
+void spl_board_init(void)
+{
+}
+
+#endif
+
+
+/* Booting from NOR in external mode */
+int board_early_init_f(void)
+{
+       return woodburn_init();
+}
+
+
+int board_init(void)
+{
+       struct pmic *p;
+       u32 val;
+       int ret;
+
+       /* address of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       ret = pmic_init(I2C_PMIC);
+       if (ret)
+               return ret;
+
+       p = pmic_get("FSL_PMIC");
+
+       /*
+        * Set switchers in Auto in NORMAL mode & STANDBY mode
+        * Setup the switcher mode for SW1 & SW2
+        */
+       pmic_reg_read(p, REG_SW_4, &val);
+       val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
+               (SWMODE_MASK << SWMODE2_SHIFT)));
+       val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
+               (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
+       /* Set SWILIMB */
+       val |= (1 << 22);
+       pmic_reg_write(p, REG_SW_4, val);
+
+       /* Setup the switcher mode for SW3 & SW4 */
+       pmic_reg_read(p, REG_SW_5, &val);
+       val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
+               (SWMODE_MASK << SWMODE3_SHIFT));
+       val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
+               (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
+       pmic_reg_write(p, REG_SW_5, val);
+
+       /* Set VGEN1 to 3.15V */
+       pmic_reg_read(p, REG_SETTING_0, &val);
+       val &= ~(VGEN1_MASK);
+       val |= VGEN1_3_15;
+       pmic_reg_write(p, REG_SETTING_0, val);
+
+       pmic_reg_read(p, REG_MODE_0, &val);
+       val |= VGEN1EN;
+       pmic_reg_write(p, REG_MODE_0, val);
+       udelay(2000);
+
+       return 0;
+}
+
+#if defined(CONFIG_FSL_ESDHC)
+struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
+
+int board_mmc_init(bd_t *bis)
+{
+       /* configure pins for SDHC1 only */
+       mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC);
+       mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC);
+
+       /* MMC Card Detect on GPIO1_7 */
+       mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5);
+       mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
+       gpio_direction_input(GPIO_MMC_CD);
+
+       mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
+       mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
+       gpio_direction_output(GPIO_MMC_WP, 0);
+
+       esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+
+       return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       return !gpio_get_value(GPIO_MMC_CD);
+}
+#endif
+
+u32 get_board_rev(void)
+{
+       int rev = 0;
+
+       return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
index 2acc941..91504c0 100644 (file)
@@ -50,6 +50,8 @@ tt01                         arm         arm1136     -                   hale
 imx31_litekit                arm         arm1136     -                   logicpd        mx31
 flea3                        arm         arm1136     -                   CarMediaLab    mx35
 mx35pdk                      arm         arm1136     -                   freescale      mx35
+woodburn                     arm         arm1136     -                   -              mx35
+woodburn_sd                  arm         arm1136     woodburn            -              mx35        woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg
 omap2420h4                   arm         arm1136     -                   ti             omap24xx
 tnetv107x_evm                arm         arm1176     tnetv107xevm        ti             tnetv107x
 rpi_b                        arm         arm1176     rpi_b               raspberrypi    bcm2835
index c774395..54fcc81 100644 (file)
@@ -79,6 +79,7 @@ COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
 COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
 COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
 COBJS-$(CONFIG_CMD_DATE) += cmd_date.o
+COBJS-$(CONFIG_CMD_SOUND) += cmd_sound.o
 ifdef CONFIG_4xx
 COBJS-$(CONFIG_CMD_SETGETDCR) += cmd_dcr.o
 endif
diff --git a/common/cmd_sound.c b/common/cmd_sound.c
new file mode 100644 (file)
index 0000000..459d1eb
--- /dev/null
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fdtdec.h>
+#include <sound.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Initilaise sound subsystem */
+static int do_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       int ret;
+
+       ret = sound_init();
+       if (ret) {
+               printf("Initialise Audio driver failed\n");
+               return CMD_RET_FAILURE;
+       }
+
+       return 0;
+}
+
+/* play sound from buffer */
+static int do_play(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       int ret = 0;
+       int msec = 1000;
+       int freq = 400;
+
+       if (argc > 1)
+               msec = simple_strtoul(argv[1], NULL, 10);
+       if (argc > 2)
+               freq = simple_strtoul(argv[2], NULL, 10);
+
+       ret = sound_play(msec, freq);
+       if (ret) {
+               printf("play failed");
+               return CMD_RET_FAILURE;
+       }
+
+       return 0;
+}
+
+static cmd_tbl_t cmd_sound_sub[] = {
+       U_BOOT_CMD_MKENT(init, 0, 1, do_init, "", ""),
+       U_BOOT_CMD_MKENT(play, 2, 1, do_play, "", ""),
+};
+
+/* process sound command */
+static int do_sound(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       cmd_tbl_t *c;
+
+       if (argc < 1)
+               return CMD_RET_USAGE;
+
+       /* Strip off leading 'sound' command argument */
+       argc--;
+       argv++;
+
+       c = find_cmd_tbl(argv[0], &cmd_sound_sub[0], ARRAY_SIZE(cmd_sound_sub));
+
+       if (c)
+               return c->cmd(cmdtp, flag, argc, argv);
+       else
+               return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+       sound, 4, 1, do_sound,
+       "sound sub-system",
+       "init - initialise the sound driver\n"
+       "sound play [len] [freq] - play a sound for len ms at freq hz\n"
+);
index 4c83a8b..4778655 100644 (file)
 # endif
 #endif
 
+#ifndef CONFIG_LCD_ALIGNMENT
+#define CONFIG_LCD_ALIGNMENT PAGE_SIZE
+#endif
+
+/* By default we scroll by a single line */
+#ifndef CONFIG_CONSOLE_SCROLL_LINES
+#define CONFIG_CONSOLE_SCROLL_LINES 1
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 ulong lcd_setmem (ulong addr);
@@ -90,6 +99,9 @@ static void lcd_setbgcolor(int color);
 
 char lcd_is_enabled = 0;
 
+static char lcd_flush_dcache;  /* 1 to flush dcache after each lcd update */
+
+
 #ifdef NOT_USED_SO_FAR
 static void lcd_getcolreg(ushort regno,
                                ushort *red, ushort *green, ushort *blue);
@@ -98,15 +110,46 @@ static int lcd_getfgcolor(void);
 
 /************************************************************************/
 
+/* Flush LCD activity to the caches */
+void lcd_sync(void)
+{
+       /*
+        * flush_dcache_range() is declared in common.h but it seems that some
+        * architectures do not actually implement it. Is there a way to find
+        * out whether it exists? For now, ARM is safe.
+        */
+#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
+       int line_length;
+
+       if (lcd_flush_dcache)
+               flush_dcache_range((u32)lcd_base,
+                       (u32)(lcd_base + lcd_get_size(&line_length)));
+#endif
+}
+
+void lcd_set_flush_dcache(int flush)
+{
+       lcd_flush_dcache = (flush != 0);
+}
+
 /*----------------------------------------------------------------------*/
 
 static void console_scrollup(void)
 {
-       /* Copy up rows ignoring the first one */
-       memcpy(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND, CONSOLE_SCROLL_SIZE);
+       const int rows = CONFIG_CONSOLE_SCROLL_LINES;
 
-       /* Clear the last one */
-       memset(CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
+       /* Copy up rows ignoring those that will be overwritten */
+       memcpy(CONSOLE_ROW_FIRST,
+              lcd_console_address + CONSOLE_ROW_SIZE * rows,
+              CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows);
+
+       /* Clear the last rows */
+       memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows,
+               COLOR_MASK(lcd_color_bg),
+              CONSOLE_ROW_SIZE * rows);
+
+       lcd_sync();
+       console_row -= rows;
 }
 
 /*----------------------------------------------------------------------*/
@@ -135,7 +178,8 @@ static inline void console_newline(void)
        if (console_row >= CONSOLE_ROWS) {
                /* Scroll everything up */
                console_scrollup();
-               --console_row;
+       } else {
+               lcd_sync();
        }
 }
 
@@ -191,6 +235,7 @@ void lcd_puts(const char *s)
        while (*s) {
                lcd_putc(*s++);
        }
+       lcd_sync();
 }
 
 /*----------------------------------------------------------------------*/
@@ -326,6 +371,12 @@ static void test_pattern(void)
 /* ** GENERIC Initialization Routines                                  */
 /************************************************************************/
 
+int lcd_get_size(int *line_length)
+{
+       *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+       return *line_length * panel_info.vl_row;
+}
+
 int drv_lcd_init (void)
 {
        struct stdio_dev lcddev;
@@ -333,7 +384,7 @@ int drv_lcd_init (void)
 
        lcd_base = (void *)(gd->fb_base);
 
-       lcd_line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
+       lcd_get_size(&lcd_line_length);
 
        lcd_init(lcd_base);             /* LCD initialization */
 
@@ -352,13 +403,6 @@ int drv_lcd_init (void)
 }
 
 /*----------------------------------------------------------------------*/
-static
-int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
-       lcd_clear();
-       return 0;
-}
-
 void lcd_clear(void)
 {
 #if LCD_BPP == LCD_MONOCHROME
@@ -400,6 +444,14 @@ void lcd_clear(void)
 
        console_col = 0;
        console_row = 0;
+       lcd_sync();
+}
+
+static int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int argc,
+                       char *const argv[])
+{
+       lcd_clear();
+       return 0;
 }
 
 U_BOOT_CMD(
@@ -445,15 +497,16 @@ static int lcd_init(void *lcdbase)
 ulong lcd_setmem(ulong addr)
 {
        ulong size;
-       int line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
+       int line_length;
 
        debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col,
                panel_info.vl_row, NBITS(panel_info.vl_bpix));
 
-       size = line_length * panel_info.vl_row;
+       size = lcd_get_size(&line_length);
 
-       /* Round up to nearest full page */
-       size = (size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
+       /* Round up to nearest full page, or MMU section if defined */
+       size = ALIGN(size, CONFIG_LCD_ALIGNMENT);
+       addr = ALIGN(addr - CONFIG_LCD_ALIGNMENT + 1, CONFIG_LCD_ALIGNMENT);
 
        /* Allocate pages for the frame buffer. */
        addr -= size;
@@ -610,6 +663,7 @@ void bitmap_plot(int x, int y)
        }
 
        WATCHDOG_RESET();
+       lcd_sync();
 }
 #else
 static inline void bitmap_plot(int x, int y) {}
@@ -975,6 +1029,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
                break;
        };
 
+       lcd_sync();
        return 0;
 }
 #endif
index b145f85..5d8454e 100644 (file)
@@ -1141,8 +1141,16 @@ int readline_into_buffer(const char *const prompt, char *buffer, int timeout)
                                        puts (tab_seq+(col&07));
                                        col += 8 - (col&07);
                                } else {
-                                       ++col;          /* echo input           */
-                                       putc (c);
+                                       char buf[2];
+
+                                       /*
+                                        * Echo input using puts() to force am
+                                        * LCD flush if we are using an LCD
+                                        */
+                                       ++col;
+                                       buf[0] = c;
+                                       buf[1] = '\0';
+                                       puts(buf);
                                }
                                *p++ = c;
                                ++n;
index f7eab7d..e08941e 100644 (file)
@@ -15,3 +15,8 @@ i.MX5x SoCs.
     mode), which causes the effect of this failure to be much lower (in terms
     of frequency deviation), avoiding system failure, or at least decreasing
     the likelihood of system failure.
+
+1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+    This option should be enabled for boards having a SYS_ON_OFF_CTL signal
+    connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
+    reference designs.
diff --git a/doc/device-tree-bindings/pwm/tegra20-pwm.txt b/doc/device-tree-bindings/pwm/tegra20-pwm.txt
new file mode 100644 (file)
index 0000000..01438ec
--- /dev/null
@@ -0,0 +1,18 @@
+Tegra SoC PWFM controller
+
+Required properties:
+- compatible: should be one of:
+  - "nvidia,tegra20-pwm"
+  - "nvidia,tegra30-pwm"
+- reg: physical base address and length of the controller's registers
+- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
+  first cell specifies the per-chip index of the PWM to use and the second
+  cell is the period in nanoseconds.
+
+Example:
+
+       pwm: pwm@7000a000 {
+               compatible = "nvidia,tegra20-pwm";
+               reg = <0x7000a000 0x100>;
+               #pwm-cells = <2>;
+       };
diff --git a/doc/device-tree-bindings/video/displaymode.txt b/doc/device-tree-bindings/video/displaymode.txt
new file mode 100644 (file)
index 0000000..45ca42d
--- /dev/null
@@ -0,0 +1,42 @@
+videomode bindings
+==================
+
+(from http://lists.freedesktop.org/archives/dri-devel/2012-July/024875.html)
+
+Required properties:
+ - xres, yres: Display resolution
+ - left-margin, right-margin, hsync-len: Horizontal Display timing
+   parameters in pixels
+ - upper-margin, lower-margin, vsync-len: Vertical display timing
+   parameters in lines
+ - clock: display clock in Hz
+
+Optional properties:
+ - width-mm, height-mm: Display dimensions in mm
+ - hsync-active-high (bool): Hsync pulse is active high
+ - vsync-active-high (bool): Vsync pulse is active high
+ - interlaced (bool): This is an interlaced mode
+ - doublescan (bool): This is a doublescan mode
+
+There are different ways of describing a display mode. The devicetree
+representation corresponds to the one used by the Linux Framebuffer
+framework described here in Documentation/fb/framebuffer.txt. This
+representation has been chosen because it's the only format which does
+not allow for inconsistent parameters. Unlike the Framebuffer framework
+the devicetree has the clock in Hz instead of ps.
+
+Example:
+
+       display@0 {
+               /* 1920x1080p24 */
+               clock = <52000000>;
+               xres = <1920>;
+               yres = <1080>;
+               left-margin = <25>;
+               right-margin = <25>;
+               hsync-len = <25>;
+               lower-margin = <2>;
+               upper-margin = <2>;
+               vsync-len = <2>;
+               hsync-active-high;
+       };
diff --git a/doc/device-tree-bindings/video/tegra20-dc.txt b/doc/device-tree-bindings/video/tegra20-dc.txt
new file mode 100644 (file)
index 0000000..4731c3f
--- /dev/null
@@ -0,0 +1,85 @@
+Display Controller
+------------------
+
+(there isn't yet a generic binding in Linux, so this describes what is in
+U-Boot, and may change based on Linux activity)
+
+The device node for a display device is as described in the document
+"Open Firmware Recommended Practice : Universal Serial Bus" with the
+following modifications and additions :
+
+Required properties :
+ - compatible : Should be "nvidia,tegra20-dc"
+
+Required subnode 'rgb' is as follows:
+
+Required properties (rgb) :
+ - nvidia,panel : phandle of LCD panel information
+
+
+The panel node describes the panel itself. This has the properties listed in
+displaymode.txt as well as:
+
+Required properties (panel) :
+ - nvidia,bits-per-pixel: number of bits per pixel (depth)
+ - nvidia,pwm : pwm to use to set display contrast (see tegra20-pwm.txt)
+ - nvidia,panel-timings: 4 cells containing required timings in ms:
+       * delay before asserting panel_vdd
+       * delay between panel_vdd-rise and data-rise
+       * delay between data-rise and backlight_vdd-rise
+       * delay between backlight_vdd and pwm-rise
+       * delay between pwm-rise and backlight_en-rise
+
+Optional GPIO properies all have (phandle, GPIO number, flags):
+ - nvidia,backlight-enable-gpios: backlight enable GPIO
+ - nvidia,lvds-shutdown-gpios: LVDS power shutdown GPIO
+ - nvidia,backlight-vdd-gpios: backlight power GPIO
+ - nvidia,panel-vdd-gpios: panel power GPIO
+
+Example:
+
+host1x {
+       compatible = "nvidia,tegra20-host1x", "simple-bus";
+       reg = <0x50000000 0x00024000>;
+       interrupts = <0 65 0x04   /* mpcore syncpt */
+                       0 67 0x04>; /* mpcore general */
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+       status = "okay";
+
+       ranges = <0x54000000 0x54000000 0x04000000>;
+
+       dc@54200000 {
+               compatible = "nvidia,tegra20-dc";
+               reg = <0x54200000 0x00040000>;
+               interrupts = <0 73 0x04>;
+               status = "okay";
+
+               rgb {
+                       status = "okay";
+                       nvidia,panel = <&lcd_panel>;
+     &nbs