Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 19 Feb 2014 11:04:45 +0000 (12:04 +0100)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 19 Feb 2014 11:04:45 +0000 (12:04 +0100)
488 files changed:
MAKEALL
Makefile
README
arch/arc/config.mk [new file with mode: 0644]
arch/arc/cpu/arc700/Makefile [new file with mode: 0644]
arch/arc/cpu/arc700/cache.c [new file with mode: 0644]
arch/arc/cpu/arc700/config.mk [new file with mode: 0644]
arch/arc/cpu/arc700/cpu.c [new file with mode: 0644]
arch/arc/cpu/arc700/interrupts.c [new file with mode: 0644]
arch/arc/cpu/arc700/reset.c [new file with mode: 0644]
arch/arc/cpu/arc700/start.S [new file with mode: 0644]
arch/arc/cpu/arc700/timer.c [new file with mode: 0644]
arch/arc/cpu/arc700/u-boot.lds [new file with mode: 0644]
arch/arc/include/asm/arch-arc700/hardware.h [new file with mode: 0644]
arch/arc/include/asm/arcregs.h [new file with mode: 0644]
arch/arc/include/asm/bitops.h [new file with mode: 0644]
arch/arc/include/asm/byteorder.h [new file with mode: 0644]
arch/arc/include/asm/cache.h [new file with mode: 0644]
arch/arc/include/asm/config.h [new file with mode: 0644]
arch/arc/include/asm/errno.h [new file with mode: 0644]
arch/arc/include/asm/global_data.h [new file with mode: 0644]
arch/arc/include/asm/io.h [new file with mode: 0644]
arch/arc/include/asm/posix_types.h [new file with mode: 0644]
arch/arc/include/asm/ptrace.h [new file with mode: 0644]
arch/arc/include/asm/sections.h [new file with mode: 0644]
arch/arc/include/asm/string.h [new file with mode: 0644]
arch/arc/include/asm/types.h [new file with mode: 0644]
arch/arc/include/asm/u-boot-arc.h [new file with mode: 0644]
arch/arc/include/asm/u-boot.h [new file with mode: 0644]
arch/arc/include/asm/unaligned.h [new file with mode: 0644]
arch/arc/lib/Makefile [new file with mode: 0644]
arch/arc/lib/bootm.c [new file with mode: 0644]
arch/arc/lib/memcmp.S [new file with mode: 0644]
arch/arc/lib/memcpy-700.S [new file with mode: 0644]
arch/arc/lib/memset.S [new file with mode: 0644]
arch/arc/lib/relocate.c [new file with mode: 0644]
arch/arc/lib/sections.c [new file with mode: 0644]
arch/arc/lib/strchr-700.S [new file with mode: 0644]
arch/arc/lib/strcmp.S [new file with mode: 0644]
arch/arc/lib/strcpy-700.S [new file with mode: 0644]
arch/arc/lib/strlen.S [new file with mode: 0644]
arch/arm/cpu/arm1176/bcm2835/config.mk [deleted file]
arch/arm/cpu/arm720t/tegra-common/cpu.c
arch/arm/cpu/arm720t/tegra-common/cpu.h
arch/arm/cpu/arm720t/tegra114/cpu.c
arch/arm/cpu/arm720t/tegra124/Makefile [new file with mode: 0644]
arch/arm/cpu/arm720t/tegra124/config.mk [new file with mode: 0644]
arch/arm/cpu/arm720t/tegra124/cpu.c [new file with mode: 0644]
arch/arm/cpu/arm720t/tegra30/cpu.c
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/cpu/armv7/tegra124/Makefile [new file with mode: 0644]
arch/arm/cpu/armv7/tegra124/config.mk [new file with mode: 0644]
arch/arm/cpu/armv7/zynq/Makefile
arch/arm/cpu/armv7/zynq/clk.c [new file with mode: 0644]
arch/arm/cpu/armv7/zynq/cpu.c
arch/arm/cpu/armv7/zynq/slcr.c
arch/arm/cpu/armv7/zynq/spl.c [new file with mode: 0644]
arch/arm/cpu/armv7/zynq/timer.c
arch/arm/cpu/armv7/zynq/u-boot-spl.lds [new file with mode: 0644]
arch/arm/cpu/armv7/zynq/u-boot.lds [moved from arch/arm/cpu/ixp/u-boot.lds with 58% similarity]
arch/arm/cpu/ixp/Makefile [deleted file]
arch/arm/cpu/ixp/config.mk [deleted file]
arch/arm/cpu/ixp/cpu.c [deleted file]
arch/arm/cpu/ixp/interrupts.c [deleted file]
arch/arm/cpu/ixp/start.S [deleted file]
arch/arm/cpu/ixp/timer.c [deleted file]
arch/arm/cpu/tegra-common/ap.c
arch/arm/cpu/tegra-common/board.c
arch/arm/cpu/tegra-common/cache.c
arch/arm/cpu/tegra-common/clock.c
arch/arm/cpu/tegra114-common/clock.c
arch/arm/cpu/tegra124-common/Makefile [new file with mode: 0644]
arch/arm/cpu/tegra124-common/clock.c [new file with mode: 0644]
arch/arm/cpu/tegra124-common/funcmux.c [new file with mode: 0644]
arch/arm/cpu/tegra124-common/pinmux.c [new file with mode: 0644]
arch/arm/cpu/tegra20-common/clock.c
arch/arm/cpu/tegra30-common/clock.c
arch/arm/dts/tegra114.dtsi
arch/arm/dts/tegra124.dtsi [new file with mode: 0644]
arch/arm/include/asm/arch-bcm2835/mbox.h
arch/arm/include/asm/arch-exynos/cpu.h
arch/arm/include/asm/arch-exynos/dwmmc.h
arch/arm/include/asm/arch-exynos/gpio.h
arch/arm/include/asm/arch-exynos/periph.h
arch/arm/include/asm/arch-ixp/ixp425.h [deleted file]
arch/arm/include/asm/arch-ixp/ixp425pci.h [deleted file]
arch/arm/include/asm/arch-s5pc1xx/cpu.h
arch/arm/include/asm/arch-s5pc1xx/gpio.h
arch/arm/include/asm/arch-tegra/clk_rst.h
arch/arm/include/asm/arch-tegra/clock.h
arch/arm/include/asm/arch-tegra/gp_padctrl.h
arch/arm/include/asm/arch-tegra/pmc.h
arch/arm/include/asm/arch-tegra/tegra.h
arch/arm/include/asm/arch-tegra124/ahb.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/clock-tables.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/clock.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/flow.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/funcmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/gp_padctrl.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/hardware.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/pinmux.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/pmu.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/sysctr.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/tegra.h [new file with mode: 0644]
arch/arm/include/asm/arch-tegra124/usb.h [new file with mode: 0644]
arch/arm/include/asm/arch-zynq/clk.h [new file with mode: 0644]
arch/arm/include/asm/arch-zynq/hardware.h
arch/arm/include/asm/arch-zynq/spl.h [new file with mode: 0644]
arch/arm/include/asm/arch-zynq/sys_proto.h
arch/arm/include/asm/global_data.h
arch/blackfin/cpu/initcode.h
arch/blackfin/cpu/start.S
arch/blackfin/include/asm/mach-common/bits/emac.h
arch/blackfin/lib/board.c
arch/microblaze/cpu/Makefile
arch/microblaze/cpu/exception.c
arch/microblaze/cpu/spl.c [new file with mode: 0644]
arch/microblaze/cpu/start.S
arch/microblaze/cpu/timer.c
arch/microblaze/cpu/u-boot-spl.lds [new file with mode: 0644]
arch/microblaze/include/asm/spl.h [new file with mode: 0644]
arch/microblaze/include/asm/u-boot.h
arch/microblaze/lib/board.c
arch/nds32/cpu/n1213/ag101/asm-offsets.c
arch/nds32/cpu/n1213/ag101/lowlevel_init.S
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
arch/powerpc/cpu/mpc85xx/t1040_ids.c
arch/powerpc/cpu/mpc85xx/t1040_serdes.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/fsl_serdes.h
arch/powerpc/include/asm/immap_85xx.h
arch/sandbox/cpu/Makefile
board/actux1/Makefile [deleted file]
board/actux1/actux1.c [deleted file]
board/actux1/actux1_hw.h [deleted file]
board/actux1/u-boot.lds [deleted file]
board/actux2/Makefile [deleted file]
board/actux2/actux2.c [deleted file]
board/actux2/actux2_hw.h [deleted file]
board/actux2/u-boot.lds [deleted file]
board/actux3/Makefile [deleted file]
board/actux3/actux3.c [deleted file]
board/actux3/actux3_hw.h [deleted file]
board/actux3/u-boot.lds [deleted file]
board/actux4/Makefile [deleted file]
board/actux4/actux4.c [deleted file]
board/actux4/actux4_hw.h [deleted file]
board/altera/nios2-generic/nios2-generic.c
board/bf609-ezkit/bf609-ezkit.c
board/boundary/nitrogen6x/nitrogen6x.c
board/dvlhost/Makefile [deleted file]
board/dvlhost/dvlhost.c [deleted file]
board/dvlhost/dvlhost_hw.h [deleted file]
board/dvlhost/u-boot.lds [deleted file]
board/dvlhost/watchdog.c [deleted file]
board/freescale/t1040qds/Makefile
board/freescale/t1040qds/README
board/freescale/t1040qds/eth.c [new file with mode: 0644]
board/freescale/t1040qds/t1040qds.c
board/freescale/t104xrdb/Makefile
board/freescale/t104xrdb/README
board/freescale/t104xrdb/eth.c [new file with mode: 0644]
board/keymile/km_arm/fpga_config.c
board/keymile/km_arm/km_arm.c
board/keymile/kmp204x/Makefile
board/keymile/kmp204x/kmp204x.c
board/keymile/kmp204x/kmp204x.h
board/keymile/kmp204x/pbi.cfg
board/keymile/kmp204x/pci.c
board/keymile/kmp204x/qrio.c [new file with mode: 0644]
board/keymile/kmp204x/rcw_kmp204x.cfg
board/keymile/scripts/develop-arm.txt
board/keymile/scripts/develop-common.txt
board/keymile/scripts/develop-ppc_82xx.txt
board/keymile/scripts/develop-ppc_8xx.txt
board/keymile/scripts/ramfs-arm.txt
board/keymile/scripts/ramfs-common.txt
board/keymile/scripts/ramfs-ppc_82xx.txt
board/keymile/scripts/ramfs-ppc_8xx.txt
board/nvidia/common/board.c
board/nvidia/dts/tegra124-venice2.dts [new file with mode: 0644]
board/nvidia/venice2/Makefile [new file with mode: 0644]
board/nvidia/venice2/as3722_init.c [new file with mode: 0644]
board/nvidia/venice2/as3722_init.h [new file with mode: 0644]
board/nvidia/venice2/pinmux-config-venice2.h [new file with mode: 0644]
board/nvidia/venice2/venice2.c [new file with mode: 0644]
board/samsung/common/Makefile
board/samsung/common/dfu_sample_env.txt [new file with mode: 0644]
board/samsung/common/misc.c [new file with mode: 0644]
board/samsung/dts/exynos5250-smdk5250.dts
board/samsung/dts/exynos5250-snow.dts
board/samsung/goni/goni.c
board/samsung/smdk5250/lowlevel_init.S [deleted file]
board/samsung/smdk5250/smdk5250.c
board/samsung/trats/trats.c
board/samsung/trats2/trats2.c
board/samsung/universal_c210/universal.c
board/spear/spear300/spear300.c
board/spear/spear310/spear310.c
board/spear/spear320/spear320.c
board/spear/spear600/spear600.c
board/spear/x600/x600.c
board/synopsys/arcangel4/Makefile [new file with mode: 0644]
board/synopsys/axs101/Makefile [new file with mode: 0644]
board/synopsys/axs101/axs101.c [new file with mode: 0644]
board/synopsys/axs101/nand.c [new file with mode: 0644]
board/ti/dra7xx/README [new file with mode: 0644]
board/ti/omap5_uevm/README [new file with mode: 0644]
board/xilinx/zynq/Makefile
board/xilinx/zynq/board.c
board/xilinx/zynq/ps7_init.c [new file with mode: 0644]
boards.cfg
common/Makefile
common/cmd_bdinfo.c
common/cmd_clk.c [new file with mode: 0644]
common/cmd_mmc.c
common/cmd_pxe.c
common/image.c
common/lcd.c
common/spl/spl_mmc.c
config.mk
doc/README.ARC [new file with mode: 0644]
doc/README.b4860qds
doc/README.designware_eth [deleted file]
doc/README.scrapyard
doc/driver-model/UDM-pci.txt
doc/driver-model/UDM-serial.txt
drivers/fpga/zynqpl.c
drivers/gpio/s5p_gpio.c
drivers/i2c/soft_i2c.c
drivers/mmc/dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
drivers/mmc/mmc.c
drivers/mmc/tegra_mmc.c
drivers/mmc/zynq_sdhci.c
drivers/mtd/nand/fsl_ifc_nand.c
drivers/mtd/nand/fsl_ifc_spl.c
drivers/net/bfin_mac.c
drivers/net/designware.c
drivers/net/designware.h
drivers/net/fm/t1040.c
drivers/net/npe/IxEthAcc.c [deleted file]
drivers/net/npe/IxEthAccCommon.c [deleted file]
drivers/net/npe/IxEthAccControlInterface.c [deleted file]
drivers/net/npe/IxEthAccDataPlane.c [deleted file]
drivers/net/npe/IxEthAccMac.c [deleted file]
drivers/net/npe/IxEthAccMii.c [deleted file]
drivers/net/npe/IxEthDBAPI.c [deleted file]
drivers/net/npe/IxEthDBAPISupport.c [deleted file]
drivers/net/npe/IxEthDBCore.c [deleted file]
drivers/net/npe/IxEthDBEvents.c [deleted file]
drivers/net/npe/IxEthDBFeatures.c [deleted file]
drivers/net/npe/IxEthDBFirewall.c [deleted file]
drivers/net/npe/IxEthDBHashtable.c [deleted file]
drivers/net/npe/IxEthDBLearning.c [deleted file]
drivers/net/npe/IxEthDBMem.c [deleted file]
drivers/net/npe/IxEthDBNPEAdaptor.c [deleted file]
drivers/net/npe/IxEthDBPortUpdate.c [deleted file]
drivers/net/npe/IxEthDBReports.c [deleted file]
drivers/net/npe/IxEthDBSearch.c [deleted file]
drivers/net/npe/IxEthDBSpanningTree.c [deleted file]
drivers/net/npe/IxEthDBUtil.c [deleted file]
drivers/net/npe/IxEthDBVlan.c [deleted file]
drivers/net/npe/IxEthDBWiFi.c [deleted file]
drivers/net/npe/IxEthMii.c [deleted file]
drivers/net/npe/IxFeatureCtrl.c [deleted file]
drivers/net/npe/IxNpeDl.c [deleted file]
drivers/net/npe/IxNpeDlImageMgr.c [deleted file]
drivers/net/npe/IxNpeDlNpeMgr.c [deleted file]
drivers/net/npe/IxNpeDlNpeMgrUtils.c [deleted file]
drivers/net/npe/IxNpeMh.c [deleted file]
drivers/net/npe/IxNpeMhConfig.c [deleted file]
drivers/net/npe/IxNpeMhReceive.c [deleted file]
drivers/net/npe/IxNpeMhSend.c [deleted file]
drivers/net/npe/IxNpeMhSolicitedCbMgr.c [deleted file]
drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c [deleted file]
drivers/net/npe/IxOsalBufferMgt.c [deleted file]
drivers/net/npe/IxOsalIoMem.c [deleted file]
drivers/net/npe/IxOsalOsCacheMMU.c [deleted file]
drivers/net/npe/IxOsalOsMsgQ.c [deleted file]
drivers/net/npe/IxOsalOsSemaphore.c [deleted file]
drivers/net/npe/IxOsalOsServices.c [deleted file]
drivers/net/npe/IxOsalOsThread.c [deleted file]
drivers/net/npe/IxQMgrAqmIf.c [deleted file]
drivers/net/npe/IxQMgrDispatcher.c [deleted file]
drivers/net/npe/IxQMgrInit.c [deleted file]
drivers/net/npe/IxQMgrQAccess.c [deleted file]
drivers/net/npe/IxQMgrQCfg.c [deleted file]
drivers/net/npe/Makefile [deleted file]
drivers/net/npe/include/IxAssert.h [deleted file]
drivers/net/npe/include/IxAtmSch.h [deleted file]
drivers/net/npe/include/IxAtmTypes.h [deleted file]
drivers/net/npe/include/IxAtmdAcc.h [deleted file]
drivers/net/npe/include/IxAtmdAccCtrl.h [deleted file]
drivers/net/npe/include/IxAtmm.h [deleted file]
drivers/net/npe/include/IxDmaAcc.h [deleted file]
drivers/net/npe/include/IxEthAcc.h [deleted file]
drivers/net/npe/include/IxEthAccDataPlane_p.h [deleted file]
drivers/net/npe/include/IxEthAccMac_p.h [deleted file]
drivers/net/npe/include/IxEthAccMii_p.h [deleted file]
drivers/net/npe/include/IxEthAccQueueAssign_p.h [deleted file]
drivers/net/npe/include/IxEthAcc_p.h [deleted file]
drivers/net/npe/include/IxEthDB.h [deleted file]
drivers/net/npe/include/IxEthDBLocks_p.h [deleted file]
drivers/net/npe/include/IxEthDBLog_p.h [deleted file]
drivers/net/npe/include/IxEthDBMessages_p.h [deleted file]
drivers/net/npe/include/IxEthDBPortDefs.h [deleted file]
drivers/net/npe/include/IxEthDBQoS.h [deleted file]
drivers/net/npe/include/IxEthDB_p.h [deleted file]
drivers/net/npe/include/IxEthMii.h [deleted file]
drivers/net/npe/include/IxEthMii_p.h [deleted file]
drivers/net/npe/include/IxEthNpe.h [deleted file]
drivers/net/npe/include/IxFeatureCtrl.h [deleted file]
drivers/net/npe/include/IxHssAcc.h [deleted file]
drivers/net/npe/include/IxI2cDrv.h [deleted file]
drivers/net/npe/include/IxNpeA.h [deleted file]
drivers/net/npe/include/IxNpeDl.h [deleted file]
drivers/net/npe/include/IxNpeDlImageMgr_p.h [deleted file]
drivers/net/npe/include/IxNpeDlMacros_p.h [deleted file]
drivers/net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h [deleted file]
drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h [deleted file]
drivers/net/npe/include/IxNpeDlNpeMgr_p.h [deleted file]
drivers/net/npe/include/IxNpeMh.h [deleted file]
drivers/net/npe/include/IxNpeMhConfig_p.h [deleted file]
drivers/net/npe/include/IxNpeMhMacros_p.h [deleted file]
drivers/net/npe/include/IxNpeMhReceive_p.h [deleted file]
drivers/net/npe/include/IxNpeMhSend_p.h [deleted file]
drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h [deleted file]
drivers/net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h [deleted file]
drivers/net/npe/include/IxNpeMicrocode.h [deleted file]
drivers/net/npe/include/IxOsBufLib.h [deleted file]
drivers/net/npe/include/IxOsBuffMgt.h [deleted file]
drivers/net/npe/include/IxOsBuffPoolMgt.h [deleted file]
drivers/net/npe/include/IxOsCacheMMU.h [deleted file]
drivers/net/npe/include/IxOsPrintf.h [deleted file]
drivers/net/npe/include/IxOsServices.h [deleted file]
drivers/net/npe/include/IxOsServicesComponents.h [deleted file]
drivers/net/npe/include/IxOsServicesEndianess.h [deleted file]
drivers/net/npe/include/IxOsServicesMemAccess.h [deleted file]
drivers/net/npe/include/IxOsServicesMemMap.h [deleted file]
drivers/net/npe/include/IxOsal.h [deleted file]
drivers/net/npe/include/IxOsalAssert.h [deleted file]
drivers/net/npe/include/IxOsalBackward.h [deleted file]
drivers/net/npe/include/IxOsalBackwardAssert.h [deleted file]
drivers/net/npe/include/IxOsalBackwardBufferMgt.h [deleted file]
drivers/net/npe/include/IxOsalBackwardCacheMMU.h [deleted file]
drivers/net/npe/include/IxOsalBackwardMemMap.h [deleted file]
drivers/net/npe/include/IxOsalBackwardOsServices.h [deleted file]
drivers/net/npe/include/IxOsalBackwardOssl.h [deleted file]
drivers/net/npe/include/IxOsalBufferMgt.h [deleted file]
drivers/net/npe/include/IxOsalBufferMgtDefault.h [deleted file]
drivers/net/npe/include/IxOsalConfig.h [deleted file]
drivers/net/npe/include/IxOsalEndianess.h [deleted file]
drivers/net/npe/include/IxOsalIoMem.h [deleted file]
drivers/net/npe/include/IxOsalMemAccess.h [deleted file]
drivers/net/npe/include/IxOsalOem.h [deleted file]
drivers/net/npe/include/IxOsalOs.h [deleted file]
drivers/net/npe/include/IxOsalOsAssert.h [deleted file]
drivers/net/npe/include/IxOsalOsBufferMgt.h [deleted file]
drivers/net/npe/include/IxOsalOsIxp400.h [deleted file]
drivers/net/npe/include/IxOsalOsIxp400CustomizedMapping.h [deleted file]
drivers/net/npe/include/IxOsalOsTypes.h [deleted file]
drivers/net/npe/include/IxOsalOsUtilitySymbols.h [deleted file]
drivers/net/npe/include/IxOsalTypes.h [deleted file]
drivers/net/npe/include/IxOsalUtilitySymbols.h [deleted file]
drivers/net/npe/include/IxParityENAcc.h [deleted file]
drivers/net/npe/include/IxPerfProfAcc.h [deleted file]
drivers/net/npe/include/IxQMgr.h [deleted file]
drivers/net/npe/include/IxQMgrAqmIf_p.h [deleted file]
drivers/net/npe/include/IxQMgrDefines_p.h [deleted file]
drivers/net/npe/include/IxQMgrDispatcher_p.h [deleted file]
drivers/net/npe/include/IxQMgrLog_p.h [deleted file]
drivers/net/npe/include/IxQMgrQAccess_p.h [deleted file]
drivers/net/npe/include/IxQMgrQCfg_p.h [deleted file]
drivers/net/npe/include/IxQueueAssignments.h [deleted file]
drivers/net/npe/include/IxSspAcc.h [deleted file]
drivers/net/npe/include/IxTimeSyncAcc.h [deleted file]
drivers/net/npe/include/IxTimerCtrl.h [deleted file]
drivers/net/npe/include/IxTypes.h [deleted file]
drivers/net/npe/include/IxUART.h [deleted file]
drivers/net/npe/include/IxVersionId.h [deleted file]
drivers/net/npe/include/ix_error.h [deleted file]
drivers/net/npe/include/ix_macros.h [deleted file]
drivers/net/npe/include/ix_os_type.h [deleted file]
drivers/net/npe/include/ix_ossl.h [deleted file]
drivers/net/npe/include/ix_symbols.h [deleted file]
drivers/net/npe/include/ix_types.h [deleted file]
drivers/net/npe/include/npe.h [deleted file]
drivers/net/npe/include/os_datatypes.h [deleted file]
drivers/net/npe/miiphy.c [deleted file]
drivers/net/npe/npe.c [deleted file]
drivers/net/xilinx_axi_emac.c
drivers/net/zynq_gem.c
drivers/pci/Makefile
drivers/pci/fsl_pci_init.c
drivers/pci/pci_ixp.c [deleted file]
drivers/power/battery/bat_trats2.c
drivers/serial/Makefile
drivers/serial/opencores_yanu.c
drivers/serial/serial.c
drivers/serial/serial_arc.c [new file with mode: 0644]
drivers/serial/serial_ixp.c [deleted file]
drivers/serial/serial_s5p.c
drivers/serial/serial_xuartlite.c
drivers/serial/serial_zynq.c
drivers/serial/usbtty.h
drivers/usb/gadget/Makefile
drivers/usb/gadget/ci_udc.c [moved from drivers/usb/gadget/mv_udc.c with 79% similarity]
drivers/usb/gadget/ci_udc.h [moved from drivers/usb/gadget/mv_udc.h with 94% similarity]
drivers/usb/gadget/f_mass_storage.c
drivers/usb/gadget/f_thor.c
drivers/usb/gadget/gadget_chips.h
drivers/usb/gadget/s3c_udc_otg.c
drivers/usb/gadget/s3c_udc_otg_xfer_dma.c
drivers/usb/host/Makefile
drivers/usb/host/ehci-ixp4xx.c [deleted file]
drivers/video/exynos_fb.c
drivers/video/exynos_fimd.c
examples/standalone/stubs.c
include/clk.h [new file with mode: 0644]
include/common.h
include/config_cmd_all.h
include/config_distro_defaults.h [new file with mode: 0644]
include/configs/T1040QDS.h
include/configs/T1040RDB.h
include/configs/T1042RDB_PI.h
include/configs/actux1.h [deleted file]
include/configs/actux2.h [deleted file]
include/configs/actux3.h [deleted file]
include/configs/actux4.h [deleted file]
include/configs/arcangel4-be.h [new file with mode: 0644]
include/configs/arcangel4.h [new file with mode: 0644]
include/configs/axs101.h [new file with mode: 0644]
include/configs/bf609-ezkit.h
include/configs/cardhu.h
include/configs/dra7xx_evm.h
include/configs/dvlhost.h [deleted file]
include/configs/km/keymile-common.h
include/configs/km/km-powerpc.h
include/configs/km/km_arm.h
include/configs/km/kmp204x-common.h
include/configs/km_kirkwood.h
include/configs/kmp204x.h
include/configs/microblaze-generic.h
include/configs/nitrogen6x.h
include/configs/omap5_uevm.h
include/configs/rpi_b.h
include/configs/s5p_goni.h
include/configs/s5pc210_universal.h
include/configs/sansa_fuze_plus.h
include/configs/spear-common.h
include/configs/spear6xx_evb.h
include/configs/tegra-common-post.h
include/configs/tegra124-common.h [new file with mode: 0644]
include/configs/trats.h
include/configs/trats2.h
include/configs/venice2.h [new file with mode: 0644]
include/configs/x600.h
include/configs/xfi3.h
include/configs/zynq-common.h
include/configs/zynq_zc70x.h
include/configs/zynq_zed.h
include/dwmmc.h
include/fdtdec.h
include/fsl_ifc.h
include/image.h
include/lcd.h
include/mmc.h
include/netdev.h
include/power/max77686_pmic.h
include/power/pmic.h
include/samsung/misc.h [new file with mode: 0644]
include/spl.h
include/usb/ci_udc.h [moved from include/usb/mv_udc.h with 73% similarity]
include/usb/s3c_udc.h
include/zynqpl.h
lib/fdtdec.c
lib/tizen/tizen.c
lib/tizen/tizen_hd_logo.h [deleted file]
lib/tizen/tizen_hd_logo_data.h [deleted file]
lib/tizen/tizen_logo_16bpp.h [new file with mode: 0644]
lib/tizen/tizen_logo_16bpp_gzip.h [new file with mode: 0644]
net/eth.c
tools/relocate-rela.c

diff --git a/MAKEALL b/MAKEALL
index 562071a..8fedea2 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -398,8 +398,6 @@ LIST_at91="$(targets_by_soc at91)"
 
 LIST_pxa="$(targets_by_cpu pxa)"
 
-LIST_ixp="$(targets_by_cpu ixp)"
-
 #########################################################################
 ## SPEAr Systems
 #########################################################################
@@ -529,6 +527,12 @@ LIST_sparc="$(targets_by_arch sparc)"
 
 LIST_nds32="$(targets_by_arch nds32)"
 
+#########################################################################
+## ARC Systems
+#########################################################################
+
+LIST_arc="$(targets_by_arch arc)"
+
 #-----------------------------------------------------------------------
 
 get_target_location() {
index 1687e2e..0e07aa5 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -227,7 +227,6 @@ LIBS-y += $(CPUDIR)/
 ifdef SOC
 LIBS-y += $(CPUDIR)/$(SOC)/
 endif
-LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/
 LIBS-$(CONFIG_OF_EMBED) += dts/
 LIBS-y += arch/$(ARCH)/lib/
 LIBS-y += fs/
diff --git a/README b/README
index 176de61..4376f28 100644 (file)
--- a/README
+++ b/README
@@ -141,7 +141,6 @@ Directory Hierarchy:
        /s3c24x0        Files specific to Samsung S3C24X0 CPUs
       /arm926ejs       Files specific to ARM 926 CPUs
       /arm1136         Files specific to ARM 1136 CPUs
-      /ixp             Files specific to Intel XScale IXP CPUs
       /pxa             Files specific to Intel XScale PXA CPUs
       /sa1100          Files specific to Intel StrongARM SA1100 CPUs
     /lib               Architecture specific library files
@@ -472,6 +471,12 @@ The following options need to be configured:
                Board config to use DDR3. It can be enabled for SoCs with
                Freescale DDR3 controllers.
 
+               CONFIG_SYS_FSL_IFC_BE
+               Defines the IFC controller register space as Big Endian
+
+               CONFIG_SYS_FSL_IFC_LE
+               Defines the IFC controller register space as Little Endian
+
                CONFIG_SYS_FSL_PBL_PBI
                It enables addition of RCW (Power on reset configuration) in built image.
                Please refer doc/README.pblimage for more details
@@ -896,6 +901,7 @@ The following options need to be configured:
                CONFIG_CMD_BSP          * Board specific commands
                CONFIG_CMD_BOOTD          bootd
                CONFIG_CMD_CACHE        * icache, dcache
+               CONFIG_CMD_CLK          * clock command support
                CONFIG_CMD_CONSOLE        coninfo
                CONFIG_CMD_CRC32        * crc32
                CONFIG_CMD_DATE         * support for RTC, date/time...
diff --git a/arch/arc/config.mk b/arch/arc/config.mk
new file mode 100644 (file)
index 0000000..76f4f7c
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+ifndef CONFIG_SYS_BIG_ENDIAN
+CONFIG_SYS_LITTLE_ENDIAN = 1
+endif
+
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+CROSS_COMPILE ?= arc-buildroot-linux-uclibc-
+endif
+
+ifdef CONFIG_SYS_BIG_ENDIAN
+CROSS_COMPILE ?= arceb-buildroot-linux-uclibc-
+PLATFORM_LDFLAGS += -EB
+endif
+
+PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -DCONFIG_ARC -gdwarf-2
+
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+# Needed for relocation
+LDFLAGS_FINAL += -pie
+
+# Load address for standalone apps
+CONFIG_STANDALONE_LOAD_ADDR ?= 0x82000000
+
+# Support generic board on ARC
+__HAVE_ARCH_GENERIC_BOARD := y
diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile
new file mode 100644 (file)
index 0000000..cdc5002
--- /dev/null
@@ -0,0 +1,13 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+extra-y        += start.o
+
+obj-y  += cache.o
+obj-y  += cpu.o
+obj-y  += interrupts.o
+obj-y  += reset.o
+obj-y  += timer.o
diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c
new file mode 100644 (file)
index 0000000..39d522d
--- /dev/null
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/arcregs.h>
+
+/* Bit values in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE  (1 << 0)
+
+/* Bit values in DC_CTRL */
+#define DC_CTRL_CACHE_DISABLE  (1 << 0)
+#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
+#define DC_CTRL_FLUSH_STATUS   (1 << 8)
+
+int icache_status(void)
+{
+       return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
+              IC_CTRL_CACHE_DISABLE;
+}
+
+void icache_enable(void)
+{
+       write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
+                     ~IC_CTRL_CACHE_DISABLE);
+}
+
+void icache_disable(void)
+{
+       write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
+                     IC_CTRL_CACHE_DISABLE);
+}
+
+void invalidate_icache_all(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+       /* Any write to IC_IVIC register triggers invalidation of entire I$ */
+       write_aux_reg(ARC_AUX_IC_IVIC, 1);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+
+int dcache_status(void)
+{
+       return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
+               DC_CTRL_CACHE_DISABLE;
+}
+
+void dcache_enable(void)
+{
+       write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
+                     ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
+}
+
+void dcache_disable(void)
+{
+       write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
+                     DC_CTRL_CACHE_DISABLE);
+}
+
+void flush_dcache_all(void)
+{
+       /* Do flush of entire cache */
+       write_aux_reg(ARC_AUX_DC_FLSH, 1);
+
+       /* Wait flush end */
+       while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+               ;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+static void dcache_flush_line(unsigned addr)
+{
+#if (CONFIG_ARC_MMU_VER > 2)
+       write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+       write_aux_reg(ARC_AUX_DC_FLDL, addr);
+
+       /* Wait flush end */
+       while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
+               ;
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+       /*
+        * Invalidate I$ for addresses range just flushed from D$.
+        * If we try to execute data flushed above it will be valid/correct
+        */
+#if (CONFIG_ARC_MMU_VER > 2)
+       write_aux_reg(ARC_AUX_IC_PTAG, addr);
+#endif
+       write_aux_reg(ARC_AUX_IC_IVIL, addr);
+#endif /* CONFIG_SYS_ICACHE_OFF */
+}
+#endif /* CONFIG_SYS_DCACHE_OFF */
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+       unsigned int addr;
+
+       start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+       end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+       for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
+               dcache_flush_line(addr);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+       unsigned int addr;
+
+       start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+       end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
+
+       for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
+#if (CONFIG_ARC_MMU_VER > 2)
+               write_aux_reg(ARC_AUX_DC_PTAG, addr);
+#endif
+               write_aux_reg(ARC_AUX_DC_IVDL, addr);
+       }
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void invalidate_dcache_all(void)
+{
+#ifndef CONFIG_SYS_DCACHE_OFF
+       /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
+       write_aux_reg(ARC_AUX_DC_IVDC, 1);
+#endif /* CONFIG_SYS_DCACHE_OFF */
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+       flush_dcache_range(start, start + size);
+}
diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arc700/config.mk
new file mode 100644 (file)
index 0000000..3206ff4
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mA7
diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/cpu/arc700/cpu.c
new file mode 100644 (file)
index 0000000..50634b8
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_SYS_ICACHE_OFF
+       icache_disable();
+#else
+       icache_enable();
+       invalidate_icache_all();
+#endif
+
+       flush_dcache_all();
+#ifdef CONFIG_SYS_DCACHE_OFF
+       dcache_disable();
+#else
+       dcache_enable();
+#endif
+       timer_init();
+
+/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
+       if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
+               gd->arch.running_on_hw = 0;
+       else
+               gd->arch.running_on_hw = 1;
+
+       gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
+       gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+       return 0;
+}
+
+int arch_early_init_r(void)
+{
+       gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+       return 0;
+}
diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c
new file mode 100644 (file)
index 0000000..d93a6eb
--- /dev/null
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arcregs.h>
+#include <asm/ptrace.h>
+
+/* Bit values in STATUS32 */
+#define E1_MASK                (1 << 1)        /* Level 1 interrupts enable */
+#define E2_MASK                (1 << 2)        /* Level 2 interrupts enable */
+
+int interrupt_init(void)
+{
+       return 0;
+}
+
+/*
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts(void)
+{
+       int status = read_aux_reg(ARC_AUX_STATUS32);
+       int state = (status | E1_MASK | E2_MASK) ? 1 : 0;
+
+       status &= ~(E1_MASK | E2_MASK);
+       /* STATUS32 register is updated indirectly with "FLAG" instruction */
+       __asm__("flag %0" : : "r" (status));
+       return state;
+}
+
+void enable_interrupts(void)
+{
+       unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
+
+       status |= E1_MASK | E2_MASK;
+       /* STATUS32 register is updated indirectly with "FLAG" instruction */
+       __asm__("flag %0" : : "r" (status));
+}
+
+static void print_reg_file(long *reg_rev, int start_num)
+{
+       unsigned int i;
+
+       /* Print 3 registers per line */
+       for (i = start_num; i < start_num + 25; i++) {
+               printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
+               if (((i + 1) % 3) == 0)
+                       printf("\n");
+
+               /* Because pt_regs has registers reversed */
+               reg_rev--;
+       }
+
+       /* Add new-line if none was inserted in the end of loop above */
+       if (((i + 1) % 3) != 0)
+               printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+       printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
+              regs->ret, regs->blink, regs->status32);
+       printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
+       printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
+              regs->sp, regs->fp);
+       printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
+              regs->lp_end, regs->lp_count);
+
+       print_reg_file(&(regs->r0), 0);
+}
+
+void bad_mode(struct pt_regs *regs)
+{
+       if (regs)
+               show_regs(regs);
+
+       panic("Resetting CPU ...\n");
+}
+
+void do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+       printf("Memory error exception @ 0x%lx\n", address);
+       bad_mode(regs);
+}
+
+void do_instruction_error(unsigned long address, struct pt_regs *regs)
+{
+       printf("Instruction error exception @ 0x%lx\n", address);
+       bad_mode(regs);
+}
+
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
+{
+       printf("Machine check exception @ 0x%lx\n", address);
+       bad_mode(regs);
+}
+
+void do_interrupt_handler(void)
+{
+       printf("Interrupt fired\n");
+       bad_mode(0);
+}
+
+void do_itlb_miss(struct pt_regs *regs)
+{
+       printf("I TLB miss exception\n");
+       bad_mode(regs);
+}
+
+void do_dtlb_miss(struct pt_regs *regs)
+{
+       printf("D TLB miss exception\n");
+       bad_mode(regs);
+}
+
+void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
+{
+       printf("TLB protection violation or misaligned access @ 0x%lx\n",
+              address);
+       bad_mode(regs);
+}
+
+void do_privilege_violation(struct pt_regs *regs)
+{
+       printf("Privilege violation exception\n");
+       bad_mode(regs);
+}
+
+void do_trap(struct pt_regs *regs)
+{
+       printf("Trap exception\n");
+       bad_mode(regs);
+}
+
+void do_extension(struct pt_regs *regs)
+{
+       printf("Extension instruction exception\n");
+       bad_mode(regs);
+}
diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/cpu/arc700/reset.c
new file mode 100644 (file)
index 0000000..98ebf1d
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <command.h>
+#include <common.h>
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+       printf("Put your restart handler here\n");
+
+#ifdef DEBUG
+       /* Stop debug session here */
+       __asm__("brk");
+#endif
+       return 0;
+}
diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S
new file mode 100644 (file)
index 0000000..563513b
--- /dev/null
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/arcregs.h>
+
+/*
+ * Note on the LD/ST addressing modes with address register write-back
+ *
+ * LD.a same as LD.aw
+ *
+ * LD.a    reg1, [reg2, x]  => Pre Incr
+ *      Eff Addr for load = [reg2 + x]
+ *
+ * LD.ab   reg1, [reg2, x]  => Post Incr
+ *      Eff Addr for load = [reg2]
+ */
+
+.macro PUSH reg
+       st.a    \reg, [%sp, -4]
+.endm
+
+.macro PUSHAX aux
+       lr      %r9, [\aux]
+       PUSH    %r9
+.endm
+
+.macro  SAVE_R1_TO_R24
+       PUSH    %r1
+       PUSH    %r2
+       PUSH    %r3
+       PUSH    %r4
+       PUSH    %r5
+       PUSH    %r6
+       PUSH    %r7
+       PUSH    %r8
+       PUSH    %r9
+       PUSH    %r10
+       PUSH    %r11
+       PUSH    %r12
+       PUSH    %r13
+       PUSH    %r14
+       PUSH    %r15
+       PUSH    %r16
+       PUSH    %r17
+       PUSH    %r18
+       PUSH    %r19
+       PUSH    %r20
+       PUSH    %r21
+       PUSH    %r22
+       PUSH    %r23
+       PUSH    %r24
+.endm
+
+.macro SAVE_ALL_SYS
+
+       st      %r0, [%sp]
+       lr      %r0, [%ecr]
+       st      %r0, [%sp, 8]   /* ECR */
+       st      %sp, [%sp, 4]
+
+       SAVE_R1_TO_R24
+       PUSH    %r25
+       PUSH    %gp
+       PUSH    %fp
+       PUSH    %blink
+       PUSHAX  %eret
+       PUSHAX  %erstatus
+       PUSH    %lp_count
+       PUSHAX  %lp_end
+       PUSHAX  %lp_start
+       PUSHAX  %erbta
+.endm
+
+.align 4
+.globl _start
+_start:
+       /* Critical system events */
+       j       reset                   /* 0 - 0x000 */
+       j       memory_error            /* 1 - 0x008 */
+       j       instruction_error       /* 2 - 0x010 */
+
+       /* Device interrupts */
+.rept  29
+       j       interrupt_handler       /* 3:31 - 0x018:0xF8 */
+.endr
+       /* Exceptions */
+       j       EV_MachineCheck         /* 0x100, Fatal Machine check  (0x20) */
+       j       EV_TLBMissI             /* 0x108, Intruction TLB miss  (0x21) */
+       j       EV_TLBMissD             /* 0x110, Data TLB miss        (0x22) */
+       j       EV_TLBProtV             /* 0x118, Protection Violation (0x23)
+                                                       or Misaligned Access  */
+       j       EV_PrivilegeV           /* 0x120, Privilege Violation  (0x24) */
+       j       EV_Trap                 /* 0x128, Trap exception       (0x25) */
+       j       EV_Extension            /* 0x130, Extn Intruction Excp (0x26) */
+
+memory_error:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_memory_error
+
+instruction_error:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_instruction_error
+
+interrupt_handler:
+       /* Todo - save and restore CPU context when interrupts will be in use */
+       bl      do_interrupt_handler
+       rtie
+
+EV_MachineCheck:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_machine_check_fault
+
+EV_TLBMissI:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_itlb_miss
+
+EV_TLBMissD:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_dtlb_miss
+
+EV_TLBProtV:
+       SAVE_ALL_SYS
+       lr      %r0, [%efa]
+       mov     %r1, %sp
+       j       do_tlb_prot_violation
+
+EV_PrivilegeV:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_privilege_violation
+
+EV_Trap:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_trap
+
+EV_Extension:
+       SAVE_ALL_SYS
+       mov     %r0, %sp
+       j       do_extension
+
+
+reset:
+       /* Setup interrupt vector base that matches "__text_start" */
+       sr      __text_start, [ARC_AUX_INTR_VEC_BASE]
+
+       /* Setup stack pointer */
+       mov     %sp, CONFIG_SYS_INIT_SP_ADDR
+       mov     %fp, %sp
+
+       /* Clear bss */
+       mov     %r0, __bss_start
+       mov     %r1, __bss_end
+
+clear_bss:
+       st.ab   0, [%r0, 4]
+       brlt    %r0, %r1, clear_bss
+
+       /* Zero the one and only argument of "board_init_f" */
+       mov_s   %r0, 0
+       j       board_init_f
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r0 = start_addr_sp
+ * r1 = new__gd
+ * r2 = relocaddr
+ */
+.align 4
+.globl relocate_code
+relocate_code:
+       /*
+        * r0-r12 might be clobbered by C functions
+        * so we use r13-r16 for storage here
+        */
+       mov     %r13, %r0               /* save addr_sp */
+       mov     %r14, %r1               /* save addr of gd */
+       mov     %r15, %r2               /* save addr of destination */
+
+       mov     %r16, %r2               /* %r9 - relocation offset */
+       sub     %r16, %r16, __image_copy_start
+
+/* Set up the stack */
+stack_setup:
+       mov     %sp, %r13
+       mov     %fp, %sp
+
+/* Check if monitor is loaded right in place for relocation */
+       mov     %r0, __image_copy_start
+       cmp     %r0, %r15               /* skip relocation if code loaded */
+       bz      do_board_init_r         /* in target location already */
+
+/* Copy data (__image_copy_start - __image_copy_end) to new location */
+       mov     %r1, %r15
+       mov     %r2, __image_copy_end
+       sub     %r2, %r2, %r0           /* r3 <- amount of bytes to copy */
+       asr     %r2, %r2, 2             /* r3 <- amount of words to copy */
+       mov     %lp_count, %r2
+       lp      copy_end
+       ld.ab   %r2,[%r0,4]
+       st.ab   %r2,[%r1,4]
+copy_end:
+
+/* Fix relocations related issues */
+       bl      do_elf_reloc_fixups
+#ifndef CONFIG_SYS_ICACHE_OFF
+       bl      invalidate_icache_all
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+       bl      flush_dcache_all
+#endif
+
+/* Update position of intterupt vector table */
+       lr      %r0, [ARC_AUX_INTR_VEC_BASE]    /* Read current position */
+       add     %r0, %r0, %r16                  /* Update address */
+       sr      %r0, [ARC_AUX_INTR_VEC_BASE]    /* Write new position */
+
+do_board_init_r:
+/* Prepare for exection of "board_init_r" in relocated monitor */
+       mov     %r2, board_init_r       /* old address of "board_init_r()" */
+       add     %r2, %r2, %r16          /* new address of "board_init_r()" */
+       mov     %r0, %r14               /* 1-st parameter: gd_t */
+       mov     %r1, %r15               /* 2-nd parameter: dest_addr */
+       j       [%r2]
diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/cpu/arc700/timer.c
new file mode 100644 (file)
index 0000000..a0acbbc
--- /dev/null
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/arcregs.h>
+
+#define NH_MODE        (1 << 1)        /* Disable timer if CPU is halted */
+
+int timer_init(void)
+{
+       write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
+       /* Set max value for counter/timer */
+       write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
+       /* Set initial count value and restart counter/timer */
+       write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
+       return 0;
+}
+
+unsigned long timer_read_counter(void)
+{
+       return read_aux_reg(ARC_AUX_TIMER0_CNT);
+}
diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds
new file mode 100644 (file)
index 0000000..2d01b21
--- /dev/null
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc")
+OUTPUT_ARCH(arc)
+ENTRY(_start)
+SECTIONS
+{
+       . = ALIGN(4);
+       .text : {
+               *(.__text_start)
+               *(.__image_copy_start)
+               CPUDIR/start.o (.text*)
+               *(.text*)
+       }
+
+       . = ALIGN(4);
+       .text_end :
+       {
+               *(.__text_end)
+       }
+
+       . = ALIGN(4);
+       .rodata : {
+               *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+       }
+
+       . = ALIGN(4);
+       .data : {
+               *(.data*)
+       }
+
+       . = ALIGN(4);
+       .u_boot_list : {
+               KEEP(*(SORT(.u_boot_list*)));
+       }
+
+       . = ALIGN(4);
+       .rel_dyn_start : {
+               *(.__rel_dyn_start)
+       }
+
+       .rela.dyn : {
+               *(.rela.dyn)
+       }
+
+       .rel_dyn_end : {
+               *(.__rel_dyn_end)
+       }
+
+       . = ALIGN(4);
+       .bss_start : {
+               *(.__bss_start);
+       }
+
+       .bss : {
+               *(.bss*)
+       }
+
+       .bss_end : {
+               *(.__bss_end);
+       }
+
+       . = ALIGN(4);
+       .image_copy_end : {
+               *(.__image_copy_end)
+               *(.__init_end)
+       }
+}
diff --git a/arch/arc/include/asm/arch-arc700/hardware.h b/arch/arc/include/asm/arch-arc700/hardware.h
new file mode 100644 (file)
index 0000000..8ec13a8
--- /dev/null
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * This file is only required to allow compilation of "designware_i2c" driver.
+ * Which explicitly includes <asm/arch/hardware.h>.
+ */
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
new file mode 100644 (file)
index 0000000..5d48d11
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARC_ARCREGS_H
+#define _ASM_ARC_ARCREGS_H
+
+/*
+ * ARC architecture has additional address space - auxiliary registers.
+ * These registers are mostly used for configuration purposes.
+ * These registers are not memory mapped and special commands are used for
+ * access: "lr"/"sr".
+ */
+
+#define ARC_AUX_IDENTITY       0x04
+#define ARC_AUX_STATUS32       0x0a
+
+/* Instruction cache related auxiliary registers */
+#define ARC_AUX_IC_IVIC                0x10
+#define ARC_AUX_IC_CTRL                0x11
+#define ARC_AUX_IC_IVIL                0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_IC_PTAG                0x1E
+#endif
+
+/* Timer related auxiliary registers */
+#define ARC_AUX_TIMER0_CNT     0x21    /* Timer 0 count */
+#define ARC_AUX_TIMER0_CTRL    0x22    /* Timer 0 control */
+#define ARC_AUX_TIMER0_LIMIT   0x23    /* Timer 0 limit */
+
+#define ARC_AUX_INTR_VEC_BASE  0x25
+
+/* Data cache related auxiliary registers */
+#define ARC_AUX_DC_IVDC                0x47
+#define ARC_AUX_DC_CTRL                0x48
+
+#define ARC_AUX_DC_IVDL                0x4A
+#define ARC_AUX_DC_FLSH                0x4B
+#define ARC_AUX_DC_FLDL                0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_AUX_DC_PTAG                0x5C
+#endif
+
+#ifndef __ASSEMBLY__
+/* Accessors for auxiliary registers */
+#define read_aux_reg(reg)      __builtin_arc_lr(reg)
+
+/* gcc builtin sr needs reg param to be long immediate */
+#define write_aux_reg(reg_immed, val)          \
+               __builtin_arc_sr((unsigned int)val, reg_immed)
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARC_ARCREGS_H */
diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
new file mode 100644 (file)
index 0000000..85721aa
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BITOPS_H
+#define __ASM_ARC_BITOPS_H
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+#endif /* __ASM_ARC_BITOPS_H */
diff --git a/arch/arc/include/asm/byteorder.h b/arch/arc/include/asm/byteorder.h
new file mode 100644 (file)
index 0000000..2fa9776
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_BYTEORDER_H
+#define __ASM_ARC_BYTEORDER_H
+
+#include <asm/types.h>
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+       #define __BYTEORDER_HAS_U64__
+       #define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __LITTLE_ENDIAN__
+       #include <linux/byteorder/little_endian.h>
+#else
+       #include <linux/byteorder/big_endian.h>
+#endif /* CONFIG_SYS_BIG_ENDIAN */
+
+#endif /* ASM_ARC_BYTEORDER_H */
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
new file mode 100644 (file)
index 0000000..16e7568
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CACHE_H
+#define __ASM_ARC_CACHE_H
+
+#include <config.h>
+
+/*
+ * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN      128
+#endif
+
+#endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/include/asm/config.h b/arch/arc/include/asm/config.h
new file mode 100644 (file)
index 0000000..5761def
--- /dev/null
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_CONFIG_H_
+#define __ASM_ARC_CONFIG_H_
+
+#define CONFIG_LMB
+
+#endif /*__ASM_ARC_CONFIG_H_ */
diff --git a/arch/arc/include/asm/errno.h b/arch/arc/include/asm/errno.h
new file mode 100644 (file)
index 0000000..4c82b50
--- /dev/null
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h
new file mode 100644 (file)
index 0000000..d644e80
--- /dev/null
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef        __ASM_ARC_GLOBAL_DATA_H
+#define __ASM_ARC_GLOBAL_DATA_H
+
+/* Architecture-specific global data */
+struct arch_global_data {
+       int running_on_hw;
+};
+
+#include <asm-generic/global_data.h>
+
+#define DECLARE_GLOBAL_DATA_PTR                register volatile gd_t *gd asm ("r25")
+
+#endif /* __ASM_ARC_GLOBAL_DATA_H */
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
new file mode 100644 (file)
index 0000000..24b7337
--- /dev/null
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_IO_H
+#define __ASM_ARC_IO_H
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+static inline void sync(void)
+{
+       /* Not yet implemented */
+}
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+       u8 b;
+
+       __asm__ __volatile__("ldb%U1    %0, %1\n"
+                            : "=r" (b)
+                            : "m" (*(volatile u8 __force *)addr)
+                            : "memory");
+       return b;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+       u16 s;
+
+       __asm__ __volatile__("ldw%U1    %0, %1\n"
+                            : "=r" (s)
+                            : "m" (*(volatile u16 __force *)addr)
+                            : "memory");
+       return s;
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+       u32 w;
+
+       __asm__ __volatile__("ld%U1     %0, %1\n"
+                            : "=r" (w)
+                            : "m" (*(volatile u32 __force *)addr)
+                            : "memory");
+       return w;
+}
+
+#define readb __raw_readb
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+       return __le16_to_cpu(__raw_readw(addr));
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+       return __le32_to_cpu(__raw_readl(addr));
+}
+
+static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
+{
+       __asm__ __volatile__("stb%U1    %0, %1\n"
+                            :
+                            : "r" (b), "m" (*(volatile u8 __force *)addr)
+                            : "memory");
+}
+
+static inline void __raw_writew(u16 s, volatile void __iomem *addr)
+{
+       __asm__ __volatile__("stw%U1    %0, %1\n"
+                            :
+                            : "r" (s), "m" (*(volatile u16 __force *)addr)
+                            : "memory");
+}
+
+static inline void __raw_writel(u32 w, volatile void __iomem *addr)
+{
+       __asm__ __volatile__("st%U1     %0, %1\n"
+                            :
+                            : "r" (w), "m" (*(volatile u32 __force *)addr)
+                            : "memory");
+}
+
+#define writeb __raw_writeb
+#define writew(b, addr) __raw_writew(__cpu_to_le16(b), addr)
+#define writel(b, addr) __raw_writel(__cpu_to_le32(b), addr)
+
+static inline int __raw_readsb(unsigned int addr, void *data, int bytelen)
+{
+       __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "stb.ab   r8, [r1, 1]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (bytelen)
+                             : "r8");
+       return bytelen;
+}
+
+static inline int __raw_readsw(unsigned int addr, void *data, int wordlen)
+{
+       __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "stw.ab   r8, [r1, 2]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (wordlen)
+                             : "r8");
+       return wordlen;
+}
+
+static inline int __raw_readsl(unsigned int addr, void *data, int longlen)
+{
+       __asm__ __volatile__ ("1:ld.di  r8, [r0]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.ab    r8, [r1, 4]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (longlen)
+                             : "r8");
+       return longlen;
+}
+
+static inline int __raw_writesb(unsigned int addr, void *data, int bytelen)
+{
+       __asm__ __volatile__ ("1:ldb.ab r8, [r1, 1]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.di    r8, [r0, 0]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (bytelen)
+                             : "r8");
+       return bytelen;
+}
+
+static inline int __raw_writesw(unsigned int addr, void *data, int wordlen)
+{
+       __asm__ __volatile__ ("1:ldw.ab r8, [r1, 2]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.ab.di r8, [r0, 0]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (wordlen)
+                             : "r8");
+       return wordlen;
+}
+
+static inline int __raw_writesl(unsigned int addr, void *data, int longlen)
+{
+       __asm__ __volatile__ ("1:ld.ab  r8, [r1, 4]\n"
+                             "sub.f    r2, r2, 1\n"
+                             "bnz.d    1b\n"
+                             "st.ab.di r8, [r0, 0]\n"
+                             :
+                             : "r" (addr), "r" (data), "r" (longlen)
+                             : "r8");
+       return longlen;
+}
+
+#define out_arch(type, endian, a, v)   __raw_write##type(cpu_to_##endian(v), a)
+#define in_arch(type, endian, a)       endian##_to_cpu(__raw_read##type(a))
+
+#define out_le32(a, v) out_arch(l, le32, a, v)
+#define out_le16(a, v) out_arch(w, le16, a, v)
+
+#define in_le32(a)     in_arch(l, le32, a)
+#define in_le16(a)     in_arch(w, le16, a)
+
+#define out_be32(a, v) out_arch(l, be32, a, v)
+#define out_be16(a, v) out_arch(w, be16, a, v)
+
+#define in_be32(a)     in_arch(l, be32, a)
+#define in_be16(a)     in_arch(w, be16, a)
+
+#define out_8(a, v)    __raw_writeb(v, a)
+#define in_8(a)                __raw_readb(a)
+
+/*
+ * Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+       out_##type((addr), in_##type(addr) & ~(clear))
+
+#define setbits(type, addr, set) \
+       out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+       out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
+#endif /* __ASM_ARC_IO_H */
diff --git a/arch/arc/include/asm/posix_types.h b/arch/arc/include/asm/posix_types.h
new file mode 100644 (file)
index 0000000..20415f0
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_POSIX_TYPES_H
+#define __ASM_ARC_POSIX_TYPES_H
+
+typedef unsigned short         __kernel_dev_t;
+typedef unsigned long          __kernel_ino_t;
+typedef unsigned short         __kernel_mode_t;
+typedef unsigned short         __kernel_nlink_t;
+typedef long                   __kernel_off_t;
+typedef int                    __kernel_pid_t;
+typedef unsigned short         __kernel_ipc_pid_t;
+typedef unsigned short         __kernel_uid_t;
+typedef unsigned short         __kernel_gid_t;
+typedef unsigned int           __kernel_size_t;
+typedef int                    __kernel_ssize_t;
+typedef int                    __kernel_ptrdiff_t;
+typedef long                   __kernel_time_t;
+typedef long                   __kernel_suseconds_t;
+typedef long                   __kernel_clock_t;
+typedef int                    __kernel_daddr_t;
+typedef char                   *__kernel_caddr_t;
+typedef unsigned short         __kernel_uid16_t;
+typedef unsigned short         __kernel_gid16_t;
+typedef unsigned int           __kernel_uid32_t;
+typedef unsigned int           __kernel_gid32_t;
+
+typedef unsigned short         __kernel_old_uid_t;
+typedef unsigned short         __kernel_old_gid_t;
+
+#ifdef __GNUC__
+typedef long long              __kernel_loff_t;
+#endif
+
+#endif /* __ASM_ARC_POSIX_TYPES_H */
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
new file mode 100644 (file)
index 0000000..8f73b31
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_PTRACE_H
+#define __ASM_ARC_PTRACE_H
+
+struct pt_regs {
+       long bta;
+       long lp_start;
+       long lp_end;
+       long lp_count;
+       long status32;
+       long ret;
+       long blink;
+       long fp;
+       long r26;       /* gp */
+       long r25;
+       long r24;
+       long r23;
+       long r22;
+       long r21;
+       long r20;
+       long r19;
+       long r18;
+       long r17;
+       long r16;
+       long r15;
+       long r14;
+       long r13;
+       long r12;
+       long r11;
+       long r10;
+       long r9;
+       long r8;
+       long r7;
+       long r6;
+       long r5;
+       long r4;
+       long r3;
+       long r2;
+       long r1;
+       long r0;
+       long sp;
+       long ecr;
+};
+
+#endif /* __ASM_ARC_PTRACE_H */
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h
new file mode 100644 (file)
index 0000000..18484a1
--- /dev/null
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_SECTIONS_H
+#define __ASM_ARC_SECTIONS_H
+
+#include <asm-generic/sections.h>
+
+extern ulong __text_end;
+
+#endif /* __ASM_ARC_SECTIONS_H */
diff --git a/arch/arc/include/asm/string.h b/arch/arc/include/asm/string.h
new file mode 100644 (file)
index 0000000..909129c
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_STRING_H
+#define __ASM_ARC_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMCMP
+#define __HAVE_ARCH_STRCHR
+#define __HAVE_ARCH_STRCPY
+#define __HAVE_ARCH_STRCMP
+#define __HAVE_ARCH_STRLEN
+
+extern void *memset(void *ptr, int, __kernel_size_t);
+extern void *memcpy(void *, const void *, __kernel_size_t);
+extern void memzero(void *ptr, __kernel_size_t n);
+extern int memcmp(const void *, const void *, __kernel_size_t);
+extern char *strchr(const char *s, int c);
+extern char *strcpy(char *dest, const char *src);
+extern int strcmp(const char *cs, const char *ct);
+extern __kernel_size_t strlen(const char *);
+
+#endif /* __ASM_ARC_STRING_H */
diff --git a/arch/arc/include/asm/types.h b/arch/arc/include/asm/types.h
new file mode 100644 (file)
index 0000000..24eeb76
--- /dev/null
@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_TYPES_H
+#define __ASM_ARC_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif /* __ASM_ARC_TYPES_H */
diff --git a/arch/arc/include/asm/u-boot-arc.h b/arch/arc/include/asm/u-boot-arc.h
new file mode 100644 (file)
index 0000000..0c0e8e6
--- /dev/null
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_ARC_H__
+#define __ASM_ARC_U_BOOT_ARC_H__
+
+int arch_early_init_r(void);
+
+#endif /* __ASM_ARC_U_BOOT_ARC_H__ */
diff --git a/arch/arc/include/asm/u-boot.h b/arch/arc/include/asm/u-boot.h
new file mode 100644 (file)
index 0000000..e354edf
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARC_U_BOOT_H__
+#define __ASM_ARC_U_BOOT_H__
+
+#include <asm-generic/u-boot.h>
+
+/* For image.h:image_check_target_arch() */
+#define IH_ARCH_DEFAULT IH_ARCH_ARC
+
+#endif /* __ASM_ARC_U_BOOT_H__ */
diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h
new file mode 100644 (file)
index 0000000..6cecbbb
--- /dev/null
@@ -0,0 +1 @@
+#include <asm-generic/unaligned.h>
diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile
new file mode 100644 (file)
index 0000000..7675f85
--- /dev/null
@@ -0,0 +1,16 @@
+#
+# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += sections.o
+obj-y += relocate.o
+obj-y += strchr-700.o
+obj-y += strcmp.o
+obj-y += strcpy-700.o
+obj-y += strlen.o
+obj-y += memcmp.o
+obj-y += memcpy-700.o
+obj-y += memset.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c
new file mode 100644 (file)
index 0000000..d185a50
--- /dev/null
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong get_sp(void)
+{
+       ulong ret;
+
+       asm("mov %0, sp" : "=r"(ret) : );
+       return ret;
+}
+
+void arch_lmb_reserve(struct lmb *lmb)
+{
+       ulong sp;
+
+       /*
+        * Booting a (Linux) kernel image
+        *
+        * Allocate space for command line and board info - the
+        * address should be as high as possible within the reach of
+        * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
+        * memory, which means far enough below the current stack
+        * pointer.
+        */
+       sp = get_sp();
+       debug("## Current stack ends at 0x%08lx ", sp);
+
+       /* adjust sp by 4K to be safe */
+       sp -= 4096;
+       lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + gd->ram_size - sp));
+}
+
+static int cleanup_before_linux(void)
+{
+       disable_interrupts();
+       flush_dcache_all();
+       invalidate_icache_all();
+
+       return 0;
+}
+
+/* Subcommand: PREP */
+static void boot_prep_linux(bootm_headers_t *images)
+{
+       if (image_setup_linux(images))
+               hang();
+}
+
+/* Subcommand: GO */
+static void boot_jump_linux(bootm_headers_t *images, int flag)
+{
+       void (*kernel_entry)(int zero, int arch, uint params);
+       unsigned int r0, r2;
+       int fake = (flag & BOOTM_STATE_OS_FAKE_GO);
+
+       kernel_entry = (void (*)(int, int, uint))images->ep;
+
+       debug("## Transferring control to Linux (at address %08lx)...\n",
+             (ulong) kernel_entry);
+       bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+       printf("\nStarting kernel ...%s\n\n", fake ?
+              "(fake run for tracing)" : "");
+       bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+
+       cleanup_before_linux();
+
+       if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
+               r0 = 2;
+               r2 = (unsigned int)images->ft_addr;
+       } else {
+               r0 = 1;
+               r2 = (unsigned int)getenv("bootargs");
+       }
+
+       if (!fake)
+               kernel_entry(r0, 0, r2);
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+       /* No need for those on ARC */
+       if ((flag & BOOTM_STATE_OS_BD_T) || (flag & BOOTM_STATE_OS_CMDLINE))
+               return -1;
+
+       if (flag & BOOTM_STATE_OS_PREP) {
+               boot_prep_linux(images);
+               return 0;
+       }
+
+       if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+               boot_jump_linux(images, flag);
+               return 0;
+       }
+
+       boot_prep_linux(images);
+       boot_jump_linux(images, flag);
+       return 0;
+}
diff --git a/arch/arc/lib/memcmp.S b/arch/arc/lib/memcmp.S
new file mode 100644 (file)
index 0000000..fa5aac5
--- /dev/null
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifdef __LITTLE_ENDIAN__
+#define WORD2 r2
+#define SHIFT r3
+#else /* __BIG_ENDIAN__ */
+#define WORD2 r3
+#define SHIFT r2
+#endif /* _ENDIAN__ */
+
+.global memcmp
+.align 4
+memcmp:
+       or      %r12, %r0, %r1
+       asl_s   %r12, %r12, 30
+       sub     %r3, %r2, 1
+       brls    %r2, %r12, .Lbytewise
+       ld      %r4, [%r0, 0]
+       ld      %r5, [%r1, 0]
+       lsr.f   %lp_count, %r3, 3
+       lpne    .Loop_end
+       ld_s    WORD2, [%r0, 4]
+       ld_s    %r12, [%r1, 4]
+       brne    %r4, %r5, .Leven
+       ld.a    %r4, [%r0, 8]
+       ld.a    %r5, [%r1, 8]
+       brne    WORD2, %r12, .Lodd
+.Loop_end:
+       asl_s   SHIFT, SHIFT, 3
+       bhs_s   .Last_cmp
+       brne    %r4, %r5, .Leven
+       ld      %r4, [%r0, 4]
+       ld      %r5, [%r1, 4]
+#ifdef __LITTLE_ENDIAN__
+       nop_s
+       /* one more load latency cycle */
+.Last_cmp:
+       xor     %r0, %r4, %r5
+       bset    %r0, %r0, SHIFT
+       sub_s   %r1, %r0, 1
+       bic_s   %r1, %r1, %r0
+       norm    %r1, %r1
+       b.d     .Leven_cmp
+       and     %r1, %r1, 24
+.Leven:
+       xor     %r0, %r4, %r5
+       sub_s   %r1, %r0, 1
+       bic_s   %r1, %r1, %r0
+       norm    %r1, %r1
+       /* slow track insn */
+       and     %r1, %r1, 24
+.Leven_cmp:
+       asl     %r2, %r4, %r1
+       asl     %r12, %r5, %r1
+       lsr_s   %r2, %r2, 1
+       lsr_s   %r12, %r12, 1
+       j_s.d   [%blink]
+       sub     %r0, %r2, %r12
+       .balign 4
+.Lodd:
+       xor     %r0, WORD2, %r12
+       sub_s   %r1, %r0, 1
+       bic_s   %r1, %r1, %r0
+       norm    %r1, %r1
+       /* slow track insn */
+       and     %r1, %r1, 24
+       asl_s   %r2, %r2, %r1
+       asl_s   %r12, %r12, %r1
+       lsr_s   %r2, %r2, 1
+       lsr_s   %r12, %r12, 1
+       j_s.d   [%blink]
+       sub     %r0, %r2, %r12
+#else /* __BIG_ENDIAN__ */
+.Last_cmp:
+       neg_s   SHIFT, SHIFT
+       lsr     %r4, %r4, SHIFT
+       lsr     %r5, %r5, SHIFT
+       /* slow track insn */
+.Leven:
+       sub.f   %r0, %r4, %r5
+       mov.ne  %r0, 1
+       j_s.d   [%blink]
+       bset.cs %r0, %r0, 31
+.Lodd:
+       cmp_s   WORD2, %r12
+
+       mov_s   %r0, 1
+       j_s.d   [%blink]
+       bset.cs %r0, %r0, 31
+#endif /* _ENDIAN__ */
+       .balign 4
+.Lbytewise:
+       breq    %r2, 0, .Lnil
+       ldb     %r4, [%r0, 0]
+       ldb     %r5, [%r1, 0]
+       lsr.f   %lp_count, %r3
+       lpne    .Lbyte_end
+       ldb_s   %r3, [%r0, 1]
+       ldb     %r12, [%r1, 1]
+       brne    %r4, %r5, .Lbyte_even
+       ldb.a   %r4, [%r0, 2]
+       ldb.a   %r5, [%r1, 2]
+       brne    %r3, %r12, .Lbyte_odd
+.Lbyte_end:
+       bcc     .Lbyte_even
+       brne    %r4, %r5, .Lbyte_even
+       ldb_s   %r3, [%r0, 1]
+       ldb_s   %r12, [%r1, 1]
+.Lbyte_odd:
+       j_s.d   [%blink]
+       sub     %r0, %r3, %r12
+.Lbyte_even:
+       j_s.d   [%blink]
+       sub     %r0, %r4, %r5
+.Lnil:
+       j_s.d   [%blink]
+       mov     %r0, 0
diff --git a/arch/arc/lib/memcpy-700.S b/arch/arc/lib/memcpy-700.S
new file mode 100644 (file)
index 0000000..51dd73a
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+.global memcpy
+.align 4
+memcpy:
+       or      %r3, %r0, %r1
+       asl_s   %r3, %r3, 30
+       mov_s   %r5, %r0
+       brls.d  %r2, %r3, .Lcopy_bytewise
+       sub.f   %r3, %r2, 1
+       ld_s    %r12, [%r1, 0]
+       asr.f   %lp_count, %r3, 3
+       bbit0.d %r3, 2, .Lnox4
+       bmsk_s  %r2, %r2, 1
+       st.ab   %r12, [%r5, 4]
+       ld.a    %r12, [%r1, 4]
+.Lnox4:
+       lppnz   .Lendloop
+       ld_s    %r3, [%r1, 4]
+       st.ab   %r12, [%r5, 4]
+       ld.a    %r12, [%r1, 8]
+       st.ab   %r3, [%r5, 4]
+.Lendloop:
+       breq    %r2, 0, .Last_store
+       ld      %r3, [%r5, 0]
+#ifdef __LITTLE_ENDIAN__
+       add3    %r2, -1, %r2
+       /* uses long immediate */
+       xor_s   %r12, %r12, %r3
+       bmsk    %r12, %r12, %r2
+       xor_s   %r12, %r12, %r3
+#else /* __BIG_ENDIAN__ */
+       sub3    %r2, 31, %r2
+       /* uses long immediate */
+       xor_s   %r3, %r3, %r12
+       bmsk    %r3, %r3, %r2
+       xor_s   %r12, %r12, %r3
+#endif /* _ENDIAN__ */
+.Last_store:
+       j_s.d   [%blink]
+       st      %r12, [%r5, 0]
+
+       .balign 4
+.Lcopy_bytewise:
+       jcs     [%blink]
+       ldb_s   %r12, [%r1, 0]
+       lsr.f   %lp_count, %r3
+       bhs_s   .Lnox1
+       stb.ab  %r12, [%r5, 1]
+       ldb.a   %r12, [%r1, 1]
+.Lnox1:
+       lppnz   .Lendbloop
+       ldb_s   %r3, [%r1, 1]
+       stb.ab  %r12, [%r5, 1]
+       ldb.a   %r12, [%r1, 2]
+       stb.ab  %r3, [%r5, 1]
+.Lendbloop:
+       j_s.d   [%blink]
+       stb     %r12, [%r5, 0]
diff --git a/arch/arc/lib/memset.S b/arch/arc/lib/memset.S
new file mode 100644 (file)
index 0000000..017e8af
--- /dev/null
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#define SMALL  7 /* Must be at least 6 to deal with alignment/loop issues.  */
+
+.global memset
+.align 4
+memset:
+       mov_s   %r4, %r0
+       or      %r12, %r0, %r2
+       bmsk.f  %r12, %r12, 1
+       extb_s  %r1, %r1
+       asl     %r3, %r1, 8
+       beq.d   .Laligned
+       or_s    %r1, %r1, %r3
+       brls    %r2, SMALL, .Ltiny
+       add     %r3, %r2, %r0
+       stb     %r1, [%r3, -1]
+       bclr_s  %r3, %r3, 0
+       stw     %r1, [%r3, -2]
+       bmsk.f  %r12, %r0, 1
+       add_s   %r2, %r2, %r12
+       sub.ne  %r2, %r2, 4
+       stb.ab  %r1, [%r4, 1]
+       and     %r4, %r4, -2
+       stw.ab  %r1, [%r4, 2]
+       and     %r4, %r4, -4
+
+       .balign 4
+.Laligned:
+       asl     %r3, %r1, 16
+       lsr.f   %lp_count, %r2, 2
+       or_s    %r1, %r1, %r3
+       lpne    .Loop_end
+       st.ab   %r1, [%r4, 4]
+.Loop_end:
+       j_s     [%blink]
+
+       .balign 4
+.Ltiny:
+       mov.f   %lp_count, %r2
+       lpne    .Ltiny_end
+       stb.ab  %r1, [%r4, 1]
+.Ltiny_end:
+       j_s     [%blink]
+
+/*
+ * memzero: @r0 = mem, @r1 = size_t
+ * memset:  @r0 = mem, @r1 = char, @r2 = size_t
+ */
+
+.global memzero
+.align 4
+memzero:
+       /* adjust bzero args to memset args */
+       mov     %r2, %r1
+       mov     %r1, 0
+       /* tail call so need to tinker with blink */
+       b       memset
diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c
new file mode 100644 (file)
index 0000000..956aa14
--- /dev/null
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <elf.h>
+#include <asm/sections.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Base functionality is taken from x86 version with added ARC-specifics
+ */
+int do_elf_reloc_fixups(void)
+{
+       Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start);
+       Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end);
+
+       Elf32_Addr *offset_ptr_rom, *last_offset = NULL;
+       Elf32_Addr *offset_ptr_ram;
+
+       do {
+               /* Get the location from the relocation entry */
+               offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
+
+               /* Check that the location of the relocation is in .text */
+               if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE &&
+                   offset_ptr_rom > last_offset) {
+                       unsigned int val;
+                       /* Switch to the in-RAM version */
+                       offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom +
+                                                       gd->reloc_off);
+
+                       /*
+                        * Use "memcpy" because target location might be
+                        * 16-bit aligned on ARC so we may need to read
+                        * byte-by-byte. On attempt to read entire word by
+                        * CPU throws an exception
+                        */
+                       memcpy(&val, offset_ptr_ram, sizeof(int));
+
+                       /* If location in ".text" section swap value */
+                       if ((unsigned int)offset_ptr_rom <
+                           (unsigned int)&__text_end)
+                               val = (val << 16) | (val >> 16);
+
+                       /* Check that the target points into .text */
+                       if (val >= CONFIG_SYS_TEXT_BASE && val <=
+                           (unsigned int)&__bss_end) {
+                               val += gd->reloc_off;
+                               /* If location in ".text" section swap value */
+                               if ((unsigned int)offset_ptr_rom <
+                                   (unsigned int)&__text_end)
+                                       val = (val << 16) | (val >> 16);
+                               memcpy(offset_ptr_ram, &val, sizeof(int));
+                       } else {
+                               debug("   %p: rom reloc %x, ram %p, value %x, limit %x\n",
+                                     re_src, re_src->r_offset, offset_ptr_ram,
+                                     val, (unsigned int)&__bss_end);
+                       }
+               } else {
+                       debug("   %p: rom reloc %x, last %p\n", re_src,
+                             re_src->r_offset, last_offset);
+               }
+               last_offset = offset_ptr_rom;
+
+       } while (++re_src < re_end);
+
+       return 0;
+}
diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c
new file mode 100644 (file)
index 0000000..b0b46a4
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * For some reason linker sets linker-generated symbols to zero in PIE mode.
+ * A work-around is substitution of linker-generated symbols with
+ * compiler-generated symbols which are properly handled by linker in PAE mode.
+ */
+
+char __bss_start[0] __attribute__((section(".__bss_start")));
+char __bss_end[0] __attribute__((section(".__bss_end")));
+char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
+char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
+char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
+char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
+char __text_start[0] __attribute__((section(".__text_start")));
+char __text_end[0] __attribute__((section(".__text_end")));
+char __init_end[0] __attribute__((section(".__init_end")));
diff --git a/arch/arc/lib/strchr-700.S b/arch/arc/lib/strchr-700.S
new file mode 100644 (file)
index 0000000..55fcc9f
--- /dev/null
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * ARC700 has a relatively long pipeline and branch prediction, so we want
+ * to avoid branches that are hard to predict.  On the other hand, the
+ * presence of the norm instruction makes it easier to operate on whole
+ * words branch-free.
+ */
+
+.global strchr
+.align 4
+strchr:
+       extb_s  %r1, %r1
+       asl     %r5, %r1, 8
+       bmsk    %r2, %r0, 1
+       or      %r5, %r5, %r1
+       mov_s   %r3, 0x01010101
+       breq.d  %r2, %r0, .Laligned
+       asl     %r4, %r5, 16
+       sub_s   %r0, %r0, %r2
+       asl     %r7, %r2, 3
+       ld_s    %r2, [%r0]
+#ifdef __LITTLE_ENDIAN__
+       asl     %r7, %r3, %r7
+#else /* __BIG_ENDIAN__ */
+       lsr     %r7, %r3, %r7
+#endif /* _ENDIAN__ */
+       or      %r5, %r5, %r4
+       ror     %r4, %r3
+       sub     %r12, %r2, %r7
+       bic_s   %r12, %r12, %r2
+       and     %r12, %r12, %r4
+       brne.d  %r12, 0, .Lfound0_ua
+       xor     %r6, %r2, %r5
+       ld.a    %r2, [%r0, 4]
+       sub     %r12, %r6, %r7
+       bic     %r12, %r12, %r6
+#ifdef __LITTLE_ENDIAN__
+       and     %r7, %r12, %r4
+       /* For speed, we want this branch to be unaligned. */
+       breq    %r7, 0, .Loop
+       /* Likewise this one */
+       b       .Lfound_char
+#else /* __BIG_ENDIAN__ */
+       and     %r12, %r12, %r4
+       /* For speed, we want this branch to be unaligned. */
+       breq    %r12, 0, .Loop
+       lsr_s   %r12, %r12, 7
+       bic     %r2, %r7, %r6
+       b.d     .Lfound_char_b
+       and_s   %r2, %r2, %r12
+#endif /* _ENDIAN__ */
+       /* We require this code address to be unaligned for speed...  */
+.Laligned:
+       ld_s    %r2, [%r0]
+       or      %r5, %r5, %r4
+       ror     %r4, %r3
+       /* ... so that this code address is aligned, for itself and ...  */
+.Loop:
+       sub     %r12, %r2, %r3
+       bic_s   %r12, %r12, %r2
+       and     %r12, %r12, %r4
+       brne.d  %r12, 0, .Lfound0
+       xor     %r6, %r2, %r5
+       ld.a    %r2, [%r0, 4]
+       sub     %r12, %r6, %r3
+       bic     %r12, %r12, %r6
+       and     %r7, %r12, %r4
+       breq    %r7, 0, .Loop
+       /*
+        *... so that this branch is unaligned.
+        * Found searched-for character.
+        * r0 has already advanced to next word.
+        */
+#ifdef __LITTLE_ENDIAN__
+       /*
+        * We only need the information about the first matching byte
+        * (i.e. the least significant matching byte) to be exact,
+        * hence there is no problem with carry effects.
+        */
+.Lfound_char:
+       sub     %r3, %r7, 1
+       bic     %r3, %r3, %r7
+       norm    %r2, %r3
+       sub_s   %r0, %r0, 1
+       asr_s   %r2, %r2, 3
+       j.d     [%blink]
+       sub_s   %r0, %r0, %r2
+
+       .balign 4
+.Lfound0_ua:
+       mov     %r3, %r7
+.Lfound0:
+       sub     %r3, %r6, %r3
+       bic     %r3, %r3, %r6
+       and     %r2, %r3, %r4
+       or_s    %r12, %r12, %r2
+       sub_s   %r3, %r12, 1
+       bic_s   %r3, %r3, %r12
+       norm    %r3, %r3
+       add_s   %r0, %r0, 3
+       asr_s   %r12, %r3, 3
+       asl.f   0, %r2, %r3
+       sub_s   %r0, %r0, %r12
+       j_s.d   [%blink]
+       mov.pl  %r0, 0
+#else /* __BIG_ENDIAN__ */
+.Lfound_char:
+       lsr     %r7, %r7, 7
+
+       bic     %r2, %r7, %r6
+.Lfound_char_b:
+       norm    %r2, %r2
+       sub_s   %r0, %r0, 4
+       asr_s   %r2, %r2, 3
+       j.d     [%blink]
+       add_s   %r0, %r0, %r2
+
+.Lfound0_ua:
+       mov_s   %r3, %r7
+.Lfound0:
+       asl_s   %r2, %r2, 7
+       or      %r7, %r6, %r4
+       bic_s   %r12, %r12, %r2
+       sub     %r2, %r7, %r3
+       or      %r2, %r2, %r6
+       bic     %r12, %r2, %r12
+       bic.f   %r3, %r4, %r12
+       norm    %r3, %r3
+
+       add.pl  %r3, %r3, 1
+       asr_s   %r12, %r3, 3
+       asl.f   0, %r2, %r3
+       add_s   %r0, %r0, %r12
+       j_s.d   [%blink]
+       mov.mi  %r0, 0
+#endif /* _ENDIAN__ */
diff --git a/arch/arc/lib/strcmp.S b/arch/arc/lib/strcmp.S
new file mode 100644 (file)
index 0000000..8cb7d2f
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * This is optimized primarily for the ARC700.
+ * It would be possible to speed up the loops by one cycle / word
+ * respective one cycle / byte by forcing double source 1 alignment, unrolling
+ * by a factor of two, and speculatively loading the second word / byte of
+ * source 1; however, that would increase the overhead for loop setup / finish,
+ * and strcmp might often terminate early.
+ */
+
+.global strcmp
+.align 4
+strcmp:
+       or      %r2, %r0, %r1
+       bmsk_s  %r2, %r2, 1
+       brne    %r2, 0, .Lcharloop
+       mov_s   %r12, 0x01010101
+       ror     %r5, %r12
+.Lwordloop:
+       ld.ab   %r2, [%r0, 4]
+       ld.ab   %r3, [%r1, 4]
+       nop_s
+       sub     %r4, %r2, %r12
+       bic     %r4, %r4, %r2
+       and     %r4, %r4, %r5
+       brne    %r4, 0, .Lfound0
+       breq    %r2 ,%r3, .Lwordloop
+#ifdef __LITTLE_ENDIAN__
+       xor     %r0, %r2, %r3   /* mask for difference */
+       sub_s   %r1, %r0, 1
+       bic_s   %r0, %r0, %r1   /* mask for least significant difference bit */
+       sub     %r1, %r5, %r0
+       xor     %r0, %r5, %r1   /* mask for least significant difference byte */
+       and_s   %r2, %r2, %r0
+       and_s   %r3, %r3, %r0
+#endif /* _ENDIAN__ */
+       cmp_s   %r2, %r3
+       mov_s   %r0, 1
+       j_s.d   [%blink]
+       bset.lo %r0, %r0, 31
+
+       .balign 4
+#ifdef __LITTLE_ENDIAN__
+.Lfound0:
+       xor     %r0, %r2, %r3   /* mask for difference */
+       or      %r0, %r0, %r4   /* or in zero indicator */
+       sub_s   %r1, %r0, 1
+       bic_s   %r0, %r0, %r1   /* mask for least significant difference bit */
+       sub     %r1, %r5, %r0
+       xor     %r0, %r5, %r1   /* mask for least significant difference byte */
+       and_s   %r2, %r2, %r0
+       and_s   %r3, %r3, %r0
+       sub.f   %r0, %r2, %r3
+       mov.hi  %r0, 1
+       j_s.d   [%blink]
+       bset.lo %r0, %r0, 31
+#else /* __BIG_ENDIAN__ */
+       /*
+        * The zero-detection above can mis-detect 0x01 bytes as zeroes
+        * because of carry-propagateion from a lower significant zero byte.
+        * We can compensate for this by checking that bit0 is zero.
+        * This compensation is not necessary in the step where we
+        * get a low estimate for r2, because in any affected bytes
+        * we already have 0x00 or 0x01, which will remain unchanged
+        * when bit 7 is cleared.
+        */
+       .balign 4
+.Lfound0:
+       lsr     %r0, %r4, 8
+       lsr_s   %r1, %r2
+       bic_s   %r2, %r2, %r0   /* get low estimate for r2 and get ... */
+       bic_s   %r0, %r0, %r1   /* <this is the adjusted mask for zeros> */
+       or_s    %r3, %r3, %r0   /* ... high estimate r3 so that r2 > r3 will */
+       cmp_s   %r3, %r2        /* ... be independent of trailing garbage */
+       or_s    %r2, %r2, %r0   /* likewise for r3 > r2 */
+       bic_s   %r3, %r3, %r0
+       rlc     %r0, 0          /* r0 := r2 > r3 ? 1 : 0 */
+       cmp_s   %r2, %r3
+       j_s.d   [%blink]
+       bset.lo %r0, %r0, 31
+#endif /* _ENDIAN__ */
+
+       .balign 4
+.Lcharloop:
+       ldb.ab  %r2,[%r0,1]
+       ldb.ab  %r3,[%r1,1]
+       nop_s
+       breq    %r2, 0, .Lcmpend
+       breq    %r2, %r3, .Lcharloop
+.Lcmpend:
+       j_s.d   [%blink]
+       sub     %r0, %r2, %r3
diff --git a/arch/arc/lib/strcpy-700.S b/arch/arc/lib/strcpy-700.S
new file mode 100644 (file)
index 0000000..41bb53e
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * If dst and src are 4 byte aligned, copy 8 bytes at a time.
+ * If the src is 4, but not 8 byte aligned, we first read 4 bytes to get
+ * it 8 byte aligned.  Thus, we can do a little read-ahead, without
+ * dereferencing a cache line that we should not touch.
+ * Note that short and long instructions have been scheduled to avoid
+ * branch stalls.
+ * The beq_s to r3z could be made unaligned & long to avoid a stall
+ * there, but it is not likely to be taken often, and it would also be likely
+ * to cost an unaligned mispredict at the next call.
+ */
+
+.global strcpy
+.align 4
+strcpy:
+       or      %r2, %r0, %r1
+       bmsk_s  %r2, %r2, 1
+       brne.d  %r2, 0, charloop
+       mov_s   %r10, %r0
+       ld_s    %r3, [%r1, 0]
+       mov     %r8, 0x01010101
+       bbit0.d %r1, 2, loop_start
+       ror     %r12, %r8
+       sub     %r2, %r3, %r8
+       bic_s   %r2, %r2, %r3
+       tst_s   %r2,%r12
+       bne     r3z
+       mov_s   %r4,%r3
+       .balign 4
+loop:
+       ld.a    %r3, [%r1, 4]
+       st.ab   %r4, [%r10, 4]
+loop_start:
+       ld.a    %r4, [%r1, 4]
+       sub     %r2, %r3, %r8
+       bic_s   %r2, %r2, %r3
+       tst_s   %r2, %r12
+       bne_s   r3z
+       st.ab   %r3, [%r10, 4]
+       sub     %r2, %r4, %r8
+       bic     %r2, %r2, %r4
+       tst     %r2, %r12
+       beq     loop
+       mov_s   %r3, %r4
+#ifdef __LITTLE_ENDIAN__
+r3z:   bmsk.f  %r1, %r3, 7
+       lsr_s   %r3, %r3, 8
+#else /* __BIG_ENDIAN__ */
+r3z:   lsr.f   %r1, %r3, 24
+       asl_s   %r3, %r3, 8
+#endif /* _ENDIAN__ */
+       bne.d   r3z
+       stb.ab  %r1, [%r10, 1]
+       j_s     [%blink]
+
+       .balign 4
+charloop:
+       ldb.ab  %r3, [%r1, 1]
+       brne.d  %r3, 0, charloop
+       stb.ab  %r3, [%r10, 1]
+       j       [%blink]
diff --git a/arch/arc/lib/strlen.S b/arch/arc/lib/strlen.S
new file mode 100644 (file)
index 0000000..666e22c
--- /dev/null
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2004, 2007-2010, 2011-2014 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+.global strlen
+.align 4
+strlen:
+       or      %r3, %r0, 7
+       ld      %r2, [%r3, -7]
+       ld.a    %r6, [%r3, -3]
+       mov     %r4, 0x01010101
+       /* uses long immediate */
+#ifdef __LITTLE_ENDIAN__
+       asl_s   %r1, %r0, 3
+       btst_s  %r0, 2
+       asl     %r7, %r4, %r1
+       ror     %r5, %r4
+       sub     %r1, %r2, %r7
+       bic_s   %r1, %r1, %r2
+       mov.eq  %r7, %r4
+       sub     %r12, %r6, %r7
+       bic     %r12, %r12, %r6
+       or.eq   %r12, %r12, %r1
+       and     %r12, %r12, %r5
+       brne    %r12, 0, .Learly_end
+#else /* __BIG_ENDIAN__ */
+       ror     %r5, %r4
+       btst_s  %r0, 2
+       mov_s   %r1, 31
+       sub3    %r7, %r1, %r0
+       sub     %r1, %r2, %r4
+       bic_s   %r1, %r1, %r2
+       bmsk    %r1, %r1, %r7
+       sub     %r12, %r6, %r4
+       bic     %r12, %r12, %r6
+       bmsk.ne %r12, %r12, %r7
+       or.eq   %r12, %r12, %r1
+       and     %r12, %r12, %r5
+       brne    %r12, 0, .Learly_end
+#endif /* _ENDIAN__ */
+
+.Loop:
+       ld_s    %r2, [%r3, 4]
+       ld.a    %r6, [%r3, 8]
+       /* stall for load result */
+       sub     %r1, %r2, %r4
+       bic_s   %r1, %r1, %r2
+       sub     %r12, %r6, %r4
+       bic     %r12, %r12, %r6
+       or      %r12, %r12, %r1
+       and     %r12, %r12, %r5
+       breq    %r12, 0, .Loop
+.Lend:
+       and.f   %r1, %r1, %r5
+       sub.ne  %r3, %r3, 4
+       mov.eq  %r1, %r12
+#ifdef __LITTLE_ENDIAN__
+       sub_s   %r2, %r1, 1
+       bic_s   %r2, %r2, %r1
+       norm    %r1, %r2
+       sub_s   %r0, %r0, 3
+       lsr_s   %r1, %r1, 3
+       sub     %r0, %r3, %r0
+       j_s.d   [%blink]
+       sub     %r0, %r0, %r1
+#else /* __BIG_ENDIAN__ */
+       lsr_s   %r1, %r1, 7
+       mov.eq  %r2, %r6
+       bic_s   %r1, %r1, %r2
+       norm    %r1, %r1
+       sub     %r0, %r3, %r0
+       lsr_s   %r1, %r1, 3
+       j_s.d   [%blink]
+       add     %r0, %r0, %r1
+#endif /* _ENDIAN */
+.Learly_end:
+       b.d     .Lend
+       sub_s.ne %r1, %r1, %r1
diff --git a/arch/arm/cpu/arm1176/bcm2835/config.mk b/arch/arm/cpu/arm1176/bcm2835/config.mk
deleted file mode 100644 (file)
index b87ce24..0000000
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# (C) Copyright 2012 Stephen Warren
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License
-# version 2 as published by the Free Software Foundation.
-#
-# This program is distributed in the hope that it will be useful, but
-# WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# Don't attempt to override the target CPU/ABI options;
-# the Raspberry Pi toolchain does the right thing by default.
-PLATFORM_RELFLAGS := $(filter-out -msoft-float,$(PLATFORM_RELFLAGS))
-PLATFORM_CPPFLAGS := $(filter-out -march=armv5t,$(PLATFORM_CPPFLAGS))
index 72c69b9..2c5cd63 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -112,24 +112,38 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
                { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
                { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
        },
+
+       /*
+        * T124: 700 MHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      23:20    4
+        * PLLX_BASE  n      15: 8    8
+        * PLLX_BASE  m       7: 0    8
+        */
+       {
+               { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+               { .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+               { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+               { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
+       },
 };
 
-void adjust_pllp_out_freqs(void)
+static inline void pllx_set_iddq(void)
 {
+#if defined(CONFIG_TEGRA124)
        struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-       struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
        u32 reg;
 
-       /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
-       reg = readl(&pll->pll_out[0]);  /* OUTA, contains OUT2 / OUT1 */
-       reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
-               | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
-       writel(reg, &pll->pll_out[0]);
-
-       reg = readl(&pll->pll_out[1]);   /* OUTB, contains OUT4 / OUT3 */
-       reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
-               | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
-       writel(reg, &pll->pll_out[1]);
+       /* Disable IDDQ */
+       reg = readl(&clkrst->crc_pllx_misc3);
+       reg &= ~PLLX_IDDQ_MASK;
+       writel(reg, &clkrst->crc_pllx_misc3);
+       udelay(2);
+       debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
+             readl(&clkrst->crc_pllx_misc3));
+#endif
 }
 
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
@@ -146,6 +160,8 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
 
        debug(" pllx_set_rate entry\n");
 
+       pllx_set_iddq();
+
        /* Set BYPASS, m, n and p to PLLX_BASE */
        reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
        reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
@@ -162,18 +178,23 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
                reg |= (1 << PLL_DCCON_SHIFT);
        writel(reg, &pll->pll_misc);
 
-       /* Enable PLLX */
-       reg = readl(&pll->pll_base);
-       reg |= PLL_ENABLE_MASK;
-
        /* Disable BYPASS */
+       reg = readl(&pll->pll_base);
        reg &= ~PLL_BYPASS_MASK;
        writel(reg, &pll->pll_base);
+       debug("pllx_set_rate: base = 0x%08X\n", reg);
 
        /* Set lock_enable to PLLX_MISC */
        reg = readl(&pll->pll_misc);
        reg |= PLL_LOCK_ENABLE_MASK;
        writel(reg, &pll->pll_misc);
+       debug("pllx_set_rate: misc = 0x%08X\n", reg);
+
+       /* Enable PLLX last, once it's all configured */
+       reg = readl(&pll->pll_base);
+       reg |= PLL_ENABLE_MASK;
+       writel(reg, &pll->pll_base);
+       debug("pllx_set_rate: base final = 0x%08X\n", reg);
 
        return 0;
 }
@@ -207,12 +228,6 @@ void init_pllx(void)
        /* set pllx */
        sel = &tegra_pll_x_table[chip_sku][osc];
        pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
-
-       /* adjust PLLP_out1-4 on T3x/T114 */
-       if (soc_type >= CHIPID_TEGRA30) {
-               debug("  init_pllx: adjusting PLLP out freqs\n");
-               adjust_pllp_out_freqs();
-       }
 }
 
 void enable_cpu_clock(int enable)
@@ -334,7 +349,6 @@ void reset_A9_cpu(int reset)
 void clock_enable_coresight(int enable)
 {
        u32 rst, src = 2;
-       int soc_type;
 
        debug("clock_enable_coresight entry\n");
        clock_set_enable(PERIPH_ID_CORESIGHT, enable);
@@ -343,20 +357,11 @@ void clock_enable_coresight(int enable)
        if (enable) {
                /*
                 * Put CoreSight on PLLP_OUT0 and divide it down as per
-                * PLLP base frequency based on SoC type (T20/T30/T114).
+                * PLLP base frequency based on SoC type (T20/T30+).
                 * Clock divider request would setup CSITE clock as 144MHz
                 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
                 */
-
-               soc_type = tegra_get_chip();
-               if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
-                       src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
-               else if (soc_type == CHIPID_TEGRA20)
-                       src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
-               else
-                       printf("%s: Unknown SoC type %X!\n",
-                                __func__, soc_type);
-
+               src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
                clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
 
                /* Unlock the CPU CoreSight interfaces */
index 60412c7..b4ca44f 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2014
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
 #define IO_STABILIZATION_DELAY (1000)
 
 #if defined(CONFIG_TEGRA20)
-#define NVBL_PLLP_KHZ  (216000)
-#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
-#define NVBL_PLLP_KHZ  (408000)
+#define NVBL_PLLP_KHZ  216000
+#define CSITE_KHZ      144000
+#elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
+       defined(CONFIG_TEGRA124)
+#define NVBL_PLLP_KHZ  408000
+#define CSITE_KHZ      204000
 #else
 #error "Unknown Tegra chip!"
 #endif
@@ -68,3 +71,4 @@ int tegra_get_chip(void);
 int tegra_get_sku_info(void);
 int tegra_get_chip_sku(void);
 void adjust_pllp_out_freqs(void);
+void pmic_enable_cpu_vdd(void);
index 51ecff7..d10b96a 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -68,7 +68,7 @@ static void enable_cpu_clocks(void)
        /* Wait for PLL-X to lock */
        do {
                reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
-       } while ((reg & (1 << 27)) == 0);
+       } while ((reg & PLL_LOCK_MASK) == 0);
 
        /* Wait until all clocks are stable */
        udelay(PLL_STABILIZATION_DELAY);
@@ -126,18 +126,6 @@ void t114_init_clocks(void)
        /* Set active CPU cluster to G */
        clrbits_le32(&flow->cluster_control, 1);
 
-       /*
-        * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-        * at 108 MHz. This is glitch free as only the source is changed, no
-        * special precaution needed.
-        */
-       val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-               (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-       writel(val, &clkrst->crc_sclk_brst_pol);
-
        writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
        debug("Setting up PLLX\n");
@@ -204,45 +192,43 @@ void t114_init_clocks(void)
        debug("t114_init_clocks exit\n");
 }
 
-static int is_partition_powered(u32 mask)
+static bool is_partition_powered(u32 partid)
 {
        struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
        /* Get power gate status */
        reg = readl(&pmc->pmc_pwrgate_status);
-       return (reg & mask) == mask;
+       return !!(reg & (1 << partid));
 }
 
-static int is_clamp_enabled(u32 mask)
+static bool is_clamp_enabled(u32 partid)
 {
        struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
        u32 reg;
 
-       /* Get clamp status. TODO: Add pmc_clamp_status alias to pmc.h */
-       reg = readl(&pmc->pmc_pwrgate_timer_on);
-       return (reg & mask) == mask;
+       /* Get clamp status. */
+       reg = readl(&pmc->pmc_clamp_status);
+       return !!(reg & (1 << partid));
 }
 
-static void power_partition(u32 status, u32 partid)
+static void power_partition(u32 partid)
 {
        struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
 
-       debug("%s: status = %08X, part ID = %08X\n", __func__, status, partid);
+       debug("%s: part ID = %08X\n", __func__, partid);
        /* Is the partition already on? */
-       if (!is_partition_powered(status)) {
+       if (!is_partition_powered(partid)) {
                /* No, toggle the partition power state (OFF -> ON) */
                debug("power_partition, toggling state\n");
-               clrbits_le32(&pmc->pmc_pwrgate_toggle, 0x1F);
-               setbits_le32(&pmc->pmc_pwrgate_toggle, partid);
-               setbits_le32(&pmc->pmc_pwrgate_toggle, START_CP);
+               writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
 
                /* Wait for the power to come up */
-               while (!is_partition_powered(status))
+               while (!is_partition_powered(partid))
                        ;
 
                /* Wait for the clamp status to be cleared */
-               while (is_clamp_enabled(status))
+               while (is_clamp_enabled(partid))
                        ;
 
                /* Give I/O signals time to stabilize */
@@ -257,13 +243,13 @@ void powerup_cpus(void)
        /* We boot to the fast cluster */
        debug("powerup_cpus entry: G cluster\n");
        /* Power up the fast cluster rail partition */
-       power_partition(CRAIL, CRAILID);
+       power_partition(CRAIL);
 
        /* Power up the fast cluster non-CPU partition */
-       power_partition(C0NC, C0NCID);
+       power_partition(C0NC);
 
        /* Power up the fast cluster CPU0 partition */
-       power_partition(CE0, CE0ID);
+       power_partition(CE0);
 }
 
 void start_cpu(u32 reset_vector)
diff --git a/arch/arm/cpu/arm720t/tegra124/Makefile b/arch/arm/cpu/arm720t/tegra124/Makefile
new file mode 100644 (file)
index 0000000..61abf45
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += cpu.o
diff --git a/arch/arm/cpu/arm720t/tegra124/config.mk b/arch/arm/cpu/arm720t/tegra124/config.mk
new file mode 100644 (file)
index 0000000..5e10701
--- /dev/null
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2010-2013
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#/
+USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/arm720t/tegra124/cpu.c b/arch/arm/cpu/arm720t/tegra124/cpu.c
new file mode 100644 (file)
index 0000000..c03aaf1
--- /dev/null
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/ahb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/flow.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/ap.h>
+#include "../tegra-common/cpu.h"
+
+/* Tegra124-specific CPU init code */
+
+static void enable_cpu_power_rail(void)
+{
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+       debug("enable_cpu_power_rail entry\n");
+
+       /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
+       pinmux_tristate_disable(PINGRP_PWR_I2C_SCL);
+       pinmux_tristate_disable(PINGRP_PWR_I2C_SDA);
+
+       pmic_enable_cpu_vdd();
+
+       /*
+        * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
+        * set it for 5ms as per SysEng (102MHz*5ms = 510000 (7C830h).
+        */
+       writel(0x7C830, &pmc->pmc_cpupwrgood_timer);
+
+       /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+       clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
+       setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
+}
+
+static void enable_cpu_clocks(void)
+{
+       struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 reg;
+
+       debug("enable_cpu_clocks entry\n");
+
+       /* Wait for PLL-X to lock */
+       do {
+               reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
+               debug("%s: PLLX base = 0x%08X\n", __func__, reg);
+       } while ((reg & PLL_LOCK_MASK) == 0);
+
+       debug("%s: PLLX locked, delay for stable clocks\n", __func__);
+       /* Wait until all clocks are stable */
+       udelay(PLL_STABILIZATION_DELAY);
+
+       debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
+       writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
+       writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
+
+       debug("%s: Enabling clock to all CPUs\n", __func__);
+       /* Enable the clock to all CPUs */
+       reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
+               CLR_CPU0_CLK_STP;
+       writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
+
+       debug("%s: Enabling main CPU complex clocks\n", __func__);
+       /* Always enable the main CPU complex clocks */
+       clock_enable(PERIPH_ID_CPU);
+       clock_enable(PERIPH_ID_CPULP);
+       clock_enable(PERIPH_ID_CPUG);
+
+       debug("%s: Done\n", __func__);
+}
+
+static void remove_cpu_resets(void)
+{
+       struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 reg;
+
+       debug("remove_cpu_resets entry\n");
+
+       /* Take the slow and fast partitions out of reset */
+       reg = CLR_NONCPURESET;
+       writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+       writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+
+       /* Clear the SW-controlled reset of the slow cluster */
+       reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+               CLR_L2RESET | CLR_PRESETDBG;
+       writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
+
+       /* Clear the SW-controlled reset of the fast cluster */
+       reg = CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
+               CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
+               CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
+               CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3 |
+               CLR_L2RESET | CLR_PRESETDBG;
+       writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
+}
+
+/**
+ * The Tegra124 requires some special clock initialization, including setting up
+ * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
+ */
+void tegra124_init_clocks(void)
+{
+       struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+       struct clk_rst_ctlr *clkrst =
+                       (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 val;
+
+       debug("tegra124_init_clocks entry\n");
+
+       /* Set active CPU cluster to G */
+       clrbits_le32(&flow->cluster_control, 1);
+
+       /* Change the oscillator drive strength */
+       val = readl(&clkrst->crc_osc_ctrl);
+       val &= ~OSC_XOFS_MASK;
+       val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
+       writel(val, &clkrst->crc_osc_ctrl);
+
+       /* Update same value in PMC_OSC_EDPD_OVER XOFS field for warmboot */
+       val = readl(&pmc->pmc_osc_edpd_over);
+       val &= ~PMC_XOFS_MASK;
+       val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT);
+       writel(val, &pmc->pmc_osc_edpd_over);
+
+       /* Set HOLD_CKE_LOW_EN to 1 */
+       setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN);
+
+       debug("Setting up PLLX\n");
+       init_pllx();
+
+       val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
+       writel(val, &clkrst->crc_clk_sys_rate);
+
+       /* Enable clocks to required peripherals. TBD - minimize this list */
+       debug("Enabling clocks\n");
+
+       clock_set_enable(PERIPH_ID_CACHE2, 1);
+       clock_set_enable(PERIPH_ID_GPIO, 1);
+       clock_set_enable(PERIPH_ID_TMR, 1);
+       clock_set_enable(PERIPH_ID_CPU, 1);
+       clock_set_enable(PERIPH_ID_EMC, 1);
+       clock_set_enable(PERIPH_ID_I2C5, 1);
+       clock_set_enable(PERIPH_ID_APBDMA, 1);
+       clock_set_enable(PERIPH_ID_MEM, 1);
+       clock_set_enable(PERIPH_ID_CORESIGHT, 1);
+       clock_set_enable(PERIPH_ID_MSELECT, 1);
+       clock_set_enable(PERIPH_ID_DVFS, 1);
+
+       /*
+        * Set MSELECT clock source as PLLP (00), and ask for a clock
+        * divider that would set the MSELECT clock at 102MHz for a
+        * PLLP base of 408MHz.
+        */
+       clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
+                                   CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
+
+       /* Give clock time to stabilize */
+       udelay(IO_STABILIZATION_DELAY);
+
+       /* I2C5 (DVC) gets CLK_M and a divisor of 17 */
+       clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
+
+       /* Give clock time to stabilize */
+       udelay(IO_STABILIZATION_DELAY);
+
+       /* Take required peripherals out of reset */
+       debug("Taking periphs out of reset\n");
+       reset_set_enable(PERIPH_ID_CACHE2, 0);
+       reset_set_enable(PERIPH_ID_GPIO, 0);
+       reset_set_enable(PERIPH_ID_TMR, 0);
+       reset_set_enable(PERIPH_ID_COP, 0);
+       reset_set_enable(PERIPH_ID_EMC, 0);
+       reset_set_enable(PERIPH_ID_I2C5, 0);
+       reset_set_enable(PERIPH_ID_APBDMA, 0);
+       reset_set_enable(PERIPH_ID_MEM, 0);
+       reset_set_enable(PERIPH_ID_CORESIGHT, 0);
+       reset_set_enable(PERIPH_ID_MSELECT, 0);
+       reset_set_enable(PERIPH_ID_DVFS, 0);
+
+       debug("tegra124_init_clocks exit\n");
+}
+
+static bool is_partition_powered(u32 partid)
+{
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+       u32 reg;
+
+       /* Get power gate status */
+       reg = readl(&pmc->pmc_pwrgate_status);
+       return !!(reg & (1 << partid));
+}
+
+static void power_partition(u32 partid)
+{
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+       debug("%s: part ID = %08X\n", __func__, partid);
+       /* Is the partition already on? */
+       if (!is_partition_powered(partid)) {
+               /* No, toggle the partition power state (OFF -> ON) */
+               debug("power_partition, toggling state\n");
+               writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+               /* Wait for the power to come up */
+               while (!is_partition_powered(partid))
+                       ;
+
+               /* Give I/O signals time to stabilize */
+               udelay(IO_STABILIZATION_DELAY);
+       }
+}
+
+void powerup_cpus(void)
+{
+       debug("powerup_cpus entry\n");
+
+       /* We boot to the fast cluster */
+       debug("powerup_cpus entry: G cluster\n");
+
+       /* Power up the fast cluster rail partition */
+       debug("powerup_cpus: CRAIL\n");
+       power_partition(CRAIL);
+
+       /* Power up the fast cluster non-CPU partition */
+       debug("powerup_cpus: C0NC\n");
+       power_partition(C0NC);
+
+       /* Power up the fast cluster CPU0 partition */
+       debug("powerup_cpus: CE0\n");
+       power_partition(CE0);
+
+       debug("powerup_cpus: done\n");
+}
+
+void start_cpu(u32 reset_vector)
+{
+       struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+       debug("start_cpu entry, reset_vector = %x\n", reset_vector);
+
+       tegra124_init_clocks();
+
+       /* Set power-gating timer multiplier */
+       clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
+       setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
+
+       enable_cpu_power_rail();
+       enable_cpu_clocks();
+       clock_enable_coresight(1);
+       remove_cpu_resets();
+       writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
+       powerup_cpus();
+       debug("start_cpu exit, should continue @ reset_vector\n");
+}
index e162357..a806483 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -84,18 +84,6 @@ void t30_init_clocks(void)
        /* Set active CPU cluster to G */
        clrbits_le32(flow->cluster_control, 1 << 0);
 
-       /*
-        * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-        * at 108 MHz. This is glitch free as only the source is changed, no
-        * special precaution needed.
-        */
-       val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-               (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-       writel(val, &clkrst->crc_sclk_brst_pol);
-
        writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
        val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
index 5bde9d1..1fea4d6 100644 (file)
@@ -26,7 +26,7 @@ struct clk_bit_info {
 };
 
 /* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
+static struct clk_bit_info clk_bit_info[] = {
        {0,     0,      -1},
        {4,     4,      -1},
        {8,     8,      -1},
@@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
        struct exynos4_clock *clk =
                (struct exynos4_clock *)samsung_get_base_clock();
        unsigned int addr;
-       unsigned int val;
 
        /*
         * CLK_DIV_FSYS1
@@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
                dev_index -= 2;
        }
 
-       val = readl(addr);
-       val &= ~(0xff << ((dev_index << 4) + 8));
-       val |= (div & 0xff) << ((dev_index << 4) + 8);
-       writel(val, addr);
+       clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+                       (div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos4x12: set the mmc clock */
@@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
        struct exynos4x12_clock *clk =
                (struct exynos4x12_clock *)samsung_get_base_clock();
        unsigned int addr;
-       unsigned int val;
 
        /*
         * CLK_DIV_FSYS1
@@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
                dev_index -= 2;
        }
 
-       val = readl(addr);
-       val &= ~(0xff << ((dev_index << 4) + 8));
-       val |= (div & 0xff) << ((dev_index << 4) + 8);
-       writel(val, addr);
+       clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+                       (div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos5: set the mmc clock */
@@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
        struct exynos5_clock *clk =
                (struct exynos5_clock *)samsung_get_base_clock();
        unsigned int addr;
-       unsigned int val;
 
        /*
         * CLK_DIV_FSYS1
@@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
                dev_index -= 2;
        }
 
-       val = readl(addr);
-       val &= ~(0xff << ((dev_index << 4) + 8));
-       val |= (div & 0xff) << ((dev_index << 4) + 8);
-       writel(val, addr);
+       clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
+                       (div & 0xff) << ((dev_index << 4) + 8));
 }
 
 /* exynos5: set the mmc clock */
@@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
        struct exynos5420_clock *clk =
                (struct exynos5420_clock *)samsung_get_base_clock();
        unsigned int addr;
-       unsigned int val, shift;
+       unsigned int shift;
 
        /*
         * CLK_DIV_FSYS1
@@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
        addr = (unsigned int)&clk->div_fsys1;
        shift = dev_index * 10;
 
-       val = readl(addr);
-       val &= ~(0x3ff << shift);
-       val |= (div & 0x3ff) << shift;
-       writel(val, addr);
+       clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
 }
 
 /* get_lcd_clk: return lcd clock frequency */
@@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
 {
        struct exynos4_clock *clk =
            (struct exynos4_clock *)samsung_get_base_clock();
-       unsigned int cfg = 0;
 
        /*
         * CLK_GATE_BLOCK
@@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
         * CLK_LCD1     [5]
         * CLK_GPS      [7]
         */
-       cfg = readl(&clk->gate_block);
-       cfg |= 1 << 4;
-       writel(cfg, &clk->gate_block);
+       setbits_le32(&clk->gate_block, 1 << 4);
 
        /*
         * CLK_SRC_LCD0
@@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
         * MIPI0_SEL            [12:15]
         * set lcd0 src clock 0x6: SCLK_MPLL
         */
-       cfg = readl(&clk->src_lcd0);
-       cfg &= ~(0xf);
-       cfg |= 0x6;
-       writel(cfg, &clk->src_lcd0);
+       clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
 
        /*
         * CLK_GATE_IP_LCD0
@@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
         * CLK_PPMULCD0         [5]
         * Gating all clocks for FIMD0
         */
-       cfg = readl(&clk->gate_ip_lcd0);
-       cfg |= 1 << 0;
-       writel(cfg, &clk->gate_ip_lcd0);
+       setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
 
        /*
         * CLK_DIV_LCD0
@@ -1114,16 +1094,13 @@ void exynos4_set_lcd_clk(void)
         * MIPI0_PRE_RATIO      [23:20]
         * set fimd ratio
         */
-       cfg &= ~(0xf);
-       cfg |= 0x1;
-       writel(cfg, &clk->div_lcd0);
+       clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
 }
 
 void exynos5_set_lcd_clk(void)
 {
        struct exynos5_clock *clk =
            (struct exynos5_clock *)samsung_get_base_clock();
-       unsigned int cfg = 0;
 
        /*
         * CLK_GATE_BLOCK
@@ -1135,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
         * CLK_LCD1     [5]
         * CLK_GPS      [7]
         */
-       cfg = readl(&clk->gate_block);
-       cfg |= 1 << 4;
-       writel(cfg, &clk->gate_block);
+       setbits_le32(&clk->gate_block, 1 << 4);
 
        /*
         * CLK_SRC_LCD0
@@ -1147,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
         * MIPI0_SEL            [12:15]
         * set lcd0 src clock 0x6: SCLK_MPLL
         */
-       cfg = readl(&clk->src_disp1_0);
-       cfg &= ~(0xf);
-       cfg |= 0x6;
-       writel(cfg, &clk->src_disp1_0);
+       clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
 
        /*
         * CLK_GATE_IP_LCD0
@@ -1162,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
         * CLK_PPMULCD0         [5]
         * Gating all clocks for FIMD0
         */
-       cfg = readl(&clk->gate_ip_disp1);
-       cfg |= 1 << 0;
-       writel(cfg, &clk->gate_ip_disp1);
+       setbits_le32(&clk->gate_ip_disp1, 1 << 0);
 
        /*
         * CLK_DIV_LCD0
@@ -1176,16 +1146,13 @@ void exynos5_set_lcd_clk(void)
         * MIPI0_PRE_RATIO      [23:20]
         * set fimd ratio
         */
-       cfg &= ~(0xf);
-       cfg |= 0x0;
-       writel(cfg, &clk->div_disp1_0);
+       clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
 }
 
 void exynos4_set_mipi_clk(void)
 {
        struct exynos4_clock *clk =
            (struct exynos4_clock *)samsung_get_base_clock();
-       unsigned int cfg = 0;
 
        /*
         * CLK_SRC_LCD0
@@ -1195,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
         * MIPI0_SEL            [12:15]
         * set mipi0 src clock 0x6: SCLK_MPLL
         */
-       cfg = readl(&clk->src_lcd0);
-       cfg &= ~(0xf << 12);
-       cfg |= (0x6 << 12);
-       writel(cfg, &clk->src_lcd0);
+       clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
 
        /*
         * CLK_SRC_MASK_LCD0
@@ -1208,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
         * MIPI0_MASK           [12]
         * set src mask mipi0 0x1: Unmask
         */
-       cfg = readl(&clk->src_mask_lcd0);
-       cfg |= (0x1 << 12);
-       writel(cfg, &clk->src_mask_lcd0);
+       setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
 
        /*
         * CLK_GATE_IP_LCD0
@@ -1222,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
         * CLK_PPMULCD0         [5]
         * Gating all clocks for MIPI0
         */
-       cfg = readl(&clk->gate_ip_lcd0);
-       cfg |= 1 << 3;
-       writel(cfg, &clk->gate_ip_lcd0);
+       setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
 
        /*
         * CLK_DIV_LCD0
@@ -1236,9 +1196,7 @@ void exynos4_set_mipi_clk(void)
         * MIPI0_PRE_RATIO      [23:20]
         * set mipi ratio
         */
-       cfg &= ~(0xf << 16);
-       cfg |= (0x1 << 16);
-       writel(cfg, &clk->div_lcd0);
+       clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
 }
 
 /*
index 904177a..645c497 100644 (file)
@@ -751,12 +751,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node)
        if (err)
                return PERIPH_ID_NONE;
 
-       /* check for invalid peripheral id */
-       if ((PERIPH_ID_SDMMC4 > cell[1]) || (cell[1] < PERIPH_ID_UART0))
-               return cell[1];
-
-       debug(" invalid peripheral id\n");
-       return PERIPH_ID_NONE;
+       return cell[1];
 }
 
 int pinmux_decode_periph_id(const void *blob, int node)
index 69fff32..52e0f4a 100644 (file)
@@ -66,7 +66,18 @@ u32 spl_boot_device(void)
 
 u32 spl_boot_mode(void)
 {
-       return gd->arch.omap_boot_params.omap_bootmode;
+       u32 val = gd->arch.omap_boot_params.omap_bootmode;
+
+       if (val == MMCSD_MODE_RAW)
+               return MMCSD_MODE_RAW;
+       else if (val == MMCSD_MODE_FAT)
+               return MMCSD_MODE_FAT;
+       else
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+               return MMCSD_MODE_EMMCBOOT;
+#else
+               return MMCSD_MODE_UNDEFINED;
+#endif
 }
 
 void spl_board_init(void)
diff --git a/arch/arm/cpu/armv7/tegra124/Makefile b/arch/arm/cpu/armv7/tegra124/Makefile
new file mode 100644 (file)
index 0000000..7f127b1
--- /dev/null
@@ -0,0 +1,6 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
diff --git a/arch/arm/cpu/armv7/tegra124/config.mk b/arch/arm/cpu/armv7/tegra124/config.mk
new file mode 100644 (file)
index 0000000..2f1c645
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013
+# NVIDIA Corporation <www.nvidia.com>
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+CONFIG_ARCH_DEVICE_TREE := tegra124
index d382d49..3363a3c 100644 (file)
@@ -12,3 +12,5 @@ obj-y := timer.o
 obj-y  += cpu.o
 obj-y  += ddrc.o
 obj-y  += slcr.o
+obj-y  += clk.o
+obj-$(CONFIG_SPL_BUILD)        += spl.o
diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c
new file mode 100644 (file)
index 0000000..d2885dc
--- /dev/null
@@ -0,0 +1,664 @@
+/*
+ * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
+ * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
+
+/* Board oscillator frequency */
+#ifndef CONFIG_ZYNQ_PS_CLK_FREQ
+# define CONFIG_ZYNQ_PS_CLK_FREQ       33333333UL
+#endif
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK     0x7f000
+#define PLLCTRL_FBDIV_SHIFT    12
+#define PLLCTRL_BPFORCE_MASK   (1 << 4)
+#define PLLCTRL_PWRDWN_MASK    2
+#define PLLCTRL_PWRDWN_SHIFT   1
+#define PLLCTRL_RESET_MASK     1
+#define PLLCTRL_RESET_SHIFT    0
+
+#define ZYNQ_CLK_MAXDIV                0x3f
+#define CLK_CTRL_DIV1_SHIFT    20
+#define CLK_CTRL_DIV1_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
+#define CLK_CTRL_DIV0_SHIFT    8
+#define CLK_CTRL_DIV0_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
+#define CLK_CTRL_SRCSEL_SHIFT  4
+#define CLK_CTRL_SRCSEL_MASK   (0x3 << CLK_CTRL_SRCSEL_SHIFT)
+
+#define CLK_CTRL_DIV2X_SHIFT   26
+#define CLK_CTRL_DIV2X_MASK    (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
+#define CLK_CTRL_DIV3X_SHIFT   20
+#define CLK_CTRL_DIV3X_MASK    (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
+
+#define ZYNQ_CLKMUX_SEL_0      0
+#define ZYNQ_CLKMUX_SEL_1      1
+#define ZYNQ_CLKMUX_SEL_2      2
+#define ZYNQ_CLKMUX_SEL_3      3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clk;
+
+/**
+ * struct clk_ops:
+ * @set_rate:  Function pointer to set_rate() implementation
+ * @get_rate:  Function pointer to get_rate() implementation
+ */
+struct clk_ops {
+       int (*set_rate)(struct clk *clk, unsigned long rate);
+       unsigned long (*get_rate)(struct clk *clk);
+};
+
+/**
+ * struct clk:
+ * @name:      Clock name
+ * @frequency: Currenct frequency
+ * @parent:    Parent clock
+ * @flags:     Clock flags
+ * @reg:       Clock control register
+ * @ops:       Clock operations
+ */
+struct clk {
+       char            *name;
+       unsigned long   frequency;
+       enum zynq_clk   parent;
+       unsigned int    flags;
+       u32             *reg;
+       struct clk_ops  ops;
+};
+#define ZYNQ_CLK_FLAGS_HAS_2_DIVS      1
+
+static struct clk clks[clk_max];
+
+/**
+ * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
+ * @srcsel:    Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
+{
+       unsigned int ret;
+
+       switch (srcsel) {
+       case ZYNQ_CLKMUX_SEL_0:
+       case ZYNQ_CLKMUX_SEL_1:
+               ret = armpll_clk;
+               break;
+       case ZYNQ_CLKMUX_SEL_2:
+               ret = ddrpll_clk;
+               break;
+       case ZYNQ_CLKMUX_SEL_3:
+               ret = iopll_clk;
+               break;
+       default:
+               ret = armpll_clk;
+               break;
+       }
+
+       return ret;
+}
+
+/**
+ * ddr2x_get_rate() - Get clock rate of DDR2x clock
+ * @clk:       Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr2x_get_rate(struct clk *clk)
+{
+       u32 clk_ctrl = readl(clk->reg);
+       u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
+
+       return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+/**
+ * ddr3x_get_rate() - Get clock rate of DDR3x clock
+ * @clk:       Clock handle
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long ddr3x_get_rate(struct clk *clk)
+{
+       u32 clk_ctrl = readl(clk->reg);
+       u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
+
+       return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
+}
+
+static void init_ddr_clocks(void)
+{
+       u32 div0, div1;
+       unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
+       u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
+
+       /* DDR2x */
+       clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
+       clks[ddr2x_clk].parent = ddrpll_clk;
+       clks[ddr2x_clk].name = "ddr_2x";
+       clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
+       clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
+
+       /* DDR3x */
+       clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
+       clks[ddr3x_clk].parent = ddrpll_clk;
+       clks[ddr3x_clk].name = "ddr_3x";
+       clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
+       clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
+
+       /* DCI */
+       clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
+       div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+       div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+       clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
+       clks[dci_clk].parent = ddrpll_clk;
+       clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
+                       DIV_ROUND_CLOSEST(prate, div0), div1);
+       clks[dci_clk].name = "dci";
+
+       gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
+}
+
+static void init_cpu_clocks(void)
+{
+       int clk_621;
+       u32 reg, div, srcsel;
+       enum zynq_clk parent;
+
+       reg = readl(&slcr_base->arm_clk_ctrl);
+       clk_621 = readl(&slcr_base->clk_621_true) & 1;
+       div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+       srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+       parent = __zynq_clk_cpu_get_parent(srcsel);
+
+       /* cpu clocks */
+       clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
+       clks[cpu_6or4x_clk].parent = parent;
+       clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
+                       zynq_clk_get_rate(parent), div);
+       clks[cpu_6or4x_clk].name = "cpu_6or4x";
+
+       clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
+       clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
+       clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
+       clks[cpu_3or2x_clk].name = "cpu_3or2x";
+
+       clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
+       clks[cpu_2x_clk].parent = cpu_6or4x_clk;
+       clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+                       (2 + clk_621);
+       clks[cpu_2x_clk].name = "cpu_2x";
+
+       clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
+       clks[cpu_1x_clk].parent = cpu_6or4x_clk;
+       clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
+                       (4 + 2 * clk_621);
+       clks[cpu_1x_clk].name = "cpu_1x";
+}
+
+/**
+ * periph_calc_two_divs() - Calculate clock dividers
+ * @cur_rate:  Current clock rate
+ * @tgt_rate:  Target clock rate
+ * @prate:     Parent clock rate
+ * @div0:      First divider (output)
+ * @div1:      Second divider (output)
+ * Returns the actual clock rate possible.
+ *
+ * Calculates clock dividers for clocks with two 6-bit dividers.
+ */
+static unsigned long periph_calc_two_divs(unsigned long cur_rate,
+               unsigned long tgt_rate, unsigned long prate, u32 *div0,
+               u32 *div1)
+{
+       long err, best_err = (long)(~0UL >> 1);
+       unsigned long rate, best_rate = 0;
+       u32 d0, d1;
+
+       for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
+               for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
+                       rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
+                                       d1);
+                       err = abs(rate - tgt_rate);
+
+                       if (err < best_err) {
+                               *div0 = d0;
+                               *div1 = d1;
+                               best_err = err;
+                               best_rate = rate;
+                       }
+               }
+       }
+
+       return best_rate;
+}
+
+/**
+ * zynq_clk_periph_set_rate() - Set clock rate
+ * @clk:       Handle of the peripheral clock
+ * @rate:      New clock rate
+ * Sets the clock frequency of @clk to @rate. Returns zero on success.
+ */
+static int zynq_clk_periph_set_rate(struct clk *clk,
+               unsigned long rate)
+{
+       u32 ctrl, div0 = 0, div1 = 0;
+       unsigned long prate, new_rate, cur_rate = clk->frequency;
+
+       ctrl = readl(clk->reg);
+       prate = zynq_clk_get_rate(clk->parent);
+       ctrl &= ~CLK_CTRL_DIV0_MASK;
+
+       if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
+               ctrl &= ~CLK_CTRL_DIV1_MASK;
+               new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
+                               &div1);
+               ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
+       } else {
+               div0 = DIV_ROUND_CLOSEST(prate, rate);
+               div0 &= ZYNQ_CLK_MAXDIV;
+               new_rate = DIV_ROUND_CLOSEST(rate, div0);
+       }
+
+       /* write new divs to hardware */
+       ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
+       writel(ctrl, clk->reg);
+
+       /* update frequency in clk framework */
+       clk->frequency = new_rate;
+
+       return 0;
+}
+
+/**
+ * zynq_clk_periph_get_rate() - Get clock rate
+ * @clk:       Handle of the peripheral clock
+ * Returns the current clock rate of @clk.
+ */
+static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
+{
+       u32 clk_ctrl = readl(clk->reg);
+       u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+       u32 div1 = 1;
+
+       if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
+               div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
+
+       /* a register value of zero == division by 1 */
+       if (!div0)
+               div0 = 1;
+       if (!div1)
+               div1 = 1;
+
+       return
+               DIV_ROUND_CLOSEST(
+                       DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
+                       div1);
+}
+
+/**
+ * __zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @srcsel:    Mux select value
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
+{
+       switch (srcsel) {
+       case ZYNQ_CLKMUX_SEL_0:
+       case ZYNQ_CLKMUX_SEL_1:
+               return iopll_clk;
+       case ZYNQ_CLKMUX_SEL_2:
+               return armpll_clk;
+       case ZYNQ_CLKMUX_SEL_3:
+               return ddrpll_clk;
+       default:
+               return 0;
+       }
+}
+
+/**
+ * zynq_clk_periph_get_parent() - Decode clock multiplexer
+ * @clk:       Clock handle
+ * Returns the clock identifier associated with the selected mux input.
+ */
+static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
+{
+       u32 clk_ctrl = readl(clk->reg);
+       u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+
+       return __zynq_clk_periph_get_parent(srcsel);
+}
+
+/**
+ * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
+ * @clk:       Pointer to struct clk for the clock
+ * @ctrl:      Clock control register
+ * @name:      PLL name
+ * @two_divs:  Indicates whether the clock features one or two dividers
+ */
+static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
+               bool two_divs)
+{
+       clk->name = name;
+       clk->reg = ctrl;
+       if (two_divs)
+               clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
+       clk->parent = zynq_clk_periph_get_parent(clk);
+       clk->frequency = zynq_clk_periph_get_rate(clk);
+       clk->ops.get_rate = zynq_clk_periph_get_rate;
+       clk->ops.set_rate = zynq_clk_periph_set_rate;
+
+       return 0;
+}
+
+static void init_periph_clocks(void)
+{
+       zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
+                                    "gem0", 1);
+       zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
+                                    "gem1", 1);
+
+       zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
+                                    "smc", 0);
+
+       zynq_clk_register_periph_clk(&clks[lqspi_clk],
+                                    &slcr_base->lqspi_clk_ctrl, "lqspi", 0);
+
+       zynq_clk_register_periph_clk(&clks[sdio0_clk],
+                                    &slcr_base->sdio_clk_ctrl, "sdio0", 0);
+       zynq_clk_register_periph_clk(&clks[sdio1_clk],
+                                    &slcr_base->sdio_clk_ctrl, "sdio1", 0);
+
+       zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
+                                    "spi0", 0);
+       zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
+                                    "spi1", 0);
+
+       zynq_clk_register_periph_clk(&clks[uart0_clk],
+                                    &slcr_base->uart_clk_ctrl, "uart0", 0);
+       zynq_clk_register_periph_clk(&clks[uart1_clk],
+                                    &slcr_base->uart_clk_ctrl, "uart1", 0);
+
+       zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
+                                    &slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
+       zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
+                                    &slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
+
+       zynq_clk_register_periph_clk(&clks[pcap_clk],
+                                    &slcr_base->pcap_clk_ctrl, "pcap", 0);
+
+       zynq_clk_register_periph_clk(&clks[fclk0_clk],
+                                    &slcr_base->fpga0_clk_ctrl, "fclk0", 1);
+       zynq_clk_register_periph_clk(&clks[fclk1_clk],
+                                    &slcr_base->fpga1_clk_ctrl, "fclk1", 1);
+       zynq_clk_register_periph_clk(&clks[fclk2_clk],
+                                    &slcr_base->fpga2_clk_ctrl, "fclk2", 1);
+       zynq_clk_register_periph_clk(&clks[fclk3_clk],
+                                    &slcr_base->fpga3_clk_ctrl, "fclk3", 1);
+}
+
+/**
+ * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
+ * @clk:       Pointer to struct clk for the clock
+ * @ctrl:      Clock control register
+ * @name:      PLL name
+ */
+static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
+{
+       clk->name = name;
+       clk->reg = ctrl;
+       clk->parent = cpu_1x_clk;
+       clk->frequency = zynq_clk_get_rate(clk->parent);
+}
+
+static void init_aper_clocks(void)
+{
+       zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "usb0_aper");
+       zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "usb1_aper");
+
+       zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "gem0_aper");
+       zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "gem1_aper");
+
+       zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "sdio0_aper");
+       zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "sdio1_aper");
+
+       zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "spi0_aper");
+       zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "spi1_aper");
+
+       zynq_clk_register_aper_clk(&clks[can0_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "can0_aper");
+       zynq_clk_register_aper_clk(&clks[can1_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "can1_aper");
+
+       zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "i2c0_aper");
+       zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "i2c1_aper");
+
+       zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "uart0_aper");
+       zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "uart1_aper");
+
+       zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "gpio_aper");
+
+       zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "lqspi_aper");
+
+       zynq_clk_register_aper_clk(&clks[smc_aper_clk],
+                                  &slcr_base->aper_clk_ctrl, "smc_aper");
+}
+
+/**
+ * __zynq_clk_pll_get_rate() - Get PLL rate
+ * @addr:      Address of the PLL's control register
+ * Returns the current PLL output rate.
+ */
+static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
+{
+       u32 reg, mul, bypass;
+
+       reg = readl(addr);
+       bypass = reg & PLLCTRL_BPFORCE_MASK;
+       if (bypass)
+               mul = 1;
+       else
+               mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
+
+       return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
+}
+
+/**
+ * zynq_clk_pll_get_rate() - Get PLL rate
+ * @pll:       Handle of the PLL
+ * Returns the current clock rate of @pll.
+ */
+static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
+{
+       return __zynq_clk_pll_get_rate(pll->reg);
+}
+
+/**
+ * zynq_clk_register_pll() - Set up a PLL with the framework
+ * @clk:       Pointer to struct clk for the PLL
+ * @ctrl:      PLL control register
+ * @name:      PLL name
+ * @prate:     PLL input clock rate
+ */
+static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
+               unsigned long prate)
+{
+       clk->name = name;
+       clk->reg = ctrl;
+       clk->frequency = zynq_clk_pll_get_rate(clk);
+       clk->ops.get_rate = zynq_clk_pll_get_rate;
+}
+
+/**
+ * clkid_2_register() - Get clock control register
+ * @id:        Clock identifier of one of the PLLs
+ * Returns the address of the requested PLL's control register.
+ */
+static u32 *clkid_2_register(enum zynq_clk id)
+{
+       switch (id) {
+       case armpll_clk:
+               return &slcr_base->arm_pll_ctrl;
+       case ddrpll_clk:
+               return &slcr_base->ddr_pll_ctrl;
+       case iopll_clk:
+               return &slcr_base->io_pll_ctrl;
+       default:
+               return &slcr_base->io_pll_ctrl;
+       }
+}
+
+/* API */
+/**
+ * zynq_clk_early_init() - Early init for the clock framework
+ *
+ * This function is called from before relocation and sets up the CPU clock
+ * frequency in the global data struct.
+ */
+void zynq_clk_early_init(void)
+{
+       u32 reg = readl(&slcr_base->arm_clk_ctrl);
+       u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+       u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+       enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
+       u32 *pllreg = clkid_2_register(parent);
+       unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+       if (!div)
+               div = 1;
+
+       gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * get_uart_clk() - Get UART input frequency
+ * @dev_index: UART ID
+ * Returns UART input clock frequency in Hz.
+ *
+ * Compared to zynq_clk_get_rate() this function is designed to work before
+ * relocation and can be called when the serial UART is set up.
+ */
+unsigned long get_uart_clk(int dev_index)
+{
+       u32 reg = readl(&slcr_base->uart_clk_ctrl);
+       u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
+       u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
+       enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
+       u32 *pllreg = clkid_2_register(parent);
+       unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
+
+       if (!div)
+               div = 1;
+
+       return DIV_ROUND_CLOSEST(prate, div);
+}
+
+/**
+ * set_cpu_clk_info() - Initialize clock framework
+ * Always returns zero.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+       zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
+                             "armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+       zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
+                             "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
+       zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
+                             "iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
+
+       init_ddr_clocks();
+       init_cpu_clocks();
+       init_periph_clocks();
+       init_aper_clocks();
+
+       gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+       gd->bd->bi_dsp_freq = 0;
+
+       return 0;
+}
+
+/**
+ * zynq_clk_get_rate() - Get clock rate
+ * @clk:       Clock identifier
+ * Returns the current clock rate of @clk on success or zero for an invalid
+ * clock id.
+ */
+unsigned long zynq_clk_get_rate(enum zynq_clk clk)
+{
+       if (clk < 0 || clk >= clk_max)
+               return 0;
+
+       return clks[clk].frequency;
+}
+
+/**
+ * zynq_clk_set_rate() - Set clock rate
+ * @clk:       Clock identifier
+ * @rate:      Requested clock rate
+ * Passes on the return value from the clock's set_rate() function or negative
+ * errno.
+ */
+int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
+{
+       if (clk < 0 || clk >= clk_max)
+               return -ENODEV;
+
+       if (clks[clk].ops.set_rate)
+               return clks[clk].ops.set_rate(&clks[clk], rate);
+
+       return -ENXIO;
+}
+
+/**
+ * zynq_clk_get_name() - Get clock name
+ * @clk:       Clock identifier
+ * Returns the name of @clk.
+ */
+const char *zynq_clk_get_name(enum zynq_clk clk)
+{
+       return clks[clk].name;
+}
+
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+       int i;
+
+       printf("clk\t\tfrequency\n");
+       for (i = 0; i < clk_max; i++) {
+               const char *name = zynq_clk_get_name(i);
+               if (name)
+                       printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
+       }
+
+       return 0;
+}
index 9af340e..7626b5c 100644 (file)
@@ -6,6 +6,7 @@
  */
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/hardware.h>
 
@@ -16,7 +17,7 @@ void lowlevel_init(void)
 int arch_cpu_init(void)
 {
        zynq_slcr_unlock();
-
+#ifndef CONFIG_SPL_BUILD
        /* Device config APB, unlock the PCAP */
        writel(0x757BDF0D, &devcfg_base->unlock);
        writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
@@ -34,7 +35,8 @@ int arch_cpu_init(void)
        /* Urgent write, ports S2/S3 */
        writel(0xC, &slcr_base->ddr_urgent);
 #endif
-
+#endif
+       zynq_clk_early_init();
        zynq_slcr_lock();
 
        return 0;
@@ -46,3 +48,11 @@ void reset_cpu(ulong addr)
        while (1)
                ;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+       /* Enable D-cache. I-cache is already enabled in start.S */
+       dcache_enable();
+}
+#endif
index b4c11c3..d7c1882 100644 (file)
@@ -8,6 +8,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
 
 #define SLCR_LOCK_MAGIC                0x767B
 #define SLCR_UNLOCK_MAGIC      0xDF0D
@@ -50,8 +51,10 @@ void zynq_slcr_cpu_reset(void)
 }
 
 /* Setup clk for network */
-void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
+void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
 {
+       int ret;
+
        zynq_slcr_unlock();
 
        if (gem_id > 1) {
@@ -59,16 +62,16 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk)
                goto out;
        }
 
+       ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate);
+       if (ret)
+               goto out;
+
        if (gem_id) {
-               /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
-               writel(clk, &slcr_base->gem1_clk_ctrl);
                /* Configure GEM_RCLK_CTRL */
-               writel(rclk, &slcr_base->gem1_rclk_ctrl);
+               writel(1, &slcr_base->gem1_rclk_ctrl);
        } else {
-               /* Set divisors for appropriate frequency in GEM_CLK_CTRL */
-               writel(clk, &slcr_base->gem0_clk_ctrl);
                /* Configure GEM_RCLK_CTRL */
-               writel(rclk, &slcr_base->gem0_rclk_ctrl);
+               writel(1, &slcr_base->gem0_rclk_ctrl);
        }
        udelay(100000);
 out:
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c
new file mode 100644 (file)
index 0000000..fcad762
--- /dev/null
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2014 Xilinx, Inc. Michal Simek
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spl.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong dummy)
+{
+       ps7_init();
+
+       /* Clear the BSS. */
+       memset(__bss_start, 0, __bss_end - __bss_start);
+
+       /* Set global data pointer. */
+       gd = &gdata;
+
+       preloader_console_init();
+       arch_cpu_init();
+       board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+       u32 mode;
+
+       switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
+#ifdef CONFIG_SPL_SPI_SUPPORT
+       case ZYNQ_BM_QSPI:
+               puts("qspi boot\n");
+               mode = BOOT_DEVICE_SPI;
+               break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+       case ZYNQ_BM_SD:
+               puts("mmc boot\n");
+               mode = BOOT_DEVICE_MMC1;
+               break;
+#endif
+       default:
+               puts("Unsupported boot mode selected\n");
+               hang();
+       }
+
+       return mode;
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+       return MMCSD_MODE_FAT;
+}
+#endif
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+       /* boot linux */
+       return 0;
+}
+#endif
index 2be253c..303dbcf 100644 (file)
@@ -29,6 +29,7 @@
 #include <div64.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,7 +49,6 @@ static struct scu_timer *timer_base =
 
 #define TIMER_LOAD_VAL 0xFFFFFFFF
 #define TIMER_PRESCALE 255
-#define TIMER_TICK_HZ  (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE)
 
 int timer_init(void)
 {
@@ -56,6 +56,8 @@ int timer_init(void)
                        (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) |
                        SCUTIMER_CONTROL_ENABLE_MASK;
 
+       gd->arch.timer_rate_hz = (gd->cpu_clk / 2) / (TIMER_PRESCALE + 1);
+
        /* Load the timer counter register */
        writel(0xFFFFFFFF, &timer_base->load);
 
@@ -69,7 +71,7 @@ int timer_init(void)
 
        /* Reset time */
        gd->arch.lastinc = readl(&timer_base->counter) /
-                                       (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+                               (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
        gd->arch.tbl = 0;
 
        return 0;
@@ -83,14 +85,15 @@ ulong get_timer_masked(void)
 {
        ulong now;
 
-       now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ);
+       now = readl(&timer_base->counter) /
+                       (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
 
        if (gd->arch.lastinc >= now) {
                /* Normal mode */
                gd->arch.tbl += gd->arch.lastinc - now;
        } else {
                /* We have an overflow ... */
-               gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now;
+               gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1;
        }
        gd->arch.lastinc = now;
 
@@ -107,7 +110,8 @@ void __udelay(unsigned long usec)
        if (usec == 0)
                return;
 
-       countticks = lldiv(TIMER_TICK_HZ * usec, 1000000);
+       countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
+                          1000000);
 
        /* decrementing timer */
        timeend = readl(&timer_base->counter) - countticks;
diff --git a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
new file mode 100644 (file)
index 0000000..0c4501e
--- /dev/null
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2014 Xilinx, Inc. Michal Simek
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+               LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+               LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = ALIGN(4);
+       .text :
+       {
+               __image_copy_start = .;
+               CPUDIR/start.o (.text*)
+               *(.text*)
+       } > .sram
+
+       . = ALIGN(4);
+       .rodata : {
+               *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+       } > .sram
+
+       . = ALIGN(4);
+       .data : {
+               *(.data*)
+       } > .sram
+
+       . = ALIGN(4);
+
+       . = .;
+
+       __image_copy_end = .;
+
+       _end = .;
+
+       /* Move BSS section to RAM because of FAT */
+       .bss (NOLOAD) : {
+               __bss_start = .;
+               *(.bss*)
+                . = ALIGN(4);
+               __bss_end = .;
+       } > .sdram
+
+       /DISCARD/ : { *(.dynsym) }
+       /DISCARD/ : { *(.dynstr*) }
+       /DISCARD/ : { *(.dynamic*) }
+       /DISCARD/ : { *(.plt*) }
+       /DISCARD/ : { *(.interp*) }
+       /DISCARD/ : { *(.gnu*) }
+}
similarity index 58%
rename from arch/arm/cpu/ixp/u-boot.lds
rename to arch/arm/cpu/armv7/zynq/u-boot.lds
index 676ae2c..a68b050 100644 (file)
@@ -1,11 +1,13 @@
 /*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
 OUTPUT_ARCH(arm)
 ENTRY(_start)
 SECTIONS
@@ -16,7 +18,7 @@ SECTIONS
        .text :
        {
                *(.__image_copy_start)
-               arch/arm/cpu/ixp/start.o(.text*)
+               CPUDIR/start.o (.text*)
                *(.text*)
        }
 
@@ -75,17 +77,23 @@ SECTIONS
                 . = ALIGN(4);
                 __bss_limit = .;
        }
+
        .bss_end __bss_limit (OVERLAY) : {
                KEEP(*(.__bss_end));
        }
 
-       .dynsym _end : { *(.dynsym) }
-       .dynbss : { *(.dynbss) }
-       .dynstr : { *(.dynstr*) }
-       .dynamic : { *(.dynamic*) }
-       .hash : { *(.hash*) }
-       .plt : { *(.plt*) }
-       .interp : { *(.interp*) }
-       .gnu : { *(.gnu*) }
-       .ARM.exidx : { *(.ARM.exidx*) }
+       /*
+        * Zynq needs to discard more sections because the user
+        * is expected to pass this image on to tools for boot.bin
+        * generation that require them to be dropped.
+        */
+       /DISCARD/ : { *(.dynsym) }
+       /DISCARD/ : { *(.dynbss*) }
+       /DISCARD/ : { *(.dynstr*) }
+       /DISCARD/ : { *(.dynamic*) }
+       /DISCARD/ : { *(.plt*) }
+       /DISCARD/ : { *(.interp*) }
+       /DISCARD/ : { *(.gnu*) }
+       /DISCARD/ : { *(.ARM.exidx*) }
+       /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
 }
diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile
deleted file mode 100644 (file)
index 4e66523..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-extra-y        = start.o
-
-obj-y  += cpu.o
-obj-$(CONFIG_USE_IRQ)  += interrupts.o
-obj-y  += timer.o
diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk
deleted file mode 100644 (file)
index 894861f..0000000
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-BIG_ENDIAN = y
-
-PLATFORM_RELFLAGS += -mbig-endian
-
-PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
-
-PLATFORM_LDFLAGS += -EB
-USE_PRIVATE_LIBGCC = yes
diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c
deleted file mode 100644 (file)
index 4387c18..0000000
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/arch/ixp425.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
-{
-       unsigned long id;
-       int speed = 0;
-
-       asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
-       puts("CPU:   Intel IXP425 at ");
-       switch ((id & 0x000003f0) >> 4) {
-       case 0x1c:
-               speed = 533;
-               break;
-
-       case 0x1d:
-               speed = 400;
-               break;
-
-       case 0x1f:
-               speed = 266;
-               break;
-       }
-
-       if (speed)
-               printf("%d MHz\n", speed);
-       else
-               puts("unknown revision\n");
-
-       return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-int cleanup_before_linux (void)
-{
-       /*
-        * this function is called just before we call linux
-        * it prepares the processor for linux
-        *
-        * just disable everything that can disturb booting linux
-        */
-
-       disable_interrupts ();
-
-       /* turn off I-cache */
-       icache_disable();
-       dcache_disable();
-
-       /* flush I-cache */
-       cache_flush();
-
-       return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-       unsigned long i = 0;
-
-       asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-/* FIXME */
-/*
-void pci_init(void)
-{
-       return;
-}
-*/
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_IXP4XX_NPE
-       npe_initialize(bis);
-#endif
-       return 0;
-}
diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c
deleted file mode 100644 (file)
index 7694c6a..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/proc-armv/ptrace.h>
-
-struct _irq_handler {
-       void                *m_data;
-       void (*m_func)( void *data);
-};
-
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-
-static void default_isr(void *data)
-{
-       printf("default_isr():  called for IRQ %d, Interrupt Status=%x PR=%x\n",
-              (int)data, *IXP425_ICIP, *IXP425_ICIH);
-}
-
-static int next_irq(void)
-{
-       return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
-}
-
-void do_irq (struct pt_regs *pt_regs)
-{
-       int irq = next_irq();
-
-       IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
-}
-
-void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
-{
-       if (irq >= N_IRQS || !handle_irq)
-               return;
-
-       IRQ_HANDLER[irq].m_data = data;
-       IRQ_HANDLER[irq].m_func = handle_irq;
-}
-
-int arch_interrupt_init (void)
-{
-       int i;
-
-       /* install default interrupt handlers */
-       for (i = 0; i < N_IRQS; i++)
-               irq_install_handler(i, default_isr, (void *)i);
-
-       /* configure interrupts for IRQ mode */
-       *IXP425_ICLR = 0x00000000;
-
-       return (0);
-}
diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S
deleted file mode 100644 (file)
index 82c868a..0000000
+++ /dev/null
@@ -1,430 +0,0 @@
-/* vi: set ts=8 sw=8 noet: */
-/*
- *  u-boot - Startup Code for XScale IXP
- *
- * Copyright (C) 2003  Kyle Harris <kharris@nexus-tech.net>
- *
- * Based on startup code example contained in the
- * Intel IXP4xx Programmer's Guide and past u-boot Start.S
- * samples.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-#include <asm/arch/ixp425.h>
-
-#define MMU_Control_M  0x001    /* Enable MMU */
-#define MMU_Control_A  0x002    /* Enable address alignment faults */
-#define MMU_Control_C  0x004    /* Enable cache */
-#define MMU_Control_W  0x008    /* Enable write-buffer */
-#define MMU_Control_P  0x010    /* Compatability: 32 bit code */
-#define MMU_Control_D  0x020    /* Compatability: 32 bit data */
-#define MMU_Control_L  0x040    /* Compatability: */
-#define MMU_Control_B  0x080    /* Enable Big-Endian */
-#define MMU_Control_S  0x100    /* Enable system protection */
-#define MMU_Control_R  0x200    /* Enable ROM protection */
-#define MMU_Control_I  0x1000   /* Enable Instruction cache */
-#define MMU_Control_X  0x2000   /* Set interrupt vectors at 0xFFFF0000 */
-#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
-
-
-/*
- * Macro definitions
- */
-       /* Delay a bit */
-       .macro DELAY_FOR cycles, reg0
-       ldr     \reg0, =\cycles
-       subs    \reg0, \reg0, #1
-       subne   pc,  pc, #0xc
-       .endm
-
-       /* wait for coprocessor write complete */
-       .macro CPWAIT reg
-       mrc  p15,0,\reg,c2,c0,0
-       mov  \reg,\reg
-       sub  pc,pc,#4
-       .endm
-
-.globl _start
-_start:
-       ldr     pc, _reset
-       ldr     pc, _undefined_instruction
-       ldr     pc, _software_interrupt
-       ldr     pc, _prefetch_abort
-       ldr     pc, _data_abort
-       ldr     pc, _not_used
-       ldr     pc, _irq
-       ldr     pc, _fiq
-
-_reset:                 .word reset
-_undefined_instruction: .word undefined_instruction
-_software_interrupt:   .word software_interrupt
-_prefetch_abort:       .word prefetch_abort
-_data_abort:           .word data_abort
-_not_used:             .word not_used
-_irq:                  .word irq
-_fiq:                  .word fiq
-
-       .balignl 16,0xdeadbeef
-
-
-/*
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * - relocate armboot to ram
- * - setup stack
- * - jump to second stage
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-       .word   CONFIG_SPL_TEXT_BASE
-#else
-       .word   CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-       .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-       .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-       .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-       .word   0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-       .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-       .word   0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-       /* disable mmu, set big-endian */
-       mov     r0, #0xf8
-       mcr     p15, 0, r0, c1, c0, 0
-       CPWAIT  r0
-
-       /* invalidate I & D caches & BTB */
-       mcr     p15, 0, r0, c7, c7, 0
-       CPWAIT  r0
-
-       /* invalidate I & Data TLB */
-       mcr     p15, 0, r0, c8, c7, 0
-       CPWAIT r0
-
-       /* drain write and fill buffers */
-       mcr     p15, 0, r0, c7, c10, 4
-       CPWAIT  r0
-
-       /* disable write buffer coalescing */
-       mrc     p15, 0, r0, c1, c0, 1
-       orr     r0, r0, #1
-       mcr     p15, 0, r0, c1, c0, 1
-       CPWAIT  r0
-
-       /* set EXP CS0 to the optimum timing */
-       ldr     r1, =CONFIG_SYS_EXP_CS0
-       ldr     r2, =IXP425_EXP_CS0
-       str     r1, [r2]
-
-       /* make sure flash is visible at 0 */
-       mov     r1, #CONFIG_SYS_SDR_CONFIG
-       ldr     r2, =IXP425_SDR_CONFIG
-       str     r1, [r2]
-
-       /* disable refresh cycles */
-       mov     r1, #0
-       ldr     r3, =IXP425_SDR_REFRESH
-       str     r1, [r3]
-
-       /* send nop command */
-       mov     r1, #3
-       ldr     r4, =IXP425_SDR_IR
-       str     r1, [r4]
-       DELAY_FOR 0x4000, r0
-
-       /* set SDRAM internal refresh val */
-       ldr     r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
-       str     r1, [r3]
-       DELAY_FOR 0x4000, r0
-
-       /* send precharge-all command to close all open banks */
-       mov     r1, #2
-       str     r1, [r4]
-       DELAY_FOR 0x4000, r0
-
-       /* provide 8 auto-refresh cycles */
-       mov     r1, #4
-       mov     r5, #8
-111:    str    r1, [r4]
-       DELAY_FOR 0x100, r0
-       subs    r5, r5, #1
-       bne     111b
-
-       /* set mode register in sdram */
-       mov     r1, #CONFIG_SYS_SDR_MODE_CONFIG
-       str     r1, [r4]
-       DELAY_FOR 0x4000, r0
-
-       /* send normal operation command */
-       mov     r1, #6
-       str     r1, [r4]
-       DELAY_FOR 0x4000, r0
-
-       /* invalidate I & D caches & BTB */
-       mcr     p15, 0, r0, c7, c7, 0
-       CPWAIT  r0
-
-       /* invalidate I & Data TLB */
-       mcr     p15, 0, r0, c8, c7, 0
-       CPWAIT r0
-
-       /* drain write and fill buffers */
-       mcr     p15, 0, r0, c7, c10, 4
-       CPWAIT  r0
-
-       /* remove flash mirror at 0x00000000 */
-       ldr     r2, =IXP425_EXP_CFG0
-       ldr     r1, [r2]
-       bic     r1, r1, #0x80000000
-       str     r1, [r2]
-
-       /* invalidate I & Data TLB */
-       mcr     p15, 0, r0, c8, c7, 0
-       CPWAIT r0
-
-       /* enable I cache */
-       mrc     p15, 0, r0, c1, c0, 0
-       orr     r0, r0, #MMU_Control_I
-       mcr     p15, 0, r0, c1, c0, 0
-       CPWAIT  r0
-
-       mrs     r0,cpsr                 /* set the cpu to SVC32 mode        */
-       bic     r0,r0,#0x1f             /* (superviser mode, M=10011)       */
-       orr     r0,r0,#0x13
-       msr     cpsr,r0
-
-       bl      _main
-
-/*------------------------------------------------------------------------------*/
-
-       .globl  c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-       bx      lr
-
-/****************************************************************************/
-/*                                                                         */
-/* Interrupt handling                                                      */
-/*                                                                         */
-/****************************************************************************/
-
-/* IRQ stack frame                                                         */
-
-#define S_FRAME_SIZE   72
-
-#define S_OLD_R0       68
-#define S_PSR          64
-#define S_PC           60
-#define S_LR           56
-#define S_SP           52
-
-#define S_IP           48
-#define S_FP           44
-#define S_R10          40
-#define S_R9           36
-#define S_R8           32
-#define S_R7           28
-#define S_R6           24
-#define S_R5           20
-#define S_R4           16
-#define S_R3           12
-#define S_R2           8
-#define S_R1           4
-#define S_R0           0
-
-#define MODE_SVC 0x13
-
-       /* use bad_save_user_regs for abort/prefetch/undef/swi ...          */
-
-       .macro  bad_save_user_regs
-       sub     sp, sp, #S_FRAME_SIZE
-       stmia   sp, {r0 - r12}                  /* Calling r0-r12           */
-       add     r8, sp, #S_PC
-
-       ldr     r2, IRQ_STACK_START_IN
-       ldmia   r2, {r2 - r4}                   /* get pc, cpsr, old_r0     */
-       add     r0, sp, #S_FRAME_SIZE           /* restore sp_SVC           */
-
-       add     r5, sp, #S_SP
-       mov     r1, lr
-       stmia   r5, {r0 - r4}                   /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
-       mov     r0, sp
-       .endm
-
-
-       /* use irq_save_user_regs / irq_restore_user_regs for                */
-       /* IRQ/FIQ handling                                                  */
-
-       .macro  irq_save_user_regs
-       sub     sp, sp, #S_FRAME_SIZE
-       stmia   sp, {r0 - r12}                  /* Calling r0-r12            */
-       add     r8, sp, #S_PC
-       stmdb   r8, {sp, lr}^                   /* Calling SP, LR            */
-       str     lr, [r8, #0]                    /* Save calling PC           */
-       mrs     r6, spsr
-       str     r6, [r8, #4]                    /* Save CPSR                 */
-       str     r0, [r8, #8]                    /* Save OLD_R0               */
-       mov     r0, sp
-       .endm
-
-       .macro  irq_restore_user_regs
-       ldmia   sp, {r0 - lr}^                  @ Calling r0 - lr
-       mov     r0, r0
-       ldr     lr, [sp, #S_PC]                 @ Get PC
-       add     sp, sp, #S_FRAME_SIZE
-       subs    pc, lr, #4                      @ return & move spsr_svc into cpsr
-       .endm
-
-       .macro get_bad_stack
-       ldr     r13, IRQ_STACK_START_IN         @ setup our mode stack
-
-       str     lr, [r13]                       @ save caller lr / spsr
-       mrs     lr, spsr
-       str     lr, [r13, #4]
-
-       mov     r13, #MODE_SVC                  @ prepare SVC-Mode
-       msr     spsr_c, r13
-       mov     lr, pc
-       movs    pc, lr
-       .endm
-
-       .macro get_irq_stack                    @ setup IRQ stack
-       ldr     sp, IRQ_STACK_START
-       .endm
-
-       .macro get_fiq_stack                    @ setup FIQ stack
-       ldr     sp, FIQ_STACK_START
-       .endm
-
-
-/****************************************************************************/
-/*                                                                         */
-/* exception handlers                                                      */
-/*                                                                         */
-/****************************************************************************/
-
-       .align  5
-undefined_instruction:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_undefined_instruction
-
-       .align  5
-software_interrupt:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_software_interrupt
-
-       .align  5
-prefetch_abort:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_prefetch_abort
-
-       .align  5
-data_abort:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_data_abort
-
-       .align  5
-not_used:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-       .align  5
-irq:
-       get_irq_stack
-       irq_save_user_regs
-       bl      do_irq
-       irq_restore_user_regs
-
-       .align  5
-fiq:
-       get_fiq_stack
-       irq_save_user_regs              /* someone ought to write a more    */
-       bl      do_fiq                  /* effiction fiq_save_user_regs     */
-       irq_restore_user_regs
-
-#else
-
-       .align  5
-irq:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_irq
-
-       .align  5
-fiq:
-       get_bad_stack
-       bad_save_user_regs
-       bl      do_fiq
-
-#endif
-
-/****************************************************************************/
-/*                                                                          */
-/* Reset function: Use Watchdog to reset                                    */
-/*                                                                          */
-/****************************************************************************/
-
-       .align  5
-.globl reset_cpu
-
-reset_cpu:
-       ldr     r1, =0x482e
-       ldr     r2, =IXP425_OSWK
-       str     r1, [r2]
-       ldr     r1, =0x0fff
-       ldr     r2, =IXP425_OSWT
-       str     r1, [r2]
-       ldr     r1, =0x5
-       ldr     r2, =IXP425_OSWE
-       str     r1, [r2]
-       b       reset_endless
-
-reset_endless:
-       b       reset_endless
diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c
deleted file mode 100644 (file)
index 38e2e28..0000000
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * (C) Copyright 2010
- * Michael Schwingen, michael@schwingen.org
- *
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/ixp425.h>
-#include <asm/io.h>
-#include <div64.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a
- * 33.333MHz crystal).
- */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-       tick *= CONFIG_SYS_HZ;
-       do_div(tick, CONFIG_IXP425_TIMER_CLK);
-       return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-       time *= CONFIG_IXP425_TIMER_CLK;
-       do_div(time, CONFIG_SYS_HZ);
-       return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-       us = us * CONFIG_IXP425_TIMER_CLK + 999999;
-       do_div(us, 1000000);
-       return us;
-}
-
-unsigned long long get_ticks(void)
-{
-       ulong now = readl(IXP425_OSTS_B);
-
-       if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) {
-               /* rollover of timestamp timer register */
-               gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1;
-               writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
-       } else {
-               /* move stamp forward with absolut diff ticks */
-               gd->arch.timestamp += (now - gd->arch.lastinc);
-       }
-       gd->arch.lastinc = now;
-       return gd->arch.timestamp;
-}
-
-
-void reset_timer_masked(void)
-{
-       /* capture current timestamp counter */
-       gd->arch.lastinc = readl(IXP425_OSTS_B);
-       /* start "advancing" time stamp from 0 */
-       gd->arch.timestamp = 0;
-}
-
-ulong get_timer_masked(void)
-{
-       return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-       return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-       unsigned long long tmp;
-
-       tmp = get_ticks() + us_to_tick(usec);
-
-       while (get_ticks() < tmp)
-               ;
-}
-
-int timer_init(void)
-{
-       writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST);
-       return 0;
-}
index 60d71a6..91d70da 100644 (file)
@@ -1,5 +1,5 @@
 /*
-* (C) Copyright 2010-2011
+* (C) Copyright 2010-2014
 * NVIDIA Corporation <www.nvidia.com>
 *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -27,7 +27,7 @@ int tegra_get_chip(void)
        /*
         * This is undocumented, Chip ID is bits 15:8 of the register
         * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
-        * Tegra30, and 0x35 for T114.
+        * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
         */
        rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
        debug("%s: CHIPID is 0x%02X\n", __func__, rev);
@@ -72,6 +72,7 @@ int tegra_get_chip_sku(void)
                case SKU_ID_T33:
                case SKU_ID_T30:
                case SKU_ID_TM30MQS_P_A3:
+               default:
                        return TEGRA_SOC_T30;
                }
                break;
@@ -79,10 +80,19 @@ int tegra_get_chip_sku(void)
                switch (sku_id) {
                case SKU_ID_T114_ENG:
                case SKU_ID_T114_1:
+               default:
                        return TEGRA_SOC_T114;
                }
                break;
+       case CHIPID_TEGRA124:
+               switch (sku_id) {
+               case SKU_ID_T124_ENG:
+               default:
+                       return TEGRA_SOC_T124;
+               }
+               break;
        }
+
        /* unknown chip/sku id */
        printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
                __func__, chip_id, sku_id);
@@ -117,8 +127,8 @@ static u32 get_odmdata(void)
         * ODMDATA is stored in the BCT in IRAM by the BootROM.
         * The BCT start and size are stored in the BIT in IRAM.
         * Read the data @ bct_start + (bct_size - 12). This works
-        * on T20 and T30 BCTs, which are locked down. If this changes
-        * in new chips (T114, etc.), we can revisit this algorithm.
+        * on BCTs for currently supported SoCs, which are locked down.
+        * If this changes in new chips, we can revisit this algorithm.
         */
 
        u32 bct_start, odmdata;
index d9cbda8..6a6faf4 100644 (file)
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011
+ *  (C) Copyright 2010-2014
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -109,12 +109,18 @@ static int uart_configs[] = {
        -1,
        -1,
        -1,
-#else  /* Tegra114 */
+#elif defined(CONFIG_TEGRA114)
        -1,
        -1,
        -1,
        FUNCMUX_UART4_GMI,      /* UARTD */
        -1,
+#else  /* Tegra124 */
+       FUNCMUX_UART1_KBC,      /* UARTA */
+       -1,
+       -1,
+       FUNCMUX_UART4_GPIO,     /* UARTD */
+       -1,
 #endif
 };
 
index 48e9319..94f5bce 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -23,8 +23,6 @@
 
 void config_cache(void)
 {
-       struct apb_misc_gp_ctlr *gp =
-               (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
        u32 reg = 0;
 
        /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
@@ -33,10 +31,10 @@ void config_cache(void)
                "orr r0, r0, #0x41\n"
                "mcr p15, 0, r0, c1, c0, 1\n");
 
-       /* Currently, only T114 needs this L2 cache change to boot Linux */
-       reg = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK);
-       if (reg != (CHIPID_TEGRA114 << HIDREV_CHIPID_SHIFT))
+       /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
+       if (tegra_get_chip() < CHIPID_TEGRA114)
                return;
+
        /*
         * Systems with an architectural L2 cache must not use the PL310.
         * Config L2CTLR here for a data RAM latency of 3 cycles.
index 268fb91..11c7435 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -142,8 +142,8 @@ void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
 
        value = readl(reg);
 
-       value &= ~OUT_CLK_SOURCE_MASK;
-       value |= source << OUT_CLK_SOURCE_SHIFT;
+       value &= ~OUT_CLK_SOURCE_31_30_MASK;
+       value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
 
        value &= ~OUT_CLK_DIVISOR_MASK;
        value |= divisor << OUT_CLK_DIVISOR_SHIFT;
@@ -155,8 +155,8 @@ void clock_ll_set_source(enum periph_id periph_id, unsigned source)
 {
        u32 *reg = get_periph_source_reg(periph_id);
 
-       clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-                       source << OUT_CLK_SOURCE_SHIFT);
+       clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+                       source << OUT_CLK_SOURCE_31_30_SHIFT);
 }
 
 /**
@@ -304,13 +304,27 @@ static int adjust_periph_pll(enum periph_id periph_id, int source,
        /* work out the source clock and set it */
        if (source < 0)
                return -1;
-       if (mux_bits == 4) {
-               clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
-                       source << OUT_CLK_SOURCE4_SHIFT);
-       } else {
-               clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
-                       source << OUT_CLK_SOURCE_SHIFT);
+
+       switch (mux_bits) {
+       case MASK_BITS_31_30:
+               clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+                               source << OUT_CLK_SOURCE_31_30_SHIFT);
+               break;
+
+       case MASK_BITS_31_29:
+               clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+                               source << OUT_CLK_SOURCE_31_29_SHIFT);
+               break;
+
+       case MASK_BITS_31_28:
+               clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+                               source << OUT_CLK_SOURCE_31_28_SHIFT);
+               break;
+
+       default:
+               return -1;
        }
+
        udelay(2);
        return 0;
 }
@@ -561,3 +575,95 @@ void clock_init(void)
        /* Do any special system timer/TSC setup */
        arch_timer_init();
 }
+
+static void set_avp_clock_source(u32 src)
+{
+       struct clk_rst_ctlr *clkrst =
+                       (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 val;
+
+       val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
+               (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
+               (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
+               (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
+               (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
+       writel(val, &clkrst->crc_sclk_brst_pol);
+       udelay(3);
+}
+
+/*
+ * This function is useful on Tegra30, and any later SoCs that have compatible
+ * PLLP configuration registers.
+ */
+void tegra30_set_up_pllp(void)
+{
+       struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+       u32 reg;
+
+       /*
+        * Based on the Tegra TRM, the system clock (which is the AVP clock) can
+        * run up to 275MHz. On power on, the default sytem clock source is set
+        * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
+        * 408MHz which is beyond system clock's upper limit.
+        *
+        * The fix is to set the system clock to CLK_M before initializing PLLP,
+        * and then switch back to PLLP_OUT4, which has an appropriate divider
+        * configured, after PLLP has been configured
+        */
+       set_avp_clock_source(SCLK_SOURCE_CLKM);
+
+       /*
+        * PLLP output frequency set to 408Mhz
+        * PLLC output frequency set to 228Mhz
+        */
+       switch (clock_get_osc_freq()) {
+       case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
+               clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
+               clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
+               break;
+
+       case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
+               clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
+               clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
+               break;
+
+       case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
+               clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
+               clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
+               break;
+       case CLOCK_OSC_FREQ_19_2:
+       default:
+               /*
+                * These are not supported. It is too early to print a
+                * message and the UART likely won't work anyway due to the
+                * oscillator being wrong.
+                */
+               break;
+       }
+
+       /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
+
+       /* OUT1, 2 */
+       /* Assert RSTN before enable */
+       reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
+       writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+       /* Set divisor and reenable */
+       reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
+               | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
+               | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
+               | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
+       writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
+
+       /* OUT3, 4 */
+       /* Assert RSTN before enable */
+       reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
+       writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+       /* Set divisor and reenable */
+       reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
+               | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
+               | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
+               | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
+       writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
+
+       set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
+}
index 5c4305a..d5194e1 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -61,12 +61,6 @@ enum {
        CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
 };
 
-enum {
-       MASK_BITS_31_30 = 2,    /* num of bits used to specify clock source */
-       MASK_BITS_31_29,
-       MASK_BITS_29_28,
-};
-
 /*
  * Clock source mux for each clock type. This just converts our enum into
  * a list of mux sources for use by the code.
@@ -109,7 +103,7 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
                MASK_BITS_31_29},
        { CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ),        CLK(OSC),
                CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
-               MASK_BITS_29_28}
+               MASK_BITS_31_28}
 };
 
 /*
@@ -610,26 +604,24 @@ void clock_early_init(void)
        struct clk_rst_ctlr *clkrst =
                (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 
+       tegra30_set_up_pllp();
+
        /*
-        * PLLP output frequency set to 408Mhz
         * PLLC output frequency set to 600Mhz
         * PLLD output frequency set to 925Mhz
         */
        switch (clock_get_osc_freq()) {
        case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
-               clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
                clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
                clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
                break;
 
        case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
-               clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
                clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
                clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
                break;
 
        case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
-               clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
                clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
                clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
                break;
diff --git a/arch/arm/cpu/tegra124-common/Makefile b/arch/arm/cpu/tegra124-common/Makefile
new file mode 100644 (file)
index 0000000..ff77992
--- /dev/null
@@ -0,0 +1,10 @@
+#
+# (C) Copyright 2013-2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += clock.o
+obj-y  += funcmux.o
+obj-y  += pinmux.o
diff --git a/arch/arm/cpu/tegra124-common/clock.c b/arch/arm/cpu/tegra124-common/clock.c
new file mode 100644 (file)
index 0000000..7394363
--- /dev/null
@@ -0,0 +1,826 @@
+/*
+ * (C) Copyright 2013
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* Tegra124 Clock control functions */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sysctr.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
+#include <div64.h>
+#include <fdtdec.h>
+
+/*
+ * Clock types that we can use as a source. The Tegra124 has muxes for the
+ * peripheral clocks, and in most cases there are four options for the clock
+ * source. This gives us a clock 'type' and exploits what commonality exists
+ * in the device.
+ *
+ * Letters are obvious, except for T which means CLK_M, and S which means the
+ * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
+ * datasheet) and PLL_M are different things. The former is the basic
+ * clock supplied to the SOC from an external oscillator. The latter is the
+ * memory clock PLL.
+ *
+ * See definitions in clock_id in the header file.
+ */
+enum clock_type_id {
+       CLOCK_TYPE_AXPT,        /* PLL_A, PLL_X, PLL_P, CLK_M */
+       CLOCK_TYPE_MCPA,        /* and so on */
+       CLOCK_TYPE_MCPT,
+       CLOCK_TYPE_PCM,
+       CLOCK_TYPE_PCMT,
+       CLOCK_TYPE_PDCT,
+       CLOCK_TYPE_ACPT,
+       CLOCK_TYPE_ASPTE,
+       CLOCK_TYPE_PMDACD2T,
+       CLOCK_TYPE_PCST,
+
+       CLOCK_TYPE_PC2CC3M,
+       CLOCK_TYPE_PC2CC3S_T,
+       CLOCK_TYPE_PC2CC3M_T,
+       CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
+       CLOCK_TYPE_MC2CC3P_A,
+       CLOCK_TYPE_M,
+       CLOCK_TYPE_MCPTM2C2C3,
+       CLOCK_TYPE_PC2CC3T_S,
+       CLOCK_TYPE_AC2CC3P_TS2,
+
+       CLOCK_TYPE_COUNT,
+       CLOCK_TYPE_NONE = -1,   /* invalid clock type */
+};
+
+enum {
+       CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
+};
+
+/*
+ * Clock source mux for each clock type. This just converts our enum into
+ * a list of mux sources for use by the code.
+ *
+ * Note:
+ *  The extra column in each clock source array is used to store the mask
+ *  bits in its register for the source.
+ */
+#define CLK(x) CLOCK_ID_ ## x
+static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
+       { CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       { CLK(AUDIO),   CLK(SFROM32KHZ),        CLK(PERIPH),    CLK(OSC),
+               CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_29},
+       { CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
+               CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       { CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ),        CLK(OSC),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_28},
+
+       /* Additional clock types on Tegra114+ */
+       /* CLOCK_TYPE_PC2CC3M */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(MEMORY),    CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3S_T */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(SFROM32KHZ), CLK(NONE),     CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3M_T */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(MEMORY),    CLK(NONE),      CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(MEMORY),    CLK(NONE),      CLK(OSC),       CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_MC2CC3P_A */
+       { CLK(MEMORY),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(PERIPH),    CLK(NONE),      CLK(AUDIO),     CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_M */
+       { CLK(MEMORY),          CLK(NONE),      CLK(NONE),      CLK(NONE),
+               CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
+               MASK_BITS_31_30},
+       /* CLOCK_TYPE_MCPTM2C2C3 */
+       { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
+               CLK(MEMORY2),   CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_PC2CC3T_S */
+       { CLK(PERIPH),  CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(OSC),       CLK(NONE),      CLK(SFROM32KHZ), CLK(NONE),
+               MASK_BITS_31_29},
+       /* CLOCK_TYPE_AC2CC3P_TS2 */
+       { CLK(AUDIO),   CLK(CGENERAL2), CLK(CGENERAL),  CLK(CGENERAL3),
+               CLK(PERIPH),    CLK(NONE),      CLK(OSC),       CLK(SRC2),
+               MASK_BITS_31_29},
+};
+
+/*
+ * Clock type for each peripheral clock source. We put the name in each
+ * record just so it is easy to match things up
+ */
+#define TYPE(name, type) type
+static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
+       /* 0x00 */
+       TYPE(PERIPHC_I2S1,      CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
+       TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PC2CC3M),
+       TYPE(PERIPHC_PWM,       CLOCK_TYPE_PC2CC3S_T),
+       TYPE(PERIPHC_05h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PC2CC3M_T),
+
+       /* 0x08 */
+       TYPE(PERIPHC_08h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_I2C5,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_0bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_0ch,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
+       TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
+
+       /* 0x10 */
+       TYPE(PERIPHC_10h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_11h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_VI,        CLOCK_TYPE_MC2CC3P_A),
+       TYPE(PERIPHC_13h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_SDMMC2,    CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_16h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_17h,       CLOCK_TYPE_NONE),
+
+       /* 0x18 */
+       TYPE(PERIPHC_18h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SDMMC4,    CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_1Bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_1Ch,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_HSI,       CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_UART1,     CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_UART2,     CLOCK_TYPE_PC2CC3M_T),
+
+       /* 0x20 */
+       TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MC2CC3P_A),
+       TYPE(PERIPHC_21h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_22h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
+       TYPE(PERIPHC_24h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_25h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_EMC,       CLOCK_TYPE_MCPTM2C2C3),
+
+       /* 0x28 */
+       TYPE(PERIPHC_UART3,     CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_29h,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
+       TYPE(PERIPHC_2bh,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_2ch,       CLOCK_TYPE_NONE),
+       TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PC2CC3M_T),
+       TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PC2CC3M_T16),
+       TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PC2CC3M_T),
+
+       /* 0x30 */
+       TYPE(PERIPHC_UART4,     CLOCK_TYPE_PC2CC3M_T),
+