Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 10 Oct 2014 06:56:01 +0000 (08:56 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Fri, 10 Oct 2014 06:56:01 +0000 (08:56 +0200)
70 files changed:
arch/arm/Kconfig
arch/arm/cpu/arm1136/mx31/timer.c
arch/arm/cpu/arm1136/mx35/timer.c
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
arch/arm/cpu/armv7/mx6/clock.c
arch/arm/cpu/armv7/mx6/hab.c
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
arch/arm/include/asm/arch-mx31/imx-regs.h
arch/arm/include/asm/arch-mx35/imx-regs.h
arch/arm/include/asm/arch-mx6/clock.h
arch/arm/include/asm/arch-mx6/hab.h
arch/arm/include/asm/arch-mx6/imx-regs.h
arch/arm/include/asm/arch-vf610/imx-regs.h
arch/arm/include/asm/arch-vf610/iomux-vf610.h
arch/arm/include/asm/imx-common/iomux-v3.h
board/bachmann/ot1200/Kconfig [new file with mode: 0644]
board/bachmann/ot1200/MAINTAINERS [new file with mode: 0644]
board/bachmann/ot1200/Makefile [new file with mode: 0644]
board/bachmann/ot1200/README [new file with mode: 0644]
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg [moved from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg with 100% similarity]
board/bachmann/ot1200/ot1200.c [new file with mode: 0644]
board/boundary/nitrogen6x/1066mhz_4x256mx16.cfg
board/boundary/nitrogen6x/nitrogen6x.c
board/compulab/common/eeprom.c
board/congatec/cgtqmx6eval/imximage.cfg [new file with mode: 0644]
board/freescale/mx6qarm2/MAINTAINERS
board/freescale/mx6qarm2/imximage.cfg
board/freescale/mx6qarm2/imximage_mx6dl.cfg [new file with mode: 0644]
board/freescale/mx6qarm2/mx6qarm2.c
board/freescale/mx6qsabreauto/mx6qsabreauto.c
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg [new file with mode: 0644]
board/freescale/mx6sxsabresd/mx6sxsabresd.c
board/freescale/vf610twr/MAINTAINERS
board/freescale/vf610twr/vf610twr.c
board/gateworks/gw_ventana/gw_ventana_spl.c
board/olimex/mx23_olinuxino/mx23_olinuxino.c
board/renesas/alt/qos.c
board/renesas/koelsch/qos.c
board/renesas/lager/lager.c
board/renesas/lager/qos.c
configs/cgtqmx6qeval_defconfig
configs/mx6dlarm2_defconfig [new file with mode: 0644]
configs/mx6dlarm2_lpddr2_defconfig [new file with mode: 0644]
configs/mx6qarm2_defconfig
configs/mx6qarm2_lpddr2_defconfig [new file with mode: 0644]
configs/mx6qsabresd_defconfig
configs/ot1200_defconfig [new file with mode: 0644]
configs/vf610twr_defconfig
configs/vf610twr_nand_defconfig [new file with mode: 0644]
drivers/mtd/nand/Makefile
drivers/mtd/nand/vf610_nfc.c [new file with mode: 0644]
drivers/usb/host/ehci-mx6.c
drivers/usb/host/ehci-mxs.c
include/configs/cm_fx6.h
include/configs/koelsch.h
include/configs/lager.h
include/configs/lsxl.h
include/configs/m28evk.h
include/configs/m53evk.h
include/configs/mx25pdk.h
include/configs/mx51evk.h
include/configs/mx6qarm2.h
include/configs/mx6slevk.h
include/configs/mx6sxsabresd.h
include/configs/nitrogen6x.h
include/configs/ot1200.h [new file with mode: 0644]
include/configs/sheevaplug.h
include/configs/vf610twr.h
include/configs/wandboard.h

index 6c5ecd2..72558b8 100644 (file)
@@ -417,6 +417,9 @@ config TARGET_HUMMINGBOARD
 config TARGET_TQMA6
        bool "TQ Systems TQMa6 board"
 
+config TARGET_OT1200
+       bool "Bachmann OT1200"
+
 config OMAP34XX
        bool "OMAP34XX SoC"
 
@@ -582,6 +585,7 @@ source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
 source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
+source "board/bachmann/ot1200/Kconfig"
 source "board/balloon3/Kconfig"
 source "board/barco/titanium/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
index f111242..3a81ce4 100644 (file)
@@ -7,9 +7,6 @@
 
 #include <common.h>
 #include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-#include <div64.h>
-#include <watchdog.h>
 #include <asm/io.h>
 
 #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-
-#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-       tick *= CONFIG_SYS_HZ;
-       do_div(tick, MXC_CLK32);
-       return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-       time *= MXC_CLK32;
-       do_div(time, CONFIG_SYS_HZ);
-       return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-       us = us * MXC_CLK32 + 999999;
-       do_div(us, 1000000);
-       return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME  ((MXC_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
-#define US_PER_TICK    (1000000 / MXC_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-       do_div(tick, TICK_PER_TIME);
-       return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-       return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-       us += US_PER_TICK - 1;
-       do_div(us, US_PER_TICK);
-       return us;
-}
-#endif
-
 /* The 32768Hz 32-bit timer overruns in 131072 seconds */
 int timer_init(void)
 {
@@ -95,53 +41,7 @@ int timer_init(void)
        return 0;
 }
 
-unsigned long long get_ticks(void)
-{
-       ulong now = GPTCNT; /* current tick value */
-
-       if (now >= gd->arch.lastinc)    /* normal mode (non roll) */
-               /* move stamp forward with absolut diff ticks */
-               gd->arch.tbl += (now - gd->arch.lastinc);
-       else                    /* we have rollover of incrementer */
-               gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
-       gd->arch.lastinc = now;
-       return gd->arch.tbl;
-}
-
-ulong get_timer_masked(void)
-{
-       /*
-        * get_ticks() returns a long long (64 bit), it wraps in
-        * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-        * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-        * 5 * 10^6 days - long enough.
-        */
-       return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-       return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
-       unsigned long long tmp;
-       ulong tmo;
-
-       tmo = us_to_tick(usec);
-       tmp = get_ticks() + tmo;        /* get current timestamp */
-
-       while (get_ticks() < tmp)       /* loop till event */
-                /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
+unsigned long timer_read_counter(void)
 {
-       return MXC_CLK32;
+       return GPTCNT;
 }
index cc6166f..4edf533 100644 (file)
@@ -9,43 +9,17 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <div64.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
-#include <asm/arch/clock.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define timestamp      (gd->arch.tbl)
-#define lastinc                (gd->arch.lastinc)
-
 /* General purpose timers bitfields */
 #define GPTCR_SWR       (1<<15)        /* Software reset */
 #define GPTCR_FRR       (1<<9) /* Freerun / restart */
 #define GPTCR_CLKSOURCE_32   (4<<6)    /* Clock source */
 #define GPTCR_TEN       (1)    /* Timer enable */
 
-/*
- * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
- * "tick" is internal timer period
- */
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-       tick *= CONFIG_SYS_HZ;
-       do_div(tick, MXC_CLK32);
-
-       return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-       us = us * MXC_CLK32 + 999999;
-       do_div(us, 1000000);
-
-       return us;
-}
-
 /*
  * nothing really to do with interrupts, just starts up a counter.
  * The 32KHz 32-bit timer overruns in 134217 seconds
@@ -71,60 +45,3 @@ int timer_init(void)
 
        return 0;
 }
-
-unsigned long long get_ticks(void)
-{
-       struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
-       ulong now = readl(&gpt->counter); /* current tick value */
-
-       if (now >= lastinc) {
-               /*
-                * normal mode (non roll)
-                * move stamp forward with absolut diff ticks
-                */
-               timestamp += (now - lastinc);
-       } else {
-               /* we have rollover of incrementer */
-               timestamp += (0xFFFFFFFF - lastinc) + now;
-       }
-       lastinc = now;
-       return timestamp;
-}
-
-ulong get_timer_masked(void)
-{
-       /*
-        * get_ticks() returns a long long (64 bit), it wraps in
-        * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-        * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-        * 5 * 10^6 days - long enough.
-        */
-       return tick_to_time(get_ticks());
-}
-
-ulong get_timer(ulong base)
-{
-       return get_timer_masked() - base;
-}
-
-/* delay x useconds AND preserve advance timstamp value */
-void __udelay(unsigned long usec)
-{
-       unsigned long long tmp;
-       ulong tmo;
-
-       tmo = us_to_tick(usec);
-       tmp = get_ticks() + tmo;        /* get current timestamp */
-
-       while (get_ticks() < tmp)       /* loop till event */
-                /*NOP*/;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-       return MXC_CLK32;
-}
index 3baf4dd..97ef67d 100644 (file)
@@ -240,9 +240,14 @@ static void mx23_mem_setup_vddmem(void)
        struct mxs_power_regs *power_regs =
                (struct mxs_power_regs *)MXS_POWER_BASE;
 
+       /* We must wait before and after disabling the current limiter! */
+       early_delay(10000);
+
        clrbits_le32(&power_regs->hw_power_vddmemctrl,
                POWER_VDDMEMCTRL_ENABLE_ILIMIT);
 
+       early_delay(10000);
+
 }
 
 static void mx23_mem_init(void)
@@ -269,7 +274,13 @@ static void mx23_mem_init(void)
        setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
 
        clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
-       early_delay(20000);
+
+       /* Wait for EMI_STAT bit DRAM_HALTED */
+       for (;;) {
+               if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
+                       break;
+               early_delay(1000);
+       }
 
        /* Adjust EMI port priority. */
        clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);
index 336e557..d200531 100644 (file)
@@ -642,6 +642,33 @@ int enable_pcie_clock(void)
                               BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
 
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+       u32 reg;
+
+       /* CG4 ~ CG6, CAAM clocks */
+       reg = __raw_readl(&imx_ccm->CCGR0);
+       if (enable)
+               reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+                       MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+                       MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+       else
+               reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+                       MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+                       MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+       __raw_writel(reg, &imx_ccm->CCGR0);
+
+       /* EMI slow clk */
+       reg = __raw_readl(&imx_ccm->CCGR6);
+       if (enable)
+               reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+       else
+               reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+       __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
        switch (clk) {
index f6810a6..8dee595 100644 (file)
@@ -1,12 +1,14 @@
 /*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/system.h>
 #include <asm/arch/hab.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 
 /* -------- start of HAB API updates ------------*/
        ((hab_rvt_exit_t *)HAB_RVT_EXIT)                        \
 )
 
+#define IVT_SIZE               0x20
+#define ALIGN_SIZE             0x1000
+#define CSF_PAD_SIZE           0x2000
+#define MX6DQ_PU_IROM_MMU_EN_VAR       0x009024a8
+#define MX6DLS_PU_IROM_MMU_EN_VAR      0x00901dd0
+#define MX6SL_PU_IROM_MMU_EN_VAR       0x00900a18
+
+/*
+ * +------------+  0x0 (DDR_UIMAGE_START) -
+ * |   Header   |                          |
+ * +------------+  0x40                    |
+ * |            |                          |
+ * |            |                          |
+ * |            |                          |
+ * |            |                          |
+ * | Image Data |                          |
+ * .            |                          |
+ * .            |                           > Stuff to be authenticated ----+
+ * .            |                          |                                |
+ * |            |                          |                                |
+ * |            |                          |                                |
+ * +------------+                          |                                |
+ * |            |                          |                                |
+ * | Fill Data  |                          |                                |
+ * |            |                          |                                |
+ * +------------+ Align to ALIGN_SIZE      |                                |
+ * |    IVT     |                          |                                |
+ * +------------+ + IVT_SIZE              -                                 |
+ * |            |                                                           |
+ * |  CSF DATA  | <---------------------------------------------------------+
+ * |            |
+ * +------------+
+ * |            |
+ * | Fill Data  |
+ * |            |
+ * +------------+ + CSF_PAD_SIZE
+ */
+
 bool is_hab_enabled(void)
 {
        struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -144,6 +184,108 @@ int get_hab_status(void)
        return 0;
 }
 
+uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
+{
+       uint32_t load_addr = 0;
+       size_t bytes;
+       ptrdiff_t ivt_offset = 0;
+       int result = 0;
+       ulong start;
+       hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
+       hab_rvt_entry_t *hab_rvt_entry;
+       hab_rvt_exit_t *hab_rvt_exit;
+
+       hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
+       hab_rvt_entry = hab_rvt_entry_p;
+       hab_rvt_exit = hab_rvt_exit_p;
+
+       if (is_hab_enabled()) {
+               printf("\nAuthenticate image from DDR location 0x%x...\n",
+                      ddr_start);
+
+               hab_caam_clock_enable(1);
+
+               if (hab_rvt_entry() == HAB_SUCCESS) {
+                       /* If not already aligned, Align to ALIGN_SIZE */
+                       ivt_offset = (image_size + ALIGN_SIZE - 1) &
+                                       ~(ALIGN_SIZE - 1);
+
+                       start = ddr_start;
+                       bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
+#ifdef DEBUG
+                       printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
+                              ivt_offset, ddr_start + ivt_offset);
+                       puts("Dumping IVT\n");
+                       print_buffer(ddr_start + ivt_offset,
+                                    (void *)(ddr_start + ivt_offset),
+                                    4, 0x8, 0);
+
+                       puts("Dumping CSF Header\n");
+                       print_buffer(ddr_start + ivt_offset+IVT_SIZE,
+                                    (void *)(ddr_start + ivt_offset+IVT_SIZE),
+                                    4, 0x10, 0);
+
+                       get_hab_status();
+
+                       puts("\nCalling authenticate_image in ROM\n");
+                       printf("\tivt_offset = 0x%x\n", ivt_offset);
+                       printf("\tstart = 0x%08lx\n", start);
+                       printf("\tbytes = 0x%x\n", bytes);
+#endif
+                       /*
+                        * If the MMU is enabled, we have to notify the ROM
+                        * code, or it won't flush the caches when needed.
+                        * This is done, by setting the "pu_irom_mmu_enabled"
+                        * word to 1. You can find its address by looking in
+                        * the ROM map. This is critical for
+                        * authenticate_image(). If MMU is enabled, without
+                        * setting this bit, authentication will fail and may
+                        * crash.
+                        */
+                       /* Check MMU enabled */
+                       if (get_cr() & CR_M) {
+                               if (is_cpu_type(MXC_CPU_MX6Q) ||
+                                   is_cpu_type(MXC_CPU_MX6D)) {
+                                       /*
+                                        * This won't work on Rev 1.0.0 of
+                                        * i.MX6Q/D, since their ROM doesn't
+                                        * do cache flushes. don't think any
+                                        * exist, so we ignore them.
+                                        */
+                                       writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
+                               } else if (is_cpu_type(MXC_CPU_MX6DL) ||
+                                          is_cpu_type(MXC_CPU_MX6SOLO)) {
+                                       writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
+                               } else if (is_cpu_type(MXC_CPU_MX6SL)) {
+                                       writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
+                               }
+                       }
+
+                       load_addr = (uint32_t)hab_rvt_authenticate_image(
+                                       HAB_CID_UBOOT,
+                                       ivt_offset, (void **)&start,
+                                       (size_t *)&bytes, NULL);
+                       if (hab_rvt_exit() != HAB_SUCCESS) {
+                               puts("hab exit function fail\n");
+                               load_addr = 0;
+                       }
+               } else {
+                       puts("hab entry function fail\n");
+               }
+
+               hab_caam_clock_enable(0);
+
+               get_hab_status();
+       } else {
+               puts("hab fuse not enabled\n");
+       }
+
+       if ((!is_hab_enabled()) || (load_addr != 0))
+               result = 1;
+
+       return result;
+}
+
 int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        if ((argc != 1)) {
@@ -156,8 +298,33 @@ int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        return 0;
 }
 
+static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
+                               char * const argv[])
+{
+       ulong   addr, ivt_offset;
+       int     rcode = 0;
+
+       if (argc < 3)
+               return CMD_RET_USAGE;
+
+       addr = simple_strtoul(argv[1], NULL, 16);
+       ivt_offset = simple_strtoul(argv[2], NULL, 16);
+
+       rcode = authenticate_image(addr, ivt_offset);
+
+       return rcode;
+}
+
 U_BOOT_CMD(
                hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
                "display HAB status",
                ""
          );
+
+U_BOOT_CMD(
+               hab_auth_img, 3, 0, do_authenticate_image,
+               "authenticate image via HAB",
+               "addr ivt_offset\n"
+               "addr - image hex address\n"
+               "ivt_offset - hex offset of IVT in the image"
+         );
index ba21cfe..6352422 100644 (file)
@@ -273,10 +273,25 @@ int board_postclk_init(void)
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+       enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+       enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+
        /* Avoid random hang when download by usb */
        invalidate_dcache_all();
+
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
+
+       /* Enable caching on OCRAM and ROM */
+       mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
+                                       ROMCP_ARB_END_ADDR,
+                                       option);
+       mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
+                                       IRAM_SIZE,
+                                       option);
 }
 #endif
 
@@ -339,10 +354,10 @@ const struct boot_mode soc_boot_modes[] = {
 void s_init(void)
 {
        struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-       int is_6q = is_cpu_type(MXC_CPU_MX6Q);
+       struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
        u32 mask480;
        u32 mask528;
-
+       u32 reg, periph1, periph2;
 
        if (is_cpu_type(MXC_CPU_MX6SX))
                return;
@@ -357,15 +372,23 @@ void s_init(void)
                ANATOP_PFD_CLKGATE_MASK(1) |
                ANATOP_PFD_CLKGATE_MASK(2) |
                ANATOP_PFD_CLKGATE_MASK(3);
-       mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
-               ANATOP_PFD_CLKGATE_MASK(1) |
+       mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
                ANATOP_PFD_CLKGATE_MASK(3);
 
-       /*
-        * Don't reset PFD2 on DL/S
-        */
-       if (is_6q)
+       reg = readl(&ccm->cbcmr);
+       periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
+               >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
+       periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+               >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
+
+       /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
+       if ((periph2 != 0x2) && (periph1 != 0x2))
+               mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
+
+       if ((periph2 != 0x1) && (periph1 != 0x1) &&
+               (periph2 != 0x3) && (periph1 != 0x3))
                mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
+
        writel(mask480, &anatop->pfd_480_set);
        writel(mask528, &anatop->pfd_528_set);
        writel(mask480, &anatop->pfd_480_clr);
index 287f8d7..879e0e0 100644 (file)
@@ -35,6 +35,13 @@ do_cpu_waiting:
  */
        .align  4
 do_lowlevel_init:
+       ldr     r2, =0xFF000044         /* PRR */
+       ldr     r1, [r2]
+       and     r1, r1, #0x7F00
+       lsrs    r1, r1, #8
+       cmp     r1, #0x4C               /* 0x4C is ID of r8a7794 */
+       beq     _exit_init_l2_a15
+
        /* surpress wfe if ca15 */
        tst r4, #4
        mrceq p15, 0, r0, c1, c0, 1     /* actlr */
@@ -42,11 +49,6 @@ do_lowlevel_init:
        mcreq p15, 0, r0, c1, c0, 1
 
        /* and set l2 latency */
-       mrceq p15, 1, r0, c9, c0, 2     /* l2ctlr */
-       orreq r0, r0, #0x00000800
-       orreq r0, r0, #0x00000003
-       mcreq p15, 1, r0, c9, c0, 2
-
        mrc p15, 0, r0, c0, c0, 5       /* r0 = MPIDR */
        and r0, r0, #0xf00
        lsr r0, r0, #8
@@ -58,7 +60,15 @@ do_lowlevel_init:
        cmp r1, #3                      /* has already been set up */
        bicne r0, r0, #0xe7
        orrne r0, r0, #0x83             /* L2CTLR[7:6] + L2CTLR[2:0] */
-       orrne r0, r0, #0x20             /* L2CTLR[5] */
+
+       ldr     r2, =0xFF000044         /* PRR */
+       ldr     r1, [r2]
+       and     r1, r1, #0x7F00
+       lsrs    r1, r1, #8
+       cmp     r1, #0x45               /* 0x45 is ID of r8a7790 */
+       bne     L2CTLR_5_SKIP
+       orrne r0, r0, #0x20             /* L2CTLR[5] */
+L2CTLR_5_SKIP:
        mcrne p15, 1, r0, c9, c0, 2
 
 _exit_init_l2_a15:
index f23350e..71ebd24 100644 (file)
@@ -909,9 +909,19 @@ struct esdc_regs {
 #define MXC_CSPIPERIOD_32KHZ   (1 << 15)
 #define MAX_SPI_BYTES  4
 
+
 #define MXC_SPI_BASE_ADDRESSES \
        0x43fa4000, \
        0x50010000, \
        0x53f84000,
 
+/*
+ * Generic timer support
+ */
+#ifdef CONFIG_MX31_CLK32
+#define        CONFIG_SYS_TIMER_RATE   CONFIG_MX31_CLK32
+#else
+#define        CONFIG_SYS_TIMER_RATE   32768
+#endif
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */
index b530029..28a47ed 100644 (file)
@@ -372,4 +372,16 @@ struct aips_regs {
 #define CCM_RCSR_NF_16BIT_SEL  (1 << 14)
 
 #endif
+
+/*
+ * Generic timer support
+ */
+#ifdef CONFIG_MX35_CLK32
+#define        CONFIG_SYS_TIMER_RATE   CONFIG_MX35_CLK32
+#else
+#define        CONFIG_SYS_TIMER_RATE   32768
+#endif
+
+#define CONFIG_SYS_TIMER_COUNTER       (GPT1_BASE_ADDR+36)
+
 #endif /* __ASM_ARCH_MX35_H */
index c11674f..3c58a0a 100644 (file)
@@ -53,6 +53,7 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 void setup_gpmi_io_clk(u32 cfg);
+void hab_caam_clock_enable(unsigned char enable);
 void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 void enable_uart_clk(unsigned char enable);
index 1f12695..c9e5318 100644 (file)
@@ -53,11 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
                void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
-#define HAB_RVT_REPORT_EVENT                   (*(uint32_t *)0x000000B4)
-#define HAB_RVT_REPORT_STATUS                  (*(uint32_t *)0x000000B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE             (*(uint32_t *)0x000000A4)
-#define HAB_RVT_ENTRY                          (*(uint32_t *)0x00000098)
-#define HAB_RVT_EXIT                           (*(uint32_t *)0x0000009C)
+#ifdef CONFIG_MX6SX
+#define HAB_RVT_BASE                   0x00000100
+#else
+#define HAB_RVT_BASE                   0x00000094
+#endif
+
+#define HAB_RVT_ENTRY                  (*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT                   (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_AUTHENTICATE_IMAGE     (*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT           (*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS          (*(uint32_t *)(HAB_RVT_BASE + 0x24))
 
 #define HAB_RVT_REPORT_EVENT_NEW               (*(uint32_t *)0x000000B8)
 #define HAB_RVT_REPORT_STATUS_NEW              (*(uint32_t *)0x000000BC)
index 22614fc..a159309 100644 (file)
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
-#ifdef CONFIG_MX6SL
-#define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#else
-#define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#endif
+#define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 #ifdef CONFIG_MX6SL
index bb00217..9d797db 100644 (file)
 /* DDRMC */
 #define DDRMC_PHY_DQ_TIMING                            0x00002613
 #define DDRMC_PHY_DQS_TIMING                           0x00002615
-#define DDRMC_PHY_CTRL                                 0x01210080
+#define DDRMC_PHY_CTRL                                 0x00210000
 #define DDRMC_PHY_MASTER_CTRL                          0x0001012a
-#define DDRMC_PHY_SLAVE_CTRL                           0x00012020
+#define DDRMC_PHY_SLAVE_CTRL                           0x00002000
+#define DDRMC_PHY_OFF                                  0x00000000
+#define DDRMC_PHY_PROC_PAD_ODT                         0x00010101
 
 #define DDRMC_PHY50_DDR3_MODE                          (1 << 12)
 #define DDRMC_PHY50_EN_SW_HALF_CYCLE                   (1 << 8)
 #define DDRMC_CR21_CCMAP_EN                            1
 #define DDRMC_CR22_TDAL(v)                             (((v) & 0x3f) << 16)
 #define DDRMC_CR23_BSTLEN(v)                           (((v) & 0x7) << 24)
-#define DDRMC_CR23_TDLL(v)                             ((v) & 0xff)
+#define DDRMC_CR23_TDLL(v)                             ((v) & 0xffff)
 #define DDRMC_CR24_TRP_AB(v)                           ((v) & 0x1f)
 #define DDRMC_CR25_TREF_EN                             (1 << 16)
 #define DDRMC_CR26_TREF(v)                             (((v) & 0xffff) << 16)
 #define DDRMC_CR33_EN_QK_SREF                          (1 << 16)
 #define DDRMC_CR34_CKSRX(v)                            (((v) & 0xf) << 16)
 #define DDRMC_CR34_CKSRE(v)                            (((v) & 0xf) << 8)
-#define DDRMC_CR38_FREQ_CHG_EN                         (1 << 8)
+#define DDRMC_CR38_FREQ_CHG_EN(v)                      (((v) & 0x1) << 8)
 #define DDRMC_CR39_PHY_INI_COM(v)                      (((v) & 0xffff) << 16)
 #define DDRMC_CR39_PHY_INI_STA(v)                      (((v) & 0xff) << 8)
 #define DDRMC_CR39_FRQ_CH_DLLOFF(v)                    ((v) & 0x3)
 #define DDRMC_CR67_ZQCS(v)                             ((v) & 0xfff)
 #define DDRMC_CR69_ZQ_ON_SREF_EX(v)                    (((v) & 0xf) << 8)
 #define DDRMC_CR70_REF_PER_ZQ(v)                       (v)
-#define DDRMC_CR72_ZQCS_ROTATE                         (1 << 24)
+#define DDRMC_CR72_ZQCS_ROTATE(v)                      (((v) & 0x1) << 24)
 #define DDRMC_CR73_APREBIT(v)                          (((v) & 0xf) << 24)
 #define DDRMC_CR73_COL_DIFF(v)                         (((v) & 0x7) << 16)
 #define DDRMC_CR73_ROW_DIFF(v)                         (((v) & 0x3) << 8)
 #define DDRMC_CR77_CS_MAP                              (1 << 24)
 #define DDRMC_CR77_DI_RD_INTLEAVE                      (1 << 8)
 #define DDRMC_CR77_SWAP_EN                             1
+#define DDRMC_CR78_Q_FULLNESS(v)                       (((v) & 0x7) << 24)
 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)                   ((v) & 0xf)
-#define DDRMC_CR79_CTLUPD_AREF                         (1 << 24)
-#define DDRMC_CR82_INT_MASK                            0x1fffffff
+#define DDRMC_CR79_CTLUPD_AREF(v)                      (((v) & 0x1) << 24)
+#define DDRMC_CR82_INT_MASK                            0x10000000
 #define DDRMC_CR87_ODT_WR_MAPCS0                       (1 << 24)
 #define DDRMC_CR87_ODT_RD_MAPCS0                       (1 << 16)
 #define DDRMC_CR88_TODTL_CMD(v)                                (((v) & 0x1f) << 16)
 #define DDRMC_CR91_R2W_SMCSDL(v)                       (((v) & 0x7) << 16)
 #define DDRMC_CR96_WLMRD(v)                            (((v) & 0x3f) << 8)
 #define DDRMC_CR96_WLDQSEN(v)                          ((v) & 0x3f)
+#define DDRMC_CR97_WRLVL_EN                            (1 << 24)
+#define DDRMC_CR98_WRLVL_DL_0                          (0)
+#define DDRMC_CR99_WRLVL_DL_1                          (0)
+#define DDRMC_CR102_RDLVL_GT_REGEN                     (1 << 16)
+#define DDRMC_CR102_RDLVL_REG_EN                       (1 << 8)
 #define DDRMC_CR105_RDLVL_DL_0(v)                      (((v) & 0xff) << 8)
+#define DDRMC_CR106_RDLVL_GTDL_0(v)                    ((v) & 0xff)
 #define DDRMC_CR110_RDLVL_DL_1(v)                      ((v) & 0xff)
+#define DDRMC_CR110_RDLVL_GTDL_1(v)                    (((v) & 0xff) << 16)
 #define DDRMC_CR114_RDLVL_GTDL_2(v)                    (((v) & 0xffff) << 8)
+#define DDRMC_CR115_RDLVL_GTDL_2(v)                    ((v) & 0xff)
 #define DDRMC_CR117_AXI0_W_PRI(v)                      (((v) & 0x3) << 8)
 #define DDRMC_CR117_AXI0_R_PRI(v)                      ((v) & 0x3)
 #define DDRMC_CR118_AXI1_W_PRI(v)                      (((v) & 0x3) << 24)
 #define DDRMC_CR122_AXI0_PRIRLX(v)                     ((v) & 0x3ff)
 #define DDRMC_CR123_AXI1_PRI3_RPRI(v)                  (((v) & 0xf) << 8)
 #define DDRMC_CR123_AXI1_PRI2_RPRI(v)                  ((v) & 0xf)
+#define DDRMC_CR123_AXI1_P_ODR_EN                      (1 << 16)
 #define DDRMC_CR124_AXI1_PRIRLX(v)                     ((v) & 0x3ff)
 #define DDRMC_CR126_PHY_RDLAT(v)                       (((v) & 0x3f) << 8)
 #define DDRMC_CR132_WRLAT_ADJ(v)                       (((v) & 0x1f) << 8)
 #define DDRMC_CR132_RDLAT_ADJ(v)                       ((v) & 0x3f)
+#define DDRMC_CR137_PHYCTL_DL(v)                       (((v) & 0xf) << 16)
+#define DDRMC_CR138_PHY_WRLV_MXDL(v)                   (((v) & 0xffff) << 16)
+#define DDRMC_CR138_PHYDRAM_CK_EN(v)                   (((v) & 0x8) << 8)
 #define DDRMC_CR139_PHY_WRLV_RESPLAT(v)                        (((v) & 0xff) << 24)
 #define DDRMC_CR139_PHY_WRLV_LOAD(v)                   (((v) & 0xff) << 16)
 #define DDRMC_CR139_PHY_WRLV_DLL(v)                    (((v) & 0xff) << 8)
 #define DDRMC_CR139_PHY_WRLV_EN(v)                     ((v) & 0xff)
+#define DDRMC_CR140_PHY_WRLV_WW(v)                     ((v) & 0x3ff)
+#define DDRMC_CR143_RDLV_GAT_MXDL(v)                   (((v) & 0xffff) << 16)
+#define DDRMC_CR143_RDLV_MXDL(v)                       ((v) & 0xffff)
+#define DDRMC_CR144_PHY_RDLVL_RES(v)                   (((v) & 0xff) << 24)
+#define DDRMC_CR144_PHY_RDLV_LOAD(v)                   (((v) & 0xff) << 16)
+#define DDRMC_CR144_PHY_RDLV_DLL(v)                    (((v) & 0xff) << 8)
+#define DDRMC_CR144_PHY_RDLV_EN(v)                     ((v) & 0xff)
+#define DDRMC_CR145_PHY_RDLV_RR(v)                     ((v) & 0x3ff)
+#define DDRMC_CR146_PHY_RDLVL_RESP(v)                  (v)
+#define DDRMC_CR147_RDLV_RESP_MASK(v)                  ((v) & 0xfffff)
+#define DDRMC_CR148_RDLV_GATE_RESP_MASK(v)             ((v) & 0xfffff)
+#define DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(v)            (((v) & 0xf) << 8)
+#define DDRMC_CR151_RDLVL_DQ_ZERO_CNT(v)               ((v) & 0xf)
 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)       (((v) & 0x1f) << 27)
 #define DDRMC_CR154_PAD_ZQ_MODE(v)                     (((v) & 0x3) << 21)
 #define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)               (((v) & 0x3) << 18)
+#define DDRMC_CR154_PAD_ZQ_HW_FOR(v)                   (((v) & 0x1) << 14)
 #define DDRMC_CR155_AXI0_AWCACHE                       (1 << 10)
-#define DDRMC_CR155_PAD_ODT_BYTE1(v)                   ((v) & 0x7)
+#define DDRMC_CR155_PAD_ODT_BYTE1(v)                   (((v) & 0x7) << 3)
+#define DDRMC_CR155_PAD_ODT_BYTE0(v)                   ((v) & 0x7)
 #define DDRMC_CR158_TWR(v)                             ((v) & 0x3f)
+#define DDRMC_CR161_ODT_EN(v)                          (((v) & 0x1) << 16)
+#define DDRMC_CR161_TODTH_RD(v)                                (((v) & 0xf) << 8)
+#define DDRMC_CR161_TODTH_WR(v)                                ((v) & 0xf)
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
index 7464da8..9226e69 100644 (file)
@@ -17,6 +17,8 @@
 #define VF610_ENET_PAD_CTRL    (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
                                PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_DDR_PAD_CTRL     PAD_CTL_DSE_25ohm
+#define VF610_DDR_PAD_CTRL_1   (PAD_CTL_DSE_25ohm | \
+                               PAD_CTL_INPUT_DIFFERENTIAL)
 #define VF610_I2C_PAD_CTRL     (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
                                PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
 #define VF610_NFC_IO_PAD_CTRL  (PAD_CTL_SPEED_MED | PAD_CTL_SRE | \
@@ -102,6 +104,7 @@ enum {
 
        VF610_PAD_PTC28__NF_CLE                 = IOMUX_PAD(0x0194, 0x0194, 6, __NA_, 0, VF610_NFC_CN_PAD_CTRL),
 
+       VF610_PAD_DDR_RESETB                    = IOMUX_PAD(0x021c, 0x021c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A15__DDR_A_15             = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A14__DDR_A_14             = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A13__DDR_A_13             = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
@@ -117,6 +120,7 @@ enum {
        VF610_PAD_DDR_A3__DDR_A_3               = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A2__DDR_A_2               = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_A1__DDR_A_1               = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+       VF610_PAD_DDR_A0__DDR_A_0               = IOMUX_PAD(0x025c, 0x025c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_BA2__DDR_BA_2             = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_BA1__DDR_BA_1             = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_BA0__DDR_BA_0             = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
@@ -124,26 +128,26 @@ enum {
        VF610_PAD_DDR_CKE__DDR_CKE_0            = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_CLK__DDR_CLK_0            = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_CS__DDR_CS_B_0            = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D15__DDR_D_15             = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D14__DDR_D_14             = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D13__DDR_D_13             = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D12__DDR_D_12             = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D11__DDR_D_11             = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D10__DDR_D_10             = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D9__DDR_D_9               = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D8__DDR_D_8               = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D7__DDR_D_7               = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D6__DDR_D_6               = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D5__DDR_D_5               = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D4__DDR_D_4               = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D3__DDR_D_3               = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D2__DDR_D_2               = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D1__DDR_D_1               = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_D0__DDR_D_0               = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_DQM1__DDR_DQM_1           = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_DQM0__DDR_DQM_0           = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_DQS1__DDR_DQS_1           = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
-       VF610_PAD_DDR_DQS0__DDR_DQS_0           = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+       VF610_PAD_DDR_D15__DDR_D_15             = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D14__DDR_D_14             = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D13__DDR_D_13             = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D12__DDR_D_12             = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D11__DDR_D_11             = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D10__DDR_D_10             = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D9__DDR_D_9               = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D8__DDR_D_8               = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D7__DDR_D_7               = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D6__DDR_D_6               = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D5__DDR_D_5               = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D4__DDR_D_4               = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D3__DDR_D_3               = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D2__DDR_D_2               = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D1__DDR_D_1               = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_D0__DDR_D_0               = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_DQM1__DDR_DQM_1           = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_DQM0__DDR_DQM_0           = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_DQS1__DDR_DQS_1           = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
+       VF610_PAD_DDR_DQS0__DDR_DQS_0           = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL_1),
        VF610_PAD_DDR_RAS__DDR_RAS_B            = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_WE__DDR_WE_B              = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
        VF610_PAD_DDR_ODT1__DDR_ODT_0           = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
index 70ee86c..a8ca49c 100644 (file)
@@ -120,6 +120,8 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_MUX_MODE_SHIFT     20
 
+#define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
+
 #define PAD_CTL_SPEED_MED      (1 << 12)
 #define PAD_CTL_SPEED_HIGH     (3 << 12)
 
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
new file mode 100644 (file)
index 0000000..55a825d
--- /dev/null
@@ -0,0 +1,23 @@
+if TARGET_OT1200
+
+config SYS_CPU
+       string
+       default "armv7"
+
+config SYS_BOARD
+       string
+       default "ot1200"
+
+config SYS_VENDOR
+       string
+       default "bachmann"
+
+config SYS_SOC
+       string
+       default "mx6"
+
+config SYS_CONFIG_NAME
+       string
+       default "ot1200"
+
+endif
diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS
new file mode 100644 (file)
index 0000000..ad75c24
--- /dev/null
@@ -0,0 +1,6 @@
+BACHMANN ELECTRONIC OT1200 BOARD
+M:     Christian Gmeiner <christian.gmeiner@gmail.com>
+S:     Maintained
+F:     board/bachmann/ot1200
+F:     include/configs/ot1200.h
+F:     configs/ot1200*_defconfig
diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
new file mode 100644 (file)
index 0000000..1bd42e8
--- /dev/null
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  := ot1200.o
diff --git a/board/bachmann/ot1200/README b/board/bachmann/ot1200/README
new file mode 100644 (file)
index 0000000..c03d44e
--- /dev/null
@@ -0,0 +1,20 @@
+U-Boot for the Bachmann electronic GmbH OT1200 devices
+
+There are two different versions of the base board, which differ
+in the way ethernet is done. The variant detection is done during
+runtime based on the address of the found phy.
+
+- "mr" variant
+FEC is connected directly to an ethernet switch (KSZ8895). The ethernet
+port is always up and auto-negotiation is not possible.
+
+- normal variant
+FEC is connected to a normal phy and auto-negotiation is possible.
+
+
+The variant name is part of the dtb file name loaded by u-boot. This
+make is possible to boot the linux kernel and make use variant specific
+devicetree (fixed-phy link).
+
+In order to support different display resoltuions/sizes the OT1200 devices
+are making use of EDID data stored in an i2c EEPROM.
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
new file mode 100644 (file)
index 0000000..0d5ede5
--- /dev/null
@@ -0,0 +1,251 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014, Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/arch/crm_regs.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <netdev.h>
+#include <i2c.h>
+#include <pca953x.h>
+#include <asm/gpio.h>
+#include <phy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OUTPUT_40OHM   (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                  \
+       OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                   \
+       PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
+       PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
+       PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL   (PAD_CTL_HYS | OUTPUT_40OHM |           \
+       PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL   (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
+       PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+int dram_init(void)
+{
+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+       return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+       MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+       MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+       imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+static iomux_v3_cfg_t const enet_pads[] = {
+       MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+       MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+       imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+       MX6_PAD_DISP0_DAT3__ECSPI3_SS0  | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT4__ECSPI3_SS1  | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void setup_iomux_spi(void)
+{
+       imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
+int board_early_init_f(void)
+{
+       setup_iomux_uart();
+       setup_iomux_spi();
+
+       return 0;
+}
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+       MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+       return 1;
+}
+
+struct fsl_esdhc_cfg usdhc_cfg[] = {
+       {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+       usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+       usdhc_cfg[0].max_bus_width = 8;
+
+       imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+       return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+/* I2C3 - IO expander  */
+static struct i2c_pads_info i2c_pad_info2 = {
+       .scl = {
+               .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+               .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+               .gp = IMX_GPIO_NR(3, 17)
+       },
+       .sda = {
+               .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+               .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+               .gp = IMX_GPIO_NR(3, 18)
+       }
+};
+
+static iomux_v3_cfg_t const pwm_pad[] = {
+       MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
+};
+
+static void leds_on(void)
+{
+       /* turn on all possible leds connected via GPIO expander */
+       i2c_set_bus_num(2);
+       pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
+       pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
+}
+
+static void backlight_lcd_off(void)
+{
+       unsigned gpio = IMX_GPIO_NR(2, 0);
+       gpio_direction_output(gpio, 0);
+
+       gpio = IMX_GPIO_NR(2, 3);
+       gpio_direction_output(gpio, 0);
+}
+
+int board_eth_init(bd_t *bis)
+{
+       uint32_t base = IMX_FEC_BASE;
+       struct mii_dev *bus = NULL;
+       struct phy_device *phydev = NULL;
+       int ret;
+
+       setup_iomux_enet();
+
+       bus = fec_get_miibus(base, -1);
+       if (!bus)
+               return 0;
+
+       /* scan phy 0 and 5 */
+       phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
+       if (!phydev) {
+               free(bus);
+               return 0;
+       }
+
+       /* depending on the phy address we can detect our board version */
+       if (phydev->addr == 0)
+               setenv("boardver", "");
+       else
+               setenv("boardver", "mr");
+
+       printf("using phy at %d\n", phydev->addr);
+       ret = fec_probe(bis, -1, base, bus, phydev);
+       if (ret) {
+               printf("FEC MXC: %s:failed\n", __func__);
+               free(phydev);
+               free(bus);
+       }
+       return 0;
+}
+
+int board_init(void)
+{
+       gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+       backlight_lcd_off();
+
+       setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+
+       leds_on();
+
+       /* enable ecspi3 clocks */
+       enable_cspi_clock(1, 2);
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       puts("Board: "CONFIG_SYS_BOARD"\n");
+       return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+       /* 4 bit bus width */
+       {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+       {NULL,          0},
+};
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_BMODE
+       add_board_boot_modes(board_boot_modes);
+#endif
+       return 0;
+}
index bb5716e..1096f77 100644 (file)
@@ -24,18 +24,18 @@ DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003
 DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
 DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
 DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43040319
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x03040279
-DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43040321
-DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03030251
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4d434248
-DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c4d
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x34424543
-DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x49324933
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001a0017
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
-DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00170027
-DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000a001f
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42740304
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x026e0265
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x02750306
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02720244
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x463d4041
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x42413c47
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x37414441
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4633473b
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x0025001f
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x00290027
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001f002b
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x000f0029
 DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
 DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
 DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
index 7edfe19..951b820 100644 (file)
@@ -28,6 +28,9 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/mxc_hdmi.h>
 #include <i2c.h>
+#include <input.h>
+#include <netdev.h>
+#include <usb/ehci-fsl.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
@@ -70,12 +73,12 @@ int dram_init(void)
        return 0;
 }
 
-iomux_v3_cfg_t const uart1_pads[] = {
+static iomux_v3_cfg_t const uart1_pads[] = {
        MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t const uart2_pads[] = {
+static iomux_v3_cfg_t const uart2_pads[] = {
        MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
@@ -83,7 +86,7 @@ iomux_v3_cfg_t const uart2_pads[] = {
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
 /* I2C1, SGTL5000 */
-struct i2c_pads_info i2c_pad_info0 = {
+static struct i2c_pads_info i2c_pad_info0 = {
        .scl = {
                .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
                .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
@@ -97,7 +100,7 @@ struct i2c_pads_info i2c_pad_info0 = {
 };
 
 /* I2C2 Camera, MIPI */
-struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
        .scl = {
                .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
                .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
@@ -111,7 +114,7 @@ struct i2c_pads_info i2c_pad_info1 = {
 };
 
 /* I2C3, J15 - RGB connector */
-struct i2c_pads_info i2c_pad_info2 = {
+static struct i2c_pads_info i2c_pad_info2 = {
        .scl = {
                .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
                .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
@@ -124,7 +127,16 @@ struct i2c_pads_info i2c_pad_info2 = {
        }
 };
 
-iomux_v3_cfg_t const usdhc3_pads[] = {
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+       MX6_PAD_SD2_CLK__SD2_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_CMD__SD2_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+       MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -134,7 +146,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
-iomux_v3_cfg_t const usdhc4_pads[] = {
+static iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -144,7 +156,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6_PAD_NANDF_D6__GPIO2_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
-iomux_v3_cfg_t const enet_pads1[] = {
+static iomux_v3_cfg_t const enet_pads1[] = {
        MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -171,7 +183,7 @@ iomux_v3_cfg_t const enet_pads1[] = {
        MX6_PAD_ENET_RXD0__GPIO1_IO27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-iomux_v3_cfg_t const enet_pads2[] = {
+static iomux_v3_cfg_t const enet_pads2[] = {
        MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -189,7 +201,7 @@ static iomux_v3_cfg_t const misc_pads[] = {
 };
 
 /* wl1271 pads on nitrogen6x */
-iomux_v3_cfg_t const wl12xx_pads[] = {
+static iomux_v3_cfg_t const wl12xx_pads[] = {
        (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
                | MUX_PAD_CTRL(WEAK_PULLDOWN),
        (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
@@ -235,9 +247,10 @@ static void setup_iomux_enet(void)
        gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 
        imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+       udelay(100);    /* Wait 100 us before using mii interface */
 }
 
-iomux_v3_cfg_t const usb_pads[] = {
+static iomux_v3_cfg_t const usb_pads[] = {
        MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
@@ -271,7 +284,7 @@ int board_ehci_power(int port, int on)
 #endif
 
 #ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[2] = {
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
        {USDHC3_BASE_ADDR},
        {USDHC4_BASE_ADDR},
 };
@@ -279,17 +292,11 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = {
 int board_mmc_getcd(struct mmc *mmc)
 {
        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
-       int ret;
+       int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
+                       IMX_GPIO_NR(2, 6);
 
-       if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
-               gpio_direction_input(IMX_GPIO_NR(7, 0));
-               ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
-       } else {
-               gpio_direction_input(IMX_GPIO_NR(2, 6));
-               ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
-       }
-
-       return ret;
+       gpio_direction_input(gp_cd);
+       return !gpio_get_value(gp_cd);
 }
 
 int board_mmc_init(bd_t *bis)
@@ -333,7 +340,7 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
        return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 }
 
-iomux_v3_cfg_t const ecspi1_pads[] = {
+static iomux_v3_cfg_t const ecspi1_pads[] = {
        /* SS1 */
        MX6_PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL),
        MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
@@ -341,7 +348,7 @@ iomux_v3_cfg_t const ecspi1_pads[] = {
        MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 };
 
-void setup_spi(void)
+static void setup_spi(void)
 {
        imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
                                         ARRAY_SIZE(ecspi1_pads));
@@ -472,6 +479,17 @@ static void enable_lvds(struct display_info_t const *dev)
        gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 }
 
+static void enable_lvds_jeida(struct display_info_t const *dev)
+{
+       struct iomuxc *iomux = (struct iomuxc *)
+                               IOMUXC_BASE_ADDR;
+       u32 reg = readl(&iomux->gpr[2]);
+       reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+            |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
+       writel(reg, &iomux->gpr[2]);
+       gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+}
+
 static void enable_rgb(struct display_info_t const *dev)
 {
        imx_iomux_v3_setup_multiple_pads(
@@ -481,10 +499,10 @@ static void enable_rgb(struct display_info_t const *dev)
 }
 
 struct display_info_t const displays[] = {{
-       .bus    = -1,
-       .addr   = 0,
+       .bus    = 1,
+       .addr   = 0x50,
        .pixfmt = IPU_PIX_FMT_RGB24,
-       .detect = detect_hdmi,
+       .detect = detect_i2c,
        .enable = do_enable_hdmi,
        .mode   = {
                .name           = "HDMI",
@@ -500,6 +518,46 @@ struct display_info_t const displays[] = {{
                .vsync_len      = 10,
                .sync           = FB_SYNC_EXT,
                .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 0,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = NULL,
+       .enable = enable_lvds_jeida,
+       .mode   = {
+               .name           = "LDB-WXGA",
+               .refresh        = 60,
+               .xres           = 1280,
+               .yres           = 800,
+               .pixclock       = 14065,
+               .left_margin    = 40,
+               .right_margin   = 40,
+               .upper_margin   = 3,
+               .lower_margin   = 80,
+               .hsync_len      = 10,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 0,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = NULL,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "LDB-WXGA-S",
+               .refresh        = 60,
+               .xres           = 1280,
+               .yres           = 800,
+               .pixclock       = 14065,
+               .left_margin    = 40,
+               .right_margin   = 40,
+               .upper_margin   = 3,
+               .lower_margin   = 80,
+               .hsync_len      = 10,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
 } }, {
        .bus    = 2,
        .addr   = 0x4,
@@ -520,6 +578,26 @@ struct display_info_t const displays[] = {{
                .vsync_len      = 10,
                .sync           = FB_SYNC_EXT,
                .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 0,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .detect = NULL,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "LG-9.7",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 768,
+               .pixclock       = 15385, /* ~65MHz */
+               .left_margin    = 480,
+               .right_margin   = 260,
+               .upper_margin   = 16,
+               .lower_margin   = 6,
+               .hsync_len      = 250,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
 } }, {
        .bus    = 2,
        .addr   = 0x38,
@@ -540,6 +618,86 @@ struct display_info_t const displays[] = {{
                .vsync_len      = 10,
                .sync           = FB_SYNC_EXT,
                .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 2,
+       .addr   = 0x10,
+       .pixfmt = IPU_PIX_FMT_RGB666,
+       .detect = detect_i2c,
+       .enable = enable_rgb,
+       .mode   = {
+               .name           = "fusion7",
+               .refresh        = 60,
+               .xres           = 800,
+               .yres           = 480,
+               .pixclock       = 33898,
+               .left_margin    = 96,
+               .right_margin   = 24,
+               .upper_margin   = 3,
+               .lower_margin   = 10,
+               .hsync_len      = 72,
+               .vsync_len      = 7,
+               .sync           = 0x40000002,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 0,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB666,
+       .detect = NULL,
+       .enable = enable_rgb,
+       .mode   = {
+               .name           = "svga",
+               .refresh        = 60,
+               .xres           = 800,
+               .yres           = 600,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = 0,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 2,
+       .addr   = 0x41,
+       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .detect = detect_i2c,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "amp1024x600",
+               .refresh        = 60,
+               .xres           = 1024,
+               .yres           = 600,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 0,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_LVDS666,
+       .detect = 0,
+       .enable = enable_lvds,
+       .mode   = {
+               .name           = "wvga-lvds",
+               .refresh        = 57,
+               .xres           = 800,
+               .yres           = 480,
+               .pixclock       = 15385,
+               .left_margin    = 220,
+               .right_margin   = 40,
+               .upper_margin   = 21,
+               .lower_margin   = 7,
+               .hsync_len      = 60,
+               .vsync_len      = 10,
+               .sync           = FB_SYNC_EXT,
+               .vmode          = FB_VMODE_NONINTERLACED
 } }, {
        .bus    = 2,
        .addr   = 0x48,
@@ -560,9 +718,34 @@ struct display_info_t const displays[] = {{
                .vsync_len      = 10,
                .sync           = 0,
                .vmode          = FB_VMODE_NONINTERLACED
+} }, {
+       .bus    = 0,
+       .addr   = 0,
+       .pixfmt = IPU_PIX_FMT_RGB24,
+       .detect = NULL,
+       .enable = enable_rgb,
+       .mode   = {
+               .name           = "qvga",
+               .refresh        = 60,
+               .xres           = 320,
+               .yres           = 240,
+               .pixclock       = 37037,
+               .left_margin    = 38,
+               .right_margin   = 37,
+               .upper_margin   = 16,
+               .lower_margin   = 15,
+               .hsync_len      = 30,
+               .vsync_len      = 3,
+               .sync           = 0,
+               .vmode          = FB_VMODE_NONINTERLACED
 } } };
 size_t display_count = ARRAY_SIZE(displays);
 
+int board_cfb_skip(void)
+{
+       return NULL != getenv("novideo");
+}
+
 static void setup_display(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -619,17 +802,62 @@ static void setup_display(void)
 }
 #endif
 
+static iomux_v3_cfg_t const init_pads[] = {
+       /* SGTL5000 sys_mclk */
+       NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
+
+       /* J5 - Camera MCLK */
+       NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
+
+       /* wl1271 pads on nitrogen6x */
+       /* WL12XX_WL_IRQ_GP */
+       NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
+       /* WL12XX_WL_ENABLE_GP */
+       NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
+       /* WL12XX_BT_ENABLE_GP */
+       NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
+       /* USB otg power */
+       NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
+       NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
+       NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
+       NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
+       NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
+};
+
+#define WL12XX_WL_IRQ_GP       IMX_GPIO_NR(6, 14)
+
+static unsigned gpios_out_low[] = {
+       /* Disable wl1271 */
+       IMX_GPIO_NR(6, 15),     /* disable wireless */
+       IMX_GPIO_NR(6, 16),     /* disable bluetooth */
+       IMX_GPIO_NR(3, 22),     /* disable USB otg power */
+       IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
+       IMX_GPIO_NR(1, 8),      /* ov5642 reset */
+};
+
+static unsigned gpios_out_high[] = {
+       IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
+       IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
+};
+
+static void set_gpios(unsigned *p, int cnt, int val)
+{
+       int i;
+
+       for (i = 0; i < cnt; i++)
+               gpio_direction_output(*p++, val);
+}
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();
 
-       /* Disable wl1271 For Nitrogen6w */
+       set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+       set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
        gpio_direction_input(WL12XX_WL_IRQ_GP);
-       gpio_direction_output(WL12XX_WL_ENABLE_GP, 0);
-       gpio_direction_output(WL12XX_BT_ENABLE_GP, 0);
-       gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
 
        imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
+       imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
        setup_buttons();
 
 #if defined(CONFIG_VIDEO_IPUV3)
@@ -663,6 +891,8 @@ int board_init(void)
 #ifdef CONFIG_MXC_SPI
        setup_spi();
 #endif
+       imx_iomux_v3_setup_multiple_pads(
+               usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
        setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
        setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
        setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
index 85442cd..2df3ada 100644 (file)
 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN        1
 #endif
 
+#ifndef CONFIG_SYS_I2C_EEPROM_BUS
+#define CONFIG_SYS_I2C_EEPROM_BUS      0
+#endif
+
 #define EEPROM_LAYOUT_VER_OFFSET       44
 #define BOARD_SERIAL_OFFSET            20
 #define BOARD_SERIAL_OFFSET_LEGACY     8
diff --git a/board/congatec/cgtqmx6eval/imximage.cfg b/board/congatec/cgtqmx6eval/imximage.cfg
new file mode 100644 (file)
index 0000000..bb6c60b
--- /dev/null
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1           --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
index 42c19d1..52cf7f9 100644 (file)
@@ -1,6 +1,10 @@
 MX6QARM2 BOARD
 M:     Jason Liu <r64343@freescale.com>
+M:     Ye Li <b37916@freescale.com>
 S:     Maintained
 F:     board/freescale/mx6qarm2/
 F:     include/configs/mx6qarm2.h
 F:     configs/mx6qarm2_defconfig
+F:     configs/mx6dlarm2_defconfig
+F:     configs/mx6qarm2_lpddr2_defconfig
+F:     configs/mx6dlarm2_lpddr2_defconfig
index 710f34d..c85bde5 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
  * Jason Liu <r64343@freescale.com>
  *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -30,6 +30,185 @@ BOOT_FROM   sd
  *     Address   absolute address of the register
  *     value     value to be stored in the register
  */
+#ifdef CONFIG_MX6DQ_LPDDR2
+/* DCD */
+DATA 4 0x020C4018 0x60324
+
+DATA 4 0x020E05a8 0x00003038
+DATA 4 0x020E05b0 0x00003038
+DATA 4 0x020E0524 0x00003038
+DATA 4 0x020E051c 0x00003038
+
+DATA 4 0x020E0518 0x00003038
+DATA 4 0x020E050c 0x00003038
+DATA 4 0x020E05b8 0x00003038
+DATA 4 0x020E05c0 0x00003038
+
+DATA 4 0x020E05ac 0x00000038
+DATA 4 0x020E05b4 0x00000038
+DATA 4 0x020E0528 0x00000038
+DATA 4 0x020E0520 0x00000038
+
+DATA 4 0x020E0514 0x00000038
+DATA 4 0x020E0510 0x00000038
+DATA 4 0x020E05bc 0x00000038
+DATA 4 0x020E05c4 0x00000038
+
+DATA 4 0x020E056c 0x00000038
+DATA 4 0x020E0578 0x00000038
+DATA 4 0x020E0588 0x00000038
+DATA 4 0x020E0594 0x00000038
+
+DATA 4 0x020E057c 0x00000038
+DATA 4 0x020E0590 0x00000038
+DATA 4 0x020E0598 0x00000038
+DATA 4 0x020E058c 0x00000000
+
+DATA 4 0x020E059c 0x00000038
+DATA 4 0x020E05a0 0x00000038
+DATA 4 0x020E0784 0x00000038
+DATA 4 0x020E0788 0x00000038
+
+DATA 4 0x020E0794 0x00000038
+DATA 4 0x020E079c 0x00000038
+DATA 4 0x020E07a0 0x00000038
+DATA 4 0x020E07a4 0x00000038
+
+DATA 4 0x020E07a8 0x00000038
+DATA 4 0x020E0748 0x00000038
+DATA 4 0x020E074c 0x00000038
+DATA 4 0x020E0750 0x00020000
+
+DATA 4 0x020E0758 0x00000000
+DATA 4 0x020E0774 0x00020000
+DATA 4 0x020E078c 0x00000038
+DATA 4 0x020E0798 0x00080000
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b401c 0x00008000
+
+DATA 4 0x021b085c 0x1b5f01ff
+DATA 4 0x021b485c 0x1b5f01ff
+
+DATA 4 0x021b0800 0xa1390000
+DATA 4 0x021b4800 0xa1390000
+
+DATA 4 0x021b0890 0x00400000
+DATA 4 0x021b4890 0x00400000
+
+DATA 4 0x021b48bc 0x00055555
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b482c 0xf3333333
+DATA 4 0x021b4830 0xf3333333
+DATA 4 0x021b4834 0xf3333333
+DATA 4 0x021b4838 0xf3333333
+
+DATA 4 0x021b0848 0x49383b39
+DATA 4 0x021b0850 0x30364738
+DATA 4 0x021b4848 0x3e3c3846
+DATA 4 0x021b4850 0x4c294b35
+
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x0
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x0
+
+DATA 4 0x021b0858 0xf00
+DATA 4 0x021b4858 0xf00
+
+DATA 4 0x021b08b8 0x800
+DATA 4 0x021b48b8 0x800
+
+DATA 4 0x021b000c 0x555a61a5
+DATA 4 0x021b0004 0x20036
+DATA 4 0x021b0010 0x160e83
+DATA 4 0x021b0014 0xdd
+DATA 4 0x021b0018 0x8174c
+DATA 4 0x021b002c 0xf9f26d2
+DATA 4 0x021b0030 0x20e
+DATA 4 0x021b0038 0x200aac
+DATA 4 0x021b0008 0x0
+
+DATA 4 0x021b0040 0x5f
+
+DATA 4 0x021b0000 0xc3010000
+
+DATA 4 0x021b400c 0x555a61a5
+DATA 4 0x021b4004 0x20036
+DATA 4 0x021b4010 0x160e83
+DATA 4 0x021b4014 0xdd
+DATA 4 0x021b4018 0x8174c
+DATA 4 0x021b402c 0xf9f26d2
+DATA 4 0x021b4030 0x20e
+DATA 4 0x021b4038 0x200aac
+DATA 4 0x021b4008 0x0
+
+DATA 4 0x021b4040 0x3f
+DATA 4 0x021b4000 0xc3010000
+
+DATA 4 0x021b001c 0x3f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0xc2018030
+DATA 4 0x021b001c 0x6028030
+DATA 4 0x021b001c 0x2038030
+
+DATA 4 0x021b401c 0x3f8030
+DATA 4 0x021b401c 0xff0a8030
+DATA 4 0x021b401c 0xc2018030
+DATA 4 0x021b401c 0x6028030
+DATA 4 0x021b401c 0x2038030
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+
+DATA 4 0x021b0020 0x7800
+DATA 4 0x021b4020 0x7800
+
+DATA 4 0x021b0818 0x0
+DATA 4 0x021b4818 0x0
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+
+DATA 4 0x021b08b8 0x800
+DATA 4 0x021b48b8 0x800
+
+DATA 4 0x021b001c 0x0
+DATA 4 0x021b401c 0x0
+
+DATA 4 0x021b0404 0x00011006
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#else
 DATA 4 0x020e05a8 0x00000030
 DATA 4 0x020e05b0 0x00000030
 DATA 4 0x020e0524 0x00000030
@@ -142,12 +321,8 @@ DATA 4 0x021b48b8 0x00000800
 DATA 4 0x021b001c 0x00000000
 DATA 4 0x021b0404 0x00011006
 
-DATA 4 0x020e0010 0xF00000FF
-DATA 4 0x020e0018 0x00070007
-DATA 4 0x020e001c 0x00070007
-
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF00000
 DATA 4 0x020c4078 0x00FFF300
@@ -159,3 +334,5 @@ DATA 4 0x020e0010 0xF00000CF
 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
 DATA 4 0x020e0018 0x007F007F
 DATA 4 0x020e001c 0x007F007F
+
+#endif /* CONFIG_MX6DQ_LPDDR2 */
diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
new file mode 100644 (file)
index 0000000..ae8dcc6
--- /dev/null
@@ -0,0 +1,462 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *     Addr-type register length (1,2 or 4 bytes)
+ *     Address   absolute address of the register
+ *     value     value to be stored in the register
+ */
+
+
+
+#ifdef CONFIG_MX6DL_LPDDR2
+
+/* IOMUX SETTINGS */
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
+DATA 4 0x020E04bc 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
+DATA 4 0x020E04c0 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
+DATA 4 0x020E04c4 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
+DATA 4 0x020E04c8 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
+DATA 4 0x020E04cc 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
+DATA 4 0x020E04d0 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
+DATA 4 0x020E04d4 0x00003028
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
+DATA 4 0x020E04d8 0x00003028
+
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
+DATA 4 0x020E0470 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
+DATA 4 0x020E0474 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
+DATA 4 0x020E0478 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
+DATA 4 0x020E047c 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
+DATA 4 0x020E0480 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
+DATA 4 0x020E0484 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
+DATA 4 0x020E0488 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
+DATA 4 0x020E048c 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
+DATA 4 0x020E0464 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
+DATA 4 0x020E0490 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
+DATA 4 0x020E04ac 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
+DATA 4 0x020E04b0 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
+DATA 4 0x020E0494 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 */
+DATA 4 0x020E04a4 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 */
+DATA 4 0x020E04a8 0x00000038
+/*
+ * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+ * DSE can be configured using Group Control Register:
+ * IOMUXC_SW_PAD_CTL_GRP_CTLDS
+ */
+DATA 4 0x020E04a0 0x00000000
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
+DATA 4 0x020E04b4 0x00000038
+/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
+DATA 4 0x020E04b8 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B0DS */
+DATA 4 0x020E0764 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B1DS */
+DATA 4 0x020E0770 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B2DS */
+DATA 4 0x020E0778 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B3DS */
+DATA 4 0x020E077c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B4DS */
+DATA 4 0x020E0780 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B5DS */
+DATA 4 0x020E0784 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B6DS */
+DATA 4 0x020E078c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_B7DS */
+DATA 4 0x020E0748 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
+DATA 4 0x020E074c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
+DATA 4 0x020E076c 0x00000038
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
+DATA 4 0x020E0750 0x00020000
+/* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
+DATA 4 0x020E0754 0x00000000
+/* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
+DATA 4 0x020E0760 0x00020000
+/* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
+DATA 4 0x020E0774 0x00080000
+
+/*
+ * DDR Controller Registers
+ *
+ * Manufacturer:       Mocron
+ * Device Part Number: MT42L64M64D2KH-18
+ * Clock Freq.:        528MHz
+ * MMDC channels: Both MMDC0, MMDC1
+ *Density per CS in Gb:        256M
+ * Chip Selects used:  2
+ * Number of Banks:    8
+ * Row address:        14
+ * Column address:     9
+ * Data bus width      32
+ */
+
+/* MMDC_P0_BASE_ADDR = 0x021b0000 */
+/* MMDC_P1_BASE_ADDR = 0x021b4000 */
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+DATA 4 0x021b001c 0x00008000
+
+/* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
+DATA 4 0x021b401c 0x00008000
+
+/*LPDDR2 ZQ params */
+DATA 4 0x021b085c 0x1b5f01ff
+DATA 4 0x021b485c 0x1b5f01ff
+
+/* Calibration setup. */
+/* DDR_PHY_P0_MPZQHWCTRL, enable on time ZQ calibration */
+DATA 4 0x021b0800 0xa1390003
+
+/*ca bus abs delay */
+DATA 4 0x021b0890 0x00400000
+/*ca bus abs delay */
+DATA 4 0x021b4890 0x00400000
+/* values of 20,40,50,60,7f tried. no difference seen */
+
+/* DDR_PHY_P1_MPWRCADL */
+DATA 4 0x021b48bc 0x00055555
+
+/*frc_msr.*/
+DATA 4 0x021b08b8 0x00000800
+/*frc_msr.*/
+DATA 4 0x021b48b8 0x00000800
+
+/* DDR_PHY_P0_MPREDQBY0DL3 */
+DATA 4 0x021b081c 0x33333333
+/* DDR_PHY_P0_MPREDQBY1DL3 */
+DATA 4 0x021b0820 0x33333333
+/* DDR_PHY_P0_MPREDQBY2DL3 */
+DATA 4 0x021b0824 0x33333333
+/* DDR_PHY_P0_MPREDQBY3DL3 */
+DATA 4 0x021b0828 0x33333333
+/* DDR_PHY_P1_MPREDQBY0DL3 */
+DATA 4 0x021b481c 0x33333333
+/* DDR_PHY_P1_MPREDQBY1DL3 */
+DATA 4 0x021b4820 0x33333333
+/* DDR_PHY_P1_MPREDQBY2DL3 */
+DATA 4 0x021b4824 0x33333333
+/* DDR_PHY_P1_MPREDQBY3DL3 */
+DATA 4 0x021b4828 0x33333333
+
+/*
+ * Read and write data delay, per byte.
+ * For optimized DDR operation it is recommended to run mmdc_calibration
+ * on your board, and replace 4 delay register assigns with resulted values
+ * Note:
+ * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
+ *    should be skipped, or the write/read calibration comming after that
+ *    will stall
+ * b. The calibration code that runs for both MMDC0 & MMDC1 should be used.
+ */
+
+DATA 4 0x021b0848 0x4b4b524f
+DATA 4 0x021b4848 0x494f4c44
+
+DATA 4 0x021b0850 0x3c3d303c
+DATA 4 0x021b4850 0x3c343d38
+
+/*dqs gating dis */
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x0
+DATA 4 0x021b483c 0x20000000
+DATA 4 0x021b4840 0x0
+
+/*clk delay */
+DATA 4 0x021b0858 0xa00
+/*clk delay */
+DATA 4 0x021b4858 0xa00
+
+/*frc_msr */
+DATA 4 0x021b08b8 0x00000800
+/*frc_msr */
+DATA 4 0x021b48b8 0x00000800
+/* Calibration setup end */
+
+/* Channel0 - startng address 0x80000000 */
+/* MMDC0_MDCFG0 */
+DATA 4 0x021b000c 0x34386145
+
+/* MMDC0_MDPDC */
+DATA 4 0x021b0004 0x00020036
+/* MMDC0_MDCFG1 */
+DATA 4 0x021b0010 0x00100c83
+/* MMDC0_MDCFG2 */
+DATA 4 0x021b0014 0x000000Dc
+/* MMDC0_MDMISC */
+DATA 4 0x021b0018 0x0000174C
+/* MMDC0_MDRWD;*/
+DATA 4 0x021b002c 0x0f9f26d2
+/* MMDC0_MDOR */
+DATA 4 0x021b0030 0x0000020e
+/* MMDC0_MDCFG3LP */
+DATA 4 0x021b0038 0x00190778
+/* MMDC0_MDOTC */
+DATA 4 0x021b0008 0x00000000
+
+/* CS0_END */
+DATA 4 0x021b0040 0x0000005f
+/* ROC */
+DATA 4 0x021b0404 0x0000000f
+
+/* MMDC0_MDCTL */
+DATA 4 0x021b0000 0xc3010000
+
+/* Channel1 - starting address 0x10000000 */
+/* MMDC1_MDCFG0 */
+DATA 4 0x021b400c 0x34386145
+
+/* MMDC1_MDPDC */
+DATA 4 0x021b4004 0x00020036
+/* MMDC1_MDCFG1 */
+DATA 4 0x021b4010 0x00100c83
+/* MMDC1_MDCFG2 */
+DATA 4 0x021b4014 0x000000Dc
+/* MMDC1_MDMISC */
+DATA 4 0x021b4018 0x0000174C
+/* MMDC1_MDRWD;*/
+DATA 4 0x021b402c 0x0f9f26d2
+/* MMDC1_MDOR */
+DATA 4 0x021b4030 0x0000020e
+/* MMDC1_MDCFG3LP */
+DATA 4 0x021b4038 0x00190778
+/* MMDC1_MDOTC */
+DATA 4 0x021b4008 0x00000000
+
+/* CS0_END */
+DATA 4 0x021b4040 0x0000003f
+
+/* MMDC1_MDCTL */
+DATA 4 0x021b4000 0xc3010000
+
+/* Channel0 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+DATA 4 0x021b001c 0x003f8030
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+DATA 4 0x021b001c 0xff0a8030
+/* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
+DATA 4 0x021b001c 0xa2018030
+/* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
+DATA 4 0x021b001c 0x06028030
+/* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
+DATA 4 0x021b001c 0x01038030
+
+/* Channel1 : Configure DDR device:*/
+/* MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 */
+DATA 4 0x021b401c 0x003f8030
+/* MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=ff */
+DATA 4 0x021b401c 0xff0a8030
+/* MRW: BA=0 CS=0 MR_ADDR=1  MR_OP=a2 */
+DATA 4 0x021b401c 0xa2018030
+/* MRW: BA=0 CS=0 MR_ADDR=2  MR_OP=6. tcl=8, tcwl=4 */
+DATA 4 0x021b401c 0x06028030
+/* MRW: BA=0 CS=0 MR_ADDR=3  MR_OP=2.drive=240/6 */
+DATA 4 0x021b401c 0x01038030
+
+/* MMDC0_MDREF */
+DATA 4 0x021b0020 0x00005800
+/* MMDC1_MDREF */
+DATA 4 0x021b4020 0x00005800
+
+/* DDR_PHY_P0_MPODTCTRL */
+DATA 4 0x021b0818 0x0
+/* DDR_PHY_P1_MPODTCTRL */
+DATA 4 0x021b4818 0x0
+
+/*
+ * calibration values based on calibration compare of 0x00ffff00:
+ * Note, these calibration values are based on Freescale's board
+ * May need to run calibration on target board to fine tune these
+ */
+
+/* DDR_PHY_P0_MPZQHWCTRL, enable automatic ZQ calibration */
+DATA 4 0x021b0800 0xa1310003
+
+/* DDR_PHY_P0_MPMUR0, frc_msr */
+DATA 4 0x021b08b8 0x00000800
+/* DDR_PHY_P1_MPMUR0, frc_msr */
+DATA 4 0x021b48b8 0x00000800
+
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+DATA 4 0x021b001c 0x00000000
+/*
+ * MMDC0_MDSCR, clear this register
+ * (especially the configuration bit as initialization is complete)
+ */
+DATA 4 0x021b401c 0x00000000
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+DATA 4 0x020e0010 0xF00000CF
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+#else /* CONFIG_MX6DL_LPDDR2 */
+
+DATA 4 0x020e0798 0x000c0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x00370037
+DATA 4 0x021b4810 0x00370037
+DATA 4 0x021b083c 0x422f0220
+DATA 4 0x021b0840 0x021f0219
+DATA 4 0x021b483C 0x422f0220
+DATA 4 0x021b4840 0x022d022f
+DATA 4 0x021b0848 0x47494b49
+DATA 4 0x021b4848 0x48484c47
+DATA 4 0x021b0850 0x39382b2f
+DATA 4 0x021b4850 0x2f35312c
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+
+DATA 4 0x021b000c 0x40445323
+DATA 4 0x021b0010 0xb66e8c63
+
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00081740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x00440e21
+#ifdef CONFIG_DDR_32BIT
+DATA 4 0x021b0040 0x00000017
+DATA 4 0x021b0000 0xc3190000
+#else
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0xc31a0000
+#endif
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x0400803a
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803b
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x07208030
+DATA 4 0x021b001c 0x07208038
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00000007
+DATA 4 0x021b4818 0x00000007
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b4004 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+DATA 4 0x020e0010 0xF00000CF
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif /* CONFIG_MX6DL_LPDDR2 */
index 6c51f3a..667dca5 100644 (file)
@@ -32,7 +32,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
+       defined(CONFIG_DDR_32BIT)
+       gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
+#else
+       gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+#endif
 
        return 0;
 }
@@ -224,7 +229,11 @@ int board_init(void)
 
 int checkboard(void)
 {
+#ifdef CONFIG_MX6DL
+       puts("Board: MX6DL-Armadillo2\n");
+#else
        puts("Board: MX6Q-Armadillo2\n");
+#endif
 
        return 0;
 }
index 836d722..1cb7561 100644 (file)
@@ -50,12 +50,12 @@ int dram_init(void)
        return 0;
 }
 
-iomux_v3_cfg_t const uart4_pads[] = {
+static iomux_v3_cfg_t const uart4_pads[] = {
        MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-iomux_v3_cfg_t const enet_pads[] = {
+static iomux_v3_cfg_t const enet_pads[] = {
        MX6_PAD_KEY_COL1__ENET_MDIO             | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6_PAD_KEY_COL2__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
        MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -74,7 +74,7 @@ iomux_v3_cfg_t const enet_pads[] = {
 };
 
 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
-struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
        .scl = {
                .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
                .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
@@ -91,7 +91,7 @@ struct i2c_pads_info i2c_pad_info1 = {
  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  * Compass Sensor, Accelerometer, Res Touch
  */
-struct i2c_pads_info i2c_pad_info2 = {
+static struct i2c_pads_info i2c_pad_info2 = {
        .scl = {
                .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
                .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
@@ -104,11 +104,11 @@ struct i2c_pads_info i2c_pad_info2 = {
        }
 };
 
-iomux_v3_cfg_t const i2c3_pads[] = {
+static iomux_v3_cfg_t const i2c3_pads[] = {
        MX6_PAD_EIM_A24__GPIO5_IO04             | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-iomux_v3_cfg_t const port_exp[] = {
+static iomux_v3_cfg_t const port_exp[] = {
        MX6_PAD_SD2_DAT0__GPIO1_IO15            | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
@@ -117,7 +117,7 @@ static void setup_iomux_enet(void)
        imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 }
 
-iomux_v3_cfg_t const usdhc3_pads[] = {
+static iomux_v3_cfg_t const usdhc3_pads[] = {
        MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
        MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -138,7 +138,7 @@ static void setup_iomux_uart(void)
 }
 
 #ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
        {USDHC3_BASE_ADDR},
 };
 
diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
new file mode 100644 (file)
index 0000000..bb6c60b
--- /dev/null
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1           --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
index 5eaec1b..68d3718 100644 (file)
@@ -157,7 +157,7 @@ int board_eth_init(bd_t *bis)
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 /* I2C1 for PMIC */
-struct i2c_pads_info i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
        .scl = {
                .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
                .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
index 56a09c9..f2997f0 100644 (file)
@@ -4,3 +4,4 @@ S:      Maintained
 F:     board/freescale/vf610twr/
 F:     include/configs/vf610twr.h
 F:     configs/vf610twr_defconfig
+F:     configs/vf610twr_nand_defconfig
index 54a9f2c..b634965 100644 (file)
@@ -45,6 +45,7 @@ void setup_iomux_ddr(void)
                VF610_PAD_DDR_A3__DDR_A_3,
                VF610_PAD_DDR_A2__DDR_A_2,
                VF610_PAD_DDR_A1__DDR_A_1,
+               VF610_PAD_DDR_A0__DDR_A_0,
                VF610_PAD_DDR_BA2__DDR_BA_2,
                VF610_PAD_DDR_BA1__DDR_BA_1,
                VF610_PAD_DDR_BA0__DDR_BA_0,
@@ -76,6 +77,7 @@ void setup_iomux_ddr(void)
                VF610_PAD_DDR_WE__DDR_WE_B,
                VF610_PAD_DDR_ODT1__DDR_ODT_0,
                VF610_PAD_DDR_ODT0__DDR_ODT_1,
+               VF610_PAD_DDR_RESETB,
        };
 
        imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
@@ -88,30 +90,30 @@ void ddr_phy_init(void)
        writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
        writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
        writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
-       writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
 
        writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
        writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
-       writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
-       writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
 
        writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
        writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
        writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
-       writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
 
        writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
        writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
        writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
-       writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
 
        writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
        writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
        writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
-       writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+       /* LPDDR2 only parameter */
+       writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
 
        writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
                &ddrmr->phy[50]);
+
+       /* Processor Pad ODT settings */
+       writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
 }
 
 void ddr_ctrl_init(void)
@@ -120,12 +122,12 @@ void ddr_ctrl_init(void)
 
        writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
        writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
-       writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+       writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
 
-       writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+       writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]);
        writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
-       writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
-               DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+       writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4),
+               &ddrmr->cr[13]);
        writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
                DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
        writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
@@ -134,24 +136,23 @@ void ddr_ctrl_init(void)
        writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
 
        writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
-       writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
-               DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+       writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
 
-       writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+       writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]);
        writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
        writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
 
        writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
-       writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
-       writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+       writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+       writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
        writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
 
        writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
-       writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+       writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]);
        writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
        writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
 
-       writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+       writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
        writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
                DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
 
@@ -164,37 +165,45 @@ void ddr_ctrl_init(void)
        writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
 
        writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
-       writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+       writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
 
        writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
                DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
        writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
-               DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+               DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
                &ddrmr->cr[74]);
        writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
                DDRMC_CR75_PLEN, &ddrmr->cr[75]);
        writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
-               DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+               DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
        writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
                DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
-       writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
-       writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+       writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12),
+               &ddrmr->cr[78]);
+       writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
 
        writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
 
-       writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
-               &ddrmr->cr[87]);
+       writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
        writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
        writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
 
        writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
        writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+       writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
+       writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
+       writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
+
+       writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
+               &ddrmr->cr[102]);
 
-       writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
-       writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
-       writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+       writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
+       writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
+       writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
+       writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
+       writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
 
-       writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+       writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0),
                &ddrmr->cr[117]);
        writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
                &ddrmr->cr[118]);
@@ -205,23 +214,40 @@ void ddr_ctrl_init(void)
                &ddrmr->cr[121]);
        writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
                DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
-       writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
-               &ddrmr->cr[123]);
+       writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+               DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
        writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
 
-       writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+       writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
        writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
                &ddrmr->cr[132]);
+       writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
+       writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1),
+               &ddrmr->cr[138]);
        writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
                DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
                &ddrmr->cr[139]);
+       writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
+       writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128),
+               &ddrmr->cr[143]);
+       writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+               DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3),
+               &ddrmr->cr[144]);
+       writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
+       writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
+       writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
+       writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
+       writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+               DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
 
        writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-               DDRMC_CR154_PAD_ZQ_MODE(1) |
-               DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
-       writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
+               DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+               DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
+       writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2),
                &ddrmr->cr[155]);
        writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+       writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+               DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
 
        ddr_phy_init();
 
@@ -278,6 +304,39 @@ static void setup_iomux_i2c(void)
        imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
 }
 
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+       static const iomux_v3_cfg_t nfc_pads[] = {
+               VF610_PAD_PTD31__NF_IO15,
+               VF610_PAD_PTD30__NF_IO14,
+               VF610_PAD_PTD29__NF_IO13,
+               VF610_PAD_PTD28__NF_IO12,
+               VF610_PAD_PTD27__NF_IO11,
+               VF610_PAD_PTD26__NF_IO10,
+               VF610_PAD_PTD25__NF_IO9,
+               VF610_PAD_PTD24__NF_IO8,
+               VF610_PAD_PTD23__NF_IO7,
+               VF610_PAD_PTD22__NF_IO6,
+               VF610_PAD_PTD21__NF_IO5,
+               VF610_PAD_PTD20__NF_IO4,
+               VF610_PAD_PTD19__NF_IO3,
+               VF610_PAD_PTD18__NF_IO2,
+               VF610_PAD_PTD17__NF_IO1,
+               VF610_PAD_PTD16__NF_IO0,
+               VF610_PAD_PTB24__NF_WE_B,
+               VF610_PAD_PTB25__NF_CE0_B,
+               VF610_PAD_PTB27__NF_RE_B,
+               VF610_PAD_PTC26__NF_RB_B,
+               VF610_PAD_PTC27__NF_ALE,
+               VF610_PAD_PTC28__NF_CLE
+       };
+
+       imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+
 static void setup_iomux_qspi(void)
 {
        static const iomux_v3_cfg_t qspi0_pads[] = {
@@ -354,6 +413,8 @@ static void clock_init(void)
                CCM_CCGR7_SDHC1_CTRL_MASK);
        clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
                CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+       clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+               CCM_CCGR10_NFC_CTRL_MASK);
 
        clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
                ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
@@ -373,14 +434,17 @@ static void clock_init(void)
                CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
                CCM_CACRR_ARM_CLK_DIV(0));
        clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
-               CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
+               CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
+               CCM_CSCMR1_NFC_CLK_SEL(0));
        clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
                CCM_CSCDR1_RMII_CLK_EN);
        clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
-               CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+               CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+               CCM_CSCDR2_NFC_EN);
        clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
                CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
-               CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
+               CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
+               CCM_CSCDR3_NFC_PRE_DIV(5));
        clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
                CCM_CSCMR2_RMII_CLK_SEL(0));
 }
@@ -411,6 +475,9 @@ int board_early_init_f(void)
        setup_iomux_enet();
        setup_iomux_i2c();
        setup_iomux_qspi();
+#ifdef CONFIG_NAND_VF610_NFC
+       setup_iomux_nfc();
+#endif
 
        return 0;
 }
index 9fc253b..ca35b3c 100644 (file)
@@ -402,13 +402,6 @@ void board_init_f(ulong dummy)
        struct ventana_board_info ventana_info;
        int board_model;
 
-       /*
-        * Zero out global data:
-        *  - this shoudl be done by crt0.S
-        *  - failure to zero it will cause i2c_setup to fail
-        */
-       memset((void *)gd, 0, sizeof(struct global_data));
-
        /* setup AIPS and disable watchdog */
        arch_cpu_init();
 
index e2a03a1..313ab20 100644 (file)
@@ -30,13 +30,25 @@ int board_early_init_f(void)
        /* SSP0 clock at 96MHz */
        mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
 
+       return 0;
+}
+
 #ifdef CONFIG_CMD_USB
-       /* Enable LAN9512 */
+int board_ehci_hcd_init(int port)
+{
+       /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
        gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 1);
-#endif
+       udelay(100);
+       return 0;
+}
 
+int board_ehci_hcd_exit(int port)
+{
+       /* Enable LAN9512 (Maxi) or GL850G (Mini) USB HUB power. */
+       gpio_direction_output(MX23_PAD_GPMI_ALE__GPIO_0_17, 0);
        return 0;
 }
+#endif
 
 int dram_init(void)
 {
@@ -66,3 +78,33 @@ int board_init(void)
 
        return 0;
 }
+
+/* Fine-tune the DRAM configuration. */
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+       /* Enable Auto Precharge. */
+       dram_vals[3] |= 1 << 8;
+       /* Enable Fast Writes. */
+       dram_vals[5] |= 1 << 8;
+       /* tEMRS = 3*tCK */
+       dram_vals[10] &= ~(0x3 << 8);
+       dram_vals[10] |= (0x3 << 8);
+       /* CASLAT = 3*tCK */
+       dram_vals[11] &= ~(0x3 << 0);
+       dram_vals[11] |= (0x3 << 0);
+       /* tCKE = 1*tCK */
+       dram_vals[12] &= ~(0x7 << 0);
+       dram_vals[12] |= (0x1 << 0);
+       /* CASLAT_LIN_GATE = 3*tCK , CASLAT_LIN = 3*tCK, tWTR=2*tCK */
+       dram_vals[13] &= ~((0xf << 16) | (0xf << 24) | (0xf << 0));
+       dram_vals[13] |= (0x6 << 16) | (0x6 << 24) | (0x2 << 0);
+       /* tDAL = 6*tCK */
+       dram_vals[15] &= ~(0xf << 16);
+       dram_vals[15] |= (0x6 << 16);
+       /* tREF = 1040*tCK */
+       dram_vals[26] &= ~0xffff;
+       dram_vals[26] |= 0x0410;
+       /* tRAS_MAX = 9334*tCK */
+       dram_vals[32] &= ~0xffff;
+       dram_vals[32] |= 0x2475;
+}
index ea51f3f..d788aa0 100644 (file)
@@ -13,7 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/rmobile.h>
 
-/* QoS version 0.10 */
+/* QoS version 0.11 */
 
 enum {
        DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@@ -156,8 +156,8 @@ void qos_init(void)
        }
 
        /* CCI-400 -QoS */
-       writel(0x20001000, CCI_400_MAXOT_1);
-       writel(0x20001000, CCI_400_MAXOT_2);
+       writel(0x20000800, CCI_400_MAXOT_1);
+       writel(0x20000800, CCI_400_MAXOT_2);
        writel(0x0000000C, CCI_400_QOSCNTL_1);
        writel(0x0000000C, CCI_400_QOSCNTL_2);
 
index 55a0420..ecf3eed 100644 (file)
@@ -13,7 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/rmobile.h>
 
-/* QoS version 0.240 for ES1 and version 0.310 for ES2 */
+/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
 
 enum {
        DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@@ -116,10 +116,16 @@ void qos_init(void)
        /* S3C -QoS */
        s3c = (struct rcar_s3c *)S3C_BASE;
        if (IS_R8A7791_ES2()) {
-               writel(0x00FF1B0D, &s3c->s3cadsplcr);
-               writel(0x1F0D0B0A, &s3c->s3crorr);
-               writel(0x1F0D0B09, &s3c->s3cworr);
-               writel(0x00200808, &s3c->s3carcr11);
+               /* Linear All mode */
+               /* writel(0x00000000, &s3c->s3cadsplcr); */
+               /* Linear Linear 0x7000 to 0x7800 mode */
+               writel(0x00BF1B0C, &s3c->s3cadsplcr);
+               /* Split Linear 0x6800 t 0x7000 mode */
+               /* writel(0x00DF1B0C, &s3c->s3cadsplcr); */
+               /* Ssplit All mode */
+               /* writel(0x00FF1B0C, &s3c->s3cadsplcr); */
+               writel(0x1F0B0908, &s3c->s3crorr);
+               writel(0x1F0C0A08, &s3c->s3cworr);
        } else {
                writel(0x00FF1B1D, &s3c->s3cadsplcr);
                writel(0x1F0D0C0C, &s3c->s3crorr);
@@ -149,10 +155,7 @@ void qos_init(void)
        writel(0x00002032, &s3c_qos->s3cqos8);
 
        s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
-       if (IS_R8A7791_ES2())
-               writel(0x80928092, &s3c_qos->s3cqos0);
-       else
-               writel(0x00820082, &s3c_qos->s3cqos0);
+       writel(0x00820082, &s3c_qos->s3cqos0);
        writel(0x20960020, &s3c_qos->s3cqos1);
        writel(0x20302030, &s3c_qos->s3cqos2);
        writel(0x20AA20DC, &s3c_qos->s3cqos3);
@@ -185,7 +188,7 @@ void qos_init(void)
                writel(0x00000001, &qos_addr->dbrqctr);
                writel(0x00002078, &qos_addr->dbthres0);
                writel(0x0000204B, &qos_addr->dbthres1);
-               writel(0x00001FE7, &qos_addr->dbthres2);
+               writel(0x0000201E, &qos_addr->dbthres2);
                writel(0x00000001, &qos_addr->dblgqon);
        }
 
@@ -193,13 +196,13 @@ void qos_init(void)
        for (i = DBSC3_00; i < DBSC3_NR; i++) {
                qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
                writel(0x00000002, &qos_addr->dblgcnt);
-               writel(0x000020EB, &qos_addr->dbtmval0);
-               writel(0x0000206E, &qos_addr->dbtmval1);
+               writel(0x00002096, &qos_addr->dbtmval0);
+               writel(0x00002064, &qos_addr->dbtmval1);
                writel(0x00002050, &qos_addr->dbtmval2);
                writel(0x0000203A, &qos_addr->dbtmval3);
                writel(0x00000001, &qos_addr->dbrqctr);
                writel(0x00002078, &qos_addr->dbthres0);
-               writel(0x0000205A, &qos_addr->dbthres1);
+               writel(0x0000204B, &qos_addr->dbthres1);
                writel(0x0000203C, &qos_addr->dbthres2);
                writel(0x00000001, &qos_addr->dblgqon);
        }
@@ -215,7 +218,7 @@ void qos_init(void)
                writel(0x00000001, &qos_addr->dbrqctr);
                writel(0x00002078, &qos_addr->dbthres0);
                writel(0x0000204B, &qos_addr->dbthres1);
-               writel(0x00001FE7, &qos_addr->dbthres2);
+               writel(0x0000201E, &qos_addr->dbthres2);
                writel(0x00000001, &qos_addr->dblgqon);
        }
 
@@ -223,13 +226,13 @@ void qos_init(void)
        for (i = DBSC3_00; i < DBSC3_NR; i++) {
                qos_addr = (struct rcar_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
                writel(0x00000002, &qos_addr->dblgcnt);
-               writel(0x000020EB, &qos_addr->dbtmval0);
-               writel(0x0000206E, &qos_addr->dbtmval1);
+               writel(0x00002096, &qos_addr->dbtmval0);
+               writel(0x00002064, &qos_addr->dbtmval1);
                writel(0x00002050, &qos_addr->dbtmval2);
                writel(0x0000203A, &qos_addr->dbtmval3);
                writel(0x00000001, &qos_addr->dbrqctr);
                writel(0x00002078, &qos_addr->dbthres0);
-               writel(0x0000205A, &qos_addr->dbthres1);
+               writel(0x0000204B, &qos_addr->dbthres1);
                writel(0x0000203C, &qos_addr->dbthres2);
                writel(0x00000001, &qos_addr->dblgqon);
        }
@@ -245,14 +248,12 @@ void qos_init(void)
        mxi = (struct rcar_mxi *)MXI_BASE;
        writel(0x00000013, &mxi->mxrtcr);
        writel(0x00000013, &mxi->mxwtcr);
-       writel(0x00780080, &mxi->mxsaar0);
-       writel(0x02000800, &mxi->mxsaar1);
 
        /* QoS Control (MXI) */
        mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
        writel(0x0000000C, &mxi_qos->vspdu0);
        writel(0x0000000C, &mxi_qos->vspdu1);
-       writel(0x0000000D, &mxi_qos->du0);
+       writel(0x0000000E, &mxi_qos->du0);
        writel(0x0000000D, &mxi_qos->du1);
 
        /* AXI -QoS */
index a5a0474..5302839 100644 (file)
@@ -29,15 +29,17 @@ void s_init(void)
 {
        struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
        struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
-       u32 stc;
 
        /* Watchdog init */
        writel(0xA5A5A500, &rwdt->rwtcsra);
        writel(0xA5A5A500, &swdt->swtcsra);
 
        /* CPU frequency setting. Set to 1.4GHz */
-       stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT;
-       clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+       if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+               u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
+                       << PLL0_STC_BIT;
+               clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+       }
 
        /* QoS(Quality-of-Service) Init */
        qos_init();
index 3742757..ce7f8ba 100644 (file)
 #include <asm/io.h>
 #include <asm/arch/rmobile.h>
 
-/* QoS version 0.955 */
+/* QoS version 0.955 for ES1 and version 0.963 for ES2 */
 
 enum {
-       DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
-       DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09,
-       DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14,
-       DBSC3_R15,
-       DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04,
-       DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09,
-       DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14,
-       DBSC3_W15,
+       DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+       DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+       DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+       DBSC3_15,
        DBSC3_NR,
 };
 
-static const u32 dbsc3_qos_addr[DBSC3_NR] = {
-       [DBSC3_R00] = DBSC3_0_QOS_R0_BASE,
-       [DBSC3_R01] = DBSC3_0_QOS_R1_BASE,
-       [DBSC3_R02] = DBSC3_0_QOS_R2_BASE,
-       [DBSC3_R03] = DBSC3_0_QOS_R3_BASE,
-       [DBSC3_R04] = DBSC3_0_QOS_R4_BASE,
-       [DBSC3_R05] = DBSC3_0_QOS_R5_BASE,
-       [DBSC3_R06] = DBSC3_0_QOS_R6_BASE,
-       [DBSC3_R07] = DBSC3_0_QOS_R7_BASE,
-       [DBSC3_R08] = DBSC3_0_QOS_R8_BASE,
-       [DBSC3_R09] = DBSC3_0_QOS_R9_BASE,
-       [DBSC3_R10] = DBSC3_0_QOS_R10_BASE,
-       [DBSC3_R11] = DBSC3_0_QOS_R11_BASE,
-       [DBSC3_R12] = DBSC3_0_QOS_R12_BASE,
-       [DBSC3_R13] = DBSC3_0_QOS_R13_BASE,
-       [DBSC3_R14] = DBSC3_0_QOS_R14_BASE,
-       [DBSC3_R15] = DBSC3_0_QOS_R15_BASE,
-       [DBSC3_W00] = DBSC3_0_QOS_W0_BASE,
-       [DBSC3_W01] = DBSC3_0_QOS_W1_BASE,
-       [DBSC3_W02] = DBSC3_0_QOS_W2_BASE,
-       [DBSC3_W03] = DBSC3_0_QOS_W3_BASE,
-       [DBSC3_W04] = DBSC3_0_QOS_W4_BASE,
-       [DBSC3_W05] = DBSC3_0_QOS_W5_BASE,
-       [DBSC3_W06] = DBSC3_0_QOS_W6_BASE,
-       [DBSC3_W07] = DBSC3_0_QOS_W7_BASE,
-       [DBSC3_W08] = DBSC3_0_QOS_W8_BASE,
-       [DBSC3_W09] = DBSC3_0_QOS_W9_BASE,
-       [DBSC3_W10] = DBSC3_0_QOS_W10_BASE,
-       [DBSC3_W11] = DBSC3_0_QOS_W11_BASE,
-       [DBSC3_W12] = DBSC3_0_QOS_W12_BASE,
-       [DBSC3_W13] = DBSC3_0_QOS_W13_BASE,
-       [DBSC3_W14] = DBSC3_0_QOS_W14_BASE,
-       [DBSC3_W15] = DBSC3_0_QOS_W15_BASE,
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_R15_BASE,
 };
 
-void qos_init(void)
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+       [DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+       [DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+       [DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+       [DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+       [DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+       [DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+       [DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+       [DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+       [DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+       [DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+       [DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+       [DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+       [DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+       [DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+       [DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+       [DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+/* QoS version 0.955 for ES1 */
+static void qos_init_es1(void)
 {
        int i;
        struct rcar_s3c *s3c;
@@ -115,7 +115,6 @@ void qos_init(void)
        writel(0x20142032, &s3c_qos->s3cqos8);
 
        s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
-
        writel(0x00810089, &s3c_qos->s3cqos0);
        writel(0x20410001, &s3c_qos->s3cqos1);
        writel(0x200A2023, &s3c_qos->s3cqos2);
@@ -129,9 +128,24 @@ void qos_init(void)
        writel(0x00200808, &s3c->s3carcr11);
 
        /* DBSC -QoS */
-       /* DBSC0 - Read/Write */
-       for (i = DBSC3_R00; i < DBSC3_NR; i++) {
-               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_qos_addr[i];
+       /* DBSC0 - Read */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+               writel(0x00000203, &qos_addr->dblgcnt);
+               writel(0x00002064, &qos_addr->dbtmval0);
+               writel(0x00002048, &qos_addr->dbtmval1);
+               writel(0x00002032, &qos_addr->dbtmval2);
+               writel(0x00002019, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002019, &qos_addr->dbthres0);
+               writel(0x00002019, &qos_addr->dbthres1);
+               writel(0x00002019, &qos_addr->dbthres2);
+               writel(0x00000000, &qos_addr->dblgqon);
+       }
+
+       /* DBSC0 - Write */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
                writel(0x00000203, &qos_addr->dblgcnt);
                writel(0x00002064, &qos_addr->dbtmval0);
                writel(0x00002048, &qos_addr->dbtmval1);
@@ -143,6 +157,7 @@ void qos_init(void)
                writel(0x00002019, &qos_addr->dbthres2);
                writel(0x00000000, &qos_addr->dblgqon);
        }
+
        /* CCI-400 -QoS */
        writel(0x20001000, CCI_400_MAXOT_1);
        writel(0x20001000, CCI_400_MAXOT_2);
@@ -1117,3 +1132,1252 @@ void qos_init(void)
        writel(0x00000001, &axi_qos->qosthres2);
        writel(0x00000000, &axi_qos->qosqon);
 }
+
+/* QoS version 0.963 for ES2 */
+static void qos_init_es2(void)
+{
+       int i;
+       struct rcar_s3c *s3c;
+       struct rcar_s3c_qos *s3c_qos;
+       struct rcar_dbsc3_qos *qos_addr;
+       struct rcar_mxi *mxi;
+       struct rcar_mxi_qos *mxi_qos;
+       struct rcar_axi_qos *axi_qos;
+
+       /* DBSC DBADJ2 */
+       writel(0x20042004, DBSC3_0_DBADJ2);
+
+       /* S3C -QoS */
+       s3c = (struct rcar_s3c *)S3C_BASE;
+       writel(0x80000000, &s3c->s3cadsplcr);
+       writel(0x1F060504, &s3c->s3crorr);
+       writel(0x1F060503, &s3c->s3cworr);
+
+       /* QoS Control Registers */
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+       writel(0x00890089, &s3c_qos->s3cqos0);
+       writel(0x20960010, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA2200, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960010, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA2200, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+       writel(0x00890089, &s3c_qos->s3cqos0);
+       writel(0x20960010, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA2200, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960010, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA2200, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+       writel(0x80928092, &s3c_qos->s3cqos0);
+       writel(0x20960020, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA20DC, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960020, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA20DC, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+       writel(0x00820082, &s3c_qos->s3cqos0);
+       writel(0x20960020, &s3c_qos->s3cqos1);
+       writel(0x20302030, &s3c_qos->s3cqos2);
+       writel(0x20AA20FA, &s3c_qos->s3cqos3);
+       writel(0x00002032, &s3c_qos->s3cqos4);
+       writel(0x20960020, &s3c_qos->s3cqos5);
+       writel(0x20302030, &s3c_qos->s3cqos6);
+       writel(0x20AA20FA, &s3c_qos->s3cqos7);
+       writel(0x00002032, &s3c_qos->s3cqos8);
+
+       writel(0x00200808, &s3c->s3carcr11);
+
+       /* DBSC -QoS */
+       /* DBSC0 - Read */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+               writel(0x00000002, &qos_addr->dblgcnt);
+               writel(0x00002096, &qos_addr->dbtmval0);
+               writel(0x00002064, &qos_addr->dbtmval1);
+               writel(0x00002032, &qos_addr->dbtmval2);
+               writel(0x00001FB0, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002078, &qos_addr->dbthres0);
+               writel(0x0000204B, &qos_addr->dbthres1);
+               writel(0x0000201E, &qos_addr->dbthres2);
+               writel(0x00000001, &qos_addr->dblgqon);
+       }
+
+       /* DBSC0 - Write */
+       for (i = DBSC3_00; i < DBSC3_NR; i++) {
+               qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+               writel(0x00000002, &qos_addr->dblgcnt);
+               writel(0x00002096, &qos_addr->dbtmval0);
+               writel(0x00002064, &qos_addr->dbtmval1);
+               writel(0x00002050, &qos_addr->dbtmval2);
+               writel(0x0000203A, &qos_addr->dbtmval3);
+               writel(0x00000001, &qos_addr->dbrqctr);
+               writel(0x00002078, &qos_addr->dbthres0);
+               writel(0x0000204B, &qos_addr->dbthres1);
+               writel(0x0000203C, &qos_addr->dbthres2);
+               writel(0x00000001, &qos_addr->dblgqon);
+       }
+
+       /* MXI -QoS */
+       /* Transaction Control (MXI) */
+       mxi = (struct rcar_mxi *)MXI_BASE;
+       writel(0x00000013, &mxi->mxrtcr);
+       writel(0x00000013, &mxi->mxwtcr);
+       writel(0x00B800C0, &mxi->mxsaar0);
+       writel(0x02000800, &mxi->mxsaar1);
+
+       /* QoS Control (MXI) */
+       mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+       writel(0x0000000C, &mxi_qos->vspdu0);
+       writel(0x0000000C, &mxi_qos->vspdu1);
+       writel(0x0000000E, &mxi_qos->du0);
+       writel(0x0000000E, &mxi_qos->du1);
+
+       /* AXI -QoS */
+       /* Transaction Control (MXI) */
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002021, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002037, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002021, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MTSB1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002021, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_PCI_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB21_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB30_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002029, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SAT1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000214C, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x000020A6, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (RT-AXI) */
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_RDM_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002299, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_RDS_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002029, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_STPRO_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002029, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (MP-AXI) */
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002037, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002014, &axi_qos->qosctset0);
+       writel(0x00000040, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002014, &axi_qos->qosctset0);
+       writel(0x00000040, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00001FF0, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00002001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x00002053, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
+       writel(0x00000000, &axi_qos->qosconf);
+       writel(0x0000206E, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (SYS-AXI256) */
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020EB, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (CCI-AXI) */
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x00002245, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002004, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000000, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       /* QoS Register (Media-AXI) */
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020dc, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x000020AA, &axi_qos->qosthres0);
+       writel(0x00002032, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+       writel(0x00000002, &axi_qos->qosconf);
+       writel(0x000020dc, &axi_qos->qosctset0);
+       writel(0x00002096, &axi_qos->qosctset1);
+       writel(0x00002030, &axi_qos->qosctset2);
+       writel(0x00002030, &axi_qos->qosctset3);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x000020AA, &axi_qos->qosthres0);
+       writel(0x00002032, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002190, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00001FF0, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00002001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x000020C8, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1R_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU1W_BASE;
+       writel(0x00000003, &axi_qos->qosconf);
+       writel(0x00002063, &axi_qos->qosctset0);
+       writel(0x00000001, &axi_qos->qosreqctr);
+       writel(0x00000001, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002004, &axi_qos->qosthres0);
+       writel(0x00000001, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+
+       axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+       writel(0x00000001, &axi_qos->qosconf);
+       writel(0x00002073, &axi_qos->qosctset0);
+       writel(0x00000020, &axi_qos->qosreqctr);
+       writel(0x00002064, &axi_qos->qosthres0);
+       writel(0x00002004, &axi_qos->qosthres1);
+       writel(0x00000001, &axi_qos->qosthres2);
+       writel(0x00000001, &axi_qos->qosqon);
+}
+
+void qos_init(void)
+{
+       if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X)
+               qos_init_es2();
+       else
+               qos_init_es1();
+}
index 6699381..4eba4be 100644 (file)
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q"
 CONFIG_ARM=y
 CONFIG_TARGET_CGTQMX6EVAL=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
new file mode 100644 (file)
index 0000000..de0193f
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QARM2=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
new file mode 100644 (file)
index 0000000..cc432cf
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QARM2=y
index bdcc672..3fe3559 100644 (file)
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6QARM2=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
new file mode 100644 (file)
index 0000000..491e22a
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
+CONFIG_ARM=y
+CONFIG_TARGET_MX6QARM2=y
index dc8e254..67c1b77 100644 (file)
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SABRESD=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
new file mode 100644 (file)
index 0000000..c516038
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_ARM=y
+CONFIG_TARGET_OT1200=y
index 10e6432..7de374a 100644 (file)
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
 CONFIG_ARM=y
 CONFIG_TARGET_VF610TWR=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
new file mode 100644 (file)
index 0000000..e78db26
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_ARM=y
+CONFIG_TARGET_VF610TWR=y
index 47eb34f..1f02bfc 100644 (file)
@@ -53,6 +53,7 @@ obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
 obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
+obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
 obj-$(CONFIG_NAND_MXC) += mxc_nand.o
 obj-$(CONFIG_NAND_MXS) += mxs_nand.o
 obj-$(CONFIG_NAND_NDFC) += ndfc.o
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
new file mode 100644 (file)
index 0000000..7feb3a7
--- /dev/null
@@ -0,0 +1,724 @@
+/*
+ * Copyright 2009-2014 Freescale Semiconductor, Inc. and others
+ *
+ * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
+ * Ported to U-Boot by Stefan Agner
+ * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
+ * Jason ported to M54418TWR and MVFA5.
+ * Authors: Stefan Agner <stefan.agner@toradex.com>
+ *          Bill Pringlemeir <bpringlemeir@nbsps.com>
+ *          Shaohui Xie <b21989@freescale.com>
+ *          Jason Jin <Jason.jin@freescale.com>
+ *
+ * Based on original driver mpc5121_nfc.c.
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Limitations:
+ * - Untested on MPC5125 and M54418.
+ * - DMA not used.
+ * - 2K pages or less.
+ * - Only 2K page w. 64+OOB and hardware ECC.
+ */
+
+#include <common.h>
+#include <malloc.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <nand.h>
+#include <errno.h>
+#include <asm/io.h>
+
+/* Register Offsets */
+#define NFC_FLASH_CMD1                 0x3F00
+#define NFC_FLASH_CMD2                 0x3F04
+#define NFC_COL_ADDR                   0x3F08
+#define NFC_ROW_ADDR                   0x3F0c
+#define NFC_ROW_ADDR_INC               0x3F14
+#define NFC_FLASH_STATUS1              0x3F18
+#define NFC_FLASH_STATUS2              0x3F1c
+#define NFC_CACHE_SWAP                 0x3F28
+#define NFC_SECTOR_SIZE                        0x3F2c
+#define NFC_FLASH_CONFIG               0x3F30
+#define NFC_IRQ_STATUS                 0x3F38
+
+/* Addresses for NFC MAIN RAM BUFFER areas */
+#define NFC_MAIN_AREA(n)               ((n) *  0x1000)
+
+#define PAGE_2K                                0x0800
+#define OOB_64                         0x0040
+
+/*
+ * NFC_CMD2[CODE] values. See section:
+ *  - 31.4.7 Flash Command Code Description, Vybrid manual
+ *  - 23.8.6 Flash Command Sequencer, MPC5125 manual
+ *
+ * Briefly these are bitmasks of controller cycles.
+ */
+#define READ_PAGE_CMD_CODE             0x7EE0
+#define PROGRAM_PAGE_CMD_CODE          0x7FC0
+#define ERASE_CMD_CODE                 0x4EC0
+#define READ_ID_CMD_CODE               0x4804
+#define RESET_CMD_CODE                 0x4040
+#define STATUS_READ_CMD_CODE           0x4068
+
+/* NFC ECC mode define */
+#define ECC_BYPASS                     0
+#define ECC_45_BYTE                    6
+
+/*** Register Mask and bit definitions */
+
+/* NFC_FLASH_CMD1 Field */
+#define CMD_BYTE2_MASK                         0xFF000000
+#define CMD_BYTE2_SHIFT                                24
+
+/* NFC_FLASH_CM2 Field */
+#define CMD_BYTE1_MASK                         0xFF000000
+#define CMD_BYTE1_SHIFT                                24
+#define CMD_CODE_MASK                          0x00FFFF00
+#define CMD_CODE_SHIFT                         8
+#define BUFNO_MASK                             0x00000006
+#define BUFNO_SHIFT                            1
+#define START_BIT                              (1<<0)
+
+/* NFC_COL_ADDR Field */
+#define COL_ADDR_MASK                          0x0000FFFF
+#define COL_ADDR_SHIFT                         0
+
+/* NFC_ROW_ADDR Field */
+#define ROW_ADDR_MASK                          0x00FFFFFF
+#define ROW_ADDR_SHIFT                         0
+#define ROW_ADDR_CHIP_SEL_RB_MASK              0xF0000000
+#define ROW_ADDR_CHIP_SEL_RB_SHIFT             28
+#define ROW_ADDR_CHIP_SEL_MASK                 0x0F000000
+#define ROW_ADDR_CHIP_SEL_SHIFT                        24
+
+/* NFC_FLASH_STATUS2 Field */
+#define STATUS_BYTE1_MASK                      0x000000FF
+
+/* NFC_FLASH_CONFIG Field */
+#define CONFIG_ECC_SRAM_ADDR_MASK              0x7FC00000
+#define CONFIG_ECC_SRAM_ADDR_SHIFT             22
+#define CONFIG_ECC_SRAM_REQ_BIT                        (1<<21)
+#define CONFIG_DMA_REQ_BIT                     (1<<20)
+#define CONFIG_ECC_MODE_MASK                   0x000E0000
+#define CONFIG_ECC_MODE_SHIFT                  17
+#define CONFIG_FAST_FLASH_BIT                  (1<<16)
+#define CONFIG_16BIT                           (1<<7)
+#define CONFIG_BOOT_MODE_BIT                   (1<<6)
+#define CONFIG_ADDR_AUTO_INCR_BIT              (1<<5)
+#define CONFIG_BUFNO_AUTO_INCR_BIT             (1<<4)
+#define CONFIG_PAGE_CNT_MASK                   0xF
+#define CONFIG_PAGE_CNT_SHIFT                  0
+
+/* NFC_IRQ_STATUS Field */
+#define IDLE_IRQ_BIT                           (1<<29)
+#define IDLE_EN_BIT                            (1<<20)
+#define CMD_DONE_CLEAR_BIT                     (1<<18)
+#define IDLE_CLEAR_BIT                         (1<<17)
+
+#define NFC_TIMEOUT    (1000)
+
+/* ECC status placed at end of buffers. */
+#define ECC_SRAM_ADDR  ((PAGE_2K+256-8) >> 3)
+#define ECC_STATUS_MASK        0x80
+#define ECC_ERR_COUNT  0x3F
+
+/*
+ * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
+ * and +7 for big-endian SOC.
+ */
+#ifdef CONFIG_VF610
+#define ECC_OFFSET     4
+#else
+#define ECC_OFFSET     7
+#endif
+
+struct vf610_nfc {
+       struct mtd_info   *mtd;
+       struct nand_chip   chip;
+       void __iomem      *regs;
+       uint               column;
+       int                spareonly;
+       int                page;
+       /* Status and ID are in alternate locations. */
+       int                alt_buf;
+#define ALT_BUF_ID   1
+#define ALT_BUF_STAT 2
+       struct clk        *clk;
+};
+
+#define mtd_to_nfc(_mtd) \
+       (struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
+
+static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
+static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
+
+static struct nand_bbt_descr bbt_main_descr = {
+       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+                  NAND_BBT_2BIT | NAND_BBT_VERSION,
+       .offs = 11,
+       .len = 4,
+       .veroffs = 15,
+       .maxblocks = 4,
+       .pattern = bbt_pattern,
+};
+
+static struct nand_bbt_descr bbt_mirror_descr = {
+       .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
+                  NAND_BBT_2BIT | NAND_BBT_VERSION,
+       .offs = 11,
+       .len = 4,
+       .veroffs = 15,
+       .maxblocks = 4,
+       .pattern = mirror_pattern,
+};
+
+static struct nand_ecclayout vf610_nfc_ecc45 = {
+       .eccbytes = 45,
+       .eccpos = {19, 20, 21, 22, 23,
+                  24, 25, 26, 27, 28, 29, 30, 31,
+                  32, 33, 34, 35, 36, 37, 38, 39,
+                  40, 41, 42, 43, 44, 45, 46, 47,
+                  48, 49, 50, 51, 52, 53, 54, 55,
+                  56, 57, 58, 59, 60, 61, 62, 63},
+       .oobfree = {
+               {.offset = 8,
+                .length = 11} }
+};
+
+static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+
+       return readl(nfc->regs + reg);
+}
+
+static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+
+       writel(val, nfc->regs + reg);
+}
+
+static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
+{
+       vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
+}
+
+static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
+{
+       vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
+}
+
+static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
+                                      u32 mask, u32 shift, u32 val)
+{
+       vf610_nfc_write(mtd, reg,
+                       (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
+}
+
+static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
+{
+       /*
+        * Use this accessor for the interal SRAM buffers. On ARM we can
+        * treat the SRAM buffer as if its memory, hence use memcpy
+        */
+       memcpy(dst, src, n);
+}
+
+/* Clear flags for upcoming command */
+static inline void vf610_nfc_clear_status(void __iomem *regbase)
+{
+       void __iomem *reg = regbase + NFC_IRQ_STATUS;
+       u32 tmp = __raw_readl(reg);
+       tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
+       __raw_writel(tmp, reg);
+}
+
+/* Wait for complete operation */
+static inline void vf610_nfc_done(struct mtd_info *mtd)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+       uint start;
+
+       /*
+        * Barrier is needed after this write. This write need
+        * to be done before reading the next register the first
+        * time.
+        * vf610_nfc_set implicates such a barrier by using writel
+        * to write to the register.
+        */
+       vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
+
+       start = get_timer(0);
+
+       while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
+               if (get_timer(start) > NFC_TIMEOUT) {
+                       printf("Timeout while waiting for !BUSY.\n");
+                       return;
+               }
+       }
+       vf610_nfc_clear_status(nfc->regs);
+}
+
+static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
+{
+       u32 flash_id;
+
+       if (col < 4) {
+               flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
+               return (flash_id >> (3-col)*8) & 0xff;
+       } else {
+               flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
+               return flash_id >> 24;
+       }
+}
+
+static u8 vf610_nfc_get_status(struct mtd_info *mtd)
+{
+       return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
+}
+
+/* Single command */
+static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
+                                  u32 cmd_code)
+{
+       void __iomem *reg = regbase + NFC_FLASH_CMD2;
+       u32 tmp;
+       vf610_nfc_clear_status(regbase);
+
+       tmp = __raw_readl(reg);
+       tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
+       tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
+       tmp |= cmd_code << CMD_CODE_SHIFT;
+       __raw_writel(tmp, reg);
+}
+
+/* Two commands */
+static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
+                             u32 cmd_byte2, u32 cmd_code)
+{
+       void __iomem *reg = regbase + NFC_FLASH_CMD1;
+       u32 tmp;
+       vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
+
+       tmp = __raw_readl(reg);
+       tmp &= ~CMD_BYTE2_MASK;
+       tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
+       __raw_writel(tmp, reg);
+}
+
+static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
+{
+       if (column != -1) {
+               struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+               if (nfc->chip.options | NAND_BUSWIDTH_16)
+                       column = column/2;
+               vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
+                                   COL_ADDR_SHIFT, column);
+       }
+       if (page != -1)
+               vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
+                                   ROW_ADDR_SHIFT, page);
+}
+
+/* Send command to NAND chip */
+static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
+                             int column, int page)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+
+       nfc->column     = max(column, 0);
+       nfc->spareonly  = 0;
+       nfc->alt_buf    = 0;
+
+       switch (command) {
+       case NAND_CMD_PAGEPROG:
+               nfc->page = -1;
+               vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
+                                       command, PROGRAM_PAGE_CMD_CODE);
+               vf610_nfc_addr_cycle(mtd, column, page);
+               break;
+
+       case NAND_CMD_RESET:
+               vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
+               break;
+       /*
+        * NFC does not support sub-page reads and writes,
+        * so emulate them using full page transfers.
+        */
+       case NAND_CMD_READOOB:
+               nfc->spareonly = 1;
+       case NAND_CMD_SEQIN: /* Pre-read for partial writes. */
+       case NAND_CMD_READ0:
+               column = 0;
+               /* Already read? */
+               if (nfc->page == page)
+                       return;
+               nfc->page = page;
+               vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
+                                       NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
+               vf610_nfc_addr_cycle(mtd, column, page);
+               break;
+
+       case NAND_CMD_ERASE1:
+               if (nfc->page == page)
+                       nfc->page = -1;
+               vf610_nfc_send_commands(nfc->regs, command,
+                                       NAND_CMD_ERASE2, ERASE_CMD_CODE);
+               vf610_nfc_addr_cycle(mtd, column, page);
+               break;
+
+       case NAND_CMD_READID:
+               nfc->alt_buf = ALT_BUF_ID;
+               vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
+               break;
+
+       case NAND_CMD_STATUS:
+               nfc->alt_buf = ALT_BUF_STAT;
+               vf610_nfc_send_command(nfc->regs, command,
+                                      STATUS_READ_CMD_CODE);
+               break;
+       default:
+               return;
+       }
+
+       vf610_nfc_done(mtd);
+}
+
+static inline void vf610_nfc_read_spare(struct mtd_info *mtd, void *buf,
+                                       int len)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+
+       len = min(mtd->oobsize, (uint)len);
+       if (len > 0)
+               vf610_nfc_memcpy(buf, nfc->regs + mtd->writesize, len);
+}
+
+/* Read data from NFC buffers */
+static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+       uint c = nfc->column;
+       uint l;
+
+       /* Handle main area */
+       if (!nfc->spareonly) {
+               l = min((uint)len, mtd->writesize - c);
+               nfc->column += l;
+
+               if (!nfc->alt_buf)
+                       vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c,
+                                        l);
+               else
+                       if (nfc->alt_buf & ALT_BUF_ID)
+                               *buf = vf610_nfc_get_id(mtd, c);
+                       else
+                               *buf = vf610_nfc_get_status(mtd);
+
+               buf += l;
+               len -= l;
+       }
+
+       /* Handle spare area access */
+       if (len) {
+               nfc->column += len;
+               vf610_nfc_read_spare(mtd, buf, len);
+       }
+}
+
+/* Write data to NFC buffers */
+static void vf610_nfc_write_buf(struct mtd_info *mtd, const u_char *buf,
+                               int len)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+       uint c = nfc->column;
+       uint l;
+
+       l = min((uint)len, mtd->writesize + mtd->oobsize - c);
+       nfc->column += l;
+       vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
+}
+
+/* Read byte from NFC buffers */
+static u8 vf610_nfc_read_byte(struct mtd_info *mtd)
+{
+       u8 tmp;
+       vf610_nfc_read_buf(mtd, &tmp, sizeof(tmp));
+       return tmp;
+}
+
+/* Read word from NFC buffers */
+static u16 vf610_nfc_read_word(struct mtd_info *mtd)
+{
+       u16 tmp;
+       vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
+       return tmp;
+}
+
+/* If not provided, upper layers apply a fixed delay. */
+static int vf610_nfc_dev_ready(struct mtd_info *mtd)
+{
+       /* NFC handles R/B internally; always ready.  */
+       return 1;
+}
+
+/*
+ * This function supports Vybrid only (MPC5125 would have full RB and four CS)
+ */
+static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+#ifdef CONFIG_VF610
+       u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
+       tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
+       tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
+
+       if (chip == 0)
+               tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT;
+       else if (chip == 1)
+               tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT;
+
+       vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
+#endif
+}
+
+/* Count the number of 0's in buff upto max_bits */
+static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
+{
+       uint32_t *buff32 = (uint32_t *)buff;
+       int k, written_bits = 0;
+
+       for (k = 0; k < (size / 4); k++) {
+               written_bits += hweight32(~buff32[k]);
+               if (written_bits > max_bits)
+                       break;
+       }
+
+       return written_bits;
+}
+
+static inline int vf610_nfc_correct_data(struct mtd_info *mtd, u_char *dat)
+{
+       struct vf610_nfc *nfc = mtd_to_nfc(mtd);
+       u8 ecc_status;
+       u8 ecc_count;
+       int flip;
+
+       ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET);
+       ecc_count = ecc_status & ECC_ERR_COUNT;
+       if (!(ecc_status & ECC_STATUS_MASK))
+               return ecc_count;
+
+       /* If 'ecc_count' zero or less then buffer is all 0xff or erased. */
+       flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count);
+
+       /* ECC failed. */
+       if (flip > ecc_count) {
+               nfc->page = -1;
+               return -1;
+       }
+
+       /* Erased page. */
+       memset(dat, 0xff, nfc->chip.ecc.size);
+       return 0;
+}
+
+
+static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
+                               uint8_t *buf, int oob_required, int page)
+{
+       int eccsize = chip->ecc.size;
+       int stat;
+       uint8_t *p = buf;
+
+
+       vf610_nfc_read_buf(mtd, p, eccsize);
+
+       if (oob_required)
+               vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+       stat = vf610_nfc_correct_data(mtd, p);
+
+       if (stat < 0)
+               mtd->ecc_stats.failed++;
+       else
+               mtd->ecc_stats.corrected += stat;
+
+       return 0;
+}
+
+/*
+ * ECC will be calculated automatically
+ */
+static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+                              const uint8_t *buf, int oob_required)
+{
+       vf610_nfc_write_buf(mtd, buf, mtd->writesize);
+       if (oob_required)
+               vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+       return 0;
+}
+
+struct vf610_nfc_config {
+       int hardware_ecc;
+       int width;
+       int flash_bbt;
+};
+
+static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
+{
+       struct mtd_info *mtd = &nand_info[devnum];
+       struct nand_chip *chip;
+       struct vf610_nfc *nfc;
+       int err = 0;
+       int page_sz;
+       struct vf610_nfc_config cfg = {
+               .hardware_ecc = 1,
+#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
+               .width = 16,
+#else
+               .width = 8,
+#endif
+               .flash_bbt = 1,
+       };
+
+       nfc = malloc(sizeof(*nfc));
+       if (!nfc) {
+               printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
+               return -ENOMEM;
+       }
+
+       chip = &nfc->chip;
+       nfc->regs = addr;
+
+       mtd->priv = chip;
+       chip->priv = nfc;
+
+       if (cfg.width == 16) {
+               chip->options |= NAND_BUSWIDTH_16;
+               vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
+       } else {
+               chip->options &= ~NAND_BUSWIDTH_16;
+               vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
+       }
+
+       chip->dev_ready = vf610_nfc_dev_ready;
+       chip->cmdfunc = vf610_nfc_command;
+       chip->read_byte = vf610_nfc_read_byte;
+       chip->read_word = vf610_nfc_read_word;
+       chip->read_buf = vf610_nfc_read_buf;
+       chip->write_buf = vf610_nfc_write_buf;
+       chip->select_chip = vf610_nfc_select_chip;
+
+       /* Bad block options. */
+       if (cfg.flash_bbt)
+               chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_CREATE;
+
+       /* Default to software ECC until flash ID. */
+       vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
+                           CONFIG_ECC_MODE_MASK,
+                           CONFIG_ECC_MODE_SHIFT, ECC_BYPASS);
+
+       chip->bbt_td = &bbt_main_descr;
+       chip->bbt_md = &bbt_mirror_descr;
+
+       page_sz = PAGE_2K + OOB_64;
+       page_sz += cfg.width == 16 ? 1 : 0;
+       vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+
+       /* Set configuration register. */
+       vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
+       vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
+       vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
+       vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
+       vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
+
+       /* Enable Idle IRQ */
+       vf610_nfc_set(mtd, NFC_IRQ_STATUS, IDLE_EN_BIT);
+
+       /* PAGE_CNT = 1 */
+       vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
+                           CONFIG_PAGE_CNT_SHIFT, 1);
+
+       /* Set ECC_STATUS offset */
+       vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
+                           CONFIG_ECC_SRAM_ADDR_MASK,
+                           CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR);
+
+       /* first scan to find the device and get the page size */
+       if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
+               err = -ENXIO;
+               goto error;
+       }
+
+       chip->ecc.mode = NAND_ECC_SOFT; /* default */
+
+       page_sz = mtd->writesize + mtd->oobsize;
+
+       /* Single buffer only, max 256 OOB minus ECC status */
+       if (page_sz > PAGE_2K + 256 - 8) {
+               dev_err(nfc->dev, "Unsupported flash size\n");
+               err = -ENXIO;
+               goto error;
+       }
+       page_sz += cfg.width == 16 ? 1 : 0;
+       vf610_nfc_write(mtd, NFC_SECTOR_SIZE, page_sz);
+
+       if (cfg.hardware_ecc) {
+               if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
+                       dev_err(nfc->dev, "Unsupported flash with hwecc\n");
+                       err = -ENXIO;
+                       goto error;
+               }
+
+               chip->ecc.layout = &vf610_nfc_ecc45;
+
+               /* propagate ecc.layout to mtd_info */
+               mtd->ecclayout = chip->ecc.layout;
+               chip->ecc.read_page = vf610_nfc_read_page;
+               chip->ecc.write_page = vf610_nfc_write_page;
+               chip->ecc.mode = NAND_ECC_HW;
+
+               chip->ecc.bytes = 45;
+               chip->ecc.size = PAGE_2K;
+               chip->ecc.strength = 24;
+
+               /* set ECC mode to 45 bytes OOB with 24 bits correction */
+               vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
+                                   CONFIG_ECC_MODE_MASK,
+                                   CONFIG_ECC_MODE_SHIFT, ECC_45_BYTE);
+
+               /* Enable ECC_STATUS */
+               vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
+       }
+
+       /* second phase scan */
+       err = nand_scan_tail(mtd);
+       if (err)
+               return err;
+
+       err = nand_register(devnum);
+       if (err)
+               return err;
+
+       return 0;
+
+error:
+       return err;
+}
+
+void board_nand_init(void)
+{
+       int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
+       if (err)
+               printf("VF610 NAND init failed (err %d)\n", err);
+}
index c0a557b..9ec5a0a 100644 (file)
@@ -174,7 +174,7 @@ struct usbnc_regs {
 
 static void usb_oc_config(int index)
 {
-       struct usbnc_regs *usbnc = (struct usbnc_regs *)(USBOH3_USB_BASE_ADDR +
+       struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
                        USB_OTHERREGS_OFFSET);
        void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
        u32 val;
@@ -207,7 +207,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        enum usb_init_type type;
-       struct usb_ehci *ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
+       struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
                (0x200 * index));
 
        if (index > 3)
index 4d652b3..6b8d969 100644 (file)
@@ -77,6 +77,16 @@ static int ehci_mxs_toggle_clock(const struct ehci_mxs_port *port, int enable)
        return 0;
 }
 
+int __weak board_ehci_hcd_init(int port)
+{
+       return 0;
+}
+
+int __weak board_ehci_hcd_exit(int port)
+{
+       return 0;
+}
+
 int ehci_hcd_init(int index, enum usb_init_type init,
                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
@@ -90,6 +100,10 @@ int ehci_hcd_init(int index, enum usb_init_type init,
                return -EINVAL;
        }
 
+       ret = board_ehci_hcd_init(index);
+       if (ret)
+               return ret;
+
        port = &mxs_port[index];
 
        /* Reset the PHY block */
@@ -154,5 +168,7 @@ int ehci_hcd_stop(int index)
        /* Disable USB clock */
        ret = ehci_mxs_toggle_clock(port, 0);
 
+       board_ehci_hcd_exit(index);
+
        return ret;
 }
index 10d02b4..7cf241e 100644 (file)
 #define CONFIG_MII
 #define CONFIG_ETHPRIME                        "FEC0"
 #define CONFIG_ARP_TIMEOUT             200UL
-#define CONFIG_NETMASK                 255.255.255.0
 #define CONFIG_NET_RETRY_COUNT         5
 
 /* USB */
index 21667d1..e015e90 100644 (file)
@@ -89,6 +89,7 @@
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE
 #define CONFIG_CONS_SCIF0
+#define CONFIG_SCIF_USE_EXT_CLK
 #undef CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
index 6e9d67d..699135f 100644 (file)
@@ -90,6 +90,7 @@
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE
 #define CONFIG_CONS_SCIF0
+#define CONFIG_SCIF_USE_EXT_CLK
 #undef CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 #define CONFIG_PLL1_DIV2_CLK_FREQ      (CONFIG_PLL1_CLK_FREQ / 2)
 #define CONFIG_MP_CLK_FREQ     (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
 #define CONFIG_HP_CLK_FREQ     (CONFIG_PLL1_CLK_FREQ / 12)
-#define CONFIG_SH_SCIF_CLK_FREQ        CONFIG_MP_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ        14745600 /* External Clock */
 
 #define CONFIG_SYS_TMU_CLK_DIV 4
 
index bf5c1a1..a14bfe3 100644 (file)
@@ -8,6 +8,8 @@
 #ifndef _CONFIG_LSXL_H
 #define _CONFIG_LSXL_H
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 /*
  * Version number information
  */
        "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \
                "setenv ncip; setenv gatewayip; setenv ethact; "        \
                "setenv bootfile; setenv dnsip; "                       \
-               "setenv bootsource hdd; run ser\0"                      \
+               "setenv bootsource legacy; run ser\0"                   \
        "restore_env=run standard_env; saveenv; reset\0"                \
        "ser=setenv stdin serial; setenv stdout serial; "               \
                "setenv stderr serial\0"                                \
index fccd29d..efe770b 100644 (file)
@@ -32,6 +32,7 @@
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GPIO
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_I2C
        "addargs=run addcons addmtd addmisc\0"                          \
        "mmcload="                                                      \
                "mmc rescan ; "                                         \
-               "ext4load mmc 0:2 ${kernel_addr_r} ${bootfile}\0"       \
+               "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0"           \
        "ubiload="                                                      \
                "ubi part UBI ; ubifsmount ubi0:rootfs ; "              \
                "ubifsload ${kernel_addr_r} /boot/${bootfile}\0"        \
                "bootm ${kernel_addr_r}\0"                              \
        "try_bootscript="                                               \
                "mmc rescan;"                                           \
-               "if ext4load mmc 0:2 ${kernel_addr_r} ${bootscript};"   \
-               "then;"                                                 \
-                       "\techo Running bootscript...;"                 \
-                       "\tsource ${kernel_addr_r};"                    \
+               "if test -e mmc 0:2 ${bootscript} ; then "              \
+               "if load mmc 0:2 ${kernel_addr_r} ${bootscript};"       \
+               "then ; "                                               \
+                       "echo Running bootscript... ; "                 \
+                       "source ${kernel_addr_r} ; "                    \
+               "fi ; "                                                 \
                "fi\0"
 
 /* The rest of the configuration is shared */
index df6a226..c133ba9 100644 (file)
@@ -38,6 +38,7 @@
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
        "addargs=run addcons addmtd addmisc\0"                          \
        "mmcload="                                                      \
                "mmc rescan ; "                                         \
-               "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0"       \
+               "load mmc 0:1 ${kernel_addr_r} ${bootfile}\0"           \
        "ubiload="                                                      \
                "ubi part UBI ; ubifsmount ubi0:rootfs ; "              \
                "ubifsload ${kernel_addr_r} /boot/${bootfile}\0"        \
                "bootm ${kernel_addr_r}\0"                              \
        "try_bootscript="                                               \
                "mmc rescan;"                                           \
-               "if ext4load mmc 0:1 ${kernel_addr_r} ${bootscript};"   \
-               "then;"                                                 \
-                       "\techo Running bootscript...;"                 \
-                       "\tsource ${kernel_addr_r};"                    \
+               "if test -e mmc 0:1 ${bootscript} ; then "              \
+               "if load mmc 0:1 ${kernel_addr_r} ${bootscript};"       \
+               "then ; "                                               \
+                       "echo Running bootscript... ; "                 \
+                       "source ${kernel_addr_r} ; "                    \
+               "fi ; "                                                 \
                "fi\0"
 
 #endif /* __M53EVK_CONFIG_H__ */
index d464ad9..c02e29b 100644 (file)
@@ -14,6 +14,7 @@
 #define CONFIG_MX25
 #define CONFIG_SYS_TEXT_BASE           0x81200000
 #define CONFIG_MXC_GPIO
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_SYS_TIMER_RATE          32768
 #define CONFIG_SYS_TIMER_COUNTER       \
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_ADDR      IMX_MMC_SDHC1_BASE
 #define CONFIG_SYS_FSL_ESDHC_NUM       1
 
 /* PMIC Configs */
index b389475..d6e8ec4 100644 (file)
@@ -26,6 +26,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_OF_LIBFDT
 
@@ -69,7 +70,7 @@
  * MMC Configs
  * */
 #define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_ADDR      MMC_SDHC1_BASE_ADDR
 #define CONFIG_SYS_FSL_ESDHC_NUM       2
 
 #define CONFIG_MMC
index 35c0a85..6e01fa0 100644 (file)
@@ -10,7 +10,6 @@
 #define __CONFIG_H
 
 #define CONFIG_MX6
-#define CONFIG_MX6Q
 
 #include "mx6_common.h"
 
@@ -37,7 +36,7 @@
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC4_BASE_ADDR
 #define CONFIG_SYS_FSL_USDHC_NUM       2
 
 #define CONFIG_MMC
 
 #define CONFIG_BOOTDELAY               3
 
-#define CONFIG_LOADADDR                        0x10800000
+#define CONFIG_LOADADDR                        0x12000000
 #define CONFIG_SYS_TEXT_BASE           0x17800000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "script=boot.scr\0" \
        "image=zImage\0" \
        "console=ttymxc3\0" \
+       "fdt_file=imx6q-arm2.dtb\0" \
+       "fdt_addr=0x18000000\0" \
        "fdt_high=0xffffffff\0" \
        "initrd_high=0xffffffff\0" \
+       "boot_fdt=try\0" \
+       "ip_dyn=yes\0" \
        "mmcdev=1\0" \
-       "mmcpart=2\0" \
-       "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+       "mmcpart=1\0" \
+       "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
        "mmcargs=setenv bootargs console=${console},${baudrate} " \
                "root=${mmcroot}\0" \
        "loadbootscript=" \
        "bootscript=echo Running bootscript from mmc ...; " \
                "source\0" \
        "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+       "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
        "mmcboot=echo Booting from mmc ...; " \
                "run mmcargs; " \
-               "bootz\0" \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if run loadfdt; then " \
+                               "bootz ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootz; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootz; " \
+               "fi;\0" \
        "netargs=setenv bootargs console=${console},${baudrate} " \
                "root=/dev/nfs " \
                "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
        "netboot=echo Booting from net ...; " \
                "run netargs; " \
-               "dhcp ${image}; bootz\0" \
+               "if test ${ip_dyn} = yes; then " \
+                       "setenv get_cmd dhcp; " \
+               "else " \
+                       "setenv get_cmd tftp; " \
+               "fi; " \
+               "${get_cmd} ${image}; " \
+               "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+                       "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+                               "bootz ${loadaddr} - ${fdt_addr}; " \
+                       "else " \
+                               "if test ${boot_fdt} = try; then " \
+                                       "bootz; " \
+                               "else " \
+                                       "echo WARN: Cannot load the DT; " \
+                               "fi; " \
+                       "fi; " \
+               "else " \
+                       "bootz; " \
+               "fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
        "mmc dev ${mmcdev};" \
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS           1
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
-#define PHYS_SDRAM_SIZE                        (2u * 1024 * 1024 * 1024)
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
index 4208ba1..fddedf1 100644 (file)
@@ -40,7 +40,7 @@
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC2_BASE_ADDR
 
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
index b92d944..e02ea18 100644 (file)
 /* MMC Configuration */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_ESDHC_ADDR      USDHC4_BASE_ADDR
 
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO     IMX_GPIO_NR(2, 1)
-#define CONFIG_PCIE_IMX_POWER_GPIO     IMX_GPIO_NR(2, 0)
+#define CONFIG_PCIE_IMX_PERST_GPIO     IMX_GPIO_NR(2, 0)
+#define CONFIG_PCIE_IMX_POWER_GPIO     IMX_GPIO_NR(2, 1)
 #endif
 
 /* FLASH and environment organization */
index 39d5bb3..6d379ed 100644 (file)
@@ -32,6 +32,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
 #define CONFIG_MXC_GPIO
+#define CONFIG_CMD_GPIO
 #define CONFIG_CI_UDC
 #define CONFIG_USBD_HS
 #define CONFIG_USB_GADGET_DUALSPEED
@@ -63,6 +64,7 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_I2C_EDID
 
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
@@ -75,6 +77,8 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET       /* For OTG port */
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
 
 /* Miscellaneous commands */
 #define CONFIG_CMD_BMODE
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_CMD_HDMIDETECT
 #define CONFIG_CONSOLE_MUX
 #define CONFIG_DRIVE_MMC
 #endif
 
-#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
+#ifdef CONFIG_USB_STORAGE
+#define CONFIG_DRIVE_USB "usb "
+#else
+#define CONFIG_DRIVE_USB
+#endif
+
+#define CONFIG_DRIVE_TYPES CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC CONFIG_DRIVE_USB
+#define CONFIG_UMSDEVS CONFIG_DRIVE_SATA CONFIG_DRIVE_MMC
 
 #if defined(CONFIG_SABRELITE)
 #define CONFIG_EXTRA_ENV_SETTINGS \
        "fdt_addr=0x18000000\0" \
        "boot_fdt=try\0" \
        "ip_dyn=yes\0" \
-       "mmcdev=0\0" \
+       "mmcdevs=0 1\0" \
        "mmcpart=1\0" \
        "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
        "mmcargs=setenv bootargs console=${console},${baudrate} " \
                "fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
-          "mmc dev ${mmcdev}; if mmc rescan; then " \
-                  "if run loadbootscript; then " \
-                          "run bootscript; " \
-                  "else " \
-                          "if run loaduimage; then " \
-                                  "run mmcboot; " \
-                          "else run netboot; " \
-                          "fi; " \
-                  "fi; " \
-          "else run netboot; fi"
+       "for mmcdev in ${mmcdevs}; do " \
+               "mmc dev ${mmcdev}; " \
+               "if mmc rescan; then " \
+                       "if run loadbootscript; then " \
+                               "run bootscript; " \
+                       "else " \
+                               "if run loaduimage; then " \
+                                       "run mmcboot; " \
+                               "fi; " \
+                       "fi; " \
+               "fi; " \
+       "done; " \
+       "run netboot; "
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS \
+       "bootdevs=" CONFIG_DRIVE_TYPES "\0" \
+       "umsdevs=" CONFIG_UMSDEVS "\0" \
        "console=ttymxc1\0" \
        "clearenv=if sf probe || sf probe || sf probe 1 ; then " \
                "sf erase 0xc0000 0x2000 && " \
                "echo restored environment to factory default ; fi\0" \
-       "bootcmd=for dtype in " CONFIG_DRIVE_TYPES \
+       "bootcmd=for dtype in ${bootdevs}" \
                "; do " \
+                       "if itest.s \"xusb\" == \"x${dtype}\" ; then " \
+                               "usb start ;" \
+                       "fi; " \
                        "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
-                               "for fs in fat ext2 ; do " \
-                                       "${fs}load " \
-                                               "${dtype} ${disk}:1 " \
-                                               "10008000 " \
-                                               "/6x_bootscript" \
-                                               "&& source 10008000 ; " \
-                               "done ; " \
+                               "load " \
+                                       "${dtype} ${disk}:1 " \
+                                       "10008000 " \
+                                       "/6x_bootscript" \
+                                       "&& source 10008000 ; " \
                        "done ; " \
                "done; " \
                "setenv stdout serial,vga ; " \
                "echo ; echo 6x_bootscript not found ; " \
                "echo ; echo serial console at 115200, 8N1 ; echo ; " \
                "echo details at http://boundarydevices.com/6q_bootscript ; " \
-               "setenv stdout serial\0" \
-       "upgradeu=for dtype in " CONFIG_DRIVE_TYPES \
+               "setenv stdout serial;" \
+               "setenv stdin serial,usbkbd;" \
+               "for dtype in ${umsdevs} ; do " \
+                       "if itest.s sata == ${dtype}; then " \
+                               "initcmd='sata init' ;" \
+                       "else " \
+                               "initcmd='mmc rescan' ;" \
+                       "fi; " \
+                       "for disk in 0 1 ; do " \
+                               "if $initcmd && $dtype dev $disk ; then " \
+                                       "setenv stdout serial,vga; " \
+                                       "echo expose ${dtype} ${disk} " \
+                                               "over USB; " \
+                                       "ums 0 $dtype $disk ;" \
+                               "fi; " \
+               "       done; " \
+               "done ;" \
+               "setenv stdout serial,vga; " \
+               "echo no block devices found;" \
+               "\0" \
+       "initrd_high=0xffffffff\0" \
+       "upgradeu=for dtype in ${bootdevs}" \
                "; do " \
                "for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
-                    "for fs in fat ext2 ; do " \
-                               "${fs}load ${dtype} ${disk}:1 10008000 " \
-                                       "/6x_upgrade " \
-                                       "&& source 10008000 ; " \
-                       "done ; " \
+                       "load ${dtype} ${disk}:1 10008000 " \
+                               "/6x_upgrade " \
+                               "&& source 10008000 ; " \
                "done ; " \
        "done\0" \
 
 
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS            16
+#define CONFIG_SYS_MAXARGS            48
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 
 #define CONFIG_SYS_MEMTEST_START       0x10000000
 #define CONFIG_CMD_BMP
 
 #define CONFIG_CMD_TIME
+#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_ALT_MEMTEST
 
 #define CONFIG_CMD_BOOTZ
 #define CONFIG_PCIE_IMX
 #endif
 
+#define CONFIG_CMD_ELF
+
+#define CONFIG_USB_GADGET
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_VBUS_DRAW    2
+
+/* Netchip IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Boundary"
+
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE   0x07000000
+
 #endif        /* __CONFIG_H */
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
new file mode 100644 (file)
index 0000000..071880f
--- /dev/null
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014 Bachmann electronic GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN           (10 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_MXC_GPIO
+
+/* FUSE Configs */
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* UART Configs */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE           UART1_BASE
+
+/* SF Configs */
+#define CONFIG_CMD_SF
+#define CONFIG_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS  2
+#define CONFIG_SF_DEFAULT_CS   (0|(IMX_GPIO_NR(1, 3)<<8))
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+
+/* IO expander */
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_ADDR    0x20
+#define CONFIG_SYS_I2C_PCA953X_WIDTH   { {0x20, 16} }
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED            100000
+
+/* OCOTP Configs */
+#define CONFIG_CMD_IMXOTP
+#define CONFIG_IMX_OTP
+#define IMX_OTP_BASE                    OCOTP_BASE_ADDR
+#define IMX_OTP_ADDR_MAX                0x7F
+#define IMX_OTP_DATA_ERROR_VAL          0xBADABADA
+#define IMX_OTPWRITE_ENABLED
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      0
+#define CONFIG_SYS_FSL_USDHC_NUM       2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+#ifdef CONFIG_MX6Q
+#define CONFIG_CMD_SATA
+#endif
+
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE     1
+#define CONFIG_DWC_AHSATA_PORT_ID      0
+#define CONFIG_DWC_AHSATA_BASE_ADDR    SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE                    ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE             MII100
+#define CONFIG_ETHPRIME                 "FEC"
+#define CONFIG_FEC_MXC_PHYADDR          0x5
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+/* Miscellaneous commands */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY               2
+
+#define CONFIG_PREBOOT                 ""
+
+#define CONFIG_LOADADDR                0x12000000
+#define CONFIG_SYS_TEXT_BASE           0x17800000
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_CBSIZE              1024
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS           1
+#define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE                 (64 * 1024)    /* 64 kb */
+#define CONFIG_ENV_OFFSET               (1024 * 1024)
+/* M25P16 has an erase size of 64 KiB */
+#define CONFIG_ENV_SECT_SIZE            (64 * 1024)
+#define CONFIG_ENV_SPI_BUS              CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS               CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE             CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ           CONFIG_SF_DEFAULT_SPEED
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* FS Configs */
+#define CONFIG_CMD_EXT3
+#define CONFIG_CMD_EXT4
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FS_GENERIC
+
+#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_BOOTFILE
+
+#endif         /* __CONFIG_H */
index 4747adf..71be823 100644 (file)
@@ -1,5 +1,6 @@
 /*
- * (C) Copyright 2009
+ * (C) Copyright 2009-2014
+ * Gerald Kerma <dreagle@doukki.net>
  * Marvell Semiconductor <www.marvell.com>
  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  *
 #define CONFIG_MACH_SHEEVAPLUG /* Machine type */
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
 
+/*
+ * Compression configuration
+ */
+#define CONFIG_BZIP2
+#define CONFIG_LZMA
+#define CONFIG_LZO
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_HUSH_PARSER         /* use "hush" command parser */
+
 /*
  * Commands configuration
  */
 #define CONFIG_SYS_NO_FLASH            /* Declare no flash (NOR/SPI) */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_BOOTZ
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_NAND
@@ -54,8 +69,8 @@
  * it has to be rounded to sector size
  */
 #define CONFIG_ENV_SIZE                        0x20000 /* 128k */
-#define CONFIG_ENV_ADDR                        0x60000
-#define CONFIG_ENV_OFFSET              0x60000 /* env starts here */
+#define CONFIG_ENV_ADDR                        0x80000
+#define CONFIG_ENV_OFFSET              0x80000 /* env starts here */
 
 /*
  * Default environment variables
        "setenv bootargs ${x_bootargs} ${x_bootargs_root}; "    \
        "${x_bootcmd_usb}; bootm 0x6400000;"
 
-#define CONFIG_MTDPARTS                "orion_nand:512k(uboot),"       \
-       "3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
+#define CONFIG_MTDPARTS                \
+       "mtdparts=orion_nand:512K(uboot),"                              \
+       "512K(env),1M(script),6M(kernel),"                              \
+       "12M(ramdisk),4M(spare),-(rootfs)"
 
 #define CONFIG_EXTRA_ENV_SETTINGS      "x_bootargs=console"    \
        "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS        \
        "x_bootcmd_usb=usb start\0" \
        "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
 
+#define MTDIDS_DEFAULT "nand0=orion_nand"
+
+#define MTDPARTS_DEFAULT       \
+       "mtdparts="CONFIG_MTDPARTS
+
 /*
  * Ethernet Driver configuration
  */
 #define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
 #endif /* CONFIG_CMD_MMC */
 
+/*
+ * SATA driver configuration
+ */
+#ifdef CONFIG_CMD_IDE
+#define __io
+#define CONFIG_IDE_PREINIT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MVSATA_IDE_USE_PORT0
+#define CONFIG_MVSATA_IDE_USE_PORT1
+#define CONFIG_SYS_ATA_IDE0_OFFSET     MV_SATA_PORT0_OFFSET
+#define CONFIG_SYS_ATA_IDE1_OFFSET     MV_SATA_PORT1_OFFSET
+#endif /* CONFIG_CMD_IDE */
+
 /*
  * File system
  */
 #define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_UBI
index 0342550..6fd0b17 100644 (file)
@@ -14,6 +14,7 @@
 
 #define CONFIG_VF610
 
+#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 
 #undef CONFIG_CMD_IMLS
 
+/* NAND support */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_VF610_NFC
+#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
+
+/* UBI */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+/* Dynamic MTD partition support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT                 "nand0=fsl_nfc"
+#define MTDPARTS_DEFAULT               "mtdparts=fsl_nfc:"             \
+                                       "128k(vf-bcb)ro,"               \
+                                       "1408k(u-boot)ro,"              \
+                                       "512k(u-boot-env),"             \
+                                       "4m(kernel),"                   \
+                                       "512k(fdt),"            \
+                                       "-(rootfs)"
+#endif
+
 #define CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
+#ifdef CONFIG_ENV_IS_IN_MMC
 #define CONFIG_ENV_SIZE                        (8 * 1024)
-#define CONFIG_ENV_IS_IN_MMC
 
 #define CONFIG_ENV_OFFSET              (12 * 64 * 1024)
 #define CONFIG_SYS_MMC_ENV_DEV         0
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                        (64 * 2048)
+#define CONFIG_ENV_SECT_SIZE           (64 * 2048)
+#define CONFIG_ENV_RANGE               (512 * 1024)
+#define CONFIG_ENV_OFFSET              0x180000
+#endif
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
index 7d96908..9fb501a 100644 (file)
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-wandboard.dtb"
 #elif defined(CONFIG_MX6Q)