Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
authorAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 2 Oct 2013 12:53:27 +0000 (14:53 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Wed, 2 Oct 2013 12:53:27 +0000 (14:53 +0200)
60 files changed:
README
arch/arm/config.mk
arch/arm/cpu/arm1136/config.mk
arch/arm/cpu/arm1176/config.mk
arch/arm/cpu/arm720t/config.mk
arch/arm/cpu/arm920t/config.mk
arch/arm/cpu/arm925t/config.mk
arch/arm/cpu/arm926ejs/config.mk
arch/arm/cpu/arm946es/config.mk
arch/arm/cpu/arm_intcm/config.mk
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/clock_am33xx.c
arch/arm/cpu/armv7/am33xx/sys_info.c
arch/arm/cpu/armv7/config.mk
arch/arm/cpu/armv7/lowlevel_init.S
arch/arm/cpu/armv7/omap-common/boot-common.c
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/cpu/armv7/rmobile/config.mk
arch/arm/cpu/armv7/zynq/timer.c
arch/arm/cpu/ixp/config.mk
arch/arm/cpu/pxa/config.mk
arch/arm/cpu/s3c44b0/Makefile [deleted file]
arch/arm/cpu/s3c44b0/cache.c [deleted file]
arch/arm/cpu/s3c44b0/config.mk [deleted file]
arch/arm/cpu/s3c44b0/cpu.c [deleted file]
arch/arm/cpu/s3c44b0/start.S [deleted file]
arch/arm/cpu/s3c44b0/timer.c [deleted file]
arch/arm/cpu/sa1100/config.mk
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/sys_proto.h
arch/arm/include/asm/arch-s3c44b0/hardware.h [deleted file]
arch/arm/include/asm/dma-mapping.h
arch/arm/include/asm/global_data.h
arch/arm/include/asm/omap_common.h
arch/arm/lib/crt0.S
arch/arm/lib/relocate.S
arch/arm/lib/spl.c
board/ti/am335x/board.c
doc/driver-model/UDM-rtc.txt
doc/driver-model/UDM-serial.txt
drivers/i2c/Makefile
drivers/i2c/s3c44b0_i2c.c [deleted file]
drivers/net/cpsw.c
drivers/power/pmic/Makefile
drivers/power/pmic/pmic_tps65217.c [new file with mode: 0644]
drivers/power/pmic/pmic_tps65910.c [new file with mode: 0644]
drivers/rtc/Makefile
drivers/rtc/s3c44b0_rtc.c [deleted file]
drivers/serial/Makefile
drivers/serial/serial.c
drivers/serial/serial_s3c44b0.c [deleted file]
include/configs/am335x_evm.h
include/configs/dra7xx_evm.h
include/configs/eb_cpux9k2.h
include/configs/pcm051.h
include/power/tps65217.h [new file with mode: 0644]
include/power/tps65910.h [new file with mode: 0644]
spl/Makefile

diff --git a/README b/README
index ccd47fa..2fcad7f 100644 (file)
--- a/README
+++ b/README
@@ -144,7 +144,6 @@ Directory Hierarchy:
       /arm1136         Files specific to ARM 1136 CPUs
       /ixp             Files specific to Intel XScale IXP CPUs
       /pxa             Files specific to Intel XScale PXA CPUs
-      /s3c44b0         Files specific to Samsung S3C44B0 CPUs
       /sa1100          Files specific to Intel StrongARM SA1100 CPUs
     /lib               Architecture specific library files
   /avr32               Files generic to AVR32 architecture
@@ -5588,15 +5587,17 @@ On ARM, the following registers are used:
 
        R0:     function argument word/integer result
        R1-R3:  function argument word
-       R9:     GOT pointer
-       R10:    stack limit (used only if stack checking if enabled)
+       R9:     platform specific
+       R10:    stack limit (used only if stack checking is enabled)
        R11:    argument (frame) pointer
        R12:    temporary workspace
        R13:    stack pointer
        R14:    link register
        R15:    program counter
 
-    ==> U-Boot will use R8 to hold a pointer to the global data
+    ==> U-Boot will use R9 to hold a pointer to the global data
+
+    Note: on ARM, only R_ARM_RELATIVE relocations are supported.
 
 On Nios II, the ABI is documented here:
        http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf
index ce3903b..d0cf43f 100644 (file)
@@ -16,7 +16,8 @@ endif
 endif
 
 LDFLAGS_FINAL += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
+                     -fno-common -ffixed-r9 -msoft-float
 
 # Support generic board on ARM
 __HAVE_ARCH_GENERIC_BOARD := y
@@ -94,7 +95,11 @@ PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
 endif
 endif
 
-# check that only R_ARM_RELATIVE relocations are generated
 ifneq ($(CONFIG_SPL_BUILD),y)
-ALL-y  += checkarmreloc
+# Check that only R_ARM_RELATIVE relocations are generated.
+ALL-y += checkarmreloc
+# The movt / movw can hardcode 16 bit parts of the addresses in the
+# instruction. Relocation is not supported for that case, so disable
+# such usage by requiring word relocations.
+PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
 endif
index 1ef6061..b4d396d 100644 (file)
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:     GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5
index 917da03..f4631cb 100644 (file)
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:     GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5t
index 56b6280..2581f0a 100644 (file)
@@ -6,8 +6,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS +=  -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
 # =========================================================================
 #
index 58fd756..67537dc 100644 (file)
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4
 # =========================================================================
 #
index 58fd756..67537dc 100644 (file)
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4
 # =========================================================================
 #
index 917ff7e..12b0d09 100644 (file)
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv5te
 # =========================================================================
 #
index 1e41c11..eb81a57 100644 (file)
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS +=  -march=armv4
 # =========================================================================
 #
index 1e41c11..eb81a57 100644 (file)
@@ -5,8 +5,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS +=  -march=armv4
 # =========================================================================
 #
index 2ea3d69..a31bf40 100644 (file)
@@ -27,6 +27,7 @@
 #include <miiphy.h>
 #include <cpsw.h>
 #include <asm/errno.h>
+#include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
@@ -137,6 +138,16 @@ int arch_misc_init(void)
 }
 
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
+/*
+ * This function is the place to do per-board things such as ramp up the
+ * MPU clock frequency.
+ */
+__weak void am33xx_spl_board_init(void)
+{
+       do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
 static void rtc32k_enable(void)
 {
        struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
index e5f287b..fabe259 100644 (file)
@@ -51,10 +51,14 @@ const struct dpll_regs dpll_ddr_regs = {
        .cm_div_m2_dpll         = CM_WKUP + 0xA0,
 };
 
-const struct dpll_params dpll_mpu = {
+struct dpll_params dpll_mpu_opp100 = {
                CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_core = {
+const struct dpll_params dpll_core_opp100 = {
                1000, OSC-1, -1, -1, 10, 8, 4};
+const struct dpll_params dpll_mpu = {
+               MPUPLL_M_300, OSC-1, 1, -1, -1, -1, -1};
+const struct dpll_params dpll_core = {
+               50, OSC-1, -1, -1, 1, 1, 1};
 const struct dpll_params dpll_per = {
                960, OSC-1, 5, -1, -1, -1, -1};
 
index 63afaaa..50eb598 100644 (file)
@@ -17,6 +17,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
+#include <power/tps65910.h>
 
 struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
 
@@ -119,3 +120,59 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_AM33XX
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev)
+{
+       int sil_rev;
+
+       sil_rev = readl(&cdev->deviceid) >> 28;
+
+       if (sil_rev == 1)
+               /* PG 2.0, efuse may not be set. */
+               return MPUPLL_M_800;
+       else if (sil_rev >= 2) {
+               /* Check what the efuse says our max speed is. */
+               int efuse_arm_mpu_max_freq;
+               efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma);
+               switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) {
+               case AM335X_ZCZ_1000:
+                       return MPUPLL_M_1000;
+               case AM335X_ZCZ_800:
+                       return MPUPLL_M_800;
+               case AM335X_ZCZ_720:
+                       return MPUPLL_M_720;
+               case AM335X_ZCZ_600:
+               case AM335X_ZCE_600:
+                       return MPUPLL_M_600;
+               case AM335X_ZCZ_300:
+               case AM335X_ZCE_300:
+                       return MPUPLL_M_300;
+               }
+       }
+
+       /* PG 1.0 or otherwise unknown, use the PG1.0 max */
+       return MPUPLL_M_720;
+}
+
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency)
+{
+       /* For PG2.1 and later, we have one set of values. */
+       if (sil_rev >= 2) {
+               switch (frequency) {
+               case MPUPLL_M_1000:
+                       return TPS65910_OP_REG_SEL_1_3_2_5;
+               case MPUPLL_M_800:
+                       return TPS65910_OP_REG_SEL_1_2_6;
+               case MPUPLL_M_720:
+                       return TPS65910_OP_REG_SEL_1_2_0;
+               case MPUPLL_M_600:
+               case MPUPLL_M_300:
+                       return TPS65910_OP_REG_SEL_1_1_3;
+               }
+       }
+
+       /* Default to PG1.0/PG2.0 values. */
+       return TPS65910_OP_REG_SEL_1_1_3;
+}
+#endif
index ca4a9e7..f0d9c04 100644 (file)
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:     GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # If armv7-a is not supported by GCC fall-back to armv5, which is
 # supported by more tool-chains
index 82b2b86..69e3053 100644 (file)
@@ -22,11 +22,11 @@ ENTRY(lowlevel_init)
        ldr     sp, =CONFIG_SYS_INIT_SP_ADDR
        bic     sp, sp, #7 /* 8-byte alignment for ABI compliance */
 #ifdef CONFIG_SPL_BUILD
-       ldr     r8, =gdata
+       ldr     r9, =gdata
 #else
        sub     sp, #GD_SIZE
        bic     sp, sp, #7
-       mov     r8, sp
+       mov     r9, sp
 #endif
        /*
         * Save the old lr(passed in ip) and the current lr to stack
index 6b4772b..0ffa03a 100644 (file)
@@ -76,6 +76,9 @@ void spl_board_init(void)
 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
        arch_misc_init();
 #endif
+#ifdef CONFIG_AM33XX
+       am33xx_spl_board_init();
+#endif
 }
 
 int board_mmc_init(bd_t *bis)
index 7580594..ab0c568 100644 (file)
@@ -589,13 +589,6 @@ void scale_vcores(struct vcores_data const *vcores)
 
        val = optimize_vcore_voltage(&vcores->iva);
        do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
-
-        if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
-               /* Configure LDO SRAM "magic" bits */
-               writel(2, (*prcm)->prm_sldo_core_setup);
-               writel(2, (*prcm)->prm_sldo_mpu_setup);
-               writel(2, (*prcm)->prm_sldo_mm_setup);
-       }
 }
 
 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
index 579818d..5a3d52c 100644 (file)
@@ -286,12 +286,6 @@ struct prcm_regs const omap5_es1_prcm = {
        .prm_vc_val_bypass = 0x4ae07ba0,
        .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
        .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
-       .prm_sldo_core_setup = 0x4ae07bc4,
-       .prm_sldo_core_ctrl = 0x4ae07bc8,
-       .prm_sldo_mpu_setup = 0x4ae07bcc,
-       .prm_sldo_mpu_ctrl = 0x4ae07bd0,
-       .prm_sldo_mm_setup = 0x4ae07bd4,
-       .prm_sldo_mm_ctrl = 0x4ae07bd8,
 
        /* SCRM stuff, used by some boards */
        .scrm_auxclk0 = 0x4ae0a310,
@@ -735,12 +729,6 @@ struct prcm_regs const omap5_es2_prcm = {
        .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
        .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
 
-       .prm_sldo_core_setup = 0x4ae07cc4,
-       .prm_sldo_core_ctrl = 0x4ae07cc8,
-       .prm_sldo_mpu_setup = 0x4ae07ccc,
-       .prm_sldo_mpu_ctrl = 0x4ae07cd0,
-       .prm_sldo_mm_setup = 0x4ae07cd4,
-       .prm_sldo_mm_ctrl = 0x4ae07cd8,
        .prm_abbldo_mpu_setup = 0x4ae07cdc,
        .prm_abbldo_mpu_ctrl = 0x4ae07ce0,
 
index 4f01610..3a36ab6 100644 (file)
@@ -4,7 +4,6 @@
 #
 # SPDX-License-Identifier:     GPL-2.0+
 #
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v7a.
 PLATFORM_CPPFLAGS += -march=armv5
index 0133565..3b8d949 100644 (file)
@@ -57,7 +57,7 @@ int timer_init(void)
                        SCUTIMER_CONTROL_ENABLE_MASK;
 
        /* Load the timer counter register */
-       writel(0xFFFFFFFF, &timer_base->counter);
+       writel(0xFFFFFFFF, &timer_base->load);
 
        /*
         * Start the A9Timer device
index 0f12f8b..fd47c60 100644 (file)
@@ -8,7 +8,7 @@
 
 BIG_ENDIAN = y
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
+PLATFORM_RELFLAGS += -mbig-endian
 
 PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
 
index 535bca3..d8d263d 100644 (file)
@@ -6,8 +6,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -mcpu=xscale
 # =========================================================================
 #
diff --git a/arch/arm/cpu/s3c44b0/Makefile b/arch/arm/cpu/s3c44b0/Makefile
deleted file mode 100644 (file)
index 39fdbf8..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(CPU).o
-
-START  = start.o
-
-COBJS  += cache.o
-COBJS  += cpu.o
-COBJS  += timer.o
-
-SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
-START  := $(addprefix $(obj),$(START))
-
-all:   $(obj).depend $(START) $(LIB)
-
-$(LIB):        $(OBJS)
-       $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/s3c44b0/cache.c b/arch/arm/cpu/s3c44b0/cache.c
deleted file mode 100644 (file)
index aeee02d..0000000
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-static void s3c44b0_flush_cache(void)
-{
-       volatile int i;
-       /* flush cycle */
-       for(i=0x10002000;i<0x10004800;i+=16)
-       {
-               *((int *)i)=0x0;
-       }
-}
-
-void icache_enable (void)
-{
-       ulong reg;
-
-       s3c44b0_flush_cache();
-
-       /*
-               Init cache
-               Non-cacheable area (everything outside RAM)
-               0x0000:0000 - 0x0C00:0000
-        */
-       NCACHBE0 = 0xC0000000;
-       NCACHBE1 = 0x00000000;
-
-       /*
-               Enable chache
-       */
-       reg = SYSCFG;
-       reg |= 0x00000006; /* 8kB */
-       SYSCFG = reg;
-}
-
-void icache_disable (void)
-{
-       ulong reg;
-
-       reg = SYSCFG;
-       reg &= ~0x00000006; /* 8kB */
-       SYSCFG = reg;
-}
-
-int icache_status (void)
-{
-       return 0;
-}
-
-void dcache_enable (void)
-{
-       icache_enable();
-}
-
-void dcache_disable (void)
-{
-       icache_disable();
-}
-
-int dcache_status (void)
-{
-       return dcache_status();
-}
diff --git a/arch/arm/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk
deleted file mode 100644 (file)
index b902ca3..0000000
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
diff --git a/arch/arm/cpu/s3c44b0/cpu.c b/arch/arm/cpu/s3c44b0/cpu.c
deleted file mode 100644 (file)
index fa93150..0000000
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * S3C44B0 CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-int arch_cpu_init (void)
-{
-       icache_enable();
-
-       return 0;
-}
-
-int cleanup_before_linux (void)
-{
-       /*
-               cache memory should be enabled before calling
-               Linux to make the kernel uncompression faster
-       */
-       icache_enable();
-
-       disable_interrupts ();
-
-       return 0;
-}
-
-void reset_cpu (ulong addr)
-{
-       /*
-               reset the cpu using watchdog
-       */
-
-       /* Disable the watchdog.*/
-       WTCON&=~(1<<5);
-
-       /* set the timeout value to a short time... */
-       WTCNT = 0x1;
-
-       /* Enable the watchdog. */
-       WTCON|=1;
-       WTCON|=(1<<5);
-
-       while(1) {
-               /*NOP*/
-       }
-}
diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S
deleted file mode 100644 (file)
index 6a59592..0000000
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * Startup Code for S3C44B0 CPU-core
- *
- * (C) Copyright 2004
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- * Jump vector table
- */
-
-
-.globl _start
-_start:        b       reset
-       add     pc, pc, #0x0c000000
-       add     pc, pc, #0x0c000000
-       add     pc, pc, #0x0c000000
-       add     pc, pc, #0x0c000000
-       add     pc, pc, #0x0c000000
-       add     pc, pc, #0x0c000000
-       add     pc, pc, #0x0c000000
-
-       .balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate u-boot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
-       .word   CONFIG_SPL_TEXT_BASE
-#else
-       .word   CONFIG_SYS_TEXT_BASE
-#endif
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-       .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-       .word __bss_end - _start
-
-.globl _end_ofs
-_end_ofs:
-       .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-       .word   0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-       .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-       .word   0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-       /*
-        * set the cpu to SVC32 mode
-        */
-       mrs     r0,cpsr
-       bic     r0,r0,#0x1f
-       orr     r0,r0,#0xd3
-       msr     cpsr,r0
-
-       /*
-        * we do sys-critical inits only at reboot,
-        * not when booting from ram!
-        */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-       bl      cpu_init_crit
-       /*
-        * before relocating, we have to setup RAM timing
-        * because memory timing is board-dependend, you will
-        * find a lowlevel_init.S in your board directory.
-        */
-       bl      lowlevel_init
-#endif
-
-       bl      _main
-
-/*------------------------------------------------------------------------------*/
-
-       .globl  c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-       bx      lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#define INTCON (0x01c00000+0x200000)
-#define INTMSK (0x01c00000+0x20000c)
-#define LOCKTIME (0x01c00000+0x18000c)
-#define PLLCON (0x01c00000+0x180000)
-#define CLKCON (0x01c00000+0x180004)
-#define WTCON (0x01c00000+0x130000)
-cpu_init_crit:
-       /* disable watch dog */
-       ldr     r0, =WTCON
-       ldr     r1, =0x0
-       str     r1, [r0]
-
-       /*
-        * mask all IRQs by clearing all bits in the INTMRs
-        */
-       ldr     r1,=INTMSK
-       ldr     r0, =0x03fffeff
-       str     r0, [r1]
-
-       ldr     r1, =INTCON
-       ldr     r0, =0x05
-       str     r0, [r1]
-
-       /* Set Clock Control Register */
-       ldr     r1, =LOCKTIME
-       ldrb    r0, =800
-       strb    r0, [r1]
-
-       ldr     r1, =PLLCON
-
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-       ldr     r0, =0x34031    /* 66MHz (Quartz=11MHz) */
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-       ldr     r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz  */
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-
-       str     r0, [r1]
-
-       ldr     r1,=CLKCON
-       ldr     r0, =0x7ff8
-       str     r0, [r1]
-
-       mov     pc, lr
-
-
-/*************************************************/
-/*     interrupt vectors       */
-/*************************************************/
-real_vectors:
-       b       reset
-       b       undefined_instruction
-       b       software_interrupt
-       b       prefetch_abort
-       b       data_abort
-       b       not_used
-       b       irq
-       b       fiq
-
-/*************************************************/
-
-undefined_instruction:
-       mov     r6, #3
-       b       reset
-
-software_interrupt:
-       mov     r6, #4
-       b       reset
-
-prefetch_abort:
-       mov     r6, #5
-       b       reset
-
-data_abort:
-       mov     r6, #6
-       b       reset
-
-not_used:
-       /* we *should* never reach this */
-       mov     r6, #7
-       b       reset
-
-irq:
-       mov     r6, #8
-       b       reset
-
-fiq:
-       mov     r6, #9
-       b       reset
diff --git a/arch/arm/cpu/s3c44b0/timer.c b/arch/arm/cpu/s3c44b0/timer.c
deleted file mode 100644 (file)
index f25af7a..0000000
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (TCNTO1 & 0xffff)
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ NOT supported
-#endif
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-       TCFG0 = 0x000000E9;
-       TCFG1 = 0x00000004;
-       TCON = 0x00000900;
-       TCNTB1 = TIMER_LOAD_VAL;
-       TCMPB1 = 0;
-       TCON = 0x00000B00;
-       TCON = 0x00000900;
-
-
-       lastdec = TCNTB1 = TIMER_LOAD_VAL;
-       timestamp = 0;
-       return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-       ulong tmo;
-
-       tmo = usec / 1000;
-       tmo *= CONFIG_SYS_HZ;
-       tmo /= 8;
-
-       tmo += get_timer (0);
-
-       while (get_timer_masked () < tmo)
-               /*NOP*/;
-}
-
-ulong get_timer_masked (void)
-{
-       ulong now = READ_TIMER;
-
-       if (lastdec >= now) {
-               /* normal mode */
-               timestamp += lastdec - now;
-       } else {
-               /* we have an overflow ... */
-               timestamp += lastdec + TIMER_LOAD_VAL - now;
-       }
-       lastdec = now;
-
-       return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-       ulong tmo;
-       ulong endtime;
-       signed long diff;
-
-       if (usec >= 1000) {
-               tmo = usec / 1000;
-               tmo *= CONFIG_SYS_HZ;
-               tmo /= 8;
-       } else {
-               tmo = usec * CONFIG_SYS_HZ;
-               tmo /= (1000*8);
-       }
-
-       endtime = get_timer(0) + tmo;
-
-       do {
-               ulong now = get_timer_masked ();
-               diff = endtime - now;
-       } while (diff >= 0);
-}
index 576f685..b3026cc 100644 (file)
@@ -6,8 +6,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
 # =========================================================================
 #
index 140379f..02ed595 100644 (file)
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
+/* MAIN PLL Fdll supported frequencies */
+#define MPUPLL_M_1000  1000
+#define MPUPLL_M_800   800
+#define MPUPLL_M_720   720
+#define MPUPLL_M_600   600
+#define MPUPLL_M_550   550
+#define MPUPLL_M_300   300
+
 /* MAIN PLL Fdll = 550 MHz, by default */
 #ifndef CONFIG_SYS_MPUCLK
-#define CONFIG_SYS_MPUCLK      550
+#define CONFIG_SYS_MPUCLK      MPUPLL_M_550
 #endif
 
 #define UART_RESET             (0x1 << 1)
@@ -21,5 +29,7 @@
 #define UART_SMART_IDLE_EN     (0x1 << 0x3)
 
 extern void enable_dmm_clocks(void);
+extern const struct dpll_params dpll_core_opp100;
+extern struct dpll_params dpll_mpu_opp100;
 
 #endif /* endif _CLOCKS_AM33XX_H_ */
index 73e6db8..52fa128 100644 (file)
 #define AM335X                         0xB944
 #define TI81XX                         0xB81E
 #define DEVICE_ID                      (CTRL_BASE + 0x0600)
+#define DEVICE_ID_MASK                 0x1FFF
+
+/* MPU max frequencies */
+#define AM335X_ZCZ_300                 0x1FEF
+#define AM335X_ZCZ_600                 0x1FAF
+#define AM335X_ZCZ_720                 0x1F2F
+#define AM335X_ZCZ_800                 0x1E2F
+#define AM335X_ZCZ_1000                        0x1C2F
+#define AM335X_ZCE_300                 0x1FDF
+#define AM335X_ZCE_600                 0x1F9F
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK                   (BIT(0) | BIT(1) | BIT(2)\
@@ -509,6 +519,8 @@ struct ctrl_dev {
        unsigned int macid1h;           /* offset 0x3c */
        unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
+       unsigned int resv5[106];
+       unsigned int efuse_sma;         /* offset 0x1FC */
 };
 
 /* gmii_sel register defines */
index c6070a3..87b7d36 100644 (file)
@@ -10,6 +10,7 @@
 
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
+#include <asm/arch/cpu.h>
 
 #define BOARD_REV_ID   0x0
 
@@ -42,4 +43,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 #ifdef CONFIG_NOR_BOOT
 void enable_norboot_pin_mux(void);
 #endif
+void am33xx_spl_board_init(void);
+int am335x_get_efuse_mpu_max_freq(struct ctrl_dev *cdev);
+int am335x_get_tps65910_mpu_vdd(int sil_rev, int frequency);
 #endif
diff --git a/arch/arm/include/asm/arch-s3c44b0/hardware.h b/arch/arm/include/asm/arch-s3c44b0/hardware.h
deleted file mode 100644 (file)
index 146e265..0000000
+++ /dev/null
@@ -1,281 +0,0 @@
-/********************************************************/
-/*                                                     */
-/* Samsung S3C44B0                                     */
-/* tpu <tapu@371.net>                                  */
-/*                                                     */
-/********************************************************/
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define REGBASE                0x01c00000
-#define REGL(addr)     (*(volatile unsigned int *)(REGBASE+addr))
-#define REGW(addr)     (*(volatile unsigned short *)(REGBASE+addr))
-#define REGB(addr)     (*(volatile unsigned char *)(REGBASE+addr))
-
-
-/*****************************/
-/* CPU Wrapper Registers     */
-/*****************************/
-
-#define SYSCFG         REGL(0x000000)
-#define NCACHBE0       REGL(0x000004)
-#define NCACHBE1       REGL(0x000008)
-#define SBUSCON                REGL(0x040000)
-
-/************************************/
-/* Memory Controller Registers      */
-/************************************/
-
-#define BWSCON         REGL(0x080000)
-#define BANKCON0       REGL(0x080004)
-#define BANKCON1       REGL(0x080008)
-#define BANKCON2       REGL(0x08000c)
-#define BANKCON3       REGL(0x080010)
-#define BANKCON4       REGL(0x080014)
-#define BANKCON5       REGL(0x080018)
-#define BANKCON6       REGL(0x08001c)
-#define BANKCON7       REGL(0x080020)
-#define REFRESH                REGL(0x080024)
-#define BANKSIZE       REGL(0x080028)
-#define MRSRB6         REGL(0x08002c)
-#define MRSRB7         REGL(0x080030)
-
-/*********************/
-/* UART Registers    */
-/*********************/
-
-#define ULCON0         REGL(0x100000)
-#define ULCON1         REGL(0x104000)
-#define UCON0          REGL(0x100004)
-#define UCON1          REGL(0x104004)
-#define UFCON0         REGL(0x100008)
-#define UFCON1         REGL(0x104008)
-#define UMCON0         REGL(0x10000c)
-#define UMCON1         REGL(0x10400c)
-#define UTRSTAT0       REGL(0x100010)
-#define UTRSTAT1       REGL(0x104010)
-#define UERSTAT0       REGL(0x100014)
-#define UERSTAT1       REGL(0x104014)
-#define UFSTAT0                REGL(0x100018)
-#define UFSTAT1                REGL(0x104018)
-#define UMSTAT0                REGL(0x10001c)
-#define UMSTAT1                REGL(0x10401c)
-#define UTXH0          REGB(0x100020)
-#define UTXH1          REGB(0x104020)
-#define URXH0          REGB(0x100024)
-#define URXH1          REGB(0x104024)
-#define UBRDIV0                REGL(0x100028)
-#define UBRDIV1                REGL(0x104028)
-
-/*******************/
-/* SIO Registers   */
-/*******************/
-
-#define SIOCON         REGL(0x114000)
-#define SIODAT         REGL(0x114004)
-#define SBRDR          REGL(0x114008)
-#define ITVCNT         REGL(0x11400c)
-#define DCNTZ          REGL(0x114010)
-
-/********************/
-/* IIS Registers    */
-/********************/
-
-#define IISCON         REGL(0x118000)
-#define IISMOD         REGL(0x118004)
-#define IISPSR         REGL(0x118008)
-#define IISFIFCON      REGL(0x11800c)
-#define IISFIF         REGW(0x118010)
-
-/**************************/
-/* I/O Ports Registers    */
-/**************************/
-
-#define PCONA          REGL(0x120000)
-#define PDATA          REGL(0x120004)
-#define PCONB          REGL(0x120008)
-#define PDATB          REGL(0x12000c)
-#define PCONC          REGL(0x120010)
-#define PDATC          REGL(0x120014)
-#define PUPC           REGL(0x120018)
-#define PCOND          REGL(0x12001c)
-#define PDATD          REGL(0x120020)
-#define PUPD           REGL(0x120024)
-#define PCONE          REGL(0x120028)
-#define PDATE          REGL(0x12002c)
-#define PUPE           REGL(0x120030)
-#define PCONF          REGL(0x120034)
-#define PDATF          REGL(0x120038)
-#define PUPF           REGL(0x12003c)
-#define PCONG          REGL(0x120040)
-#define PDATG          REGL(0x120044)
-#define PUPG           REGL(0x120048)
-#define SPUCR          REGL(0x12004c)
-#define EXTINT         REGL(0x120050)
-#define EXTINTPND      REGL(0x120054)
-
-/*********************************/
-/* WatchDog Timers Registers     */
-/*********************************/
-
-#define WTCON          REGL(0x130000)
-#define WTDAT          REGL(0x130004)
-#define WTCNT          REGL(0x130008)
-
-/*********************************/
-/* A/D Converter Registers       */
-/*********************************/
-
-#define ADCCON         REGL(0x140000)
-#define ADCPSR         REGL(0x140004)
-#define ADCDAT         REGL(0x140008)
-
-/***************************/
-/* PWM Timer Registers     */
-/***************************/
-
-#define TCFG0          REGL(0x150000)
-#define TCFG1          REGL(0x150004)
-#define TCON           REGL(0x150008)
-#define TCNTB0         REGL(0x15000c)
-#define TCMPB0         REGL(0x150010)
-#define TCNTO0         REGL(0x150014)
-#define TCNTB1         REGL(0x150018)
-#define TCMPB1         REGL(0x15001c)
-#define TCNTO1         REGL(0x150020)
-#define TCNTB2         REGL(0x150024)
-#define TCMPB2         REGL(0x150028)
-#define TCNTO2         REGL(0x15002c)
-#define TCNTB3         REGL(0x150030)
-#define TCMPB3         REGL(0x150034)
-#define TCNTO3         REGL(0x150038)
-#define TCNTB4         REGL(0x15003c)
-#define TCMPB4         REGL(0x150040)
-#define TCNTO4         REGL(0x150044)
-#define TCNTB5         REGL(0x150048)
-#define TCNTO5         REGL(0x15004c)
-
-/*********************/
-/* IIC Registers     */
-/*********************/
-
-#define IICCON         REGL(0x160000)
-#define IICSTAT                REGL(0x160004)
-#define IICADD         REGL(0x160008)
-#define IICDS          REGL(0x16000c)
-
-/*********************/
-/* RTC Registers     */
-/*********************/
-
-#define RTCCON         REGB(0x170040)
-#define RTCALM         REGB(0x170050)
-#define ALMSEC         REGB(0x170054)
-#define ALMMIN         REGB(0x170058)
-#define ALMHOUR                REGB(0x17005c)
-#define ALMDAY         REGB(0x170060)
-#define ALMMON         REGB(0x170064)
-#define ALMYEAR                REGB(0x170068)
-#define RTCRST         REGB(0x17006c)
-#define BCDSEC         REGB(0x170070)
-#define BCDMIN         REGB(0x170074)
-#define BCDHOUR                REGB(0x170078)
-#define BCDDAY         REGB(0x17007c)
-#define BCDDATE                REGB(0x170080)
-#define BCDMON         REGB(0x170084)
-#define BCDYEAR                REGB(0x170088)
-#define TICINT         REGB(0x17008c)
-
-/*********************************/
-/* Clock & Power Registers       */
-/*********************************/
-
-#define PLLCON         REGL(0x180000)
-#define CLKCON         REGL(0x180004)
-#define CLKSLOW                REGL(0x180008)
-#define LOCKTIME       REGL(0x18000c)
-
-/**************************************/
-/* Interrupt Controller Registers     */
-/**************************************/
-
-#define INTCON         REGL(0x200000)
-#define INTPND         REGL(0x200004)
-#define INTMOD         REGL(0x200008)
-#define INTMSK         REGL(0x20000c)
-#define I_PSLV         REGL(0x200010)
-#define I_PMST         REGL(0x200014)
-#define I_CSLV         REGL(0x200018)
-#define I_CMST         REGL(0x20001c)
-#define I_ISPR         REGL(0x200020)
-#define I_ISPC         REGL(0x200024)
-#define F_ISPR         REGL(0x200038)
-#define F_ISPC         REGL(0x20003c)
-
-/********************************/
-/* LCD Controller Registers     */
-/********************************/
-
-#define LCDCON1                REGL(0x300000)
-#define LCDCON2                REGL(0x300004)
-#define LCDSADDR1      REGL(0x300008)
-#define LCDSADDR2      REGL(0x30000c)
-#define LCDSADDR3      REGL(0x300010)
-#define REDLUT         REGL(0x300014)
-#define GREENLUT       REGL(0x300018)
-#define BLUELUT                REGL(0x30001c)
-#define DP1_2          REGL(0x300020)
-#define DP4_7          REGL(0x300024)
-#define DP3_5          REGL(0x300028)
-#define DP2_3          REGL(0x30002c)
-#define DP5_7          REGL(0x300030)
-#define DP3_4          REGL(0x300034)
-#define DP4_5          REGL(0x300038)
-#define DP6_7          REGL(0x30003c)
-#define LCDCON3                REGL(0x300040)
-#define DITHMODE       REGL(0x300044)
-
-/*********************/
-/* DMA Registers     */
-/*********************/
-
-#define ZDCON0         REGL(0x280000)
-#define ZDISRC0                REGL(0x280004)
-#define ZDIDES0                REGL(0x280008)
-#define ZDICNT0                REGL(0x28000c)
-#define ZDCSRC0                REGL(0x280010)
-#define ZDCDES0                REGL(0x280014)
-#define ZDCCNT0                REGL(0x280018)
-
-#define ZDCON1         REGL(0x280020)
-#define ZDISRC1                REGL(0x280024)
-#define ZDIDES1                REGL(0x280028)
-#define ZDICNT1                REGL(0x28002c)
-#define ZDCSRC1                REGL(0x280030)
-#define ZDCDES1                REGL(0x280034)
-#define ZDCCNT1                REGL(0x280038)
-
-#define BDCON0         REGL(0x380000)
-#define BDISRC0                REGL(0x380004)
-#define BDIDES0                REGL(0x380008)
-#define BDICNT0                REGL(0x38000c)
-#define BDCSRC0                REGL(0x380010)
-#define BDCDES0                REGL(0x380014)
-#define BDCCNT0                REGL(0x380018)
-
-#define BDCON1         REGL(0x380020)
-#define BDISRC1                REGL(0x380024)
-#define BDIDES1                REGL(0x380028)
-#define BDICNT1                REGL(0x38002c)
-#define BDCSRC1                REGL(0x380030)
-#define BDCDES1                REGL(0x380034)
-#define BDCCNT1                REGL(0x380038)
-
-
-#define CLEAR_PEND_INT(n)       I_ISPC = (1<<(n))
-#define INT_ENABLE(n)          INTMSK &= ~(1<<(n))
-#define INT_DISABLE(n)         INTMSK |= (1<<(n))
-
-#define HARD_RESET_NOW()
-
-#endif /* __ASM_ARCH_HARDWARE_H */
index 009863b..55a4e26 100644 (file)
@@ -16,7 +16,7 @@ enum dma_data_direction {
 
 static void *dma_alloc_coherent(size_t len, unsigned long *handle)
 {
-       *handle = (unsigned long)malloc(len);
+       *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
        return (void *)*handle;
 }
 
index 79a9597..e126436 100644 (file)
@@ -47,6 +47,6 @@ struct arch_global_data {
 
 #include <asm-generic/global_data.h>
 
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
+#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r9")
 
 #endif /* __ASM_GBL_DATA_H */
index 5e2f027..61fee9f 100644 (file)
@@ -310,12 +310,6 @@ struct prcm_regs {
        u32 prm_vc_val_bypass;
        u32 prm_vc_cfg_i2c_mode;
        u32 prm_vc_cfg_i2c_clk;
-       u32 prm_sldo_core_setup;
-       u32 prm_sldo_core_ctrl;
-       u32 prm_sldo_mpu_setup;
-       u32 prm_sldo_mpu_ctrl;
-       u32 prm_sldo_mm_setup;
-       u32 prm_sldo_mm_ctrl;
        u32 prm_abbldo_mpu_setup;
        u32 prm_abbldo_mpu_ctrl;
 
index 960d12e..ac54b93 100644 (file)
@@ -69,7 +69,7 @@ ENTRY(_main)
        bic     sp, sp, #7      /* 8-byte alignment for ABI compliance */
        sub     sp, #GD_SIZE    /* allocate one GD above SP */
        bic     sp, sp, #7      /* 8-byte alignment for ABI compliance */
-       mov     r8, sp          /* GD is above SP */
+       mov     r9, sp          /* GD is above SP */
        mov     r0, #0
        bl      board_init_f
 
@@ -81,15 +81,15 @@ ENTRY(_main)
  * 'here' but relocated.
  */
 
-       ldr     sp, [r8, #GD_START_ADDR_SP]     /* sp = gd->start_addr_sp */
+       ldr     sp, [r9, #GD_START_ADDR_SP]     /* sp = gd->start_addr_sp */
        bic     sp, sp, #7      /* 8-byte alignment for ABI compliance */
-       ldr     r8, [r8, #GD_BD]                /* r8 = gd->bd */
-       sub     r8, r8, #GD_SIZE                /* new GD is below bd */
+       ldr     r9, [r9, #GD_BD]                /* r9 = gd->bd */
+       sub     r9, r9, #GD_SIZE                /* new GD is below bd */
 
        adr     lr, here
-       ldr     r0, [r8, #GD_RELOC_OFF]         /* r0 = gd->reloc_off */
+       ldr     r0, [r9, #GD_RELOC_OFF]         /* r0 = gd->reloc_off */
        add     lr, lr, r0
-       ldr     r0, [r8, #GD_RELOCADDR]         /* r0 = gd->relocaddr */
+       ldr     r0, [r9, #GD_RELOCADDR]         /* r0 = gd->relocaddr */
        b       relocate_code
 here:
 
@@ -111,8 +111,8 @@ clbss_l:cmp r0, r1                  /* while not at end of BSS */
        bl red_led_on
 
        /* call board_init_r(gd_t *id, ulong dest_addr) */
-       mov     r0, r8                  /* gd_t */
-       ldr     r1, [r8, #GD_RELOCADDR] /* dest_addr */
+       mov     r0, r9                  /* gd_t */
+       ldr     r1, [r9, #GD_RELOCADDR] /* dest_addr */
        /* call board_init_r */
        ldr     pc, =board_init_r       /* this is auto-relocated! */
 
index ab90430..a62a556 100644 (file)
@@ -22,7 +22,7 @@
 
 ENTRY(relocate_code)
        ldr     r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
-       subs    r9, r0, r1              /* r9 <- relocation offset */
+       subs    r4, r0, r1              /* r4 <- relocation offset */
        beq     relocate_done           /* skip relocation */
        ldr     r2, =__image_copy_end   /* r2 <- SRC &__image_copy_end */
 
@@ -44,9 +44,9 @@ fixloop:
        bne     fixnext
 
        /* relative fix: increase location by offset */
-       add     r0, r0, r9
+       add     r0, r0, r4
        ldr     r1, [r0]
-       add     r1, r1, r9
+       add     r1, r1, r4
        str     r1, [r0]
 fixnext:
        cmp     r2, r3
index 26d0be4..dfcc596 100644 (file)
@@ -25,9 +25,6 @@ gd_t gdata __attribute__ ((section(".data")));
  */
 void __weak board_init_f(ulong dummy)
 {
-       /* Set the stack pointer. */
-       asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
 
index cc04426..c2fc5a6 100644 (file)
@@ -26,6 +26,8 @@
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
+#include <power/tps65217.h>
+#include <power/tps65910.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -244,6 +246,150 @@ const struct dpll_params dpll_ddr_evm_sk = {
 const struct dpll_params dpll_ddr_bone_black = {
                400, OSC-1, 1, -1, -1, -1, -1};
 
+void am33xx_spl_board_init(void)
+{
+       struct am335x_baseboard_id header;
+       int mpu_vdd;
+
+       if (read_eeprom(&header) < 0)
+               puts("Could not get board ID.\n");
+
+       /* Get the frequency */
+       dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+       if (board_is_bone(&header) || board_is_bone_lt(&header)) {
+               /* BeagleBone PMIC Code */
+               int usb_cur_lim;
+
+               /*
+                * Only perform PMIC configurations if board rev > A1
+                * on Beaglebone White
+                */
+               if (board_is_bone(&header) && !strncmp(header.version,
+                                                      "00A1", 4))
+                       return;
+
+               if (i2c_probe(TPS65217_CHIP_PM))
+                       return;
+
+               /*
+                * On Beaglebone White we need to ensure we have AC power
+                * before increasing the frequency.
+                */
+               if (board_is_bone(&header)) {
+                       uchar pmic_status_reg;
+                       if (tps65217_reg_read(TPS65217_STATUS,
+                                             &pmic_status_reg))
+                               return;
+                       if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
+                               puts("No AC power, disabling frequency switch\n");
+                               return;
+                       }
+               }
+
+               /*
+                * Override what we have detected since we know if we have
+                * a Beaglebone Black it supports 1GHz.
+                */
+               if (board_is_bone_lt(&header))
+                       dpll_mpu_opp100.m = MPUPLL_M_1000;
+
+               /*
+                * Increase USB current limit to 1300mA or 1800mA and set
+                * the MPU voltage controller as needed.
+                */
+               if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
+                       usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
+                       mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+               } else {
+                       usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
+                       mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+               }
+
+               if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
+                                      TPS65217_POWER_PATH,
+                                      usb_cur_lim,
+                                      TPS65217_USB_INPUT_CUR_LIMIT_MASK))
+                       puts("tps65217_reg_write failure\n");
+
+               /* Set DCDC3 (CORE) voltage to 1.125V */
+               if (tps65217_voltage_update(TPS65217_DEFDCDC3,
+                                           TPS65217_DCDC_VOLT_SEL_1125MV)) {
+                       puts("tps65217_voltage_update failure\n");
+                       return;
+               }
+
+               /* Set CORE Frequencies to OPP100 */
+               do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+               /* Set DCDC2 (MPU) voltage */
+               if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+                       puts("tps65217_voltage_update failure\n");
+                       return;
+               }
+
+               /*
+                * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
+                * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
+                */
+               if (board_is_bone(&header)) {
+                       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                                              TPS65217_DEFLS1,
+                                              TPS65217_LDO_VOLTAGE_OUT_3_3,
+                                              TPS65217_LDO_MASK))
+                               puts("tps65217_reg_write failure\n");
+               } else {
+                       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                                              TPS65217_DEFLS1,
+                                              TPS65217_LDO_VOLTAGE_OUT_1_8,
+                                              TPS65217_LDO_MASK))
+                               puts("tps65217_reg_write failure\n");
+               }
+
+               if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
+                                      TPS65217_DEFLS2,
+                                      TPS65217_LDO_VOLTAGE_OUT_3_3,
+                                      TPS65217_LDO_MASK))
+                       puts("tps65217_reg_write failure\n");
+       } else {
+               int sil_rev;
+
+               /*
+                * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
+                * MPU frequencies we support we use a CORE voltage of
+                * 1.1375V.  For MPU voltage we need to switch based on
+                * the frequency we are running at.
+                */
+               if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
+                       return;
+
+               /*
+                * Depending on MPU clock and PG we will need a different
+                * VDD to drive at that speed.
+                */
+               sil_rev = readl(&cdev->deviceid) >> 28;
+               mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
+                                                     dpll_mpu_opp100.m);
+
+               /* Tell the TPS65910 to use i2c */
+               tps65910_set_i2c_control();
+
+               /* First update MPU voltage. */
+               if (tps65910_voltage_update(MPU, mpu_vdd))
+                       return;
+
+               /* Second, update the CORE voltage. */
+               if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
+                       return;
+
+               /* Set CORE Frequencies to OPP100 */
+               do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+       }
+
+       /* Set MPU Frequency to what we detected now that voltages are set */
+       do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
 const struct dpll_params *get_dpll_ddr_params(void)
 {
        struct am335x_baseboard_id header;
index 5d9fb33..6aaeb86 100644 (file)
@@ -228,31 +228,26 @@ III) Analysis of in-tree drivers
   The driver is standard rtc. Simple conversion is possible.
 
 
-  34) drivers/rtc/s3c44b0_rtc.c
-  -----------------------------
-  The driver is standard rtc. Simple conversion is possible.
-
-
-  35) drivers/rtc/ds1337.c
+  34) drivers/rtc/ds1337.c
   ------------------------
   The driver is standard rtc. Simple conversion is possible.
 
 
-  36) drivers/rtc/isl1208.c
+  35) drivers/rtc/isl1208.c
   -------------------------
   The driver is standard rtc. Simple conversion is possible.
 
 
-  37) drivers/rtc/max6900.c
+  36) drivers/rtc/max6900.c
   -------------------------
   The driver is standard rtc. Simple conversion is possible.
 
 
-  38) drivers/rtc/mc146818.c
+  37) drivers/rtc/mc146818.c
   --------------------------
   The driver is standard rtc. Simple conversion is possible.
 
 
-  39) drivers/rtc/at91sam9_rtt.c
+  38) drivers/rtc/at91sam9_rtt.c
   ------------------------------
   The driver is standard rtc. Simple conversion is possible.
index 1011c32..54f853e 100644 (file)
@@ -148,32 +148,28 @@ III) Analysis of in-tree drivers
   --------------------
   This driver, being quite ad-hoc might need some work to bring back to shape.
 
-  22) serial_s3c44b0.c
-  --------------------
-  No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
-  23) serial_s5p.c
+  22) serial_s5p.c
   ----------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  24) serial_sa1100.c
+  23) serial_sa1100.c
   -------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  25) serial_sh.c
+  24) serial_sh.c
   ---------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  26) serial_xuartlite.c
+  25) serial_xuartlite.c
   ----------------------
   No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
 
-  27) usbtty.c
+  26) usbtty.c
   ------------
   This driver seems very complicated and entangled with USB framework. The
   conversion might be complicated here.
 
-  28) arch/powerpc/cpu/mpc512x/serial.c
+  27) arch/powerpc/cpu/mpc512x/serial.c
   -------------------------------------
   This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
   proper place.
index 37ccbd1..df3092e 100644 (file)
@@ -21,7 +21,6 @@ COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o
 COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o
 COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
-COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
 COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
 COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
diff --git a/drivers/i2c/s3c44b0_i2c.c b/drivers/i2c/s3c44b0_i2c.c
deleted file mode 100644 (file)
index 8445e01..0000000
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-
-/*
- * Initialization, must be called once on start up, may be called
- * repeatedly to change the speed and slave addresses.
- */
-void i2c_init(int speed, int slaveaddr)
-{
-       /*
-               setting up I2C support
-       */
-       unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF;
-
-       save_F = PCONF;
-       save_PF = PUPF;
-
-       rPCONF = ((save_F & ~(0xF))| 0xa);
-       rPUPF = (save_PF | 0x3);
-       PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/
-       PUPF = rPUPF; /* Disable pull-up */
-
-       /* Configuring pin for WC pin of EEprom */
-       rPCONA = PCONA;
-       rPCONA &= ~(1<<9);
-       PCONA = rPCONA;
-
-       rPDATA = PDATA;
-       rPDATA &= ~(1<<9);
-       PDATA = rPDATA;
-
-       /*
-               Enable ACK, IICCLK=MCLK/16, enable interrupt
-               75MHz/16/(12+1) = 390625 Hz
-       */
-       rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC);
-       IICCON = rIICCON;
-
-       IICADD = slaveaddr;
-}
-
-/*
- * Probe the given I2C chip address.  Returns 0 if a chip responded,
- * not 0 on failure.
- */
-int i2c_probe(uchar chip)
-{
-       /*
-               not implemented
-       */
-
-       printf("i2c_probe chip %d\n", (int) chip);
-       return -1;
-}
-
-/*
- * Read/Write interface:
- *   chip:    I2C chip address, range 0..127
- *   addr:    Memory (register) address within the chip
- *   alen:    Number of bytes to use for addr (typically 1, 2 for larger
- *              memories, 0 for register type devices with only one
- *              register)
- *   buffer:  Where to read/write the data
- *   len:     How many bytes to read/write
- *
- *   Returns: 0 on success, not 0 on failure
- */
-
-#define S3C44B0X_rIIC_INTPEND               (1<<4)
-#define S3C44B0X_rIIC_LAST_RECEIV_BIT       (1<<0)
-#define S3C44B0X_rIIC_INTERRUPT_ENABLE      (1<<5)
-#define S3C44B0_IIC_TIMEOUT 100
-
-int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-
-       int k, j, temp;
-       u32 rIICSTAT;
-
-       /*
-               send the device offset
-       */
-
-       rIICSTAT = 0xD0;
-       IICSTAT = rIICSTAT;
-
-       IICDS = chip;   /* this is a write operation... */
-
-       rIICSTAT |= (1<<5);
-       IICSTAT = rIICSTAT;
-
-       for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-               temp = IICCON;
-               if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-               break;
-               udelay(2000);
-       }
-       if (k==S3C44B0_IIC_TIMEOUT)
-               return -1;
-
-       /* wait and check ACK */
-       temp = IICSTAT;
-       if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
-               return -1;
-
-       IICDS = addr;
-       IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
-       /* wait and check ACK */
-       for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-               temp = IICCON;
-               if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-               break;
-               udelay(2000);
-       }
-       if (k==S3C44B0_IIC_TIMEOUT)
-               return -1;
-
-       temp = IICSTAT;
-       if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
-               return -1;
-
-       /*
-               now we can start with the read operation...
-       */
-
-       IICDS = chip | 0x01;    /* this is a read operation... */
-
-       rIICSTAT = 0x90; /*master recv*/
-       rIICSTAT |= (1<<5);
-       IICSTAT = rIICSTAT;
-
-       IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
-       /* wait and check ACK */
-       for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-               temp = IICCON;
-               if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-               break;
-               udelay(2000);
-       }
-       if (k==S3C44B0_IIC_TIMEOUT)
-               return -1;
-
-       temp = IICSTAT;
-       if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
-               return -1;
-
-       for (j=0; j<len-1; j++) {
-
-       /*clear pending bit to resume */
-
-       temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-       IICCON = temp;
-
-       /* wait and check ACK */
-       for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-               temp = IICCON;
-               if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-               break;
-               udelay(2000);
-       }
-       if (k==S3C44B0_IIC_TIMEOUT)
-               return -1;
-
-
-               buffer[j] = IICDS; /*save readed data*/
-
-    } /*end for(j)*/
-
-       /*
-               reading the last data
-               unset ACK generation
-       */
-       temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7));
-       IICCON = temp;
-
-       /* wait but NOT check ACK */
-       for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-               temp = IICCON;
-               if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-               break;
-               udelay(2000);
-       }
-       if (k==S3C44B0_IIC_TIMEOUT)
-               return -1;
-
-       buffer[j] = IICDS; /*save readed data*/
-
-       rIICSTAT = 0x90; /*master recv*/
-
-       /* Write operation Terminate sending STOP */
-       IICSTAT = rIICSTAT;
-       /*Clear Int Pending Bit to RESUME*/
-       temp = IICCON;
-       IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
-
-       IICCON = IICCON | (1<<7);       /*restore ACK generation*/
-
-       return 0;
-}
-
-int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-{
-       int j, k;
-       u32 rIICSTAT, temp;
-
-
-       /*
-               send the device offset
-       */
-
-       rIICSTAT = 0xD0;
-       IICSTAT = rIICSTAT;
-
-       IICDS = chip;   /* this is a write operation... */
-
-       rIICSTAT |= (1<<5);
-       IICSTAT = rIICSTAT;
-
-       IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
-       /* wait and check ACK */
-       for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-               temp = IICCON;
-               if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-               break;
-               udelay(2000);
-       }
-       if (k==S3C44B0_IIC_TIMEOUT)
-               return -1;
-
-       temp = IICSTAT;
-       if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
-               return -1;
-
-       IICDS = addr;
-       IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-
-       /* wait and check ACK */
-       for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-               temp = IICCON;
-               if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-               break;
-               udelay(2000);
-       }
-       if (k==S3C44B0_IIC_TIMEOUT)
-         return -1;
-
-       temp = IICSTAT;
-       if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT )
-               return -1;
-
-       /*
-               now we can start with the read write operation
-       */
-       for (j=0; j<len; j++) {
-
-               IICDS = buffer[j]; /*prerare data to write*/
-
-               /*clear pending bit to resume*/
-
-               temp = IICCON & ~(S3C44B0X_rIIC_INTPEND);
-               IICCON = temp;
-
-               /* wait but NOT check ACK */
-               for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) {
-                       temp = IICCON;
-                       if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND)
-                       break;
-
-                       udelay(2000);
-               }
-
-               if (k==S3C44B0_IIC_TIMEOUT)
-                       return -1;
-
-       } /* end for(j) */
-
-       /* sending stop to terminate */
-       rIICSTAT = 0xD0;  /*master send*/
-       IICSTAT = rIICSTAT;
-       /*Clear Int Pending Bit to RESUME*/
-       temp = IICCON;
-       IICCON = temp & (~S3C44B0X_rIIC_INTPEND);
-
-       return 0;
-}
index 9bab71a..39240d9 100644 (file)
@@ -568,9 +568,14 @@ static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 static void cpsw_slave_update_link(struct cpsw_slave *slave,
                                   struct cpsw_priv *priv, int *link)
 {
-       struct phy_device *phy = priv->phydev;
+       struct phy_device *phy;
        u32 mac_control = 0;
 
+       phy = priv->phydev;
+
+       if (!phy)
+               return;
+
        phy_startup(phy);
        *link = phy->link;
 
@@ -947,6 +952,9 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave)
                        dev,
                        slave->data->phy_if);
 
+       if (!phydev)
+               return -1;
+
        phydev->supported &= supported;
        phydev->advertising = phydev->supported;
 
index f054470..11b3d03 100644 (file)
@@ -13,6 +13,8 @@ COBJS-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
 COBJS-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
 COBJS-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 COBJS-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
+COBJS-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
+COBJS-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c
new file mode 100644 (file)
index 0000000..36e9024
--- /dev/null
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <power/tps65217.h>
+
+/**
+ * tps65217_reg_read() - Generic function that can read a TPS65217 register
+ * @src_reg:            Source register address
+ * @src_val:            Address of destination variable
+ * @return:             0 for success, not 0 on failure.
+ */
+int tps65217_reg_read(uchar src_reg, uchar *src_val)
+{
+       return i2c_read(TPS65217_CHIP_PM, src_reg, 1, src_val, 1);
+}
+
+/**
+ *  tps65217_reg_write() - Generic function that can write a TPS65217 PMIC
+ *                        register or bit field regardless of protection
+ *                        level.
+ *
+ *  @prot_level:          Register password protection.  Use
+ *                        TPS65217_PROT_LEVEL_NONE,
+ *                        TPS65217_PROT_LEVEL_1 or TPS65217_PROT_LEVEL_2
+ *  @dest_reg:            Register address to write.
+ *  @dest_val:            Value to write.
+ *  @mask:                Bit mask (8 bits) to be applied.  Function will only
+ *                        change bits that are set in the bit mask.
+ *
+ *  @return:              0 for success, not 0 on failure, as per the i2c API
+ */
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+                      uchar mask)
+{
+       uchar read_val;
+       uchar xor_reg;
+       int ret;
+
+       /*
+        * If we are affecting only a bit field, read dest_reg and apply the
+        * mask
+        */
+       if (mask != TPS65217_MASK_ALL_BITS) {
+               ret = i2c_read(TPS65217_CHIP_PM, dest_reg, 1, &read_val, 1);
+               if (ret)
+                       return ret;
+               read_val &= (~mask);
+               read_val |= (dest_val & mask);
+               dest_val = read_val;
+       }
+
+       if (prot_level > 0) {
+               xor_reg = dest_reg ^ TPS65217_PASSWORD_UNLOCK;
+               ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+                               &xor_reg, 1);
+               if (ret)
+                       return ret;
+       }
+
+       ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
+       if (ret)
+               return ret;
+
+       if (prot_level == TPS65217_PROT_LEVEL_2) {
+               ret = i2c_write(TPS65217_CHIP_PM, TPS65217_PASSWORD, 1,
+                               &xor_reg, 1);
+               if (ret)
+                       return ret;
+
+               ret = i2c_write(TPS65217_CHIP_PM, dest_reg, 1, &dest_val, 1);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
+/**
+ * tps65217_voltage_update() - Function to change a voltage level, as this
+ *                            is a multi-step process.
+ * @dc_cntrl_reg:             DC voltage control register to change.
+ * @volt_sel:                 New value for the voltage register
+ * @return:                   0 for success, not 0 on failure.
+ */
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
+{
+       if ((dc_cntrl_reg != TPS65217_DEFDCDC1) &&
+           (dc_cntrl_reg != TPS65217_DEFDCDC2) &&
+           (dc_cntrl_reg != TPS65217_DEFDCDC3))
+               return 1;
+
+       /* set voltage level */
+       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
+                              TPS65217_MASK_ALL_BITS))
+               return 1;
+
+       /* set GO bit to initiate voltage transition */
+       if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFSLEW,
+                              TPS65217_DCDC_GO, TPS65217_DCDC_GO))
+               return 1;
+
+       return 0;
+}
diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c
new file mode 100644 (file)
index 0000000..7ee1160
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <power/tps65910.h>
+
+/*
+ * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
+ *                             interface.
+ * @return:                   0 on success, not 0 on failure
+ */
+int tps65910_set_i2c_control(void)
+{
+       int ret;
+       uchar buf;
+
+       /* VDD1/2 voltage selection register access by control i/f */
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+                      &buf, 1);
+
+       if (ret)
+               return ret;
+
+       buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
+
+       return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
+                        &buf, 1);
+}
+
+/*
+ * tps65910_voltage_update() - Voltage switching for MPU frequency switching.
+ * @module:                   mpu - 0, core - 1
+ * @vddx_op_vol_sel:          vdd voltage to set
+ * @return:                   0 on success, not 0 on failure
+ */
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
+{
+       uchar buf;
+       unsigned int reg_offset;
+       int ret;
+
+       if (module == MPU)
+               reg_offset = TPS65910_VDD1_OP_REG;
+       else
+               reg_offset = TPS65910_VDD2_OP_REG;
+
+       /* Select VDDx OP   */
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       buf &= ~TPS65910_OP_REG_CMD_MASK;
+
+       ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       /* Configure VDDx OP  Voltage */
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       buf &= ~TPS65910_OP_REG_SEL_MASK;
+       buf |= vddx_op_vol_sel;
+
+       ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
+       if (ret)
+               return ret;
+
+       if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
+               return 1;
+
+       return 0;
+}
index b477c23..dcc0632 100644 (file)
@@ -53,7 +53,6 @@ COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
 COBJS-$(CONFIG_RTC_RV3029) += rv3029.o
 COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
 COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
-COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o
 COBJS-$(CONFIG_RTC_X1205) += x1205.o
 
 COBJS  := $(sort $(COBJS-y))
diff --git a/drivers/rtc/s3c44b0_rtc.c b/drivers/rtc/s3c44b0_rtc.c
deleted file mode 100644 (file)
index de7898c..0000000
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-/*
- * S3C44B0 CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/hardware.h>
-#include <rtc.h>
-
-int rtc_get (struct rtc_time* tm)
-{
-       RTCCON |= 1;
-       tm->tm_year  = bcd2bin(BCDYEAR);
-       tm->tm_mon   = bcd2bin(BCDMON);
-       tm->tm_wday   = bcd2bin(BCDDATE);
-       tm->tm_mday   = bcd2bin(BCDDAY);
-       tm->tm_hour  = bcd2bin(BCDHOUR);
-       tm->tm_min  = bcd2bin(BCDMIN);
-       tm->tm_sec  = bcd2bin(BCDSEC);
-
-       if (tm->tm_sec==0) {
-               /* we have to re-read the rtc data because of the "one second deviation" problem */
-               /* see RTC datasheet for more info about it */
-               tm->tm_year  = bcd2bin(BCDYEAR);
-               tm->tm_mon   = bcd2bin(BCDMON);
-               tm->tm_mday   = bcd2bin(BCDDAY);
-               tm->tm_wday   = bcd2bin(BCDDATE);
-               tm->tm_hour  = bcd2bin(BCDHOUR);
-               tm->tm_min  = bcd2bin(BCDMIN);
-               tm->tm_sec  = bcd2bin(BCDSEC);
-       }
-
-       RTCCON &= ~1;
-
-       if(tm->tm_year >= 70)
-               tm->tm_year += 1900;
-       else
-               tm->tm_year += 2000;
-
-       return 0;
-}
-
-int rtc_set (struct rtc_time* tm)
-{
-       if(tm->tm_year < 2000)
-               tm->tm_year -= 1900;
-       else
-               tm->tm_year -= 2000;
-
-       RTCCON |= 1;
-       BCDYEAR = bin2bcd(tm->tm_year);
-       BCDMON = bin2bcd(tm->tm_mon);
-       BCDDAY = bin2bcd(tm->tm_mday);
-       BCDDATE = bin2bcd(tm->tm_wday);
-       BCDHOUR = bin2bcd(tm->tm_hour);
-       BCDMIN = bin2bcd(tm->tm_min);
-       BCDSEC = bin2bcd(tm->tm_sec);
-       RTCCON &= 1;
-
-       return 0;
-}
-
-void rtc_reset (void)
-{
-       RTCCON |= 1;
-       BCDYEAR = 0;
-       BCDMON = 0;
-       BCDDAY = 0;
-       BCDDATE = 0;
-       BCDHOUR = 0;
-       BCDMIN = 0;
-       BCDSEC = 0;
-       RTCCON &= 1;
-}
index 4c45bfa..e1fd7a5 100644 (file)
@@ -31,7 +31,6 @@ COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
 COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
 COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
-COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
 COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
 COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
index 35dc61e..df2b84a 100644 (file)
@@ -156,7 +156,6 @@ serial_initfunc(lh7a40x_serial_initialize);
 serial_initfunc(max3100_serial_initialize);
 serial_initfunc(mxc_serial_initialize);
 serial_initfunc(pl01x_serial_initialize);
-serial_initfunc(s3c44b0_serial_initialize);
 serial_initfunc(sa1100_serial_initialize);
 serial_initfunc(sh_serial_initialize);
 serial_initfunc(arm_dcc_initialize);
@@ -250,7 +249,6 @@ void serial_initialize(void)
        max3100_serial_initialize();
        mxc_serial_initialize();
        pl01x_serial_initialize();
-       s3c44b0_serial_initialize();
        sa1100_serial_initialize();
        sh_serial_initialize();
        arm_dcc_initialize();
diff --git a/drivers/serial/serial_s3c44b0.c b/drivers/serial/serial_s3c44b0.c
deleted file mode 100644 (file)
index 2a07498..0000000
+++ /dev/null
@@ -1,216 +0,0 @@
-pyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * ght 2002-2004
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* flush serial input queue. returns 0 on success or negative error
- * number otherwise
- */
-static int serial_flush_input(void)
-{
-       volatile u32 tmp;
-
-       /* keep on reading as long as the receiver is not empty */
-       while(UTRSTAT0&0x01) {
-               tmp = REGB(URXH0);
-       }
-
-       return 0;
-}
-
-
-/* flush output queue. returns 0 on success or negative error number
- * otherwise
- */
-static int serial_flush_output(void)
-{
-       /* wait until the transmitter is no longer busy */
-       while(!(UTRSTAT0 & 0x02)) {
-       }
-
-       return 0;
-}
-
-
-static void s3c44b0_serial_setbrg(void)
-{
-       u32 divisor = 0;
-
-       /* get correct divisor */
-       switch(gd->baudrate) {
-
-       case 1200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-               divisor = 3124;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-               divisor = 3905;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-               break;
-
-       case 9600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-               divisor = 390;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-               divisor = 487;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-               break;
-
-       case 19200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-               divisor = 194;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-               divisor = 243;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif
-               break;
-
-       case 38400:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-               divisor = 97;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-               divisor = 121;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
-
-       case 57600:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-               divisor = 64;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-               divisor = 80;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
-
-       case 115200:
-#if CONFIG_S3C44B0_CLOCK_SPEED==66
-               divisor = 32;
-#elif CONFIG_S3C44B0_CLOCK_SPEED==75
-               divisor = 40;
-#else
-# error CONFIG_S3C44B0_CLOCK_SPEED undefined
-#endif /* break; */
-       }
-
-       serial_flush_output();
-       serial_flush_input();
-       UFCON0 = 0x0;
-       ULCON0 = 0x03;
-       UCON0 = 0x05;
-       UBRDIV0 = divisor;
-
-       UFCON1 = 0x0;
-       ULCON1 = 0x03;
-       UCON1 = 0x05;
-       UBRDIV1 = divisor;
-
-       for(divisor=0; divisor<100; divisor++) {
-               /* NOP */
-       }
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-static int s3c44b0_serial_init(void)
-{
-       serial_setbrg ();
-
-       return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-static void s3c44b0_serial_putc(const char c)
-{
-       /* wait for room in the transmit FIFO */
-       while(!(UTRSTAT0 & 0x02));
-
-       UTXH0 = (unsigned char)c;
-
-       /*
-               to be polite with serial console add a line feed
-               to the carriage return character
-       */
-       if (c=='\n')
-               serial_putc('\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int s3c44b0_serial_tstc(void)
-{
-       return (UTRSTAT0 & 0x01);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int s3c44b0_serial_getc(void)
-{
-       int rv;
-
-       for(;;) {
-               rv = s3c44b0_serial_tstc();
-
-               if(rv > 0)
-                       return URXH0;
-       }
-}
-
-static struct serial_device s3c44b0_serial_drv = {
-       .name   = "s3c44b0_serial",
-       .start  = s3c44b0_serial_init,
-       .stop   = NULL,
-       .setbrg = s3c44b0_serial_setbrg,
-       .putc   = s3c44b0_serial_putc,
-       .puts   = default_serial_puts,
-       .getc   = s3c44b0_serial_getc,
-       .tstc   = s3c44b0_serial_tstc,
-};
-
-void s3c44b0_serial_initialize(void)
-{
-       serial_register(&s3c44b0_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-       return &s3c44b0_serial_drv;
-}
index 3de30fc..cdf689f 100644 (file)
        "run mmcboot;" \
        "setenv mmcdev 1; " \
        "setenv bootpart 1:2; " \
+       "setenv mmcroot /dev/mmcblk1p2 ro; " \
        "run mmcboot;" \
        "run nandboot;"
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+#define CONFIG_POWER_TPS65910
+
 /* SPL */
 #ifndef CONFIG_NOR_BOOT
+#define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 
 /* CPSW support */
index 4fbe768..7b120de 100644 (file)
 
 #define CONFIG_DRA7XX
 
-#define CONFIG_ENV_IS_NOWHERE          /* For now. */
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV         1       /* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET              0xE0000
+#define CONFIG_ENV_OFFSET_REDUND       (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_CMD_SAVEENV
 
 #define CONSOLEDEV                     "ttyO0"
 #define CONFIG_CONS_INDEX              1
index ccc7bd0..b8e672f 100644 (file)
@@ -83,7 +83,7 @@
  * Size of malloc() pool
  */
 
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 520*1024)
+#define CONFIG_SYS_MALLOC_LEN          (4 * 1024 * 1024)
 
 /*
  * sdram
index e2b4de7..2fff0be 100644 (file)
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_BOARD_INIT
 /*
  * Place the image at the start of the ROM defined image space.
  * We limit our size to the ROM-defined downloaded image area, and use the
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
new file mode 100644 (file)
index 0000000..297c4cb
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65217a
+ */
+
+#ifndef __POWER_TPS65217_H__
+#define __POWER_TPS65217_H__
+
+/* I2C chip address */
+#define TPS65217_CHIP_PM                       0x24
+
+/* Registers */
+enum {
+       TPS65217_CHIPID                         = 0x00,
+       TPS65217_POWER_PATH,
+       TPS65217_INTERRUPT,
+       TPS65217_CHGCONFIG0,
+       TPS65217_CHGCONFIG1,
+       TPS65217_CHGCONFIG2,
+       TPS65217_CHGCONFIG3,
+       TPS65217_WLEDCTRL1,
+       TPS65217_WLEDCTRL2,
+       TPS65217_MUXCTRL,
+       TPS65217_STATUS,
+       TPS65217_PASSWORD,
+       TPS65217_PGOOD,
+       TPS65217_DEFPG,
+       TPS65217_DEFDCDC1,
+       TPS65217_DEFDCDC2,
+       TPS65217_DEFDCDC3,
+       TPS65217_DEFSLEW,
+       TPS65217_DEFLDO1,
+       TPS65217_DEFLDO2,
+       TPS65217_DEFLS1,
+       TPS65217_DEFLS2,
+       TPS65217_ENABLE,
+       TPS65217_DEFUVLO,
+       TPS65217_SEQ1,
+       TPS65217_SEQ2,
+       TPS65217_SEQ3,
+       TPS65217_SEQ4,
+       TPS65217_SEQ5,
+       TPS65217_SEQ6,
+       TPS65217_PMIC_NUM_OF_REGS,
+};
+
+#define TPS65217_PROT_LEVEL_NONE               0x00
+#define TPS65217_PROT_LEVEL_1                  0x01
+#define TPS65217_PROT_LEVEL_2                  0x02
+
+#define TPS65217_PASSWORD_LOCK_FOR_WRITE       0x00
+#define TPS65217_PASSWORD_UNLOCK               0x7D
+
+#define TPS65217_DCDC_GO                       0x80
+
+#define TPS65217_MASK_ALL_BITS                 0xFF
+
+#define TPS65217_USB_INPUT_CUR_LIMIT_MASK      0x03
+#define TPS65217_USB_INPUT_CUR_LIMIT_100MA     0x00
+#define TPS65217_USB_INPUT_CUR_LIMIT_500MA     0x01
+#define TPS65217_USB_INPUT_CUR_LIMIT_1300MA    0x02
+#define TPS65217_USB_INPUT_CUR_LIMIT_1800MA    0x03
+
+#define TPS65217_DCDC_VOLT_SEL_1125MV          0x09
+#define TPS65217_DCDC_VOLT_SEL_1275MV          0x0F
+#define TPS65217_DCDC_VOLT_SEL_1325MV          0x11
+
+#define TPS65217_LDO_MASK                      0x1F
+#define TPS65217_LDO_VOLTAGE_OUT_1_8           0x06
+#define TPS65217_LDO_VOLTAGE_OUT_3_3           0x1F
+
+#define TPS65217_PWR_SRC_USB_BITMASK           0x4
+#define TPS65217_PWR_SRC_AC_BITMASK            0x8
+
+int tps65217_reg_read(uchar src_reg, uchar *src_val);
+int tps65217_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
+                      uchar mask);
+int tps65217_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
+#endif /* __POWER_TPS65217_H__ */
diff --git a/include/power/tps65910.h b/include/power/tps65910.h
new file mode 100644 (file)
index 0000000..ca84301
--- /dev/null
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011-2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * For more details, please see the TRM at http://www.ti.com/product/tps65910
+ */
+#ifndef __POWER_TPS65910_H__
+#define __POWER_TPS65910_H__
+
+#define MPU     0
+#define CORE    1
+
+#define TPS65910_SR_I2C_ADDR                           0x12
+#define TPS65910_CTRL_I2C_ADDR                         0x2D
+
+/* PMIC Register offsets */
+enum {
+       TPS65910_VDD1_REG                               = 0x21,
+       TPS65910_VDD1_OP_REG                            = 0x22,
+       TPS65910_VDD2_REG                               = 0x24,
+       TPS65910_VDD2_OP_REG                            = 0x25,
+       TPS65910_DEVCTRL_REG                            = 0x3F,
+};
+
+/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
+#define TPS65910_VGAIN_SEL_MASK                                (0x3 << 6)
+#define TPS65910_ILMAX_MASK                            (0x1 << 5)
+#define TPS65910_TSTEP_MASK                            (0x7 << 2)
+#define TPS65910_ST_MASK                               (0x3)
+
+#define TPS65910_REG_VGAIN_SEL_X1                      (0x0 << 6)
+#define TPS65910_REG_VGAIN_SEL_X1_0                    (0x1 << 6)
+#define TPS65910_REG_VGAIN_SEL_X3                      (0x2 << 6)
+#define TPS65910_REG_VGAIN_SEL_X4                      (0x3 << 6)
+
+#define TPS65910_REG_ILMAX_1_0_A                       (0x0 << 5)
+#define TPS65910_REG_ILMAX_1_5_A                       (0x1 << 5)
+
+#define TPS65910_REG_TSTEP_                            (0x0 << 2)
+#define TPS65910_REG_TSTEP_12_5                                (0x1 << 2)
+#define TPS65910_REG_TSTEP_9_4                         (0x2 << 2)
+#define TPS65910_REG_TSTEP_7_5                         (0x3 << 2)
+#define TPS65910_REG_TSTEP_6_25                                (0x4 << 2)
+#define TPS65910_REG_TSTEP_4_7                         (0x5 << 2)
+#define TPS65910_REG_TSTEP_3_12                                (0x6 << 2)
+#define TPS65910_REG_TSTEP_2_5                         (0x7 << 2)
+
+#define TPS65910_REG_ST_OFF                            (0x0)
+#define TPS65910_REG_ST_ON_HI_POW                      (0x1)
+#define TPS65910_REG_ST_OFF_1                          (0x2)
+#define TPS65910_REG_ST_ON_LOW_POW                     (0x3)
+
+
+/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
+#define TPS65910_OP_REG_SEL                            (0x7F)
+
+#define TPS65910_OP_REG_CMD_MASK                       (0x1 << 7)
+#define TPS65910_OP_REG_CMD_OP                         (0x0 << 7)
+#define TPS65910_OP_REG_CMD_SR                         (0x1 << 7)
+
+#define TPS65910_OP_REG_SEL_MASK                       (0x7F)
+#define TPS65910_OP_REG_SEL_0_9_5                      (0x1F)  /* 0.9500 V */
+#define TPS65910_OP_REG_SEL_1_1_3                      (0x2E)  /* 1.1375 V */
+#define TPS65910_OP_REG_SEL_1_2_0                      (0x33)  /* 1.2000 V */
+#define TPS65910_OP_REG_SEL_1_2_6                      (0x38)  /* 1.2625 V */
+#define TPS65910_OP_REG_SEL_1_3_2_5                    (0x3D)  /* 1.3250 V */
+
+/* Device control register . (DEVCTRL_REG) */
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK           (0x1 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C     (0x0 << 4)
+#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C    (0x1 << 4)
+
+int tps65910_set_i2c_control(void);
+int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
+#endif /* __POWER_TPS65910_H__ */
index 174d0a7..b366ac2 100644 (file)
@@ -87,7 +87,8 @@ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o
 LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o
 LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o
 LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o
-LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o
+LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \
+       drivers/power/pmic/libpmic.o
 LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o
 LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o
 LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o