config SYS_L2CACHE_OFF
bool "Do not use L2 cache"
+config ARCH_MXS
+ bool "Freescale i.MX23 & i.MX28"
+ select CPU_ARM926EJS
+
+config ARCH_MX6
+ bool "Freescale MX6"
+ select CPU_V7
+
+config ARCH_MX5
+ bool "Freescale MX5"
+ select CPU_V7
+
config SOC_AM335X
bool
select CPU_V7
config TARGET_TX6
bool "Support tx6"
- select SOC_MX6
config TARGET_ZMX25
bool "Support zmx25"
select CPU_V7
select SUPPORT_SPL
-config ARCH_MX6
- bool "Freescale MX6"
- select CPU_V7
-
-config ARCH_MX5
- bool "Freescale MX5"
- select CPU_V7
-
config TARGET_M53EVK
bool "Support m53evk"
select CPU_V7
source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/cpu/arm926ejs/mxs/Kconfig"
+
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
--- /dev/null
+if ARCH_MXS
+
+config SOC_MX23
+ bool
+
+config SOC_MX28
+ bool
+
+endif
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_SOC_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_ARCH_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
-obj-$(CONFIG_SOC_MX6) += mx6/
+obj-$(CONFIG_ARCH_MX6) += mx6/
obj-$(CONFIG_OMAP34XX) += omap3/
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
}
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
#if defined(CONFIG_SOC_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
#else
u32 cpurev;
__maybe_unused u32 max_freq;
-#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_ARCH_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, minc, maxc, ret;
#endif
cpurev = get_cpu_rev();
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
printf("CPU: Freescale i.MX%s rev%d.%d",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif
-#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_ARCH_MX6) && defined(CONFIG_IMX6_THERMAL)
puts("CPU: ");
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
{
#if defined(CONFIG_CMD_SATA)
sata_stop();
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
disable_sata_clock();
#endif
#endif
#include <asm/spl.h>
#include <spl.h>
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
{
static inline int gpt_has_clk_source_osc(void)
{
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
(soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
-#elif defined(CONFIG_SOC_MX6)
+#elif defined(CONFIG_ARCH_MX6)
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
#define __PAD_CTRL_VALID (1 << 17)
#define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT)
-#ifdef CONFIG_SOC_MX6
+#ifdef CONFIG_ARCH_MX6
#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16)
mxs_reg_32(hw_apbh_version);
};
-#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))
+#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_ARCH_MX6))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0); /* 0x000 */
mxs_reg_32(hw_apbh_ctrl1); /* 0x010 */
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
-#elif defined(CONFIG_SOC_MX6)
+#elif defined(CONFIG_ARCH_MX6)
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else
#include <linux/kbuild.h>
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) \
- || defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ || defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
#include <asm/arch/imx-regs.h>
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#include <asm/arch/crm_regs.h>
#endif
DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_MX6UL_14X14_EVK=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SOC_MX6UL"
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_256M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_128M,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_40X1=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_41X0=y
CONFIG_TX28_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="TX28_S,SYS_SDRAM_SIZE=SZ_64M"
CONFIG_ARM=y
+CONFIG_ARCH_MXS=y
CONFIG_TARGET_TX28=y
CONFIG_TARGET_TX28_41X0=y
CONFIG_TX28_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX0=y
CONFIG_TX51_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX0=y
CONFIG_TX51_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX1_2=y
CONFIG_TX51_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_CPU_CLK=800"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX51=y
CONFIG_TARGET_TX51_8XX1_2=y
CONFIG_TX51_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_2G"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_1232=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=SZ_2G"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_1232=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_SIZE=SZ_2G"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_1232=y
CONFIG_TX53_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X030=y
CONFIG_TX53_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X030=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X030=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X130=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X130=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X130=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X131=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X131=y
CONFIG_TX53_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
CONFIG_TARGET_TX53=y
CONFIG_TARGET_TX53_X131=y
CONFIG_TX53_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=4096,SECURE_BOOT,TX6_REV=0x2"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1020=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_1033=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_10X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6Q_11X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=16"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8034=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6S_8035=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8011=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_NAND_BLOCKS=2048"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8012=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8033=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_80X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF,SYS_SDRAM_BUS_WIDTH=32"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_8111=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT_MFG=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT_NOENV=y
CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT,SYS_LVDS_IF"
CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
CONFIG_TARGET_TX6=y
CONFIG_TARGET_TX6U_81X0=y
CONFIG_TX6_UBOOT=y
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
return 1;
#endif
config APBH_DMA
bool "Freescale MXS and i.MX6 APBH DMA support"
- depends on SOC_MX28 || SOC_MX6
+ depends on ARCH_MXS || ARCH_MX6
config APBH_DMA_BURST
bool "Enable DMA burst mode"
#if defined(CONFIG_SOC_MX23)
uint32_t *setreg = &apbh_regs->hw_apbh_ctrl0_set;
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))
+#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_ARCH_MX6))
uint32_t *setreg = &apbh_regs->hw_apbh_channel_ctrl_set;
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
- defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
[3] = GPIO4_BASE_ADDR,
#endif
-#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
[4] = GPIO5_BASE_ADDR,
#ifndef CONFIG_SOX_MX6UL
[5] = GPIO6_BASE_ADDR,
#endif
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
#ifndef CONFIG_SOC_MX6UL
[6] = GPIO7_BASE_ADDR,
#endif
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
- defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
-#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
#endif
};
{ "gpio_mxc", &mxc_plat[1] },
{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
- defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+ defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ "gpio_mxc", &mxc_plat[3] },
#endif
-#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ "gpio_mxc", &mxc_plat[4] },
{ "gpio_mxc", &mxc_plat[5] },
#endif
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6)
{ "gpio_mxc", &mxc_plat[6] },
#endif
};
config MXC_OCOTP
bool "Freescale OCOTP support"
- depends on SOC_MX5 || SOC_MX6
+ depends on ARCH_MX5 || ARCH_MX6
config MXS_OCOTP
bool "Freescale OCOTP support"
- depends on SOC_MXS
+ depends on ARCH_MXS
config PCA9551_LED
bool "Enable PCA9551 LED driver"
config FSL_USDHC
bool "Support USDHC"
- depends on FSL_ESDHC && SOC_MX6
+ depends on FSL_ESDHC && ARCH_MX6
config MXS_MMC
bool "i.MXS MMC/SDHC controller"
- depends on SOC_MXS || SOC_MX6
+ depends on ARCH_MXS || ARCH_MX6
select GENERIC_MMC
select BOUNCE_BUFFER
config NAND_MXS_NO_BBM_SWAP
bool "disable bad block mark swapping"
- depends on NAND_MXS && SOC_MX6
+ depends on NAND_MXS && ARCH_MX6
select SYS_NAND_USE_FLASH_BBT
endif
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
#define UCMD_RESET (1 << 1) /* controller reset */
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
static const unsigned phy_bases[] = {
USB_PHY0_BASE_ADDR,
USB_PHY1_BASE_ADDR,
static void usb_oc_config(int index)
{
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
USB_OTHERREGS_OFFSET);
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
#elif defined(CONFIG_SOC_MX7)
setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
enum usb_init_type type;
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
u32 controller_spacing = 0x200;
#elif defined(CONFIG_SOC_MX7)
u32 controller_spacing = 0x10000;
usb_power_config(index);
usb_oc_config(index);
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
usb_internal_phy_clock_gate(index, 1);
usb_phy_enable(index, ehci);
#endif
config HW_WATCHDOG
bool "Generic SoC specific watchdog support"
- depends on !SOC_MX6
+ depends on !ARCH_MX6
config IMX_WATCHDOG
bool "Freescale i.MX watchdog support"
- depends on SOC_MX31 || SOC_MX35 || SOC_MX5 || SOC_MX6 || SOC_VF610 || SOC_LS102XA
+ depends on SOC_MX31 || SOC_MX35 || ARCH_MX5 || ARCH_MX6 || SOC_VF610 || SOC_LS102XA
#define CONFIG_JRSTARTR_JR0 0x00000001
struct jr_regs {
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
u32 irba_l;
u32 irba_h;
#else
u32 irsa;
u32 rsvd3;
u32 irja;
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
u32 orba_l;
u32 orba_h;
#else
* related information
*/
struct sg_entry {
-#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_ARCH_MX6)
uint32_t addr_lo; /* Memory Address - lo */
uint16_t addr_hi; /* Memory Address of start of buffer - hi */
uint16_t reserved_zero;
#define SG_ENTRY_OFFSET_SHIFT 0
};
-#ifdef CONFIG_SOC_MX6
+#ifdef CONFIG_ARCH_MX6
/* CAAM Job Ring 0 Registers */
/* Secure Memory Partition Owner register */
#define SMCSJR_PO (3 << 6)