ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0
authorNishanth Menon <nm@ti.com>
Thu, 13 Aug 2015 14:51:00 +0000 (09:51 -0500)
committerLothar Waßmann <LW@KARO-electronics.de>
Thu, 10 Sep 2015 09:29:49 +0000 (11:29 +0200)
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.

Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.

NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/omap_common.h
board/ti/dra7xx/evm.c

index d01ce88..fffe0ee 100644 (file)
@@ -11,6 +11,7 @@
  */
 
 #include <asm/omap_common.h>
+#include <asm/io.h>
 
 struct prcm_regs const omap5_es1_prcm = {
        /* cm1.ckgen */
@@ -379,6 +380,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_phy_power_usb                  = 0x4A002370,
        .control_phy_power_sata                 = 0x4A002374,
        .ctrl_core_sma_sw_0                     = 0x4A0023FC,
+       .ctrl_core_sma_sw_1                     = 0x4A002534,
        .control_core_mac_id_0_lo               = 0x4A002514,
        .control_core_mac_id_0_hi               = 0x4A002518,
        .control_core_mac_id_1_lo               = 0x4A00251C,
@@ -994,3 +996,10 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_l3main1_tptc1_clkctrl               = 0x4a008778,
        .cm_l3main1_tptc2_clkctrl               = 0x4a008780,
 };
+
+void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
+{
+       u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 :
+               (*ctrl)->ctrl_core_sma_sw_0;
+       clrsetbits_le32(reg, clear_bits, set_bits);
+}
index 2f53d85..4cd0a3c 100644 (file)
 #define ISOLATE_IO                     1
 #define DEISOLATE_IO                   0
 
+/* CTRL_CORE_SMA_SW_1 */
+#define RGMII2_ID_MODE_N_MASK          (1 << 26)
+#define RGMII1_ID_MODE_N_MASK          (1 << 25)
+
 /* PRM_IO_PMCTRL */
 #define PMCTRL_ISOCLK_OVERRIDE_SHIFT   0
 #define PMCTRL_ISOCLK_OVERRIDE_MASK    (1 << 0)
index ddf5c7a..c329641 100644 (file)
@@ -235,6 +235,8 @@ struct ctrl_ioregs {
        u32 ctrl_ddr_ctrl_ext_0;
 };
 
+void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
+
 #endif /* __ASSEMBLY__ */
 
 /* Boot parameters */
index 000a533..2461667 100644 (file)
@@ -466,6 +466,7 @@ struct omap_sys_ctrl_regs {
        u32 control_padconf_wkup_base;
        u32 iodelay_config_base;
        u32 ctrl_core_sma_sw_0;
+       u32 ctrl_core_sma_sw_1;
 };
 
 struct dpll_params {
index 9603f10..6e3c855 100644 (file)
@@ -104,6 +104,9 @@ void recalibrate_iodelay(void)
                npads = ARRAY_SIZE(dra74x_core_padconf_array);
                iodelay = dra742_es2_0_iodelay_cfg_array;
                niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
+               /* Setup port1 and port2 for rgmii with 'no-id' mode */
+               clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
+                                     RGMII1_ID_MODE_N_MASK);
                break;
        }
        __recalibrate_iodelay(pads, npads, iodelay, niodelays);