EXYNOS5: Add pinmux support for SPI

This patch adds pinmux support for SPI channels

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index d99daa06e1fd854500a11e1d85032a40767f6f6c..f02f441a8b7dd563a72b0fe79adba047748dc151 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
                s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
                s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
        }
+
        return 0;
 }
 
@@ -240,6 +241,49 @@ static void exynos5_i2s_config(int peripheral)
                s5p_gpio_cfg_pin(&gpio1->b0, i, GPIO_FUNC(0x02));
 }
 
+void exynos5_spi_config(int peripheral)
+{
+       int cfg = 0, pin = 0, i;
+       struct s5p_gpio_bank *bank = NULL;
+       struct exynos5_gpio_part1 *gpio1 =
+               (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+       struct exynos5_gpio_part2 *gpio2 =
+               (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2();
+
+       switch (peripheral) {
+       case PERIPH_ID_SPI0:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI1:
+               bank = &gpio1->a2;
+               cfg = GPIO_FUNC(0x2);
+               pin = 4;
+               break;
+       case PERIPH_ID_SPI2:
+               bank = &gpio1->b1;
+               cfg = GPIO_FUNC(0x5);
+               pin = 1;
+               break;
+       case PERIPH_ID_SPI3:
+               bank = &gpio2->f1;
+               cfg = GPIO_FUNC(0x2);
+               pin = 0;
+               break;
+       case PERIPH_ID_SPI4:
+               for (i = 0; i < 2; i++) {
+                       s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4));
+                       s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4));
+               }
+               break;
+       }
+       if (peripheral != PERIPH_ID_SPI4) {
+               for (i = pin; i < pin + 4; i++)
+                       s5p_gpio_cfg_pin(bank, i, cfg);
+       }
+}
+
 static int exynos5_pinmux_config(int peripheral, int flags)
 {
        switch (peripheral) {
@@ -270,6 +314,13 @@ static int exynos5_pinmux_config(int peripheral, int flags)
        case PERIPH_ID_I2S1:
                exynos5_i2s_config(peripheral);
                break;
+       case PERIPH_ID_SPI0:
+       case PERIPH_ID_SPI1:
+       case PERIPH_ID_SPI2:
+       case PERIPH_ID_SPI3:
+       case PERIPH_ID_SPI4:
+               exynos5_spi_config(peripheral);
+               break;
        default:
                debug("%s: invalid peripheral %d", __func__, peripheral);
                return -1;

diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 673f4c78f541b826b704a203426a38e8c504ec99..13abd2d703a58d7dacb42dd533aff3b4a6c0a8bf 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -45,6 +45,11 @@ enum periph_id {
        PERIPH_ID_SDMMC3,
        PERIPH_ID_SDMMC4,
        PERIPH_ID_SROMC,
+       PERIPH_ID_SPI0,
+       PERIPH_ID_SPI1,
+       PERIPH_ID_SPI2,
+       PERIPH_ID_SPI3,
+       PERIPH_ID_SPI4,
        PERIPH_ID_UART0,
        PERIPH_ID_UART1,
        PERIPH_ID_UART2,