From: Lothar Waßmann Date: Fri, 7 Jul 2017 14:03:47 +0000 (+0200) Subject: arm: mx6: add support for i.MX6ULL X-Git-Tag: KARO-TX6ULL-2017-07-07~1 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=80f0fd8a4e8990ad05261e9d36b6e7e1a4d97245 arm: mx6: add support for i.MX6ULL --- diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index bd8bbd0c3c..28fcaf782a 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -24,6 +24,9 @@ config SOC_MX6SX config SOC_MX6UL bool +config SOC_MX6ULL + bool + choice prompt "MX6 board select" optional diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 9080d11764..31db295bb4 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -71,7 +71,7 @@ void mx6sx_dram_iocfg(unsigned width, } #endif -#ifdef CONFIG_SOC_MX6UL +#if defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) void mx6ul_dram_iocfg(unsigned width, const struct mx6ul_iomux_ddr_regs *ddr, const struct mx6ul_iomux_grp_regs *grp) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index c7f9fffacb..ecc72e89c2 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -11,8 +11,10 @@ #define MXC_CPU_MX6SX 0x62 #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6UL 0x64 -#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ -#define MXC_CPU_MX6D 0x67 +#define MXC_CPU_MX6ULL 0x65 +#define MXC_CPU_MX6SOLO 0x66 /* dummy ID */ +#define MXC_CPU_MX6SLL 0x67 +#define MXC_CPU_MX6D 0x6A #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index acb1136372..a10fdc56d2 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -279,15 +279,18 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \ + is_cpu_type(MXC_CPU_MX6ULL)) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \ + is_cpu_type(MXC_CPU_MX6ULL)) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL) || \ + is_cpu_type(MXC_CPU_MX6ULL)) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) @@ -558,14 +561,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) #endif -#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) +#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL) #define MXC_CCM_CCGR2_CSI_OFFSET 2 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) #else #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) #endif -#if !defined(CONFIG_SOC_MX6SX) && !defined(CONFIG_SOC_MX6UL) +#if !defined(CONFIG_SOC_MX6SX) && !(defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL)) #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) #endif @@ -589,7 +594,8 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) -#if defined(CONFIG_SOC_MX6SX) || (CONFIG_SOC_MX6UL) +#if defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL) #define MXC_CCM_CCGR2_LCD_OFFSET 28 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) #define MXC_CCM_CCGR2_PXP_OFFSET 30 diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h index 65f28ad3c0..770327ccef 100644 --- a/arch/arm/include/asm/arch-mx6/hab.h +++ b/arch/arm/include/asm/arch-mx6/hab.h @@ -181,6 +181,7 @@ static inline void **hab_rvt_base(void) break; case MXC_CPU_MX6SX: case MXC_CPU_MX6UL: + case MXC_CPU_MX6ULL: base = 0x100UL; break; default: diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 49a124ea61..350a252f4b 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -11,7 +11,7 @@ #define ARCH_MXC -#ifdef CONFIG_SOC_MX6UL +#if defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) #define CONFIG_SYS_CACHELINE_SIZE 64 #else #define CONFIG_SYS_CACHELINE_SIZE 32 @@ -25,14 +25,15 @@ #define GPU_2D_ARB_END_ADDR 0x02203FFF #define OPENVG_ARB_BASE_ADDR 0x02204000 #define OPENVG_ARB_END_ADDR 0x02207FFF -#elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)) +#elif (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL)) #define CAAM_ARB_BASE_ADDR 0x00100000 #define CAAM_ARB_END_ADDR 0x00107FFF #define GPU_ARB_BASE_ADDR 0x01800000 #define GPU_ARB_END_ADDR 0x01803FFF #define APBH_DMA_ARB_BASE_ADDR 0x01804000 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF -#define M4_BOOTROM_BASE_ADDR 0x007F8000 +#define M4_BOOTROM_BASE_ADDR 0x007F8000 #else #define CAAM_ARB_BASE_ADDR 0x00100000 @@ -54,13 +55,15 @@ #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* GPV - PL301 configuration ports */ -#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)) +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || \ + defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)) #define GPV2_BASE_ADDR 0x00D00000 #else #define GPV2_BASE_ADDR 0x00200000 #endif -#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)) +#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL)) #define GPV3_BASE_ADDR 0x00E00000 #define GPV4_BASE_ADDR 0x00F00000 #define GPV5_BASE_ADDR 0x01000000 @@ -99,7 +102,7 @@ #define QSPI0_AMBA_END 0x6FFFFFFF #define QSPI1_AMBA_BASE 0x70000000 #define QSPI1_AMBA_END 0x7FFFFFFF -#elif defined(CONFIG_SOC_MX6UL) +#elif defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) #define WEIM_ARB_BASE_ADDR 0x50000000 #define WEIM_ARB_END_ADDR 0x57FFFFFF #define QSPI0_AMBA_BASE 0x60000000 @@ -119,7 +122,8 @@ #define WEIM_ARB_END_ADDR 0x0FFFFFFF #endif -#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)) +#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX) || \ + defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)) #define MMDC0_ARB_BASE_ADDR 0x80000000 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF #define MMDC1_ARB_BASE_ADDR 0xC0000000 @@ -248,7 +252,7 @@ #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) /* i.MX6SL */ #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) -#ifdef CONFIG_SOC_MX6UL +#if defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) #define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) #else /* i.MX6SX */ @@ -268,7 +272,7 @@ #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#ifdef CONFIG_SOC_MX6UL +#if defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) #elif defined(CONFIG_SOC_MX6SX) #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) @@ -320,14 +324,16 @@ #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) /* only for i.MX6SX/UL */ -#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \ - MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR) +#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) || \ + is_cpu_type(MXC_CPU_MX6ULL)) ? \ + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR) #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 -#if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)) +#if !(defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL)) #define IRAM_SIZE 0x00040000 #else #define IRAM_SIZE 0x00020000 @@ -464,7 +470,8 @@ struct src { struct iomuxc { -#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)) +#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL)) u8 reserved[0x4000]; #endif u32 gpr[14]; @@ -590,7 +597,8 @@ struct cspi_regs { #define MXC_CSPICON_POL 4 /* SCLK polarity */ #define MXC_CSPICON_SSPOL 12 /* SS polarity */ #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ -#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6UL) +#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL) || \ + defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ @@ -651,7 +659,8 @@ struct fuse_bank1_regs { reg_32(ana2); }; -#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL)) +#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6UL) || \ + defined(CONFIG_SOC_MX6ULL)) struct fuse_bank4_regs { reg_32(sjc_resp_low); reg_32(sjc_resp_high); diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index 4717a9469d..8004c67ae0 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -13,7 +13,7 @@ #include "mx6dl-ddr.h" #elif defined(CONFIG_SOC_MX6SX) #include "mx6sx-ddr.h" -#elif defined(CONFIG_SOC_MX6UL) +#elif defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) #include "mx6ul-ddr.h" #else #error "Please select cpu" diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h index 708eaaabd7..230f171301 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -37,7 +37,7 @@ enum { #include "mx6sl_pins.h" #elif defined(CONFIG_SOC_MX6SX) #include "mx6sx_pins.h" -#elif defined(CONFIG_SOC_MX6UL) +#elif defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL) #include "mx6ul_pins.h" #else #error "Please select cpu" diff --git a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h index 13e6263e10..b5b722ad84 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6ul-ddr.h @@ -7,7 +7,7 @@ #ifndef __ASM_ARCH_MX6UL_DDR_H__ #define __ASM_ARCH_MX6UL_DDR_H__ -#ifndef CONFIG_SOC_MX6UL +#if !defined(CONFIG_SOC_MX6UL) && !defined(CONFIG_SOC_MX6ULL) #error "wrong CPU" #endif diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 38f0a6bffb..5c8ee0f99b 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -50,7 +50,7 @@ static unsigned long gpio_ports[] = { #endif #endif #if defined(CONFIG_SOC_MX53) || defined(CONFIG_ARCH_MX6) -#ifndef CONFIG_SOC_MX6UL +#if !(defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)) [6] = GPIO7_BASE_ADDR, #endif #endif diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 19eb25c617..5618ab5a1e 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -562,7 +562,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register for i.MX6UL */ -#ifndef CONFIG_SOC_MX6UL +#if !(defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)) /* FIFO receive start register */ writel(0x520, &fec->eth->r_fstart); #endif diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 130666fd19..0915ca016d 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -17,7 +17,7 @@ #ifndef __MX6_COMMON_H #define __MX6_COMMON_H -#ifndef CONFIG_SOC_MX6UL +#if !(defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)) #define CONFIG_ARM_ERRATA_743622 #define CONFIG_ARM_ERRATA_751472 #define CONFIG_ARM_ERRATA_794072 @@ -54,7 +54,8 @@ #define CONFIG_REVISION_TAG /* Boot options */ -#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6UL)) +#if (defined(CONFIG_SOC_MX6SX) || defined(CONFIG_SOC_MX6SL) || \ + defined(CONFIG_SOC_MX6UL) || defined(CONFIG_SOC_MX6ULL)) #define CONFIG_LOADADDR 0x82000000 #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x87800000