From: Tom Rini Date: Tue, 25 Nov 2014 16:10:01 +0000 (-0500) Subject: Merge branch 'master' of http://git.denx.de/u-boot-samsung X-Git-Tag: KARO-TXA5-2015-06-26~220 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=878cd63e02f63f245182a101807186b44e20f116;hp=-c Merge branch 'master' of http://git.denx.de/u-boot-samsung --- 878cd63e02f63f245182a101807186b44e20f116 diff --combined arch/arm/cpu/armv7/exynos/Kconfig index e9a102ce3c,13dbd95c02..f3eadb4db3 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@@ -26,8 -26,6 +26,8 @@@ config TARGET_ODROI config TARGET_ARNDALE bool "Exynos5250 Arndale board" + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD @@@ -46,11 -44,16 +46,16 @@@ config TARGET_SMDK542 select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD - config TARGET_PEACH_PIT + config TARGET_PEACH_PI bool "Peach Pi board" select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD + config TARGET_PEACH_PIT + bool "Peach Pit board" + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + endchoice config SYS_SOC diff --combined arch/arm/cpu/armv7/exynos/clock.c index c0c95fbc83,4ecce448ce..8fab135beb --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@@ -118,7 -118,8 +118,8 @@@ static int exynos_get_pll_clk(int pllre div = PLL_DIV_1024; else if (proid_is_exynos4412()) div = PLL_DIV_65535; - else if (proid_is_exynos5250() || proid_is_exynos5420()) + else if (proid_is_exynos5250() || proid_is_exynos5420() + || proid_is_exynos5800()) div = PLL_DIV_65536; else return 0; @@@ -1422,8 -1423,8 +1423,8 @@@ static int clock_calc_best_scalar(unsig return 1; for (i = 1; i <= loops; i++) { - const unsigned int effective_div = max(min(input_rate / i / - target_rate, cap), 1); + const unsigned int effective_div = + max(min(input_rate / i / target_rate, cap), 1U); const unsigned int effective_rate = input_rate / i / effective_div; const int error = target_rate - effective_rate; @@@ -1581,7 -1582,7 +1582,7 @@@ static unsigned long exynos4_get_i2c_cl unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else { @@@ -1617,7 -1618,7 +1618,7 @@@ unsigned long get_i2c_clk(void unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { @@@ -1630,7 -1631,7 +1631,7 @@@ unsigned long get_uart_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_uart_clk(dev_index); return exynos5_get_uart_clk(dev_index); } else { @@@ -1643,7 -1644,7 +1644,7 @@@ unsigned long get_mmc_clk(int dev_index) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_mmc_clk(dev_index); return exynos5_get_mmc_clk(dev_index); } else { @@@ -1654,7 -1655,7 +1655,7 @@@ void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_mmc_clk(dev_index, div); else exynos5_set_mmc_clk(dev_index, div); @@@ -1668,7 -1669,7 +1669,7 @@@ unsigned long get_lcd_clk(void if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_get_lcd_clk(); else return exynos5_get_lcd_clk(); @@@ -1682,7 -1683,7 +1683,7 @@@ void set_lcd_clk(void else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420()) + else if (proid_is_exynos5420() || proid_is_exynos5800()) exynos5420_set_lcd_clk(); } } @@@ -1696,7 -1697,7 +1697,7 @@@ void set_mipi_clk(void int set_spi_clk(int periph_id, unsigned int rate) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) + if (proid_is_exynos5420() || proid_is_exynos5800()) return exynos5420_set_spi_clk(periph_id, rate); return exynos5_set_spi_clk(periph_id, rate); } else { diff --combined arch/arm/cpu/armv7/exynos/spl_boot.c index ae3ad0167d,dbd312cfc1..bc237c969f --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@@ -151,7 -151,7 +151,7 @@@ static void exynos_spi_copy(unsigned in } for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { - todo = min(uboot_size - upto, (1 << 15)); + todo = min(uboot_size - upto, (unsigned int)(1 << 15)); spi_rx_tx(regs, todo, (void *)(uboot_addr), (void *)(SPI_FLASH_UBOOT_POS), i); } @@@ -195,10 -195,16 +195,16 @@@ void copy_uboot_to_ram(void void (*end_bootop_from_emmc)(void); #endif #ifdef CONFIG_USB_BOOTING - u32 (*usb_copy)(void); int is_cr_z_set; unsigned int sec_boot_check; + /* + * Note that older hardware (before Exynos5800) does not expect any + * arguments, but it does not hurt to pass them, so a common function + * prototype is used. + */ + u32 (*usb_copy)(u32 num_of_block, u32 *dst); + /* Read iRAM location to check for secondary USB boot mode */ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) @@@ -240,7 -246,7 +246,7 @@@ */ is_cr_z_set = config_branch_prediction(0); usb_copy = get_irom_func(USB_INDEX); - usb_copy(); + usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE); config_branch_prediction(is_cr_z_set); break; #endif diff --combined include/configs/arndale.h index aa6b631c5d,919729d8ae..81e8a7c3a3 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@@ -9,6 -9,9 +9,9 @@@ #ifndef __CONFIG_ARNDALE_H #define __CONFIG_ARNDALE_H + #define EXYNOS_FDTFILE_SETTING \ + "fdtfile=exynos5250-arndale.dtb\0" + #include "exynos5250-common.h" /* SD/MMC configuration */ @@@ -17,8 -20,6 +20,6 @@@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE - #define CONFIG_CMD_EXT2 - /* USB */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS @@@ -60,4 -61,6 +61,4 @@@ /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ #define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 -#define CONFIG_ARMV7_VIRT - #endif /* __CONFIG_H */ diff --combined include/configs/smdk2410.h index b83c15f01f,5df0e28990..71eb81c2f7 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@@ -17,12 -17,15 +17,14 @@@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */ #define CONFIG_SYS_TEXT_BASE 0x0 + #define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* input clock of PLL (the SMDK2410 has 12MHz input clock) */