From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Fri, 22 Nov 2013 09:19:35 +0000 (+0100)
Subject: Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'
X-Git-Tag: v2014.01-rc2~42^2~17
X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=d44a5f51288aec60c6bdb4ac939d75c24e5bf9c2;hp=56eb3da43fab5990a4b7bc118b76c7cae2ceb140

Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'
---

diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 2bb38438ae..9af340e75e 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -16,23 +16,24 @@ void lowlevel_init(void)
 int arch_cpu_init(void)
 {
 	zynq_slcr_unlock();
-	/* remap DDR to zero, FILTERSTART */
-	writel(0, &scu_base->filter_start);
 
 	/* Device config APB, unlock the PCAP */
 	writel(0x757BDF0D, &devcfg_base->unlock);
 	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+	/* remap DDR to zero, FILTERSTART */
+	writel(0, &scu_base->filter_start);
+
 	/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
 	writel(0x1F, &slcr_base->ocm_cfg);
 	/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
 	writel(0x0, &slcr_base->fpga_rst_ctrl);
-	/* TZ_DDR_RAM, Set DDR trust zone non-secure */
-	writel(0xFFFFFFFF, &slcr_base->trust_zone);
 	/* Set urgent bits with register */
 	writel(0x0, &slcr_base->ddr_urgent_sel);
 	/* Urgent write, ports S2/S3 */
 	writel(0xC, &slcr_base->ddr_urgent);
+#endif
 
 	zynq_slcr_lock();