karo-tx-uboot.git
8 years agoenv_mmc: fix buffer allocation for armv7
Markus Niebel [Fri, 4 Oct 2013 13:48:03 +0000 (15:48 +0200)]
env_mmc: fix buffer allocation for armv7

commit d196bd880347373237d73e0d115b4d51c68cf2ad adds
redundand environment to mmc. The usage of malloc in
env_relocate_spec triggers cache errors on armv7.

Tested on a not mainlined i.MX53 board:

Board: TQMa53
I2C:   ready
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
ERROR: v7_dcache_inval_range - start address is not aligned - 0x8f57c2d8
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x8f57e2d8
ERROR: v7_dcache_inval_range - start address is not aligned - 0x8f57e2e0
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x8f5802e0
Using default environment

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
8 years agoenv: dataflash: fix env_init issue
Bo Shen [Tue, 8 Oct 2013 08:30:21 +0000 (16:30 +0800)]
env: dataflash: fix env_init issue

As the SPI controller is not initialized before env_init(), it causes
reading env in dataflash failed. So, although saveenv() successfully,
it shows warning information when reboot the system as following:

  *** Warning - bad CRC, using default environment

Let the env_relocate() to check env CRC and import it.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
8 years agoARM: omap4: Update sdram setting for panda rev A6
Dan Murphy [Wed, 9 Oct 2013 18:53:58 +0000 (13:53 -0500)]
ARM: omap4: Update sdram setting for panda rev A6

OMAP4 panda rev A6 is a 4430 es2.3 IC with an updated memory
part.

The panda rev A6 uses Elpida 2x4Gb memory and no longer uses Micron
so the timings needs to be updated

Signed-off-by: Dan Murphy <dmurphy@ti.com>
8 years agoam335x_evm.h: Make 'am335x_boneblack' use redundant environment
Tom Rini [Thu, 10 Oct 2013 14:25:18 +0000 (10:25 -0400)]
am335x_evm.h: Make 'am335x_boneblack' use redundant environment

Signed-off-by: Tom Rini <trini@ti.com>
8 years ago.gitignore: add auto-generated /include/[s|t]pl-autoconf.mk
Daniel Schwierzeck [Sun, 13 Oct 2013 15:08:02 +0000 (17:08 +0200)]
.gitignore: add auto-generated /include/[s|t]pl-autoconf.mk

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 years agoSPDX: document dual license notation
Wolfgang Denk [Tue, 8 Oct 2013 19:53:45 +0000 (21:53 +0200)]
SPDX: document dual license notation

In [1] we discussed how we should deal with dual (or, more generally,
multiple) licensed files.  Add this to  Licenses/README  so it's
properly documented.

[1] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/166518

Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Add the word 'list' to the end of the line, per Stephen Warren's
feedback]
Signed-off-by: Tom Rini <trini@ti.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Mon, 14 Oct 2013 15:20:32 +0000 (11:20 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-nand-flash
Tom Rini [Mon, 14 Oct 2013 13:37:51 +0000 (09:37 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

8 years agoMerge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Albert ARIBAUD [Fri, 11 Oct 2013 12:47:25 +0000 (14:47 +0200)]
Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

8 years agousb: Prevent using reserved registers on DM36x usb
Andrew Murray [Sun, 29 Sep 2013 17:02:22 +0000 (18:02 +0100)]
usb: Prevent using reserved registers on DM36x usb

The musb driver defines and uses MUSB_CSR0_H_DIS_PING, however this
bit is reserved on the DM36x. Thus this patch ensures that the
reserved bit is not accesssed.

It has been observed that some USB devices will fail to enumerate
with errors such as 'error in inquiry' without this patch.

See http://www.ti.com/litv/pdf/sprufh9a for details.

Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk>
Acked-by: Marek Vasut <marex@denx.de>
8 years agoomap5_common: Re-work mmc boot to try SD and eMMC, correct root device
Tom Rini [Wed, 9 Oct 2013 14:59:33 +0000 (10:59 -0400)]
omap5_common: Re-work mmc boot to try SD and eMMC, correct root device

OMAP5 boards may have both eMMC (on MMC2) and an SD slot (on MMC1).  We
Update the default bootcmd to match what happens on AM335x where we try
SD first, and then eMMC.  In this case however, the hardware layout used
for powering both of these means that in the kernel eMMC shall be found
first as it is powered by a fixed regulator and SD found second as SD is
powered via the palmas which will result in deferred probing.

Tested-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
8 years agocmd_ubi: add write.part command, to write a volume in multiple parts
Paul Burton [Wed, 4 Sep 2013 14:16:59 +0000 (15:16 +0100)]
cmd_ubi: add write.part command, to write a volume in multiple parts

This allows you to write data to an UBI volume when the amount of memory
available to write that data from is less than the total size of the
data. For example, you may split a root filesystem UBIFS image into
parts, provide the total size of the image to the first write.part
command and then use multiple write.part commands to write the
subsequent parts of the volume. This results in a sequence of commands
akin to:

  ext4load mmc 0:1 0x80000000 rootfs.ubifs.0
  ubi write.part 0x80000000 root 0x08000000 0x18000000
  ext4load mmc 0:1 0x80000000 rootfs.ubifs.1
  ubi write.part 0x80000000 root 0x08000000
  ext4load mmc 0:1 0x80000000 rootfs.ubifs.2
  ubi write.part 0x80000000 root 0x08000000

This would write 384MiB of data to the UBI volume 'root' whilst only
requiring 128MiB of said data to be held in memory at a time.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
8 years agocmd_ubi: use int64_t volume size for 'ubi create'
Paul Burton [Wed, 4 Sep 2013 14:16:58 +0000 (15:16 +0100)]
cmd_ubi: use int64_t volume size for 'ubi create'

int64_t matches the bytes field in struct ubi_mkvol_req to which the
size is assigned. With the prior signed 32 bit integer, volumes were
restricted to being less than 2GiB in size.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
8 years agocmd_mtdparts: use 64 bits for flash size, partition size & offset
Paul Burton [Wed, 4 Sep 2013 14:16:57 +0000 (15:16 +0100)]
cmd_mtdparts: use 64 bits for flash size, partition size & offset

This matches the 64 bit size in struct mtd_info and allows the mtdparts
command to function correctly with a flash >= 4GiB. Format specifiers
for size & offset are given the ll length, matching its use in
drivers/mtd in absence of something like inttypes.h/PRIx64.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
8 years agomtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEAN
Paul Burton [Wed, 4 Sep 2013 14:16:56 +0000 (15:16 +0100)]
mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEAN

Linux modified the MTD driver interface in commit edbc4540 (with the
same name as this commit). The effect is that calls to mtd_read will
not return -EUCLEAN if the number of ECC-corrected bit errors is below
a certain threshold, which defaults to the strength of the ECC. This
allows -EUCLEAN to stop indicating "some bits were corrected" and begin
indicating "a large number of bits were corrected, the data held in
this region of flash may be lost soon". UBI makes use of this and when
-EUCLEAN is returned from mtd_read it will move data to another block
of flash. Without adopting this interface change UBI on U-boot attempts
to move data between blocks every time a single bit is corrected using
the ECC, which is a very common occurance on some devices.

For some devices where bit errors are common enough, UBI can get stuck
constantly moving data around because each block it attempts to use has
a single bit error. This condition is hit when wear_leveling_worker
attempts to move data from one PEB to another in response to an
-EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is
called to perform the data copy, and after the data is written it is
read back to check its validity. If that read returns UBI_IO_BITFLIPS
(in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to
wear_leveling worker, which then proceeds to schedule the destination
PEB for erasure. This leads to erase_worker running on the PEB, and
following a successful erase wear_leveling_worker is called which
begins this whole cycle all over again. The end result is that (without
UBI debug output enabled) the boot appears to simply hang whilst in
reality U-boot busily works away at destroying a block of the NAND
flash. Debug output from this situation:

  UBI DBG: ensure_wear_leveling: schedule scrubbing
  UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
  UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027
  UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096
  UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083
  UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data
  UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192
  UBI: fixable bit-flip detected at PEB 1027
  UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083
  UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096
  UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083
  UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096
  UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192
  UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192
  UBI: fixable bit-flip detected at PEB 4083
  UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0
  UBI DBG: erase_worker: erase PEB 4083 EC 55
  UBI DBG: sync_erase: erase PEB 4083, old EC 55
  UBI DBG: do_sync_erase: erase PEB 4083
  UBI DBG: sync_erase: erased PEB 4083, new EC 56
  UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083
  UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0
  UBI DBG: ensure_wear_leveling: schedule scrubbing
  UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083
  ...

This patch adopts the interface change as in Linux commit edbc4540 in
order to avoid such situations. Given that none of the drivers under
drivers/mtd return -EUCLEAN, this should only affect those using
software ECC. I have tested that it works on a board which is
currently out of tree, but which I hope to be able to begin
upstreaming soon.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Stefan Roese <sr@denx.de>
8 years agokm/scripts: fix ramfs
Andreas Huber [Thu, 4 Jul 2013 13:37:34 +0000 (15:37 +0200)]
km/scripts: fix ramfs

'actual_bank' is not used anymore, instead boot_bank is used.

Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
8 years agopowerpc/km: drop unused CONFIG_SYS_DTT_LOW_TEMP
Holger Brunck [Thu, 4 Jul 2013 13:37:33 +0000 (15:37 +0200)]
powerpc/km: drop unused CONFIG_SYS_DTT_LOW_TEMP

This define is not used in u-boot code, we can drop this define safely.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
8 years agokm/common: switch on CMD_GREPENV
Holger Brunck [Thu, 4 Jul 2013 13:37:32 +0000 (15:37 +0200)]
km/common: switch on CMD_GREPENV

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
8 years agopowerpc/83xx: remove staticness for qe_iop_conf_tab
Holger Brunck [Thu, 4 Jul 2013 13:37:31 +0000 (15:37 +0200)]
powerpc/83xx: remove staticness for qe_iop_conf_tab

commit a5510058 powerpc/83xx/km: make local functions and structs static

removed the staticness also from this struct. But this struct is needed
in arch/powerpc/cpu/mpc83xx/cpu_init.c and declared as extern.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
8 years agoMerge branch 'next' of git://git.denx.de/u-boot-mpc83xx
Tom Rini [Wed, 9 Oct 2013 14:06:40 +0000 (10:06 -0400)]
Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

8 years agoda850evm.h: Always set CONFIG_CMD_SF, move to by CONFIG_SPI_FLASH
Tom Rini [Tue, 8 Oct 2013 19:08:38 +0000 (15:08 -0400)]
da850evm.h: Always set CONFIG_CMD_SF, move to by CONFIG_SPI_FLASH

When we have CONFIG_SPI_FLASH set we now require CONFIG_CMD_SF.

Signed-off-by: Tom Rini <trini@ti.com>
8 years agoRevert "am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should mmcroot."
Tom Rini [Tue, 8 Oct 2013 15:09:17 +0000 (11:09 -0400)]
Revert "am335x_evm.h: If mmcdev and bootpart switch to mmcdev 1, so should mmcroot."

Upon further inspection and review and chatting with kernel folks, what
happens here is that what mmcblk# a device gets is based on probe order.
So a system with an SD card inserted with place eMMC on mmcblk1, but
without an SD card, it will be on mmcblk0.  So U-boot can only provide a
best guess.  In this case, if no SD card is present, we would want to
pass mmcblk0p2 still.  If an SD card is present, it woudl be able to
provide a uEnv.txt that would be loaded (even if the kernel is NOT
there) which can still update mmcroot variable.

This reverts commit 827512fb1154c05c6eb1e2259e936df55c98a535.

Cc: Robert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: Tom Rini <trini@ti.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Tue, 8 Oct 2013 13:51:48 +0000 (09:51 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-spi
Tom Rini [Tue, 8 Oct 2013 13:03:15 +0000 (09:03 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-spi

8 years agospi: exynos: Support word transfers
Rajeshwari Shinde [Tue, 8 Oct 2013 10:50:06 +0000 (16:20 +0530)]
spi: exynos: Support word transfers

Since SPI register access is so expensive, it is worth transferring data
a word at a time if we can. This complicates the driver unfortunately.

Use the byte-swapping feature to avoid having to convert to/from big
endian in software.

This change increases speed from about 2MB/s to about 4.5MB/s.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agospi: exynos: Minimise access to SPI FIFO level
Rajeshwari Shinde [Tue, 8 Oct 2013 10:50:05 +0000 (16:20 +0530)]
spi: exynos: Minimise access to SPI FIFO level

Accessing SPI registers is slow, but access to the FIFO level register
in particular seems to be extraordinarily expensive (I measure up to
600ns). Perhaps it is required to synchronise with the SPI byte output
logic which might run at 1/8th of the 40MHz SPI speed (just a guess).

Reduce access to this register by filling up and emptying FIFOs
more completely, rather than just one word each time around the inner
loop.

Since the rxfifo value will now likely be much greater that what we read
before we fill the txfifo, we only fill the txfifo halfway. This is
because if the txfifo is empty, but the rxfifo has data in it, then writing
too much data to the txfifo may overflow the rxfifo as data arrives.

This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agospi: exynos: Support a delay after deactivate
Rajeshwari Shinde [Tue, 8 Oct 2013 10:50:04 +0000 (16:20 +0530)]
spi: exynos: Support a delay after deactivate

For devices that need some time to react after a spi transaction
finishes, add the ability to set a delay.

Implement this as a delay on the first/next transaction to avoid
any delay in the fairly common case where a SPI transaction is
followed by other processing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agoexynos: Export timer_get_us() to get microsecond timer
Rajeshwari Shinde [Tue, 8 Oct 2013 10:50:03 +0000 (16:20 +0530)]
exynos: Export timer_get_us() to get microsecond timer

This function, if implemented by the board, provides a microsecond
timer. The granularity may be larger than 1us if hardware does not
support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agoFix number base handling of "load" command
Wolfgang Denk [Sat, 5 Oct 2013 19:07:25 +0000 (21:07 +0200)]
Fix number base handling of "load" command

As documented, almost all U-Boot commands expect numbers to be entered
in hexadecimal input format. (Exception: for historical reasons, the
"sleep" command takes its argument in decimal input format.)

This rule was broken for the "load" command; for details please see
especially commits 045fa1e "fs: add filesystem switch libary,
implement ls and fsload commands" and 3f83c87 "fs: fix number base
behaviour change in fatload/ext*load".  In the result, the load
command would always require an explicit "0x" prefix for regular
(i. e. base 16 formatted) input.

Change this to use the standard notation of base 16 input format.
While strictly speaking this is a change of the user interface, we
hope that it will not cause trouble.  Stephen Warren comments (see
[1]):

        I suppose you can change the behaviour if you want; anyone
        writing "0x..." for their values presumably won't be
        affected, and if people really do assume all values in U-Boot
        are in hex, presumably nobody currently relies upon using
        non-prefixed values with the generic load command, since it
        doesn't work like that right now.

[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/171172

Acked-by: Tom Rini <trini@ti.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
8 years agosocfpga: Adding pin mux handoff files
Chin Liang See [Wed, 11 Sep 2013 16:26:10 +0000 (11:26 -0500)]
socfpga: Adding pin mux handoff files

Adding the generated pin mux configuration by Preloader
Generator tool

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
8 years agosocfpga: Adding System Manager driver
Chin Liang See [Wed, 11 Sep 2013 16:24:48 +0000 (11:24 -0500)]
socfpga: Adding System Manager driver

Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
8 years agoomap1510inn: arm925t: remove support
Albert ARIBAUD [Mon, 23 Sep 2013 17:11:38 +0000 (19:11 +0200)]
omap1510inn: arm925t: remove support

omap1510inn is orphan and has been for years now.
Reove it and, as it was the only arm925t target,
also remove arm925t support.
Update doc/README.scrapyard accordingly.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
8 years agodoc: SPI: Update SPI status track
Jagannadha Sutradharudu Teki [Mon, 7 Oct 2013 12:03:20 +0000 (17:33 +0530)]
doc: SPI: Update SPI status track

Updated SPI/status.txt, with memory_map and TODO.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: ramtron: Remove page_size print
Jagannadha Sutradharudu Teki [Mon, 7 Oct 2013 11:51:20 +0000 (17:21 +0530)]
sf: ramtron: Remove page_size print

There is no page_size for ramtron flashes,
so just print the detected flash and it's size.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: Minor cleanups
Jagannadha Sutradharudu Teki [Mon, 7 Oct 2013 14:04:56 +0000 (19:34 +0530)]
sf: Minor cleanups

- Add spaces, tabs
- Commenting.
- Rearrange code.
- Add static qualifier for missing func.
- Remove memory_map from ramtron.c
- Ramtron: spi_flash_internal.h -> sf_internal.h

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agoREADME: qspi usecase and testing documentation.
Poddar, Sourav [Mon, 7 Oct 2013 10:23:04 +0000 (15:53 +0530)]
README: qspi usecase and testing documentation.

Contains documentation and testing details for qspi flash
interface.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agodra7xx_evm: add SPL API, QSPI, and serial flash support
Matt Porter [Mon, 7 Oct 2013 10:23:03 +0000 (15:53 +0530)]
dra7xx_evm: add SPL API, QSPI, and serial flash support

Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agospi: add TI QSPI driver
Matt Porter [Mon, 7 Oct 2013 10:23:02 +0000 (15:53 +0530)]
spi: add TI QSPI driver

Adds a SPI master driver for the TI QSPI peripheral.
- Added quad read support.
- Added memory mapped support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: Add memory mapped read support
Poddar, Sourav [Mon, 7 Oct 2013 10:23:01 +0000 (15:53 +0530)]
sf: Add memory mapped read support

Qspi controller can have a memory mapped port which can be used for
data read. Added support to enable memory mapped port read.

This patch enables the following:
- It enables exchange of memory map address between mtd and qspi
through the introduction of "memory_map" flag.
- Add support to communicate to the driver that memory mapped
 transfer is to be started through introduction of new flags like
"SPI_XFER_MEM_MAP" and "SPI_XFER_MEM_MAP_END".

This will enable the spi controller to do memory mapped configurations
if required.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agoarmv7: hw_data: change clock divider setting.
Poddar, Sourav [Mon, 7 Oct 2013 10:23:00 +0000 (15:53 +0530)]
armv7: hw_data: change clock divider setting.

Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agoomap5: add qspi support
Matt Porter [Mon, 7 Oct 2013 10:22:59 +0000 (15:52 +0530)]
omap5: add qspi support

Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
8 years agosf: probe: Add support for EN25S64
Priyanka Jain [Thu, 3 Oct 2013 15:37:00 +0000 (21:07 +0530)]
sf: probe: Add support for EN25S64

Add support for EON EN25S64 SPI flash.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agodoc: SPI: Add status.txt for tracking SPI subsys status
Jagannadha Sutradharudu Teki [Thu, 26 Sep 2013 10:25:52 +0000 (15:55 +0530)]
doc: SPI: Add status.txt for tracking SPI subsys status

doc/SPI/status.txt added to track the u-boot SPI subsystem status.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: Rename spi_flash files
Jagannadha Sutradharudu Teki [Thu, 26 Sep 2013 10:30:15 +0000 (16:00 +0530)]
sf: Rename spi_flash files

Renamed:
spi_flash.c -> sf.c
spi_flash_internal.h -> sf_internal.h
spi_flash_ops.c -> sf_ops.c
spi_flash_probe.c -> sf_probe.c

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agospi: spi cleanups
Jagannadha Sutradharudu Teki [Wed, 25 Sep 2013 10:17:36 +0000 (15:47 +0530)]
spi: spi cleanups

- Rearranged multi-line comment style.
- Add tabs.
- Add spaces.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: spi_flash cleanups
Jagannadha Sutradharudu Teki [Wed, 2 Oct 2013 14:08:49 +0000 (19:38 +0530)]
sf: spi_flash cleanups

More cleanups on spi_flash side:
- Removed unneeded comments.
- Rearranged macros in proper location.
- Rearranged func declerations
- Renamed few function names.
- Added License headers.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: Remove spi_flash_do_alloc references
Jagannadha Sutradharudu Teki [Wed, 7 Aug 2013 16:06:25 +0000 (21:36 +0530)]
sf: Remove spi_flash_do_alloc references

Added a support for common probe, hence removed removed
spi_flash_do_alloc reference.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for MX25L51235F
Jagannadha Sutradharudu Teki [Wed, 28 Aug 2013 09:19:13 +0000 (14:49 +0530)]
sf: probe: Add support for MX25L51235F

Add support for Macronix MX25L51235F SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for MX25L25635F
Jagannadha Sutradharudu Teki [Wed, 28 Aug 2013 09:16:49 +0000 (14:46 +0530)]
sf: probe: Add support for MX25L25635F

Add support for Macronix MX25L25635F SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: ops: Add static qualifier to spi_flash_cmd_bankaddr_write
Jagannadha Sutradharudu Teki [Wed, 28 Aug 2013 09:27:03 +0000 (14:57 +0530)]
sf: ops: Add static qualifier to spi_flash_cmd_bankaddr_write

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Print erase_size while printing flash details
Jagannadha Sutradharudu Teki [Sun, 15 Sep 2013 17:36:12 +0000 (23:06 +0530)]
sf: probe: Print erase_size while printing flash details

Included erase_size while printing probed flash details.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Use print_size arg as page_size
Jagannadha Sutradharudu Teki [Sun, 15 Sep 2013 17:34:16 +0000 (23:04 +0530)]
sf: probe: Use print_size arg as page_size

Use flash->page_size arg in print_size() instead of
flash->sector_size while printing detected flas part details.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for S25FL512S_256K
Jagannadha Sutradharudu Teki [Wed, 28 Aug 2013 06:48:56 +0000 (12:18 +0530)]
sf: probe: Add support for S25FL512S_256K

Add support for Spansion S25FL512S_256K SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for S25FL256S_256K
Jagannadha Sutradharudu Teki [Wed, 28 Aug 2013 06:47:56 +0000 (12:17 +0530)]
sf: probe: Add support for S25FL256S_256K

Add support for Spansion S25FL256S_256K SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for EN25Q64
Jagannadha Sutradharudu Teki [Tue, 6 Aug 2013 10:50:23 +0000 (16:20 +0530)]
sf: probe: Add support for EN25Q64

Add support for EON EN25Q64 SPI flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: Remove unneeded flash drivers files
Jagannadha Sutradharudu Teki [Thu, 29 Aug 2013 13:58:09 +0000 (19:28 +0530)]
sf: Remove unneeded flash drivers files

Now the common probing is handled in spi_flash_probe.c
hence removed the unneeded flash drivers.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: ramtron: Add support for separate flash driver
Jagannadha Sutradharudu Teki [Tue, 24 Sep 2013 10:33:45 +0000 (16:03 +0530)]
sf: ramtron: Add support for separate flash driver

Compared to other spi flashes, ramtron has a different
probing and implementation on flash ops, hence moved
ramtron probe code into ramtron driver.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: Add proper comment style on spi_flash structure
Jagannadha Sutradharudu Teki [Sat, 28 Sep 2013 12:40:43 +0000 (18:10 +0530)]
sf: Add proper comment style on spi_flash structure

Added proper comment style on spi_flash structure to make
more readable.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Simply the BAR configuration logic
Jagannadha Sutradharudu Teki [Thu, 26 Sep 2013 08:54:58 +0000 (14:24 +0530)]
sf: probe: Simply the BAR configuration logic

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for flag status polling
Jagannadha Sutradharudu Teki [Wed, 2 Oct 2013 14:07:43 +0000 (19:37 +0530)]
sf: probe: Add support for flag status polling

From Micron, 512MB onwards, flash requires to poll flag status
instead of read status- hence added E_FSR flag on spectific
flash parts.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for erase sector selection flag
Jagannadha Sutradharudu Teki [Wed, 2 Oct 2013 14:06:58 +0000 (19:36 +0530)]
sf: probe: Add support for erase sector selection flag

SECT_4K, SECT_32K and SECT_64K opeartions are performed to
to specific flash by adding a SECT* flag on respective
spi_flash_params.flag param.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support to clear flash BP# bits
Jagannadha Sutradharudu Teki [Thu, 26 Sep 2013 07:46:45 +0000 (13:16 +0530)]
sf: probe: Add support to clear flash BP# bits

Few of the flashes(Atmel, Macronix and SST) require to
clear BP# bits in flash power ups.

So clear these BP# bits at probe time, so-that the flash
is ready for user operations.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for SST_WP
Jagannadha Sutradharudu Teki [Wed, 2 Oct 2013 14:04:53 +0000 (19:34 +0530)]
sf: probe: Add support for SST_WP

Most of the SST flashes needs to write up using SST_WP, AAI
Word Program, so added a flag param on spi_flash_params table.

SST flashes, which supports SST_WP need to use a WP write
sst_write_wp instead of common flash write.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Give proper spacing on flash table params
Jagannadha Sutradharudu Teki [Sat, 28 Sep 2013 11:36:03 +0000 (17:06 +0530)]
sf: probe: Give proper spacing on flash table params

Given proper spacing between flash table params.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for AT45DB* flash parts
Jagannadha Sutradharudu Teki [Tue, 6 Aug 2013 14:31:08 +0000 (20:01 +0530)]
sf: probe: Add support for AT45DB* flash parts

Added AT45DB* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for SST25* flash parts
Jagannadha Sutradharudu Teki [Mon, 5 Aug 2013 12:06:02 +0000 (17:36 +0530)]
sf: probe: Add support for SST25* flash parts

Added SST25* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
8 years agosf: probe: Add support for S25FL* flash parts
Jagannadha Sutradharudu Teki [Sat, 28 Sep 2013 11:19:37 +0000 (16:49 +0530)]
sf: probe: Add support for S25FL* flash parts

Added S25FL* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for W25* flash parts
Jagannadha Sutradharudu Teki [Sat, 28 Sep 2013 11:27:56 +0000 (16:57 +0530)]
sf: probe: Add support for W25* flash parts

Added W25* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for MX25L* flash parts
Jagannadha Sutradharudu Teki [Mon, 5 Aug 2013 11:56:16 +0000 (17:26 +0530)]
sf: probe: Add support for MX25L* flash parts

Added MX25L* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for GD25* flash parts
Jagannadha Sutradharudu Teki [Mon, 5 Aug 2013 10:50:27 +0000 (16:20 +0530)]
sf: probe: Add support for GD25* flash parts

Added GD25* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for EN25Q* flash parts
Jagannadha Sutradharudu Teki [Tue, 6 Aug 2013 14:30:00 +0000 (20:00 +0530)]
sf: probe: Add support for EN25Q* flash parts

Added EN25Q* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add support for M25P* flash parts
Jagannadha Sutradharudu Teki [Mon, 5 Aug 2013 10:47:37 +0000 (16:17 +0530)]
sf: probe: Add support for M25P* flash parts

Added M25P* parts are which are avilable in spi_flash_probe_legacy.c.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: probe: Add new spi_flash_probe support
Jagannadha Sutradharudu Teki [Tue, 24 Sep 2013 10:31:23 +0000 (16:01 +0530)]
sf: probe: Add new spi_flash_probe support

Added new spi_flash_probe support, currently added N25Q*
flash part attributes support.

Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agosf: Divide spi_flash into multiple parts
Jagannadha Sutradharudu Teki [Thu, 29 Aug 2013 13:31:56 +0000 (19:01 +0530)]
sf: Divide spi_flash into multiple parts

Divided the spi_flash framework into mutiple parts for
- spi_flash.c:
        spi flash core file, interaction for spi/qspi driver to
        spi_flash framework.
- spi_flash_ops.c
        spi flash preffered operations, erase,write and read.
- spi_flash_probe.c
        spi flash probing, easy to extend probing functionality.

This change will support to extend the functionality in a
proper manner.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
8 years agopci: Properly configure prefetchable memory region
Thierry Reding [Fri, 20 Sep 2013 13:50:50 +0000 (15:50 +0200)]
pci: Properly configure prefetchable memory region

Forcibly set hose->pci_prefetch to NULL to make sure it will be setup.
This will help if for any reason callers didn't make sure themselves to
NULL the field.

Signed-off-by: Thierry Reding <treding@nvidia.com>
8 years agoARM: virtualization: replace verbose license with SPDX identifier
Andre Przywara [Mon, 7 Oct 2013 08:56:51 +0000 (10:56 +0200)]
ARM: virtualization: replace verbose license with SPDX identifier

The original creation of arch/arm/cpu/armv7/{virt-v7.c,nonsec_virt.S}
predates the SPDX conversion, so the original elaborate license
statements sneaked in.
Fix this by replacing them with the proper abbreviation.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agodoc: Fix a typo in the description in doc/README.JFFS2_NAND
Otavio Salvador [Thu, 3 Oct 2013 11:04:40 +0000 (08:04 -0300)]
doc: Fix a typo in the description in doc/README.JFFS2_NAND

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
8 years agoinclude/linux/fb.h: Add a missing include for 'list.h'
Otavio Salvador [Thu, 3 Oct 2013 11:04:39 +0000 (08:04 -0300)]
include/linux/fb.h: Add a missing include for 'list.h'

The modelist data uses the list definition but the 'list.h' header
were not being included. The build failure is bellow:

,----
| In file included from yyyy.c:16:0:
| .../u-boot/include/linux/fb.h:503:19: error: field 'modelist' has incomplete type
|   struct list_head modelist; /* mode list */
|                    ^
| make[1]: *** [yyyy.o] Error 1
| make[1]: Leaving directory `.../u-boot/board/xxx/yyyy'
| make: *** [board/xxx/yyyy/libyyyy.o] Error 2
`----

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
8 years agomtd: Fix function description in part_validate comment
Otavio Salvador [Thu, 3 Oct 2013 11:04:38 +0000 (08:04 -0300)]
mtd: Fix function description in part_validate comment

The part_validate comment had a wrong description of the actions it
does and referenced to non-existent functions while in fact it calls
'part_validate_eraseblock()'.

Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
8 years agopower:pmic: prevent data abort for pmic bat command
Piotr Wilczek [Thu, 26 Sep 2013 12:43:35 +0000 (14:43 +0200)]
power:pmic: prevent data abort for pmic bat command

This patch prevents data abort when pmic bat command is called
on non-batery pmic device.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
CC: Lukasz Majewski <l.majewski@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>
8 years agousb: Fix error handling in musb_hcd.c
Andrew Murray [Tue, 1 Oct 2013 14:58:56 +0000 (15:58 +0100)]
usb: Fix error handling in musb_hcd.c

The wait_until_[rx|tx]ep_ready functions return a u8 to indicate success
containing the value 0, 1 or -1. This patch changes the return type to an
int to accommodate the negative return values.

These functions are used in the file using calls such as if (!wait_until...
Where a -1 is returned it is mishandled and treated as success instead of
a CRC error. This patch addresses this.

Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk>
Acked-by: Marek Vasut <marex@denx.de>
8 years agopcm051/igep0033: Supply bd_ram_ofs for cpsw driver
Lars Poeschel [Mon, 30 Sep 2013 07:51:34 +0000 (09:51 +0200)]
pcm051/igep0033: Supply bd_ram_ofs for cpsw driver

Since 2bf36ac638ab2db9f0295aa47064976eeebf80c1 the BD ram address is
not hardcoded inside cpsw driver any more. Platforms have to supply
their bd_ram_ofs in the platform data to the driver. This commit does
this for pcm051 and igep0033 boards.

Tested-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
8 years agoARM: IGEP0033: Update timing to run DDR at 400MHz.
Enric Balletbo i Serra [Tue, 10 Sep 2013 09:12:26 +0000 (11:12 +0200)]
ARM: IGEP0033: Update timing to run DDR at 400MHz.

We can run the DDR at 400MHz, so update the timings for that purpose.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
8 years agoam335x_evm: Switch to zImage as default rather than uImage
Tom Rini [Tue, 24 Sep 2013 13:40:52 +0000 (09:40 -0400)]
am335x_evm: Switch to zImage as default rather than uImage

Signed-off-by: Tom Rini <trini@ti.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Fri, 4 Oct 2013 17:17:48 +0000 (13:17 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

8 years agoARM: VExpress: enable ARMv7 virt support for VExpress A15
Andre Przywara [Thu, 19 Sep 2013 16:06:46 +0000 (18:06 +0200)]
ARM: VExpress: enable ARMv7 virt support for VExpress A15

To enable hypervisors utilizing the ARMv7 virtualization extension
on the Versatile Express board with the A15 core tile, we add the
required configuration variable.
Also we define the board specific smp_set_cpu_boot_addr() function to
set the start address for secondary cores in the VExpress specific
manner.
There is no need to provide a custom smp_waitloop() function here.

This also serves as an example for what to do when adding support for
new boards.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoARM: extend non-secure switch to also go into HYP mode
Andre Przywara [Thu, 19 Sep 2013 16:06:45 +0000 (18:06 +0200)]
ARM: extend non-secure switch to also go into HYP mode

For the KVM and XEN hypervisors to be usable, we need to enter the
kernel in HYP mode. Now that we already are in non-secure state,
HYP mode switching is within short reach.

While doing the non-secure switch, we have to enable the HVC
instruction and setup the HYP mode HVBAR (while still secure).

The actual switch is done by dropping back from a HYP mode handler
without actually leaving HYP mode, so we introduce a new handler
routine in our new secure exception vector table.

In the assembly switching routine we save and restore the banked LR
and SP registers around the hypercall to do the actual HYP mode
switch.

The C routine first checks whether we are in HYP mode already and
also whether the virtualization extensions are available. It also
checks whether the HYP mode switch was finally successful.
The bootm command part only calls the new function after the
non-secure switch.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoARM: add SMP support for non-secure switch
Andre Przywara [Thu, 19 Sep 2013 16:06:44 +0000 (18:06 +0200)]
ARM: add SMP support for non-secure switch

Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.

So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.

The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
While this approach is pretty universal across several ARMv7 boards,
we make this function weak in case someone needs to tweak this for
a specific board.

The way of setting the secondary's start address is board specific,
but mostly different only in the actual SMP pen address, so we also
provide a weak default implementation and just depend on the proper
address to be set in the config file.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoARM: trigger non-secure state switch during bootm execution
Andre Przywara [Thu, 19 Sep 2013 16:06:43 +0000 (18:06 +0200)]
ARM: trigger non-secure state switch during bootm execution

To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoARM: add C function to switch to non-secure state
Andre Przywara [Thu, 19 Sep 2013 16:06:42 +0000 (18:06 +0200)]
ARM: add C function to switch to non-secure state

The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.

We check the availability of the security extensions first.

Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Boards not implementing the CBAR can override this value via a
configuration file variable.

Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
   (GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
   (GICD_IGROUPRn = 0xFFFFFFFF)

The core specific GIC setup is then done in the assembly routine.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoARM: add assembly routine to switch to non-secure state
Andre Przywara [Thu, 19 Sep 2013 16:06:41 +0000 (18:06 +0200)]
ARM: add assembly routine to switch to non-secure state

While actually switching to non-secure state is one thing, another
part of this process is to make sure that we still have full access
to the interrupt controller (GIC).
The GIC is fully aware of secure vs. non-secure state, some
registers are banked, others may be configured to be accessible from
secure state only.
To be as generic as possible, we get the GIC memory mapped address
based on the PERIPHBASE value in the CBAR register. Since this
register is not architecturally defined, we check the MIDR before to
be from an A15 or A7.
For CPUs not having the CBAR or boards with wrong information herein
we allow providing the base address as a configuration variable.

Now that we know the GIC address, we:
a) allow private interrupts to be delivered to the core
   (GICD_IGROUPR0 = 0xFFFFFFFF)
b) enable the CPU interface (GICC_CTLR[0] = 1)
c) set the priority filter to allow non-secure interrupts
   (GICC_PMR = 0xFF)

Also we allow access to all coprocessor interfaces from non-secure
state by writing the appropriate bits in the NSACR register.

The generic timer base frequency register is only accessible from
secure state, so we have to program it now. Actually this should be
done from primary firmware before, but some boards seems to omit
this, so if needed we do this here with a board specific value.
The Versatile Express board does not need this, so we remove the
frequency from the configuration file here.

After having switched to non-secure state, we also enable the
non-secure GIC CPU interface, since this register is banked.

Since we need to call this routine also directly from the smp_pen
later (where we don't have any stack), we can only use caller saved
registers r0-r3 and r12 to not mess with the compiler.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoARM: add secure monitor handler to switch to non-secure state
Andre Przywara [Thu, 19 Sep 2013 16:06:40 +0000 (18:06 +0200)]
ARM: add secure monitor handler to switch to non-secure state

A prerequisite for using virtualization is to be in HYP mode, which
requires the CPU to be in non-secure state first.
Add a new file in arch/arm/cpu/armv7 to hold a monitor handler routine
which switches the CPU to non-secure state by setting the NS and
associated bits.
According to the ARM architecture reference manual this should not be
done in SVC mode, so we have to setup a SMC handler for this.
We create a new vector table to avoid interference with other boards.
The MVBAR register will be programmed later just before the smc call.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoARM: prepare armv7.h to be included from assembly source
Andre Przywara [Thu, 19 Sep 2013 16:06:39 +0000 (18:06 +0200)]
ARM: prepare armv7.h to be included from assembly source

armv7.h contains some useful constants, but also C prototypes.
To include it also in assembly files, protect the non-assembly
part appropriately.

Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
8 years agoPrepare v2013.04-rc4 v2013.10-rc4
Tom Rini [Wed, 2 Oct 2013 18:42:08 +0000 (14:42 -0400)]
Prepare v2013.04-rc4

Signed-off-by: Tom Rini <trini@ti.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Wed, 2 Oct 2013 15:45:22 +0000 (11:45 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

8 years agoMerge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Albert ARIBAUD [Wed, 2 Oct 2013 12:53:27 +0000 (14:53 +0200)]
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

8 years agoMerge branch 'buildman' of git://git.denx.de/u-boot-x86
Tom Rini [Wed, 2 Oct 2013 12:26:23 +0000 (08:26 -0400)]
Merge branch 'buildman' of git://git.denx.de/u-boot-x86

8 years agoMerge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Albert ARIBAUD [Wed, 2 Oct 2013 06:10:36 +0000 (08:10 +0200)]
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

8 years agobuildman: Allow make flags to be specified for each board
Simon Glass [Mon, 23 Sep 2013 23:35:17 +0000 (17:35 -0600)]
buildman: Allow make flags to be specified for each board

There are a few make options such as BUILD_TAG which can be provided when
building U-Boot. Provide a way for buildman to pass these flags to make
also.

The flags should be in a [make-flags] section and arranged by target name
(the 'target' column in boards.cfg. See the README for more details.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agobuildman: Adjust tests for new boards.cfg format
Simon Glass [Mon, 23 Sep 2013 23:35:16 +0000 (17:35 -0600)]
buildman: Adjust tests for new boards.cfg format

Commit 27af930e9a5c91365ca639ada580b338eabe4989 changed the boards.cfg format
but missed to change the parsing in buildman. A follow-on commit
03c1bb242548e4e9d267d784861ccd69a1887aa0 fixed this but missed fixing the
tests.

This patch updates the tests to fit the new Board constructor.

./tools/buildman/buildman -t
<unittest.result.TestResult run=1 errors=0 failures=0>

Signed-off-by: Simon Glass <sjg@chromium.org>