karo-tx-uboot.git
9 years agoscsi: Provide support for a list of AHCI controllers.
Vadim Bendebury [Mon, 29 Oct 2012 05:23:45 +0000 (05:23 +0000)]
scsi: Provide support for a list of AHCI controllers.

Many AHCI controllers are identical, the main (and often the
only) difference being the PCI Vendor ID/Device ID combination
reported by the device.

This change allows the config file to define a list of PCI vendor
ID/device ID pairs. The driver would scan the list and initialize
the first device it finds.

No actual multiple device list is introduced yet, this change
just add the framework.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoahci: Support splitting of read transactions into multiple chunks
Vadim Bendebury [Mon, 29 Oct 2012 05:23:44 +0000 (05:23 +0000)]
ahci: Support splitting of read transactions into multiple chunks

With an Intel AHCI controller, the driver does not operate properly
if the requested amount of blocks to read exceeds 255.

It is probably possible to specify 0 as the block count and the driver
will read 256 blocks, but it was decided to limit the number of blocks
read at once to 128 (it should be a power of 2 for the optimal
performance of solid state drives).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoZFS: Fix compile warning in fs/zfs/zfs.c (GCC 4.6.4 from ELDK 5.2.1)
Stefan Roese [Fri, 26 Oct 2012 04:24:01 +0000 (04:24 +0000)]
ZFS: Fix compile warning in fs/zfs/zfs.c (GCC 4.6.4 from ELDK 5.2.1)

This patch fixes the following compile warning:
zfs.c:2006:1: warning: 'zfs_label' defined but not used [-Wunused-function]
zfs.c:2029:1: warning: 'zfs_uuid' defined but not used [-Wunused-function]

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jorgen Lundman <lundman@lundman.net>
9 years agoZFS: Fix compile warning in cmd_zfs.c (GCC 4.6.4 from ELDK 5.2.1)
Stefan Roese [Fri, 26 Oct 2012 04:24:00 +0000 (04:24 +0000)]
ZFS: Fix compile warning in cmd_zfs.c (GCC 4.6.4 from ELDK 5.2.1)

This patch fixes the following compile warnings:

cmd_zfs.c:177:1: warning: initialization from incompatible pointer type [enabled by default]
cmd_zfs.c:177:1: warning: (near initialization for '_u_boot_list_cmd_zfsls.cmd') [enabled by default]
cmd_zfs.c:182:1: warning: initialization from incompatible pointer type [enabled by default]
cmd_zfs.c:182:1: warning: (near initialization for '_u_boot_list_cmd_zfsload.cmd') [enabled by default]

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Jorgen Lundman <lundman@lundman.net>
9 years agoam335x_evm: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support
Tom Rini [Wed, 24 Oct 2012 07:28:17 +0000 (07:28 +0000)]
am335x_evm: Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support

We add CONFIG_ENV_VARS_UBOOT_CONFIG,
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and CONFIG_BOARD_LATE_INIT to set
the variables and then fdtfile and findfdt to make us of this.  It is
now possible to do 'run findfdt' to have fdtfile be set to the value of
the dtb file to load for the board we are running on.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoAdd board_name to CONFIG_ENV_VARS_UBOOT_CONFIG
Stephen Warren [Wed, 31 Oct 2012 11:17:28 +0000 (11:17 +0000)]
Add board_name to CONFIG_ENV_VARS_UBOOT_CONFIG

CONFIG_ENV_VARS_UBOOT_CONFIG creates environment variables indicating
which configuration U-Boot was built for. Some U-Boot binaries run on
multiple boards, and hence this information may not uniquley describe
the HW that U-Boot is actually running on. Another patch introduces
environment variable board_name to represent that. In order to avoid
scripts having to check $board_name, use it if set, and then fall back
to using $board, make CONFIG_ENV_VARS_UBOOT_CONFIG also set a default
value for board_name, so that variable is always available.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agoREADME: Document CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Tom Rini [Wed, 24 Oct 2012 07:28:16 +0000 (07:28 +0000)]
README: Document CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

This option is intended to be set by boards which will set the
board_name and board_rev environment variables.  These are to be used
when the U-Boot binary can support more than one board type at run-time
and the user needs an easy way (for example for scripting to determine
what device tree to load) to determine what board they are on.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agogit-mailrc: Change x86 maintainer to Simon
Simon Glass [Wed, 31 Oct 2012 12:41:49 +0000 (12:41 +0000)]
git-mailrc: Change x86 maintainer to Simon

Grame is still listed since he has agreed to continue with some review.
Also add an alias to shorten things.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agolib/vsprintf.c: don't special-case pointers to address null
Wolfgang Denk [Tue, 30 Oct 2012 09:19:52 +0000 (09:19 +0000)]
lib/vsprintf.c: don't special-case pointers to address null

The %p format of printf() would print a pointer to address null as
"(null)".  This makes sense in a real OS where a NULL pointer must
never be dereferenced, but this is a bootloader, and there are cases
where accessing the data at address null makes perfect sense.

Remove the special case in lib/vsprintf.c using "#if 0" with a comment
to make clear this was an intentional change and to stop re-adding
this code.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agocmd_fdt.c: Use %p when printing pointers
Tom Rini [Mon, 29 Oct 2012 14:53:18 +0000 (14:53 +0000)]
cmd_fdt.c: Use %p when printing pointers

When putting pointers into a format string use %p to ensure that they
are printed correctly regardless of bitsize.  This fixes warnings on
sandbox on 64bit systems.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Gerald Van Baren <vanbaren@cideas.com>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agofs: handle CONFIG_NEEDS_MANUAL_RELOC
Stephen Warren [Tue, 30 Oct 2012 07:50:47 +0000 (07:50 +0000)]
fs: handle CONFIG_NEEDS_MANUAL_RELOC

Without this, fstypes[].probe points at the wrong place, so calling the
function results in undefined behaviour.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
9 years agoMAKEALL: Add -s to '${MAKE} tidy' section
Tom Rini [Thu, 25 Oct 2012 08:53:14 +0000 (08:53 +0000)]
MAKEALL: Add -s to '${MAKE} tidy' section

When BUILD_NBUILDS is > 1 we run the tidy command.  With the addition of
DocBook this now includes a -C doc/DocBook and a 'entering/leaving' pair
of messages happen.  Since we don't want to see what's being cleaned
here, we can just invoke make -s like we do when building.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoext4: Fix printf() format string error
Simon Glass [Tue, 23 Oct 2012 13:49:25 +0000 (13:49 +0000)]
ext4: Fix printf() format string error

Fix the following error in the ext4 command:

cmd_ext4.c:110:3: error: format '%lu' expects argument of type
'long unsigned int', but argument 4 has type 'int' [-Werror=format]

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoFPGA: Cyclon II: Correctly reset the FPGA before configuration
Stephan Gatzka [Mon, 22 Oct 2012 23:11:41 +0000 (23:11 +0000)]
FPGA: Cyclon II: Correctly reset the FPGA before configuration

Deassert the CONFIG pin before asserting it again. This assures that the
FPGA will be resetted and therefore configuration will be correctly
enabled.

This is also already done on other FPGA's, e.g. Stratix.

Signed-off-by: Stephan Gatzka <stephan.gatzka@hbm.com>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agofs: add filesystem switch libary, implement ls and fsload commands
Stephen Warren [Mon, 22 Oct 2012 06:43:51 +0000 (06:43 +0000)]
fs: add filesystem switch libary, implement ls and fsload commands

Implement "ls" and "fsload" commands that act like {fat,ext2}{ls,load},
and transparently handle either file-system. This scheme could easily be
extended to other filesystem types; I only didn't do it for zfs because
I don't have any filesystems of that type to test with.

Replace the implementation of {fat,ext[24]}{ls,load} with this new code
too.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
9 years agofs: separate CONFIG_FS_{FAT, EXT4} from CONFIG_CMD_{FAT, EXT*}
Stephen Warren [Mon, 22 Oct 2012 06:43:50 +0000 (06:43 +0000)]
fs: separate CONFIG_FS_{FAT, EXT4} from CONFIG_CMD_{FAT, EXT*}

This makes the FAT and ext4 filesystem implementations build if
CONFIG_FS_{FAT,EXT4} are defined, rather than basing the build on
whether CONFIG_CMD_{FAT,EXT*} are defined. This will allow the
filesystems to be built separately from the filesystem-specific commands
that use them. This paves the way for the creation of filesystem-generic
commands that used the filesystems, without requiring the filesystem-
specific commands.

Minor documentation changes are made for this change.

The new config options are automatically selected by the old config
options to retain backwards-compatibility.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
9 years agofs: delete unused Makefile
Stephen Warren [Mon, 22 Oct 2012 06:43:49 +0000 (06:43 +0000)]
fs: delete unused Makefile

fs/Makefile is unused. The top-level Makefile sets LIBS-y += fs/xxx and
hence causes make to directly descend two directory levels into each
individual filesystem, and it never descends into fs/ itself.

So, delete this useless file.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-coldfire
Tom Rini [Mon, 29 Oct 2012 15:02:11 +0000 (08:02 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-coldfire

9 years agoColdFire: Remove save env in NAND support for M54418TWR board.
Jason Jin [Thu, 25 Oct 2012 07:27:37 +0000 (15:27 +0800)]
ColdFire: Remove save env in NAND support for M54418TWR board.

This patch remove the env saving in NAND as so far the
NAND driver is not ported to the M54418TWR platform.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
9 years agoColdFire: Update the lds file for M54418TWR board.
Jason Jin [Thu, 25 Oct 2012 06:51:42 +0000 (14:51 +0800)]
ColdFire: Update the lds file for M54418TWR board.

The M54418TWR lds file  need to update since commit:

8b493a52367623f36e628e4ab2cf8ee082b655e0

common: Discard the __u_boot_cmd section

The command declaration now uses the new LG-array method to generate
list of commands. Thus the __u_boot_cmd section is now superseded and
redundant and therefore can be removed. Also, remove externed symbols
associated with this section from include/command.h .

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
9 years agoESTEEM192E: adjust linker script to grown code size
Wolfgang Denk [Wed, 24 Oct 2012 02:36:17 +0000 (02:36 +0000)]
ESTEEM192E: adjust linker script to grown code size

Once more, some of the previous changes caused the code to grow, which
causes errors like

u-boot.lds:74 cannot move location counter backwards (from 40008384 to 40008000)

when building with some older tool chains (like ELDK 4.2).
Adjust the linker script to make fit again.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Conn Clark <clark@esteem.com>
9 years agoTQM8xx: adjust linker script to grown code size
Wolfgang Denk [Wed, 24 Oct 2012 02:36:16 +0000 (02:36 +0000)]
TQM8xx: adjust linker script to grown code size

Once more, some of the previous changes caused the code to grow, which
causes errors like

u-boot.lds:80 cannot move location counter backwards (from 400082a4 to 40008000)

when building with some older tool chains (like ELDK 4.2).
Adjust the linker script to make fit again.

Signed-off-by: Wolfgang Denk <wd@denx.de>
9 years agoPPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)
Wolfgang Denk [Wed, 24 Oct 2012 02:36:15 +0000 (02:36 +0000)]
PPC: remove dead boards (AMX860, c2mon, ETX094, IAD210, LANTEC, SCM)

These boards have long reached EOL, and there has been no indication
of any active users of such hardware for years.  Get rid of the dead
weight.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Grandegger <wg@denx.de>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Fri, 26 Oct 2012 22:44:31 +0000 (15:44 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

9 years agoARM: fix u-boot.lds for -ffunction-sections/-fdata-sections
Stephen Warren [Mon, 22 Oct 2012 06:19:32 +0000 (06:19 +0000)]
ARM: fix u-boot.lds for -ffunction-sections/-fdata-sections

When -ffunction-sections or -fdata-section are used, symbols are placed
into sections such as .data.eserial1_device and .bss.serial_current.
Update the linker script to explicitly include these. Without this
change (at least with my gcc-4.5.3 built using crosstool-ng), I see that
the sections do end up being included, but __bss_end__ gets set to the
same value as __bss_start.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agoarm: ks8695: use defined constants for UART
Yann Vernier [Fri, 5 Oct 2012 02:09:48 +0000 (02:09 +0000)]
arm: ks8695: use defined constants for UART

CONFIG_BAUDRATE and KS8695_UART_LINEC_WLEN8 used for UART registers

9 years agoOrigen: Add default clock settings for multimedia IPs
Annamalai Lakshmanan [Thu, 30 Aug 2012 20:33:58 +0000 (20:33 +0000)]
Origen: Add default clock settings for multimedia IPs

Added clock settings for MFC, FIMC, FB and G3D. They are clocked to
maximum respective frequencies as per datasheet.

Signed-off-by: Annamalai Lakshmanan <annamalai.lakshmanan@linaro.org>
Signed-off-by: Giridhar Maruthy <giridhar.maruthy@linaro.org>
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
9 years agoarm: arm925t: remove SX1 board
Albert ARIBAUD [Thu, 18 Oct 2012 10:15:45 +0000 (10:15 +0000)]
arm: arm925t: remove SX1 board

SX1 does not build properly by itself, is not built
as part of MAKEALL arm or MAKEALL -a arm, and is only
present in Makefile, not boards.cfg. As it also has no
entry in MAINTAINERS, it is orphan and non-functional.
Remove it.

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
9 years agoarm720: Remove CONFIG_ARM7_REVD
Marek Vasut [Wed, 3 Oct 2012 08:54:13 +0000 (08:54 +0000)]
arm720: Remove CONFIG_ARM7_REVD

This is a dead code, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
9 years agoarm720: Further clean up the arm720t directory
Marek Vasut [Wed, 3 Oct 2012 08:54:12 +0000 (08:54 +0000)]
arm720: Further clean up the arm720t directory

Clean up away old macros and such, so the file doesn't start piling
up cruft.

Signed-off-by: Marek Vasut <marex@denx.de>
clean

9 years agostdio: Remove the CLPS7111 serial driver
Marek Vasut [Wed, 3 Oct 2012 08:54:11 +0000 (08:54 +0000)]
stdio: Remove the CLPS7111 serial driver

This driver is no longer used, remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
9 years agoarm: Remove support for NETARM
Marek Vasut [Wed, 3 Oct 2012 08:54:10 +0000 (08:54 +0000)]
arm: Remove support for NETARM

This stuff has been rotting in the tree for a while now. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
9 years agoarm: Remove support for s3c4510
Marek Vasut [Wed, 3 Oct 2012 08:54:09 +0000 (08:54 +0000)]
arm: Remove support for s3c4510

This stuff has been rotting in the tree for a year now. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
9 years agoarm: Remove support for lpc2292
Marek Vasut [Wed, 3 Oct 2012 08:54:08 +0000 (08:54 +0000)]
arm: Remove support for lpc2292

This stuff has been rotting in the tree for a year now. Remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
9 years agoserial: remove calls to serial_assign()
Allen Martin [Thu, 25 Oct 2012 13:30:14 +0000 (13:30 +0000)]
serial: remove calls to serial_assign()

Remove calls to serial_assign() that are failing now that it returns a
proper error code.  This calls were not actually doing anything
because they passed the name of a stdio_dev when a serial_device name
is exptectd.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
9 years agoMerge remote-tracking branch 'u-boot-atmel/master'
Albert ARIBAUD [Fri, 26 Oct 2012 05:54:25 +0000 (07:54 +0200)]
Merge remote-tracking branch 'u-boot-atmel/master'

9 years agoMerge remote-tracking branch 'u-boot-ti/master'
Albert ARIBAUD [Fri, 26 Oct 2012 05:00:28 +0000 (07:00 +0200)]
Merge remote-tracking branch 'u-boot-ti/master'

9 years agoFAT: implement fat_set_blk_dev(), convert cmd_fat.c
Stephen Warren [Wed, 17 Oct 2012 06:44:59 +0000 (06:44 +0000)]
FAT: implement fat_set_blk_dev(), convert cmd_fat.c

This makes the FAT filesystem API more consistent with other block-based
filesystems. If in the future standard multi-filesystem commands such as
"ls" or "load" are implemented, having FAT work the same way as other
filesystems will be necessary.

Convert cmd_fat.c to the new API, so the code looks more like other files
implementing the same commands for other filesystems.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
9 years agoFAT: initialize all fields in cur_part_info, simplify init
Stephen Warren [Wed, 17 Oct 2012 06:44:58 +0000 (06:44 +0000)]
FAT: initialize all fields in cur_part_info, simplify init

cur_part_info.{name,type} are strings. So, we don't need to memset()
the entire thing, just put the NULL-termination in the first byte.

Add missing initialization of the bootable and uuid fields.

None of these fields are actually used by fat.c. However, since it
stores the entire disk_partition_t, we should make sure that all fields
are valid.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
9 years agoFAT: remove cur_part_nr
Stephen Warren [Wed, 17 Oct 2012 06:44:57 +0000 (06:44 +0000)]
FAT: remove cur_part_nr

A future patch will implement the more standard filesystem API
fat_set_blk_dev(). This API has no way to know which partition number
the partition represents. Equally, future DM rework will make the
concept of partition number harder to pass around.

So, simply remove cur_part_nr from fat.c; its only use is in a
diagnostic printf, and the context where it's printed should make it
obvious which partition is referred to anyway (since the partition ID
would come from the user command-line that caused it).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
9 years agodrivers/serial/serial_ns16550.c: sparse fixes
Kim Phillips [Tue, 16 Oct 2012 14:28:48 +0000 (14:28 +0000)]
drivers/serial/serial_ns16550.c: sparse fixes

serial_ns16550.c:222:1: warning: symbol 'eserial1_init' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_setbrg' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_getc' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_tstc' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_putc' was not declared. Should it be static?
serial_ns16550.c:222:1: warning: symbol 'eserial1_puts' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_init' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_setbrg' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_getc' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_tstc' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_putc' was not declared. Should it be static?
serial_ns16550.c:225:1: warning: symbol 'eserial2_puts' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_init' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_setbrg' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_getc' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_tstc' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_putc' was not declared. Should it be static?
serial_ns16550.c:228:1: warning: symbol 'eserial3_puts' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_init' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_setbrg' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_getc' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_tstc' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_putc' was not declared. Should it be static?
serial_ns16550.c:231:1: warning: symbol 'eserial4_puts' was not declared. Should it be static?

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agodrivers/i2c/fsl_i2c.c: sparse fix
Kim Phillips [Tue, 16 Oct 2012 14:28:43 +0000 (14:28 +0000)]
drivers/i2c/fsl_i2c.c: sparse fix

fsl_i2c.c:217:14: warning: symbol 'get_i2c_clock' was not declared. Should it be static?

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Heiko Schocher <hs@denx.de>
9 years agoam33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers
Peter Korsgaard [Thu, 18 Oct 2012 01:21:13 +0000 (01:21 +0000)]
am33xx/ddr_defs.h: rename DDR2/DDR3 defines to their actual part numbers

So other parts can be added.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx: support board specific ddr settings
Peter Korsgaard [Thu, 18 Oct 2012 01:21:12 +0000 (01:21 +0000)]
am33xx: support board specific ddr settings

Move the hardcoded ddr2/ddr3 settings for the ti boards to board code,
so other boards can use different types/timings.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make apply with rtc32k_enable() in the file]
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoam33xx: move generic parts of pinmux handling out from board/ti/am335x
Peter Korsgaard [Thu, 18 Oct 2012 01:21:11 +0000 (01:21 +0000)]
am33xx: move generic parts of pinmux handling out from board/ti/am335x

So they are available for other boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx/board: use cpu_mmc_init() for default mmc initialization
Peter Korsgaard [Thu, 18 Oct 2012 01:21:10 +0000 (01:21 +0000)]
am33xx/board: use cpu_mmc_init() for default mmc initialization

So platforms can override it with board_mmc_init() if needed.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx: move ti i2c baseboard header handling to board/ti/am335x/
Peter Korsgaard [Thu, 18 Oct 2012 01:21:09 +0000 (01:21 +0000)]
am33xx: move ti i2c baseboard header handling to board/ti/am335x/

The i2c header is specific to ti(-derived) boards, and not generic for all
am335x boards.

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
[trini: Make re-apply with rtc32k_enable() applied]
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoam33xx/board.c: make wdtimer/uart_base static
Peter Korsgaard [Thu, 18 Oct 2012 01:21:08 +0000 (01:21 +0000)]
am33xx/board.c: make wdtimer/uart_base static

Only used here (and uart_base only for SPL).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoam33xx: Add SPI SPL as an option
Tom Rini [Tue, 16 Oct 2012 13:06:07 +0000 (13:06 +0000)]
am33xx: Add SPI SPL as an option

Add the required config.mk logic for this SoC as well as the BOOT_DEVICE
define.  Finally, enable the options on the am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoomapimage: Add support for byteswapped SPI images
Tom Rini [Tue, 16 Oct 2012 13:06:06 +0000 (13:06 +0000)]
omapimage: Add support for byteswapped SPI images

Add MLO.byteswap as a target to spl/Makefile and un-guard the first MLO
rule so we don't have to duplicate it.

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoomap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED
Peter Korsgaard [Wed, 17 Oct 2012 09:20:46 +0000 (09:20 +0000)]
omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED

D0/D1 Swapped or not is a board property, not anything specific to
the am33xx SoC, so add a custom define for it.

At the same time correct the bit handling for the swapped mode
(DPE0 should be cleared and SI/DPE1 set).

Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
9 years agoOMAP3: add video support to the mcx board
Stefano Babic [Sat, 20 Oct 2012 23:56:07 +0000 (23:56 +0000)]
OMAP3: add video support to the mcx board

Add video support to the board with the display
focaltech etm070003dh6.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoVIDEO: add macro to set LCD size for DSS driver
Stefano Babic [Tue, 16 Oct 2012 04:07:05 +0000 (04:07 +0000)]
VIDEO: add macro to set LCD size for DSS driver

Signed-off-by: Stefano Babic <sbabic@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
9 years agoOMAP3: mcx: updated to new hardware revision
Stefano Babic [Tue, 16 Oct 2012 04:07:04 +0000 (04:07 +0000)]
OMAP3: mcx: updated to new hardware revision

Some GPIOs differ in the new revision board.
Previous revision are considered obsolete and
they will not anymore supported.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoOMAP3: updated pinmux and environment for new revision of mcx board
Stefano Babic [Tue, 16 Oct 2012 04:07:03 +0000 (04:07 +0000)]
OMAP3: updated pinmux and environment for new revision of mcx board

The mcx board was slightly modified and the pinmux must be updated.
There is no need to support the old board, that becomes obsolete.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoOMAP3: mt_ventoux: power on USB at startup
Stefano Babic [Tue, 16 Oct 2012 04:02:20 +0000 (04:02 +0000)]
OMAP3: mt_ventoux: power on USB at startup

Updated revision of the board uses GPIOs to activate
the USB ports.

Signed-off-by: Stefano Babic <sbabic@denx.de>
9 years agoam335x: Enable RTC 32K OSC clock
Vaibhav Hiremath [Thu, 8 Mar 2012 11:45:47 +0000 (17:15 +0530)]
am335x: Enable RTC 32K OSC clock

In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume.  In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain.  Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.

So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoColdFire: Add Freescale MCF54418TWR ColdFire development board support
Alison Wang [Thu, 18 Oct 2012 19:25:52 +0000 (19:25 +0000)]
ColdFire: Add Freescale MCF54418TWR ColdFire development board support

Add Freescale MCF54418TWR ColdFire development board support.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
9 years agoColdFire: Add MCF5441x CPU support
Alison Wang [Thu, 18 Oct 2012 19:25:51 +0000 (19:25 +0000)]
ColdFire: Add MCF5441x CPU support

Add MCF5441x CPU support.

The MCF5441x devices are a family of highly-integrated 32-bit
microprocessors based on the Version 4m ColdFire microarchitecture,
comprising of the V4 integer core, memory management unit(MMU) and
enchanced multiply-accumulate unit(EMAC).

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
9 years agoColdFire: Fix unused variable in cpu_init.c
Alison Wang [Sun, 21 Oct 2012 21:27:48 +0000 (21:27 +0000)]
ColdFire: Fix unused variable in cpu_init.c

Fix the following build warnings in cpu_init.c:

cpu_init.c: In function 'cpu_init_f':
cpu_init.c:47:9: warning: unused variable 'pll'
cpu_init.c:46:10: warning: unused variable 'fbcs'
cpu_init.c:44:10: warning: unused variable 'scm1'

Signed-off-by: Alison Wang <b18965@freescale.com>
9 years agokm83xx: add kmvect1 board
Gerlando Falauto [Wed, 10 Oct 2012 22:13:10 +0000 (22:13 +0000)]
km83xx: add kmvect1 board

Add support for the new kmvect1 board powered by the mpc8309 processor.
As this board is very similar to the existing suvd3, instead of adding a
new config header file, just add a new config option to suvd3.h

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agokm83xx: add common support for km8309 boards
Gerlando Falauto [Wed, 10 Oct 2012 22:13:09 +0000 (22:13 +0000)]
km83xx: add common support for km8309 boards

Add support for Keymile boards based on mpc8309
(it would be only kmvect1 for now)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
[#elseif -> #if to allow kmcoge5ne and kmeter1 to build successfully]
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agompc83xx: add support for mpc8309
Gerlando Falauto [Wed, 10 Oct 2012 22:13:08 +0000 (22:13 +0000)]
mpc83xx: add support for mpc8309

This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocleanup: introduce CONFIG_MPC830x
Gerlando Falauto [Wed, 10 Oct 2012 22:13:07 +0000 (22:13 +0000)]
cleanup: introduce CONFIG_MPC830x

Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x
Gerlando Falauto [Wed, 10 Oct 2012 22:13:06 +0000 (22:13 +0000)]
cleanup: use CONFIG_QE instead of CONFIG_MPC8360 || CONFIG_MPC832x

simplify #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
for qe variables
with #if defined(CONFIG_QE)

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocosmetic: suvd3: align #defines
Gerlando Falauto [Wed, 10 Oct 2012 22:13:05 +0000 (22:13 +0000)]
cosmetic: suvd3: align #defines

Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
9 years agocm-t35: clean unused defines from config
Igor Grinberg [Sun, 7 Oct 2012 01:17:34 +0000 (01:17 +0000)]
cm-t35: clean unused defines from config

Neither cm-t35, nor cm-t3730 is using OneNAND or flash.
Remove the related defines from config file.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
9 years agoconfigs: Fix usage of mmc rescan
Andrew Bradford [Mon, 1 Oct 2012 05:06:52 +0000 (05:06 +0000)]
configs: Fix usage of mmc rescan

Fix usage of 'mmc rescan' by many configs.  Proper use is
'mmc dev ${mmcdev}; mmc rescan' to set the mmc device and then rescan
the device.  'mmc rescan' itself does not take any arguments.

Signed-off-by: Andrew Bradford <andrew@bradfordembedded.com>
9 years agoam33xx: Enable DDR3 for DDR3 version of beaglebone
Joel A Fernandes [Tue, 25 Sep 2012 06:49:47 +0000 (06:49 +0000)]
am33xx: Enable DDR3 for DDR3 version of beaglebone

DDR3 support is tested and working with beaglebone hardware. Include a check
for this board type and configure DDR3. The timings and other configuration
match EVM SK.

Signed-off-by: Joel A Fernandes <joelagnel@ti.com>
Acked-by: Jason Kridner <jdk@ti.com>
9 years agoUSB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY
Pankaj Bharadiya [Thu, 13 Sep 2012 09:38:16 +0000 (09:38 +0000)]
USB: musb_udc: Make musb_peri_rx_ep check for MUSB_RXCSR_RXPKTRDY

The endpoint rx count register value will be zero if it is read before
receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set.

Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before
reading endpoint rx count register. Proceed with rx count read and
FIFO read only if RXPKTRDY bit is set.

Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fdt
Tom Rini [Tue, 23 Oct 2012 02:54:48 +0000 (19:54 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-fdt

9 years agoMerge branch 'next'
Gerald Van Baren [Tue, 23 Oct 2012 00:42:09 +0000 (20:42 -0400)]
Merge branch 'next'

9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Tom Rini [Mon, 22 Oct 2012 23:54:38 +0000 (16:54 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-mpc85xx

9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mmc
Tom Rini [Mon, 22 Oct 2012 23:53:19 +0000 (16:53 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-mmc

9 years ago85xx: Protect timeout_save variable with ifdefs
Andy Fleming [Mon, 22 Oct 2012 22:28:18 +0000 (17:28 -0500)]
85xx: Protect timeout_save variable with ifdefs

The timeout_save variable was only used by the DDR111_134
erratum code. It was being set, but never used. Newer compilers
will actually complain about this.

Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/boot: Change the compile macro for SRIO & PCIE boot master module
Liu Gang [Sun, 14 Oct 2012 20:55:17 +0000 (20:55 +0000)]
powerpc/boot: Change the compile macro for SRIO & PCIE boot master module

Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agophylib: Enable SMSC LAN87xx PHY support
Mingkai Hu [Fri, 12 Oct 2012 02:34:15 +0000 (02:34 +0000)]
phylib: Enable SMSC LAN87xx PHY support

LAN8720 PHY is used on Freescale C2X0QDS board.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/espi: remove write command length check
Shaohui Xie [Thu, 11 Oct 2012 20:31:46 +0000 (20:31 +0000)]
powerpc/espi: remove write command length check

Current espi controller driver assumes the command length of write command is
not equal to '1', it was made based on SPANSION SPI flash, but some SPI flash
driver such as SST does use write command length as '1', so write command on
SST SPI flash will not work. And the length check for write command is not
necessary for SPANSION, though it's harmless for SPANSION, it will stop write
operation on flashes like SST, so we remove the check.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/fm: fix TBI PHY address settings
shaohui xie [Thu, 11 Oct 2012 20:25:36 +0000 (20:25 +0000)]
powerpc/fm: fix TBI PHY address settings

TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is wrong in case of FM2, which has a different
mac base.

struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
/* Assign a Physical address to the TBI */
out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopoweprc/85xx: add QMan frequency info and fdt fixup.
Haiying Wang [Thu, 11 Oct 2012 07:13:39 +0000 (07:13 +0000)]
poweprc/85xx: add QMan frequency info and fdt fixup.

Starting from QMan3.0, the QMan clock cycle needs be exposed so that the kernel
driver can use it to calculate the shaper prescaler and rate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agompc85xx/portals: Add qman and bman ip_cfg field into portal info
Haiying Wang [Thu, 11 Oct 2012 07:13:38 +0000 (07:13 +0000)]
mpc85xx/portals: Add qman and bman ip_cfg field into portal info

Because QMan3.0 and BMan2.1 used ip_cfg in ip_rev_2 register to differ the
total portal number, buffer pool number etc, we can use this info to limit
those resources in kernel driver.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/t4qds: Add T4QDS board
York Sun [Thu, 11 Oct 2012 07:13:37 +0000 (07:13 +0000)]
powerpc/t4qds: Add T4QDS board

The T4240QDS is a high-performance computing evaluation, development and
test platform supporting the T4240 QorIQ Power Architecture™ processor.

SERDES Connections
  32 lanes grouped into four 8-lane banks
  Two “front side” banks dedicated to Ethernet
  Two “back side” banks dedicated to other protocols
DDR Controllers
  Three independant 64-bit DDR3 controllers
  Supports rates up to 2133 MHz data-rate
  Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
QIXIS System Logic FPGA

Each DDR controller has two DIMM slots. The first slot of each controller
has up to 4 chip selects to support single-, dual- and quad-rank DIMMs.
The second slot has only 2 chip selects to support single- and dual-rank
DIMMs. At any given time, up to total 4 chip selects can be used.

Detail information can be found in doc/README.t4qds

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
York Sun [Mon, 8 Oct 2012 07:44:31 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform

New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1
York Sun [Mon, 8 Oct 2012 07:44:30 +0000 (07:44 +0000)]
powerpc/mpc85xx: Rewrite spin table to comply with ePAPR v1.1

Move spin table to cached memory to comply with ePAPR v1.1.
Load R3 with 64-bit value if CONFIG_SYS_PPC64 is defined.

'M' bit is set for DDR TLB to maintain cache coherence.

See details in doc/README.mpc85xx-spin-table.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Remove R6 from spin table
York Sun [Mon, 8 Oct 2012 07:44:29 +0000 (07:44 +0000)]
powerpc/mpc85xx: Remove R6 from spin table

R6 was in ePAPR draft version but was dropped in official spec.
Removing it to comply.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Fix DDR SPD failed message
York Sun [Mon, 8 Oct 2012 07:44:28 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Fix DDR SPD failed message

Since empty DIMM slot is allowed on other than the first slot, remove the
error message if SPD is not found in this case.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Add auto select bank interleaving mode
York Sun [Mon, 8 Oct 2012 07:44:27 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Add auto select bank interleaving mode

Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or
cs0_cs1 interleaving, or non-interleaving if not available.

Fix the message of interleaving disabled if controller interleaving
is enabled but DIMMs don't support it.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add workaround for DDR erratum A004934
York Sun [Mon, 8 Oct 2012 07:44:26 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add workaround for DDR erratum A004934

After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: software workaround for DDR erratum A-004468
York Sun [Mon, 8 Oct 2012 07:44:25 +0000 (07:44 +0000)]
powerpc/mpc85xx: software workaround for DDR erratum A-004468

Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT
York Sun [Mon, 8 Oct 2012 07:44:24 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT

When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation
York Sun [Mon, 8 Oct 2012 07:44:23 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Fix DDR driver handling quad-rank DIMMs and address calculation

Fix handling quad-rank DIMMs in a system with two DIMM slots and first
slot supports both dual-rank DIMM and quad-rank DIMM.

For systems with quad-rank DIMM and double dual-rank DIMMs, cs_config
registers need to be enabled to maintain proper ODT operation. The
inactive CS should have bnds registers cleared.

Fix the turnaround timing for systems with all chip-selects enabled. This
wasn't an issue before because DDR was running lower than 1600MT/s with
this interleaving mode.

Fix DDR address calculation. It wasn't an issue until we have multiple
controllers with each more than 4GB and interleaving is disabled.

It also fixes the message of DDR: 2 GiB (DDR3, 64-bit, CL=0.5, ECC off)
when debugging DDR and first DDR controller is disabled. With the fix,
the first enabled controller information will be displayed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: Update DDR registers
York Sun [Mon, 8 Oct 2012 07:44:22 +0000 (07:44 +0000)]
powerpc/mpc8xxx: Update DDR registers

DDRC ver 4.7 adds DDR_SLOW bit in sdram_cfg_2 register. This bit needs to be
set for speed lower than 1250MT/s.

CDR1 and CDR2 are control driver registers. ODT termination valueis for
IOs are defined. Starting from DDRC 4.7, the decoding of ODT for IOs is
000 -> Termsel off
001 -> 120 Ohm
010 -> 180 Ohm
011 -> 75 Ohm
100 -> 110 Ohm
101 -> 60 Ohm
110 -> 70 Ohm
111 -> 47 Ohm

Add two write leveling registers. Each QDS now has its own write leveling
start value. In case of zero value, the value of QDS0 will be used. These
values are board-specific and are set in board files.

Extend DDR register timing_cfg_1 to have 4 bits for each field.

DDR control driver registers and write leveling registers are added to
interactive debugging for easy access.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agofm/mEMAC: add mEMAC frame work
Roy Zang [Mon, 8 Oct 2012 07:44:21 +0000 (07:44 +0000)]
fm/mEMAC: add mEMAC frame work

The multirate ethernet media access controller (mEMAC) interfaces to
10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII
interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add B4860 and variant SoCs
York Sun [Mon, 8 Oct 2012 07:44:20 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add B4860 and variant SoCs

Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):

Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
    clusters-each core runs up to 1.2 GHz, with an architecture highly
    optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
    cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
    each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
    including Turbo or Viterbi decoding, Turbo encoding and rate matching,
    MIMO MMSE equalization scheme, matrix operations, CRC insertion and
    check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
    and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
    the e6500 cores, SC3900 FVP cores, memories and external interfaces.
    CoreNet fabric interconnect runs at 667 MHz and supports coherent and
    non-coherent out of order transactions with prioritization and
    bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
  Frame Manager (FMan), which supports in-line packet parsing and general
    classification to enable policing and QoS-based packet distribution
  Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
    of queue management, task management, load distribution, flow ordering,
    buffer management, and allocation tasks from the cores
  Security engine (SEC 5.3)-crypto-acceleration for protocols such as
    IPsec, SSL, and 802.16
  RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
    outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
    bandwidth saving and high utilization of processor elements. The
    9856-Kbyte internal memory space includes the following:
  32 Kbyte L1 ICache per e6500/SC3900 core
  32 Kbyte L1 DCache per e6500/SC3900 core
  2048 Kbyte unified L2 cache for each SC3900 FVP cluster
  2048 Kbyte unified L2 cache for the e6500 cluster
  Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
  Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
    of up to 8 lanes
  Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
    less antenna connection
  Two 10-Gbit Ethernet controllers (10GEC)
  Six 1G/2.5-Gbit Ethernet controllers for network communications
  PCI Express controller
  Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add T4240 SoC
York Sun [Mon, 8 Oct 2012 07:44:19 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add T4240 SoC

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add T4 device definitions
Andy Fleming [Mon, 8 Oct 2012 07:44:18 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add T4 device definitions

The T4 has added devices to previous corenet implementations:

* SEC has 3 more DECO units
* New PMAN device
* New DCE device

This doesn't add full support for the new devices. Just some
preliminary support.

Move PMAN LIODN to upper half of register

Despite having only one LIODN, the PMAN LIODN is stored in the
upper half of the register. Re-use the 2-LIODN code and just
set the LIODN as if the second one is 0. This results in the
actual LIODN being written to the upper half of the register.

Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoboard/freescale/common: VSC3316/VSC3308 initialization code
Shaveta Leekha [Mon, 8 Oct 2012 07:44:17 +0000 (07:44 +0000)]
board/freescale/common: VSC3316/VSC3308 initialization code

Add code for configuring VSC3316/3308 crosspoint switches
Add README to understand the APIs

   - VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch
     capable of data rates upto 11.5Gbps. VSC3316 has 16 input and 16
     output ports whereas VSC3308 has 8 input and 8 output ports.
     Programming of these devices are performed by two-wire or four-wire
     serial interface.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet2: fix mismatch DDR sync bit from RCW
York Sun [Mon, 8 Oct 2012 07:44:16 +0000 (07:44 +0000)]
powerpc/corenet2: fix mismatch DDR sync bit from RCW

Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet2: Add SerDes for corenet2
York Sun [Mon, 8 Oct 2012 07:44:15 +0000 (07:44 +0000)]
powerpc/corenet2: Add SerDes for corenet2

Create new files to handle 2nd generation Chassis as the registers are
organized differently.

 - Add SerDes protocol parsing and detection
 - Add support of 4 SerDes
 - Add CPRI protocol in fsl_serdes.h
The Common Public Radio Interface (CPRI) is publicly available
specification that standardizes the protocol interface between the
radio equipment control (REC) and the radio equipment (RE) in wireless
basestations. This allows interoperability of equipment from different
vendors,and preserves the software investment made by wireless service
providers.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2
York Sun [Mon, 8 Oct 2012 07:44:14 +0000 (07:44 +0000)]
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2

Corenet 2nd generation Chassis has different RCW and registers for SerDes.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>