karo-tx-uboot.git
9 years agox86: Provide tick counter and frequency reference for Intel core architecture
Vadim Bendebury [Mon, 3 Dec 2012 13:59:20 +0000 (13:59 +0000)]
x86: Provide tick counter and frequency reference for Intel core architecture

Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.

Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Issue SMI to finalize Coreboot in final stage
Duncan Laurie [Sat, 3 Nov 2012 11:41:35 +0000 (11:41 +0000)]
x86: Issue SMI to finalize Coreboot in final stage

This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Fix MTRR clear to detect which MTRR to use
Duncan Laurie [Mon, 3 Dec 2012 13:59:00 +0000 (13:59 +0000)]
x86: Fix MTRR clear to detect which MTRR to use

Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Emit port 80 post codes in show_boot_progress()
Stefan Reinauer [Mon, 3 Dec 2012 13:58:12 +0000 (13:58 +0000)]
x86: Emit port 80 post codes in show_boot_progress()

This helps us monitor boot progress and determine where U-Boot dies if
there are any problems.

Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: fdt: Create basic .dtsi file for coreboot
Simon Glass [Mon, 3 Dec 2012 13:56:51 +0000 (13:56 +0000)]
x86: fdt: Create basic .dtsi file for coreboot

This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly
Gabe Black [Sat, 3 Nov 2012 11:41:31 +0000 (11:41 +0000)]
x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly

We will use coreboot.dtsi as our fdt include file.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add support for CONFIG_OF_CONTROL
Gabe Black [Sat, 3 Nov 2012 11:41:30 +0000 (11:41 +0000)]
x86: Add support for CONFIG_OF_CONTROL

Allow a device tree to be provided through the standard mechanisms.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading
Stefan Reinauer [Sat, 3 Nov 2012 11:41:29 +0000 (11:41 +0000)]
x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading

This option delays loading of the environment until later, so that only the
default environment will be available to U-Boot.

This can address the security risk of untrusted data being used during boot.

When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a
run-time way of enabling loadinlg of the environment. Add this to the
fdt as /config/delay-environment.

Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
9 years agox86: Add back cold- and warm-boot flags
Gabe Black [Sat, 3 Nov 2012 11:41:28 +0000 (11:41 +0000)]
x86: Add back cold- and warm-boot flags

These were removed, but actually are useful.

Cold means that we started from a reset/power on.
Warm means that we started from another U-Boot.

We determine whether u-boot on x86 was warm or cold booted (really if
it started at the beginning of the text segment or at the ELF entry point).
We plumb the result through to the global data structure.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Override calculate_relocation_address to use the e820 map
Gabe Black [Mon, 3 Dec 2012 14:26:08 +0000 (14:26 +0000)]
x86: Override calculate_relocation_address to use the e820 map

Because calculate_relocation_address now uses the e820 map, it will be able
to avoid addresses over 32 bits and regions that are at high addresses but
not big enough for U-Boot. It also means we can remove the hack which
limitted U-Boot's idea of the size of memory to less than 4GB.

Also take into account the space needed for the heap and stack, so we avoid
picking a very small region those areas might overlap with something it
shouldn't.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Make calculate_relocation_address an overridable function
Gabe Black [Sat, 3 Nov 2012 11:41:26 +0000 (11:41 +0000)]
x86: Make calculate_relocation_address an overridable function

Different systems may have different mechanisms for picking a suitable place
to relocate U-Boot to.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Make the upper bound on relocated symbols closed instead of open
Gabe Black [Sat, 3 Nov 2012 11:41:25 +0000 (11:41 +0000)]
x86: Make the upper bound on relocated symbols closed instead of open

This seems to be a bug.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Reorder x86's post relocation memory layout
Gabe Black [Sat, 3 Nov 2012 11:41:24 +0000 (11:41 +0000)]
x86: Reorder x86's post relocation memory layout

This changes the layout in decreasing addresses from:

1. Stack
2. Sections in the image
3. Heap

to

1. Sections in the image
2. Heap
3. Stack

This allows the stack to grow significantly more since it isn't constrained by
the other u-boot areas. More importantly, the generic memory wipe code assumes
that the stack is the lowest addressed area used by the main part of u-boot.
In the original layout, that means that u-boot tramples all over itself. In
the new layout, it works.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Initialise SPI if enabled
Gabe Black [Sat, 3 Nov 2012 11:41:23 +0000 (11:41 +0000)]
x86: Initialise SPI if enabled

If we have SPI support, make sure that we init it.

Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vic Yang <victoryang@chromium.org>
9 years agox86: Implement arch_phys_memset so that it can wipe memory above 4GB
Gabe Black [Tue, 23 Oct 2012 18:04:46 +0000 (18:04 +0000)]
x86: Implement arch_phys_memset so that it can wipe memory above 4GB

Implement arch_phys_memset so that it can set memory at physical addresses
above 4GB using PAE paging. Because there are only 5 page tables in PAE mode,
1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The
tables must be 4K page aligned and are declared that way, and because U-Boot
starts as 4K aligned and the relocation code relocates it to a 4K aligned
address, the tables work as intended.

While paging is turned on, all 4GB are identity mapped except for one 2MB
page which is used as the window into high memory. This way, U-Boot will
continue to work as expected when running code that expects to access memory
freely, but the code can still get at high memory through its window.

The window is put at 2MB so that it's 2MB page aligned, low in memory to be
out of the way of things U-Boot is likely to care about, and above the lowest
1MB where lots of random things live.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoIntroduce arch_phys_memset which works like memset but on physical memory
Gabe Black [Sun, 2 Dec 2012 04:55:18 +0000 (04:55 +0000)]
Introduce arch_phys_memset which works like memset but on physical memory

The default implementation of this function is just memset, but other
implementations will be needed when physical memory isn't accessible by
U-Boot using normal addressing mechanisms.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Increase the size of the phys_size_t and phys_addr_t types
Gabe Black [Tue, 23 Oct 2012 18:04:44 +0000 (18:04 +0000)]
x86: Increase the size of the phys_size_t and phys_addr_t types

These types should be 64 bits long to reflect the fact that physical
addresses and the size of physical areas of memory are more than 32 bits
long.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Fix off-by-one error in do_elf_reloc_fixups()
Duncan Laurie [Tue, 23 Oct 2012 18:04:43 +0000 (18:04 +0000)]
x86: Fix off-by-one error in do_elf_reloc_fixups()

The use of post-increment with a do-while loop results in
the loop going one step too far when handling relocation fixups.

In about 1/100 cases this would cause it to hang.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Ignore memory >4GB when parsing Coreboot tables
Duncan Laurie [Tue, 23 Oct 2012 18:04:42 +0000 (18:04 +0000)]
x86: Ignore memory >4GB when parsing Coreboot tables

U-boot is unable to actually use that memory and it can
cause problems with relocation if it tries to.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Enable CONFIG_CMD_ZBOOT for coreboot
Simon Glass [Sun, 2 Dec 2012 04:49:55 +0000 (04:49 +0000)]
x86: Enable CONFIG_CMD_ZBOOT for coreboot

Enable this option to support booting a zImage.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Fix indirect jmp warning in zimage.c
Simon Glass [Tue, 23 Oct 2012 18:04:40 +0000 (18:04 +0000)]
x86: Fix indirect jmp warning in zimage.c

This fixes the following warning:

zimage.c:312: Warning: indirect jmp without `*'

Also fixed these warnings to keep checkpatch quiet:

warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline
warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Clean up MTRR 7 right before jumping to the kernel
Stefan Reinauer [Sun, 2 Dec 2012 04:49:53 +0000 (04:49 +0000)]
x86: Clean up MTRR 7 right before jumping to the kernel

This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Import MSR/MTRR code from Linux
Graeme Russ [Sun, 2 Dec 2012 04:55:11 +0000 (04:55 +0000)]
x86: Import MSR/MTRR code from Linux

Imported from Linux 3.1 with a few modifications to suit U-Boot

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Provide a function to clean up just before booting a zimage
Stefan Reinauer [Tue, 23 Oct 2012 18:04:37 +0000 (18:04 +0000)]
x86: Provide a function to clean up just before booting a zimage

This function can be used by boards which want to do some clean-up
before booting a zImage.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add basic cache operations
Stefan Reinauer [Sun, 2 Dec 2012 04:49:50 +0000 (04:49 +0000)]
x86: Add basic cache operations

Add functions to enable/disable the data cache.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Fill in the dram info using the e820 map on coreboot/x86
Gabe Black [Tue, 23 Oct 2012 18:04:35 +0000 (18:04 +0000)]
x86: Fill in the dram info using the e820 map on coreboot/x86

This way when that dram "banks" are displayed, there's some useful information
there. The number of "banks" we claim to have needs to be adjusted so that it
covers the number of RAM e820 regions we expect to have/care about.

This needs to be done after "RAM" initialization even though we always run
from RAM. The bd pointer in the global data structure doesn't automatically
point to anything, and it isn't set up until "RAM" is available since, I
assume, it would take too much space in the very constrained pre-RAM
environment.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a CBMEM timestamp generated right before the kernel startup.
Vadim Bendebury [Tue, 23 Oct 2012 18:04:34 +0000 (18:04 +0000)]
x86: Add a CBMEM timestamp generated right before the kernel startup.

To maintain the initialization state of the timestamp facility, thesq
pointer to the CBMEM section containing the timestamp table should be
kept in the .data section (so that it is maintained across u-boot
relocation).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Enable coreboot timestamp facility support in u-boot.
Vadim Bendebury [Tue, 23 Oct 2012 18:04:33 +0000 (18:04 +0000)]
x86: Enable coreboot timestamp facility support in u-boot.

This change turns on the code which allows u-boot to add
timestamps to the timestamp table created by coreboot.

Since u-boot does not use the tsc_t like structure to represent
HW counter readings, this structure is being replaced by 64 bit
integer.

The timestamp_init() function is now initializing the base timer
value used by u-boot to calculate the HW counter increments.

Timestamp facility is initialized as soon as the timestamp table
pointer is found in the coreboot table. The u-boot generated
timer events' ID will start at 1000 to clearly separate u-boot
events from coreboot events in the timer trace.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add function to read time stamp counter
Vadim Bendebury [Tue, 23 Oct 2012 18:04:32 +0000 (18:04 +0000)]
x86: Add function to read time stamp counter

Put this function in the u-boot-x86.h header file. We could instead create
timer.h perhaps.

We support setting a base time, and reading the time relative to this base.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: gpio: Add additional GPIO banks to the ICH6 driver
Bill Richardson [Sat, 20 Oct 2012 11:44:36 +0000 (11:44 +0000)]
x86: gpio: Add additional GPIO banks to the ICH6 driver

We can generally trust the ICH to have GPIO Bank 0 (the first 32 pins) in the
same place across all versions. This change adds two more banks, for up to
96 GPIOS.

BUT:
- Not all chipsets have the same number of GPIOs
- Not all chipsets have the same number of GPIO banks
- Not all chipsets put the additional banks at the same offset from GPIOBASE
- There so many chipset variants that it's pretty much impossible to support
  them all, or even keep track of the new ones.

So, although this adds suppport for the additional banks that seem to work
for the particular variants of CougarPoint Mobile chipsets that we've tried,
there's no chance it will support everything Intel produces. Good luck.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Enable ICH6 GPIO controller for coreboot
Simon Glass [Sun, 2 Dec 2012 03:44:44 +0000 (03:44 +0000)]
x86: Enable ICH6 GPIO controller for coreboot

Coreboot uses this controller to implement GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: gpio: Add GPIO driver for Intel ICH6 and later.
Bill Richardson [Sat, 20 Oct 2012 11:44:34 +0000 (11:44 +0000)]
x86: gpio: Add GPIO driver for Intel ICH6 and later.

Implement <asm-generic/gpio.h> functions for Intel ICH6 and later.
Only GPIOs 0-31 are handled by this code.

Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years ago4xx: Fix PCI memory mapping on CPCI405 boards
Matthias Fuchs [Fri, 2 Nov 2012 13:30:34 +0000 (14:30 +0100)]
4xx: Fix PCI memory mapping on CPCI405 boards

This patch fixes an issue with overlapping PCI regions
on boards with more than 64MB RAM.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agoMakefile: Add target for combined spl/u-boot.bin & u-boot.img
Stefan Roese [Fri, 24 Aug 2012 15:36:53 +0000 (17:36 +0200)]
Makefile: Add target for combined spl/u-boot.bin & u-boot.img

This new make target "u-boot-img.bin" consists of the U-Boot
SPL image with the real, full-blown U-Boot image directly
attached to it. The full-blown U-Boot image has the mkimage
header included, with its load-address and entry-point.

This will be used by the upcoming a3m071 MPC5200 board port.

Signed-off-by: Stefan Roese <sr@denx.de>
9 years agoMakefile: Add possibility to set entry-point for u-boot.img
Stefan Roese [Thu, 16 Aug 2012 15:54:52 +0000 (17:54 +0200)]
Makefile: Add possibility to set entry-point for u-boot.img

This patch enabled boards using the SPL framework to set
an entry point in the U-Boot mkimage image "u-boot.img".
Until now the entry point in the header has been set to 0.
By setting CONFIG_SYS_UBOOT_START in the board header, boards
can override this default location.

This will be used by the upcoming a3m071 MPC5200 board port.

Signed-off-by: Stefan Roese <sr@denx.de>
9 years agompc5200: Add a3m071 board support
Stefan Roese [Tue, 14 Aug 2012 13:04:19 +0000 (15:04 +0200)]
mpc5200: Add a3m071 board support

This patch adds support for the a3m071 board based on the
MPC5200.

Signed-off-by: Stefan Roese <sr@denx.de>
9 years agompc5200: Add SPL support
Stefan Roese [Thu, 16 Aug 2012 15:53:18 +0000 (17:53 +0200)]
mpc5200: Add SPL support

This patch adds SPL booting support (NOR flash) for the
MPC5200 platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
9 years agoenv: Enable getenv_f() for SPL_BUILD
Stefan Roese [Wed, 26 Sep 2012 11:01:00 +0000 (13:01 +0200)]
env: Enable getenv_f() for SPL_BUILD

With this patch, getenv_f() can be included easily into the SPL
binary. With this, SPL boards can now use getenv_f() to read
environment variables (e.g. to detect if the OS or U-Boot shall
be executed).

In the approach this is done for env stored in NOR flash, as this
will be used by an upcoming MPC5200 board port.

Signed-off-by: Stefan Roese <sr@denx.de>
9 years agoSPL: Port SPL framework to powerpc
Stefan Roese [Thu, 23 Aug 2012 06:34:21 +0000 (08:34 +0200)]
SPL: Port SPL framework to powerpc

This patch enables the SPL framework to be used on powerpc platforms
and not only ARM.

timer_init() does not exist on PPC systems. The timer (decrementer) is
initialized and enabled in interrupt_init() here. And currently
interrupt_init() is called after relocation to SDRAM. Since the only
powerpc SPL implementation (a3m071) doesn't need a timer, let's remove
this timer_init() call for PPC systems.

Signed-off-by: Stefan Roese <sr@denx.de>
9 years agopowerpc: Extract EPAPR_MAGIC constants into processor.h
Stefan Roese [Thu, 23 Aug 2012 07:25:37 +0000 (09:25 +0200)]
powerpc: Extract EPAPR_MAGIC constants into processor.h

By extracting these defines into a header, they can be re-used by other
C sources as well. This will be done by the SPL framework OS boot
support.

Signed-off-by: Stefan Roese <sr@denx.de>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Mon, 3 Dec 2012 13:47:05 +0000 (06:47 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-x86

9 years agox86: Don't spam POST80 codes with slow IO functions
Stefan Reinauer [Sat, 20 Oct 2012 12:33:16 +0000 (12:33 +0000)]
x86: Don't spam POST80 codes with slow IO functions

This patch prevents u-boot from "spamming" random progress codes on
a port 80 "post card".
The previous version of this patch just removed the delays in the "slow"
IO functions, as they do not need to be slow, however, this patch is
less intrusive.

It uses another unused port that is often used by BIOSes (and the Linux
Kernel) for small delay timing purposes.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Define CONFIG_SYS_VSNPRINTF for coreboot
Simon Glass [Sat, 20 Oct 2012 12:33:15 +0000 (12:33 +0000)]
x86: Define CONFIG_SYS_VSNPRINTF for coreboot

This option protects the printf() functions from overflow.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Fix typo in pcat_timer.c
Stefan Reinauer [Sat, 20 Oct 2012 12:33:14 +0000 (12:33 +0000)]
x86: Fix typo in pcat_timer.c

Fix a small comment typo.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Include types.h explicitly in the i386 version of io.h
Gabe Black [Sat, 20 Oct 2012 12:33:13 +0000 (12:33 +0000)]
x86: Include types.h explicitly in the i386 version of io.h

The i386 version of io.h depends on the phys_addr_t type which is defined in
types.h. It wasn't including that explicitly, and was working presumably
because the other files including it had already included types.h themselves
directly or indirectly. This change fixes that.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a dummy implementation for timer_get_us
Gabe Black [Sat, 20 Oct 2012 12:33:11 +0000 (12:33 +0000)]
x86: Add a dummy implementation for timer_get_us

The microsecond timer is not currently implemented, but add a dummy
implementation for now.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a default implementation for cleanup_before_linux()
Gabe Black [Sat, 20 Oct 2012 12:33:10 +0000 (12:33 +0000)]
x86: Add a default implementation for cleanup_before_linux()

This function provides an opportunity for some last minute cleanup and
reconfiguration before control is handed over to Linux. It's possible this
may need to do something in the future, but for now it's left empty. It's set
up as a weak symbol so it can be overridden if necessary on a case by case
basis.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a minimal device tree for alex x86
Gabe Black [Sat, 20 Oct 2012 12:33:09 +0000 (12:33 +0000)]
x86: Add a minimal device tree for alex x86

The device tree now includes the necessary console configuration
information.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add an fdt pointer to the global data structure
Gabe Black [Sat, 20 Oct 2012 12:33:08 +0000 (12:33 +0000)]
x86: Add an fdt pointer to the global data structure

This change adds a pointer to the global data structure in x86 to point to
the device tree. This mirrors an identical pointer in ARM.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: video: Add coreboot framebuffer support
Stefan Reinauer [Fri, 30 Nov 2012 06:32:33 +0000 (06:32 +0000)]
x86: video: Add coreboot framebuffer support

Add a basic driver for the coreboot framebuffer.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove coreboot start16 code
Simon Glass [Sat, 20 Oct 2012 12:33:06 +0000 (12:33 +0000)]
x86: Remove coreboot start16 code

This file is no longer needed for coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Allow compiling out realmode/bios code
Gabe Black [Thu, 29 Nov 2012 16:23:41 +0000 (16:23 +0000)]
x86: Allow compiling out realmode/bios code

We don't want this for coreboot, so provide a way of compiling it out.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Select stdio devices for coreboot
Simon Glass [Thu, 29 Nov 2012 09:58:58 +0000 (09:58 +0000)]
x86: Select stdio devices for coreboot

We want to support VGA, serial, USB keyboard and the Coreboot memory
console buffer.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add console command to display CBMEM console buffer
Vadim Bendebury [Fri, 12 Oct 2012 18:48:48 +0000 (18:48 +0000)]
x86: Add console command to display CBMEM console buffer

This command is useful to allow to observe messages generated by
coreboot and u-boot until present. In particular it is handy when
u-boot is instrumented to fall through into console mode on startup
errors.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add CBMEM console driver for coreboot
Vadim Bendebury [Fri, 12 Oct 2012 18:48:47 +0000 (18:48 +0000)]
x86: Add CBMEM console driver for coreboot

This patch builds upon the recently introduced CBMEM console
feature of coreboot.

CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.

Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.

>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:

vvvvvvvvvvvvvvvvv
SCSI:  AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
...
Magic signature found
Kernel command line: "cros_secure  quiet loglevel=1 console=tty2...
^^^^^^^^^^^^^^^^^

Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Decode additional coreboot sysinfo tags
Simon Glass [Fri, 12 Oct 2012 18:48:46 +0000 (18:48 +0000)]
x86: coreboot: Decode additional coreboot sysinfo tags

Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Drop sysinfo.c
Stefan Reinauer [Fri, 12 Oct 2012 18:48:45 +0000 (18:48 +0000)]
x86: coreboot: Drop sysinfo.c

sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.c

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Fri, 30 Nov 2012 14:15:27 +0000 (07:15 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-sh

9 years agoinclude/linux/byteorder: Always defines __fswab64, __swab64p and __swab64s
Nobuhiro Iwamatsu [Wed, 14 Nov 2012 21:35:26 +0000 (21:35 +0000)]
include/linux/byteorder: Always defines __fswab64, __swab64p and __swab64s

When __BYTEORDER_HAS_U64__ is not defined, we got warning following:

-----
/tmp/include/linux/byteorder/little_endian.h: In function ā€˜__cpu_to_be64pā€™:
/tmp/include/linux/byteorder/little_endian.h:71:2: warning: implicit declaration of function ā€˜__swab64pā€™
[-Wimplicit-function-declaration]
-----

Usually, __arch__swab64* required for __fswab64,  __swab64p and __swab64s
is defined.  Therefore, __BYTEORDER_HAS_U64__ is unnecessary.
This removes __BYTEORDER_HAS_U64__.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
9 years agoserial: serial_sh: bugfix: autoboot fails if serial console is not connected
Tetsuyuki Kobayashi [Mon, 19 Nov 2012 21:37:38 +0000 (21:37 +0000)]
serial: serial_sh: bugfix: autoboot fails if serial console is not connected

On kzm9g board (rmobile SoC), autoboot fails if serial console cable is not
connected.  When serial cable is not connected, serial error occurs and
some garbage comes in data register.
sh_serial_tstc() in serial_sh.c does not check error status and misunderstand
there is some input data.  It is the reason that autoboot fails.
This patch adds checking error status in sh_serial_tstc().

This patch is based on v2013.01-rc1 tag of u-boot master git.

Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agosh: fix trigger_address_error()
Yoshihiro Shimoda [Sun, 4 Nov 2012 15:53:13 +0000 (15:53 +0000)]
sh: fix trigger_address_error()

The function should set BL bit, but it should not clear other flags.
So, the patch uses set_bl_bit() instead of a local asm code.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fdt
Tom Rini [Thu, 29 Nov 2012 13:41:56 +0000 (06:41 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-fdt

9 years agofdt: Correct global_data condition in main
Simon Glass [Wed, 28 Nov 2012 07:54:58 +0000 (07:54 +0000)]
fdt: Correct global_data condition in main

We need an extra condition here in case we want to use fdt without the
silent console/cmdline editing/post options. It is easier to just remove
the #ifdef.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-x86
Tom Rini [Wed, 28 Nov 2012 20:44:40 +0000 (13:44 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-x86

9 years agox86: coreboot: Enable LPC TPM
Simon Glass [Sun, 25 Nov 2012 20:12:16 +0000 (20:12 +0000)]
x86: coreboot: Enable LPC TPM

Coreboot boards have an LPC TPM connected, so enable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove coreboot start16 code
Simon Glass [Tue, 27 Nov 2012 21:08:12 +0000 (21:08 +0000)]
x86: Remove coreboot start16 code

Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Implement recursively scanning PCI busses
Gabe Black [Wed, 10 Oct 2012 13:12:59 +0000 (13:12 +0000)]
x86: coreboot: Implement recursively scanning PCI busses

A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.

On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.

This was tested as follows:

Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Modify u-boot code to allow building coreboot payload
Vadim Bendebury [Wed, 10 Oct 2012 13:12:58 +0000 (13:12 +0000)]
x86: coreboot: Modify u-boot code to allow building coreboot payload

This prevents the preprocessor from complaining when processing
variadic macros

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
9 years agox86: coreboot: Tell u-boot about PCI bus 0 when initializing
Gabe Black [Wed, 10 Oct 2012 13:12:57 +0000 (13:12 +0000)]
x86: coreboot: Tell u-boot about PCI bus 0 when initializing

U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
9 years agox86: coreboot: Move non-board specific files to coreboot arch directory
Stefan Reinauer [Wed, 10 Oct 2012 13:12:56 +0000 (13:12 +0000)]
x86: coreboot: Move non-board specific files to coreboot arch directory

coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add some missing includes
Gabe Black [Wed, 10 Oct 2012 13:12:55 +0000 (13:12 +0000)]
x86: Add some missing includes

I suspect these includes were usually available because something else
included them earlier or because they were brought in transitively.

Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Allow excluding reset vector code from u-boot
Gabe Black [Tue, 27 Nov 2012 21:08:06 +0000 (21:08 +0000)]
x86: Allow excluding reset vector code from u-boot

When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add initial memory barrier macros
Simon Glass [Wed, 10 Oct 2012 13:12:53 +0000 (13:12 +0000)]
x86: Add initial memory barrier macros

These are available on other architectures, so add them on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add ilog2 to bitops
Graeme Russ [Tue, 27 Nov 2012 15:38:38 +0000 (15:38 +0000)]
x86: Add ilog2 to bitops

ilog2 is required by AHCI driver

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove duplicate PCI init
Graeme Russ [Tue, 27 Nov 2012 15:38:37 +0000 (15:38 +0000)]
x86: Remove duplicate PCI init

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Put global data on the stack
Graeme Russ [Tue, 27 Nov 2012 15:38:36 +0000 (15:38 +0000)]
x86: Put global data on the stack

Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Forward declare gd_t
Graeme Russ [Tue, 27 Nov 2012 15:38:35 +0000 (15:38 +0000)]
x86: Forward declare gd_t

So it can be used as a type in struct global_data and remove an ugly typecast

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Tom Rini [Wed, 28 Nov 2012 15:30:21 +0000 (08:30 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-mpc85xx

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 28 Nov 2012 03:34:51 +0000 (20:34 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

9 years agopowerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE
York Sun [Thu, 8 Nov 2012 12:33:39 +0000 (12:33 +0000)]
powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE

Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in
cpu_init.c.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: update the work-around for P4080 erratum SERDES-9
Timur Tabi [Thu, 1 Nov 2012 08:20:22 +0000 (08:20 +0000)]
powerpc/85xx: update the work-around for P4080 erratum SERDES-9

The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/p4080ds: fix PCI-e x8 link training down failure
Yuanquan Chen [Mon, 26 Nov 2012 23:49:45 +0000 (23:49 +0000)]
powerpc/p4080ds: fix PCI-e x8 link training down failure

Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.

Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet_ds: move SATA config to board configuration
Zang Roy-R61911 [Mon, 26 Nov 2012 00:05:38 +0000 (00:05 +0000)]
powerpc/corenet_ds: move SATA config to board configuration

board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :

 #ifdef CONFIG_FSL_SATA_V2
 ...
 #endif

To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.

This patch reverts Timur's
commit:3e0529f742e893653848494ffb9f7cd0d91304bf

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: implement check for erratum A-004580 work-around
Timur Tabi [Thu, 1 Nov 2012 08:20:23 +0000 (08:20 +0000)]
powerpc/85xx: implement check for erratum A-004580 work-around

The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list
Kim Phillips [Wed, 31 Oct 2012 11:09:26 +0000 (11:09 +0000)]
powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list

by moving compat_strlist into the .bss section.

0xfe004d80 fdt_fixup_crypto_node [u-boot]: 264

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Temporary fix for spin table backward compatibility
York Sun [Sun, 28 Oct 2012 08:12:54 +0000 (08:12 +0000)]
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/P2041RDB: Fix Flash address LAW address
York Sun [Fri, 26 Oct 2012 16:40:15 +0000 (16:40 +0000)]
powerpc/P2041RDB: Fix Flash address LAW address

P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet_ds: Update DDR timing for single-rank DIMMs
York Sun [Fri, 26 Oct 2012 16:40:14 +0000 (16:40 +0000)]
powerpc/corenet_ds: Update DDR timing for single-rank DIMMs

Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: implement check for erratum A-004849 work-around
Timur Tabi [Thu, 25 Oct 2012 12:40:00 +0000 (12:40 +0000)]
powerpc/85xx: implement check for erratum A-004849 work-around

The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to
update.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
Timur Tabi [Tue, 23 Oct 2012 09:40:22 +0000 (09:40 +0000)]
powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board

The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
Timur Tabi [Tue, 23 Oct 2012 10:48:09 +0000 (10:48 +0000)]
powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC

The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/qoriq: Move FMAN microcode location
York Sun [Fri, 19 Oct 2012 08:35:12 +0000 (08:35 +0000)]
powerpc/qoriq: Move FMAN microcode location

Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: Properly determine maximum supported bus width
Andy Fleming [Wed, 31 Oct 2012 19:02:38 +0000 (19:02 +0000)]
mmc: Properly determine maximum supported bus width

At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:

MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0
MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1
MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2

However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.

The new code clarifies the very different namespaces:

host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)

We create arrays to map between the namespaces, like in Linux.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
9 years ago8xxx: Change all 8*xx_DDR addresses to 8xxx
Andy Fleming [Wed, 24 Oct 2012 00:03:46 +0000 (19:03 -0500)]
8xxx: Change all 8*xx_DDR addresses to 8xxx

There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
9 years agommc: Fix incorrect handling of 'read' & 'write' commands
Taylor Hutt [Thu, 22 Nov 2012 09:13:00 +0000 (09:13 +0000)]
mmc: Fix incorrect handling of 'read' & 'write' commands

If a malformed 'read' or 'write' command is issued, the Sandbox U-Boot
can crash because the command-handling code does no error checking on
the number of provided arguments.

This change makes the mmc 'erase', 'read' and 'write' commands only
function if the proper number of arguments are supplied.

Also puts the else assignment at the beginning fo the if() statement
to shortens the generated code.  This removes an unnecessary jump from
the generated code.

Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: tegra: use bounce buffer APIs
Stephen Warren [Tue, 6 Nov 2012 11:27:30 +0000 (11:27 +0000)]
mmc: tegra: use bounce buffer APIs

Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.

Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC
code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agocommon: rework bouncebuf implementation
Stephen Warren [Tue, 6 Nov 2012 11:27:29 +0000 (11:27 +0000)]
common: rework bouncebuf implementation

The current bouncebuf API requires all parameters to be passed to both
bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf
start function to accept a state structure as a parameter, and only
require that state struct to be passed to the stop function. This
simplifies usage of the bounce buffer by clients.

Don't modify the data pointer, but rather store the temporary buffer in
this state struct. The bouncebuf code ensures that client code can
always use a single buffer pointer in the state structure, irrespective
of whether a bounce buffer actually had to be allocated.

Move cache management logic into the bounce buffer code, so that each
client doesn't have to duplicate this. I believe there's no need to
invalidate the buffer before a DMA operation, since flushing the cache
should prevent any write-backs.

Update the MXS MMC driver for this change.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agobouncebuf: remove dummy implementation
Stephen Warren [Tue, 6 Nov 2012 11:27:28 +0000 (11:27 +0000)]
bouncebuf: remove dummy implementation

If any driver ever needs to use the bounce buffer API, it always needs
to use it. As such, providing a dummy implementation of those APIs when
CONFIG_BOUNCE_BUFFER isn't defined does not make sense. Remove the dummy
implementation.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoReplace CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER in configs
Stephen Warren [Tue, 6 Nov 2012 11:27:27 +0000 (11:27 +0000)]
Replace CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER in configs

Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the
boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced
CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed
converting a few boards over to the new option. Fix this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: add no simultaenous power and vdd
Mela Custodio [Sat, 3 Nov 2012 17:40:16 +0000 (17:40 +0000)]
mmc: add no simultaenous power and vdd

Bring in the code from Linux kernel.

Added to Linux kernel by:
commit e08c1694d9e2138204f2b79b73f0f159074ce2f5
Author: Andres Salomon <dilinger@queued.net>
Date:   Fri Jul 4 10:00:03 2008 -0700

Some HW balks when writing both voltage setting and power up at the same
time to SDHCI_POWER_CONTROL register.

Signed-off-by: Rommel G Custodio <sessyargc@gmail.com>
CC: Andy Fleming <afleming@freescale.com>
v2: fix attribution and SOB
Signed-off-by: Andy Fleming <afleming@freescale.com>