9 years agox86: Add CBMEM console driver for coreboot
Vadim Bendebury [Fri, 12 Oct 2012 18:48:47 +0000 (18:48 +0000)]
x86: Add CBMEM console driver for coreboot

This patch builds upon the recently introduced CBMEM console
feature of coreboot.

CBMEM console uses a memry area allocated by coreboot to store
the console output. The memory area has a certain structure,
which allows to determine where the buffer is, the buffer size
and the location of the pointer in the buffer. This allows
different phases of the firmware (rom based coreboot, ram based
coreboot, u-boot after relocation with this change) to keep
adding text to the same buffer.

Note that this patch introduces a new console driver and adds the
driver to the list of drivers to be used for console output, i.e.
it engages only after u-boot relocates. Usiong CBMEM console for
capturing the pre-relocation console output will be done under a
separate change.

>From Linux, run the cbmem.py utility (which is a part of the coreboot
package) to see the output, e.g.:

SCSI:  AHCI 0001.0300 32 slots 6 ports ? Gbps 0xf impl SATA mode
flags: 64bit ilck stag led pmp pio
Magic signature found
Kernel command line: "cros_secure  quiet loglevel=1 console=tty2...

Note that the entire u-boot output fits into the buffer only if
the coreboot log level is reduced from the most verbose. Ether
the buffer size will have to be increased, or the coreboot
verbosity permanently reduced.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Decode additional coreboot sysinfo tags
Simon Glass [Fri, 12 Oct 2012 18:48:46 +0000 (18:48 +0000)]
x86: coreboot: Decode additional coreboot sysinfo tags

Add support for decoding tags for GPIOs, compile/build info, cbmem and
other features.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Drop sysinfo.c
Stefan Reinauer [Fri, 12 Oct 2012 18:48:45 +0000 (18:48 +0000)]
x86: coreboot: Drop sysinfo.c

sysinfo.c only contains the lib_sysinfo data structure which
is used/filled by tables.c. This split was introduced by importing
code from libpayload originally, but to keep the code simple, add
the single line of actual code to tables.c

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fdt
Tom Rini [Thu, 29 Nov 2012 13:41:56 +0000 (06:41 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-fdt

9 years agofdt: Correct global_data condition in main
Simon Glass [Wed, 28 Nov 2012 07:54:58 +0000 (07:54 +0000)]
fdt: Correct global_data condition in main

We need an extra condition here in case we want to use fdt without the
silent console/cmdline editing/post options. It is easier to just remove
the #ifdef.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-x86
Tom Rini [Wed, 28 Nov 2012 20:44:40 +0000 (13:44 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-x86

9 years agox86: coreboot: Enable LPC TPM
Simon Glass [Sun, 25 Nov 2012 20:12:16 +0000 (20:12 +0000)]
x86: coreboot: Enable LPC TPM

Coreboot boards have an LPC TPM connected, so enable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove coreboot start16 code
Simon Glass [Tue, 27 Nov 2012 21:08:12 +0000 (21:08 +0000)]
x86: Remove coreboot start16 code

Now that coreboot doesn't need the start16 code, remove it. We need
to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Implement recursively scanning PCI busses
Gabe Black [Wed, 10 Oct 2012 13:12:59 +0000 (13:12 +0000)]
x86: coreboot: Implement recursively scanning PCI busses

A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.

On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.

This was tested as follows:

Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: coreboot: Modify u-boot code to allow building coreboot payload
Vadim Bendebury [Wed, 10 Oct 2012 13:12:58 +0000 (13:12 +0000)]
x86: coreboot: Modify u-boot code to allow building coreboot payload

This prevents the preprocessor from complaining when processing
variadic macros

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
9 years agox86: coreboot: Tell u-boot about PCI bus 0 when initializing
Gabe Black [Wed, 10 Oct 2012 13:12:57 +0000 (13:12 +0000)]
x86: coreboot: Tell u-boot about PCI bus 0 when initializing

U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
9 years agox86: coreboot: Move non-board specific files to coreboot arch directory
Stefan Reinauer [Wed, 10 Oct 2012 13:12:56 +0000 (13:12 +0000)]
x86: coreboot: Move non-board specific files to coreboot arch directory

coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add some missing includes
Gabe Black [Wed, 10 Oct 2012 13:12:55 +0000 (13:12 +0000)]
x86: Add some missing includes

I suspect these includes were usually available because something else
included them earlier or because they were brought in transitively.

Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Allow excluding reset vector code from u-boot
Gabe Black [Tue, 27 Nov 2012 21:08:06 +0000 (21:08 +0000)]
x86: Allow excluding reset vector code from u-boot

When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add initial memory barrier macros
Simon Glass [Wed, 10 Oct 2012 13:12:53 +0000 (13:12 +0000)]
x86: Add initial memory barrier macros

These are available on other architectures, so add them on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add ilog2 to bitops
Graeme Russ [Tue, 27 Nov 2012 15:38:38 +0000 (15:38 +0000)]
x86: Add ilog2 to bitops

ilog2 is required by AHCI driver

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Remove duplicate PCI init
Graeme Russ [Tue, 27 Nov 2012 15:38:37 +0000 (15:38 +0000)]
x86: Remove duplicate PCI init

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Put global data on the stack
Graeme Russ [Tue, 27 Nov 2012 15:38:36 +0000 (15:38 +0000)]
x86: Put global data on the stack

Putting global data on the stack simplifies the init process (and makes it
slightly quicker). During the 'flash' stage of the init sequence, global
data is in the CAR stack. After SDRAM is initialised, global data is copied
from CAR to the SDRAM stack

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Forward declare gd_t
Graeme Russ [Tue, 27 Nov 2012 15:38:35 +0000 (15:38 +0000)]
x86: Forward declare gd_t

So it can be used as a type in struct global_data and remove an ugly typecast

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marek Vasut <marex@denx.de>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Tom Rini [Wed, 28 Nov 2012 15:30:21 +0000 (08:30 -0700)]
Merge branch 'master' of git://denx.de/git/u-boot-mpc85xx

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 28 Nov 2012 03:34:51 +0000 (20:34 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

9 years agopowerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE
York Sun [Thu, 8 Nov 2012 12:33:39 +0000 (12:33 +0000)]
powerpc/mpc85xx: Fix a bug introduced by CONFIG_PPC_SPINTABLE_COMPATIBLE

Fix a bug introduced by this patch
powerpc/mpc85xx: Temporary fix for spin table backward compatibility


Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: update the work-around for P4080 erratum SERDES-9
Timur Tabi [Thu, 1 Nov 2012 08:20:22 +0000 (08:20 +0000)]
powerpc/85xx: update the work-around for P4080 erratum SERDES-9

The documented work-around for P4080 erratum SERDES-9 has been updated.
It is now compatible with the work-around for erratum A-4580.

This requires adding a few bitfield macros for the BnTTLCRy0 register.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/p4080ds: fix PCI-e x8 link training down failure
Yuanquan Chen [Mon, 26 Nov 2012 23:49:45 +0000 (23:49 +0000)]
powerpc/p4080ds: fix PCI-e x8 link training down failure

Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.

Signed-off-by: Yuanquan Chen <B41889@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet_ds: move SATA config to board configuration
Zang Roy-R61911 [Mon, 26 Nov 2012 00:05:38 +0000 (00:05 +0000)]
powerpc/corenet_ds: move SATA config to board configuration

board configuration file is included before asm/config_mpc85xx.h.
however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h.
it will never take effective in the board configuration file for
this kind of code :


To solve this problem, move CONFIG_FSL_SATA_V2 to board
configuration header file.

This patch reverts Timur's

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: implement check for erratum A-004580 work-around
Timur Tabi [Thu, 1 Nov 2012 08:20:23 +0000 (08:20 +0000)]
powerpc/85xx: implement check for erratum A-004580 work-around

The work-around for erratum A-004580 ("Internal tracking loop can falsely
lock causing unrecoverable bit errors") is implemented via the PBI
(pre-boot initialization code, typically attached to the RCW binary).
This is because the work-around is easier to implement in PBI than in
U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004580, we can do this by verifying
that the values in the specific registers that the work-around says to

This change requires access to the SerDes lane sub-structure in
serdes_corenet_t, so we make it a named struct.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list
Kim Phillips [Wed, 31 Oct 2012 11:09:26 +0000 (11:09 +0000)]
powerpc/mpc8xxx: take fdt_fixup_crypto_node() off the checkstack list

by moving compat_strlist into the .bss section.

0xfe004d80 fdt_fixup_crypto_node [u-boot]: 264

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: Temporary fix for spin table backward compatibility
York Sun [Sun, 28 Oct 2012 08:12:54 +0000 (08:12 +0000)]
powerpc/mpc85xx: Temporary fix for spin table backward compatibility

Once u-boot sets the spin table to cache-enabled memory, old kernel which
uses cache-inhibit mapping without coherence will not work properly. We
use this temporary fix until kernel has updated its spin table code.
For now this fix is activated by default. To disable this fix for new
kernel, set environmental variable "spin_table_compat=no". After kernel
has updated spin table code, this default shall be changed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/P2041RDB: Fix Flash address LAW address
York Sun [Fri, 26 Oct 2012 16:40:15 +0000 (16:40 +0000)]
powerpc/P2041RDB: Fix Flash address LAW address

P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet
connector. It is necessary to use the same base address for correct LAW
address. An offset is added for NOR flash.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/corenet_ds: Update DDR timing for single-rank DIMMs
York Sun [Fri, 26 Oct 2012 16:40:14 +0000 (16:40 +0000)]
powerpc/corenet_ds: Update DDR timing for single-rank DIMMs

Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: implement check for erratum A-004849 work-around
Timur Tabi [Thu, 25 Oct 2012 12:40:00 +0000 (12:40 +0000)]
powerpc/85xx: implement check for erratum A-004849 work-around

The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a
deadlock under certain traffic patterns causing the system to hang") is
implemented via the PBI (pre-boot initialization code, typically attached
to the RCW binary).  This is because the work-around is easier to implement
in PBI than in U-Boot itself.

It is still useful, however, for the 'errata' command to tell us whether
the work-around has been applied.  For A-004849, we can do this by verifying
that the values in the specific registers that the work-around says to

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
Timur Tabi [Tue, 23 Oct 2012 09:40:22 +0000 (09:40 +0000)]
powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board

The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
Timur Tabi [Tue, 23 Oct 2012 10:48:09 +0000 (10:48 +0000)]
powerpc/85xx/p5040: add CONFIG_SYS_PPC64, del CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC

The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in
config_mpc85xx.h.  This macro was absent in the initial P5040 patch because
it crossed paths with the patch that introduced the macro.

Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the
upstream U-Boot.  It's a holdover from the SDK.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/qoriq: Move FMAN microcode location
York Sun [Fri, 19 Oct 2012 08:35:12 +0000 (08:35 +0000)]
powerpc/qoriq: Move FMAN microcode location

Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning
of this virtual bank so that this bank can store RCW or be used together
with other banks to store large images.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: Properly determine maximum supported bus width
Andy Fleming [Wed, 31 Oct 2012 19:02:38 +0000 (19:02 +0000)]
mmc: Properly determine maximum supported bus width

At some point, a confusion arose about the use of the bit
definitions in host_caps for bus widths, and the value
in ext_csd. By coincidence, a simple shift could convert
between one and the other:


However, as host_caps is a bitmask of supported things,
there is not, in fact, a one-to-one correspondence. host_caps
is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical
things were happening where we would try to set the bus width
to 12.

The new code clarifies the very different namespaces:

host_caps/card_caps = bitmask (MMC_MODE_*)
ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*)
mmc->bus_width integer number of bits (1, 4, 8)

We create arrays to map between the namespaces, like in Linux.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
9 years ago8xxx: Change all 8*xx_DDR addresses to 8xxx
Andy Fleming [Wed, 24 Oct 2012 00:03:46 +0000 (19:03 -0500)]
8xxx: Change all 8*xx_DDR addresses to 8xxx

There were a number of shared files that were using
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:


All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
9 years agommc: Fix incorrect handling of 'read' & 'write' commands
Taylor Hutt [Thu, 22 Nov 2012 09:13:00 +0000 (09:13 +0000)]
mmc: Fix incorrect handling of 'read' & 'write' commands

If a malformed 'read' or 'write' command is issued, the Sandbox U-Boot
can crash because the command-handling code does no error checking on
the number of provided arguments.

This change makes the mmc 'erase', 'read' and 'write' commands only
function if the proper number of arguments are supplied.

Also puts the else assignment at the beginning fo the if() statement
to shortens the generated code.  This removes an unnecessary jump from
the generated code.

Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: tegra: use bounce buffer APIs
Stephen Warren [Tue, 6 Nov 2012 11:27:30 +0000 (11:27 +0000)]
mmc: tegra: use bounce buffer APIs

Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In
some cases (e.g. user load commands) this cannot be guaranteed by callers
of the MMC APIs. To solve this, modify the Tegra MMC driver to use the
new bounce_buffer_*() APIs.

Note: Ideally, all U-Boot code will always provide address- and size-
aligned buffers, so a bounce buffer will only ever be needed for user-
supplied buffers (e.g. load commands). Ensuring this removes the need
for performance-sucking bounce buffer cache management and memcpy()s.
The one known exception at present is the SCR buffer in sd_change_freq(),
which is only 8 bytes long. Solving this requires enhancing struct
mmc_data to know the difference between buffer size and transferred data
size, or forcing all callers of mmc_send_cmd() to have allocated buffers
using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not
enforced in any way at present, and so cannot be assumed by the core MMC

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agocommon: rework bouncebuf implementation
Stephen Warren [Tue, 6 Nov 2012 11:27:29 +0000 (11:27 +0000)]
common: rework bouncebuf implementation

The current bouncebuf API requires all parameters to be passed to both
bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf
start function to accept a state structure as a parameter, and only
require that state struct to be passed to the stop function. This
simplifies usage of the bounce buffer by clients.

Don't modify the data pointer, but rather store the temporary buffer in
this state struct. The bouncebuf code ensures that client code can
always use a single buffer pointer in the state structure, irrespective
of whether a bounce buffer actually had to be allocated.

Move cache management logic into the bounce buffer code, so that each
client doesn't have to duplicate this. I believe there's no need to
invalidate the buffer before a DMA operation, since flushing the cache
should prevent any write-backs.

Update the MXS MMC driver for this change.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agobouncebuf: remove dummy implementation
Stephen Warren [Tue, 6 Nov 2012 11:27:28 +0000 (11:27 +0000)]
bouncebuf: remove dummy implementation

If any driver ever needs to use the bounce buffer API, it always needs
to use it. As such, providing a dummy implementation of those APIs when
CONFIG_BOUNCE_BUFFER isn't defined does not make sense. Remove the dummy

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoReplace CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER in configs
Stephen Warren [Tue, 6 Nov 2012 11:27:27 +0000 (11:27 +0000)]

Commits 6dc71c8 "MMC: MXS: Toggle the generic bounce buffer on the
boards" and 49a627f "MMC: Remove the MMC bounce buffer" replaced
converting a few boards over to the new option. Fix this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: add no simultaenous power and vdd
Mela Custodio [Sat, 3 Nov 2012 17:40:16 +0000 (17:40 +0000)]
mmc: add no simultaenous power and vdd

Bring in the code from Linux kernel.

Added to Linux kernel by:
commit e08c1694d9e2138204f2b79b73f0f159074ce2f5
Author: Andres Salomon <dilinger@queued.net>
Date:   Fri Jul 4 10:00:03 2008 -0700

Some HW balks when writing both voltage setting and power up at the same
time to SDHCI_POWER_CONTROL register.

Signed-off-by: Rommel G Custodio <sessyargc@gmail.com>
CC: Andy Fleming <afleming@freescale.com>
v2: fix attribution and SOB
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: at91sam9x5: support to save environment in mmc
Wu, Josh [Fri, 2 Nov 2012 00:17:27 +0000 (00:17 +0000)]
mmc: at91sam9x5: support to save environment in mmc

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agommc: Fix interpretation of MMC_CMD_ALL_SEND_CID
Taylor Hutt [Sat, 20 Oct 2012 17:15:59 +0000 (17:15 +0000)]
mmc: Fix interpretation of MMC_CMD_ALL_SEND_CID

The interpretation of the data returned by the MMC_CMD_ALL_SEND_CID
command was incorrect with respect to the JEDEC Standard No. 84-A441.

This change makes the interpretation correct with respect to the
defined fields of the CID register.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoEXYNOS: mmc: support DesignWare Controller for Samsung-SoC
Jaehoon Chung [Mon, 15 Oct 2012 19:10:31 +0000 (19:10 +0000)]
EXYNOS: mmc: support DesignWare Controller for Samsung-SoC

Support DesignWare MMC Controller for Samsung Specific.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Rajeshawari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
9 years agoRemove obsolete header file
Pantelis Antoniou [Wed, 28 Nov 2012 02:43:54 +0000 (02:43 +0000)]
Remove obsolete header file

usbdescriptors.h conflicts with linux/usb/ch9.h
Remove it.

Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-nand-flash
Tom Rini [Mon, 26 Nov 2012 21:53:33 +0000 (14:53 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

9 years agonand: Add torture feature
Benoît Thébaudeau [Fri, 16 Nov 2012 19:20:54 +0000 (20:20 +0100)]
nand: Add torture feature

This patch adds a NAND Flash torture feature, which is useful as a block stress
test to determine if a block is still good and reliable (or should be marked as
bad), e.g. after a write error.

This code is ported from mtd-utils' lib/libmtd.c.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
[scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings]
Signed-off-by: Scott Wood <scottwood@freescale.com>
9 years agonand: Fix nand_erase_opts() offset check
Benoît Thébaudeau [Mon, 5 Nov 2012 10:16:15 +0000 (10:16 +0000)]
nand: Fix nand_erase_opts() offset check

NAND Flash is erased by blocks, not by pages.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
9 years agonand: Clean up nand_util
Benoît Thébaudeau [Mon, 5 Nov 2012 10:15:46 +0000 (10:15 +0000)]
nand: Clean up nand_util

This patch cleans up nand_util.c:
 - Fix tabs.
 - Fix typos.
 - Remove space character before opening parenthesis in function calls.
 - Fix comments.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Scott Wood <scottwood@freescale.com>
9 years agonand: Move the sub-page read support enable to a flag
Joe Hershberger [Mon, 5 Nov 2012 06:46:31 +0000 (06:46 +0000)]
nand: Move the sub-page read support enable to a flag

Use a flag instead of a hard-coded macro so that sub-page reads can be
enabled in other cases (such as on-die ecc).

This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
9 years agodriver/mtd:IFC NAND:Initialise internal SRAM before any write
Prabhakar Kushwaha [Wed, 12 Sep 2012 22:26:05 +0000 (22:26 +0000)]
driver/mtd:IFC NAND:Initialise internal SRAM before any write

IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.

Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[scottwood@freescale.com: fix fsl_ifc_sram_init prototype]
Signed-off-by: Scott Wood <scottwood@freescale.com>
9 years agoREADME: Reference nand monitor commands in U-Boot README
Karl O. Pinc [Fri, 3 Aug 2012 05:57:21 +0000 (05:57 +0000)]
README: Reference nand monitor commands in U-Boot README

Reference nand monitor commands in U-Boot README

Signed-off-by: Karl O. Pinc <kop@meme.com>
9 years agonand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers
Scott Wood [Fri, 2 Nov 2012 23:41:35 +0000 (18:41 -0500)]
nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC drivers

These controllers can only do hardware ECC on full page transfers.

Signed-off-by: Scott Wood <scottwood@freescale.com>
9 years agopowerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
Scott Wood [Fri, 12 Oct 2012 23:02:24 +0000 (18:02 -0500)]
powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot

This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data.  The SPL itself cannot use SPD due
to code size constraints.  It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with.  It's possible that different revisions of the board
require different settings.  Using SPD eliminates that problem.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map
Scott Wood [Wed, 3 Oct 2012 00:35:18 +0000 (19:35 -0500)]
powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map

- Sort by address, and fix column alignment

- Don't label things as localbus that aren't.  Instead, put chipselect
  info at the end of the description for localbus windows.  Note that
  NAND/NOR have their chipselects swapped when booting from NAND, and CS2
  can be either PMC or VSC7385 depending on hwconfig.

- Shrink NAND to the 32K that's actually mapped in the localbus

- Assign an address and size to L2 SRAM.  Remove the similarly named
  but unintelligible "L2 SDRAM(REV.)".

- Remove the untrue comment about L1 stack being mapped with TLB0.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl
Scott Wood [Fri, 21 Sep 2012 21:31:00 +0000 (16:31 -0500)]
powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agospl/nand: config symbol documentation
Scott Wood [Fri, 21 Sep 2012 23:35:27 +0000 (18:35 -0500)]
spl/nand: config symbol documentation

Document parameters used for specifying the NAND image to be loaded.

Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only
nand_spl_simple.c, not the entire nand directory.  The word "simple" is
there for a reason.  :-)

Signed-off-by: Scott Wood <scottwood@freescale.com>
v2: updated for makefile changes earlier in patchset

9 years agospl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.
Scott Wood [Fri, 21 Sep 2012 00:09:07 +0000 (19:09 -0500)]
spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.

Some small SPLs do not use nand_base.c, and a subset of those also
require a special driver.  Some SPLs need software ECC but others can't
fit it.

All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these
symbols added to preserve existing behavior.

Signed-off-by: Scott Wood <scottwood@freescale.com>
v2: use positive logic for including bits of NAND, rather than
a MINIMAL symbol that excludes things.

9 years agopowerpc/mpc85xx/p1_p2_rdb_pc: new SPL support
Scott Wood [Fri, 21 Sep 2012 00:05:12 +0000 (19:05 -0500)]
powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support


Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agospl/85xx: new SPL support
Scott Wood [Fri, 21 Sep 2012 00:02:18 +0000 (19:02 -0500)]
spl/85xx: new SPL support

Update CONFIG_RAMBOOT and CONFIG_NAND_SPL references to accept CONFIG_SPL
and CONFIG_SPL_BUILD, respectively.  CONFIG_NAND_SPL can be removed once
the last mpc85xx nand_spl target is gone.

CONFIG_RAMBOOT will need to remain for other use cases, but it doesn't
seem right to overload it for meaning SPL as well as nand_spl does.  Even
if it's somewhat appropriate for the main u-boot, the SPL itself isn't
(necessarily) ramboot, and we don't have separate configs for SPL and
main u-boot.  It was also inconsistent, as other platforms such as
mpc83xx didn't use CONFIG_RAMBOOT in this way.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agospl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL
Scott Wood [Thu, 20 Sep 2012 21:35:21 +0000 (16:35 -0500)]
spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL

cpu_init_nand.c is renamed to spl_minimal.c as it is not really NAND-specific.

Signed-off-by: Scott Wood <scottwood@freescale.com>
v2: factor out START, and change cpu_init_nand.c to spl_minimal.c
Cc: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: consistently use COBJS-y
Scott Wood [Tue, 25 Sep 2012 23:17:45 +0000 (18:17 -0500)]
powerpc/mpc85xx: consistently use COBJS-y

A subsequent patch will conditionalize some of the files that are
currently unconditional.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agospl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c
Scott Wood [Thu, 20 Sep 2012 21:35:21 +0000 (16:35 -0500)]
spl/mpc85xx: rename cpu_init_nand.c to spl_minimal.c

There is nothing really NAND-specific about this file.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agospl: include resetvec and lib8xxx
Scott Wood [Wed, 19 Sep 2012 22:56:39 +0000 (17:56 -0500)]
spl: include resetvec and lib8xxx

The toplevel makefile hardcodes this stuff, so spl/Makefile needs to as well.

Signed-off-by: Scott Wood <scottwood@freescale.com>
9 years agospl/mpc85xx: move udelay to cpu code
Scott Wood [Sat, 18 Aug 2012 00:46:29 +0000 (19:46 -0500)]
spl/mpc85xx: move udelay to cpu code

It applies to non-Freescale 85xx boards as well as Freescale boards,
so it doesn't belong in board/freescale.  Plus, it needs to come out
of nand_spl if it's to be used by the new SPL.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx
Scott Wood [Fri, 17 Aug 2012 21:17:50 +0000 (16:17 -0500)]
powerpc/mpc8xxx: move LAW code into arch/powerpc/cpu/mpc8xxx

It's arch code and not a driver, so move it where it belongs.  When it
originally went into drivers/misc there was no 8xxx CPU directory.

This will make new-SPL support a little easier since we can keep the CPU
stuff together and not need to pull stuff in from drivers/misc.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agopowerpc/mpc85xx: fix TLB alignment
Scott Wood [Thu, 20 Sep 2012 23:34:49 +0000 (18:34 -0500)]
powerpc/mpc85xx: fix TLB alignment

In the RAMBOOT/SPL case we were creating a TLB entry starting at
CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly
aligned for the TLB entry size.  This turned out to not be the case
with NAND SPL because the main U-Boot starts at an offset into the image
in order to skip the SPL itself.

Fix the TLB entry to always start at a proper alignment.  We still assume that
CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary
thus requiring multiple TLB entries.

Signed-off-by: Scott Wood <scottwood@frescale.com>
Cc: Andy Fleming <afleming@freescale.com>
9 years agopowerpc: change .fixup test to a GCC version test
Scott Wood [Fri, 21 Sep 2012 00:10:01 +0000 (19:10 -0500)]
powerpc: change .fixup test to a GCC version test

This was introduced by commit 244615197469dd6fe75ae082f38424b97c79aeaf, but it
fails in a minimal SPL build where the only thing in arch/powerpc/lib is
cache.c, which apparently doesn't generate any fixup records.

The problem is reported to occur with GCC 3.x, so insist on GCC 4.0 or newer.
Patterned after checkthumb as suggested by Tom Rini.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Tom Rini <trini@ti.com>
v2: test gcc version instead of testing nothing

9 years agospl: introduce CONFIG_SPL_TARGET
Scott Wood [Fri, 21 Sep 2012 21:27:32 +0000 (16:27 -0500)]
spl: introduce CONFIG_SPL_TARGET

Currently the SPL target is specified in a CPU-specific makefile
fragment.  While some targets may need something more complicated than a
simple target name, targets which don't need this shouldn't have to provide a makefile fragment just for this.

Signed-off-by: Scott Wood <scottwood@freescale.com>
v2: Removed default target as it's been pointed out to me how existing platforms
cause the SPL to be built.

9 years agospl: rename u-boot-pad.bin to u-boot-with-spl.bin
Scott Wood [Wed, 19 Sep 2012 22:45:41 +0000 (17:45 -0500)]
spl: rename u-boot-pad.bin to u-boot-with-spl.bin

Signed-off-by: Scott Wood <scottwood@freescale.com>
9 years agoAdd u-boot-pad.bin target to the Makefile
José Miguel Gonçalves [Wed, 19 Sep 2012 01:25:26 +0000 (01:25 +0000)]
Add u-boot-pad.bin target to the Makefile

Samsung's S3C24XX SoCs need this in order to generate a binary image
with a padded SPL concatenated with U-Boot.

Signed-off-by: José Miguel Gonçalves <jose.goncalves@inov.pt>
[scottwood@freescale.com: fixed prereq of u-boot.ubl]
Signed-off-by: Scott Wood <scottwood@freescale.com>
v2: Removed spl/ prefix from u-boot.ubl prerequisite.

9 years agopowerpc/mpc85xx: add comma before "already enabled"
Scott Wood [Tue, 30 Oct 2012 00:00:41 +0000 (19:00 -0500)]
powerpc/mpc85xx: add comma before "already enabled"

Now outputs like this:

L2:    512 KB already enabled, moving to 0xf8f80000

rather than this:

L2:    512 KB already enabledmoving to 0xf8f80000

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
9 years agopowerpc/mpc85xx: move debug tlb entry after TLB is in known state
Scott Wood [Fri, 26 Oct 2012 00:27:41 +0000 (19:27 -0500)]
powerpc/mpc85xx: move debug tlb entry after TLB is in known state

Previously, in many if not all configs we were creating overlapping TLB entries
which is illegal.  This caused a crash during boot when moving p2020rdb NAND SPL
into L2 SRAM.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Prabhakar, please test that debug still works.

9 years agoserial/ns16550: wait for TEMT before initializing
Scott Wood [Tue, 18 Sep 2012 23:19:05 +0000 (18:19 -0500)]
serial/ns16550: wait for TEMT before initializing

TEMT is set when the transmitter is totally empty and all output has

This prevents output problems (including a loss of synchronization
observed on p2020 that persisted for quite a while) if SPL has output
still on its way out.

Signed-off-by: Scott Wood <scottwood@freescale.com>
v2: fixed typo in subject, and explained what the bit does in the changelog

9 years agoserial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONS
Scott Wood [Tue, 16 Oct 2012 20:43:15 +0000 (15:43 -0500)]
serial/ns16550: don't build serial_ns16550 with MIN_FUNCTIONS

CONFIG_NS16550_MIN_FUNCTIONS is used by small SPLs to gain access to basic
ns16550 output code without pulling in things not needed by the SPL.

This previously only worked with non-MULTI configs.  Recently MULTI was
made mandatory, and MIN_FUNCTIONS fails like this:

drivers/serial/libserial.o: In function `calc_divisor.clone.0':
serial_ns16550.c:(.text.calc_divisor.clone.0+0x24): undefined reference to `get_bus_freq'
drivers/serial/libserial.o: In function `_serial_getc':
(.text._serial_getc+0x30): undefined reference to `NS16550_getc'
drivers/serial/libserial.o: In function `_serial_tstc':
(.text._serial_tstc+0x30): undefined reference to `NS16550_tstc'
drivers/serial/libserial.o: In function `_serial_setbrg':
(.text._serial_setbrg+0x3c): undefined reference to `NS16550_reinit'
make[1]: *** [/tmp/u-boot/spl/u-boot-spl] Error 1
make: *** [/tmp/u-boot/spl/u-boot-spl.bin] Error 2

With MIN_FUNCTIONS we don't need anything from this file, so don't build
it.  The conditional needs to be in the file itself rather than the
makefile, because the config symbols are only imported to the makefiles
once, not separately for the SPL phase of the build.

Signed-off-by: Scott Wood <scottwood@freescale.com>
9 years agoMIPS: do not initialize timestamp variable before relocate_code
Zhi-zhou Zhang [Sat, 24 Nov 2012 05:07:13 +0000 (05:07 +0000)]
MIPS: do not initialize timestamp variable before relocate_code

Because timestamp is declared as `static', we needn't initialize
it by writing it a zero. If we do it before relocate_code, we
will write into a flash address(0xffffffffbfc0xxxx).

Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-fdt
Tom Rini [Tue, 20 Nov 2012 17:46:30 +0000 (10:46 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-fdt

9 years agoMerge branch 'next'
Gerald Van Baren [Tue, 20 Nov 2012 00:26:35 +0000 (19:26 -0500)]
Merge branch 'next'

9 years agousb: r8a6659: Fix build by missing of parenthesis
Nobuhiro Iwamatsu [Thu, 15 Nov 2012 05:56:04 +0000 (14:56 +0900)]
usb: r8a6659: Fix build by missing of parenthesis

By commit c7e3b2b5, this was chanded to support multiple controllers.
But this has missing of parenthesis. This commit fix it.

r8a66597-hcd.c: In function ‘usb_lowlevel_init’:
r8a66597-hcd.c:911:52: error: expected declaration specifiers before ‘)’
r8a66597-hcd.c:935:1: error: expected ‘=’, ‘,’, ‘;’, ‘asm’ or‘__attribute__’ before ‘{’ token
r8a66597-hcd.c:939:1: error: expected ‘{’ at end of input

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Lucas Stach <dev@lynxeye.de>
9 years agousb: r8a66597: Switched from variable to only macro
Nobuhiro Iwamatsu [Tue, 20 Mar 2012 20:23:29 +0000 (20:23 +0000)]
usb: r8a66597: Switched from variable to only macro

Some variables are initialized with a value defined by macro.
This was changed to use the macro directly. And the variable not to
use deleted it.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoomap3_beagle: use new MUSB intstead of the old one
Ilya Yanok [Tue, 6 Nov 2012 13:48:31 +0000 (13:48 +0000)]
omap3_beagle: use new MUSB intstead of the old one

Enable using of new MUSB framework on Beagle.

NOTE! This is not just a change of backend code: top-level behavior
is also changed, we now use USB device port for USB Ethernet instead
of serial.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agoomap3_beagle: add musb-new init
Ilya Yanok [Tue, 6 Nov 2012 13:48:30 +0000 (13:48 +0000)]
omap3_beagle: add musb-new init

Add initialization for new MUSB framework.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agomusb-new: omap2plus backend driver
Ilya Yanok [Tue, 6 Nov 2012 13:48:29 +0000 (13:48 +0000)]
musb-new: omap2plus backend driver

Backend driver for MUSB OTG controllers found on TI OMAP2/3/4
(tested only on OMAP3 Beagle).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agoam3517_evm: switch to musb-new
Ilya Yanok [Tue, 6 Nov 2012 13:48:28 +0000 (13:48 +0000)]
am3517_evm: switch to musb-new

Use new musb framework instead of the old one on AM3517_EVM.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agoOMAP3: am35x: add musb functions
Ilya Yanok [Tue, 6 Nov 2012 13:48:27 +0000 (13:48 +0000)]
OMAP3: am35x: add musb functions

AM35XX specific functions for integrated USB PHY/MUSB IP.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agoOMAP3: am35x_def.h: add USB defines
Ilya Yanok [Tue, 6 Nov 2012 13:48:26 +0000 (13:48 +0000)]
OMAP3: am35x_def.h: add USB defines

Add defines for MUSB IP block on AM35X SoCs.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agomusb-new: am35x backend driver
Ilya Yanok [Tue, 6 Nov 2012 13:48:25 +0000 (13:48 +0000)]
musb-new: am35x backend driver

Backend driver for MUSB OTG controllers found on TI AM35x.

It seems that on AM35X interrupt status registers can be updated
_before_ core registers. As we don't use true interrupts in U-Boot
and poll interrupt status registers instead this can result in
interrupt handler being called with non-updated core registers.
This confuses the code and result in hanged transfers.
Add a small delay in am35x_interrupt as a workaround.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agoam335x_evm: enable both musb gadget and host
Ilya Yanok [Tue, 6 Nov 2012 13:48:24 +0000 (13:48 +0000)]
am335x_evm: enable both musb gadget and host

Enable musb gadget in Ethernet mode on port 0 and
musb host on port1.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agoam33xx: init OTG hardware and new musb gadget driver
Ilya Yanok [Tue, 6 Nov 2012 13:48:23 +0000 (13:48 +0000)]
am33xx: init OTG hardware and new musb gadget driver

AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agomusb-new: dsps backend driver
Ilya Yanok [Tue, 6 Nov 2012 13:48:22 +0000 (13:48 +0000)]
musb-new: dsps backend driver

Backend driver for MUSB OTG controllers found on TI AM33xx and
TI81xx SoCs (tested with AM33xx only).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agomusb-new: port of Linux musb driver
Ilya Yanok [Tue, 6 Nov 2012 13:48:21 +0000 (13:48 +0000)]
musb-new: port of Linux musb driver

Existing U-Boot musb driver has no support for the new gadget framework
and also seems to have other limitations. As gadget framework is ported
from Linux it seems pretty natural to port musb gadget driver as well.

This driver supports both host and peripheral modes.

This is not a replacement for current musb driver (at least now) as
there are still some consumers of the old UDC interface.

No DMA operation support included, CONFIG_MUSB_PIO_ONLY should be

Virtual root hub device is not implemented.

Known problems: with no devices connected usb_lowlevel_start() fails.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agousb: use linux/usb/ch9.h instead of usbdescriptors.h
Ilya Yanok [Tue, 6 Nov 2012 13:48:20 +0000 (13:48 +0000)]
usb: use linux/usb/ch9.h instead of usbdescriptors.h

Linux usb/ch9.h seems to have all the same information (and more)
as usbdescriptors.h so use the former instead of the later one.

As a consequense of this change USB_SPEED_* values don't correspond
directly to EHCI speed encoding anymore, I've added necessary
recoding in EHCI driver. Also there is no point to put speed into
pipe anymore so it's removed and a bunch of host drivers fixed to
look at usb_device->speed instead.

Old usbdescriptors.h included is not removed as it seems to be
used by old USB device code.

This makes usb.h and usbdevice.h incompatible. Fortunately the
only place that tries to include both are the old MUSB code and
it needs usb.h only for USB_DMA_MINALIGN used in aligned attribute
on musb_regs structure but this attribute seems to be unneeded
(old MUSB code doesn't support any DMA at all).

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agolinux/usb/ch9.h: update with the version from Linux tree
Ilya Yanok [Tue, 6 Nov 2012 13:48:19 +0000 (13:48 +0000)]
linux/usb/ch9.h: update with the version from Linux tree

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
9 years agoUSB: add arrow key support to usb_kbd
Allen Martin [Tue, 6 Nov 2012 21:26:03 +0000 (13:26 -0800)]
USB: add arrow key support to usb_kbd

Check for scancodes for arrow keys and map them to ^F/^B, ^N/^P.
Control characters are used instead of ANSI sequence because the
queueing code in usb_kbd doesn't handle the data increase when one
keypress generates 3 keycodes.  The real fix is to convert this driver
to use the input subsystem and queue, but this allows arrow keys to
work until this driver is converted.

Signed-off-by: Allen Martin <amartin@nvidia.com>
9 years agotegra: Enable USB keyboard
Allen Martin [Wed, 24 Oct 2012 08:32:06 +0000 (08:32 +0000)]
tegra: Enable USB keyboard

Enable USB keyboard for seaboard and ventana

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
9 years agotegra: move TEGRA_DEVICE_SETTINGS to tegra-common-post.h
Allen Martin [Wed, 24 Oct 2012 08:32:05 +0000 (08:32 +0000)]
tegra: move TEGRA_DEVICE_SETTINGS to tegra-common-post.h

Move environment settings for stdin/stdout/stderr to
tegra-common-post.h and generate them automaticaly based on input
device selection.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
9 years agoUSB: make usb_kbd obey USB DMA alignment requirements
Allen Martin [Wed, 24 Oct 2012 08:32:04 +0000 (08:32 +0000)]
USB: make usb_kbd obey USB DMA alignment requirements

Change usb_kbd driver to obey alignment requirements for USB DMA on
the buffer used for data transfer.  This is necessary for
architectures that enable dcache and enable USB DMA.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
9 years agoboards: remove the no longer used CONFIG_EHCI_DCACHE
Jeroen Hofstee [Mon, 22 Oct 2012 20:35:46 +0000 (22:35 +0200)]
boards: remove the no longer used CONFIG_EHCI_DCACHE

CONFIG_EHCI_DCACHE was removed by commit b8adb12
"USB: Drop cache flush bloat in EHCI-HCD". Remove the defines from
the boards configs as well.

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
cc: Marek Vasut <marex@denx.de>
cc: Stefan Roese <sr@denx.de>
cc: Tom Rini <trini@ti.com>
cc: Wolfgang Denk <wd@denx.de>
cc: Thierry Reding <thierry.reding@avionic-design.de>
cc: Tom Warren <twarren@nvidia.com>
cc: Stephen Warren <swarren@nvidia.com>
cc: Stefano Babic <sbabic@denx.de>

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-video
Tom Rini [Mon, 19 Nov 2012 16:28:04 +0000 (09:28 -0700)]
Merge branch 'master' of git://git.denx.de/u-boot-video