karo-tx-uboot.git
9 years agoboard/freescale/common: IDT8T49N222A configuration code
Shaveta Leekha [Tue, 2 Jul 2013 09:05:47 +0000 (14:35 +0530)]
board/freescale/common: IDT8T49N222A configuration code

Add code for configuring IDT8T49N222A device for various output refclks
    - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with
      alarm and monitoring functions suitable for networking and
      communications applications. It is able to generate wide range of output
      frequencies.
    - In B4860QDS, it has been used to generate different refclks to SerDes modules
    - Programming of these devices are performed by I2C interface.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
9 years agoboard/bsc9132qds: Configure DSP DDR controller
Priyanka Jain [Tue, 2 Jul 2013 03:52:23 +0000 (09:22 +0530)]
board/bsc9132qds: Configure DSP DDR controller

BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side
DDR. They are mapped to PowerPC and DSP CCSR space respectively.
BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC
and other to DSP side controller.

Configure DSP DDR controller similar to PowerPC side DDR controller as
memories are exactly similar.

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
9 years agoboard/bsc9132qds: Add DSP side tlb and laws
Priyanka Jain [Tue, 2 Jul 2013 03:51:04 +0000 (09:21 +0530)]
board/bsc9132qds: Add DSP side tlb and laws

BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.

To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores

Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE
Liu Gang [Fri, 28 Jun 2013 09:58:37 +0000 (17:58 +0800)]
powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIE

When a board (slave) boots from SRIO/PCIE, it would get the instructions
from a remote board (master) by SRIO/PCIE interface, and the slave's
u-boot image should be built with the

SYS_TEXT_BASE=0xFFF80000;

So the u-boot of the slave should avoid the NOR_BOOT branch at the
booting stage.

For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB
entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000",
and with the 4M size as the boot window in NOR_BOOT branch. Because
the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so
the TLB entry will be from base address 0xffc00000 and with 4M size.

Then the u-boot will set TLB entry 14 from base address
"CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial
stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR
= 0xffd00000. So the TLB entry 14 and 15 will be in confliction.

There will be right TLB entries configurations when avoid the
NOR_BOOT branch and set the boot window from 0xfff00000 with 1M
size space.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
9 years agop1020rdb-pd: platform support
Haijun.Zhang [Fri, 28 Jun 2013 02:47:09 +0000 (10:47 +0800)]
p1020rdb-pd: platform support

Add new board p1020RDB-PD. P1020RDB-PD board was update from P1020RDB.
DDR changed from DDR2 1G to DDR3 2G.
NAND: 128 MiB
Flash: 64 MiB

Also change P1020RDB to P1020RDB-PC to distinguish from P1020RDB board.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: Workaround for A-005812
York Sun [Tue, 25 Jun 2013 18:37:49 +0000 (11:37 -0700)]
powerpc/mpc85xx: Workaround for A-005812

Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can
result in invalid atomic operations. For u-boot, this erratum only impacts
SoCs running in write shadow mode.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc8xxx: Add memory reset control
York Sun [Tue, 25 Jun 2013 18:37:48 +0000 (11:37 -0700)]
powerpc/mpc8xxx: Add memory reset control

JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc8xxx: Add x4 DDR device support
York Sun [Tue, 25 Jun 2013 18:37:47 +0000 (11:37 -0700)]
powerpc/mpc8xxx: Add x4 DDR device support

On selected platforms, x4 DDR devices can be supported. Using x4 devices may
lower the performance, but generally they are available for higher density.

Tested on MT36JSF2G72PZ-1G9E1 RDIMM.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4240qds: Adjust DDR timing for RDIMM
York Sun [Tue, 25 Jun 2013 18:37:46 +0000 (11:37 -0700)]
powerpc/t4240qds: Adjust DDR timing for RDIMM

RDIMM has different timing. Tested RDIMM is MT18JSF1G72PDZ-1G9E1 for
dual rank. Single- and quad-rank are not tested due to availability.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff
York Sun [Tue, 25 Jun 2013 18:37:45 +0000 (11:37 -0700)]
powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff

When chip select interleaving is enabled, cs0_bnds is used for address
binding. Other csn_bnds are not used. When two controllers interleaving is
enabled, cs0_bnds of both controllers are used, other csn_bnds are not.
However, the unused csn_bnds may be used internally for calculating
addresses for calibration. Setting those registers to 0 may confuse
controllers in some cases. Instead, setting them to 0xffffffff together
with normal LAWs will guarantee the address is not mapped to DDR.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/T4240EMU: Add T4240EMU target
York Sun [Thu, 27 Jun 2013 17:48:29 +0000 (10:48 -0700)]
powerpc/T4240EMU: Add T4240EMU target

Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
ECC for DDR is disabled due the procedure to load images
No board FPGA (QIXIS)
NOR flash has 32-bit port for higher loading speed
IFC and I2C timing don't really matter, so set them fast
No ethernet

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/corenet: Move RCW print to cpu.c
York Sun [Tue, 25 Jun 2013 18:37:43 +0000 (11:37 -0700)]
powerpc/corenet: Move RCW print to cpu.c

The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4qds: cleanup board header file
York Sun [Tue, 25 Jun 2013 18:37:42 +0000 (11:37 -0700)]
powerpc/t4qds: cleanup board header file

CONFIG_PHYS_64BIT is always defined for t4qds. Removed unused #ifdef.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agompc85xx: Base emulator support
York Sun [Tue, 25 Jun 2013 18:37:41 +0000 (11:37 -0700)]
mpc85xx: Base emulator support

Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agodrivers/fm: Fix compiling error if FW location is not defined
York Sun [Tue, 25 Jun 2013 18:37:40 +0000 (11:37 -0700)]
drivers/fm: Fix compiling error if FW location is not defined

FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even
remote. In case none of them is defined, set it to null.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/corenet: Move CONFIG_FSL_CORENET out of board header file
York Sun [Tue, 25 Jun 2013 18:37:39 +0000 (11:37 -0700)]
powerpc/corenet: Move CONFIG_FSL_CORENET out of board header file

Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board
specific feature and belongs to SoC header.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4: Correct LIODN assignment for SRIO
Liu Gang [Tue, 25 Jun 2013 10:12:14 +0000 (18:12 +0800)]
powerpc/t4: Correct LIODN assignment for SRIO

For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
9 years agopowerpc/b4860: Correct LIODN assignment for SRIO
Liu Gang [Tue, 25 Jun 2013 10:12:13 +0000 (18:12 +0800)]
powerpc/b4860: Correct LIODN assignment for SRIO

For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
9 years agopowerpc/srio: Update the SRIO LIODN registers and ID table macro
Liu Gang [Tue, 25 Jun 2013 10:12:12 +0000 (18:12 +0800)]
powerpc/srio: Update the SRIO LIODN registers and ID table macro

For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/85xx: Add TWR-P10xx board support
Xie Xiaobo [Mon, 24 Jun 2013 07:01:30 +0000 (15:01 +0800)]
powerpc/85xx: Add TWR-P10xx board support

TWR-P1025 Specification:
-----------------------
Memory subsystem:
   512MB DDR3 (on board DDR)
   64Mbyte 16bit NOR flash
   One microSD Card slot

Ethernet:
   eTSEC1: Connected to Atheros AR8035 GETH PHY
   eTSEC3: Connected to Atheros AR8035 GETH PHY

UART:
   Two UARTs are routed to the FDTI dual USB to RS232 convertor

USB: Two USB2.0 Type A ports

I2C:
   AT24C01B 1K Board EEPROM (8 bit address)

QUICC Engine:
   Connected to DP83849i PHY supply two 10/100M ethernet ports
   QE UART for RS485 or RS232

PCIE:
   One mini-PCIE slot

Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
[yorksun: Fixup include/configs/p1_twr.h]
Signed-off-by: York Sun <yorksun@freescale.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-i2c
Tom Rini [Tue, 6 Aug 2013 13:49:06 +0000 (09:49 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c

9 years agoi2c: soft: Fix typo in CONFIG_SYS_I2C_SOFT_SPEED
Marek Vasut [Thu, 1 Aug 2013 10:32:20 +0000 (12:32 +0200)]
i2c: soft: Fix typo in CONFIG_SYS_I2C_SOFT_SPEED

In case only the CONFIG_SYS_I2C_SPEED is set in configuration file,
the CONFIG_SYS_I2C_SOFT_SPEED is defined as CONFIG_SYS_I2C_SPEED.
The CONFIG_SYS_I2C_SOFT_SPEED is then used throughout the driver.

Unfortunatelly, due to a typo in the driver, instead of defining
CONFIG_SYS_I2C_SOFT_SPEED, an CONFIG_SYS_SOFT_I2C_SPEED was defined
and therefore the driver failed to compile. The same applies for
CONFIG_SYS_I2C_SOFT_SLAVE , where the swap happens as well.

This patch fixes the issue.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
9 years agodts/Makefile: pass -undef -D__DTS__ to cpp
Stephen Warren [Wed, 24 Jul 2013 17:09:24 +0000 (10:09 -0700)]
dts/Makefile: pass -undef -D__DTS__ to cpp

This brings U-Boot's cpp invocation into line with the way the Linux
kernel invokes cpp on device trees. Consistency will be useful to ensure
*.dts is portable between the two.

-undef also has the added advantage of not defining "linux", so DT
property names such as "linux,keymap" don't get mangled.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodts/Makefile: don't use cpp -P
Stephen Warren [Wed, 24 Jul 2013 17:09:23 +0000 (10:09 -0700)]
dts/Makefile: don't use cpp -P

Recent dtc supports #line directives in the input source code, and even
uses them to generate useful line numbers in any messages it emits. Stop
passing -P to cpp, since there's no need any more.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoconfig: don't define CONFIG_ARCH_DEVICE_TREE
Stephen Warren [Wed, 24 Jul 2013 17:09:22 +0000 (10:09 -0700)]
config: don't define CONFIG_ARCH_DEVICE_TREE

Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodts/Makefile: don't define ARCH_CPU_DTS, BOARD_DTS
Stephen Warren [Wed, 24 Jul 2013 17:09:21 +0000 (10:09 -0700)]
dts/Makefile: don't define ARCH_CPU_DTS, BOARD_DTS

Now that nothing uses the defines ARCH_CPU_DTS, BOARD_DTS, stop defining
them.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodt: don't use ARCH_CPU_DTS
Stephen Warren [Wed, 24 Jul 2013 17:09:20 +0000 (10:09 -0700)]
dt: don't use ARCH_CPU_DTS

Now that we assume dtc supports the -i option, we don't need to use
ARCH_CPU_DTS in *.dts{,i}; we simply specify the include filename
directly, and dtc will find it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodts/Makefile: unify cpp/dtc include paths
Stephen Warren [Wed, 24 Jul 2013 17:09:19 +0000 (10:09 -0700)]
dts/Makefile: unify cpp/dtc include paths

*.dts may use #include (via cpp) or /include/ (via dtc; assuming a newer
dtc). The choice is up to the creator of the DT. Create a common variable
DTC_INCDIRS that lists the paths searched by include statements, and
update cpp and dtc invocation to use them.

For cpp, also specify -nostdinc to ensure the same set of paths is
available to both type of include statement.

For dtc, create a new DTC_FLAGS variable to hold all the flags passed to
dtc.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agodts/Makefile: simplify dtc invocation
Stephen Warren [Wed, 24 Jul 2013 17:09:18 +0000 (10:09 -0700)]
dts/Makefile: simplify dtc invocation

The invocation of dtc is significantly more complex that it could be,
in order to work around an issue on old versions of dtc, which print
a message to stdout every time they run.

Remove this workaround, on the assumption that people have or will
upgrade to a newer version of dtc. This simplifies the build rule
significantly.

Related, split the invocation of cpp and dtc into separate commands
rather than a pipeline, so that if either fail, it is detected. This has
the nice benefit of saving off the result of the pre-processing step,
allowing it to be easily inspected.

Assuming a new enough dtc (which an earlier patch enforces), dtc will
parse #line directives in its input file, and generate correct file and
line numbers in error messages, even though cpp is unconditionally
applied to its input file.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoxilinx: move microblaze-generic .dts to standard location
Stephen Warren [Wed, 24 Jul 2013 17:09:17 +0000 (10:09 -0700)]
xilinx: move microblaze-generic .dts to standard location

Aside from microblaze, all other SoCs/boards/vendors store their DT files
in board/$vendor/dts/$soc-$board.dts. Move microblaze-generic.dts to this
location for consistency.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <monstr@monstr.eu>
9 years agoValidate dtc is new enough
Stephen Warren [Wed, 24 Jul 2013 17:09:16 +0000 (10:09 -0700)]
Validate dtc is new enough

Subsequent patches assume that dtc supports various recent features.
These are available in dtc 1.4.0. Validate that dtc is at least that
version.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Thu, 1 Aug 2013 13:19:28 +0000 (09:19 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

9 years agospi: bfin_spi: Use DIV_ROUND_UP instead of open-coded
Axel Lin [Fri, 12 Jul 2013 09:39:41 +0000 (17:39 +0800)]
spi: bfin_spi: Use DIV_ROUND_UP instead of open-coded

Use DIV_ROUND_UP to simplify the code.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
9 years agoblackfin: Fix using gd->baudrate before setting its value
Axel Lin [Mon, 1 Jul 2013 05:16:17 +0000 (13:16 +0800)]
blackfin: Fix using gd->baudrate before setting its value

Current code uses gd->baudrate before setting its value.
Besides, I got below build warning which is introduced by
commit ddb5c5be "blackfin: add baudrate to bdinfo".

board.c:235:3: warning: passing argument 1 of 'simple_strtoul' makes pointer from integer without a cast [enabled by default]
include/vsprintf.h:27:7: note: expected 'const char *' but argument is of type 'unsigned int'

This patch ensures we get the baudrate setting before using it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
9 years agoblackfin: gpio: Use proper mask for comparing function
Axel Lin [Fri, 28 Jun 2013 06:45:06 +0000 (14:45 +0800)]
blackfin: gpio: Use proper mask for comparing function

The function return from P_FUNCT2MUX(per) takes 2 bits, however
for BF537_FAMILY with offset != 1 the function is 1 bit.

Also has small refactor for better readability.
In portmux_setup(), it looks odd having "muxreg &= ~(3 << 1);"
while in current code we do muxreg |= (function << offset);.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
9 years agogpio: adi_gpio2: Unreserve gpio in special_gpio_free()
Axel Lin [Wed, 26 Jun 2013 02:10:04 +0000 (10:10 +0800)]
gpio: adi_gpio2: Unreserve gpio in special_gpio_free()

In special_gpio_free(), call unreserve() rather than reserve() to release gpio.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
9 years agoblackfin: gpio: Unreserve gpio in special_gpio_free()
Axel Lin [Wed, 26 Jun 2013 02:09:16 +0000 (10:09 +0800)]
blackfin: gpio: Unreserve gpio in special_gpio_free()

In special_gpio_free(), call unreserve() rather than reserve() to release gpio.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
9 years agocfi_flash: Add prototypes of overridable functions
Masahiro Yamada [Thu, 6 Jun 2013 07:54:04 +0000 (16:54 +0900)]
cfi_flash: Add prototypes of overridable functions

This commit adds some prototypes into include/mtd/cfi_flash.h.
These functions are defined with a weak attribute in
drivers/mtd/cfi_flash.c.
This means they can be overrided by board-specific ones
if necessary.

When defining such functions under board/ directory or
somewhere, cfi_flash.h should be included.
This makes sure that board-specfic cfi functions
are defined in a correct prototype.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agoehci-hcd: fix memory leak in lowlevel init
Nikita Kiryanov [Mon, 29 Jul 2013 10:27:40 +0000 (13:27 +0300)]
ehci-hcd: fix memory leak in lowlevel init

usb_lowlevel_init() allocates a new periodic_list each time it is invoked,
without freeing the original list. Since it is initialized later on in the code,
just reuse the first-allocated list in future invocations of usb_lowlevel_init.

Cc: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agousb_hub: fix power cycling logic
Nikita Kiryanov [Mon, 29 Jul 2013 10:27:39 +0000 (13:27 +0300)]
usb_hub: fix power cycling logic

When power cycling the hub ports, a misbehaving port will prevent all ports
from being powered on because we quit at the first sign of trouble.

Skip problematic ports instead of failing the entire power on.

Cc: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
9 years agousb: ehci-omap: Don't softreset USB High-speed Host (UHH) Module
Roger Quadros [Mon, 22 Jul 2013 08:14:37 +0000 (11:14 +0300)]
usb: ehci-omap: Don't softreset USB High-speed Host (UHH) Module

Fixes NFS root problems with Beagle (3530 ES1.0) when used with
external USB-ethernet adapter and "USB start" command used within
u-boot.

Soft resetting the UHH module causes instability issues on
all OMAPs so we just avoid it.

See OMAP36xx Errata
  i571: USB host EHCI may stall when entering smart-standby mode
  i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock

On OMAP4/5, soft-resetting the UHH module can put it into
Smart-Idle mode and lead to a deadlock.

On OMAP3 this doesn't seem to be the case but still instabilities
are observed on beagle (3530 ES1.0) if soft-reset is used.
 e.g. NFS root failures with Linux kernel.

Signed-off-by: Roger Quadros <rogerq@ti.com>
9 years agodfu: Implementation of target reset after communication with dfu-util's -R switch
Lukasz Majewski [Thu, 18 Jul 2013 11:19:14 +0000 (13:19 +0200)]
dfu: Implementation of target reset after communication with dfu-util's -R switch

This patch extends dfu code to support transmission with -R switch
specified at dfu-util.

When -R is specified, the extra USB_REQ_DFU_DETACH request is sent after
successful data transmission. Then dfu resources are released and reset
command is issued.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
9 years agousb: mv_udc: Add bounce buffer
Marek Vasut [Wed, 10 Jul 2013 01:16:43 +0000 (03:16 +0200)]
usb: mv_udc: Add bounce buffer

The requests sent to the controller are not properly cache aligned
most of the time, thus implement a simple bounce buffer to avoid
problem with cache.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Add proper cache management
Marek Vasut [Wed, 10 Jul 2013 01:16:42 +0000 (03:16 +0200)]
usb: mv_udc: Add proper cache management

Implement functions to flush/invalidate dcache over QH and qTDs
and make use of them where appropriate. Also use them to replace
the old incorrect cache management attempt. This is the first step
towards making this driver work with data cache enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Implement better qTD item accessor
Marek Vasut [Wed, 10 Jul 2013 01:16:41 +0000 (03:16 +0200)]
usb: mv_udc: Implement better qTD item accessor

The code for retrieving qTD item for particular endpoint is hard
to understand, moreover it's duplicated all over the driver. Move
the code into single nice and documented function.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Improve allocation of qTD items
Marek Vasut [Wed, 10 Jul 2013 01:16:40 +0000 (03:16 +0200)]
usb: mv_udc: Improve allocation of qTD items

Allocate the qTD items all at once instead of allocating them
separately. Moreover, make sure each qTD is properly aligned
to 32-bytes boundary and that cache can be safely flushed over
each qTD touple.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Implement better QH accessor
Marek Vasut [Wed, 10 Jul 2013 01:16:39 +0000 (03:16 +0200)]
usb: mv_udc: Implement better QH accessor

The code for retrieving QH for particular endpoint is hard to understand,
moreover it's duplicated all over the driver. Move the code into single
nice and documented function.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Add cacheline length check
Marek Vasut [Wed, 10 Jul 2013 01:16:38 +0000 (03:16 +0200)]
usb: mv_udc: Add cacheline length check

Check the length of system cacheline at compile-time and fail
if the system uses too long cachelines.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Properly align the endpoint QH and qTD list
Marek Vasut [Wed, 10 Jul 2013 01:16:37 +0000 (03:16 +0200)]
usb: mv_udc: Properly align the endpoint QH and qTD list

The endpoint QH list has to be aligned to 10-bit boundary. We also have
to make sure the list is aligned on a cacheline boundary. Make sure it
is. Furthermore, check if the memory allocation for the QH list didn't
fail. Moveover, improve the comment about the QH list structure.

Finally, the qTD item list has to be aligned only to 5-bit boundary, not
10-bit as it is now, fix this as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Move QH and qTD into mv_drv
Marek Vasut [Wed, 10 Jul 2013 01:16:36 +0000 (03:16 +0200)]
usb: mv_udc: Move QH and qTD into mv_drv

Both the endpoint queue head and the endpoint item list is a controller
specific thing. Move them both into controller private data.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Init mv_drv.gadget.ops statically
Marek Vasut [Wed, 10 Jul 2013 01:16:35 +0000 (03:16 +0200)]
usb: mv_udc: Init mv_drv.gadget.ops statically

There is no need to init this field at runtime, so init it statically.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Remove QH_MAXNUM macro
Marek Vasut [Wed, 10 Jul 2013 01:16:34 +0000 (03:16 +0200)]
usb: mv_udc: Remove QH_MAXNUM macro

The QH_MAXNUM is used in absolutelly incorrect manner and is not
even needed. Remove it and correctly replace it's occurance with
2 * NUM_ENDPOINTS .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Clean up the initial variable check
Marek Vasut [Wed, 10 Jul 2013 01:16:33 +0000 (03:16 +0200)]
usb: mv_udc: Clean up the initial variable check

Clean up the code that checks the validity of a USB gadget driver
in usb_gadget_register_driver(). Moreover, limit the speed of the
driver to either FULL or HIGH, this is more precise and once we
have xHCI support, also more correct.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Make use of struct ehci_ctrl
Marek Vasut [Wed, 10 Jul 2013 01:16:32 +0000 (03:16 +0200)]
usb: mv_udc: Make use of struct ehci_ctrl

The usb_lowlevel_init() call already fills and passes back struct
ehci_ctrl , which readily contains correctly determined address of
the port register block address computed from values from controller
configuration registers. Leverage this and make use of this value
as this makes the code mode universal, but also gets us rid of the
CONFIG_USB_REG_BASE configuration option.

Moreover, this patch cleans up the usb_gadget_register_driver() call
a little by correcting the error handling. Note the usb_lowlevel_init()
and mvudc_probe() are now called in reversed order, but this has no
impact on the code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: ehci: Split out struct ehci_ctrl definition
Marek Vasut [Wed, 10 Jul 2013 01:16:31 +0000 (03:16 +0200)]
usb: ehci: Split out struct ehci_ctrl definition

Move the struct ehci_ctrl defition from ehci-hcd.c into ehci.h
so it can be re-used by drivers. In particular, the mv_udc driver
can benefit from this move.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Clean up the EP initialization
Marek Vasut [Wed, 10 Jul 2013 01:16:30 +0000 (03:16 +0200)]
usb: mv_udc: Clean up the EP initialization

Move the constant values that are programmed into mv_ep.ep into
separate static const structure so they can be memcpy()'d when
the initialization happens.

Moveover, we only every init NUM_ENDPOINTS, not 2 * NUM_ENDPOINTS,
so fix this bug as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Move endpoint array into driver data
Marek Vasut [Wed, 10 Jul 2013 01:16:29 +0000 (03:16 +0200)]
usb: mv_udc: Move endpoint array into driver data

The endpoints are operated on a per-controller basis, move the
endpoint array into controller's private data. Also shuffle the
struct mv_ep structure definition just above the definition of
the struct mv_drv so they're well grouped together.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Clean up mv_udc.h
Marek Vasut [Wed, 10 Jul 2013 01:16:28 +0000 (03:16 +0200)]
usb: mv_udc: Clean up mv_udc.h

Do a coding-style cleanup of this file and throw away useless
defined values. These values were likely a result of a copy-paste
job.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agousb: mv_udc: Unbreak the mv_udc driver
Marek Vasut [Wed, 10 Jul 2013 01:16:27 +0000 (03:16 +0200)]
usb: mv_udc: Unbreak the mv_udc driver

The mv_udc driver is broken for a while and doesn't even compile.
This patch fixes the issues and gets the driver into working state
again. This driver was tested on Freescale i.MX233/i.MX28 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
9 years agopowerpc/ppc4xx: Convert new gdsys files to SPDX license tags
Tom Rini [Fri, 26 Jul 2013 19:32:59 +0000 (15:32 -0400)]
powerpc/ppc4xx: Convert new gdsys files to SPDX license tags

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
Tom Rini [Fri, 26 Jul 2013 19:29:45 +0000 (15:29 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-ppc4xx

9 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash
Tom Rini [Fri, 26 Jul 2013 19:29:08 +0000 (15:29 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-cfi-flash

9 years agopowerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards
Dirk Eibach [Wed, 26 Jun 2013 14:04:31 +0000 (16:04 +0200)]
powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards

CONFIG_SYS_FLASH_PROTECTION was active on most gdsys boards by default,
while hardware flash protection was not implemented.
Hardware support was added recently and we get into trouble because backward
compatibility is broken (u-boot can't unprotect the protected flash after a
downgrade). So we decided to disable hardware flash protection for all our boards.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agopowerpc/ppc4xx: Consider gdsys FPGA OSD size
Dirk Eibach [Wed, 26 Jun 2013 14:04:30 +0000 (16:04 +0200)]
powerpc/ppc4xx: Consider gdsys FPGA OSD size

OSD size was constant 32x16 characters.
Now the size is set as announced by the FPGA.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agopowerpc/ppc4xx: Support gdsys multichannel iocon hardware
Dirk Eibach [Thu, 25 Jul 2013 17:28:13 +0000 (19:28 +0200)]
powerpc/ppc4xx: Support gdsys multichannel iocon hardware

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agopowerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers
Dirk Eibach [Wed, 26 Jun 2013 14:04:28 +0000 (16:04 +0200)]
powerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agopowerpc/ppc4xx: Add gdsys mclink interface
Dirk Eibach [Wed, 26 Jun 2013 14:04:27 +0000 (16:04 +0200)]
powerpc/ppc4xx: Add gdsys mclink interface

mclink is a serial interface for communication between gdsys FPGA.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agopowerpc/ppc4xx: Use generic accessor functions for gdsys FPGA
Dirk Eibach [Wed, 26 Jun 2013 14:04:26 +0000 (16:04 +0200)]
powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA

A set of accessor functions was added to be able to access not only
memory mapped FPGA in a generic way.

Thanks to Wolfgang Denk for getting this sorted properly.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agocfi_flash: use buffer length in unmap_physmem()
Kuo-Jung Su [Thu, 4 Jul 2013 03:40:36 +0000 (11:40 +0800)]
cfi_flash: use buffer length in unmap_physmem()

While the flash_detect_legacy() of drivers/mtd/cfi_flash.c
feed unmap_physmem() with MAP_NOCACHE as 2nd parameter,
the do_spi_flash_read_write() of common/cmd_sf.c
feed unmap_physmem() with the length of the mapped buffer
as 2nd parameter.

It's apparently a bug, and I personally think the 2nd parameter
should be the length of the mapped buffer.

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
CC: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-nds32
Tom Rini [Thu, 25 Jul 2013 12:22:08 +0000 (08:22 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-nds32

9 years agoqemu-malta: Update for SPDX license identifiers
Tom Rini [Wed, 24 Jul 2013 13:34:30 +0000 (09:34 -0400)]
qemu-malta: Update for SPDX license identifiers

Signed-off-by: Tom Rini <trini@ti.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mips
Tom Rini [Wed, 24 Jul 2013 13:30:46 +0000 (09:30 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-mips

Conflict over SPDX changes means that one change was effectively dropped
as it was fixing typos in a removed hunk of text.

Conflicts:
arch/mips/cpu/mips64/start.S

Signed-off-by: Tom Rini <trini@ti.com>
9 years agodrivers/i2c: Update fti2c010.[ch], i2c_core.c to use SPDX identifiers
Tom Rini [Wed, 24 Jul 2013 13:25:40 +0000 (09:25 -0400)]
drivers/i2c: Update fti2c010.[ch], i2c_core.c to use SPDX identifiers

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
9 years agonds32: Enable FPU if the version of CPU supported
ken kuo [Wed, 24 Jul 2013 18:17:11 +0000 (02:17 +0800)]
nds32: Enable FPU if the version of CPU supported

Some version of Andes core support FPU coprocessor,
if this is the case, and toolchain support FPU instruction set,
we should enable it at low level initialization time.

Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
9 years agonds32: Update <asm/io.h> and <asm/setup.h> with SPDX license identifiers
Tom Rini [Wed, 24 Jul 2013 13:39:00 +0000 (09:39 -0400)]
nds32: Update <asm/io.h> and <asm/setup.h> with SPDX license identifiers

Signed-off-by: Tom Rini <trini@ti.com>
9 years agonds32: Convert Makefiles to use COBJS-y style
ken kuo [Wed, 24 Jul 2013 18:24:54 +0000 (02:24 +0800)]
nds32: Convert Makefiles to use COBJS-y style

Signed-off-by: Kuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>
9 years agoMIPS: mips32/cache.S: use v1 register for indirect function calls
Gabor Juhos [Thu, 13 Jun 2013 10:59:36 +0000 (12:59 +0200)]
MIPS: mips32/cache.S: use v1 register for indirect function calls

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips32/cache.S: store cache line size in t8 register
Gabor Juhos [Thu, 13 Jun 2013 10:59:35 +0000 (12:59 +0200)]
MIPS: mips32/cache.S: store cache line size in t8 register

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips32/cache.S: save return address in t9 register
Gabor Juhos [Thu, 13 Jun 2013 10:59:34 +0000 (12:59 +0200)]
MIPS: mips32/cache.S: save return address in t9 register

Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: xburst/start.S: rework relocation info check
Gabor Juhos [Fri, 14 Jun 2013 12:47:10 +0000 (14:47 +0200)]
MIPS: xburst/start.S: rework relocation info check

Make it similar to the code in mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: xburst/start.S: use t8 register for dynamic relocation
Gabor Juhos [Thu, 13 Jun 2013 10:59:32 +0000 (12:59 +0200)]
MIPS: xburst/start.S: use t8 register for dynamic relocation

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: xburst/start.S: save gd in s0 register
Gabor Juhos [Thu, 13 Jun 2013 10:59:31 +0000 (12:59 +0200)]
MIPS: xburst/start.S: save gd in s0 register

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: xburst/start.S: save relocation offset in s1 register
Gabor Juhos [Thu, 13 Jun 2013 10:59:30 +0000 (12:59 +0200)]
MIPS: xburst/start.S: save relocation offset in s1 register

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: xburst/start.S: save relocation address in s2 register
Gabor Juhos [Thu, 13 Jun 2013 10:59:29 +0000 (12:59 +0200)]
MIPS: xburst/start.S: save relocation address in s2 register

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips32/start.S: rework relocation info check
Gabor Juhos [Thu, 13 Jun 2013 10:59:28 +0000 (12:59 +0200)]
MIPS: mips32/start.S: rework relocation info check

Make it similar to the code in mips64/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips32/start.S: use t8 register for dynamic relocation
Gabor Juhos [Thu, 13 Jun 2013 10:59:27 +0000 (12:59 +0200)]
MIPS: mips32/start.S: use t8 register for dynamic relocation

Synchronize the code with mips64/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips32/cache.S: remove superfluous register assignment
Gabor Juhos [Wed, 12 Jun 2013 16:02:46 +0000 (18:02 +0200)]
MIPS: mips32/cache.S: remove superfluous register assignment

The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
9 years agoMIPS: remove obsolete TODO items
Gabor Juhos [Wed, 12 Jun 2013 16:02:45 +0000 (18:02 +0200)]
MIPS: remove obsolete TODO items

The MIPS  code uses centralized u-boot.lds script already,
and dynamic relocation is supported as well.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips64/interrupt.c: remove superfluous include
Gabor Juhos [Wed, 12 Jun 2013 16:02:44 +0000 (18:02 +0200)]
MIPS: mips64/interrupt.c: remove superfluous include

Nothing is used from asm/mipsregs.h.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips32/time.c: fix checkpatch errors/warnings
Gabor Juhos [Wed, 12 Jun 2013 16:02:43 +0000 (18:02 +0200)]
MIPS: mips32/time.c: fix checkpatch errors/warnings

Checking mips32/time.c with checkpatch.pl shows this:

  arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters
  arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required
  total: 1 errors, 1 warnings, 0 checks, 85 lines checked

Fix the code to make checkpatch.pl happy.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: qemu-malta: bring up ethernet
Gabor Juhos [Wed, 22 May 2013 03:57:44 +0000 (03:57 +0000)]
MIPS: qemu-malta: bring up ethernet

Qemu emulates a PCNET PCI card for the Malta CoreLV board.
Enable the pcnet driver and add board specific ethernet
initialization function to bring it up. Also enable the
CONFIG_CMD_NET and CONFIG_CMD_PING options.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: qemu-malta: add PCI support
Gabor Juhos [Wed, 22 May 2013 03:57:42 +0000 (03:57 +0000)]
MIPS: qemu-malta: add PCI support

Qemu emulates the Galileo GT64120 System Controller
which provides a CPU bus to PCI bus bridge.

The patch adds driver for this bridge and enables
PCI support for the emulated Malta board.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: qemu-malta: setup GT64120 registers as done by YAMON
Gabor Juhos [Wed, 22 May 2013 03:57:41 +0000 (03:57 +0000)]
MIPS: qemu-malta: setup GT64120 registers as done by YAMON

Move the GT64120 register base to 0x1be00000
and setup PCI BAR registers as done by the
original YAMON bootloader.

This is needed for running Linux kernel.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: qemu-malta: enable flash support
Gabor Juhos [Wed, 22 May 2013 03:57:39 +0000 (03:57 +0000)]
MIPS: qemu-malta: enable flash support

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: qemu-malta: add reset support
Gabor Juhos [Wed, 22 May 2013 03:57:38 +0000 (03:57 +0000)]
MIPS: qemu-malta: add reset support

The MIPS Malta board has a SOFTRES register. Writing a
magic value into that register initiates a board reset.

Use this feature to implement reset support.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: qemu-malta: add support for emulated MIPS Malta board
Gabor Juhos [Wed, 22 May 2013 03:57:37 +0000 (03:57 +0000)]
MIPS: qemu-malta: add support for emulated MIPS Malta board

Add minimal support for the MIPS Malta CoreLV board
emulated by Qemu. The only supported peripherial is
the UART.

This is enough to boot U-Boot to the command prompt
both in little and big endian mode.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: start.S: emulate REVISION register for qemu-malta
Gabor Juhos [Wed, 22 May 2013 03:57:46 +0000 (03:57 +0000)]
MIPS: start.S: emulate REVISION register for qemu-malta

On the origial Malta boards the REVISION register is
accessible at the 0x1fc00010 address. The contents of
this register gives information about the revision
of the Malta and Core Boards.

This register is used by the Linux kernel to identify
the actual board it is running on. However the register
is not emulated properly by Qemu, so put a hardcoded
value into the flash to make Linux work.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: import gt64120.h header from Linux
Gabor Juhos [Wed, 22 May 2013 03:57:40 +0000 (03:57 +0000)]
MIPS: import gt64120.h header from Linux

The Linux specific register access macros, the
extern function declarations and the UL suffixes
has been removed.

The header file will be used for the qemu-malta
board.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agonet: pcnet: use pci_virt_to_mem to obtain buffer addresses
Gabor Juhos [Wed, 22 May 2013 03:57:43 +0000 (03:57 +0000)]
net: pcnet: use pci_virt_to_mem to obtain buffer addresses

The pcnet driver uses the pci_phys_to_mem function
to get the memory address of the DMA buffers. This
This assumes an 1:1 mapping between the PCI and
physical memory which is not true on all platforms.

On MIPS platform U-Boot is running within a mapped
memory region, and the pci_phys_to_mem macro can't
be used to obtain the memory address of the buffers.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
9 years agoMIPS: mips64: fix typos in copyright text of start.S
Tom Rini [Wed, 24 Jul 2013 13:50:52 +0000 (09:50 -0400)]
MIPS: mips64: fix typos in copyright text of start.S

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Conflicts:

arch/mips/cpu/mips64/start.S

Signed-off-by: Tom Rini <trini@ti.com>